Semiconductor integrated circuit and data transfer method
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Filing Date
- 2026-02-12
- Publication Date
- 2026-06-02
Abstract
Description
Semiconductor integrated circuit and data transfer method
[0001] The present disclosure relates to a semiconductor integrated circuit and a data transfer method for scrambling data and transferring the scrambled data to a destination circuit.
[0002] 2. Description of the Related Art Conventionally, semiconductor integrated circuits for transferring data have been proposed (see, for example, Japanese Patent Application Laid-Open No. 2003-144998).
[0003] Patent No. 5606527
[0004] When transferring data, the signal quality of the transferred data may deteriorate depending on the data pattern.
[0005] Therefore, the present disclosure provides a semiconductor integrated circuit and the like that can suppress deterioration of data signal quality that may occur depending on the data pattern when transferring data.
[0006] The semiconductor integrated circuit according to the present disclosure is a semiconductor integrated circuit for scrambling data and transferring it to a destination circuit, and includes a scrambler that generates a scrambling key having a Hamming weight of B / 2 when B is an even number, and generates a scrambling key having a Hamming weight of (B+1) / 2 or (B-1) / 2 when B is an odd number, and scrambles the data using the scrambling key, and a transfer control unit that transfers the scrambled data, which is the scrambled data, to the destination circuit.
[0007] The data transfer method according to the present disclosure is a data transfer method executed by a semiconductor integrated circuit for scrambling data and transferring the scrambled data to a destination circuit, and includes the steps of: generating a scramble key having a Hamming weight of B / 2 when B is an even number, and generating a scramble key having a Hamming weight of (B+1) / 2 or (B-1) / 2 when B is an odd number, scrambling the data using the scramble key; and transferring the scrambled data, which is the scrambled data, to the destination circuit.
[0008] These comprehensive or specific aspects may be realized as a system, a method, an integrated circuit, a computer program, or a computer-readable recording medium such as a CD-ROM, or may be realized as any combination of a system, a method, an integrated circuit, a computer program, and a recording medium.
[0009] According to a semiconductor integrated circuit and the like according to an aspect of the present disclosure, it is possible to suppress deterioration of data signal quality that may occur depending on the data pattern when transferring data.
[0010] FIG. 1 is a diagram for explaining the number of simultaneous switches between 0x00 data and the data before and after it. FIG. 2 is a diagram for explaining the number of simultaneous switches between 0xFF data and the data before and after it. FIG. 3 is a block diagram showing an example of a semiconductor integrated circuit according to a first embodiment. FIG. 4 is a diagram for explaining the number of simultaneous switches between 0x00 data and the data before and after it after scrambling with a scramble key having a Hamming weight of 4. FIG. 5 is a block diagram showing an example of a semiconductor integrated circuit according to a second embodiment. FIG. 6 is a flowchart showing an example of a data transfer method according to another embodiment.
[0011] (How One Aspect of the Present Disclosure Was Achieved) Conventionally, it has been known that when transferring data, the signal quality of the transferred data deteriorates depending on the data pattern.
[0012] For example, when the data to be transferred is bus-format data consisting of multiple bits, simultaneous toggling of the multiple bits can cause noise such as simultaneous switching noise (SSN, also referred to as power supply noise) to be carried over to the transferred data. Here, simultaneous switching noise refers to noise that occurs when multiple bits toggle simultaneously, that is, when the number of simultaneous switches increases, and the potential of the power supply line of a drive circuit or the like that drives these bits fluctuates, causing this power supply line potential fluctuation to be carried over to the transferred data. When simultaneous switching noise occurs, signal quality deteriorates due to increased power supply noise or increased jitter.
[0013] The number of simultaneous switches tends to be particularly large between data in which the logical values of all bits are 0 or 1, such as 0x00 or 0xFF in a data pattern, and the data before and after it. This will be explained using FIGS. 1A and 1B.
[0014] 1A is a diagram illustrating the number of simultaneous switches between 0x00 data and the data before and after it, and FIG. 1B is a diagram illustrating the number of simultaneous switches between 0xFF data and the data before and after it.
[0015] For example, when data is transferred to a destination circuit over multiple cycles, as shown in FIG. 1A , assume that the 8-bit data transferred in cycle N is 0x00. Also, assume that the 8-bit data transferred in cycle N−1 is 0xDA and the 8-bit data transferred in cycle N+1 is 0xEB. Between the data in cycle N−1 and the data in cycle N, the bits DQ1, DQ3, DQ4, DQ6, and DQ7 transition from logic 1 to logic 0, resulting in a high number of simultaneous switches from logic 1 to logic 0 (five). Also, between the data in cycle N and the data in cycle N+1, the bits DQ0, DQ1, DQ3, DQ5, DQ6, and DQ7 transition from logic 0 to logic 1, resulting in a high number of simultaneous switches from logic 0 to logic 1 (six).
[0016] For example, when data is transferred to a destination circuit over multiple cycles, as shown in FIG. 1B , assume that the 8-bit data transferred in cycle N is 0xFF. Assume also that the 8-bit data transferred in cycle N−1 is 0x12 and the 8-bit data transferred in cycle N+1 is 0x80. Between the data in cycle N−1 and the data in cycle N, the bits DQ0, DQ2, DQ3, DQ5, DQ6, and DQ7 transition from logic 0 to logic 1, resulting in a high number of simultaneous switches from logic 0 to logic 1 (6). Furthermore, between the data in cycle N and the data in cycle N+1, the bits DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, and DQ6 transition from logic 1 to logic 0, resulting in a high number of simultaneous switches from logic 1 to logic 0 (7).
[0017] In general digital data, data in which all bits have a logical value of 0 or 1 appears relatively frequently. This is because data in which all bits have a logical value of 0 or 1 is used as a default value for a parameter or for padding or stuffing. In addition, there exists data such as a color bar that contains a large amount of data in which all bits have a logical value of 0 or 1.
[0018] In this way, with general digital data, the frequency of data in which all bits have a logical value of 0 or 1 is high, which tends to result in a large number of simultaneous switches. If there are a large number of simultaneous switches when transferring data, simultaneous switching noise may occur, which can degrade the signal quality of the transferred data.
[0019] Therefore, below, we will explain a semiconductor integrated circuit that can suppress deterioration of data signal quality that can occur depending on the data pattern when transferring data, specifically a semiconductor integrated circuit that can suppress deterioration of signal quality by reducing the number of simultaneous switches caused by data in which the logical values of all bits are 0 or 1.
[0020] Hereinafter, the embodiments will be specifically described with reference to the drawings.
[0021] The embodiments described below are all comprehensive or specific examples, and the numerical values, shapes, materials, components, arrangement and connection of the components, steps, and order of steps shown in the following embodiments are merely examples and are not intended to limit the present disclosure.
[0022] First Embodiment A semiconductor integrated circuit according to a first embodiment will be described below.
[0023] 2 is a block diagram showing an example of a semiconductor integrated circuit 10 according to the first embodiment. In addition to the semiconductor integrated circuit 10, a transfer destination circuit 90 is also shown in FIG. For example, the transfer destination circuit 90 is a circuit provided separately from the semiconductor integrated circuit 10. For example, the transfer destination circuit 90 has a memory.
[0024] The semiconductor integrated circuit 10 is a circuit for scrambling data and transferring it to a destination circuit 90. This data is also referred to as transfer data. For example, the transfer data can have a bus width of B bits (B is an integer equal to or greater than 2; in FIG. 2, B is 8 bits) and can take any value, such as data in which the logical values of all bits are 0 or 1. The semiconductor integrated circuit 10 scrambles the transfer data and transfers the scrambled transfer data, which is the scrambled transfer data, to the destination circuit 90 in each of a plurality of cycles. The semiconductor integrated circuit 10 also transmits a strobe signal to the destination circuit 90 to cause the destination circuit 90 to receive the scrambled data.
[0025] The semiconductor integrated circuit 10 includes a core block 11 , a transfer control unit 20 , a buffer 21 , a buffer 22 , a scrambler 50 , and a look-up table (LUT) 70 .
[0026] The core block 11 generates B-bit transfer data to be transferred to the transfer destination circuit 90, and outputs the generated transfer data to the scrambler 50. At this time, the core block 11 repeatedly generates and repeatedly outputs the transfer data.
[0027] Furthermore, every time the core block 11 outputs transfer data, it outputs a strobe signal to the transfer control unit 20 to cause the transfer destination circuit 90 to receive the transfer data. Here, the strobe signal is, for example, a signal input to a clock input terminal of a flip-flop circuit for acquiring the transferred data in the transfer destination circuit 90. In this case, the strobe signal may be, for example, a differential signal consisting of two bits, or a one-bit signal.
[0028] The scrambler 50 scrambles the B-bit transfer data output from the core block 11. For example, the scrambler 50 includes a scramble key generation unit 51 and an exclusive OR operation unit 52.
[0029] The scramble key generation unit 51 generates a scramble key used when scrambling transfer data. When the bus width of the transfer data is B, the scramble key generation unit 51 generates a scramble key with a Hamming weight of B / 2 if B is an even number, and generates a scramble key with a Hamming weight of (B+1) / 2 or (B-1) / 2 if B is an odd number. The Hamming weight is the number of non-zero symbols in a symbol string, in other words, the number of 1s in a bit string. Hereinafter, a value that is B / 2 when the bus width B is an even number, and a value that is (B+1) / 2 or (B-1) / 2 when the bus width B is an odd number, will also be referred to as "half the bus width." For example, when the bus width of the transfer data is 8, the scramble key generation unit 51 generates a scramble key with a Hamming weight of 4 (for example, as shown in FIG. 2, scramble key X ＨＷ＝４ For example, if the bus width of the transfer data is 9 bits, the scramble key generator 51 generates a scramble key with a Hamming weight of 4 or 5. In FIG. 2, the bus width B is 8 bits, so a scramble key with a Hamming weight of 4 is generated.
[0030] The exclusive OR operation unit 52 scrambles the transfer data by performing an exclusive OR between the transfer data and the scrambling key. Note that the scrambler 50 may have a NEXO-OR operation unit instead of the exclusive OR operation unit 52, and the NEXO-OR operation unit may scramble the transfer data by performing an NEXO-OR between the transfer data and the scrambling key.
[0031] In this way, by scrambling the transfer data by exclusive OR or exclusive NOR of the transfer data, in which the logical values of all bits are 0 or 1, and the scramble key, whose Hamming weight is half the bus width of the transfer data, the Hamming weight of the transfer data (scrambled data) can also be half the bus width of the transfer data (strictly speaking, (B+1) / 2 or (B-1) / 2 if the bus width is odd).
[0032] The transfer control unit 20 transfers scrambled data, which is scrambled transfer data, to the transfer destination circuit 90. Specifically, the transfer control unit 20 transfers the scrambled data to the transfer destination circuit 90 by transferring the scrambled data multiple cycles, and transmits a strobe signal to the transfer destination circuit 90 to cause the transfer destination circuit 90 to receive the scrambled data. More specifically, the transfer control unit 20 transfers B-bit scrambled data output from the scrambler 50 to the transfer destination circuit 90 via the buffer 21 for each of multiple cycles, and transmits a strobe signal to the transfer destination circuit 90 via the buffer 22 to cause the transfer destination circuit 90 to receive the scrambled data.
[0033] For example, the transfer control unit 20 transmits the scrambled data to the memory of the transfer destination circuit 90. That is, for example, the transfer control unit 20 writes and transfers the scrambled data to the memory of the transfer destination circuit 90.
[0034] The destination circuit 90 receives the scrambled data transferred from the semiconductor integrated circuit 10 using the strobe signal transferred from the semiconductor integrated circuit 10 .
[0035] As shown in FIG. 2, the destination circuit 90 includes a receiving circuit 92 and a core block 91 .
[0036] The receiving circuit 92 is configured by, for example, B flip-flop circuits, each of which receives a signal of B-bit scrambled data at its data input terminal and receives a strobe signal at its clock input terminal.
[0037] With the above configuration, the receiving circuit 92 receives the scrambled data transferred from the semiconductor integrated circuit 10 at the timing when the strobe signal (here, a differential signal consisting of 2 bits) changes.
[0038] The core block 91 performs various signal processing using the scrambled data received by the receiving circuit 92. For example, the core block 91 stores the scrambled data in the memory of the transfer destination circuit 90.
[0039] For example, the scrambler 50 generates a scramble key based on the storage address of the scrambled data in the memory of the destination circuit 90. As shown in FIG. 2, the memory of the semiconductor integrated circuit 10 may store an LUT 70, in which a plurality of storage address candidates are associated one-to-one with a plurality of scramble key candidates. The scrambler 50 may generate a scramble key by comparing the storage address with the LUT 70. This allows the scramble key to be easily generated simply by preparing the LUT 70.
[0040] The LUT 70 may have a one-to-one correspondence between each of the candidates for some digits of a plurality of destination addresses and each of the candidates for a plurality of scramble keys, and the scrambler 50 may generate a scramble key by comparing some digits of the destination address with this LUT 70. In this way, by using some digits of the destination address rather than all digits, the number of scramble key candidates can be reduced, and the LUT 70 can be easily prepared.
[0041] Furthermore, for example, the transfer control unit 20 acquires the scrambled data from the memory of the transfer destination circuit 90. That is, for example, the transfer control unit 20 acquires the scrambled data from the memory of the transfer destination circuit 90 by read transfer.
[0042] For example, the scrambler 50 generates a scramble key based on the storage address of the acquired scrambled data, and descrambles the acquired scrambled data using the scramble key, thereby decrypting the scrambled data and acquiring the transfer data before scrambling.
[0043] If the storage address of the scrambled data is known, a scramble key for descrambling this scrambled data can be generated, eliminating the need for a storage area to store the scramble key used during scrambling. In other words, by utilizing the storage address required for write transfer and read transfer of data, there is no need to store the scramble key.
[0044] Next, the effect achieved by scrambling transfer data using a scramble key whose Hamming weight is half the bus width of the transfer data will be described with reference to FIG.
[0045] FIG. 3 is a diagram for explaining the number of simultaneous switches between the transfer data of 0x00 and the transfer data before and after it after the transfer data has been scrambled by an exclusive OR operation with a scramble key having a Hamming weight of 4.
[0046] For example, when transfer data (e.g., 8-bit data) is transferred over multiple cycles, the data transferred in cycle N-1 is 0xFF, the data transferred in cycle N is 0x00, and the data transferred in cycle N+1 is 0xFF. The scrambler 50 scrambles the transfer data in each cycle with a scramble key having a Hamming weight of 4, so that, as shown in Fig. 3, the scrambled data after scrambling 0xFF data transferred in cycle N-1 with scramble key 0xAA becomes 0x55, the scrambled data after scrambling 0x00 data transferred in cycle N with scramble key 0x33 becomes 0x33, and the scrambled data after scrambling 0xFF data transferred in cycle N+1 with scramble key 0x1B becomes 0xE4.
[0047] 3, it can be seen that the Hamming weight of the scrambled data, which is transfer data scrambled with a scramble key having a Hamming weight of 4, is also 4. This makes it possible to limit the number of simultaneous switching operations to 4 or less.
[0048] Specifically, between the scrambled data of the N-1 cycle and the scrambled data of the N cycle, the bits of DQ1 and DQ5 transition from a logical value of 0 to a logical value of 1, and the number of simultaneous switches from a logical value of 0 to a logical value of 1 is 2. Furthermore, between the scrambled data of the N-1 cycle and the scrambled data of the N cycle, the bits of DQ2 and DQ6 transition from a logical value of 1 to a logical value of 0, and the number of simultaneous switches from a logical value of 1 to a logical value of 0 is 2.
[0049] Furthermore, between the scrambled data of the Nth cycle and the scrambled data of the N+1th cycle, the bits of DQ2, DQ6, and DQ7 transition from logic 0 to logic 1, and the number of simultaneous switches from logic 0 to logic 1 is 3. Furthermore, between the scrambled data of the Nth cycle and the scrambled data of the N+1th cycle, the bits of DQ0, DQ1, and DQ4 transition from logic 1 to logic 0, and the number of simultaneous switches from logic 1 to logic 0 is 3.
[0050] In this way, by scrambling the transfer data using a scrambling key whose Hamming weight is half the bus width of the transfer data, the number of simultaneous switches between transfer data in which all bits have a logical value of 0 and transfer data in which all bits have a logical value of 1 can be reduced to less than half the bus width of the transfer data.
[0051] For example, simultaneous switching noise can be suppressed by making the number of simultaneous switches between transfer data in which all bits have a logical value of 0 and transfer data in which all bits have a logical value of 1 (e.g., the number of simultaneous switches from logical value 0 to logical value 1, or the number of simultaneous switches from logical value 1 to logical value 0) equal to or less than half the bus width of the transfer data. For example, even when transfer data in which all bits have a logical value of 0 or 1 is scrambled with a scramble key whose Hamming weight has not been adjusted, the number of simultaneous switches between transfer data in which all bits have a logical value of 0 and transfer data in which all bits have a logical value of 1 may be equal to or less than half the bus width of the transfer data. However, simply scrambling the transfer data with a scramble key whose Hamming weight has not been adjusted may result in the number of simultaneous switches being greater than half the bus width of the transfer data, and simultaneous switching noise may not be suppressed.
[0052] In contrast, by using a scramble key with a Hamming weight of B / 2, (B+1) / 2, or (B-1) / 2 (i.e., a scramble key with a Hamming weight that is half the bus width of the transfer data) to scramble transfer data in which all bits have a logical value of 0 or 1, the number of simultaneous switches between transfer data in which all bits have a logical value of 0 and transfer data in which all bits have a logical value of 1 can be reduced. This is because when transfer data in which all bits have a logical value of 0 or 1 is scrambled with such a scramble key, half of the bits in the transfer data (scrambled data) have a logical value of 0 and the remaining half have a logical value of 1, resulting in a maximum number of simultaneous switches that is half the bus width of the transfer data. Therefore, when transferring transfer data, it is possible to suppress degradation of the signal quality of the transfer data that may occur depending on the data pattern.
[0053] Second Embodiment Next, a semiconductor integrated circuit according to a second embodiment will be described.
[0054] 4 is a block diagram showing an example of a semiconductor integrated circuit 10a according to the second embodiment. In addition to the semiconductor integrated circuit 10a, Fig. 4 also shows a transfer destination circuit 90. For example, the transfer destination circuit 90 is a circuit provided separately from the semiconductor integrated circuit 10a, and includes a memory.
[0055] The semiconductor integrated circuit 10a differs from the semiconductor integrated circuit 10 according to the first embodiment in that it includes a transfer control unit 20a instead of the transfer control unit 20, and further includes a determination unit 30, a dummy data generation unit 40, and a threshold setting unit 60. Since the other points are the same as those in the semiconductor integrated circuit 10 according to the first embodiment, the following description will mainly focus on the points that are different.
[0056] The transfer control unit 20a transfers scrambled data, which is scrambled transfer data, to the transfer destination circuit 90. Specifically, the transfer control unit 20a transfers the scrambled data to the transfer destination circuit 90 by transferring the scrambled data multiple cycles, and transmits a strobe signal to the transfer destination circuit 90 to cause the transfer destination circuit 90 to receive the scrambled data. More specifically, the transfer control unit 20a receives as input B-bit scrambled data output from the scrambler 50, a strobe signal output from the core block 11, B-bit dummy data output from a dummy data generation unit 40 (described later), and a determination flag output from a determination unit 30 (described later). The transfer control unit 20a transfers the B-bit transfer data to the transfer destination circuit 90 via the buffer 21 for each of multiple cycles, and transmits a strobe signal to the transfer destination circuit 90 via the buffer 22 to cause the transfer destination circuit 90 to receive the transfer data. Here, the transfer data is scrambled data output from the scrambler 50 or dummy data output from the dummy data generation unit 40. Dummy data refers to data that is not processed in the transfer destination circuit 90 (here, the receiving circuit 92). The determination flag is a flag that indicates the result of a determination made by the transfer control unit 20a as to whether or not to transmit dummy data before the transfer control unit 20a transfers the transfer-scheduled data, which is the latest scrambled data output from the scrambler 50, to the transfer destination circuit 90.
[0057] When the determination unit 30 outputs a determination flag indicating a determination result that the transfer control unit 20a has determined not to transmit dummy data before the transfer control unit 20a transfers the data to be transferred to the transfer destination circuit 90, the transfer control unit 20a transfers the data to be transferred to the transfer destination circuit 90 and transmits a strobe signal to the transfer destination circuit 90. In this case, the transfer destination circuit 90 receives the scrambled data transferred from the transfer control unit 20a.
[0058] When the determination unit 30 outputs a determination flag indicating a determination result that the transfer control unit 20a has determined to transmit dummy data before the transfer control unit 20a transfers the data to be transferred to the transfer destination circuit 90, the transfer control unit 20a transmits the dummy data to the transfer destination circuit 90 and suppresses the transmission of a strobe signal for causing the transfer destination circuit 90 to receive the dummy data. In this case, the transfer destination circuit 90 does not receive the dummy data transferred from the transfer control unit 20a.
[0059] Furthermore, when the judgment unit 30 outputs a judgment flag indicating the judgment result that the transfer control unit 20a has determined to send dummy data before the transfer control unit 20a transfers the data to be transferred to the transfer destination circuit 90, the transfer control unit 20a outputs a stop signal to the core block 11 to stop the output of the next transfer data for one cycle.
[0060] The determination unit 30 receives as input the scrambled data to be transferred next by the transfer control unit 20a, which is output from the scrambler 50, and the scrambled data that has been transferred in the most recent cycle among the data previously transferred by the transfer control unit 20a, which is output from the transfer control unit 20a. The determination unit 30 determines whether the number of bits that transition from logic 0 to logic 1, or the number of bits that transition from logic 1 to logic 0, between the scrambled data to be transferred and the scrambled data that has been transferred in the most recent cycle, is greater than a predetermined threshold (for example, 4).
[0061] For example, the predetermined threshold may be a variable, and may be set by the threshold setting unit 60. Specifically, if B is an even number, the threshold setting unit 60 sets the predetermined threshold to B / 2 or more, and if B is an odd number, the threshold setting unit 60 sets the predetermined threshold to (B+1) / 2 or more. For example, if the bus width of the transfer data is 8, the threshold setting unit 60 sets the predetermined threshold to 4 or more, and if the bus width of the transfer data is 9, the threshold setting unit 60 sets the predetermined threshold to 5. This makes it possible to set a condition under which dummy data is transmitted without transferring scrambled data.
[0062] The semiconductor integrated circuit 10a does not necessarily have to include the threshold setting unit 60, and the predetermined threshold may be a predetermined value (fixed value).
[0063] The dummy data generation unit 40 receives as input the scrambled data to be transferred next by the transfer control unit 20a output from the scrambler 50, the scrambled data that has already been transferred in the most recent cycle among the data previously transferred by the transfer control unit 20a output from the transfer control unit 20a, and the judgment flag output from the judgment unit 30, generates dummy data using a predetermined method, and outputs the generated dummy data to the transfer control unit 20a.
[0064] The dummy data generator 40 generates dummy data between the scrambled data and the dummy data such that the maximum number of simultaneous switching operations is half the bus width of the transfer data.
[0065] For example, the dummy data generation unit 40 may generate dummy data consisting of a first bit, which is K bits (K is half the bus width) out of the B bits in the data to be transferred, and a second bit, which is B-K bits excluding the first bit out of the B bits in the most recently transferred data.
[0066] Furthermore, for example, the dummy data generating section 40 may generate dummy data whose predetermined Hamming weight is half the bus width.
[0067] When the logical values of all bits of the transfer data are 0 or 1, the number of bits that transition from logical 0 to logical 1, or the number of bits that transition from logical 1 to logical 0, between the scrambled data to be transferred and the scrambled data that has been transferred in the latest cycle is equal to or less than a predetermined threshold value (for example, 4). As explained in the first embodiment, this is because the transfer data is scrambled using a scramble key whose Hamming weight is half the bus width of the transfer data.
[0068] On the other hand, there may be cases where transfer data in which the logical values of all bits are not 0 or 1 is input to the semiconductor integrated circuit 10a. In such cases, the number of bits that transition from logical value 0 to logical value 1, or the number of bits that transition from logical value 1 to logical value 0, between the scrambled data to be transferred and the scrambled data that has already been transferred in the latest cycle may be greater than a predetermined threshold value (for example, 4).
[0069] Therefore, when the judgment unit 30 determines that the number of bits transitioning from logical value 0 to logical value 1, or the number of bits transitioning from logical value 1 to logical value 0, is greater than a predetermined threshold, the transfer control unit 20a sends dummy data to the destination circuit 90 before transferring the scrambled data to be transferred to the destination circuit 90, and performs an invalidation process to invalidate the dummy data in the destination circuit 90.
[0070] Based on the transfer-scheduled data and the transferred data, the determination unit 30 can determine whether there is a relatively high possibility that noise that may occur depending on the data pattern will be carried over into the transfer-scheduled data in the cycle in which the transfer-scheduled data is scheduled to be transferred. Therefore, if there is a relatively high possibility, the determination unit 30 can determine that the transfer control unit 20a should transmit dummy data to the transfer destination circuit 90 before the transfer control unit 20a transfers the transfer-scheduled data to the transfer destination circuit 90. If the determination unit 30 makes such a determination, the transfer control unit 20a transfers the dummy data to the transfer destination circuit 90 before transferring the transfer-scheduled data. In other words, if there is a relatively high possibility that noise that may occur depending on the data pattern will be carried over into the transfer-scheduled data in the cycle in which the transfer-scheduled data is scheduled to be transferred, the transfer control unit 20a transmits the dummy data without transferring the transfer-scheduled data. Therefore, even if transfer data in which the logical values of all bits are not 0 or 1 are input to the semiconductor integrated circuit 10a and the number of simultaneous switches can be greater than half the bus width of the transfer data, deterioration of the signal quality of the transfer data that can occur depending on the data pattern can be suppressed when transferring the transfer data.
[0071] (Other Embodiments) As described above, the embodiments have been described as examples of the technology according to the present disclosure. However, the technology according to the present disclosure is not limited to these, and can be applied to embodiments in which modifications, substitutions, additions, omissions, etc. are made as appropriate. For example, the following modifications are also included in one embodiment of the present disclosure.
[0072] For example, although the bus width of the transfer data is 8 bits in the examples shown in FIGS. 2 and 4, the bus width of the transfer data is not limited to 8 bits.
[0073] For example, the scrambler 50 may further add a scramble key to the beginning or end of the scrambled data, thereby making it possible to descramble the scrambled data using the scramble key added to the scrambled data, eliminating the need for a storage area for storing the scramble key used during scrambling.
[0074] For example, the destination circuit 90 may be a circuit that does not have a memory, such as a display, and the transfer data may be image data or video data.
[0075] For example, in the above embodiment, an example of generating a scramble key using the LUT 70 has been described, but this is not limiting. For example, a scramble key may be generated by randomly selecting one scramble key from a plurality of scramble key candidates prepared in advance.
[0076] In the second embodiment, an example has been described in which, when a judgment flag indicating a judgment result that the transfer control unit 20a has judged to send dummy data is output from the judgment unit 30 before the transfer control unit 20a transfers the data to be transferred to the transfer destination circuit 90, the transfer control unit 20a performs an invalidation process to invalidate the dummy data in the transfer destination circuit 90, by suppressing the transmission of a strobe signal to cause the transfer destination circuit 90 to receive the dummy data.
[0077] On the other hand, when the determination unit 30 outputs a determination flag indicating a determination result that the transfer control unit 20a has determined to transmit dummy data before the transfer control unit 20a transmits the data to be transferred to the transfer destination circuit 90, the transfer control unit 20a may perform processing to cause the transfer destination circuit 90 to invalidate the dummy data by transmitting an invalid flag signal to the transfer destination circuit 90 to cause the transfer destination circuit 90 to invalidate the dummy data. At this time, the transfer control unit 20a may transmit the strobe signal to the transfer destination circuit 90 without performing processing to suppress transmission of the strobe signal to cause the transfer destination circuit 90 to receive the dummy data.
[0078] On the other hand, when the determination unit 30 outputs a determination flag indicating a determination result that the transfer control unit 20a has determined not to transmit dummy data before the transfer control unit 20a transmits the data to be transferred to the transfer destination circuit 90, the transfer control unit 20a transfers the data to be transferred to the transfer destination circuit 90 and transmits a strobe signal to the transfer destination circuit 90. In this case, the transfer control unit 20a does not transmit an invalid flag signal to the transfer destination circuit 90.
[0079] As a result, the scrambled data transferred from the semiconductor integrated circuit 10 a is input to the core block 91 , but the dummy data is not input, and the dummy data can be invalidated in the transfer destination circuit 90 .
[0080] For example, the present disclosure can be realized not only as a semiconductor integrated circuit, but also as a data transfer method including steps (processing) performed by components that make up the semiconductor integrated circuit.
[0081] FIG. 5 is a flowchart showing an example of a data transfer method according to another embodiment.
[0082] The data transfer method is a data transfer method executed by a semiconductor integrated circuit for scrambling data and transferring it to a destination circuit, and includes the steps of: generating a scramble key having a Hamming weight of B / 2 (step S12) when B is an even number (Yes in step S11); generating a scramble key having a Hamming weight of (B+1) / 2 or (B-1) / 2 when B is an odd number (No in step S11) (step S13); scrambling the data using the scramble key (step S14); and transferring the scrambled data, which is the scrambled data, to the destination circuit (step S15), as shown in FIG. 5 .
[0083] For example, the present disclosure can be realized as a program for causing a computer (processor) to execute steps included in a data transfer method. Furthermore, the present disclosure can be realized as a non-transitory computer-readable recording medium, such as a CD-ROM, on which the program is recorded.
[0084] For example, when the present disclosure is realized as a program (software), each step is performed by running the program using hardware resources such as a computer's CPU, memory, input / output circuits, etc. In other words, each step is performed by the CPU acquiring data from memory or input / output circuits, etc., performing calculations, and outputting the calculation results to memory or input / output circuits, etc.
[0085] In the above-described embodiments, each component included in the semiconductor integrated circuit may be configured with dedicated hardware, or may be realized by executing a software program suitable for each component. Each component may be realized by a program execution unit such as a CPU or processor reading and executing a software program recorded on a recording medium such as a hard disk or semiconductor memory.
[0086] Some or all of the functions of the semiconductor integrated circuit according to the above embodiments are typically realized as an LSI, which is an integrated circuit. These may be individually integrated into single chips, or some or all of them may be integrated into a single chip. Furthermore, the integrated circuit is not limited to an LSI, and may be realized using a dedicated circuit or a general-purpose processor. It is also possible to use an FPGA (Field Programmable Gate Array) that can be programmed after LSI manufacturing, or a reconfigurable processor that can reconfigure the connections and settings of circuit cells within the LSI.
[0087] Furthermore, if an integrated circuit technology that can replace LSI emerges due to advances in semiconductor technology or other derivative technologies, it is natural that each component included in a semiconductor integrated circuit may be integrated using that technology.
[0088] In addition, this disclosure also includes forms obtained by making various modifications to the embodiments that a person skilled in the art would think of, and forms realized by arbitrarily combining the components and functions in each embodiment within the scope of the present disclosure.
[0089] (Additional Notes) The above description of the embodiments discloses the following techniques.
[0090] (Technology 1) A semiconductor integrated circuit for scrambling data and transferring it to a destination circuit, the semiconductor integrated circuit comprising: a scrambler that generates a scrambling key with a Hamming weight of B / 2 when B is an even number, and a scrambling key with a Hamming weight of (B+1) / 2 or (B-1) / 2 when B is an odd number, where B is a bus width of the data, and scrambles the data using the scrambling key; and a transfer control unit that transfers the scrambled data, which is the scrambled data, to the destination circuit.
[0091] For example, simultaneous switching noise can be suppressed by making the number of simultaneous switches between data whose all bits have a logical value of 0 and data whose all bits have a logical value of 1 (e.g., the number of simultaneous switches from logical value 0 to logical value 1, or the number of simultaneous switches from logical value 1 to logical value 0) equal to or less than half the bus width of the data (strictly speaking, equal to or less than (B+1) / 2 if the bus width is odd). For example, even when data whose all bits have a logical value of 0 or 1 is scrambled with a scramble key whose Hamming weight has not been adjusted, the number of simultaneous switches between data whose all bits have a logical value of 0 and data whose all bits have a logical value of 1 may be equal to or less than half the bus width of the data. However, simply scrambling the data with a scramble key whose Hamming weight has not been adjusted may result in the number of simultaneous switches being greater than half the bus width of the data, and simultaneous switching noise may not be suppressed.
[0092] In contrast, by using a scramble key with a Hamming weight of B / 2, (B+1) / 2, or (B-1) / 2 (hereinafter also referred to as a scramble key with a Hamming weight half the bus width of the data) to scramble data in which all bits have a logical value of 0 or 1, the number of simultaneous switches between data in which all bits have a logical value of 0 and data in which all bits have a logical value of 1 can be reduced. This is because when data in which all bits have a logical value of 0 or 1 is scrambled with such a scramble key, half of all the bits in the data have a logical value of 0 and the remaining half have a logical value of 1, resulting in a maximum number of simultaneous switches equal to half the bus width of the data. Therefore, degradation of data signal quality that may occur depending on the data pattern when transferring data can be suppressed.
[0093] (Technology 2) The semiconductor integrated circuit according to Technology 1, wherein the scrambler scrambles the data by performing an exclusive OR or an exclusive NOR on the data and the scrambling key.
[0094] In this way, by scrambling the data, all of whose bits have a logical value of 0 or 1, using the exclusive OR or exclusive NOR of the scrambling key, the Hamming weight of the data can also be half the bus width of the data.
[0095] (Technology 3) A semiconductor integrated circuit according to Technology 1 or 2, wherein the transfer control unit transmits the scrambled data to a memory of the destination circuit, and the scrambler generates the scramble key based on a storage address of the scrambled data in the memory.
[0096] This makes it possible to generate a scramble key according to the address where the data is saved.
[0097] (Technology 4) The semiconductor integrated circuit according to Technology 3, wherein the scrambler generates the scramble key by comparing the destination address with a lookup table in which each of a plurality of destination address candidates corresponds one-to-one with each of a plurality of scramble key candidates.
[0098] This makes it possible to easily generate a scramble key simply by preparing a lookup table.
[0099] (Technology 5) The semiconductor integrated circuit described in Technology 3, wherein the scrambler generates the scramble key by comparing a portion of the digits of the destination address with a lookup table in which each of a plurality of candidates for the portion of the digits of the destination address is in a one-to-one correspondence with each of a plurality of candidates for the scramble key.
[0100] This allows a scramble key to be generated easily by simply preparing a lookup table. Also, by using only some of the digits of the destination address instead of all of them, the number of scramble key candidates can be reduced, making it easier to prepare a lookup table.
[0101] (Technology 6) The semiconductor integrated circuit according to any one of Technologies 3 to 5, wherein the transfer control unit further acquires the scrambled data from the memory, and the scrambler generates the scramble key based on the storage address of the acquired scrambled data, and descrambles the acquired scrambled data using the scramble key.
[0102] This means that if the storage address of the scrambled data is known, a scramble key for descrambling this scrambled data can be generated, eliminating the need for a storage area for storing the scramble key used during scrambling.
[0103] (Technology 7) The semiconductor integrated circuit according to any one of techniques 1 to 5, wherein the scrambler further adds the scramble key to the beginning or end of the scrambled data.
[0104] According to this, the scrambled data can be descrambled using the scramble key assigned to the scrambled data, and therefore a storage area for storing the scramble key used during scrambling is not required.
[0105] (Technology 8) The transfer control unit transfers the scrambled data to the transfer destination circuit by performing multiple cycles of transferring the scrambled data, and transmits a strobe signal to the transfer destination circuit to cause the transfer destination circuit to receive the scrambled data. The semiconductor integrated circuit further calculates the number of bits that transition from a logic value of 0 to a logic value of 1, or the number of bits that transition from a logic value of 1 to a logic value of 0, between the scrambled data that the transfer control unit plans to transfer next and the scrambled data that the transfer control unit has already transferred in the latest cycle among the data that the transfer control unit has previously transferred. A semiconductor integrated circuit according to any one of techniques 1 to 7, comprising: a determination unit that determines whether a number of bits is greater than a predetermined threshold; and a dummy data generation unit that generates dummy data, wherein when the determination unit determines that the number of bits that transition from a logical value 0 to a logical value 1, or the number of bits that transition from a logical value 1 to a logical value 0, is greater than the predetermined threshold, the transfer control unit transfers the dummy data to the transfer destination circuit and performs invalidation processing to invalidate the dummy data in the transfer destination circuit before transferring the scrambled data to be transferred to the transfer destination circuit.
[0106] A semiconductor integrated circuit may receive data in which the logical values of all bits are not 0 or 1. When data in which the logical values of all bits are not 0 or 1 is scrambled using a scramble key whose Hamming weight is half the bus width of the data, the number of simultaneous switches may exceed half the bus width of the data, and simultaneous switching noise may not be suppressed. Therefore, in such cases, dummy data is used.
[0107] Specifically, the determination unit can determine, based on the transfer-scheduled data and the transferred data, whether there is a relatively high possibility that noise that may occur depending on the data pattern will be carried over into the transfer-scheduled data in a cycle in which the transfer-scheduled data is scheduled to be transferred. Therefore, if the possibility is relatively high, the determination unit can determine that the transfer control unit should transmit dummy data to the transfer destination circuit before the transfer control unit transfers the transfer-scheduled data to the transfer destination circuit. If the determination unit makes such a determination, the transfer control unit transmits dummy data to the transfer destination circuit before transferring the transfer-scheduled data. That is, if there is a relatively high possibility that noise that may occur depending on the data pattern will be carried over into the transfer-scheduled data in a cycle in which the transfer-scheduled data is scheduled to be transferred, the transfer control unit transmits the dummy data without transferring the transfer-scheduled data. Therefore, even if data in which the logical values of all bits are not 0 or 1 are input to the semiconductor integrated circuit and the number of simultaneous switches is greater than half the bus width of the data, degradation of the signal quality of the transfer data that may occur depending on the data pattern can be suppressed when transferring data.
[0108] (Technology 9) The semiconductor integrated circuit according to Technology 8, further comprising a threshold setting unit that sets the predetermined threshold, and the threshold setting unit sets the predetermined threshold to B / 2 or more when B is an even number, and sets the predetermined threshold to (B+1) / 2 or more when B is an odd number.
[0109] This makes it possible to set conditions under which dummy data is transmitted without scrambled data being transferred.
[0110] (Technology 10) A data transfer method executed by a semiconductor integrated circuit for scrambling data and transferring the scrambled data to a destination circuit, the data transfer method including the steps of: generating a scramble key having a Hamming weight of B / 2 when B is an even number, and generating a scramble key having a Hamming weight of (B+1) / 2 or (B-1) / 2 when B is an odd number, where B is a bus width of the data; and scrambling the data using the scramble key; and transferring the scrambled data, which is the scrambled data, to the destination circuit.
[0111] This makes it possible to provide a data transfer method that can suppress deterioration of data signal quality that may occur depending on the data pattern when transferring data.
[0112] The present disclosure can be applied to semiconductor integrated circuits that transfer data.
[0113] REFERENCE SIGNS LIST 10, 10a Semiconductor integrated circuit 11, 91 Core block 20, 20a Transfer control unit 21, 22 Buffer 30 Determination unit 40 Dummy data generation unit 50 Scrambler 51 Scramble key generation unit 52 Exclusive OR operation unit 60 Threshold setting unit 70 LUT 90 Transfer destination circuit 92 Receiving circuit
Claims
1. A semiconductor integrated circuit for scrambling data and transferring it to a destination circuit, A scrambler that, when the bus width of the data is B, generates a scramble key with a Hamming weight of B / 2 if B is even, and generates a scramble key with a Hamming weight of (B+1) / 2 or (B-1) / 2 if B is odd, and scrambles the data using the scramble key, The system includes a transfer control unit that transfers the scrambled data, which is the scrambled data, to a transfer destination circuit. Semiconductor integrated circuit.
2. The scrambler scrambles the data by performing an exclusive OR or negative exclusive OR operation between the data and the scramble key. The semiconductor integrated circuit according to claim 1.
3. The transfer control unit transmits the scrambled data to the memory of the transfer destination circuit. The scrambler generates the scramble key based on the destination address of the scrambled data in the memory. The semiconductor integrated circuit according to claim 1.
4. The scrambler generates the scramble key by matching the destination address with a lookup table in which each of the multiple candidate destination addresses is associated one-to-one with each of the multiple candidate scramble keys. The semiconductor integrated circuit according to claim 3.
5. The scrambler generates the scramble key by matching a portion of the destination address with each of the multiple candidate portions of the destination address and each of the multiple candidate scramble keys in a one-to-one correspondence. The semiconductor integrated circuit according to claim 3.
6. The transfer control unit further acquires the scrambled data from the memory, The scrambler generates a scramble key based on the storage address of the acquired scrambled data, and descrambles the acquired scrambled data using the scramble key. The semiconductor integrated circuit according to claim 3.
7. The scrambler further adds the scramble key to the beginning or end of the scrambled data. The semiconductor integrated circuit according to claim 1.
8. The transfer control unit performs the transfer of the scrambled data multiple times, thereby transferring the data to the destination circuit, and also transmits a strobe signal to the destination circuit to cause the destination circuit to receive the scrambled data. The aforementioned semiconductor integrated circuit further, A determination unit determines whether the number of bits transitioning from logical value 0 to logical value 1, or from logical value 1 to logical value 0, between the scrambled data scheduled to be transferred by the transfer control unit next and the scrambled data that has been transferred in the most recent cycle of data previously transferred by the transfer control unit, is greater than a predetermined threshold. It comprises a dummy data generation unit that generates dummy data, If the determination unit determines that the number of bits transitioning from logical value 0 to logical value 1, or the number of bits transitioning from logical value 1 to logical value 0, the transfer control unit transfers the dummy data to the transfer destination circuit and performs invalidation processing to invalidate the dummy data in the transfer destination circuit before transferring the scrambled data to the transfer destination circuit. A semiconductor integrated circuit according to any one of claims 1 to 7.
9. The semiconductor integrated circuit further includes a threshold setting unit for setting the predetermined threshold, The threshold setting unit is, If B is an even number, the predetermined threshold is set to B / 2 or greater. If B is an odd number, the predetermined threshold is set to (B+1) / 2 or greater. The semiconductor integrated circuit according to claim 8.
10. A data transfer method performed by a semiconductor integrated circuit for scrambling data and transferring it to a destination circuit, If the bus width of the data is B, the scramble key is generated such that if B is even, a scramble key with a Hamming weight of B / 2 is generated, and if B is odd, a scramble key with a Hamming weight of (B+1) / 2 or (B-1) / 2 is generated, and the data is scrambled using the scramble key. The step of transferring the scrambled data, which is the scrambled data, to a destination circuit includes: Data transfer method.