Distributed Amplifier

Abstract

The distributed amplifier electrically connects between a plurality of transistors (11)-(14) whose source nodes are grounded, and the gate node of the last transistor (14) located on the input terminal (100) and the output terminal (200) side, and includes a gate line (2) having a plurality of gate connection points (21)-(24) to which the gate nodes of the plurality of transistors (11)-(14) are electrically connected, and a plurality of inter-gate lines (201)-(204) each connected between adjacent gate connection points, and a line (2) for gates connecting the drain node of the first transistor (11) located on the input terminal (100) side and the output terminal (200). the drain connection points (31)-(34) to which the drain nodes of the plurality of transistors (11)-(14) are electrically connected, respectively; and a line for drain (3) having a plurality of inter-drain lines (301)-(304) which are series circuits of drain-side transmission lines (30a1)-(30a4) and capacitors (30b1)-(30b4), each connected between adjacent drain connection points; and a plurality of drain voltage supply circuits (61)-(64) each connected between the drain voltage supply node and a corresponding drain connection point (31)-(34) of the line for drain (3).

Description

[Technical field]

[0001] The present disclosure relates to a distributed amplifier, which is a type of high-frequency amplifier. [Background technology]

[0002] 2. Description of the Related Art Distributed amplifiers are implemented in wireless communication devices, radar devices, and the like as high-frequency amplifiers for amplifying high-frequency signals. Non-Patent Document 1 shows this type of distributed amplifier. The distributed amplifier disclosed in Non-Patent Document 1 has multiple source-grounded transistors arranged in parallel, with the drain electrodes of adjacent transistors in the multiple transistors being electrically connected by a drain-side transmission line, and the gate electrodes of adjacent transistors in the multiple transistors being electrically connected by a gate-side transmission line. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] C. Campbell, “A Wideband Power Amplifier MMIC Utilizing GaN on SiC HEMT Technology,” IEEE JOURNAL. Solid-State Circuits, vol.44, no.10, Oct.2009. pp. 2640-2647 Summary of the Invention [Problem to be solved by the invention]

[0004] The distributed amplifier disclosed in Non-Patent Document 1 has a configuration in which the drain supply voltage for all transistors is provided from a common bias circuit, that is, the drain supply voltage is equal for all transistors. This causes a problem in that the drain efficiency of the transistors on the input side becomes lower than the drain efficiency of the transistors on the output side, resulting in a low efficiency of the distributed amplifier as a whole.

[0005] The present disclosure is made to solve the above-mentioned problems, and has an object to provide a distributed amplifier in which the drain efficiency of a transistor is improved and the efficiency of the distributed amplifier as a whole is improved. [Means for solving the problem]

[0006] The distributed amplifier according to the present disclosure electrically connects between a plurality of transistors, each of whose source nodes is grounded, and a gate node of a last transistor located on the input terminal and output terminal side, and has a plurality of gate connection points to which the gate nodes of the plurality of transistors are electrically connected, and each of which is connected between adjacent gate connection points. , which is a series circuit of the gate side transmission line and a capacitor. a gate line having a plurality of inter-gate lines; a plurality of gate bias voltage application circuits each connected between a gate voltage application node and a corresponding gate connection point of the gate line; The drain node of the first transistor located on the input terminal side is electrically connected to the output terminal, and the drain nodes of the plurality of transistors are electrically connected to each other via a plurality of drain connection points, and the drain line has a plurality of inter-drain lines which are series circuits of a drain-side transmission line and a capacitor, each of which is connected between adjacent drain connection points, and a plurality of drain voltage supply circuits each of which is connected between the drain voltage supply node and a corresponding drain connection point of the drain line. Effect of the Invention

[0007] According to the present disclosure, it is possible to accommodate a wideband input signal, the drain efficiency of the transistor is improved, and the efficiency of the entire distributed amplifier is improved. [Brief description of the drawings]

[0008] [Figure 1] 1 is a configuration diagram showing an equivalent circuit of a distributed amplifier according to a first embodiment. [Diagram 2] 4 is a diagram showing an example of static characteristics and load lines of adjacent transistors when the drain voltage and the gate bias voltage are the same in the distributed amplifier according to the first embodiment; FIG. [Diagram 3]FIG. 4 is a diagram showing an example of load lines of a first to fourth transistors when the drain voltage and the gate bias voltage are the same in the distributed amplifier according to the first embodiment. [Figure 4] FIG. 4 is a diagram showing an example of the drain efficiency of the first to fourth transistors when the drain voltage and the gate bias voltage are the same in the distributed amplifier according to the first embodiment. [Diagram 5] 1 is a diagram showing an example of the static characteristics and load line of adjacent transistors when the drain voltage of the transistor on the input terminal side is made lower than the drain voltage of the transistor on the output terminal side in the distributed amplifier according to the first embodiment. FIG. [Figure 6] 4 is a diagram showing a drain voltage and a gate bias voltage in the distributed amplifier according to the first embodiment. FIG. [Figure 7] FIG. 11 is a diagram showing an example of load lines of a first transistor to a fourth transistor when the drain voltages supplied from the drain voltage supply node located on the output terminal side to the drain voltage supply node located on the input terminal side are successively decreased, and the gate bias voltages applied from the gate voltage application node located on the output terminal side to the gate voltage application node located on the input terminal side are successively increased in a distributed amplifier according to the first embodiment. [Figure 8] FIG. 11 is a diagram showing an example of the drain efficiency of a first transistor to a fourth transistor when the drain voltages supplied from the drain voltage supply node located on the output terminal side to the drain voltage supply node located on the input terminal side are successively decreased, and the gate bias voltages applied from the gate voltage application node located on the output terminal side to the gate voltage application node located on the input terminal side are successively increased in the distributed amplifier of the first embodiment. [Figure 9] FIG. 4 is a diagram showing an example of drain efficiency as a distributed amplifier relative to the frequency of an input signal in the distributed amplifier according to the first embodiment. [Figure 10]4 is a diagram showing an example of output power as a distributed amplifier relative to the frequency of an input signal in the distributed amplifier according to the first embodiment. FIG. [Figure 11] FIG. 11 is a configuration diagram showing an equivalent circuit of a distributed amplifier according to a second embodiment. [Figure 12] FIG. 11 is a configuration diagram showing an equivalent circuit of a distributed amplifier according to a third embodiment. [Figure 13] FIG. 11 is a configuration diagram showing an equivalent circuit of a distributed amplifier according to a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Embodiment 1 A distributed amplifier according to a first embodiment will be described with reference to FIGS. The distributed amplifier according to the first embodiment is a high-frequency amplifier that amplifies high-frequency signals used in wireless communication devices, radar devices, and the like. The distributed amplifier according to the first embodiment is implemented in a GaN (Gallium Nitride) MMIC (Monolithic Microwave Integrated Circuit).

[0010] The distributed amplifier of the first embodiment includes a plurality of transistors 11-14, a gate line 2 having a plurality of inter-gate lines 201-205, a drain line 3 having a plurality of inter-drain lines 301-304, a plurality of gate input circuits 41-44, a plurality of gate bias voltage application circuits 51-54, a plurality of drain voltage supply circuits 61-64, and a termination resistor 7.

[0011] In the multiple transistors 11 to 14, the subscripts attached to the symbols indicate the first, second, third, and fourth transistors in order from the input terminal 100 side. The first transistor 11 is the first transistor located on the input terminal 100 side, and the fourth transistor 14 is the last transistor located on the output terminal 200 side.

[0012] In the multiple gate-to-gate lines 201-205, the multiple drain-to-drain lines 301-304, the multiple gate bias voltage application circuits 51-54, and the multiple drain voltage supply circuits 61-64, the subscripts added to the symbols correspond to the multiple transistors 11-14, respectively, and are designated first, second, third, and fourth in order from the input terminal 100 side, just like the multiple transistors 11-14.

[0013] For the sake of explanation, the case where the number of transistors 11 to 14 is four has been described, but any number may be used. Moreover, when referring to any one of a plurality of items (N: a natural number of 2 or more), the subscript n (1 to N) is added for explanation. In addition, when explaining in common, the subscripts and the numbers 1 to 4 will be omitted to avoid complication.

[0014] An input signal, which is a high frequency signal, is input to an input terminal 100 . An input signal input to an input terminal 100 is amplified by a plurality of transistors 11 to 14 and is output from an output terminal 200 as an output signal.

[0015] Each of the first transistor 11 to the fourth transistor 14 is an element that receives an input signal from the input terminal 100 at a gate node to which the gate electrode is connected, receives a drain voltage at a drain node to which the drain electrode is connected, and has a source node to which the source electrode is connected and grounded at a ground potential node, and amplifies the input signal input from the input terminal 100.

[0016] The gate widths of the first transistor 11 to the fourth transistor 14 are the same, and are set to 1 mm, for example. The gate width of the first transistor 11 to the fourth transistor 14 does not have to be 1 mm, and each of them may have a different gate width.

[0017] Each of the first transistor 11 to the fourth transistor 14 is a field effect transistor (FET), and is a GaN FET. In the first embodiment, the operation class of each of the first to fourth transistors 11 to 14 will be described as Class B operation, but Class A or Class C operation may also be used. In addition, since the gate bias voltages applied to the gate potentials of the first transistor 11 to the fourth transistor 14 can be individually adjusted to different voltage values, the operating classes of the first transistor 11 to the fourth transistor 14 may be made different.

[0018] The gate line 2 electrically connects the input terminal 100 and one end of the termination resistor 7 . The gate line 2 has a plurality of gate connection points 21 to 24 electrically connected to the gate nodes of the first transistor 11 to the fourth transistor 14, respectively. The gate line 2 has a plurality of inter-gate lines 201 to 205 connected between adjacent gate connection points.

[0019] The first inter-gate line 201 is connected between the input terminal 100 and the first gate connection point 21 . The second inter-gate line 202 is connected between the first gate connection point 21 and the second gate connection point 22 . The third inter-gate line 203 is connected between the second gate node 22 and the third gate node 23 .

[0020] The fourth inter-gate line 204 is connected between the third gate node 23 and the fourth gate node 24 . The fifth inter-gate line 205 is connected between the fourth gate connection point 24 and one end of the termination resistor 7 .

[0021] The first inter-gate line 201 to the fifth inter-gate line 205 are each a series circuit of gate-side transmission lines 20a1 to 20a5 and capacitors 20b1 to 20b5. Each of the capacitors 20b1 to 20b5 cuts off a direct current between adjacent gate connection points to which it is electrically connected.

[0022] Each of the gate-side transmission lines 20a1 to 20a5 is a microstrip line mounted on a GaN MMIC. Each of the gate-side transmission lines 20a1 to 20a5 is formed in a meander line shape in the GaN MMIC and functions as an inductor. Each of the capacitors 20b1 to 20b5 is a MIM (Metal Insulator Metal) capacitor mounted on a GaN MMIC.

[0023] The drain line 3 electrically connects between the drain node of the first transistor 11 and the output terminal 200 . The drain line 3 has a plurality of drain connection points 31 to 34 electrically connected to the drain nodes of the first transistor 11 to the fourth transistor 14, respectively. The line for drain 3 has a plurality of inter-drain lines 301 to 304 connected between adjacent drain connection points.

[0024] The first inter-drain line 301 is connected between the first drain node 31 and the second drain node 32 . The second inter-drain line 302 is connected between the second drain node 32 and the third drain node 33 . The third inter-drain line 303 is connected between the third drain node 33 and the fourth drain node 34 . The fourth inter-drain line 304 is connected between the fourth drain node 34 and the output terminal 200 .

[0025] The first inter-drain line 301 to the fourth inter-drain line 304 are each a series circuit of drain-side transmission lines 30a1 to 30a4 and capacitors 30b1 to 30b4. Each of the capacitors 30b1 to 30b4 cuts off a direct current between adjacent drain connection points to which it is electrically connected.

[0026] Each of the drain side transmission lines 30a1 to 30a4 is a microstrip line mounted on a GaN MMIC. Each of the drain side transmission lines 30a1 to 30a4 is formed in a meander line shape in the GaN MMIC and functions as an inductor. Each of the capacitors 30b1 to 30b4 is an MIM capacitor mounted on a GaN MMIC.

[0027] The first gate input circuit 41 to the fourth gate input circuit 44 are provided corresponding to the first transistor 11 to the fourth transistor 14, respectively. The first gate input circuit 41 to the fourth gate input circuit 44 are connected between the gate nodes of the corresponding first transistor 11 to fourth transistor 14 and the corresponding gate connection points 21 to 24 of the gate line 2, respectively.

[0028] The first gate input circuit 41 to the fourth gate input circuit 44 are parallel circuits of resistors 4a1 to 4a4 and capacitors 4b1 to 4b4, respectively. Each of resistors 4a1 to 4a4 is a resistor mounted on a GaN MMIC. Each of the capacitors 4b1 to 4b4 is an MIM capacitor mounted on a GaN MMIC.

[0029] In each of the first gate input circuit 41 to the fourth gate input circuit 44, the capacitors 4b1 to 4b4 are provided to increase the cutoff frequency, but they do not necessarily have to be provided. That is, the first gate input circuit 41 to the fourth gate input circuit 44 may each include only the resistors 4a1 to 4a4.

[0030] The first gate bias voltage application circuit 51 to the fourth gate bias voltage application circuit 54 are provided corresponding to the first transistor 11 to the fourth transistor 14, respectively. The first gate bias voltage application circuit 51 to the fourth gate bias voltage application circuit 54 are connected between the corresponding gate voltage application nodes 81 to 84 and the corresponding gate connection points 21 to 24 of the gate line 2, respectively.

[0031] The first gate bias voltage application circuit 51 has a first gate voltage application inductor 5a1 connected between the first gate voltage application node 81 and the first gate connection point 21, and a first capacitor 5b1 connected between the first gate voltage application node 81 and the ground potential node. The second gate bias voltage application circuit 52 has a second gate voltage application inductor 5a2 connected between the second gate voltage application node 82 and the second gate connection point 22, and a second capacitor 5b2 connected between the second gate voltage application node 82 and the ground potential node.

[0032] The third gate bias voltage application circuit 53 has a third gate voltage application inductor 5a3 connected between the third gate voltage application node 83 and the third gate connection point 23, and a third capacitor 5b3 connected between the third gate voltage application node 83 and the ground potential node. The fourth gate bias voltage application circuit 54 has a fourth gate voltage application inductor 5a4 connected between the fourth gate voltage application node 84 and the fourth gate connection point 24, and a fourth capacitor 5b4 connected between the fourth gate voltage application node 84 and the ground potential node.

[0033] The first gate voltage application node 81 to the fourth gate voltage application node 84 are applied with corresponding gate bias voltages Vg1 to Vg4, respectively. The capacitors 20b1 to 20b5 of the inter-gate lines 201 to 205 in the gate line 2 block DC current between the input terminal 100 and the gate connection point 21 in the gate line 2, between the gate connection points 21 to 24 in the gate line 2, and between the gate connection point 24 in the gate line 2 and one end of the termination resistor 7.

[0034] As a result, gate bias voltages Vg1 to Vg4 are individually applied to the gate nodes of the first transistor 11 to the fourth transistor 14 from the corresponding gate voltage application nodes 81 to 84, respectively, via the corresponding gate voltage application inductors 5a1 to 5a4 and the gate input circuits 41 to 44.

[0035] Since the gate bias voltages Vg1 to Vg4 can be adjusted individually, the operating points of the first to fourth transistors 11 to 14 can be adjusted individually, thereby improving the output and efficiency as a distributed amplifier. Furthermore, since the gate bias voltages Vg1 to Vg4 can be adjusted individually, the operation class of each of the first transistor 11 to the fourth transistor 14 can be changed from class B operation to class A operation or class C operation individually.

[0036] The relationship between the gate bias voltages Vg1 to Vg4 is expressed by the following formula (1). Vg1 ≧ Vg2 ≧ Vg3 ≧ Vg4 (1) That is, in the adjacent transistors 1, the gate bias voltage Vg for the transistor 1 located on the input terminal 100 side is set to be equal to or higher than the gate bias voltage Vg for the transistor 1 located on the output terminal 200 side.

[0037] In particular, it is more preferable to increase the voltage value in sequence from the fourth gate bias voltage Vg4 to the first gate bias voltage Vg1, as shown in the following formula (2). Vg1>Vg2>Vg3>Vg4(2)

[0038] Each of the gate voltage application inductors 5a1 to 5a4 is formed in a spiral shape in the GaN MMIC and functions as an inductor. Each of the capacitors 5b1 to 5b4 is an MIM capacitor mounted on a GaN MMIC.

[0039] The first drain voltage supply circuit 61 to the fourth drain voltage supply circuit 64 are provided corresponding to the first transistor 11 to the fourth transistor 14, respectively. The first drain voltage supply circuit 61 to the fourth drain voltage supply circuit 64 are connected between the corresponding drain voltage supply nodes 91 to 94 and the corresponding drain connection points 31 to 34 of the drain line 3, respectively.

[0040] The first drain voltage supply circuit 61 has a first drain voltage supply inductor 6a1 connected between a first drain voltage supply node 91 and a first drain connection point 31, and a first capacitor 6b1 connected between the first drain voltage supply node 91 and a ground potential node. The second drain voltage supply circuit 62 has a second drain voltage supply inductor 6a2 connected between the second drain voltage supply node 92 and the second drain connection point 32, and a second capacitor 6b2 connected between the second drain voltage supply node 92 and the ground potential node.

[0041] The third drain voltage supply circuit 63 has a third drain voltage supply inductor 6a3 connected between the third drain voltage supply node 93 and the third drain connection point 33, and a third capacitor 6b3 connected between the third drain voltage supply node 93 and the ground potential node. The fourth drain voltage supply circuit 64 has a fourth drain voltage supply inductor 6a4 connected between the fourth drain voltage supply node 94 and the fourth drain connection point 34, and a fourth capacitor 6b4 connected between the fourth drain voltage supply node 94 and the ground potential node.

[0042] The first drain voltage supply node 91 to the fourth drain voltage supply node 94 are supplied with corresponding drain supply voltages Vd1 to Vd4, respectively. By the capacitors 30b1-30b5 of the inter-drain lines 301-305 in the drain line 3, DC currents between the drain nodes 31-34 in the drain line 3 and between the drain node 34 in the drain line 3 and the output terminal 200 are cut off.

[0043] As a result, drain supply voltages Vd1 to Vd4 are individually applied to the drain nodes of the first to fourth transistors 11 to 14 from the corresponding drain voltage supply nodes 91 to 94, respectively, via the corresponding drain voltage supply inductors 6a1 to 6a4.

[0044] Since the drain supply voltages Vd1 to Vd4 can be adjusted individually, the operating points of the first to fourth transistors 11 to 14 can be adjusted individually, thereby improving the output and efficiency as a distributed amplifier. Furthermore, since the drain supply voltages Vd1 to Vd4 can be adjusted individually, it is possible to adjust the on-resistance of each of the first transistor 11 to the fourth transistor 14. In particular, by sequentially decreasing the voltage value from the fourth drain supply voltage Vd4 to the first drain supply voltage Vd1, the on-resistance sequentially decreases from the fourth transistor 14 to the first transistor 11, thereby improving the drain efficiency of the first transistor 11 to the fourth transistor 14 and reducing the difference in drain efficiency between adjacent transistors 11.

[0045] The relationship between the drain supply voltages Vd1 to Vd4 is expressed by the following equation (3). Vd1≦Vd2≦Vd3≦Vd4(3) That is, in adjacent transistors 1, the drain supply voltage Vd for the transistor 1 located on the input terminal 100 side is set to be equal to or lower than the drain supply voltage Vd for the transistor 1 located on the output terminal 200 side.

[0046] In particular, it is more preferable to decrease the voltage value in sequence from the fourth drain supply voltage Vd4 to the first drain supply voltage Vd1, as shown in the following formula (4). Vd1 <Vd2<Vd3<Vd4(4)

[0047] Each of the drain voltage supply inductors 6a1 to 64 is formed in a spiral shape in the GaN MMIC and functions as an inductor. Each of the capacitors 6b1 to 6b4 is a MIM capacitor mounted on a GaN MMIC. The other end of the termination resistor 7 is connected to the ground node.

[0048] Next, the operation of the distributed amplifier according to the first embodiment will be described. When an input signal consisting of a high-frequency signal is input to the input terminal 100 , the input signal propagates through the first inter-gate line 201 in the gate line 2 and reaches the first gate connection point 21 . The input signal that reaches the first gate connection point 21 is distributed to the first gate input circuit 41 and the second inter-gate line 202 .

[0049] The input signal distributed to the first gate input circuit 41 is biased to a first gate bias voltage Vg 1 supplied from a first gate bias voltage application circuit 51 and input to the gate node of the first transistor 11 . The first transistor 11 amplifies an input signal biased to the first gate bias voltage Vg1 and outputs it as an output signal to the first drain connection point 31 in the drain line 3 to which the first drain supply voltage Vd1 is supplied from the first drain voltage supply circuit 61. The output signal output to the first drain connection point 31 propagates through the first inter-drain line 301 in the line for drain 3 and reaches the second drain connection point 32 .

[0050] The input signal distributed to the second inter-gate line 202 propagates through the second inter-gate line 202 and reaches the second gate connection point 22 . The input signal that reaches the second gate connection point 22 is distributed to the second gate input circuit 42 and the third inter-gate line 203 .

[0051] The input signal distributed to the second gate input circuit 42 is biased to a second gate bias voltage Vg2 supplied from a second gate bias voltage application circuit 52 and input to the gate node of the second transistor 12. The second transistor 12 amplifies the input signal biased to the second gate bias voltage Vg2 and outputs it as an output signal to the second drain connection point 32 in the drain line 3 to which the second drain supply voltage Vd2 is supplied from the second drain voltage supply circuit 62.

[0052] The output signal output to the second drain node 32 is combined at the second drain node 32 of the line for drain 3 with the output signal from the first transistor 11 propagated through the first inter-drain line 301 . The composite signal obtained by combining the output signal from the first transistor 11 and the output signal from the second transistor 12 propagates through the second inter-drain line 302 in the drain line 3 and reaches the third drain connection point 33.

[0053] The input signal distributed to the third inter-gate line 203 propagates through the third inter-gate line 203 and reaches the third gate connection point 23 . The input signal that reaches the third gate connection point 23 is distributed to the third gate input circuit 43 and the fourth inter-gate line 204 .

[0054] The input signal distributed to the third gate input circuit 43 is biased to a third gate bias voltage Vg3 supplied from a third gate bias voltage application circuit 53 and input to the gate node of the third transistor 13. The third transistor 13 amplifies the input signal biased to the third gate bias voltage Vg3 and outputs it as an output signal to the third drain connection point 33 in the drain line 3 to which the third drain supply voltage Vd3 is supplied from the third drain voltage supply circuit 63.

[0055] The output signal output to the third drain connection point 33 is combined at the third drain connection point 33 of the drain line 3 with a composite signal obtained by combining the output signal from the first transistor 11 and the output signal from the second transistor 12 propagated through the second inter-drain line 302. The composite signal obtained by combining the output signals of the first transistor 11 to the third transistor 13 propagates through the third inter-drain line 303 in the drain line 3, and reaches the fourth drain connection point .

[0056] The input signal distributed to the fourth inter-gate line 204 propagates through the fourth inter-gate line 204 and reaches the fourth gate connection point 24 . The input signal that reaches the fourth gate connection point 24 is distributed to the fourth gate input circuit 44 and the fifth inter-gate line 205 .

[0057] The input signal distributed to the fourth gate input circuit 44 is biased to a fourth gate bias voltage Vg4 supplied from a fourth gate bias voltage application circuit 54 and input to the gate node of the fourth transistor 14. The fourth transistor 14 amplifies the input signal biased to the fourth gate bias voltage Vg4 and outputs it as an output signal to the fourth drain connection point 34 in the drain line 3 to which the fourth drain supply voltage Vd4 is supplied from the fourth drain voltage supply circuit 64.

[0058] The output signal output to the fourth drain connection point 34 is combined at the fourth drain connection point 34 of the drain line 3 with a composite signal obtained by combining the output signals of the first transistor 11 to the third transistor 13 propagated through the third inter-drain line 303. A composite signal obtained by combining the output signals of the first transistor 11 to the fourth transistor 14 is propagated through the fourth inter-drain line 304 in the drain line 3 , and is output from the output terminal 200 . The input signal distributed to the fifth inter-gate line 205 propagates through the fifth inter-gate line 205 and is terminated by the termination resistor 7 .

[0059] In this manner, the first transistor 11 to the fourth transistor 14 each operate by the corresponding drain supply voltages Vd1 to Vd4 to individually amplify the input signals that have been individually gate-biased by the corresponding gate bias voltages Vg1 to Vg4, and the output signals amplified by the first transistor 11 to the fourth transistor 14 are combined and output to the output terminal 200.

[0060] Next, the operating characteristics of the distributed amplifier according to the first embodiment will be described. First, the static characteristics and load line (VI characteristics) of two adjacent transistors 1 will be described when the gate bias voltage Vg applied to the gate voltage application node 8 is the same gate bias voltage Vg and the drain supply voltage Vd supplied to the drain voltage supply node 9 is the same drain supply voltage Vdd.

[0061] The two adjacent transistors 1 are of the same size, that is, have the same gate width of 1 mm, and are intended to operate in class B mode. In addition, the instantaneous maximum drain current Imax of the drain current Ids flowing through each of two adjacent transistors 1 is set to be the same. As an example, the drain supply voltage Vdd was set to 30V, and the gate bias voltage Vg was set to -2.7V. An input signal consisting of a high-frequency signal with a frequency of 12 GHz was input to the input terminal 100 .

[0062] Under these conditions, the distributed amplifier was operated and the static characteristics and load lines of the two adjacent transistors were investigated, yielding the results shown in Figure 2. In FIG. 2, the horizontal axis indicates the drain voltage Vds, the vertical axis indicates the drain current Ids, the dashed line indicates the static characteristics, and the solid line A 01 is the load line (VI characteristic) of transistor 1 on the input terminal side, and the waveform B is shown by the solid line. 01 is the source node of transistor 1 on the input terminal side (ground potential ) Voltage swing Vds of the drain node 01, dashed line A 02 is the load line (VI characteristic) of transistor 1 on the output terminal side, and the waveform B is shown by the dashed line. 02 is the source node of transistor 1 on the output terminal side (ground potential ) Voltage swing Vds of the drain node 02 Shows.

[0063] As can be seen from FIG. 2, the voltage amplitude is Vds 01 <Vds 02 , the instantaneous drain voltage when the drain current is maximum is Vmin 01 >Vmin 02 , on-resistance is Ron 01 >Ron 02 The load corresponding to the inverse of the slope of the load line is RL 01 <RL 02 This is the relationship. The suffix 01 shown here indicates the transistor 1 on the input terminal side, and the suffix 02 indicates the transistor 1 on the output terminal side.

[0064] The above relationship is because the output signal amplified by the transistor 1 on the input terminal side and the output signal amplified by the transistor 1 on the output terminal side are combined at the drain connection point of the drain line 3 to which the drain node of the transistor 1 on the output terminal side is connected, so the voltage amplitude Vds of the transistor 1 on the output terminal side 02 is the voltage amplitude Vds of transistor 1 on the input terminal side 01 This can also be understood from the fact that it becomes larger.

[0065] Moreover, the output power Pout and the drain efficiency DE of the transistor can be expressed by the following equations (5) and (6), respectively. TIFF0007625154000001.tif20166 TIFF0007625154000002.tif21166

[0066] In the above equations (5) and (6), Vdd is the drain supply voltage supplied to the transistor 1, Ron is the on-resistance value of the transistor 1, and RL is the resistance value of the load. As can be seen from the above formula (6), the drain efficiency DE decreases as the load resistance RL decreases and as the on-resistance Ron increases.

[0067] In the distributed amplifier of the first embodiment including the first transistor 11 to the fourth transistor 14 shown in FIG. 1, the drain supply voltages Vd1 to Vd4 supplied to the first drain voltage supply node 91 to the fourth drain voltage supply node 94, respectively, are set to the same drain supply voltage Vdd, the gate bias voltages Vg1 to Vg4 applied to the first gate voltage application node 81 to the fourth gate voltage application node 84, respectively, are set to the same gate bias voltage Vg, and an input signal consisting of a high-frequency signal with a frequency of 12 GHz is input to the input terminal 100. The load lines (VI characteristics) of the first transistor 11 to the fourth transistor 14 were investigated, and the result shown in FIG. 3 was obtained.

[0068] The first transistor 11 to the fourth transistor 14 are of the same size, that is, have the same gate width of 1 mm, and are intended to operate in class B mode. As an example, the drain supply voltage Vdd is set to 30V, and the gate bias voltage Vg is set to -2.7V.

[0069] In FIG. 3, the horizontal axis indicates the drain voltage, the vertical axis indicates the drain current, and the solid curve E 01 is the load line (VI characteristic) of the first transistor 11, and the dashed curve E 02 is the load line (VI characteristic) of the second transistor 12, and the curve E shown by the dashed line 03 is a load line (VI characteristic) of the third transistor 13, and is a curve E 04 4 shows the load line (VI characteristics) of the fourth transistor 14.

[0070] In addition, the gate bias voltages Vg1 to Vg4 applied to the first gate voltage application node 81 to the fourth gate voltage application node 84, respectively, were set to the same gate bias voltage Vg, the drain supply voltages Vd1 to Vd4 supplied to the first drain voltage supply node 91 to the fourth drain voltage supply node 94, respectively, were set to the same drain supply voltage Vdd, and the frequency of the input signal input to the input terminal 100 was changed from 2.5 GHz to 13 GHz. In response to this, the drain efficiency of each of the first transistor 11 to the fourth transistor 14 was investigated, and the result shown in FIG. 4 was obtained.

[0071] The first transistor 11 to the fourth transistor 14 are of the same size, that is, have the same gate width of 1 mm, and are intended to operate in class B mode. As an example, the gate bias voltage Vg is set to −2.7V, and the drain supply voltage Vdd is set to 30V.

[0072] In FIG. 4, the horizontal axis indicates the frequency of the input signal, the vertical axis indicates the drain efficiency, and the solid curve F 01 is the drain efficiency of the first transistor 11, and the dashed curve F 02 is the drain efficiency of the second transistor 12, and the curve F shown by the dashed line 03 is the drain efficiency of the third transistor 13, and the curve F 04 denotes the drain efficiency of the fourth transistor 14.

[0073] Moreover, the results of investigation of the drain efficiency Ea of the entire distributed amplifier are shown as a dashed line in FIG. As is clear from FIG. 9, in the input signal frequency band of 2.5 GHz to 13 GHz, the minimum value of the drain efficiency Ea of the entire distributed amplifier was 34.5%.

[0074] Next, the static characteristics, load line (VI characteristics), and drain efficiency of the first transistor 11 to the fourth transistor 14 will be described when making full use of the feature in the distributed amplifier of embodiment 1 that the drain supply voltages Vd1 to Vd4 can be individually adjusted and supplied to the drain nodes of the first transistor 11 to the fourth transistor 14 due to the DC cutting function of the capacitors 30b1 to 30b4 of the inter-drain lines 301 to 304 in the drain line 3, and that the gate bias voltages Vg1 to Vg4 can be individually adjusted and applied to the gate nodes of the first transistor 11 to the fourth transistor 14 due to the DC cutting function of the capacitors 20b1 to 20b5 of the inter-gate lines 201 to 205 in the gate line 2.

[0075] First, for two adjacent transistors 1, the static characteristics and load line (VI characteristics) of the transistor 1 on the input side and the transistor 1 on the output side investigated under the following conditions will be described. The drain supply voltage supplied to the drain voltage supply node 9 for the output transistor 1 is the drain supply voltage Vd 02 The drain supply voltage supplied to the drain voltage supply node 9 of the input-side transistor 1 is Vd 02 The drain supply voltage Vd is the smaller voltage value. 01 Let us assume that.

[0076] In addition, the gate bias voltage applied to the gate voltage application node 8 of the output side transistor 1 is the gate bias voltage Vg 02 The gate bias voltage applied to the gate voltage application node 8 of the input side transistor 1 is Vg 02 The gate bias voltage Vg is the larger voltage value. 01 Let us assume that. The two adjacent transistors 1 are of the same size, that is, have the same gate width of 1 mm, and are intended to operate in class B mode.

[0077] In addition, the instantaneous maximum drain current Imax of the drain current Ids flowing through each of two adjacent transistors 1 is set to be the same. As an example, the drain supply voltage Vd 02 30V (Vdd), drain supply voltage Vd 01 28V, gate bias voltage Vg 02 -2.7V(Vg), gate bias voltage Vg 01 was set to -2.5V. An input signal consisting of a high-frequency signal with a frequency of 12 GHz was input to the input terminal 100 .

[0078] Under these conditions, the distributed amplifier was operated and the static characteristics and load line (VI characteristics) of two adjacent transistors were investigated, and the results shown in Figure 5 were obtained. In Figure 5, the horizontal axis represents the drain voltage Vds, the vertical axis represents the drain current Ids, the dashed line represents the static characteristics, the dashed line A2 represents the load line (VI characteristics) of the transistor 1 on the output terminal side, and the dashed line A1 represents the load line (VI characteristics) of the transistor 1 on the input terminal side.

[0079] In addition, the solid line A 01 is the same drain supply voltage Vd 02 (Vdd), with the same gate bias voltage Vg 02 (Vg) is the load line (VI characteristic) of the input side transistor 1. 2 Line A shown in solid line 01 This is the same as the load line (VI characteristic) of transistor 1 on the input terminal side shown by Also, the dashed line A2 in FIG. 2 Line A shown by a dashed line in 02 This is the same as the load line (VI characteristic) of transistor 1 on the output terminal side shown by

[0080] As can be seen from FIG. 5, the load line (VI characteristic) A1 of the transistor 1 on the input side is a drain supply voltage Vd 02 Load line (VI characteristic) A of transistor 1 on the input side (Vdd) 01Drain supply voltage Vd 02 and the drain supply voltage Vd 01 The difference between the load and the load line is shown as a shift toward the origin.

[0081] The instantaneous drain voltage Vmin1 when the drain current of the input-side transistor 1 is at its maximum is taken as the instantaneous drain voltage Vmin2 (Vmin 02 ) can be approximated. Therefore, the on-resistance Ron1 of the input-side transistor 1 is the drain supply voltage Vd 02 (Vdd) is the on-resistance Ron of the input transistor 1 01 The on-resistance of the transistor 1 on the output terminal side is smaller than Ron2 (Ron 02 )

[0082] As a result, the on-resistance Ron1 of the input side transistor 1 becomes 01 As a result of this being smaller, the drain efficiency of the input-side transistor 1 is improved, as can be seen from the above equation (6). By improving the drain efficiency of the transistor 1 on the input side, the difference between the drain efficiency of the transistor 1 on the input side and the drain efficiency of the transistor 1 on the output terminal side can be reduced, and the drain efficiency of the transistor 1 on the input side can be made closer to the drain efficiency of the transistor 1 on the output terminal side.

[0083] In short, the relationship between two adjacent transistors can be as follows: That is, the voltage amplitude can be set to Vds1 ≈ Vds2, the instantaneous drain voltage when the drain current is at its maximum to Vmin1 ≈ Vmin2, the on-resistance to Ron1 ≈ Ron2, and the load equivalent to the inverse of the slope of the load line to RL1 ≈ RL2. The subscript 1 here indicates the transistor 1 on the input terminal side, and the subscript 2 indicates the transistor 1 on the output terminal side. As a result, the drain efficiency of the input - side transistor 1 can be made closer to the drain efficiency of the output - terminal - side transistor 1, and a decrease in the drain efficiency of the input - side transistor 1 by can be prevented.

[0084] In the distributed amplifier according to Embodiment 1 including the first transistor 11 to the fourth transistor 14 shown in FIG. 1, the drain supply voltages Vd1 to Vd4 respectively supplied from the first drain - voltage supply node 91 to the fourth drain - voltage supply node 94 are made to decrease in order (Vd1 < Vd2 < Vd3 < Vd4) from the fourth drain - voltage supply node 94 located on the output - terminal 200 side to the first drain - voltage supply node 91 located on the input - terminal 100 side, and the gate - bias voltages Vg1 to Vg4 respectively applied from the first gate - voltage application node 81 to the fourth gate - voltage application node 84 are made to increase in order (Vg1 > Vg2 > Vg3 > Vg4) from the fourth gate - voltage application node 84 located on the output - terminal 200 side to the first gate - voltage application node 81 located on the input - terminal 100 side. When an input signal composed of a high - frequency signal with a frequency of 12 GHz is input to the input terminal 100, the load lines (V - I characteristics) of the first transistor 11 to the fourth transistor 14 were investigated, and the results shown in FIG. 7 were obtained.

[0085] The first transistor 11 to the fourth transistor 14 are of the same size, that is, the gate width is the same 1 mm, and the transistors operating in class - B operation are targeted. Also, as an example, as shown in FIG. 6, the drain supply voltage, Vd4 is set to 30 V, Vd3 is set to 28 V, Vd2 is set to 25 V, Vd1 is set to 20 V, and the gate - bias voltage, Vg4 is set to - 2.7 V, Vg3 is set to - 2.5 V, Vg2 is set to - 2.2 V, Vg1 is set to - 1.7 V.

[0086] In FIG. 7, the horizontal axis represents the drain voltage, the vertical axis represents the drain current, the curve E1 shown by the solid line is the load line (V-I characteristic) of the first transistor 11, the curve E2 shown by the broken line is the load line (V-I characteristic) of the second transistor 12, the curve E3 shown by the one-dot chain line is the load line (V-I characteristic) of the third transistor 13, and the curve E4 shown by the two-dot chain line is the load line (V-I characteristic) of the fourth transistor 14.

[0087] As understood from FIG. 7, the load lines (V-I characteristics) of the first transistor 11 to the third transistor 13 approach the axis of the drain current in the same manner as the load line (V-I characteristic) of the fourth transistor 14. That is, in the first transistor 11 to the third transistor 13, the instantaneous drain voltages Vmin1 to Vmin3 when the drain current becomes maximum approach the instantaneous drain voltage Vmin4 when the drain current becomes maximum in the fourth transistor 14.

[0088] In other words, the instantaneous drain voltages when the drain current becomes maximum in the first transistor 11 to the fourth transistor 14 have the relationship of Vmin1≒Vmin2≒Vmin3≒Vmin4, and the decrease in the drain efficiency of the first transistor 11 to the third transistor 13 can be suppressed, approaching the drain efficiency of the fourth transistor 14. As a result, it leads to an improvement in the drain efficiency of the entire distributed amplifier.

[0089] Also, when the drain supply voltages Vd1 to Vd4 supplied to the first drain voltage supply node 91 to the fourth drain voltage supply node 94 are set as Vd1 < Vd2 < Vd3 < Vd4, the gate bias voltages Vg1 to Vg4 applied to the first gate voltage application node 81 to the fourth gate voltage application node 84 are set as Vg1 > Vg2 > Vg3 > Vg4, and the frequency of the input signal input to the input terminal 100 is changed from 2.5 GHz to 13 GHz, the drain efficiencies of the first transistor 11 to the fourth transistor 14 were investigated, and the results shown in FIG. 8 were obtained.

[0090] The first transistor 11 to the fourth transistor 14 are of the same size, that is, the gate width is the same 1 mm, and the transistors operating in class B operation are targeted. Also, as an example, as shown in FIG. 6, the drain supply voltages, Vd4 was set to 30V, Vd3 to 28V, Vd2 to 25V, Vd1 to 20V, and the gate bias voltages, Vg4 to -2.7V, Vg3 to -2.5V, Vg2 to -2.2V, Vg1 to -1.7V.

[0091] In FIG. 8, the horizontal axis represents the frequency of the input signal, the vertical axis represents the drain efficiency, the curve F1 shown by the solid line is the drain efficiency of the first transistor 11, the curve F2 shown by the broken line is the drain efficiency of the second transistor 12, the curve F3 shown by the one-dot chain line is the drain efficiency of the third transistor 13, and the curve F4 shown by the two-dot chain line is the drain efficiency of the fourth transistor 14.

[0092] As understood from FIG. 8, over the wide band of 2.5 GHz to 13 GHz of the frequency of the input signal, the decrease in the drain efficiency of the first transistor 11 to the third transistor 13 can be suppressed, and the drain efficiency of the first transistor 11 to the third transistor 13 approaches the drain efficiency of the fourth transistor 14.

[0093] As a result, over the wide band of 2.5 GHz to 13 GHz of the frequency of the input signal, by sequentially decreasing the drain supply voltages Vd1 to Vd4 supplied from the fourth drain voltage supply node 94 located on the output terminal 200 side toward the first drain voltage supply node 91 located on the input terminal 100 side (Vd1 < Vd2 < Vd3 < Vd4), it leads to an improvement in the drain efficiency of the entire distributed amplifier.

[0094] That is, as shown by the solid line in FIG. 9 for the investigation result of the drain efficiency Eb of the entire distributed amplifier, in the band of 2.5 GHz to 13 GHz of the frequency of the input signal, the minimum value of the drain efficiency Eb of the entire distributed amplifier was 41.5%. As can be understood from the survey results shown in Fig. 9, when the drain supply voltages Vd1 to Vd4 supplied from the first drain voltage supply node 91 to the fourth drain voltage supply node 94 are in the relationship of Vd1 < Vd2 < Vd3 < Vd4, the drain efficiency Eb of the entire distributed amplifier is improved.

[0095] Furthermore, in the distributed amplifier according to Embodiment 1, an input signal having a frequency of 2.5 GHz to 13 GHz was input to the input terminal 100, and the output power output to the output terminal 200 was investigated. The survey results are shown in Fig. 10. In Fig. 10, the horizontal axis represents the frequency of the input signal input to the input terminal 100, and the vertical axis represents the output power output to the output terminal 200.

[0096] In Fig. 10, the curve Oa indicated by the broken line has the same gate bias voltages Vg1 to Vg4 applied from the first gate voltage application node 81 to the fourth gate voltage application node 84, and the drain supply voltages Vd1 to Vd4 supplied from the first drain voltage supply node 91 to the fourth drain voltage supply node 94 are the same drain supply voltage, and shows the output power output to the output terminal 200.

[0097] In Fig. 10, the curve Ob indicated by the solid line has the drain supply voltages Vd1 to Vd4 supplied from the first drain voltage supply node 91 to the fourth drain voltage supply node 94 in the relationship of Vd1 < Vd2 < Vd3 < Vd4, and the gate bias voltages Vg1 to Vg4 applied from the first gate voltage application node 81 to the fourth gate voltage application node 84 in the relationship of Vg1 > Vg2 > Vg3 > Vg4, and shows the output power output to the output terminal 200.

[0098] As is clear from Fig. 10, in the frequency band of 2.5 GHz to 13 GHz of the input signal, the minimum value of the output power Oa was 41.8 dBm, and the minimum value of the output power Ob was 42.0 dBm. As understood from the investigation results, by increasing the gate bias voltages Vg1 to Vg4 applied from the fourth gate voltage application node 84 located on the output terminal 200 side to the first gate voltage application node 81 located on the input terminal 100 side in order (Vg1 > Vg2 > Vg3 > Vg4) over a wide frequency band of 2.5 GHz to 13 GHz of the input signal, it leads to an improvement in the output power output from the output terminal 200 of the distributed amplifier.

[0099] The distributed amplifier according to Embodiment 1 includes a plurality of transistors 11 to 14 each having its source node grounded, and is a distributed amplifier in which the plurality of transistors 11 to 14 are connected in parallel by a drain line 3. The drain line 3 has a plurality of drain connection points 31 to 34 to which the drain nodes of the plurality of transistors 11 to 14 are electrically connected respectively, and a plurality of inter-drain lines 301 to 304 which are series circuits of drain-side transmission lines 30a1 to 30a4 and capacitors 30b1 to 30b4 connected between adjacent drain connection points. Since it includes a plurality of drain voltage supply circuits 61 to 64 each connected between a drain voltage supply node 91 to 94 and a corresponding drain connection point 31 to 34 of the drain line 3, the drain efficiency of the entire distributed amplifier is improved.

[0100] In particular, by decreasing the drain supply voltages Vd1 to Vd4 supplied from the fourth drain voltage supply node 94 located on the output terminal 200 side to the first drain voltage supply node 91 located on the input terminal 100 side in order (Vd1 < Vd2 < Vd3 < Vd4), it leads to an improvement in the drain efficiency of the entire distributed amplifier, specifically, over a wide frequency band of 2.5 GHz to 13 GHz of the input signal, an improvement in the drain efficiency of the entire distributed amplifier.

[0101] Furthermore, the distributed amplifier according to the first embodiment has a gate line 2 having a plurality of gate connection points 21-24 electrically connected to the gate nodes of the plurality of transistors 11-14, a plurality of inter-gate lines 201-204 which are series circuits of gate-side transmission lines 20a1-20a4 and capacitors 20b1-20b4, each of which is connected between adjacent gate connection points, and has a plurality of gate bias voltage application circuits 51-54 which are connected between the gate voltage application nodes 81-84 and the corresponding gate connection points 21-24 of the gate line 2, respectively. Therefore, by increasing the gate bias voltages Vg1-Vg4 applied from the fourth gate voltage application node 84 located on the output terminal 200 side to the first gate voltage application node 81 located on the input terminal 100 side in order (Vg1>Vg2>Vg3>Vg4), this leads to an improvement in the output power output to the output terminal 200 of the distributed amplifier over a wide input signal frequency band of 2.5 GHz to 13 GHz.

[0102] Furthermore, the distributed amplifier according to the first embodiment includes a plurality of gate input circuits 41-44 each of which is connected between the gate nodes of the corresponding transistors 11-14 and the corresponding gate connection points 21-24 of the gate line 2 and is made up of a parallel circuit of resistors 4a1-4a4 and capacitors 4b1-4b4. This makes it possible to increase the cutoff frequency of the input signal input to the gate nodes of the transistors 11-14.

[0103] Although the distributed amplifier of embodiment 1 has been described using as an example a distributed amplifier implemented in a GaN MMIC, it may also be implemented in a GaAs MMIC, or may be configured by discretely constructing the individual components.

[0104] Embodiment 2 A distributed amplifier according to a second embodiment will be described with reference to FIG. The distributed amplifier of the first embodiment has a first gate input circuit 41 to a fourth gate input circuit 44 connected between the gate nodes of the first transistor 11 to the fourth transistor 14 and the corresponding first gate connection point 21 to the fourth gate connection point 24 of the gate line 2.

[0105] In contrast, the distributed amplifier of embodiment 2 differs from the distributed amplifier of embodiment 1 in that the gate nodes of the first transistor 11 to the fourth transistor 14 are directly connected to the corresponding first gate connection point 21 to fourth gate connection point 24 of the gate line 2 by wiring paths, but is otherwise the same. In FIG. 11, the same reference numerals as in FIG. 1 indicate the same or corresponding parts. The distributed amplifier according to the second embodiment has the same effects as the distributed amplifier according to the first embodiment.

[0106] Embodiment 3 A distributed amplifier according to a third embodiment will be described with reference to FIG. The distributed amplifier according to the third embodiment is different from the distributed amplifier according to the first embodiment in the arrangement of the gate line 2, the gate input circuits 41-44, and the gate bias voltage application circuits 51-54, but is otherwise the same. Therefore, the following description will focus mainly on the gate line 2, the first to fourth DC blocking capacitors 20b2 to 20b5, and the gate bias voltage application circuits 51 to . In FIG. 12, the same reference numerals as in FIG. 1 indicate the same or corresponding parts.

[0107] The gate line 2 electrically connects the input terminal 100 and one end of the termination resistor 7 . The gate line 2 has a plurality of gate connection points 21 to 24 electrically connected to the gate nodes of the first transistor 11 to the fourth transistor 14, respectively. The gate line 2 has a plurality of inter-gate lines 201 to 205 connected between adjacent gate connection points.

[0108] The first inter-gate line 201 is connected between the input terminal 100 and the first gate connection point 21, and is a series circuit of a gate-side transmission line 20a1 and a capacitor 20b. The second inter-gate line 202 is connected between the first gate connection point 21 and the second gate connection point 22, and is a gate side transmission line 20a2. The third inter-gate line 203 is connected between the second gate connection point 22 and the third gate connection point 23, and is a gate side transmission line 20a3.

[0109] The fourth inter-gate line 204 is connected between the third gate connection point 23 and the fourth gate connection point 24, and is a gate side transmission line 20a4. The fifth inter-gate line 205 is connected between the fourth gate connection point 24 and one end of the terminating resistor 7, and is a gate side transmission line 20a5.

[0110] Each of the gate-side transmission lines 20a1 to 20a5 is a microstrip line mounted on a GaN MMIC. Each of the gate-side transmission lines 20a1 to 20a5 is formed in a meander line shape in the GaN MMIC and functions as an inductor.

[0111] The first to fourth DC blocking capacitors 20b2 to 20b5 are provided corresponding to the first to fourth transistors 11 to 14, respectively. The first to fourth DC blocking capacitors 20b2 to 20b5 are connected between the gate nodes of the corresponding first to fourth transistors 11 to 14 and the corresponding gate connection points 21 to 24 of the gate line 2, respectively.

[0112] Each of the first DC blocking capacitor 20b2 to the fourth DC blocking capacitor 20b5 has a function of DC blocking between the gate node of the corresponding first transistor 11 to the corresponding fourth transistor 14 and the gate line 2, and also has a function as the capacitors 4b1 to 4b4 in the gate input circuits 41 to 44 in the first embodiment. Each of the first DC blocking capacitor 20b2 to the fourth DC blocking capacitor 20b5 is a MIM capacitor implemented in a GaN MMIC.

[0113] The first gate bias voltage application circuit 51 to the fourth gate bias voltage application circuit 54 are provided corresponding to the first transistor 11 to the fourth transistor 14, respectively. The first gate bias voltage application circuit 51 to the fourth gate bias voltage application circuit 54 are connected between the corresponding gate voltage application nodes 81 to 84 and the gate nodes of the corresponding transistors 11 to 14, respectively.

[0114] The first gate bias voltage application circuit 51 has a first gate voltage application inductor 5a1 connected between a first gate voltage application node 81 and the gate node of the first transistor 11, and a first capacitor 5b1 connected between the first gate voltage application node 81 and a ground potential node. The second gate bias voltage application circuit 52 has a second gate voltage application inductor 5a2 connected between a second gate voltage application node 82 and the gate node of the second transistor 12, and a second capacitor 5b2 connected between the second gate voltage application node 82 and the ground potential node.

[0115] The third gate bias voltage application circuit 53 has a third gate voltage application inductor 5a3 connected between a third gate voltage application node 83 and the gate node of the third transistor 13, and a third capacitor 5b3 connected between the third gate voltage application node 83 and the ground potential node. The fourth gate bias voltage application circuit 54 has a fourth gate voltage application inductor 5a4 connected between a fourth gate voltage application node 84 and the gate node of the fourth transistor 14, and a fourth capacitor 5b4 connected between the fourth gate voltage application node 84 and the ground potential node.

[0116] The first gate voltage application node 81 to the fourth gate voltage application node 84 are applied with corresponding gate bias voltages Vg1 to Vg4, respectively. The first gate bias voltage application circuit 51 to the fourth gate bias voltage application circuit 54 connected to the gate nodes of the corresponding first transistor 11 to fourth transistor 14 are DC-isolated from the gate line 2 by the first DC-blocking capacitor 20b2 to the fourth DC-blocking capacitor 20b5, respectively.

[0117] As a result, gate bias voltages Vg1 to Vg4 are individually applied to the gate nodes of the first to fourth transistors 11 to 14 from the corresponding gate voltage application nodes 81 to 84, respectively, via the corresponding gate voltage application inductors 5a1 to 5a4.

[0118] Since the gate bias voltages Vg1 to Vg4 can be adjusted individually, the operating points of the first to fourth transistors 11 to 14 can be adjusted individually, thereby improving the output and efficiency as a distributed amplifier. Furthermore, since the gate bias voltages Vg1 to Vg4 can be adjusted individually, the operation class of each of the first transistor 11 to the fourth transistor 14 can be changed from class B operation to class A operation or class C operation individually.

[0119] The relationship between the gate bias voltages Vg1 to Vg4 is the same as in the first embodiment, Vg1≧Vg2≧Vg3≧Vg4, and more preferably, Vg1>Vg2>Vg3>Vg4. Each of the gate voltage application inductors 5a1 to 54 is formed in a spiral shape in the GaN MMIC and functions as an inductor. Each of the capacitors 5b1 to 5b4 is a MIM capacitor implemented in a GaN MMIC.

[0120] Similar to the distributed amplifier according to Embodiment 1, the distributed amplifier according to Embodiment 3 includes a plurality of drain voltage supply circuits 61 to 64 each connected between the drain voltage supply nodes 91 to 94 and the corresponding drain connection points 31 to 34 of the drain line 3. Therefore, the drain efficiency of the entire distributed amplifier is improved.

[0121] In particular, similar to the distributed amplifier according to Embodiment 1, the distributed amplifier according to Embodiment 3 decreases the drain supply voltages Vd1 to Vd4 supplied from the fourth drain voltage supply node 94 located on the output terminal 200 side toward the first drain voltage supply node 91 located on the input terminal 100 side in order (Vd1 < Vd2 < Vd3 < Vd4). This leads to an improvement in the drain efficiency of the entire distributed amplifier. Specifically, it leads to an improvement in the drain efficiency of the entire distributed amplifier over a wide frequency band of 2.5 GHz to 13 GHz of the input signal.

[0122] Also, in the distributed amplifier according to the embodiment 3 Each of the gate - to - gate lines 202 to 205 in the gate line 2 is a gate - side transmission line 20a2 to 20a5. The distributed amplifier according to the embodiment includes a plurality of DC - blocking capacitors 20b2 to 20b5 each connected between the gate nodes of the corresponding transistors 11 to 14 and the corresponding gate connection points 21 to 24 of the gate line 2, and a plurality of gate bias voltage application circuits 51 to 54 each connected between the corresponding gate voltage application nodes 81 to 84 and the gate nodes of the corresponding transistors 11 to 14. Therefore, by increasing the gate bias voltages Vg1 to Vg4 applied from the fourth gate voltage application node 84 located on the output terminal 200 side toward the first gate voltage application node 81 located on the input terminal 100 side in order (Vg1 > Vg2 > Vg3 > Vg4), it leads to an improvement in the output power output to the output terminal 200 of the distributed amplifier over a wide frequency band of 2.5 GHz to 13 GHz of the input signal.

[0123] Embodiment 4 A distributed amplifier according to a fourth embodiment will be described with reference to FIG. The distributed amplifier of embodiment 1 applies gate bias voltages Vg1 to Vg4 to the gate nodes of the first transistor 11 to the fourth transistor 14 via the first gate bias voltage application circuit 51 to the fourth gate bias voltage application circuit 54, which are connected to the first gate voltage application node 81 to the fourth gate voltage application node 84, respectively.

[0124] In contrast, the distributed amplifier of embodiment 4 differs from the distributed amplifier of embodiment 1 in that gate bias voltages Vg1 to Vg4 are applied to the gate nodes of each of the first transistor 11 to the fourth transistor 14 via a common gate bias voltage application circuit 5 and a voltage distribution circuit 50, but is the same in other respects. Therefore, the following description will be centered on the gate bias voltage application circuit 5, which applies the gate bias voltages Vg1 to Vg4 to the gate nodes of the first transistor 11 to the fourth transistor 14, and the voltage distribution circuit 50. In FIG. 13, the same reference numerals as in FIG. 1 indicate the same or corresponding parts.

[0125] The common gate bias voltage application circuit 5 is connected to the gate voltage application node 8 and the last gate connection point located on the output terminal 200 side of the gate line 2, which is the fourth gate connection point 24 in this fourth embodiment. A gate bias voltage Vgg is applied to the gate voltage application node 8 . The gate bias voltage Vgg is the same as the gate bias voltage Vg4 applied to the gate voltage application node 84 in the distributed amplifier according to the first embodiment, and is -2.7V specifically.

[0126] The voltage distribution circuit 50 receives the gate bias voltage Vgg applied to the gate voltage application node 8 via the gate bias voltage application circuit 5, and applies gate bias voltages in increasing order (Vg1>Vg2>Vg3>Vg4) from the gate node of the transistor located on the output terminal 200 side, in this embodiment 4 the fourth transistor 14, to the gate node of the transistor located on the input terminal 100 side, in this embodiment 4 the first transistor 11.

[0127] The voltage distribution circuit 50 is a resistor series circuit in which a first voltage division resistor 501 to a fourth voltage division resistor 504 corresponding to the first transistor 11 to the fourth transistor 14, respectively, are connected in series between the gate node of the fourth transistor 14 and the ground node. The first voltage dividing resistor 501 has one end connected to the ground node and the other end connected to the gate node of the first transistor 11 .

[0128] The second voltage division resistor 502 has one end connected to the other end of the first voltage division resistor 501 and the other end connected to the gate node of the second transistor 12 . The third voltage division resistor 503 has one end connected to the other end of the second voltage division resistor 502 and the other end connected to the gate node of the third transistor 13 .

[0129] The fourth voltage division resistor 504 has one end connected to the other end of the third voltage division resistor 503 and the other end connected to the gate node of the fourth transistor 14 . Each of the first voltage division resistor 501 to the fourth voltage division resistor 504 is a resistor mounted on the GaN MMIC.

[0130] The capacitors 20b1 to 20b5 of the inter-gate lines 201 to 205 in the gate line 2 block DC current between the input terminal 100 and the gate connection point 21 in the gate line 2, between the gate connection points 21 to 24 in the gate line 2, and between the gate connection point 24 in the gate line 2 and one end of the termination resistor 7.

[0131] Therefore, if the resistance values ​​of the first voltage division resistor 501 to the fourth voltage division resistor 504 are Rg1 to Rg4, respectively, the gate bias voltages Vg1 to Vg3 applied to the first transistor 11 to the third transistor 13, respectively, due to the voltage drops caused by the second voltage division resistor 502 to the fourth voltage division resistor 504, are expressed by the following equations (7) to (9).

[0132] Vg3 = Vg4 - Rg4 × Ig (7) Vg2=Vg3-Rg3×Ig=Vg4-Rg4×Ig-Rg3×Ig =Vg4-(Rg4+Rg3)×Ig (8) Vg1=Vg2-Rg2×Ig=Vg4-Rg4×Ig-Rg3×Ig-Rg2×Ig =Vg4-(Rg4+Rg3+Rg2)×Ig (9)

[0133] In the above equations (7) to (9), Ig is the current flowing through the resistor series circuit configured from the first voltage division resistor 501 to the fourth voltage division resistor 504. Since the fourth gate bias voltage Vg4 is set to −2.7 V, the relationship Vg1>Vg2>Vg3>Vg4 holds, as can be understood from the above expressions (7) to (9) with the ground potential of the ground potential node as the reference.

[0134] Furthermore, by setting the resistance values ​​Rg1 to Rg4 of the first to fourth voltage division resistors 501 to 504, respectively, Vg4 can be set to -2.7V, Vg3 to -2.5V, Vg2 to -2.2V, and Vg1 to -1.7V as shown in the first embodiment. The distributed amplifier according to the fourth embodiment has the same effects as the distributed amplifier according to the first embodiment.

[0135] It should be noted that the embodiments may be freely combined, or any of the components in each embodiment may be modified, or any of the components in each embodiment may be omitted. [Industrial Applicability]

[0136] INDUSTRIAL APPLICABILITY A distributed amplifier according to the present disclosure is suitable for use as a high-frequency amplifier for amplifying high-frequency signals transmitted and received by wireless communication devices, radar devices, and the like. [Explanation of symbols]

[0137] 100 input terminal, 200 output terminal, 11 to 14 transistors, 2 gate line, 201 to 205 inter-gate line, 20a1 to 20a5 gate side transmission line, 20b1 to 20b5 capacitor, 3 drain line, 301 to 304 inter-drain line, 41 to 44 gate input circuit, 51 to 54 gate bias voltage application circuit, 5a1 to 5a4 gate voltage application inductor, 61 to 64 drain voltage supply circuit, 6a1 to 6a4 drain voltage supply inductor, 7 termination resistor, 81 to 84 gate voltage application node, 91 to 94 drain voltage supply node, 501 to 504 voltage division resistor.

Claims

1. Multiple transistors, each with a grounded source node, A gate line having multiple gate connection points to which the gate nodes of the multiple transistors are electrically connected, and multiple gate-to-gate lines which are series circuits of gate-side transmission lines and capacitors connected between adjacent gate connection points, which electrically connect the input terminal and the gate node of the last transistor located on the output terminal side, A plurality of gate bias voltage application circuits, each connected between a corresponding gate voltage application node and a corresponding gate connection point of the gate line, A drain line having multiple drain connection points to which the drain node of the first transistor located on the input terminal side is electrically connected to the output terminal, and multiple inter-drain lines which are series circuits of a drain-side transmission line and a capacitor, each connected between adjacent drain connection points, is electrically connected to the drain node of the multiple transistors. A plurality of drain voltage supply circuits, each connected between a corresponding drain voltage supply node and the corresponding drain connection point of the drain line, A distributed amplifier equipped with the following features.

2. The distributed amplifier according to claim 1, wherein, in each gate voltage application node to which each of the plurality of gate bias voltage application circuits is connected, the gate bias voltage applied to the gate voltage application node located on the input terminal side of adjacent gate voltage application nodes is equal to or greater than the gate bias voltage applied to the gate voltage application node located on the output terminal side.

3. The distributed amplifier according to claim 1, wherein, in each of the multiple gate bias voltage application nodes to which each of the gate bias voltage application circuits is connected, the gate bias voltage applied from the gate voltage application node located on the output terminal side toward the gate voltage application node located on the input terminal side is increased in sequence.

4. A plurality of transistors, each of which has a source node grounded, A gate line having multiple gate connection points to which each of the gate nodes of the multiple transistors is electrically connected, and multiple gate-side transmission lines that are connected between adjacent gate connection points, which are gate-side transmission lines, electrically connect the input terminal and the gate node of the last transistor located on the output terminal side. Multiple DC blocking capacitors are connected between the gate node of the corresponding transistor and the corresponding gate connection point of the gate line, Multiple gate bias voltage application circuits, each connected between a corresponding gate voltage application node and the corresponding transistor's gate node, A drain line having multiple drain connection points to which the drain node of the first transistor located on the input terminal side is electrically connected to the output terminal, and multiple inter-drain lines which are series circuits of a drain-side transmission line and a capacitor, each connected between adjacent drain connection points, is electrically connected to the drain node of the multiple transistors. A plurality of drain voltage supply circuits, each connected between a corresponding drain voltage supply node and the corresponding drain connection point of the drain line, A distributed amplifier equipped with the following features.

5. The distributed amplifier according to claim 4, wherein, in each gate voltage application node to which each of the plurality of gate bias voltage application circuits is connected, the gate bias voltage applied to the gate voltage application node located on the input terminal side of adjacent gate voltage application nodes is equal to or greater than the gate bias voltage applied to the gate voltage application node located on the output terminal side.

6. The distributed amplifier according to claim 4, wherein, in each of the multiple gate bias voltage application nodes to which each of the gate bias voltage application circuits is connected, the gate bias voltage applied from the gate voltage application node located on the output terminal side toward the gate voltage application node located on the input terminal side is increased in sequence.

7. A plurality of transistors, each of which has a source node grounded, A gate line having multiple gate connection points to which the gate nodes of the multiple transistors are electrically connected, and multiple gate-to-gate lines which are series circuits of gate-side transmission lines and capacitors connected between adjacent gate connection points, which electrically connect the input terminal and the gate node of the last transistor located on the output terminal side, A drain line having multiple drain connection points to which the drain node of the first transistor located on the input terminal side is electrically connected to the output terminal, and multiple inter-drain lines which are series circuits of a drain-side transmission line and a capacitor, each connected between adjacent drain connection points, is electrically connected to the drain node of the multiple transistors. A plurality of drain voltage supply circuits, each connected between a drain voltage supply node and the corresponding drain connection point of the drain line, A gate bias voltage application circuit connected to a gate voltage application node and the last gate connection point located on the output terminal side of the gate line, A voltage distribution circuit receives the gate bias voltage applied to the gate voltage application node via the gate bias voltage application circuit, and applies the gate bias voltage sequentially increasing from the gate node of the transistor located on the output terminal side to the gate node of the transistor located on the input terminal side. A distributed amplifier equipped with the following features.

8. The distributed amplifier according to claim 7, wherein the voltage distribution circuit is a series resistor circuit in which voltage dividing resistors corresponding to each of the plurality of transistors are connected in series between the gate node and the ground node of the transistor located on the output terminal side.

9. A distributed amplifier according to any one of claims 1 to 8, wherein in each drain voltage supply node to which each of the plurality of drain voltage supply circuits is connected, the drain supply voltage supplied to the drain voltage supply node located on the input terminal side of an adjacent drain voltage supply node is less than or equal to the drain supply voltage supplied to the drain voltage supply node located on the output terminal side.

10. A distributed amplifier according to any one of claims 1 to 8, wherein in each drain voltage supply node to which each of the plurality of drain voltage supply circuits is connected, the drain supply voltage supplied from the drain voltage supply node located on the output terminal side toward the drain voltage supply node located on the input terminal side is sequentially reduced.

11. A distributed amplifier according to any one of claims 1 to 3, 7, or 8, comprising a plurality of gate input circuits, each connected between the gate node of a corresponding transistor and the corresponding gate connection point of the gate line.

12. The distributed amplifier according to claim 11, wherein each of the plurality of gate input circuits is a parallel circuit of a resistor and a capacitor.

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