Display apparatus

Abstract

A display device according to an embodiment of the present specification may include: a wiring board comprising a light-emitting portion and a transmission area in which a plurality of link wirings and a gate driver are arranged; a plurality of display units each comprising a light-emitting portion and a transmission area in which a plurality of light-emitting elements are arranged and spaced apart from each other on the wiring board; and a plurality of bonding members disposed between the display units and the wiring board and connected to the gate driver and the plurality of link wirings.

Description

Technology Field

[0001] This specification relates to a display device, and more specifically, to a display device having a plurality of display units arranged on a wiring board having a plurality of link wirings arranged thereon. Background Technology

[0002] Display devices are applied to various electronic devices such as TVs, mobile phones, laptops, and tablets. To this end, research is continuously being conducted to develop thinner, lighter, and lower power consumption display devices.

[0003] Among display devices, light-emitting displays embed a light-emitting element or light source within the display device and display information using light generated from the embedded self-emissive element or light source. Display devices containing self-emissive elements can be implemented thinner than display devices with embedded light sources, and have the advantage of being flexible, allowing for the realization of displays that can be folded, bent, or rolled up.

[0004] Display devices containing self-emissive elements include, for example, Organic Light Emitting Devices (OLEDs) that use organic materials as the light-emitting layer, or Micro Light Emitting Diode displays that use inorganic materials as the light-emitting layer. Although OLEDs do not require a separate light source, they have a problem in that defective pixels are prone to occurring due to external environmental factors, as organic materials are susceptible to moisture and oxygen. In contrast, Micro LED displays use inorganic materials that are resistant to moisture and oxygen as the light-emitting layer; thus, they are not affected by external environments, offering high reliability and a longer lifespan compared to OLEDs. The problem to be solved

[0005] The problem to be solved according to the embodiments of the present specification is to provide a large-area transparent display device by arranging a plurality of display units on a wiring board on which a plurality of link wirings and gate drivers are arranged.

[0006] In addition, the problem to be solved according to the embodiments of the present specification is to provide a display device capable of implementing a zero bezel area in which the bezel area is arranged in a minimum space or substantially no bezel area exists.

[0007] In addition, the problem to be solved according to the embodiments of the present specification is to provide a display device that prevents the reliability of the product from being reduced due to a dim defect in which a fine vertical line is visible on the light-emitting part of the display unit.

[0008] In addition, the problem to be solved according to the embodiments of the present specification is to provide a display device capable of increasing the transmittance of a transparent display device by increasing the design margin through the use of a wiring board.

[0009] The problems solved according to one embodiment of this specification are not limited to the purposes mentioned above, and other unmentioned purposes and advantages of the present invention may be understood from the following description and will be more clearly understood by the embodiments of this specification. Furthermore, it will be readily apparent that the purposes and advantages of this specification can be realized by the means and combinations thereof set forth in the claims. means of solving the problem

[0010] A display device according to one embodiment of the present specification may include: a wiring board comprising a light-emitting portion and a transmission area in which a plurality of link wirings and a gate driver are arranged; a plurality of display units each comprising a light-emitting portion and a transmission area in which a plurality of light-emitting elements are arranged and spaced apart from each other on the wiring board; and a plurality of bonding members disposed between the display units and the wiring board and connected to the gate driver and the plurality of link wirings. Effects of the invention

[0011] According to one embodiment of the present specification, a large-area transparent display device can be realized by overlapping a plurality of display units on the upper surface of a wiring board on which a plurality of link wirings and gate drivers are arranged.

[0012] In addition, by introducing a configuration in which a gate driver is placed on the light-emitting part of a wiring board at a position overlapping with the light-emitting part of a display unit, it is possible to prevent defects and dim defects from occurring where the boundary area between adjacent display units is visible to the user.

[0013] Accordingly, this has the effect of enabling the bezel area on the outer edge of the display unit to be positioned in a minimal space, or to implement a zero-bezel area where the bezel area practically does not exist.

[0014] In addition, by introducing a configuration in which a gate driver is placed on the light-emitting part of a wiring board at a position overlapping with the light-emitting part of a display unit, there is an advantage in that the transparent area is reduced, thereby preventing a decrease in transmittance.

[0015] In addition, the gate driver disposed on the wiring board has a width smaller than the area including the pixel area and bonding member of the display unit, thereby preventing a reduction in the aperture ratio. This prevents a reduction in power consumption.

[0016] In addition, process optimization can be achieved by electrically connecting the wiring board and multiple display units from the top and bottom using bonding members without using separate side wiring.

[0017] The effects of this specification are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art from the description below. Brief explanation of the drawing

[0018] FIG. 1 is a schematic plan view of a display device according to one embodiment of the present specification. FIG. 2 is a schematic plan view of a wiring board according to one embodiment of the present specification. Figure 3 is a cross-sectional view of 3 in Figure 1. Figure 4 is a plan view of 4 in Figure 2. Figure 5 is a plan view of a part of the display unit. FIG. 6 is a plan view of a portion of a display device according to one embodiment of the present specification. Figure 7 is a cross-sectional view of 7 in Figure 5. FIGS. 8 to 13 are drawings showing a display device according to another embodiment of the present specification. Specific details for implementing the invention

[0019] The advantages and features of this specification and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below but may be implemented in various different forms, and these embodiments are provided merely to ensure that the disclosure of this specification is complete and to fully inform those skilled in the art of the scope of the invention.

[0020] Shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are exemplary and are not limited to the depicted items. Throughout the specification, the same reference numerals refer to the same components. Furthermore, in describing this specification, if it is determined that a detailed description of related prior art could unnecessarily obscure the essence of this specification, such detailed description is omitted. Where terms such as "includes," "has," or "is made up" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it includes cases where it is included in the plural unless specifically stated otherwise.

[0021] In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit statement.

[0022] In the case of describing a positional relationship, for example, when the positional relationship between two parts is described using expressions such as 'on,' 'upper,' 'lower,' or 'next to,' one or more other parts may be located between the two parts unless 'immediately' or 'directly' is used.

[0023] In the case of an explanation of a temporal relationship, for example, when a temporal sequence is explained using 'after', 'following', 'next', 'before', etc., it may include cases where the sequence is not continuous unless 'immediately' or 'directly' is used.

[0024] Although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of this specification.

[0025] The features of each of the various embodiments of this specification may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0026] Hereinafter, a display device according to each embodiment of the present invention will be described with reference to the attached drawings.

[0028] FIG. 1 is a schematic plan view of a display device according to one embodiment of the present specification. FIG. 2 is a schematic plan view of a wiring board according to one embodiment of the present specification. FIG. 3 is a cross-sectional view of 3 in FIG. 1.

[0029] In FIG. 1, for convenience of explanation, among the components of a display device (TD), only a wiring board (M-SUB), a plurality of link wires (LL), a gate driver (GIA), a plurality of circuit films (110) on which an integrated circuit chip (113) is placed, a printed circuit board (115), and a plurality of display units (TU) are shown. FIG. 2 shows the components shown in FIG. 1 excluding the plurality of display units (TU). FIG. 3 also shows only one display unit (TU) placed on a wiring board (M-SUB) in a display device according to one embodiment of the present specification.

[0030] Referring to FIGS. 1 to 3, a display device (TD) according to one embodiment of the present specification may be a tiling display device comprising a plurality of display units (TU) arranged on a wiring board (M-SUB). Each of the display units (TU) may be arranged along a first direction and a second direction intersecting the first direction with adjacent display units. Here, the first direction may be a horizontal direction and the second direction may be a vertical direction.

[0031] Each display unit (TU) can be electrically connected to a wiring board (M-SUB) through a bonding member (320). The first substrate (105) of the wiring board (M-SUB) and the second substrate (202) of the display unit (TU) may include glass or transparent plastic. By arranging a plurality of display units (TU) on the upper surface of the wiring board (M-SUB), a large-area transparent display device can be provided.

[0032] A plurality of link wires (LL) and a gate driver (GIA) may be disposed on a wiring board (M-SUB). A plurality of link wires (LL) may be disposed along one direction of the wiring board (M-SUB). At least one end of the wiring board (M-SUB), a driving unit may be disposed including a printed circuit board (115) connected to a circuit film (110) on which an integrated circuit chip (113) for transmitting various signals to each subpixel of a display unit is mounted.

[0033] The driving unit may be connected to the end of the link wiring (LL) and the gate driver (GIA) through a plurality of connecting electrodes (120). Signals transmitted to the subpixels may include, for example, a high potential voltage, a low potential voltage, a scan signal, or a data signal. The output transmitted from the gate driver (GIA) may include an output voltage capable of driving a gate line connected to a thin-film transistor placed on the display unit (TU).

[0034] In the embodiments of this specification, a driving unit including a printed circuit board (115) connected to a circuit film (110) on which an integrated circuit chip (113) is mounted is provided in a configuration disposed at both ends of a wiring board (M-SUB), but is not limited thereto.

[0035] A plurality of link wires (LL) can transmit various signals transmitted from the driving unit to a plurality of signal wires arranged in each of the display units (TU). For example, the signal wires may include, but are not limited to, high potential voltage lines, low potential voltage lines, scan lines, or data lines.

[0036] A plurality of display units (TU) arranged on a wiring board (M-SUB) can be connected to the wiring board (M-SUB) through electrical connections between a plurality of signal lines, a plurality of link lines (LL) disposed on the wiring board (M-SUB), and a gate driver (GIA). Here, the plurality of link lines (LL) may be arranged to overlap with the plurality of display units (TU) so as not to be exposed to the outside. By doing so, the area of ​​the circuit region where the plurality of link lines (LL) are disposed can be reduced, thereby increasing the display area. This will be explained below with reference to FIGS. 4 to 6.

[0037] FIG. 4 is a plan view of 4 in FIG. 2. FIG. 5 is a plan view of a portion of a display unit. FIG. 6 is a plan view of a portion of a display device according to one embodiment of the present specification.

[0038] Referring to FIGS. 4 to 6, a first region of a wiring board (M-SUB) may include a plurality of light-emitting parts (PXA), and a second region may include a plurality of transmission regions (TA). The first region and the second region may be positioned alternately. The light-emitting part (PXA), which is the first region of the wiring board (M-SUB), may be divided into blocks. For example, the light-emitting part (PXA) may include a first light-emitting part (PXA-1) located in the first block and a second light-emitting part (PXA-2) located in the second block.

[0039] The second region of the wiring board (M-SUB), the transparent region (TA), can be divided into blocks. For example, the transparent region (TA) may include a first transparent region (TA-1) located in the first block and a second transparent region (TA-2) located in the second block. Although only the first block and the second block are shown in FIG. 4 for convenience of explanation, multiple blocks may be arranged.

[0040] A first transmission area (TA-1) may be disposed between the first light-emitting part (PXA-1) and the second light-emitting part (PXA-2), and a second transmission area (TA-2) may be disposed between the second light-emitting part (PXA-2) and the light-emitting part located in another block.

[0041] Each light-emitting part (PXA) disposed in the first region of the wiring board (M-SUB) can be positioned corresponding to each light-emitting part (PXA) disposed in the first region of the display unit (TU), and each transmission region (TA) disposed in the second region of the wiring board (M-SUB) can be positioned corresponding to each transmission region (TA) of the second region of the display unit (TU).

[0042] The transparent area (TA) may be an area where no opaque or reflective material is placed. The display device (TD) according to the embodiments of this specification may obtain transmittance through the transparent area (TA). Accordingly, the display device (TD) may be a transparent display device in which an object or image placed on the back surface of the display device can be seen through the transparent area (TA).

[0043] A link wiring (LL) and a gate driver (GIA) arranged along one direction of the wiring board (M-SUB) may be disposed on the light-emitting portion (PXA) of the wiring board (M-SUB). The gate driver supplies a signal to drive the gate line.

[0044] One method of deploying gate drivers is to deploy them in a Gate-In-Panel (GIP) manner in each of the display units. Gate drivers deployed in the GIP manner are positioned in the outer bezel areas on both sides of each display unit (TU) to compensate for the short charging time of each gate line, thereby providing the same gate output to both ends of each gate line.

[0045] However, in a tiling display device configured by arranging multiple display units (TU) on a wiring board (M-SUB), adjacent display units are arranged in contact with each other along a first direction and a second direction intersecting the first direction. In a configuration where adjacent display units are arranged in contact, if a gate driver is placed in the bezel areas on both sides of each display unit (TU), the opaque area of ​​the bezel area increases. Consequently, in a configuration where adjacent display units are arranged in contact, the bezel area becomes visible to the user, which may degrade the image quality. Accordingly, there is a problem in that it is difficult to implement the tiling display device.

[0046] In addition, instead of placing the gate driver in the bezel area, there is a method of distributing it within the display unit (TU). For example, there is a method of distributing multiple gate drivers in the space between the light-emitting parts on the display unit (TU). However, when gate drivers are distributed between the light-emitting parts on the display unit (TU), the transparent area is reduced, which may result in a decrease in transmittance. Furthermore, a dim defect may occur in which fine vertical lines are visible in the area where the gate driver is distributed.

[0047] Accordingly, in the embodiments of the present specification, by introducing a configuration in which a gate driver (GIA) is placed on the light-emitting part (PXA) of the wiring board (M-SUB), it is possible to prevent defects and dim defects in which the boundary area between adjacent display units (TU) is visible to the user.

[0048] Referring again to FIG. 4, a gate driver (GIA) may be arranged in blocks on a first light-emitting part (PXA-1) located in a first block of a wiring board (M-SUB) and a second light-emitting part (PXA-2) located in a second block. The gate driver (GIA) may include a plurality of thin-film transistors that drive each of the gate lines.

[0049] Gate drivers (GIAs) arranged in blocks may have a first width (W1) on a first light-emitting part (PXA-1) located in a first block and a second light-emitting part (PXA-2) located in a second block. Gate drivers (GIAs) arranged in adjacent blocks may be electrically connected via a horizontal connecting wire (CL). For example, the horizontal connecting wire (CL) may be electrically connected from a gate driver (GIA) arranged on a first light-emitting part (PXA-1) located in a first block to a gate driver (GIA) arranged on a second light-emitting part (PXA-2) located in a second block, across a first transmission area (TA-1) in a horizontal direction.

[0050] Referring to FIGS. 5 and 6, each display unit (TU) disposed on a wiring board (M-SUB) may include a light-emitting part (PXA) corresponding to each light-emitting part (PXA) disposed in a first region of the wiring board (M-SUB) and a transmission area (TA) corresponding to each transmission area (TA) disposed in a second region of the wiring board (M-SUB).

[0051] The light-emitting part (PXA) and the transmission area (TA) of the display unit (TU) may be divided into blocks. For example, the light-emitting part (PXA) may include a first light-emitting part (PXA-1) located in a first block and a second light-emitting part (PXA-2) located in a second block. Additionally, the transmission area (TA) may include a first transmission area (TA-1) located in a first block and a second transmission area (TA-2) located in a second block. Although only the first block and the second block are shown in FIG. 5 for convenience of explanation, the display unit (TU) may include a plurality of blocks.

[0052] Various circuit elements, including a light-emitting element (ED) and a driving thin-film transistor for driving the light-emitting element (ED), may be disposed on the light-emitting portion (PXA) of the display unit (TU). The transmission area (TA) of the display unit (TU) may be an area where no opaque or reflective material is disposed.

[0053] The light-emitting part (PXA) of the display unit (TU) may include a pixel area (PX) in which a plurality of light-emitting elements (ED) are arranged. A single pixel area (PX) can be understood as a group comprising a plurality of subpixels. The light-emitting elements (ED) arranged in the pixel area (PX) of the display unit (TU) may include at least one light-emitting element arranged in each of the subpixels. For example, the light-emitting elements (ED) may include a first light-emitting element (ED1a), a second light-emitting element (ED2a), or a third light-emitting element (ED3a), which are main light-emitting elements emitting red (R), green (G), and blue (B) light, respectively, but are not limited thereto.

[0054] Additionally, each of the plurality of subpixels may further include a plurality of redundancy light-emitting elements (ED1b, ED2b, ED3b) for a repair process. For example, the redundancy light-emitting elements (ED1b, ED2b, ED3b) may include a first redundancy light-emitting element (ED1b), a second redundancy light-emitting element (ED2b), or a third redundancy light-emitting element (ED3b) that corresponds to emitting the same color as the first light-emitting element (ED1a), the second light-emitting element (ED2a), or the third light-emitting element (ED3a), respectively.

[0055] A bonding member (320) may also be disposed on the light-emitting part (PXA) of the display unit (TU). Referring to FIG. 6, the bonding member (320) may be disposed overlapping with the link wiring (LL) disposed on the wiring board (M-SUB).

[0056] The bonding member (320) is positioned to overlap with a plurality of link wires (LL) on the wiring board (M-SUB) so that the wiring board (M-SUB) and each display unit (TU) can be electrically connected to each other from the top and bottom. For example, the bonding member (320) can serve to transmit various signals transmitted through the link wires (LL) to a light-emitting element (ED) or a driving thin-film transistor (TFT). Process optimization can be achieved by electrically connecting the wiring board (M-SUB) and the plurality of display units (TU) using the bonding member (320) without using separate side wiring.

[0057] The area including the pixel area (PX) where a plurality of light-emitting elements (ED) of the display unit (TU) are arranged and the bonding member (320) may have a size of a second width (W2). The gate driver (GIA) arranged in block units on the wiring board (M-SUB) has a size of a first width (W1) in each light-emitting part (PXA-1, PXA-2) and may have a size of a smaller width than the light-emitting part where a plurality of light-emitting elements of the display unit (TU) are arranged. For example, the gate driver (GIA) may have a size smaller than the size of the second width (W2) of the area including the pixel area (PX) where a plurality of light-emitting elements (ED) of the display unit (TU) are arranged and the bonding member (320). Accordingly, the aperture ratio may be prevented from being reduced, thereby preventing the brightness from being reduced.

[0058] The gate driver (GIA) can be positioned overlapping the light-emitting part (PXA) of the display unit (TU) by being placed on the light-emitting part (PXA) of the wiring board (M-SUB). As a result, the design margin of the light-emitting part (PXA) of the display unit (TU) can be increased by the size of the area where the gate driver (GIA) is placed.

[0059] For example, if multiple gate drivers are distributed and placed in the space between light-emitting parts on a display unit (TU), the area available for placing circuit elements such as transistors may be reduced by the area where the gate drivers are placed. Additionally, coupling caused by parasitic capacitors may occur between the horizontal connection wiring connecting gate drivers (GIAs) placed in adjacent blocks and the data line, which is one of the signal wirings. Consequently, the space margin between adjacent circuit elements is reduced, which may lead to capacitor coupling or positional parasitic capacitor deviation. Capacitor coupling or positional parasitic capacitor deviation causes brightness variation, where brightness differs by location in the light-emitting part, which can result in a dim defect where fine vertical lines are visible in the light-emitting part. Such dim defects can degrade image quality and reduce the reliability of the display device product.

[0060] In this regard, according to an embodiment of the present specification, the gate driver (GIA) is positioned on the light-emitting part (PXA) of the wiring board (M-SUB) at a location that overlaps with the light-emitting part (PXA) of the display unit (TU), thereby increasing the design margin and preventing capacitor coupling or positional parasitic capacitor deviation. Accordingly, the reliability of the display device can be improved by preventing the occurrence of dim defects caused by positional brightness deviation in the light-emitting part.

[0061] Additionally, according to an embodiment of the present specification, the gate driver (GIA) may be arranged in the shape of a driving circuit placed in the pixel area (PX) of the display unit (TU).

[0062] Additionally, according to an embodiment of the present specification, instead of placing the gate driver (GIA) in the bezel area on both outer sides of the display unit (TU), it is placed on the light-emitting part (PXA) of the wiring board (M-SUB), so that the bezel area of ​​the display unit (TU) can be placed in a minimal space or implemented as a zero bezel area where there is substantially no bezel area.

[0063] A plurality of pixel regions (PX) and a bonding member (320) may be disposed on the light-emitting part (PXA) of the display unit (TU). A light-emitting element and a driving circuit including a thin-film transistor for driving the light-emitting element may be disposed in each of the plurality of pixel regions (PX). The following description will be made with reference to FIG. 7. FIG. 7 is a cross-sectional view of 7 in FIG. 5. FIG. 7 shows a light-emitting element and a thin-film transistor disposed in a single subpixel for convenience of explanation. Each subpixel may include the same components.

[0064] Referring to FIG. 7, a subpixel according to one embodiment of the present specification may include a thin-film transistor (TFT), a storage capacitor (Cst), and various wirings disposed on a second substrate (202). The thin-film transistor (TFT) can drive a light-emitting element (ED), and the storage capacitor (Cst) can store voltage so that the light-emitting element (ED) maintains the same state continuously for one frame.

[0065] A light-blocking layer (LS) may be disposed on the second substrate (202). The light-blocking layer (LS) can reduce leakage current by blocking light incident on the active layer of a plurality of transistors from the bottom of the second substrate (202). For example, the light-blocking layer (LS) may be disposed below the active layer (ACT) of a thin-film transistor (TFT) that functions as a driving transistor to block light incident on the active layer (ACT).

[0066] A buffer layer (204) is disposed on the light-blocking layer (LS). The buffer layer (204) can prevent the penetration of impurities or moisture through the second substrate (202). The buffer layer (204) may include an insulating material, for example, silicon oxide (SiOx) or silicon nitride (SiNx).

[0067] A thin-film transistor (TFT) is disposed on a buffer layer (204). The thin-film transistor (TFT) may include a semiconductor layer (ACT), a gate electrode (GE), a source electrode (SE), and a drain electrode (DE). A gate insulating layer (GI) may be disposed between the semiconductor layer (ACT) and the gate electrode (GE).

[0068] The semiconductor layer (ACT) may include an active region that forms a channel by overlapping with the gate electrode (GE), and source and drain regions located on both sides of the active region. An interlayer insulating film (206) is disposed on the gate electrode (GE). The interlayer insulating film (206) may include a source contact (SC) and a drain contact (DC). The source contact (SC) and the drain contact (DC) are each connected to a source electrode (SE) and a drain electrode (DE) located on the interlayer insulating film (206), and thus can be electrically connected to the source region and the drain region of the semiconductor layer (ACT), respectively.

[0069] A storage capacitor (Cst) may include a first capacitor electrode (ST1) and a second capacitor electrode (ST2). The first capacitor electrode (ST1) may be disposed between a second substrate (202) and a buffer layer (204). The first capacitor electrode (ST1) may be integrally formed with a light-blocking layer (LS). A buffer layer (204) and a gate insulating layer (GI) may be disposed as dielectrics on the first capacitor electrode (ST1). A second capacitor electrode (ST2) may be disposed on the gate insulating layer (GI). The second capacitor electrode (ST2) may be made of the same material as the gate electrode (GE).

[0070] A first passivation layer (208) is disposed on the source electrode (SE) and the drain electrode (DE). The first passivation layer (208) protects the thin-film transistor (TFT) and may contain an insulating material. A first flattening layer (210) is disposed on the first passivation layer (208). The first flattening layer (210) serves to flatten the surface step caused by the underlying structure, such as the thin-film transistor (TFT). The first flattening layer (210) may be composed of a photoactive compound (PAC), but is not limited thereto.

[0071] The first flattening layer (210) may include a contact hole (212) that exposes a portion of the surface of the source electrode (SE) and the drain electrode (DE). A second passivation layer (216) may be disposed on the first flattening layer (210) including the contact hole (212), and via contacts (220a, 220b) that each fill the contact hole (212) may be disposed. The via contacts (220a, 220b) may include a first via contact (220a) and a second via contact (220b).

[0072] A first connecting electrode (225a) connected to the first via contact (220a) and a second connecting electrode (225b) connected to the second via contact (220b) may be disposed on the second passivation layer (116). The drain electrode (DE) connected to the first via contact (220a) may be electrically connected to the light blocking layer (LS) through a through electrode (VC) that penetrates the interlayer insulating film (206) and the buffer layer (204).

[0073] The first connection electrode (225a), the second connection electrode (225b), and the signal wiring (230) may be located on the same plane. The third passivation layer (235) may expose the upper surface of each of the first connection electrode (225a), the second connection electrode (225b), and the signal wiring (230). The signal wiring (230) may include a plurality of signal wirings. For example, the plurality of signal wirings may include a plurality of scan lines, a plurality of high potential voltage (Vdd) lines, a plurality of data lines, and a plurality of reference voltage lines. The plurality of signal wirings may be arranged on the same plane as each other on the second substrate (202). Additionally, the plurality of signal wirings may be made of the same material as the first connection electrode (225a) and the second connection electrode (225b).

[0074] An adhesive layer (AD) is disposed on the third passivation layer (235). The adhesive layer (AD) serves to adhere the light-emitting element (ED). The adhesive layer (AD) may be made of a thermally curable material or a photocurable material, but is not limited thereto.

[0075] A light-emitting element (ED) may be disposed on the adhesive layer (AD). The light-emitting element (ED) according to the embodiments of this specification may be a micro LED. A micro LED is an LED made of inorganic material and can be understood as a light-emitting element with a size of 100 μm or less. In addition, although a horizontal micro LED has been described as an example in the embodiments of this specification, it is not limited thereto. For example, the light-emitting element may be a vertical micro LED, a flip-chip type micro LED, or a nanorod type micro LED.

[0076] A light-emitting device (ED) may include a nitride semiconductor structure (NSS), a first electrode (E1), and a second electrode (E2). The nitride semiconductor structure (NSS) may include a first semiconductor layer (NS1), an active layer (EL) disposed on one side of the first semiconductor layer (NS1), and a second semiconductor layer (NS2). The first electrode (E1) is disposed on the first semiconductor layer (NS1) where the active layer (EL) is not located, and the second electrode (E2) is disposed on the second semiconductor layer (NS2).

[0077] The first semiconductor layer (NS1) is a layer for supplying electrons to the active layer (EL) and may include a nitride semiconductor containing a first conductivity type impurity. For example, the first conductivity type impurity may include an N-type impurity. The active layer (EL) disposed on one side of the first semiconductor layer (NS1) may include a Multi Quantum Well (MQW) structure. The second semiconductor layer (NS2) is a layer for injecting holes into the active layer (EL). The second semiconductor layer (NS2) may include a nitride semiconductor containing a second conductivity type impurity. For example, the second conductivity type impurity may include a P-type impurity.

[0078] The protective layer pattern (PT) can cover the outer surface of the light-emitting device (ED). The protective layer pattern (PT) serves to complement the device's characteristics by preventing damage that may occur to the side surfaces of the nitride semiconductor structure (NSS) during the dry etching process performed to form the nitride semiconductor structure (NSS).

[0079] The light-emitting element (ED) may be covered with a second flattening layer (240). The second flattening layer (240) may have sufficient thickness to flatten the upper surface having a step difference caused by circuit elements. The second flattening layer (240) may include opening holes (241, 243). The opening holes (241, 243) may include a first opening hole (241) and a second opening hole (243). Additionally, the second flattening layer (240) may expose a portion of the upper surface of the first electrode (E1) and the second electrode (E2) of the light-emitting element (ED). The first electrode (E1) and the second electrode (E2) may be electrically connected to the first wiring electrode (CE1) and the second wiring electrode (CE2), respectively.

[0080] The first wiring electrode (CE1) may extend to the exposed surface of the first opening hole (241), and the second wiring electrode (CE2) may extend to the exposed surface of the second opening hole (243). The first wiring electrode (CE1) may be electrically connected to the signal wiring (230). The second wiring electrode (CE2) may be electrically connected to the drain electrode (DE) through the first connecting electrode (225a).

[0081] The first wiring electrode (CE1) and the second wiring electrode (CE2) may be disposed on the same layer and composed of the same conductive material. In one example, the first wiring electrode (CE1) and the second wiring electrode (CE2) may comprise a transparent metal oxide such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).

[0082] A bank (BNK) may be disposed on the second flattening layer (240). The bank (BNK) may be formed by including an opaque material, but is not limited thereto. The first opening hole (241) and the second opening hole (243) may be filled with a material constituting the bank (BNK). Additionally, the bank (BNK) may be disposed in the area surrounding the light-emitting element (ED), excluding the area where the light-emitting element (ED) is disposed. A protective layer (245) may be disposed on the second flattening layer (240) containing the bank (BNK). The protective layer (245) can prevent impurities from penetrating into the light-emitting element (ED).

[0083] An interlayer connecting electrode (ILC) may be disposed that penetrates the protective layer (245) and the second flattening layer (240) to expose a portion of the surface of the second connecting electrode (225b). The interlayer connecting electrode (ILC) may be electrically connected to a thin-film transistor (TFT) of the display unit (TU) through the second connecting electrode (225b).

[0084] A bonding member (320) may be disposed on the protective layer (245). The bonding member (320) may include a spacer pattern (300), a conductive connection pattern (305), and an adhesive pattern (310). The spacer pattern (300) may serve to maintain and support the gap between the wiring board (M-SUB) and the display unit (TU). The spacer pattern (300) may be formed in a regular taper shape in which the width of the lower surface is wider than that of the upper surface, but is not limited thereto.

[0085] The outer surface of the spacer pattern (300) may be covered with a conductive connection pattern (305). For example, the conductive connection pattern (305) may be positioned to surround the outer surface while covering the upper surface of the spacer pattern (300). Additionally, the conductive connection pattern (305) may be electrically connected to a thin-film transistor (TFT) through an interlayer connection electrode (ILC).

[0086] An adhesive pattern (310) may be placed on a conductive connection pattern (305) covering the upper surface of a spacer pattern (300). The adhesive pattern (310) can bond and fix the wiring board (M-SUB) and the display unit (TU).

[0087] Additionally, the adhesive pattern (320) may be electrically conductive to transmit a driving signal transmitted through the link wiring (LL) of the wiring substrate (M-SUB) to a thin-film transistor (TFT) to cause a light-emitting element on the display unit (TU) to emit light. To this end, the adhesive pattern (310) may be formed by including a material that is electrically conductive and adhesive. For example, the adhesive pattern (310) may include an anisotropic conductive film (ACF).

[0088] The electrically conductive bonding member (320) can serve as a connecting wire to drive a gate line connected to a thin-film transistor placed on a display unit (TU) by transmitting an output from a gate driver (GIA) placed on a wiring board (M-SUB).

[0089] A display device according to one embodiment of the present specification can increase the design margin of the light-emitting part (PXA) of a display unit (TU) by placing a gate driver (GIA) on the light-emitting part (PXA) of a wiring board (M-SUB) that overlaps with the light-emitting part (PXA) of a display unit (TU). In addition, by placing the gate driver (GIA) on the light-emitting part (PXA) of the wiring board (M-SUB), it is possible to prevent a dim defect in which fine vertical lines are visible in the light-emitting part of the display unit (TU) and thus become visible to the user. This can improve the product reliability of the display device.

[0090] Meanwhile, by placing a driving transistor (TFT) and a storage capacitor (Cst) that occupy a large design area in the light-emitting portion of the wiring board (M-SUB), the effect of coupling phenomena between signals supplied to the subpixel can be minimized, thereby preventing crosstalk defects. This will be explained below with reference to FIGS. 8 to 13.

[0091] FIGS. 8 to 13 are drawings illustrating a display device according to another embodiment of the present specification. FIG. 8 shows only one display unit (TU) disposed on a wiring board (M-SUB) in a display device according to another embodiment of the present specification. FIG. 9 is a plan view of 9 in FIG. 8. FIG. 10 is a plan view of 10 in FIG. 9. FIG. 11 is a plan view of a portion of the display unit. FIG. 12 is a plan view of 12 in FIG. 11. FIG. 13 is a plan view of a portion of the display unit bonded to the wiring board.

[0092] In this specification, the display device according to another embodiment is identical to FIGS. 4 through 6 in other components, except for the configuration in which a driving thin-film transistor (Dr-TFT), a storage capacitor (Cst), and a data voltage (Vdata) are arranged on a wiring substrate (M-SUB). Accordingly, components indicated by the same reference numerals as FIGS. 4 through 6 may be briefly described or omitted.

[0093] Referring to FIGS. 9 and 10, a link wire (LL) and a gate driver (GIA) may be disposed on the light-emitting part (PXA) of the wiring board (M-SUB). The gate driver may supply a signal to drive the gate line. A gate driver (GIA) may be disposed in block units on a first light-emitting part (PXA-1) located in the first block of the wiring board (M-SUB) and a second light-emitting part (PXA-2) located in the second block. The gate driver (GIA) may have a size of a first width (W1). Gate drivers (GIA) disposed in adjacent blocks may be electrically connected through a horizontal connection wire (CL).

[0094] In the light-emitting portion (PXA) of the wiring board (M-SUB) on which the gate driver (GIA) is placed, a thin-film transistor (Dr-TFT) that functions as a driving transistor together with the gate driver (GIA), a storage capacitor (Cst), and a data line (DL) to which a data voltage (Vdata) is applied may be placed.

[0095] A thin-film transistor (Dr-TFT) can drive a light-emitting element (ED), and a storage capacitor (Cst) can store voltage so that the light-emitting element (ED) maintains the same state continuously for one frame. The thin-film transistor (Dr-TFT) may include a semiconductor layer (ACT), a gate electrode (GE), a source electrode (SE), and a drain electrode (DE). A bonding member contact hole (320H) may be placed overlapping the source electrode (SE) and the drain electrode (DE). Through the bonding member contact hole (320H), it can be electrically connected to a bonding member (320) placed on a display unit (TU).

[0096] The data voltage (Vdata) can transmit a data signal to a thin-film transistor (Dr-TFT) through a data line (DL) extended along one direction of the light-emitting part (PXA) of the wiring board (M-SUB). A scan line (SL1) can be placed across the data line (DL). And a first transistor (T1) to which the data voltage (Vdata) is applied can be placed at the location where the data line (DL) and the scan line (SL1) intersect.

[0097] The lower capacitor electrode constituting the storage capacitor (Cst) may contain the same material as the semiconductor layer (ACT), and the upper capacitor electrode may contain the same material as the gate electrode (GE) of the thin-film transistor (Dr-TFT).

[0098] A data line (DL) that supplies a data signal determining the current value of a thin-film transistor (Dr-TFT) driving a light-emitting element, and a first transistor (T1) to which a data voltage (Vdata) is applied are placed on a wiring board (M-SUB). In addition, by placing the thin-film transistor (Dr-TFT) and storage capacitor (Cst), which occupy a large design area, on the wiring board (M-SUB), additional margin for the size of the thin-film transistor (Dr-TFT) and storage capacitor (Cst) can be secured.

[0099] Referring to FIGS. 11 to 13, a light-emitting element (ED) and a bonding member (320) placed in a pixel area (PX) can be placed on a display unit (TU). By placing a thin-film transistor (Dr-TFT) and a storage capacitor (Cst), which occupy a large design area, on a wiring substrate (M-SUB), the area occupied by circuit elements placed on the display unit (TU) can be reduced. Accordingly, as the transmittance of the display unit (TU) can be improved, a transparent display device requiring high resolution and high transmittance can be easily implemented.

[0100] A reference voltage line (Vref) may be arranged along one direction of the display unit (TU). A scan line (SL2) and a light emission signal line (EM) may be arranged along the other direction that intersects the direction in which the reference voltage line (Vref) is arranged. The light emission signal line (EM) is a wiring to which a light emission signal is applied and may be arranged parallel to the scan line (SL2). A driving signal may be supplied to a light-emitting element (ED) according to the light emission signal transmitted to the light emission signal line (EM).

[0101] A plurality of bonding members (320) electrically connected to a semiconductor layer (ACT) may be disposed on the display unit (TU). Each of the plurality of bonding members (320) may receive a driving signal from a thin-film transistor (Dr-TFT) through a bonding member contact hole (320H) disposed on a wiring substrate (M-SUB).

[0102] The current value (Ioled) of a thin-film transistor (Dr-TFT) driving a light-emitting device can be determined by a reference voltage (Vref) and a data voltage (Vdata). The current value (Ioled) can be determined by the following [Equation 1].

[0103] [Equation 1] Ioled = k / 2*(Vref-Vdata) 2 (k is a constant)

[0104] According to [Equation 1], the reference voltage (Vref) and data voltage (Vdata) must be supplied uniformly so that the current value (Ioled) of the thin-film transistor (Dr-TFT) driving the light-emitting element is supplied uniformly, thereby enabling stable image supply. If there are fluctuations in the reference voltage (Vref) and data voltage (Vdata), a crosstalk phenomenon may occur, causing distortion in the image due to the influence of coupling, etc. Crosstalk can degrade image quality and reduce the reliability of the display device.

[0105] In this regard, another embodiment of the present specification may place the data voltage (Vdata), which is one of the variables determining the current value (Ioled) of the thin-film transistor (Dr-TFT) driving the light-emitting element, on a wiring substrate (M-SUB), and place the reference voltage (Vref) separately on a display unit (TU). Accordingly, the coupling effect between the reference voltage (Vref) and the data voltage (Vdata) can be minimized to prevent crosstalk from occurring.

[0106] Although the embodiments of this specification have been described in more detail with reference to the attached drawings, this specification is not necessarily limited to these embodiments and may be modified in various ways within the scope of the technical spirit of this specification. Accordingly, the embodiments disclosed in this specification are intended to explain, not limit, the technical spirit of this specification, and the scope of the technical spirit of this specification is not limited by these embodiments. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0107] 105: First substrate 110: Circuit film 113: Integrated circuit chip 115: Printed circuit board 202: Second substrate 320: Bonding member M-SUB: Wiring board LL: Link wiring TU: Display Unit PX: Pixel area ED: Light-emitting element TFT: Thin-film transistor GIA: Gate Driver PXA: Light emitter TA: Transmission area

Claims

Claim 1 A display device comprising: a wiring board comprising a first substrate including a light-emitting corresponding region and a first transmission region; a second substrate comprising a light-emitting region arranged to overlap facing the light-emitting corresponding region and a second transmission region arranged to overlap facing the first transmission region, and a plurality of display units arranged spaced apart from each other on the wiring board; and a plurality of bonding members arranged between the display units and the wiring board, wherein the wiring board comprises: a driving thin-film transistor arranged in the light-emitting corresponding region; a storage capacitor electrically connected to the driving thin-film transistor; and a bonding member contact hole arranged to overlap with at least one of the source electrode and drain electrode of the driving thin-film transistor, wherein a plurality of light-emitting elements are arranged in the light-emitting region of the second substrate of the display unit, and at least one of the plurality of bonding members is electrically connected to the driving thin-film transistor through the bonding member contact hole. Claim 2 In claim 1, the wiring board is composed of a single board commonly provided to the plurality of display units, and the plurality of display units are arranged spaced apart from each other along a first direction and a second direction intersecting the first direction on the wiring board. Claim 3 In paragraph 2, the display device wherein adjacent display units among the plurality of display units are arranged in contact with each other along the first direction and the second direction. Claim 4 A display device according to paragraph 2, wherein two or more of the plurality of bonding members are correspondingly arranged in each of the plurality of display units. Claim 5 A display device according to claim 1, wherein the light-emitting corresponding area of ​​the wiring board is positioned alternately with the first transmission area, and the light-emitting corresponding area is divided into a plurality of blocks, and includes a first light-emitting corresponding area located in a first block and a second light-emitting corresponding area located in a second block spaced apart from the first block. Claim 6 A display device according to claim 5, wherein the first transmission region comprises: a first portion located between the first light-emitting corresponding region and the second light-emitting corresponding region; and a second portion located between the second light-emitting corresponding region and the light-emitting corresponding region of another block adjacent to the second block. Claim 7 In paragraph 5, at least one of the above driving thin-film transistors is a display device disposed in the first block and the second block, respectively. Claim 8 A display device according to claim 1, wherein the wiring board further comprises a data line to which a data voltage is applied and the data line intersects the data line, and the display unit further comprises a reference voltage line extending along one direction and the second scan line extending along another direction intersecting the one direction and a light-emitting signal line. Claim 9 In claim 1, the bonding member is a display device positioned at a location corresponding to the light-emitting area of ​​the display unit. Claim 10 In claim 9, the bonding member comprises: a spacer pattern maintaining a gap between the wiring substrate and the display unit; a conductive connection pattern covering the upper and outer surfaces of the spacer pattern; and an adhesive pattern located on the conductive connection pattern and connected to the driving thin-film transistor through the bonding member contact hole. Claim 11 In claim 1, a display device in which the driving thin-film transistor and the storage capacitor are not disposed in the display unit. Claim 12 A display device according to claim 1, wherein a light-emitting element is not disposed in the light-emitting corresponding area of ​​the wiring board. Claim 13 A display device according to claim 1, wherein the light-emitting element comprises a plurality of main light-emitting elements; and a redundancy light-emitting element corresponding to each of the plurality of main light-emitting elements to emit the same color as each of the main light-emitting elements. Claim 14 In claim 8, a display device in which the current value (Ioled) of the driving thin-film transistor is determined in proportion to the square of the difference between the reference voltage (Vref) and the data voltage.

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