Storage device and method for operating the device

Abstract

A storage device and a method for operating the same are provided. The storage device includes a non-volatile memory in which data is written in mapping size units, and a storage controller that provides a command to the non-volatile memory, wherein the storage controller includes a host interface that receives a write command from a host instructing to write first data of a first size smaller than the mapping size unit to a first address, and a partial write reader that provides a read command to the non-volatile memory to read second data stored in the non-volatile memory, which is addressed based on the first address, before the first data is received through the host interface.

Description

Technology Field

[0001] The present invention relates to a storage device and a method for operating the same. Background Technology

[0002] NAND flash memory, a type of storage device, does not allow in-place writes when modifying stored data. Therefore, to modify data smaller than the mapping size—the data storage unit of NAND flash memory—a read-modify-write operation is required, which involves reading the existing data, merging it with the new data, and then moving it to another page.

[0003] However, since this Read-Modify-Write operation requires a significant amount of execution time, it is necessary to minimize it. The problem to be solved

[0004] The technical problem that the present invention aims to solve is to provide a storage device with improved operational performance.

[0005] Another technical problem that the present invention aims to solve is to provide a method for operating a storage device with improved operational performance.

[0006] The technical problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0007] A storage device according to some embodiments for achieving the above technical problem comprises a non-volatile memory in which data is written in mapping size units, and a storage controller that provides a command to the non-volatile memory, wherein the storage controller comprises a host interface that receives a write command from a host instructing to write first data of a first size smaller than the mapping size unit to a first address, and a partial write reader that provides a read command to the non-volatile memory to read second data stored in the non-volatile memory, which is addressed based on the first address, before the first data is received through the host interface.

[0008] A storage device according to some embodiments for achieving the above technical problem comprises a non-volatile memory in which data is written in mapping size units, and a storage controller that provides a command to the non-volatile memory, wherein the storage controller comprises a host interface that receives a write command instructing a host to write a first data of a first size smaller than a mapping size unit to a first address, and a memory interface that provides a memory command corresponding to the write command to the non-volatile memory, and wherein the storage controller provides a read command to the non-volatile memory through the memory interface to read a second data stored in the non-volatile memory, which is addressed based on the first address, before receiving the first data from the host through the host interface.

[0009] A method for operating a storage device according to some embodiments for achieving other technical objectives described above comprises providing a nonvolatile memory in which data is written in mapping size units, and a storage controller that provides a memory command to the nonvolatile memory, wherein the storage controller receives a write command instructing to write a first data of a first size at a first address, and in response to the first size being smaller than a mapping size unit, the storage controller provides a read command to the nonvolatile memory to read a second data stored in the nonvolatile memory, which is addressed based on the first address, before receiving the first data.

[0010] Specific details of other embodiments are included in the detailed description and drawings. Brief explanation of the drawing

[0011] FIG. 1 is a block diagram illustrating a memory system according to some embodiments. Figure 2 is a diagram showing the storage controller and non-volatile memory of the storage device of Figure 1 reconfigured. Figure 3 is a diagram illustrating the storage controller, memory interface, and non-volatile memory of Figure 1 reconfigured. FIG. 4 is an exemplary block diagram showing the non-volatile memory of FIG. 3. FIG. 5 is a diagram illustrating a 3D V-NAND structure that can be applied to a non-volatile memory according to some embodiments. Figure 6 is a block diagram of the processor of Figure 1. Figure 7 is a block diagram of the partial light leader of Figure 1. Figures 8 and 9 are drawings for explaining the function of the command distributor of Figure 7. FIGS. 10 and FIGS. 11 are drawings for explaining the operation of a storage device according to some embodiments. FIG. 12 is a drawing for explaining the effects of a storage device according to some embodiments. FIG. 13 is a diagram illustrating the operation of a storage device according to several other embodiments. FIGS. 14 and FIGS. 15 are drawings for explaining the operation of a storage device according to some other embodiments. FIG. 16 is a diagram illustrating the operation of a storage device according to some other embodiments. Specific details for implementing the invention

[0012] Hereinafter, embodiments according to the technical concept of the present invention will be described with reference to the attached drawings.

[0013] FIG. 1 is a block diagram illustrating a memory system according to some embodiments.

[0014] The memory system (10) may include a host device (100) and a storage device (200). Additionally, the storage device (200) may include a storage controller (210) and a non-volatile memory (NVM, 220). Additionally, in some embodiments, the host device (100) may include a host controller (110) and a host memory (120). The host memory (120) may function as a buffer memory for temporarily storing data to be transmitted to the storage device (200) or data transmitted from the storage device (200).

[0015] The storage device (200) may include storage media for storing data upon request from the host device (100). For example, the storage device (200) may include at least one of a Solid State Drive (SSD), embedded memory, and removable external memory. If the storage device (200) is an SSD, the storage device (200) may be a device that conforms to the non-volatile memory express (NVMe) standard.

[0016] If the storage device (200) is an embedded memory or an external memory, the storage device (200) may be a device that follows the UFS (universal flash storage) or eMMC (embedded multi-media card) standard. The host device (100) and the storage device (200) can each generate and transmit packets according to the adopted standard protocol.

[0017] When the non-volatile memory (220) of the storage device (200) includes flash memory, such flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, the storage device (200) may include various other types of non-volatile memory. For example, the storage device (200) may be equipped with Magnetic RAM (MRAM), Spin-Transfer Torque MRAM, Conductive Bridging RAM (CBRAM), Ferroelectric RAM (FeRAM), Phase RAM (PRAM), Resistive RAM, and various other types of memory.

[0018] In some embodiments, the host controller (110) and the host memory (120) may be implemented as separate semiconductor chips. Alternatively, in some embodiments, the host controller (110) and the host memory (120) may be integrated on the same semiconductor chip. As an example, the host controller (110) may be any one of a plurality of modules provided in an application processor, and such an application processor may be implemented as a System on Chip (SoC). Additionally, the host memory (120) may be an embedded memory provided within the application processor, or a non-volatile memory or memory module placed outside the application processor.

[0019] The host controller (110) can manage the operation of storing data in the buffer area (e.g., write data) in the non-volatile memory (220) or storing data in the non-volatile memory (220) (e.g., read data) in the buffer area.

[0020] The storage controller (210) may include a host interface (211), a memory interface (212), and a processor (213). Additionally, the storage controller (210) may further include a Flash Translation Layer (FTL, 214), a packet manager (215), a buffer memory (216), an error correction code (ECC, 217) engine, and an advanced encryption standard (AES, 218) engine.

[0021] The storage controller (210) may further include a working memory (not shown) on which a flash conversion layer (FTL, 214) is loaded, and data write and read operations for the non-volatile memory (220) may be controlled by the processor (213) executing the flash conversion layer (214).

[0022] The host interface (211) can transmit and receive packets with the host device (100). The packet transmitted from the host device (100) to the host interface (211) may include a command or data to be written to the non-volatile memory (220), and the packet transmitted from the host interface (211) to the host device (100) may include a response to the command or data read from the non-volatile memory (220).

[0023] The memory interface (212) can transmit data to be written to the non-volatile memory (220) or receive data read from the non-volatile memory (220). This memory interface (212) can be implemented to comply with standard protocols such as Toggle or ONFI.

[0024] The flash conversion layer (214) can perform various functions such as address mapping, wear-leveling, and garbage collection. Address mapping is an operation that converts a logical address received from a host into a physical address used to actually store data in the non-volatile memory (220). Wear-leveling is a technique to prevent excessive degradation of a specific block by ensuring that blocks in the non-volatile memory (220) are used evenly, and can be implemented, for example, through firmware technology that balances the erase counts of physical blocks. Garbage collection is a technique to secure usable capacity in the non-volatile memory (220) by copying the valid data of a block to a new block and then erasing the existing block.

[0025] The packet manager (215) can generate a packet according to the protocol of the interface agreed upon with the host device (100) or parse various information from a packet received from the host device (100). Additionally, the buffer memory (216) can temporarily store data to be written to the non-volatile memory (220) or data to be read from the non-volatile memory (220). The buffer memory (216) may be configured within the storage controller (210), but it may also be placed outside the storage controller (210).

[0026] The ECC engine (217) can perform error detection and correction functions for read data read from the non-volatile memory (220). More specifically, the ECC engine (217) can generate parity bits for the write data to be written to the non-volatile memory (220), and the parity bits thus generated can be stored in the non-volatile memory (220) together with the write data. When reading data from the non-volatile memory (220), the ECC engine (217) can correct errors in the read data using the parity bits read from the non-volatile memory (220) together with the read data, and output the read data with the errors corrected.

[0027] The AES engine (218) can perform at least one of the encryption and decryption operations on data input to the storage controller (210) using a symmetric-key algorithm.

[0028] The partial write reader (219) can determine whether the write command received from the host device (100) is a partial write command. If the write command received from the host device (100) is a partial write command, the partial write reader (219) can apply a read command to the non-volatile memory (220) to perform a partial write. Alternatively, if the write command received from the host device (100) is not a partial write command, the partial write reader (219) can not apply a read command to the non-volatile memory (220) and allow the processor (213) to perform the write command.

[0029] In some embodiments, the partial light reader (219) may be implemented in hardware and included in the storage controller (210). However, embodiments are not limited thereto, and the partial light reader (219) may also be implemented in software and executed by the processor (213).

[0030] The concept of the partial light command and the specific operation of the partial light leader (219) will be described later.

[0031] Figure 2 is a diagram showing the storage controller and non-volatile memory of the storage device of Figure 1 reconfigured.

[0032] Referring to FIG. 2, the storage device (200) may include a non-volatile memory (220) and a storage controller (210). The storage device (200) may support a plurality of channels (CH1 to CHm), and the non-volatile memory (220) and the storage controller (210) may be connected through the plurality of channels (CH1 to CHm). For example, the storage device (200) may be implemented as a storage device such as a Solid State Drive (SSD).

[0033] The non-volatile memory (220) may include a plurality of non-volatile memory devices (NVM11 to NVMmn). Each of the non-volatile memory devices (NVM11 to NVMmn) may be connected to one of a plurality of channels (CH1 to CHm) through a corresponding way. For example, the non-volatile memory devices (NVM11 to NVM1n) may be connected to a first channel (CH1) through ways (W11 to W1n), and the non-volatile memory devices (NVM21 to NVM2n) may be connected to a second channel (CH2) through ways (W21 to W2n). In an exemplary embodiment, each of the non-volatile memory devices (NVM11 to NVMmn) may be implemented as any memory unit capable of operating according to individual commands from the storage controller (210). For example, each of the non-volatile memory devices (NVM11 to NVMmn) may be implemented as a chip or a die, but the present invention is not limited thereto.

[0034] The storage controller (210) can transmit and receive signals to and from the non-volatile memory (220) through multiple channels (CH1~CHm). For example, the storage controller (210) can transmit commands (CMDa~CMDm), addresses (ADDRa~ADDRm), and data (DATAa~DATAm) to the non-volatile memory (220) through the channels (CH1~CHm), or receive data (DATAa~DATAm) from the non-volatile memory (220).

[0035] The storage controller (210) can select one of the non-volatile memory devices connected to the respective channel through each channel and transmit and receive signals with the selected non-volatile memory device. For example, the storage controller (210) can select a non-volatile memory device (NVM11) among the non-volatile memory devices (NVM11 to NVM1n) connected to the first channel (CH1). The storage controller (210) can transmit a command (CMDa), an address (ADDRa), and data (DATAa) to the selected non-volatile memory device (NVM11) through the first channel (CH1), or receive data (DATAa) from the selected non-volatile memory device (NVM11).

[0036] The storage controller (210) can transmit and receive signals to and from the non-volatile memory (220) in parallel through different channels. For example, the storage controller (210) can transmit a command (CMDb) to the non-volatile memory (220) through a second channel (CH2) while transmitting a command (CMDa) to the non-volatile memory (220) through a first channel (CH1). For example, the storage controller (210) can receive data (DATAb) from the non-volatile memory (220) through a second channel (CH2) while receiving data (DATAa) from the non-volatile memory (220) through a first channel (CH1).

[0037] The storage controller (210) can control the overall operation of the non-volatile memory (220). The storage controller (210) can control each of the non-volatile memory devices (NVM11–NVMmn) connected to the channels (CH1–CHm) by transmitting signals to the channels (CH1–CHm). For example, the storage controller (210) can control one of the selected non-volatile memory devices (NVM11–NVM1n) by transmitting a command (CMDa) and an address (ADDRa) to the first channel (CH1).

[0038] Each of the non-volatile memory devices (NVM11 to NVMmn) can operate under the control of the storage controller (210). For example, the non-volatile memory device (NVM11) can program data (DATAa) according to a command (CMDa), an address (ADDRa), and data (DATAa) provided through the first channel (CH1). For example, the non-volatile memory device (NVM21) can read data (DATAb) according to a command (CMDb) and an address (ADDRb) provided through the second channel (CH2), and transmit the read data (DATAb) to the storage controller (210).

[0039] FIG. 2 illustrates that a non-volatile memory (220) communicates with a storage controller (210) through m channels, and that the non-volatile memory (220) includes n non-volatile memory devices corresponding to each channel, but the number of channels and the number of non-volatile memory devices connected to one channel can be varied.

[0040] FIG. 3 is a diagram illustrating a reconfigured storage controller, memory interface, and non-volatile memory of FIG. 1. The memory interface (212) of FIG. 1 may include the controller interface circuit (212a) of FIG. 3.

[0041] The non-volatile memory (220) may include first to eighth pins (P11 to P18), a memory interface circuit (212b), a control logic circuit (510), and a memory cell array (520).

[0042] The memory interface circuit (212b) can receive a chip enable signal (nCE) from the storage controller (210) through the first pin (P11). The memory interface circuit (212b) can transmit and receive signals with the storage controller (210) through the second to eighth pins (P12 to P18) according to the chip enable signal (nCE). For example, when the chip enable signal (nCE) is in an enable state (e.g., low level), the memory interface circuit (212b) can transmit and receive signals with the storage controller (210) through the second to eighth pins (P12 to P18).

[0043] The memory interface circuit (212b) can receive a command latch enable signal (CLE), an address latch enable signal (ALE), and a write enable signal (nWE) from the storage controller (210) through the second to fourth pins (P12 to P14). The memory interface circuit (212b) can receive a data signal (DQ) from the storage controller (210) or transmit a data signal (DQ) to the storage controller (210) through the seventh pin (P17). A command (CMD), an address (ADDR), and data (DATA) can be transmitted through the data signal (DQ). For example, the data signal (DQ) can be transmitted through a plurality of data signal lines. In this case, the seventh pin (P17) may include a plurality of pins corresponding to the plurality of data signals.

[0044] The memory interface circuit (212b) can obtain a command (CMD) from a data signal (DQ) received during the enable period (e.g., high level state) of a command latch enable signal (CLE) based on the toggle timings of a write enable signal (nWE). The memory interface circuit (212b) can obtain an address (ADDR) from a data signal (DQ) received during the enable period (e.g., high level state) of an address latch enable signal (ALE) based on the toggle timings of a write enable signal (nWE).

[0045] In some embodiments, the write enable signal (nWE) may maintain a static state (e.g., high level or low level) and then toggle between the high level and the low level. For example, the write enable signal (nWE) may toggle during the interval in which a command (CMD) or an address (ADDR) is transmitted. Accordingly, the memory interface circuit (212b) may obtain the command (CMD) or the address (ADDR) based on the toggle timings of the write enable signal (nWE).

[0046] The memory interface circuit (212b) can receive a read enable signal (nRE) from the storage controller (210) through the fifth pin (P15). The memory interface circuit (212b) can receive a data strobe signal (DQS) from the storage controller (210) through the sixth pin (P16) or transmit a data strobe signal (DQS) to the storage controller (210).

[0047] In the data (DATA) output operation of the non-volatile memory (220), the memory interface circuit (212b) may receive a read enable signal (nRE) that toggles through the fifth pin (P15) before outputting the data (DATA). The memory interface circuit (212b) may generate a data strobe signal (DQS) that toggles based on the toggling of the read enable signal (nRE). For example, the memory interface circuit (212b) may generate a data strobe signal (DQS) that begins to toggle after a predetermined delay (e.g., tDQSRE) based on the toggling start time of the read enable signal (nRE). The memory interface circuit (212b) may transmit a data signal (DQ) containing data (DATA) based on the toggling timing of the data strobe signal (DQS). Accordingly, the data (DATA) can be aligned with the toggle timing of the data strobe signal (DQS) and transmitted to the storage controller (210).

[0048] In the data (DATA) input operation of the non-volatile memory (220), when a data signal (DQ) containing data (DATA) is received from the storage controller (210), the memory interface circuit (212b) may receive a data strobe signal (DQS) that toggles along with the data (DATA) from the storage controller (210). The memory interface circuit (212b) may acquire data (DATA) from the data signal (DQ) based on the toggle timing of the data strobe signal (DQS). For example, the memory interface circuit (212b) may acquire data (DATA) by sampling the data signal (DQ) at the rising edge and falling edge of the data strobe signal (DQS).

[0049] The memory interface circuit (212b) can transmit a ready / busy output signal (nR / B) to the storage controller (210) via the eighth pin (P18). The memory interface circuit (212b) can transmit status information of the non-volatile memory (220) to the storage controller (210) via the ready / busy output signal (nR / B). When the non-volatile memory (220) is in a busy state (i.e., when internal operations of the non-volatile memory (220) are being performed), the memory interface circuit (212b) can transmit a ready / busy output signal (nR / B) indicating the busy state to the storage controller (210). When the non-volatile memory (220) is in a ready state (i.e., when internal operations of the non-volatile memory (220) are not performed or are completed), the memory interface circuit (212b) can transmit a ready / busy output signal (nR / B) indicating the ready state to the storage controller (210).

[0050] For example, while the non-volatile memory (220) reads data (DATA) from the memory cell array (520) in response to a page read command, the memory interface circuit (212b) can transmit a ready / busy output signal (nR / B) indicating a busy state (e.g., low level) to the storage controller (210). For example, while the non-volatile memory (220) programs data (DATA) into the memory cell array (520) in response to a program command, the memory interface circuit (212b) can transmit a ready / busy output signal (nR / B) indicating a busy state to the storage controller (210).

[0051] The control logic circuit (510) can control various operations of the non-volatile memory (220) overall. The control logic circuit (510) can receive a command / address (CMD / ADDR) obtained from the memory interface circuit (212b). The control logic circuit (510) can generate control signals to control other components of the non-volatile memory (220) according to the received command / address (CMD / ADDR). For example, the control logic circuit (510) can generate various control signals to program data (DATA) into the memory cell array (520) or to read data (DATA) from the memory cell array (520).

[0052] The memory cell array (520) can store data (DATA) obtained from the memory interface circuit (212b) under the control of the control logic circuit (510). The memory cell array (520) can output the stored data (DATA) to the memory interface circuit (212b) under the control of the control logic circuit (510).

[0053] The memory cell array (520) may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. However, the present invention is not limited thereto, and the memory cells may be RRAM (Resistive Random Access Memory) cells, FRAM (Ferroelectric Random Access Memory) cells, PRAM (Phase Change Random Access Memory) cells, TRAM (Thyristor Random Access Memory) cells, or MRAM (Magnetic Random Access Memory) cells. Hereinafter, embodiments of the present invention will be described with a focus on embodiments in which the memory cells are NAND flash memory cells.

[0054] The storage controller (210) may include first to eighth pins (P21 to P28) and a controller interface circuit (212a). The first to eighth pins (P21 to P28) may correspond to the first to eighth pins (P11 to P18) of the non-volatile memory (220).

[0055] The controller interface circuit (212a) can transmit a chip enable signal (nCE) to the non-volatile memory (220) through the first pin (P21). The controller interface circuit (212a) can transmit and receive signals to and from the selected non-volatile memory (220) through the second to eighth pins (P22~P28) via the chip enable signal (nCE).

[0056] The controller interface circuit (212a) can transmit a command latch enable signal (CLE), an address latch enable signal (ALE), and a write enable signal (nWE) to the non-volatile memory (220) through the second to fourth pins (P22 to P24). The controller interface circuit (212a) can transmit a data signal (DQ) to the non-volatile memory (220) or receive a data signal (DQ) from the non-volatile memory (220) through the seventh pin (P27).

[0057] The controller interface circuit (212a) can transmit a data signal (DQ) containing a command (CMD) or an address (ADDR) to the non-volatile memory (220) along with a toggling write enable signal (nWE). The controller interface circuit (212a) can transmit a data signal (DQ) containing a command (CMD) to the non-volatile memory (220) by transmitting a command latch enable signal (CLE) having an enable state, and can transmit a data signal (DQ) containing an address (ADDR) to the non-volatile memory (220) by transmitting an address latch enable signal (ALE) having an enable state.

[0058] The controller interface circuit (212a) can transmit a read enable signal (nRE) to the non-volatile memory (220) through the fifth pin (P25). The controller interface circuit (212a) can receive a data strobe signal (DQS) from the non-volatile memory (220) or transmit a data strobe signal (DQS) to the non-volatile memory (220) through the sixth pin (P26).

[0059] In the operation of outputting data (DATA) from the non-volatile memory (220), the controller interface circuit (212a) can generate a toggling read enable signal (nRE) and transmit the read enable signal (nRE) to the non-volatile memory (220). For example, the controller interface circuit (212a) can generate a read enable signal (nRE) that changes from a fixed state (e.g., high level or low level) to a toggling state before the data (DATA) is output. Accordingly, a toggling data strobe signal (DQS) can be generated in the non-volatile memory (220) based on the read enable signal (nRE). The controller interface circuit (212a) can receive a data signal (DQ) containing data (DATA) along with the toggling data strobe signal (DQS) from the non-volatile memory (220). The controller interface circuit (212a) can acquire data (DATA) from the data signal (DQ) based on the toggle timing of the data strobe signal (DQS).

[0060] In the operation of inputting data (DATA) to the non-volatile memory (220), the controller interface circuit (212a) can generate a toggling data strobe signal (DQS). For example, the controller interface circuit (212a) can generate a data strobe signal (DQS) that changes from a fixed state (e.g., high level or low level) to a toggling state before transmitting the data (DATA). Based on the toggling timings of the data strobe signal (DQS), the controller interface circuit (212a) can transmit a data signal (DQ) containing the data (DATA) to the non-volatile memory (220).

[0061] The controller interface circuit (212a) can receive a ready / busy output signal (nR / B) from the non-volatile memory (220) through the eighth pin (P28). The controller interface circuit (212a) can determine the status information of the non-volatile memory (220) based on the ready / busy output signal (nR / B).

[0062] FIG. 4 is an exemplary block diagram showing the non-volatile memory of FIG. 3.

[0063] Referring to FIG. 4, the non-volatile memory (220) may include a control logic circuit (510), a memory cell array (520), a page buffer section (550), a voltage generator (530), and a row decoder (540). Although not shown in FIG. 4, the non-volatile memory (220) may further include a memory interface circuit (212b) shown in FIG. 3, and may also further include column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, etc.

[0064] The control logic circuit (510) can control various operations within the non-volatile memory (220) overall. The control logic circuit (510) can output various control signals in response to a command (CMD) and / or an address (ADDR) from the memory interface circuit (212b in FIG. 3). For example, the control logic circuit (510) can output a voltage control signal (CTRL_vol), a row address (X-ADDR), and a column address (Y-ADDR).

[0065] The memory cell array (520) may include a plurality of memory blocks (BLK1 to BLKz) (z is a positive integer), and each of the plurality of memory blocks (BLK1 to BLKz) may include a plurality of memory cells. The memory cell array (520) may be connected to a page buffer unit (550) via bit lines (BL) and may be connected to a row decoder (540) via word lines (WL), string select lines (SSL), and ground select lines (GSL).

[0066] In an exemplary embodiment, the memory cell array (520) may include a three-dimensional memory cell array, and the three-dimensional memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells connected to word lines stacked vertically on a substrate. U.S. Patent Publication No. 7,679,133, U.S. Patent Publication No. 8,553,466, U.S. Patent Publication No. 8,654,587, U.S. Patent Publication No. 8,559,235, and U.S. Patent Application Publication No. 2011 / 0233648 are incorporated herein by reference. In an exemplary embodiment, the memory cell array (520) may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include a plurality of NAND strings arranged along row and column directions.

[0067] The page buffer unit (550) may include a plurality of page buffers (PB1 to PBn) (where n is an integer greater than or equal to 3), and the plurality of page buffers (PB1 to PBn) may each be connected to memory cells through a plurality of bit lines (BL). The page buffer unit (550) may select at least one bit line among the bit lines (BL) in response to a column address (Y-ADDR). The page buffer unit (550) may operate as a write driver or a sense amplifier depending on the operation mode. For example, during a program operation, the page buffer unit (550) may apply a bit line voltage corresponding to the data to be programmed with the selected bit line. During a read operation, the page buffer unit (550) may detect the current or voltage of the selected bit line to detect the data stored in the memory cell.

[0068] The voltage generator (530) can generate various types of voltages to perform program, read, and erase operations based on the voltage control signal (CTRL_vol). For example, the voltage generator (530) can generate a program voltage, a read voltage, a program verification voltage, an erase voltage, etc. as a word line voltage (VWL).

[0069] The row decoder (540) can select one of a plurality of word lines (WL) and one of a plurality of string select lines (SSL) in response to a row address (X-ADDR). For example, during a program operation, the row decoder (540) can apply a program voltage and a program verification voltage to the selected word line, and during a read operation, it can apply a read voltage to the selected word line.

[0070] FIG. 5 is a diagram illustrating a 3D V-NAND structure that can be applied to a non-volatile memory according to some embodiments. When a storage module of a storage device is implemented as a 3D V-NAND type flash memory, each of the plurality of memory blocks constituting the storage module can be represented by an equivalent circuit as shown in FIG. 5.

[0071] The memory block (BLKi) illustrated in FIG. 5 represents a three-dimensional memory block formed in a three-dimensional structure on a substrate. For example, a plurality of memory NAND strings included in the memory block (BLKi) may be formed in a direction perpendicular to the substrate.

[0072] Referring to FIG. 5, a memory block (BLKi) may include a plurality of memory NAND strings (NS11 to NS33) connected between bit lines (BL1, BL2, BL3) and a common source line (CSL). Each of the plurality of memory NAND strings (NS11 to NS33) may include a string select transistor (SST), a plurality of memory cells (MC1, MC2, ..., MC8), and a ground select transistor (GST). FIG. 7 illustrates that each of the plurality of memory NAND strings (NS11 to NS33) includes eight memory cells (MC1, MC2, ..., MC8), but is not necessarily limited thereto.

[0073] A string select transistor (SST) can be connected to corresponding string select lines (SSL1, SSL2, SSL3). Multiple memory cells (MC1, MC2, ..., MC8) can each be connected to corresponding gate lines (GTL1, GTL2, ..., GTL8). The gate lines (GTL1, GTL2, ..., GTL8) may correspond to word lines, and some of the gate lines (GTL1, GTL2, ..., GTL8) may correspond to dummy word lines. A ground select transistor (GST) can be connected to corresponding ground select lines (GSL1, GSL2, GSL3). A string select transistor (SST) is connected to corresponding bit lines (BL1, BL2, BL3), and a ground select transistor (GST) can be connected to a common source line (CSL).

[0074] Word lines of the same height (e.g., WL1) are connected in common, and ground select lines (GSL1, GSL2, GSL3) and string select lines (SSL1, SSL2, SSL3) can be separated. FIG. 9 is illustrated as a memory block (BLK) connected to eight gate lines (GTL1, GTL2, ..., GTL8) and three bit lines (BL1, BL2, BL3), but is not necessarily limited thereto.

[0075] Figure 6 is a block diagram of the processor of Figure 1.

[0076] Referring to FIGS. 1 and FIGS. 6, the processor (213) may include a first processor (213a) and a second processor (213b).

[0077] The first processor (213a) may request and receive data from the host device (100) to perform a write operation when a write command is provided from the host device (100). Additionally, the first processor (213a) may store the data received from the host device (100) in a buffer memory (216). In some embodiments, the first processor (213a) may include a host core, but the embodiments are not limited thereto.

[0078] The second processor (213b) can write data stored in the buffer memory (216) to the non-volatile memory (220) to execute a write command received from the host device (100). In some embodiments, the second processor (213b) may include a flash core, but the embodiments are not limited thereto.

[0079] FIG. 7 is a block diagram of the partial light reader of FIG. 1. FIG. 8 and FIG. 9 are drawings to explain the function of the command distributor of FIG. 7.

[0080] Referring to FIGS. 1 and FIGS. 7, the partial light leader (219) may include a command distributor (219a) and an off-road engine (219b).

[0081] The command distributor (219a) can determine whether a write command received from the host device (100) is a partial write command. Here, a partial write command means a write command for data that is smaller than the storage unit (mapping size) of the non-volatile memory (220).

[0082] For example, referring to FIG. 8, when a non-volatile memory (220) stores data in four write units (WU), if a write command having a size of four write units (WU) is applied from a host device (100), this is not a partial write command.

[0083] For example, if one write unit (WU) is 1024 bytes, the non-volatile memory (220) stores data in units of 4096 bytes (mapping size), and if a write command is issued from the host device (100) to write data having a size of 4096 bytes, this is not a partial write command. Here, the mapping size of the non-volatile memory (220) is exemplified as 4096 bytes, but this is merely an example and the embodiments are not limited thereto. The mapping size of the non-volatile memory (220) can be modified and implemented as many times as 1024 bytes, 2048 bytes, 8192 bytes, etc.

[0084] In this way, when a write command is received from the host device (100) to write data of the same size as the mapping size of the non-volatile memory (220), the storage controller (210) simply writes the data provided by the host device (100) to the non-volatile memory (220).

[0085] However, referring to FIG. 9, when a light command having the size of one, two, or three light units (WU) is applied from the host device (100), this is a partial light command.

[0086] That is, if a write command with a size of 1024 bytes is applied from the host device (100), a write command with a size of 2048 bytes is applied, or a write command with a size of 3072 bytes is applied, this is a partial write command.

[0087] Referring to FIGS. 1, 6 and 7, the command distributor (219a) determines whether the write command received from the host device (100) is a partial write command that must write data having a size smaller than the mapping size of the non-volatile memory (220).

[0088] If it is not a partial light command, the command distributor (219a) instructs only the first processor (213a) to request data from the host device (100) for receiving data from the host device (100).

[0089] However, in the case of a partial light command, the command distributor (219a) instructs the first processor (213a) to request data from the host device (100) for receiving data from the host device (100), and instructs the off-road engine (219b) that a data read is required for the partial light. A more detailed explanation regarding this will be provided later.

[0090] Referring to FIGS. 1 and FIGS. 7, the off-road engine (219b) may include an address converter (219c) and a flash manager (219d).

[0091] The address converter (219c) can, for example, look up the physical address of the non-volatile memory (220) corresponding to the logical address received from the host device (100) by referring to the mapping table stored in the FTL (214).

[0092] The flash manager (219d) can apply a read command to the non-volatile memory (220) to read data of the non-volatile memory (220) addressed to a physical address sought from the address converter (219).

[0093] In this embodiment, the flash manager (219d) is implemented separately from the processor (213) so that it can apply a read command to the non-volatile memory (220) without using the processor (213). That is, in this embodiment, the flash manager (219d) and the processor (213) can apply a read command to the non-volatile memory (220) independently of each other.

[0094] Hereinafter, the operation of the storage device (200) will be described in more detail with reference to FIGS. 10 and FIGS. 11.

[0095] FIGS. 10 and FIGS. 11 are drawings for explaining the operation of a storage device according to some embodiments.

[0096] Referring to FIGS. 1, FIGS. 10 and FIGS. 11, a storage controller (210) receives a write command from a host device (100) (S100).

[0097] A light command provided from the host device (100) can be provided to the command distributor (219a) of the storage controller (210).

[0098] The command distributor (219a) of the storage controller (210) determines whether the write command received from the host device (100) is a partial write command (S110).

[0099] If the write command received from the host device (100) is not a partial write command, the command distributor (219a) instructs the first processor (213a) to request data from the host device (100) for a write operation to the non-volatile memory (220), in which case the offload engine (291b) does not operate.

[0100] In the following, an example is given in which the mapping size of the non-volatile memory (220) is four write units (WU), and a write command received from the host device (100) instructs to write a corresponding to one write unit (WU).

[0101] If the light command received from the host device (100) is a partial light command, the command distributor (219a) instructs the off-road engine (291b) that a data read is required for the partial light (S112).

[0102] The address converter (219c) of the off-road engine (291b) searches for the physical address of the non-volatile memory (220) based on the logical address received via the write command (S114).

[0103] For example, if a write command received from a host device (100) instructs to write data a to a logical address L1, the address converter (219c) of the offload engine (291b) searches for a physical address P1 of a non-volatile memory (220) corresponding to the logical address L1 by referring to a mapping table (214a).

[0104] In some embodiments, the mapping table (214a) may be included in the FTL (214), but the embodiments are not limited thereto.

[0105] The flash manager (219d) of the off-road engine (291b) applies a read command instructing to read data addressed to physical address P1 into the non-volatile memory (220) (S120).

[0106] As explained above, in this embodiment, the flash manager (219d) applies a read command to the non-volatile memory (220) without using the second processor (213b) which performs the function of applying a command to the non-volatile memory (220) from the processor (213).

[0107] Meanwhile, if the write command received from the host device (100) is a partial write command, the command distributor (219a) instructs the first processor (213a) to request data from the host device (100) for a write operation to the non-volatile memory (220) (S122).

[0108] In response, the first processor (213a) requests data from the host device (100) (S130) and receives data a from the host device (100) (S140). Upon receiving data a, the first processor (213a) stores data a in the data buffer (216a). Then, it notifies the second processor (213b) that data a has been received.

[0109] In some embodiments, the data buffer (216a) may be included in the buffer memory (216), but the embodiments are not limited thereto, and the data buffer (216a) may be placed outside the storage controller (210).

[0110] In response to a read command authorized by the flash manager (219d), data d, e, f, g is read from the non-volatile memory (220) (S150). Here, the data is four because, as previously explained, the mapping size of the non-volatile memory (220) is four write units (WU). In some embodiments, the non-volatile memory (220) can provide data d, e, f, g to the storage controller (210) through the data input / output operation described above with reference to FIG. 3.

[0111] The read data d, e, f, g is stored in the data buffer (216a) by the flash manager (219d). At this time, the flash manager (219d) does not store all of the read d, e, f, g in the data buffer (216a), but rather stores only e, f, g in the data buffer (216a) by referring to the sector bitmap.

[0112] That is, the flash manager (219d) recognizes through the sector bitmap that one of the four light units (WU) of the data buffer (216a) is an area where data a received from the host device (100) will be stored, and stores data e, f, and g only in the remaining three light units (WU).

[0113] Through this process, data to be used to execute a partial write command received from the host device (100) is stored in the data buffer (216a) without an overwrite or data copy process.

[0114] The second processor (213b) checks whether data capable of performing a partial write is prepared in the flash manager (219d) (S155), and if the data is prepared, applies a write command instructing to write data a, e, f, g to a location addressed to P2 in the non-volatile memory (220) (S160). In some embodiments, the storage controller (210) may provide data a, e, f, g to the non-volatile memory (220) through the data input / output operation described above with reference to FIG. 3.

[0115] When data a, e, f, g is written to a location addressed to P2 of the non-volatile memory (220) in this way, the physical address corresponding to the logical address L1 in the mapping table (214a) can be updated from P1 to P2.

[0116] FIG. 12 is a diagram illustrating the effects of a storage device according to some embodiments. A of FIG. 12 is a diagram illustrating the partial write operation of a storage controller (210 of FIG. 1) that does not include the partial write reader (219 of FIG. 1) described above, and B is a diagram illustrating the partial write operation of a storage controller (210 of FIG. 1) that does not include the partial write reader (219 of FIG. 1) described above.

[0117] First, referring to A in FIG. 12, the storage controller receives a partial write command (S1) and requests and receives partial write data (a in FIG. 11) from the host device (S2). Then, the storage controller reads the data stored in the non-volatile memory (S3) and updates the data buffer with the read data (S4). After that, the storage controller performs a partial write operation on the non-volatile memory (S5).

[0118] However, referring to Fig. 12B, immediately after the storage controller receives a partial write command (S11), it immediately performs a read operation on the data stored in the non-volatile memory (S13). Then, the operation (S12) of requesting and receiving partial write data (a in Fig. 11) from the host device is performed independently and in parallel with the read operation (S13) on the data stored in the non-volatile memory. Accordingly, the start time of the partial write operation (S15) performed on the non-volatile memory is significantly shortened, and the completion time of the partial write operation (S15) is also shortened. Accordingly, the speed of the partial write operation of the storage device is improved, and the operational performance of the storage device can be improved.

[0119] FIG. 13 is a diagram illustrating the operation of a storage device according to several other embodiments. Below, descriptions that overlap with the previously described embodiments will be omitted, and the differences will be explained in detail.

[0120] Referring to FIG. 13, in this embodiment, after read data (d, e, f, g of FIG. 10) is received (S140) from a non-volatile memory (220), data (a of FIG. 10) is received (S150) from a host device (100).

[0121] In this case, data e, f, and g are stored first in the data buffer (216a), and data a can be stored later.

[0122] FIGS. 14 and FIGS. 15 are drawings for explaining the operation of a storage device according to some other embodiments.

[0123] Referring to FIGS. 14 and 15, the storage controller (210) receives a write command from the host device (100) (S200).

[0124] A light command provided from the host device (100) can be provided to the command distributor (219a) of the storage controller (210).

[0125] The command distributor (219a) of the storage controller (210) determines whether the write command received from the host device (100) is a partial write command (S210).

[0126] If the light command received from the host device (100) is a partial light command, the command distributor (219a) instructs the off-road engine (291b) that a data read is required for the partial light, and at the same time instructs the first processor (213a) to request data from the host device (100) for a write operation to the non-volatile memory (220) (S212).

[0127] In response, the first processor (213a) requests data from the host device (100) (S220), and the address converter (219c) of the offload engine (291b) searches for the physical address of the non-volatile memory (220) based on the logical address received via the write command (S214).

[0128] Accordingly, a data request (S220) transmitted from the storage controller (210) to the host device (100) may be performed before a read command authorization operation (S230) provided from the storage controller (210) to the non-volatile memory (220).

[0129] The subsequent read command authorization operation (S230), the operation of receiving data a from the host device (100) (S240), the operation of reading data d, e, f, g from the non-volatile memory (220) in response to the read command authorized by the flash manager (219d) (S250), the operation of the second processor (213b) checking whether data capable of performing a partial write to the flash manager (219d) is prepared (S255), and the operation of authorizing a write command instructing to write data a, e, f, g to the non-volatile memory (220) (S260) are similar to the previously described embodiment, so a redundant description is omitted.

[0130] FIG. 16 is a diagram illustrating the operation of a storage device according to several other embodiments. In the following description as well, explanations that overlap with the previously described embodiments will be omitted, and the differences will be explained in detail.

[0131] Referring to FIG. 16, in this embodiment, after read data (d, e, f, g of FIG. 15) is received (S240) from a non-volatile memory (220), data (a of FIG. 15) is received (S250) from a host device (100).

[0132] In this case, data e, f, and g are stored first in the data buffer (216a), and data a can be stored later.

[0133] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0134] 100: Host device 200: Storage device 210: Storage Controller 219: Partial Light Leader 220: Non-volatile memory

Claims

Claim 1 A storage device comprising: a non-volatile memory in which data is written in mapping size units; and a storage controller that provides a command to the non-volatile memory, wherein the storage controller comprises: a host interface that receives a write command from a host instructing to write first data of a first size smaller than the mapping size unit to a first address; and a partial write reader that provides a read command to the non-volatile memory to read second data stored in the non-volatile memory, which is addressed based on the first address, before the first data is received through the host interface. Claim 2 In claim 1, the partial light reader comprises a storage device including a command distributor that determines whether the first size is smaller than the mapping size unit, and an offload engine that receives the output of the command distributor and provides the read command to the non-volatile memory. Claim 3 A storage device according to claim 2, further comprising a mapping table in which a second address of the non-volatile memory corresponding to the first address is stored, wherein the offload engine includes an address converter that searches for the second address by referring to the mapping table, and a flash manager that provides the read command to the non-volatile memory using the second address searched by the address converter. Claim 4 A storage device according to paragraph 2, further comprising a processor and a buffer memory, wherein the processor requests and receives the first data from the host, and then stores the first data in the buffer memory, and the offload engine stores the read second data in the buffer memory. Claim 5 In paragraph 4, the second data is read from the non-volatile memory in the mapping size unit, and the offload engine stores the third data, excluding the data of the first size from the read second data, in the buffer memory. Claim 6 In claim 5, the storage device comprises a first processor that requests and receives the first data from the host and then stores the first data in the buffer memory, and a second processor that writes the first data stored in the buffer memory and the third data to the non-volatile memory. Claim 7 A storage device according to claim 1, further comprising a buffer memory in which data is stored in the mapping size unit, and wherein a portion of the first data and the second data is stored in the buffer memory in correspondence with the mapping size unit. Claim 8 A storage device comprising: a non-volatile memory in which data is written in mapping size units; and a storage controller that provides a command to the non-volatile memory, wherein the storage controller includes a host interface that receives a write command instructing a host to write first data of a first size smaller than the mapping size unit to a first address, and a memory interface that provides a memory command corresponding to the write command to the non-volatile memory, and wherein the storage controller provides a read command to the non-volatile memory through the memory interface to read second data stored in the non-volatile memory, which is addressed based on the first address, before receiving the first data from the host through the host interface. Claim 9 In claim 8, the storage device wherein the storage controller provides the read command to the non-volatile memory through the memory interface, and then transmits a request signal to the host through the host interface to request the first data. Claim 10 In claim 9, the storage controller is a storage device that receives the second data from the non-volatile memory before receiving the first data from the host. Claim 11 In claim 8, the storage device, wherein the storage controller transmits a request signal requesting the first data to the host via the host interface before providing the read command to the non-volatile memory via the memory interface. Claim 12 In claim 11, the storage controller is a storage device that receives the second data from the non-volatile memory before receiving the first data from the host. Claim 13 A method for operating a storage device comprising: a nonvolatile memory in which data is written in mapping size units; a storage controller that provides a memory command to the nonvolatile memory; receiving a write command that instructs the storage controller to write a first data of a first size to a first address; and, in response to the first size being smaller than the mapping size unit, providing the nonvolatile memory with a read command to read a second data stored in the nonvolatile memory, which is addressed based on the first address, before the storage controller receives the first data. Claim 14 A method of operating a storage device according to claim 13, further comprising that the storage controller does not provide the read command to the non-volatile memory in response to the first size being the same as the mapping size unit. Claim 15 A method of operating a storage device according to claim 13, further comprising the storage controller searching for a second address of the non-volatile memory based on the first address, wherein the read command is a command to read the second data stored in the non-volatile memory addressed to the second address. Claim 16 A method of operating a storage device according to claim 13, further comprising the storage controller receiving the second data in the mapping size unit from the non-volatile memory, storing the first data in a buffer memory, and storing some of the received second data in the buffer memory. Claim 17 A method of operating a storage device according to claim 13, further comprising the storage controller providing the read command to the non-volatile memory, transmitting a request signal requesting the first data, and receiving the first data. Claim 18 A method of operating a storage device according to claim 17, further comprising receiving the second data from the non-volatile memory before the storage controller receives the first data. Claim 19 A method of operating a storage device according to claim 13, further comprising the storage controller transmitting a request signal requesting the first data, providing the read command to the non-volatile memory, and receiving the first data. Claim 20 A method of operating a storage device according to claim 19, further comprising the storage controller receiving the first data before receiving the second data from the non-volatile memory.

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