Apparatus and method for parallel processing

Abstract

The present invention relates to a parallel computing device capable of error detection and error correction. According to one aspect of the present invention, a method of operating a parallel computing device comprising a plurality of cores may include: a step of searching for a core (hereinafter referred to as a zero core) in which at least one of the operands of a multiplication operation performed in each of the plurality of cores for processing a first instruction is zero; a step of performing a multiplication operation in each of the plurality of cores, wherein at least one zero core performs a multiplication operation on operands identical to those of a core (hereinafter referred to as a non-zero core) in which the operand is not zero; and a step of determining whether there is an error in the non-zero core by comparing the operation result of at least one zero core with the operation result of the non-zero core.

Description

Technology Field

[0001] The present invention relates to a parallel computing device capable of error detection and error correction. Background Technology

[0002] A parallel computing device including multiple cores divides a single task into multiple threads and processes parallel operations for multiple threads using multiple cores. In cases where multiplication operations are performed on most cores, there is a problem that multiple cores must perform operations collectively even when the result of the multiplication operation is 0 because at least one of the operands is 0. Prior art literature

[0003] (Patent Literature) Republic of Korea Published Patent No. 10-2020-0096102 “Parallel Processing of Computational Models” The problem to be solved

[0004] The objective of the present invention is to provide a technology for detecting and correcting computational errors in parallel computation processing.

[0005] In addition, the objective of the present invention is to provide a technology for detecting and correcting computational errors in parallel computation processing involving operations on sparse matrices, such as the training of artificial neural network models.

[0006] In addition, the objective of the present invention is to provide a technology for detecting and correcting computational errors in parallel computation processing of a GPU.

[0007] In addition, the objective of the present invention is to provide a technology for detecting the occurrence of failure in a plurality of cores for parallel computation processing and isolating the cores where the failure occurred. means of solving the problem

[0008] According to one aspect of the present invention, a method of operating a parallel computing device comprising a plurality of cores may include: a step of searching for a core (hereinafter referred to as a zero core) in which at least one of the operands of a multiplication operation performed in each of the plurality of cores for processing a first instruction is zero; a step of performing a multiplication operation in each of the plurality of cores, wherein at least one zero core performs a multiplication operation on operands identical to those of a core (hereinafter referred to as a non-zero core) in which the operand is not zero; and a step of determining whether there is an operation error by comparing the operation result of at least one zero core with the operation result of a non-zero core.

[0009] In one embodiment, the step of determining whether there is an operation error may determine that there is an error in the operation performed on the non-zero core or the zero core if the operation result of at least one zero core does not match the operation result of the non-zero core.

[0010] In one embodiment, the method of operating a parallel computing device may further include: a step in which, if it is determined that there is an error in the operation performed on a non-zero core or a zero core, at least three cores including a non-zero core and a zero core among a plurality of cores re-perform a multiplication operation on the operands operated by the non-zero core; and a step of determining whether the non-zero core or the zero core is faulty based on the operation results of at least three cores.

[0011] In one embodiment, the step of determining whether a non-zero core or a zero core is faulty may determine that the non-zero core or the zero core is faulty if the operation result of the non-zero core or the zero core among at least three cores does not match the operation result of another core.

[0012] In one embodiment, the method of operating a parallel computing device may further include the step of, when it is determined that there is a failure in a non-zero core or a zero core, setting the operation to be performed on the non-zero core or zero core determined to be faulty to be performed on another zero core when processing an instruction to be processed (hereinafter, a second instruction) after processing a first instruction.

[0013] In one embodiment, the step of re-performing the multiplication operation may, if it is determined that there is an error in the operation of a non-zero core or zero core, not start processing the instruction to be processed after the first instruction (hereinafter, the second instruction) and re-perform the multiplication operation.

[0014] In one embodiment, the method of operating a parallel computing device may further include the step of setting the operation result of the two or more zero cores as the operation result of the non-zero core when it is determined that there is an error in the operation of the non-zero core or zero core, or when the operation results of two or more zero cores match each other.

[0015] In one embodiment, the first instruction may include a multiplication operation on a sparse matrix.

[0016] In one embodiment, the step of searching for a core in which at least one is 0 (hereinafter, zero core) can be performed by performing a logical AND operation on the operators to be processed in each of the plurality of cores to determine whether at least one operator is 0.

[0017] In one embodiment, the step of searching for a core in which at least one operand is 0 (hereinafter, zero core) can be performed by checking whether at least one operator among the operators to be processed in each of the plurality of cores of the first instruction is 0, thereby searching for the zero core.

[0018] According to another aspect of the present invention, a parallel computing device may include: a plurality of cores for performing parallel computing processing; a zero core search unit for searching for a core (hereinafter, zero core) in which at least one of the operands of a multiplication operation performed in each of the plurality of cores for processing a first instruction is zero; an operation control unit for controlling the multiplication operation to be performed in each of the plurality of cores, wherein at least one zero core performs a multiplication operation on operands identical to those of a core (hereinafter, non-zero core) in which the operand is not zero; and an error determination unit for determining whether there is an error in the non-zero core or the zero core by comparing the operation result of at least one zero core with the operation result of the non-zero core.

[0019] According to another aspect of the present invention, a method of operating a parallel computing device may include: receiving an instruction including N threads; assigning N threads to each of a plurality of cores; searching for at least one thread (hereinafter, zero thread) among the N threads in which at least one of the operands of a multiplication operation is 0; reassigning at least one core (hereinafter, zero core) that has been assigned at least one zero thread to process a non-zero thread that is identical to the core (non-zero core) to which a non-zero thread (hereinafter, non-zero thread) is matched; and determining whether there is an operation error based on the result of a multiplication operation of at least one zero core and the result of a multiplication operation of a non-zero core according to the reassignment. Effects of the invention

[0020] According to one aspect of the present invention, it is possible to detect and correct operation errors in parallel operation processing.

[0021] In addition, according to another aspect of the present invention, it is possible to detect and correct operation errors in parallel operation processing including operations on sparse matrices, such as training of an artificial neural network model.

[0022] In addition, according to another aspect of the present invention, it is possible to detect and correct computation errors in parallel computation processing of a GPU.

[0023] In addition, according to another aspect of the present invention, it is possible to detect the occurrence of failure in a plurality of cores for parallel computation processing and to isolate the core in which the failure occurred. Brief explanation of the drawing

[0024] FIG. 1 is a block diagram of a parallel computing device according to one embodiment of the present invention. FIG. 2 is a flowchart of an operation method of a parallel computing device according to an embodiment of the present invention. FIG. 3 is a diagram illustrating the overall flow of SM operations of a GPU to which a parallel computing device according to one embodiment of the present invention is applied. FIG. 4 is a diagram illustrating an example of a parallel computing device searching for a zero core according to an embodiment of the present invention. FIG. 5 is a diagram illustrating an example of a parallel computing device according to an embodiment of the present invention allocating threads to each core. FIG. 6 is a diagram illustrating the error detection process of a parallel computing device according to one embodiment of the present invention. FIG. 7 is a diagram illustrating an example of allocating threads for error detection according to an embodiment of the present invention. FIG. 8 is a diagram illustrating error detection and correction according to an embodiment of the present invention. FIG. 9 is a block diagram of a parallel computing device according to another embodiment of the present invention. Specific details for implementing the invention

[0025] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the scope of the present invention is defined only by the claims.

[0026] In describing the embodiments of the present invention, specific descriptions of known functions or configurations will be omitted unless actually necessary for describing the embodiments of the present invention. Furthermore, the terms described below are defined in consideration of the functions in the embodiments of the present invention, and these may vary depending on the intentions or practices of the user or operator. Therefore, such definitions should be based on the content throughout this specification.

[0027] Terms such as '… unit', '… unit' used below refer to a unit that processes at least one function or operation, and this may be implemented in hardware or software, or a combination of hardware and software.

[0029] FIG. 1 is a block diagram of a parallel computing device according to one embodiment of the present invention.

[0030] Referring to FIG. 1, a parallel computing device (1000) may include a plurality of cores (1100), a zero core search unit (1200), a computing control unit (1300), and an error determination unit (1400).

[0031] Multiple cores (1100) are each independent processing units and can perform parallel operations to process a single instruction.

[0032] In one embodiment, a plurality of cores (1100) may refer to a plurality of cores (1100) included in a GPU, etc.

[0033] In one embodiment, a plurality of cores (1100) can perform parallel operations on instructions by processing N threads as a unit (e.g., warp), with each of the plurality of cores (1100) processing operations on one thread.

[0034] In one embodiment, a plurality of cores (1100) can process instructions using a SIMT (Single Instruction Multiple Thread) method.

[0035] In one embodiment, the command may include a multiplication operation on a sparse matrix. Specifically, the command may include an operation on a feature matrix that has passed through the Rectified Linear Unit (ReLU) activation function of an artificial neural network model, such as a Deep Neural Network (DNN) or a Convolutional Neural Network (CNN); that is, a matrix containing many zero elements. Artificial neural network models, such as Deep Neural Network (DNN) models or Convolutional Neural Network (CNN) models, use activation functions to learn complex non-linear representations. The most widely used activation function is the Rectified Linear Unit (ReLU). The ReLU activation function can change all negative values ​​in the activation feature matrix to zero. Due to this characteristic, the activation feature matrix passed through the ReLU function becomes a sparse matrix with many zero values. Additionally, pruning techniques used for model lightweighting set low-importance weights in the model to zero. Consequently, since deep neural networks primarily perform sparse matrix multiplication operations due to two factors—the ReLU activation function and pruning—the parallel processing device according to the present invention can also be applied to the training and use of artificial neural network models that include operations on sparse matrices. Furthermore, the Multiply-Accumulate (MAC) operation, which is mainly used for matrix multiplication, is defined as D = A * B + C. The sparse matrix multiplication operation sets the operands A and B, which are required for the multiplication of many MAC operations, to zero, thereby not changing the final result (D = 0 + C = D) regardless of whether a MAC operation is performed. Therefore, since the sparsity occurring in DNNs can reduce computational efficiency by creating unnecessary operations, the present invention makes it possible to utilize these unnecessary operations for error correction.

[0036] The zero core search unit (1200) can search for at least one core (hereinafter, zero core) among a plurality of cores (1100) that performs a multiplication operation including an operator in which at least one of the operands of the multiplication operation is 0, in order to perform parallel operation of instructions.

[0037] In one embodiment, the zero core search unit (1200) can search for at least one zero core by performing a logical AND operation between operands assigned to each of the plurality of cores (1100).

[0038] In one embodiment, the zero core search unit (1200) searches for a thread (hereinafter, zero thread) in which at least one of the operands of a multiplication operation is zero among N (a natural number greater than or equal to 2) threads assigned to each of the plurality of cores (1100), and based on the search result, the core assigned to the zero thread can be determined as the zero core, and the core assigned to a thread that is not a zero thread (non-zero thread) can be determined as the non-zero core.

[0039] The operation control unit (1300) can control the overall operation of the parallel operation device (1000) for processing instructions.

[0040] In one embodiment, the operation control unit (1300) can control the operation of the plurality of cores (1100) to process instructions in parallel at the plurality of cores (1100). Specifically, the operation control unit (1300) can divide the instructions into N threads corresponding to the number of cores and control each of the plurality of cores (1100) to process the N threads in parallel.

[0041] In one embodiment, the operation control unit (1300) can control at least one zero core to perform a multiplication operation on operands that are the same as the operands of a core that is not zero (hereinafter, non-zero core).

[0042] In one embodiment, the operation control unit (1300) can control the operation to perform a multiplication operation on operands identical to the operands of the multiplication operation to be performed in one non-zero core in processing the first instruction. Specifically, when performing parallel operation of the first instruction, if the operands to be processed in the first core (zero core) are A1 and B1 and at least one of them is 0, and the operands to be processed in the second core are A2 and B2 and both are not 0, the result of the multiplication operation of the first core is 0, so in order to use the operation operation of the first core to detect whether there is an error in the operation of the second core, the first core can be controlled to perform a multiplication operation on operands A2 and B2 identical to those of the second core.

[0043] In one embodiment, if the operation control unit (1300) determines that there is an error in the operation, it can control the operation of operands for which the operation error occurred to be performed again in three or more cores, including non-zero cores and zero cores, where the operation error occurred.

[0044] In one embodiment, if the operation control unit (1300) determines that there is an error in the operation, it may stop the input of the instruction to be processed (hereinafter, the second instruction) after processing the first instruction, and control the operation of operands to be processed in the non-zero core to be performed again in each of the three or more cores including the non-zero core and the zero core that performed the operation.

[0045] In one embodiment, the operation control unit (1300) can assign threads to be processed in each of the plurality of cores (1100). Additionally, even if a zero thread is already assigned to a zero core, the operation control unit (1300) can assign a non-zero thread assigned to a non-zero core to at least one zero core.

[0046] The error determination unit (1400) can determine whether there is an error in the operation performed in the core based on the operation result of the non-zero core and the operation result of at least one zero core.

[0047] In one embodiment, the error determination unit (1400) may determine that there is an error in the operation result for an operand performed in the non-zero core or the zero core if the operation result performed in the non-zero core and the operation result performed in the zero core do not match.

[0048] In one embodiment, the error determination unit (1400) may determine that there is an error in the operand operation performed in the non-zero core if the operation result of the non-zero core does not match the operation result of at least one zero core.

[0049] In one embodiment, the error determination unit (1400) can determine that there is no error in the operation between the non-zero core and the zero core if the operation result of the non-zero core matches the operation result of the zero core. At this time, the error determination unit (1400) can output 0, which is the result of the multiplication operation of the operands to be processed, as the operation result of the zero core.

[0050] In one embodiment, the error determination unit (1400) can correct an error in the operation of a core with a different operation result by replacing the operation result of the two or more cores with the operation result of the core with a different operation result when the operation results of two or more cores match each other and the operation result of one core is different from the operation result of two or more cores.

[0051] In one embodiment, the error determination unit (1400) can determine whether one core is faulty based on the operation result of a core that has operated on three or more of the same operands.

[0052] In one embodiment, the error determination unit (1400) may determine that a failure, i.e. a mechanical defect, has occurred in the one core whose result does not match the result of two or more cores if, even after performing the multiplication operation again on the operands for which an error occurred, the result of the operation of one of the three cores does not match the result of the operation of two or more cores. This is because if an operation error occurs repeatedly, it is highly likely that a permanent defect has occurred in the corresponding core.

[0053] In one embodiment, the error determination unit (1400) may, after re-performing the multiplication operation on the operands where an error occurred, use the non-zero core operation result as the result of the current operation if the result of the operation of the non-zero core matches the result of the operation of two or more non-zero cores. Afterward, the error determination unit (1400) may receive a second instruction to be processed after the first instruction.

[0054] Additionally, the error determination unit (1400) can perform error detection and error correction using a voting method. For example, if the error determination unit (1400) performs operations on the same operand in three or more cores but different operation results are obtained, the operation result obtained with the largest number can be determined as the operation result for the operand.

[0056] FIG. 2 is a flowchart of an operation method of a parallel computing device according to an embodiment of the present invention.

[0057] Hereinafter, the above method is described as an example performed by the parallel computing device (1000) shown in FIG. 1.

[0058] In step S2100, the parallel computing device (1000) can receive an instruction (hereinafter referred to as the first instruction) to perform a parallel operation through a plurality of cores (1100).

[0059] In one embodiment, the command may include a multiplication operation on a sparse matrix. Specifically, the command may include an operation on a feature matrix that has passed through the activation function ReLU (Rectified Linear Unit) of an artificial neural network model, such as a Deep Neural Network (DNN) or a Convolutional Neural Network (CNN), that is, a matrix containing many zero elements.

[0060] In step S2200, the parallel computing device (1000) may search for at least one core (hereinafter, zero core) among the plurality of cores (1100) that performs a multiplication operation including an operator in which at least one of the operands of the multiplication operation is 0, in order to perform a parallel operation of the first instruction.

[0061] In one embodiment, the parallel computing device (1000) can search for at least one zero core by performing a logical AND operation (logical AND operation) between operands to be assigned to each of the plurality of cores (1100).

[0062] In one embodiment, the parallel computing device (1000) may determine whether to perform an error detection and correction operation based on the number of zero cores and the number of non-zero cores (hereinafter, non-zero cores) according to the search results of zero cores. Since the present invention is based on processing a sparse matrix in which 0 is greater than 1, the following describes a case in which an error detection and correction operation is performed when processing instructions.

[0063] In step S2300, the parallel computing device (1000) can perform a multiplication operation on operands identical to the operands of the multiplication operation to be performed in one non-zero core in processing the first instruction. Specifically, in parallel computing the first instruction, if the operands to be processed in the first core (zero core) are A1 and B1 and at least one of them is 0, and the operands to be processed in the second core are A2 and B2 and both are not 0, the result of the multiplication operation of the first core is 0, so in order to use the operation of the first core to detect whether there is an error in the operation of the second core, the first core can perform a multiplication operation on operands A2 and B2 identical to those of the second core.

[0064] In step S2400, the parallel computing device (1000) can determine whether there is an error in the operation performed on the non-zero core or the zero core based on the operation result of the non-zero core and the operation result of at least one zero core.

[0065] In one embodiment, if the operation result performed in the non-zero core and the operation result performed in the zero core do not match, the parallel operation device (1000) may determine that there is an error in the operation result for the operand performed in the non-zero core or the zero core.

[0066] In one embodiment, the parallel computing device (1000) may determine that there is an error in the computation performed on the non-zero core or the zero core if the computation result of the non-zero core does not match the computation result of at least one zero core.

[0067] In one embodiment, the parallel computing device (1000) can determine that there are no errors in the operation between the non-zero core and the zero core if the operation result of the non-zero core matches the operation result of the zero core. At this time, the parallel computing device (1000) can output 0, which is the result of the multiplication operation of the operands originally to be processed, as the operation result of the zero core.

[0068] In one embodiment, the parallel computing device (1000) can correct errors in the computation of cores with different computation results by replacing the computation results of the two or more cores with the computation results of the cores with different computation results when the computation results of two or more cores match each other and the computation result of one core differs from the computation results of two or more cores.

[0069] In step S2500, if the parallel computing device (1000) determines that there is an error in the computation, it can re-perform the computation of the operands on which the computation error occurred in each of the three or more cores, including the non-zero core and the zero core where the computation error occurred.

[0070] In one embodiment, if the parallel computing device (1000) determines that there is an error in the operation of the core, it stops the input of the instruction to be processed (hereinafter, the second instruction) after processing the first instruction, and can re-perform the operation of the operands to be processed in the non-zero core in each of the three or more cores including the non-zero core and the zero core that performed the operation.

[0071] In step S2600, the parallel computing device (1000) can determine whether the core is faulty based on the result of the operation of the core that has operated on three or more of the same operands.

[0072] In one embodiment, the parallel computing device (1000) may determine that a failure, i.e. a mechanical defect, has occurred in the one core whose result does not match the result of two or more cores even after the multiplication operation on the operands that have an error has been performed again, if the result of one of the three cores does not match the result of two or more cores. This is because if an operation error has occurred repeatedly, it is highly likely that a permanent defect has occurred in the corresponding core.

[0073] In one embodiment, the parallel computing device (1000) can perform error detection and error correction using a voting method. For example, if the error determination unit (1400) performs operations on the same operand in three or more cores but different operation results are obtained, the operation result obtained with the largest number can be determined as the operation result for the operand.

[0074] In one embodiment, after the parallel computing device (1000) performs a multiplication operation again on operands where an error occurred, if the result of the operation of a non-zero core matches the result of the operation of two or more non-zero cores, the result of the operation performed this time can be used as the result of the operation of a non-zero core. Afterwards, the parallel computing device (1000) can receive a second instruction to be processed after the first instruction.

[0075] In step S2700, if the parallel computing device (1000) determines that a failure has occurred in a non-zero core, it may modify the core pairing information used for distributing the operator to be processed in each of the multiple cores (1100) to process instructions in parallel.

[0076] In one embodiment, the parallel computing device (1000) can modify the core pairing information so that, when processing a subsequently input instruction, the operator to be processed in the core determined to be defective is processed in another zero core.

[0077] In step S2800, the parallel computing device (1000) receives a second instruction and can perform parallel computation on the second instruction through multiple cores (1100) based on modified core pairing information. That is, when processing the second instruction, the parallel computing device (1000) can perform computation on another zero core for the operation to be processed on the core determined to be defective.

[0079] FIG. 3 is a diagram illustrating the overall flow of SM operations of a GPU to which a parallel computing device according to one embodiment of the present invention is applied.

[0080] Referring to FIG. 3, multiple instructions included in the Register File are each stored together with instruction information and operands in the Operand Collector, and the instruction information and operands stored in each Operand Collector (buffer) are moved to the Processing Core by the command of Issue. The Mask generator can search for a zero thread among multiple threads using the instructions and operands stored in the Operand Collector. The Shuffling Unit can transfer an operand assigned to one non-zero core to at least one zero core based on core pairing information. The Error Detection Unit can determine whether an error occurred in the operation of the non-zero core by comparing the operation results of the non-zero core and the zero core that performed the same operation on the same non-zero thread among the operation results for each thread of the multiple cores (1100). If the Error Detection Unit determines that there is no error in the operation performed on the non-zero core or the zero core because the operation results of the non-zero core and the zero core match, the operation result of the non-zero core can be used as the result of the operation performed on the non-zero thread, and the zero core can be used as 0 as the operation result and transferred to Write Back. This is because, during parallel processing, the result of the zero thread that should have been computed on the zero core would have been 0. If the Error Detection Unit determines that an error has occurred in the computation of a non-zero core, it can transmit the error info. of the non-zero core to the SparseFT Controller. Since the SparseFT Controller must re-process the previously executed instruction to correct the error that occurred in the non-zero core computation, it can request Issue to resend the instruction that was previously sent.When an instruction is re-transmitted, the Shuffling Unit can pass the same thread to two or more zero cores as the non-zero thread to be processed by the non-zero core where the operation error occurred. The Error Detection Unit can determine whether a non-zero core is faulty based on the re-operation results of the non-zero core and two or more zero cores. If the operation results of the non-zero core and two or more zero cores match, the Error Detection Unit can use the operation result of the non-zero core that performed the re-operation to pass to WriteBack as the operation result of the non-zero core. This is because the error that occurred during the first operation of the non-zero core did not occur during the re-operation. If the operation results of two or more zero cores match each other but do not match the operation result of the non-zero core, the Error Detection Unit can determine that a fault, i.e., a permanent defect, has occurred in the non-zero core. The Error Detection Unit can transmit faulty core info. of the non-zero core to the SparseFT Controller. At this time, the Error Detection Unit can use the operation results of two or more zero cores that match each other as the operation results of non-zero cores and transmit them to Write Back. The SparseFT Controller can store faulty core info. of non-zero cores in the Fault Map. Based on the faulty core info. stored in the Fault Map, the SparseFT Controller can modify the core pairing info. to perform operations on the faulty core on another core (non-zero core).

[0082] FIG. 4 is a diagram illustrating an example of a parallel computing device searching for a zero core according to an embodiment of the present invention.

[0083] Referring to FIG. 4, the Mask generator can perform a logical AND operation (logical AND operation) using an AND gate on the operands (Reg2, Reg3) of the multiplication operation among the operands (Reg1, Reg2, Reg3) of each thread. The result of this logical AND operation (Mask Vector) can be transmitted to the SparseFT Controller. In this case, if the result of the logical AND operation is 0, it corresponds to a zero thread in which at least one of the operands of the multiplication operation is 0.

[0085] FIG. 5 is a diagram illustrating an example of a parallel computing device according to an embodiment of the present invention allocating threads to each core.

[0086] Referring to FIG. 5 (a), the parallel computing device (1000) can perform operations on threads in each of the multiple cores (1100) as already allocated, without performing thread reallocation for error detection when the number of zero threads (or zero cores) is less than or equal to a preset standard, that is, when the number of zero threads is less than or equal to the number of non-zero threads. In other words, the parallel computing device (1000) may not perform an error detection operation when the number of zero threads is less than the number of non-zero threads.

[0087] Referring to FIG. 5 (b), the parallel computing device (1000) can make Core 0 and Core 3 perform the same operations as Core 1 and Core 2, respectively assigned zero threads (0), and Core 1 and Core 3, respectively assigned non-zero threads (A, B), so that Core 0 performs the same operations as Core 1 and Core 3 perform the same operations as Core 2. Subsequently, the parallel computing device (1000) can determine whether there is an error in the computation of Core 1 by comparing the computation results of Core 0 and Core 1, and can determine whether there is an error in the computation of Core 2 by comparing the computation results of Core 2 and Core 3.

[0088] Referring to FIG. 5 (c), if an error occurs in the operation of Core 2 (Core 2) according to FIG. 5 (b), the parallel computing device (1000) may reallocate the thread (B) assigned to Core 2 (Core 2) to all Core 0 (Core 0) to Core 3 (Core 3) and allow Core 0 (Core 0) to Core 3 (Core 3) to perform operations on the thread (B). The parallel computing device (1000) may correct the error in Core 2 (Core 2) by comparing the operation results of Core 0 (Core 0) to Core 3 (Core 3). The parallel computing device (1000) can correct the error in Core 2 by replacing the results of Core 0, Core 1, and Core 3 with the results of Core 2, since the results of Core 0, Core 1, and Core 3 match each other and the results of Core 2 do not match the results of Core 2, which indicates that a failure has occurred in Core 2.

[0089] Referring to FIG. 5 (d), if the parallel computing device (1000) determines that a failure has occurred in Core 2, in processing subsequent instructions, it can assign the non-zero threads to be assigned to Core 2 to Core 3, which will be assigned zero threads, thereby allowing Core 3 to perform the non-zero threads that Core 2 needs to perform. Subsequently, the parallel computing device (1000) can use the result of the calculation performed in Core 3 as the result of the calculation performed in Core 2.

[0091] FIG. 6 is a diagram illustrating the error detection process of a parallel computing device according to one embodiment of the present invention.

[0092] Referring to FIG. 6, the parallel processing unit (1000) may assign a first non-zero core (Processing Core 0) and a first zero core (Processing Core 2) to process a first non-zero thread, and assign a second non-zero core (Processing Core 1) and a second zero core (Processing Core 3) to process a second non-zero thread. The Error Detection Unit may use core pairing information to compare whether the results of the first non-zero core (Processing Core 0) and the first zero core (Processing Core 2) processing the first non-zero thread match each other, and whether the results of the second non-zero core (Processing Core 1) and the second zero core (Processing Core 3) processing the second non-zero thread match each other. At this time, the Error Detection Unit may use a MUX (not shown) to transmit the results of each core's processing to a comparator (not shown) and use the comparator to compare the results of the core's processing. The Error Detection Unit can determine that an error has occurred in the operation result of an operation core by using the result of comparing the operation results of the cores in the comparator, if the operation results do not match. The Error Detection Unit can transmit information about the core where the error occurred to the Controller (SparseFT Controller).

[0094] FIG. 7 is a diagram illustrating an example of allocating threads for error detection according to an embodiment of the present invention.

[0095] Referring to FIG. 7, an example is illustrated in which multiple cores (1100) of a parallel computing device (1000) perform operations. The parallel computing device (1000) may distribute and assign multiple threads to each of the multiple cores (1100). Among the threads assigned to each of Core 1 to Core 8, the threads assigned to Core 1, Core 4, Core 6, and Core 7 correspond to zero threads in which at least one operand is 0. When a zero core processing a zero thread is found, the parallel computing device (1000) may copy a thread (operand) identical to the thread assigned to the non-zero core and assign it to the zero core so that the zero core performs the same operation as the non-zero core in duplicate.

[0097] FIG. 8 is a diagram illustrating error detection and correction according to an embodiment of the present invention.

[0098] Referring to FIG. 8 (a), after performing the operation as illustrated in FIG. 7, the parallel computing device (1000) can determine whether the operation results of the non-zero core and the zero core that performed the operation on the same thread match each other. Since the operation results of Core 3 and Core 4 do not match each other, the parallel computing device (1000) can determine that an error occurred in the operation of Core 3, which is a non-zero core.

[0099] Referring to FIG. 8 (b), the parallel computing device (1000) may assign the same thread to other cores, namely Cores 1 to 4, to perform operations on each of Cores 1 to 4 in order to correct an operation error of Core 3. If the operation result of Core 3 does not match Cores 1, 2, and 4, the parallel computing device (1000) may determine that a failure has occurred in Core 3.

[0100] Referring to FIG. 8 (c), the parallel computing device (1000) can modify the core pairing information based on the failure information of core 3, thereby allowing the threads that core 3 needs to process to be assigned to another zero core when processing future instructions.

[0102] FIG. 9 is a block diagram of a parallel computing device according to another embodiment of the present invention.

[0103] As illustrated in FIG. 9, the parallel computing device (1000) may include at least one of a processor (9100), memory (9200), storage unit (9300), user interface input unit (9400), and user interface output unit (9500), and these may communicate with each other via a bus (9600). Additionally, the parallel computing device (1000) may also include a network interface (9700) for connecting to a network. The processor (9100) may be a CPU or semiconductor device that executes processing instructions stored in memory (9200) and / or storage (9300). The memory (9200) and storage unit (9300) may include various types of volatile / non-volatile memory media. For example, the memory may include ROM (9240) and RAM (9250).

[0105] The device described above may be implemented as a hardware component, a software component, and / or a combination of a hardware component and a software component. For example, the device and components described in the embodiments may be implemented using one or more general-purpose or special-purpose computers, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable array (FPA), a programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing unit may execute an operating system (OS) and one or more software applications executed on the operating system.

[0106] Additionally, the processing unit may access, store, manipulate, process, and generate data in response to the execution of software. For ease of understanding, the processing unit may be described as being used as a single unit, but those skilled in the art will understand that the processing unit may include multiple processing elements and / or multiple types of processing elements. For example, the processing unit may include multiple processors or one processor and one controller. In addition, other processing configurations, such as parallel processors, are also possible.

[0107] Software may include computer programs, code, instructions, or a combination of one or more of these, and may configure a processing unit to operate as desired or command the processing unit independently or collectively. Software and / or data may be permanently or temporarily embodied in any type of machine, component, physical device, virtual equipment, computer storage medium or device, or transmitted signal wave so as to be interpreted by the processing unit or to provide instructions or data to the processing unit. Software may be distributed over networked computer systems and may be stored or executed in a distributed manner. Software and data may be stored on one or more computer-readable recording media.

[0109] The above description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications and variations within the scope of the essential quality of the present invention. Accordingly, the embodiments disclosed in this specification are intended to explain, not limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments. The scope of protection of the present invention shall be interpreted by the claims below, and all technical concepts within the equivalent scope shall be interpreted as being included within the scope of rights of the present invention. Explanation of the symbols

[0110] 1000: Parallel processing unit 1100: Multiple cores 1200: Zero Core Search Unit 1300: Operation Control Unit 1400: Error Judgment Unit

Claims

Claim 1 A method of operating a parallel computing device comprising a plurality of cores, comprising: a step of searching for a core (hereinafter referred to as a zero core) in which at least one of the operands of a multiplication operation performed in each of the plurality of cores for processing a first instruction is zero; a step of performing a multiplication operation in each of the plurality of cores, wherein at least one zero core performs a multiplication operation on operands identical to those of a core (hereinafter referred to as a non-zero core) in which the operand is not zero; and a step of determining whether there is an operation error by comparing the operation result of the at least one zero core with the operation result of the non-zero core; wherein if it is determined that there is an error in the operation performed in the non-zero core or the zero core, at least three cores among the plurality of cores, including the non-zero core and the zero core, re-perform a multiplication operation on the operands operated by the non-zero core; and a step of determining whether the non-zero core is faulty based on the operation result of the at least three cores. A method comprising, in the step of re-performing a multiplication operation on operands computed by the non-zero core, if it is determined that there is an error in the operation performed by the non-zero core or the zero core, a step of assigning the non-zero thread assigned to the non-zero core to at least one zero core, even if a zero thread is assigned to the zero core. Claim 2 In claim 1, the step of determining whether there is an operation error is a method of determining that there is an error in the operation performed on the non-zero core or the zero core if the operation result of the at least one zero core and the operation result of the non-zero core do not match. Claim 3 delete Claim 4 In claim 1, the step of determining whether the non-zero core or the zero core is faulty is a method of determining that the non-zero core or the zero core is faulty if the operation result of the non-zero core or the zero core among the at least three cores does not match the operation result of the other cores. Claim 5 A method according to claim 4, further comprising the step of, when it is determined that there is a failure in the non-zero core or the zero core, setting the instruction to be processed after processing the first instruction (hereinafter, the second instruction) to be executed on another zero core to be executed on the non-zero core or zero core determined to be faulty. Claim 6 A method according to claim 1, wherein the step of re-performing the multiplication operation is, if it is determined that there is an error in the operation performed in the non-zero core or the zero core, the multiplication operation is re-performed without starting the processing of the instruction to be processed after the first instruction (hereinafter, the second instruction). Claim 7 The method of claim 1 further comprises the step of, if it is determined that there is an error in the operation performed on the non-zero core or the zero core, and if the operation results of two or more cores match each other, setting the operation results of the two or more cores as the operation results of the non-zero core or the zero core. Claim 8 A method according to claim 1, wherein the first instruction comprises a multiplication operation on a sparse matrix. Claim 9 In claim 1, the step of searching for a core in which at least one is 0 (hereinafter, zero core) is a method of searching for the zero core by checking whether at least one operator among the operators to be processed in each of the plurality of cores among the first instruction is 0. Claim 10 In claim 9, the step of searching for at least one core that is 0 (hereinafter, zero core) is a method of checking whether at least one operator is 0 by performing a logical AND operation on operators to be processed in each of the plurality of cores. Claim 11 A plurality of cores performing parallel computation processing; a zero core search unit for a core (hereinafter referred to as a zero core) in which at least one of the operands of a multiplication operation performed in each of the plurality of cores for processing a first instruction is zero; an operation control unit that controls the multiplication operation to be performed in each of the plurality of cores, wherein at least one zero core performs a multiplication operation on operands identical to those of a core (hereinafter referred to as a non-zero core) whose operand is not zero; and an error determination unit that determines whether there is an operation error by comparing the operation result of the at least one zero core with the operation result of the non-zero core; wherein, if the operation control unit determines that there is an error in the operation performed in the non-zero core or the zero core, at least three cores among the plurality of cores, including the non-zero core and the zero core, control the non-zero core to re-perform a multiplication operation on the operands operated by the non-zero core, and the error determination unit determines whether the non-zero core or the zero core is faulty based on the operation result of the at least three cores, and the operation A parallel computing device that assigns a thread to be processed at each of the plurality of cores, and assigns a non-zero thread assigned to a non-zero core to at least one of the zero cores even if a zero thread has already been assigned to the zero core. Claim 12 Parallel computing device according to claim 11, wherein the error determination unit determines that there is an error in the operation performed on the non-zero core or the zero core if the operation result of the at least one zero core and the operation result of the non-zero core do not match. Claim 13 delete Claim 14 A parallel computing device according to claim 11, wherein the error determination unit determines that there is a fault in the non-zero core or the zero core if the operation result of the non-zero core or the zero core among the at least three cores does not match the operation result of the other cores. Claim 15 A parallel computing device according to claim 14, wherein, when it is determined that there is a failure in the non-zero core or the non-zero core, in processing an instruction to be processed after processing the first instruction (hereinafter, the second instruction), the operation to be performed on the non-zero core or zero core determined to be faulty is set to be performed on another zero core. Claim 16 A parallel computing device according to claim 11, wherein the control unit controls the multiplication operation to be performed again without starting the processing of the instruction to be processed after the first instruction (hereinafter, the second instruction) if it is determined that there is an error in the operation performed in the non-zero core or the zero core. Claim 17 A parallel computing device according to claim 11, wherein the control unit sets the operation result of the two or more zero cores as the operation result of the non-zero core when it is determined that there is an error in the operation performed on the non-zero core or the zero core, or when the operation results of two or more zero cores match each other. Claim 18 In paragraph 11, the above first instruction is a parallel processing device comprising a multiplication operation for a sparse matrix. Claim 19 In claim 11, the zero core search unit searches for the zero core by checking whether at least one operator among the operators to be processed in each of the plurality of cores in the first instruction is zero, a parallel computing device. Claim 20 In claim 19, the zero core search unit is a parallel processing device that checks whether at least one operator is zero by performing a logical AND operation on operators to be processed at each of the plurality of cores. Claim 21 A computer-readable recording medium storing a computer program, wherein the computer program, when executed by a processor, comprises: a step of searching for a core (hereinafter referred to as a zero core) in which at least one of the operands of a multiplication operation performed in each of a plurality of cores for processing a first instruction is zero; a step of performing a multiplication operation in each of the plurality of cores, wherein at least one zero core performs a multiplication operation on operands identical to those of a core (hereinafter referred to as a non-zero core) in which the operand is not zero; and a step of determining whether there is an operation error by comparing the operation result of the at least one zero core with the operation result of the non-zero core. A computer-readable recording medium comprising instructions for causing the processor to perform a method including, wherein if it is determined that there is an error in the operation performed on the non-zero core or the zero core, at least three cores including the non-zero core and the zero core among the plurality of cores re-perform a multiplication operation on the operands operated by the non-zero core, and determine whether the non-zero core is faulty based on the operation result of the at least three cores, and if it is determined that there is an error in the operation performed on the operands operated by the non-zero core during the process of re-performing the multiplication operation on the operands operated by the non-zero core, even if a zero thread is assigned to the zero core, assign the non-zero thread assigned to the non-zero core to at least one zero core. Claim 22 The method comprises: receiving an instruction including N threads; assigning the N threads to each of a plurality of cores; searching for at least one thread among the N threads in which at least one of the operands of a multiplication operation is 0 (hereinafter, zero thread); reassigning at least one core (hereinafter, zero core) assigned to at least one zero thread to process the non-zero thread that is identical to the core (non-zero core) to which the non-zero thread (hereinafter, non-zero thread) is matched; and determining whether an error has occurred in the operation of the non-zero core based on the result of the multiplication operation of at least one zero core and the result of the multiplication operation of the non-zero core according to the reassignment; and if it is determined that there is an error in the operation performed by the non-zero core or the zero core, at least three cores among the plurality of cores, including the non-zero core and the zero core, re-perform the multiplication operation on the operands operated by the non-zero core. A parallel processing method comprising: a step of determining whether the non-zero core is faulty based on the operation results of at least three cores; and, in the step of re-performing a multiplication operation on operands operated by the non-zero core, if it is determined that there is an error in the operation performed by the non-zero core or the zero core, a step of assigning the non-zero thread assigned to the non-zero core to at least one zero core, even if a zero thread is assigned to the zero core.

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