NAND flash memory device capable of selectively erasing one flash memory cell and operating method thereof

Abstract

A flash memory device according to the present invention comprises: a cell array including a first NAND string including a plurality of flash memory cells in which control gates are connected to a plurality of word lines and a string selection switch that connects a plurality of flash memory cells to a first bit line according to the control of a first string selection line; and a control circuit that controls a first erase operation for erasing one selected flash memory cell among a plurality of flash memory cells of the first NAND string, wherein the control circuit sets the voltage between the first bit line and the first string selection line to a first voltage that generates GIDL in the string selection switch, and sets the control gate voltage of the flash memory cell to be erased and the control gate voltage of the flash memory cell excluding the flash memory cell to be erased among a plurality of flash memory cells differently.

Description

Technology Field

[0001] The present invention relates to a method of operation of a NAND flash memory device capable of erasing data stored in one selected flash memory cell among a plurality of flash memory cells included in a NAND string. Background Technology

[0002] In conventional NAND flash memory devices using a floating gate or SONOS (silicon / oxide / nitride / oxide / silicon) structure, writing and erasing are free at the single device level.

[0003] However, in a NAND flash memory device containing a NAND string, write operations are possible at the flash memory cell level, but erase operations are performed at the block level rather than the flash memory cell level.

[0004] In other words, in conventional NAND flash memory devices, write protection conditions for other flash memory cells exist during write operations, but erase protection conditions for other flash memory cells do not exist during erase operations.

[0005] This problem is the same not only in two-dimensional NAND flash memory devices but also in three-dimensional NAND flash memory devices.

[0006] In conventional 3D structured NAND flash memory devices, an erasure method using GIDL (Gate Induced Drain Leakage) is used.

[0007] However, in conventional NAND flash memory devices, conditions for preventing the erasure of other flash memory cells during the process of performing an erase operation on a selected flash memory cell have not been developed.

[0008] If write operations are performed on a single flash memory cell basis and erase operations are performed on a block basis, data failure may occur in a specific flash memory cell if the threshold voltage characteristics of that flash memory cell are different.

[0009] To address this, error correction technology can be adopted, but this requires the addition of significant hardware and software resources.

[0010] Since it is impossible to erase specific flash memory cells where errors have occurred, erasing must be done in block units; consequently, the number of write / erase cycles increases, accelerating the rate at which the characteristics of the flash memory cells degrade.

[0011] This problem can occur more frequently as the level of data stored in a single flash memory cell increases, and becomes a more significant issue in cases where the accuracy of the data stored in each flash memory cell is critical, such as in neural network computation circuits that store weights using NAND flash memory devices. Prior art literature

[0012] (Patent Document 0001) US 7907450 B2 (Patent Document 0002) US 9711229 B1 The problem to be solved

[0013] The present invention provides a method of operation for a flash memory device capable of selectively erasing one cell in a NAND flash memory device having a NAND string structure.

[0014] The present invention provides a method of operation for a flash memory device capable of selectively erasing one cell in a three-dimensional NAND flash memory device. means of solving the problem

[0015] A flash memory device according to one embodiment of the present invention comprises: a cell array including a first NAND string comprising a plurality of flash memory cells, each having a gate connected to a plurality of word lines, and a string selection switch that connects a plurality of flash memory cells to a first bit line according to the control of a first string selection line; and a control circuit that controls a first erase operation for erasing one selected flash memory cell among a plurality of flash memory cells of the first NAND string, wherein the control circuit sets the voltage between the first bit line and the first string selection line to a first voltage that generates GIDL in the string selection switch, and sets the gate voltage of the flash memory cell to be erased and the gate voltage of the flash memory cell excluding the flash memory cell to be erased among a plurality of flash memory cells differently.

[0016] A method of operating a flash memory device according to one embodiment of the present invention, in a flash memory device for erasing one selected flash memory cell included in a NAND string, comprises: a step of reading a threshold voltage of the selected flash memory cell; a step of performing an erasure operation on the selected flash memory cell when the read threshold voltage is greater than an upper limit; and a step of performing a write operation on the selected flash memory cell when the read threshold voltage is less than a lower limit.

[0017] A method of operating a flash memory device according to one embodiment of the present invention is a method of operating a flash memory device for erasing any one selected flash memory cell included in a NAND string, comprising: a step of performing a write operation on the selected flash memory cell when the data stored in the selected flash memory cell is changed to first data; and a step of performing an erase operation on the selected flash memory cell when the data stored in the selected flash memory cell is changed to second data.

[0018] A method of operating a flash memory device according to one embodiment of the present invention is a method of operating a flash memory device having a block comprising a plurality of NAND strings each comprising a plurality of flash memory cells having control gates connected to a plurality of word lines, the method comprising: a step of performing a write operation on a certain number of flash memory cells included in the block; a step of reading a threshold voltage of a selected flash memory cell among a certain number of flash memory cells; and a step of performing an erase operation or a write operation on a selected flash memory cell by comparing the read threshold voltage with a target value.

[0019] A method of operating a flash memory device according to one embodiment of the present invention is a method of operating a flash memory device for erasing any one selected flash memory cell included in a NAND string, comprising: a step of reading a turn-on current flowing through the selected flash memory cell; and a step of comparing the read turn-on current with a target value and performing an erase operation or a write operation on the selected flash memory cell. Effects of the invention

[0020] Using this technology, a specific single flash memory cell can be erased without performing block-unit erase operations.

[0021] By utilizing this technology, the erase operation for the entire flash memory cell can be reduced, thereby improving overall operational performance and preventing the shortening of the flash memory cell's lifespan.

[0022] By using this technology, data can be accurately written to specific cells and errors can be easily corrected without adding complex circuits such as ECC. Brief explanation of the drawing

[0023] FIG. 1 is a block diagram showing a flash memory device according to an embodiment of the present invention. FIGS. 2 and 3 are circuit diagrams showing flash memory erasure operation conditions of a flash memory device according to an embodiment of the present invention. FIG. 4 is a diagram showing the flash memory cell erasure operation conditions of a flash memory device according to an embodiment of the present invention. FIG. 5 is a graph illustrating the flash memory cell erasure operation conditions of a flash memory device according to an embodiment of the present invention. Figure 6 is a graph showing the relationship between the GIDL voltage and the change in threshold voltage of a flash memory cell. Figure 7 is a graph showing the relationship between the erase voltage and the change in threshold voltage of a flash memory cell. Figure 8 is a graph showing the relationship between the unselected bitline voltage and the change in threshold voltage of the flash memory cell. Figure 9 is a graph showing the relationship between the location of a flash memory cell and the amount of change in threshold voltage during a flash memory cell erase operation. FIGS. 10 and FIGS. 11 are flowcharts illustrating the operation of a flash memory device according to an embodiment of the present invention. Specific details for implementing the invention

[0024] Embodiments of the present invention are disclosed below with reference to the attached drawings.

[0025] FIG. 1 is a block diagram showing a flash memory device (1) according to one embodiment of the present invention.

[0026] A flash memory device (1) includes a cell array (100) comprising a plurality of NAND strings (200), a word line control circuit (10) for controlling a word line (WL) of the cell array (100), a bit line control circuit (20) for controlling a bit line (BL) of the cell array (100), a string selection control circuit (30) for controlling a string selection line (DSL) of the cell array (100), an additional string selection control circuit (40) for controlling an additional string selection line (SSL) of the cell array (100), and a source line control circuit (50) for controlling a source line of the cell array (100).

[0027] The word line control circuit (10), bit line control circuit (20), string selection control circuit (30), additional string selection control circuit (40), and source line control circuit (50) can be collectively referred to as a control circuit.

[0028] That is, in this embodiment, the control circuit controls the word line, bit line, string select line, additional string select line, and source line to perform a selective erase operation for one flash memory cell.

[0029] FIG. 2 illustrates four NAND strings (200) connected to two adjacent bit lines and two string select lines in FIG. 1.

[0030] The NAND string (200) is a structure commonly used in NAND flash memory, and the NAND string (200) includes a bitline selection switch (BSW) in which a source and a drain are sequentially connected between a bitline (BL) and a sourceline (SL), a plurality of flash memory cells (FC), and a sourceline selection switch (SSW).

[0031] In this embodiment, the bitline select switch (BSW) and the sourceline select switch (SSW) are NMOS transistors.

[0032] A string select line (DSL) is connected to the gate of the bit line select switch (BSW), the control gate of a plurality of flash memory cells (FC) is connected to a plurality of word lines (WL), and an additional string select line (SSL) is connected to the gate of the source line select switch (SSW). Hereinafter, the string select line (DSL) may be referred to as the drain select line (DSL).

[0033] Since the bitline select switch (BSW) and sourceline select switch (SSW) perform the function of selecting a NAND string, they can be referred to as string select switches.

[0034] Likewise, the string select line (DSL) and additional string select line (SSL) can be referred to as string select lines.

[0035] In this embodiment, the bitline selection switch (BSW) and the sourceline selection switch (SSW) are assumed to be n-MOS transistors in which the region connected to the bitline and the region connected to the sourceline are doped with n-type impurities.

[0036] If the bit line select switch (BSW) and the source line select switch (SSW) are changed to other types of semiconductor switches, such as P-MOS transistors, the voltage applied to the bit line (BL), source line (SL), string select line (DSL), and additional string select line (SSL) during the erase operation may also be changed accordingly. This is a design change that can be easily made by a person skilled in the art from the disclosure of the present invention, so a specific disclosure is omitted.

[0037] Returning to Fig. 1, the cell array (100) consists of a plurality of NAND strings arranged in two dimensions, resulting in a plurality of flash memory cells arranged in three dimensions.

[0038] A single word line is commonly connected to the control gates of multiple flash memory cells located on a plane perpendicular to the z-axis.

[0039] One bit line (BL) is commonly connected to the drain of a bit line selection switch (BSW) of a plurality of NAND strings (200) located on a plane perpendicular to the x-axis.

[0040] One string select line (DSL) is commonly connected to the gates of bit line select switches (BSW) of a plurality of NAND strings (200) located on a plane perpendicular to the y-axis.

[0041] The source line (SL) is commonly connected to the source of the source line selection switch (SSW) of all NAND strings (200).

[0042] The additional string select line (SSL) is commonly connected to the gate of the source line select switch (SSW) of all NAND strings (200).

[0043] The cell array (100) is substantially the same as the conventional configuration.

[0044] The present invention provides a technique for selecting and erasing one flash memory cell without changing the structure of the cell array (100).

[0045] In this embodiment, the wordline control circuit (10) provides different voltage signals to the wordline connected to the selected flash memory cell and to the wordline not connected.

[0046] In this embodiment, the bitline control circuit (20), string selection control circuit (30), additional string selection control circuit (40), and sourceline control circuit (50) set the voltages of the bitline (BL), string selection line (DSL), source line (SL), and additional string selection line (SSL) to a constant condition to cause gate-induced drain leakage (GIDL) in the NAND string (200) where the selected flash memory cell (FC) is located.

[0047] The holes generated by GIDL are supplied to the channel of the NAND string (200) to move electrons stored in the charge storage layer of the flash memory cell (FC) into the channel, or the holes are stored in the charge storage layer to lower the threshold voltage of the flash memory cell (FC) and perform an erase operation.

[0048] FIG. 2 is a circuit diagram illustrating the operation of erasing a single flash memory cell in a flash memory device (1) according to one embodiment of the present invention, and FIG. 4 shows the voltages of the bit line (BL) and string select line (DSL) of FIG. 2 summarized.

[0049] In this embodiment, 6V is applied to the word line connected to the selected flash memory cell (FC), and 0V is applied to the word line not connected to the unselected flash memory cell (FC). Hereinafter, the word line connected to the selected flash memory cell (FC) is referred to as the selected word line.

[0050] In this embodiment, 16V is applied to the bit line connected to the selected flash memory cell (FC), and 12V is applied to the bit line not connected to the selected flash memory cell (FC). Hereinafter, the bit line connected to the selected flash memory cell (FC) is referred to as the selected bit line.

[0051] 10V is applied to the string select line (DSL) of the bit line select switch (BSW) connected to the selected flash memory cell (FC), and 13V is applied to the string select line (DSL) of the bit line select switch (BSW) that is not connected. Hereinafter, the string select line connected to the selected flash memory cell (FC) is referred to as the selected string select line.

[0052] In Figure 2, the erase operation is performed only on one flash memory cell connected to the selected word line, selected bit line, and selected string selection line, and the erase operation is not performed on the remaining cells.

[0053] The voltage obtained by subtracting the string select line voltage (VDSL) from the bit line voltage (VBL) or the voltage obtained by subtracting the additional string select line voltage (VSSL) from the source line voltage (VSL) is the GIDL voltage (V GIDL It can be displayed as ).

[0054] GIDL voltage (V GIDL ) shows four combinations as shown in Fig. 3 depending on whether the bitline and string selection line are selected.

[0055] In this embodiment, the GIDL voltage between the selected bit line and the selected string select line satisfies the erasure condition by GIDL, and if not, the erasure operation by GIDL is suppressed.

[0056] In this embodiment, when the GIDL voltage is 6V or higher, the erasure condition by GIDL is satisfied, but when it is lower, the erasure operation is suppressed.

[0057] In this embodiment, 0V is applied to the word line connected to the selected flash memory cell (FC), and 6V is applied to the word line not connected to the unselected flash memory cell (FC), so that holes move to the charge storage layer of the selected flash memory cell (FC) (or electrons move from the charge storage layer to the channel), and the threshold voltage of the selected flash memory cell is lowered.

[0058] If a lower voltage (e.g., a negative voltage) is provided to the selected word line, holes can move to the charge storage layer in a shorter time.

[0059] In this embodiment, 12V is applied to the source line (SL) and 10V is applied to the additional string select line (SSL), so the GIDL voltage on the source line side becomes 2V.

[0060] Accordingly, in this embodiment, GIDL does not occur in the source line (SL) direction, but only in the bit line (BL) direction.

[0061] Power consumption can be reduced by reducing the current flowing between the bit line (BL) and the source line (SL) in an operation that erases only the selected flash memory cells.

[0062] When the voltage of the additional string select line (SSL) is applied at 10V, the source line select switch (SSW) is turned off and the current is cut off.

[0063] When erasing a single selected flash memory cell as in this embodiment, blocking the generation of GIDL in the source line direction may be advantageous for reducing power consumption.

[0064] Even when performing an erase operation on a single selected flash memory cell, a block-unit erase operation may be required.

[0065] To perform block-unit erase operations, the voltage of the source line (SL) can be raised to 16V and the voltage of all word lines can be set to 0V.

[0066] Since all source lines (SL) are commonly connected to the NAND strings (200), block-unit erasure operations can be performed more simply than adjusting the voltage of all bit lines and the voltage of all string select lines.

[0067] The bitline voltage (VBL) or sourceline voltage (VSL) may be referred to as the erase voltage (Verase) or erase bias.

[0068] The erase voltage (Verase) is the GIDL voltage (V GIDL It affects the erase operation along with ). For example, GIDL voltage (V GIDL If ) is the same, the erasure performance can be improved as the erasure voltage (Verase) increases.

[0069] FIG. 3 is a circuit diagram showing the erasure operation of a selected flash memory cell of a flash memory device (1).

[0070] In the embodiment of FIG. 3, the memory cell array (100) further includes a plurality of switches (300), and the plurality of switches (300) connect a plurality of word lines and control gates of a plurality of flash memory cells.

[0071] The wordline control circuit (10) can additionally control a plurality of switches (300) to perform a selective erasure operation.

[0072] The wordline control circuit (10) can control a plurality of switches (300) so that a flash memory cell to be erased is connected to the wordline through a control operation, and a flash memory cell not to be erased is separated from the wordline.

[0073] In this embodiment, a low voltage (0V) is applied to the flash memory cell to which the erase operation is to be performed, as shown in FIG. 2, so that holes flow into the charge storage layer.

[0074] However, the control gate of a flash memory cell for which an erase operation will not be performed becomes a floating state.

[0075] At this time, a positive body voltage is applied to the control gate of the floating flash memory cell through coupling, so that it can have a voltage greater than 0V.

[0076] In one embodiment, a positive voltage may be applied in advance to a word line connected to an unselected flash memory cell before the erase operation begins, and when the erase operation begins, the switch connected to the unselected flash memory cell may be turned off to prevent the erase of the unselected flash memory cell.

[0077] In another embodiment, the wordline voltage (0V) of the selected flash memory cell may be coupled to the control gate of an unselected flash memory cell adjacent to the selected flash memory cell. To prevent this, a positive voltage may be applied to the control gate of the unselected flash memory cell adjacent to the selected flash memory cell as shown in FIG. 2, and the control gate of the remaining unselected flash memory cell may be set to a floating state as shown in FIG. 3.

[0078] At this time, the number of adjacent flash memory cells to which a positive voltage is applied may be modified by a person skilled in the art according to the embodiment.

[0079] Figure 5 is a graph showing a comparison of the erasure operation of the flash memory device (1).

[0080] Figure 5A is a graph showing a conventional block-unit erasure technique.

[0081] Conventionally, during an erase operation, all bit lines (BL) and source lines (SL) included in the block are raised to, for example, 16V.

[0082] At the beginning of the rise in voltage between the bit line and source line, the string select line (DSL) and additional string select line (SSL) are maintained at a low voltage, such as 0V.

[0083] When the voltage of the bit line (BL) and source line (SL) rises above a certain level, the voltage of the string select line (DSL) and additional string select line (SSL) begins to rise.

[0084] While the voltage of the bit line (BL) and source line (SL) is maintained at 16V, the voltage of the string select line (DSL) and additional string select line (SSL) is maintained at, for example, 10V.

[0085] At this time, when a low voltage (e.g., 0V) is applied to the control gate of all flash memory cells (FC) included in the NAND string (200), electron-hole pairs are generated due to GIDL, and thereby an erase operation is performed on all flash memory cells included in the NAND string (200).

[0086] FIG. 5B is a graph illustrating the erase operation for a flash memory cell selected in this embodiment.

[0087] Unlike Fig. 5A, voltage conditions are additionally set for the unselected bit line and the unselected string select line for the erase operation on the selected cell.

[0088] In this embodiment, the voltage of the unselected bit line (BL) rises together with the voltage of the selected bit line, but rises to a lower voltage (e.g., 12V) than the voltage of the selected bit line.

[0089] Also, the voltage of the unselected string select line (DSL) rises along with the voltage of the selected string select line, but rises to a higher voltage (e.g., 13V) than the voltage of the selected string select line.

[0090] Accordingly, the GIDL voltage between the selected bit line and the selected string select line satisfies the conditions for performing an erase operation by GIDL.

[0091] In contrast, the GIDL voltage between an unselected bit line and an arbitrary string select line, or the GIDL voltage between an arbitrary bit line and an unselected string select line, does not satisfy the conditions for an erase operation by GIDL, so the erase operation is suppressed.

[0092] Figure 6 is a graph showing the relationship between the GIDL voltage and the change in threshold voltage.

[0093] In Fig. 6, (A) shows a block-unit erasure operation, and (B) shows an erasure operation for a selected cell.

[0094] The vertical axis represents the change in threshold voltage of the flash memory cell before and after the erase operation; since the threshold voltage decreases during the erase operation, the change in threshold voltage has a positive value.

[0095] The amount of change at which the erasure operation can be determined to be completed may vary depending on the embodiment and can be determined in advance through experimentation.

[0096] In this embodiment, it is assumed that the erase operation is completed when the threshold voltage decreases by 0.4V. Under these conditions, in the conventional case, the erase operation is performed when the GIDL voltage is about 3.2V or higher, whereas in this embodiment, the erase operation is performed when the GIDL voltage is 4V or higher.

[0097] Determining the bitline voltage and the string select line voltage depending on the selection while satisfying the conditions of Fig. 6 can be varied in design by a person skilled in the art.

[0098] Figure 6 assumes that the erase voltage is 13V, but if the erase voltage is increased to 16V, the GIDL voltage required for erasure may change.

[0099] Figure 7 is a graph showing the relationship between the erase voltage and the threshold voltage fluctuation amount of the flash memory cell.

[0100] In FIG. 7, (A) corresponds to a block-unit erasure operation, and (B) corresponds to an erasure operation for a selected cell.

[0101] As described, when the GIDL voltage is fixed, the range of variation of the threshold voltage increases as the erasure voltage increases.

[0102] Accordingly, if the erase voltage in Fig. 6 is increased to 16V, the GIDL voltage may change.

[0103] Figure 8 shows the relationship between the bitline voltage in an unselected NAND string and the change in threshold voltage of a flash memory cell.

[0104] In Fig. 8, the selected bitline voltage is 16V, the GIDL voltage of the selected NAND string is 6V, and the GIDL voltage of the unselected NAND string is 0V.

[0105] In Figure 8, if the voltage of the unselected bit line is set to 9V or less, the voltage difference between the selected bit line and the unselected bit line increases, causing a breakdown phenomenon.

[0106] Accordingly, the voltage of the unselected bit line must be set to a value of 9V or higher.

[0107] The graph in Fig. 8 illustrates cases where the voltage of the unselected bit line is 10V, 11V, 12V, and 13V.

[0108] In Fig. 8, the flash memory cell corresponding to the black square corresponds to the selected flash memory cell, and the cell corresponding to the remaining shape corresponds to the unselected flash memory cell.

[0109] Even if the voltage of the unselected bitline increases, the change in the threshold voltage of the unselected flash memory cell is negligible.

[0110] However, the amount of change in the threshold voltage of the selected flash memory cell gradually increases as the voltage of the unselected bit line increases.

[0111] For example, if the voltage of an unselected bit line is 12V, the threshold voltage change of the selected flash memory cell increases to 0.4V or more.

[0112] If a higher voltage is applied to an unselected bit line, the threshold voltage change of the selected cell may increase, but the threshold voltage of the unselected flash memory cell may change significantly as the GIDL voltage between the unselected bit line and any string select line becomes sufficiently large.

[0113] Although a low voltage can be applied to unselected bit lines to prevent GIDL from occurring, breakdown may occur as described above. To prevent this, the spacing between bit lines can be widened, but this is not desirable as it affects the integration density of the cell.

[0114] Figure 9 is a graph showing the relationship between the location of a selected flash memory cell and the amount of change in threshold voltage.

[0115] In FIG. 9, (A) corresponds to the case where the selected flash memory cell is in the middle of the NAND string, (B) corresponds to the case where the selected flash memory cell is located at the very bottom of the NAND string, (C) corresponds to the case where the selected flash memory cell is located at the very top of the NAND string, and (D) corresponds to the unselected flash memory cell.

[0116] As described, the change in threshold voltage of unselected flash memory cells is negligible regardless of the number of erase operations.

[0117] However, it can be seen that the change in threshold voltage of the selected flash memory cell is of a similar magnitude regardless of the position of the selected flash memory cell, and increases to a similar magnitude as the number of erase operations increases.

[0118] Through this, it can be seen that the threshold voltage of a specific flash memory cell can be adjusted to a desired size by repeating the erase operation on a single selected flash memory cell.

[0119] FIGS. 10 and 11 are flowcharts illustrating the operation of a flash memory according to an embodiment of the present invention. The operation of FIGS. 10 and 11 can be performed by a control circuit.

[0120] The operation of FIG. 10 illustrates an embodiment in which a write operation or an erase operation is performed on a selected flash memory cell such that the threshold voltage of the selected flash memory cell is located within a constant range between a lower limit (VL) and an upper limit (VM).

[0121] In this case, the upper limit (VM) and lower limit (VL) can be determined differently depending on the cell data.

[0122] First, the threshold voltage of the selected flash memory cell is read (S110).

[0123] It is determined whether the threshold voltage is lower than or equal to the lower limit (VL) (S120), and if the threshold voltage is lower than or equal to the lower limit (VL), a write operation is performed (S130).

[0124] If the threshold voltage exceeds the lower limit (VL), it is determined whether the threshold voltage is less than the upper limit (VM) (S140).

[0125] If the threshold voltage is greater than or equal to the upper limit (VM), an erasure operation is performed on the selected cell (S150). Afterwards, the process moves to step (S110), and if the threshold voltage is less than the upper limit (VM), the operation is terminated.

[0126] The operation of Fig. 10 indicates that when the threshold voltage of a specific flash memory cell deviates from a normal distribution and causes an error, instead of using an ECC circuit, an erase operation is performed on the corresponding flash memory cell to maintain the threshold voltage within a normal distribution.

[0127] Accordingly, error occurrences can be reduced even without using complex circuits such as ECC circuits.

[0128] In addition, even if the ECC circuit is maintained, the complexity of the circuit can be reduced by keeping the error correction capability of the ECC circuit to a minimum.

[0129] In another embodiment, a rewrite operation can be performed to improve the data retention characteristics of the flash memory cell.

[0130] In this case, the threshold voltage of the flash memory cell may increase, which could be problematic, but by performing an erase operation as needed as shown in Fig. 9, the threshold voltage of the flash memory cell can be increased while improving the retention characteristics of the flash memory cell.

[0131] By using the technology of Fig. 10, in an embodiment where NAND flash memory cell devices are used as synapses in a memory-based neural network, the weight dispersion of synapses in the synapse array can be significantly reduced, and thereby the accuracy of the neural network can be significantly improved.

[0132] The operation of Fig. 10 can be advantageously applied in situations where cell data corresponding to a specific bit among multi-bit data is modified. This operation can be performed frequently, for example, when changing the weights of a neural network.

[0133] The flowchart of FIG. 11 is based on the premise that the threshold voltage is low when the data of the flash memory cell is 1, and the threshold voltage is high when the data of the flash memory cell is 0.

[0134] Accordingly, to make the data 0, a write operation must be performed, and to make the cell data 1, an erase operation must be performed.

[0135] First, determine whether the cell data is modified from 1 to 0 (S210).

[0136] When data is modified from 0 to 1, an erase operation is performed to decrease the threshold voltage (S220), and when data is modified from 1 to 0, a write operation is performed to increase the threshold voltage (S230).

[0137] The present invention can be applied in various embodiments as follows.

[0138] When performing write operations in NAND flash memory by performing block erase operations and ISPP (Incremental Step Pulse Program) operations, if a flash memory cell with a large variation in threshold voltage is found, selective erase operations can be performed to reduce the variation in threshold voltage.

[0139] By performing block-unit write operations on NAND flash memory cells to raise the threshold voltage of all flash memory cells and lowering the threshold voltage of selected flash memory cells through ISPE (Incremental Step Pulse Erase) operations, the dispersion of the overall threshold voltage can be balanced.

[0140] By performing a write operation on a wordline basis in a NAND flash memory cell, the threshold voltage of all flash memory cells connected to the corresponding wordline is raised, and the threshold voltage of the selected flash memory cell is lowered through an Incremental Step Pulse Erase (ISPE) operation, thereby matching the dispersion of the overall threshold voltage.

[0141] At this time, both coarse tuning (large adjustment of the threshold voltage fluctuation range) and fine tuning (fine tuning) can be performed simultaneously.

[0142] When flash memory cells store multi-level data, the dispersion of the threshold voltage can have a more sensitive impact on data accuracy, and in this case, a selective erase operation can be performed on a single cell to reduce the dispersion of the threshold voltage.

[0143] As described above, when an error occurs in a specific flash memory cell, instead of correcting the error using error correction code technology, the threshold voltage of the flash memory cell can be adjusted to a desired range by performing selective erase and write operations on the flash memory cell where the error occurred.

[0144] In the event that an error occurs in flash memory due to a threshold voltage change caused by a read operation (Read Disturbance), the fail bit can be handled using selective erase and write operations.

[0145] In the event that a fail bit occurs during a rewrite operation in flash memory, the fail bit can be handled using an optional erase and write operation.

[0146] When storing synapse weights of a neural network in flash memory, the threshold voltage can be accurately controlled by performing write and erase operations on the flash memory cells.

[0147] If synapse weight data stored in a flash memory cell changes, the synapse weight value can be modified through selective erase and write operations on the flash memory cell.

[0148] In order to increase inference accuracy in memory-based artificial intelligence technology, it is important to accurately match the turn-on current value flowing through the NAND string. As mentioned above, the turn-on current value can be accurately matched by performing a selective erase operation for each flash memory cell.

[0149] For example, if the threshold voltage of a flash memory cell increases, the turn-on current decreases, and if the threshold voltage of a flash memory cell decreases, the turn-on current increases.

[0150] Accordingly, when the turn-on current is smaller than the target value, the turn-on current can be increased by lowering the threshold voltage through a selective erase operation, and when the turn-on current is larger than the target value, the turn-on current can be decreased by raising the threshold voltage through a write operation.

[0151] The scope of the present invention is not limited to the disclosure above. The scope of the present invention should be interpreted based on the scope literally described in the claims and their equivalents. Explanation of the symbols

[0152] 1: Flash memory device 100: Cell array 200: NAND string 10: Wordline control circuit 20: Bitline control circuit 30: String selection control circuit 40: Additional string selection control circuit 50: Source line control circuit

Claims

Claim 1 A cell array comprising a plurality of flash memory cells having control gates connected to a plurality of word lines, and a first NAND string including a string selection switch that connects a plurality of flash memory cells to a first bit line according to the control of a first string selection line; and includes a control circuit for controlling a first erase operation for erasing one selected flash memory cell among a plurality of flash memory cells of the first NAND string, wherein the control circuit sets the voltage between the first bit line and the first string select line to a first voltage that generates GIDL at the string select switch, and sets the control gate voltage of the flash memory cell to be erased and the control gate voltage of the flash memory cells excluding the flash memory cell to be erased among the plurality of flash memory cells differently, and the cell array further includes a second NAND string comprising a plurality of flash memory cells having control gates connected to a plurality of word lines and a string select switch that connects a plurality of flash memory cells to the first bit line according to the control of the second string select line, and the control circuit controls the voltage between the second string select line and the first bit line to be a second voltage smaller than the first voltage during the first erase operation, and the control circuit during the first erase operation the second string A flash memory device that controls the voltage of a select line to have a value smaller than the voltage of the first bit line and larger than the voltage of the first string select line. Claim 2 delete Claim 3 A flash memory device according to claim 1, wherein the cell array further comprises a third NAND string including a plurality of flash memory cells having control gates connected to a plurality of word lines and a string selection switch connecting a plurality of flash memory cells to a second bit line according to the control of the first string selection line, and the control circuit controls the voltage between the second bit line and the first string selection line to become a third voltage smaller than the first voltage during the first erase operation. Claim 4 A flash memory device according to claim 3, wherein the cell array further comprises a fourth NAND string including a plurality of flash memory cells having control gates connected to a plurality of word lines and a string selection switch connecting a plurality of flash memory cells to a second bit line according to the control of the second string selection line, and the control circuit controls the voltage between the second bit line and the second string selection line to become a fourth voltage smaller than the first voltage during the first erase operation. Claim 5 A flash memory device according to claim 3, wherein the control circuit controls the voltage of the second bit line to be smaller than the voltage of the first bit line during the first erasure operation. Claim 6 A flash memory device according to claim 3, wherein the control circuit controls the voltage of the second bit line to have a value smaller than the voltage of the first bit line and larger than the voltage of the first string select line during the first erasure operation. Claim 7 delete Claim 8 A flash memory device according to claim 1, wherein the first NAND string further includes an additional string selection switch that connects a plurality of flash memory cells to a source line according to the control of an additional string selection line, and the control circuit controls the voltage between the additional string selection line and the source line to become a fifth voltage that is smaller than the first voltage during the first erasure operation. Claim 9 A flash memory device according to claim 8, wherein the control circuit further performs a second erasure operation to erase all of the plurality of flash memory cells included in the first NAND string, and during the second erasure operation, controls the voltage between the additional string selection line and the source line to the first voltage or a voltage that causes GIDL to occur at the additional string selection switch, and sets a voltage that enables erasure at the control gate of the plurality of flash memory cells included in the first NAND string. Claim 10 A flash memory device according to claim 1, wherein the first NAND string and the second NAND string each further include an additional string selection switch that connects a plurality of flash memory cells to a source line according to the control of an additional string selection line, and the control circuit controls the voltage between the additional string selection line and the source line to be a sixth voltage that is smaller than the first voltage during the first erasure operation. Claim 11 A flash memory device according to claim 10, wherein the control circuit further performs a second erase operation to erase all of the plurality of flash memory cells included in the first NAND string and the second NAND string, and during the second erase operation, controls the voltage between the additional string select line and the source line to the first voltage or a voltage that causes GIDL to occur at the additional string select switch, and sets a voltage that enables erasure at the control gate of the plurality of flash memory cells included in the first NAND string and the second NAND string. Claim 12 A flash memory device according to claim 3, wherein the first NAND string, the second NAND string, and the third NAND string each further include an additional string selection switch that connects a plurality of flash memory cells to a source line according to the control of an additional string selection line, and the control circuit controls the voltage between the additional string selection line and the source line to be a seventh voltage that is smaller than the first voltage during the first erasure operation. Claim 13 A flash memory device according to claim 12, wherein the control circuit further performs a second erase operation to erase all of the plurality of flash memory cells included in the first NAND string, the second NAND string, and the third NAND string, and during the second erase operation, controls the voltage between the additional string select line and the source line to the first voltage or a voltage that causes GIDL to occur at the additional string select switch, and sets a voltage that enables erasure at the control gates of the plurality of flash memory cells included in the first NAND string, the second NAND string, and the third NAND string. Claim 14 A flash memory device according to claim 4, wherein the first NAND string, the second NAND string, the third NAND string, and the fourth NAND string each further include an additional string selection switch that connects a plurality of flash memory cells to a source line according to the control of an additional string selection line, and the control circuit controls the voltage between the additional string selection line and the source line to become an eighth voltage that is smaller than the first voltage during the first erasure operation. Claim 15 A flash memory device according to claim 14, wherein the control circuit further performs a second erase operation to erase all of the plurality of flash memory cells included in the first NAND string, the second NAND string, the third NAND string, and the fourth NAND string, and during the second erase operation, controls the voltage between the additional string selection line and the source line to the first voltage or a voltage that causes GIDL to occur at the additional string selection switch, and sets a voltage that enables erasure at the control gates of the plurality of flash memory cells included in the first NAND string, the second NAND string, the third NAND string, and the fourth NAND string. Claim 16 A flash memory device according to claim 1, wherein the control circuit performs the first erase operation on the selected cell when the threshold voltage of the selected cell exceeds an upper limit, and performs the write operation on the selected cell when the threshold voltage of the selected cell is less than a lower limit. Claim 17 A flash memory device according to claim 1, wherein the control circuit sets the control gate voltage of the flash memory cell to be erased lower than the control gate voltage of the flash memory cell excluding the flash memory cell to be erased among the plurality of flash memory cells. Claim 18 A flash memory device according to claim 1, wherein the cell array further comprises a plurality of switches connecting the plurality of word lines to the control gates of the plurality of flash memory cells, and the control circuit controls the plurality of switches such that the control gate of the flash memory cell to be erased is connected to the word line, and the control gate of the flash memory cell excluding the flash memory cell to be erased among the plurality of flash memory cells is disconnected from the word line. Claim 19 A flash memory device according to claim 1, wherein the cell array further comprises a plurality of switches connecting the plurality of word lines to the control gates of the plurality of flash memory cells, and the control circuit controls the plurality of switches such that the control gate of the flash memory cell to be erased and the control gate of one or more flash memory cells adjacent to the flash memory cell to be erased are connected to the word line, and the control gate of a flash memory cell among the plurality of flash memory cells, excluding the flash memory cell to be erased and the one or more adjacent flash memory cells, is disconnected from the word line, and the control circuit sets the control gate voltage of the flash memory cell to be erased and the control gate voltage of the one or more adjacent flash memory cells differently. Claim 20 A method of operating a flash memory device according to claim 1, comprising: reading a threshold voltage of any one selected flash memory cell included in a NAND string; performing an erase operation on the selected flash memory cell when the read threshold voltage is greater than an upper limit; and performing a write operation on the selected flash memory cell when the read threshold voltage is less than a lower limit. Claim 21 A method of operation of a flash memory device according to claim 20, wherein the upper limit and lower limit correspond to the upper limit and lower limit in a distribution of threshold voltages corresponding to the data level of the selected flash memory cell. Claim 22 A method of operating a flash memory device according to claim 1, comprising: a step of performing a write operation on a selected flash memory cell when data stored in any one selected flash memory cell included in a NAND string is changed to first data; and a step of performing an erase operation on a selected flash memory cell when data stored in the selected flash memory cell is changed to second data. Claim 23 A method of operating a flash memory device according to claim 22, further comprising: a step of finding a flash memory cell in which an error has occurred in data read from the flash memory device; and a step of designating the cell in which the error has occurred as the selected flash memory cell. Claim 24 A method of operating a flash memory device according to claim 22, further comprising: a step of finding a flash memory cell corresponding to weight data to be changed among the synapse weight data of a neural network stored in the flash memory device; and a step of designating the cell corresponding to the weight data to be changed as the selected flash memory cell. Claim 25 A method of operation of a flash memory device according to claim 1, comprising: a step of performing a write operation on a predetermined number of flash memory cells included in a block comprising a plurality of NAND strings, each including a plurality of flash memory cells having control gates connected to a plurality of word lines; a step of reading a threshold voltage of a selected flash memory cell among the predetermined number of flash memory cells; and a step of comparing the read threshold voltage with a target value to perform an erase operation or a write operation on the selected flash memory cell. Claim 26 A method of operation of a flash memory device according to claim 25, wherein the predetermined number of flash memory cells is the total number of flash memory cells included in the block. Claim 27 A method of operation of a flash memory device according to claim 25, wherein the predetermined number of flash memory cells is a plurality of flash memory cells connected to a selected word line among the plurality of word lines. Claim 28 A method of operating a flash memory device according to claim 25, wherein the step of performing the write operation comprises providing a voltage for a write operation to a word line connected to a predetermined number of flash memory cells and connecting at least one of a bit line or a source line to supply a carrier for a write operation to a channel of the predetermined number of flash memory cells. Claim 29 A method of operating a flash memory device according to claim 1, comprising: a step of reading a turn-on current flowing through any one selected flash memory cell included in a NAND string; and a step of comparing the read turn-on current with a target value and performing an erase operation or a write operation on the selected flash memory cell. Claim 30 A method of operating a flash memory device according to claim 29, further comprising the step of performing a write operation on all memory cells included in the NAND string.

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