Stacked memory devices and methods

Abstract

The invention relates to a stacked memory device and a method. Systems, methods, and devices are provided for stacked memory based on folded bit lines and interleaved semiconductor channels. The system, apparatus, and method include offsetting a position of a first set of isolation trenches relative to a position of a second set of isolation trenches; forming a first local bit line at a first angle relative to the orientation of the first and second sets of isolation trenches; offsetting the position of the third group of isolation trenches relative to the position of the fourth group of isolation trenches; and forming a second local bit line at a second angle relative to the orientation of the third and fourth sets of isolation trenches, the second angle being different from the first angle.

Description

Technical Field

[0001] This disclosure generally relates to memory systems. In particular, the subject matter relates to stacked memories based on folded bit lines and interleaved semiconductor channels. Background Technology

[0002] This background section is intended to provide background information only, and the disclosure of any concepts in this section does not constitute an admission that the concepts are prior art.

[0003] Memory chips can include integrated circuits that store and retrieve data in digital devices such as computers and mobile devices. Memory chips can store data temporarily or permanently. Memory chips can include random access memory (RAM), dynamic random access memory (DRAM), read-only memory (ROM), flash memory, etc. Memory chips can include output lines connected to the system data bus. Some memory chips can be cut from a wafer and placed in a separate housing. Memory chips can be mounted on a printed circuit board (PCB), integrated onto a system-on-a-chip (SoC), stacked vertically, etc. Summary of the Invention

[0004] In various embodiments, the systems and methods described herein include systems, methods, and apparatus for stacked memories based on folded bit lines and interleaved semiconductor channels. In some aspects, the technology described herein relates to a stacked memory device comprising: a first set of isolation trenches and a second set of isolation trenches, the first set of isolation trenches being positioned relative to the second set of isolation trenches; a first local bit line formed at a first angle relative to the orientations of the first and second sets of isolation trenches; a third set of isolation trenches and a fourth set of isolation trenches, the third set of isolation trenches being positioned relative to the fourth set of isolation trenches; and a second local bit line formed at a second angle relative to the orientations of the third and fourth sets of isolation trenches, the second angle being different from the first angle.

[0005] In some respects, the techniques described herein relate to stacked memory devices, wherein a first angle of a first local bit line is in the range of 10 to 80 degrees relative to the orientation of a first set of isolation trenches and a second set of isolation trenches oriented at zero angles.

[0006] In some respects, the technology described herein relates to a stacked memory device, wherein: a first connector connects a first local bit line to a first global bit line, the first global bit line connects the first local bit line to a first sense amplifier, and the first global bit line is positioned at a zero angle.

[0007] In some respects, the techniques described herein relate to stacked memory devices, wherein: the second angle of the second local bit line is in the range of 100 to 170 degrees relative to the orientation of the third and fourth sets of isolation trenches oriented at zero angles.

[0008] In some respects, the technology described herein relates to a stacked memory device, wherein: a second connector connects a second local bit line to a second global bit line, the second global bit line connects the second local bit line to a second sense amplifier, and the second global bit line is positioned at a zero angle.

[0009] In some respects, the techniques described herein relate to stacked memory devices, wherein a first portion of a first local bit line is formed between a first isolation trench and a second isolation trench of a first set of isolation trenches.

[0010] In some respects, the techniques described herein relate to stacked memory devices, wherein a second portion of a first local bit line is formed between a third and a fourth isolation trench of a second set of isolation trenches.

[0011] In some respects, the techniques described herein relate to stacked memory devices, wherein a first local bit line is connected to a first column memory cell and a second column memory cell.

[0012] In some aspects, the technology described herein relates to a stacked memory device comprising: a first set of isolation trenches and a second set of isolation trenches, the location of the first set of isolation trenches being offset relative to the location of the second set of isolation trenches; a first local bit line formed between the first and second isolation trenches of the first set of isolation trenches; and a second local bit line formed between a third and a fourth isolation trench of the second set of isolation trenches.

[0013] In some respects, the techniques described herein relate to stacked memory devices in which the position of a first local bit line is offset relative to the position of a second local bit line.

[0014] In some respects, the techniques described herein relate to stacked memory devices, wherein the angle of the connecting line connecting the center of a first local bit line and the center of a second local bit line is in the range of 10 to 80 degrees relative to the orientation of a first set of isolation trenches and a second set of isolation trenches oriented at zero angle.

[0015] In some respects, the techniques described herein relate to stacked memory devices, wherein: a first connector connects a first local bit line to a first global bit line, and the first global bit line connects the first local bit line to a first sense amplifier.

[0016] In some respects, the techniques described herein relate to stacked memory devices, wherein: a first global bit line is at least partially located between a first isolation trench and a second isolation trench, and the first global bit line is located at a zero angle.

[0017] In some respects, the techniques described herein relate to stacked memory devices, wherein: a second connector connects a second local bit line to a second global bit line, and the second global bit line connects the second local bit line to a second sense amplifier.

[0018] In some respects, the techniques described herein relate to a stacked memory device in which: a second global bit line is at least partially located between a third isolation trench and a fourth isolation trench, and the second global bit line is located at a zero angle.

[0019] In some respects, the techniques described herein relate to stacked memory devices, wherein: a first local bit line is connected to a first column of memory cells, and a second local bit line is connected to a second column of memory cells.

[0020] In some aspects, the technology described herein relates to a method comprising: offsetting the position of a first set of isolation trenches relative to the position of a second set of isolation trenches; forming a first local bit line at a first angle relative to the orientation of the first and second sets of isolation trenches; offsetting the position of a third set of isolation trenches relative to the position of a fourth set of isolation trenches; and forming a second local bit line at a second angle relative to the orientation of the third and fourth sets of isolation trenches, the second angle being different from the first angle.

[0021] In some respects, the technique described herein relates to a method in which a first angle of a first local bit line is in the range of 10 to 80 degrees relative to the orientation of a first set of isolation trenches and a second set of isolation trenches oriented at zero angles.

[0022] In some respects, the technology described herein relates to a method in which: a first connector connects a first local bit line to a first global bit line, the first global bit line connects the first local bit line to a first sensing amplifier, and the first global bit line is positioned at zero angle.

[0023] In some respects, the technique described herein relates to a method in which: the second angle of the second local bit line is in the range of 100 to 170 degrees relative to the orientation of the third and fourth sets of isolation trenches oriented at zero angles.

[0024] A computer-readable medium is disclosed. The computer-readable medium can store instructions that, when executed by a computer, cause the computer to perform substantially the same or similar operations as further disclosed herein. Similarly, non-transitory computer-readable media, apparatuses, and systems for performing substantially the same or similar operations as described herein are further disclosed.

[0025] The systems and methods described herein include several advantages and benefits. For example, memory devices based on the systems and methods described herein can include sense amplifiers (SAs) with increased pitch margins, which are achieved based on a folded bitline architecture. For example, the systems and methods described herein can provide increased leeway in the physical layout of the sense amplifier within the constraints of a memory cell array based on the bitline pitch or spacing, where the bitline pitch is attributed to the folded bitline architecture. Furthermore, memory devices can be configured for integration with core and peripheral transistors based on the folded bitline systems and methods described herein. Attached Figure Description

[0026] The foregoing and other aspects of this system and method will be better understood when this application is read in conjunction with the following drawings (in which the same reference numerals indicate similar or identical elements). Furthermore, the drawings provided herein are for illustrative purposes only; other embodiments, which may not be explicitly shown, are not excluded from the scope of this disclosure.

[0027] These and other features and advantages of this disclosure will be understood and appreciated by referring to the specification, claims, and drawings, in which:

[0028] Figure 1 Example architectures based on one or more implementations as described herein are shown.

[0029] Figure 2 Example architectures based on one or more implementations as described herein are shown.

[0030] Figure 3 Example architectures based on one or more implementations as described herein are shown.

[0031] Figure 4 Example architectures based on one or more implementations as described herein are shown.

[0032] Figure 5 A flowchart illustrating an example method associated with the disclosed system, demonstrating an example implementation as described herein.

[0033] Figure 6 A flowchart illustrating an example method associated with the disclosed system, demonstrating an example implementation as described herein.

[0034] While this system and method are susceptible to various modifications and alternatives, specific embodiments thereof are illustrated by way of example in the accompanying drawings and will be described herein. The drawings may not be to scale. However, it should be understood that the drawings and their detailed description are not intended to limit the system and method to the specific forms disclosed, but rather are intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the system and method as defined by the appended claims. Detailed Implementation

[0035] Details of one or more embodiments of the subject matter described herein are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims.

[0036] Various embodiments of this disclosure will now be described more fully below with reference to the accompanying drawings, which illustrate some, but not all, of the embodiments. In fact, this disclosure may be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Unless otherwise stated, the term “or” is used herein in both a substitute and connective sense. The terms “illustrative” and “example” are used as examples and do not indicate a level of quality. The same reference numerals always denote the same elements. Arrows in each figure depict bidirectional data flow and / or bidirectional data flow capabilities. The terms “path,” “path,” and “route” are used interchangeably herein.

[0037] Embodiments of this disclosure can be implemented in various ways, including as a computer program product including an article of manufacture. A computer program product may include a non-transitory computer-readable storage medium storing applications, programs, program components, scripts, source code, program code, object code, bytecode, compiled code, interpreted code, machine code, executable instructions, etc. (also referred to herein as executable instructions, instructions for execution, computer program product, program code, and / or similar terms used interchangeably herein). Such a non-transitory computer-readable storage medium includes all computer-readable media (including volatile and non-volatile media).

[0038] In one embodiment, non-volatile computer-readable storage media may include floppy disks, flexible disks, hard disks, solid-state storage (SSS) (e.g., solid-state drives (SSDs)), solid-state cards (SSCs), solid-state modules (SSMs), enterprise flash drives, magnetic tape, or any other non-transitory magnetic media. Non-volatile computer-readable storage media may include punched cards, paper tape, optical marking sheets (or any other physical medium having a pattern of holes or other optically identifiable markings), compact disc read-only memory (CD-ROM), rewritable compact disc (CD-RW), digital multi-purpose optical disc (DVD), Blu-ray disc (BD), or any other non-transitory optical media. Such non-volatile computer-readable storage media may include read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory (e.g., serial, NAND, NOR, etc.), multimedia memory cards (MMC), secure digital storage (SD) cards, smart media cards, compressed flash memory (CF) cards, memory sticks, etc. In addition, non-volatile computer-readable storage media may include conductive bridged random access memory (CBRAM), phase change random access memory (PRAM), ferroelectric random access memory (FeRAM), non-volatile random access memory (NVRAM), magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), silicon-oxide-nitride-oxide-silicon memory (SONOS), floating junction gate random access memory (FJGRAM), millipede memory, racetrack memory, etc.

[0039] In one embodiment, volatile computer-readable storage media may include random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), fast page mode dynamic random access memory (FPM DRAM), extended data output dynamic random access memory (EDO DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), second generation double data rate synchronous dynamic random access memory (DDR2 SDRAM), third generation double data rate synchronous dynamic random access memory (DDR3 SDRAM), Rambus dynamic random access memory (RDRAM), dual transistor RAM (TTRAM), thyristor RAM (T-RAM), zero capacitor (Z-RAM), Rambus inline memory module (RIMM), dual inline memory module (DIMM), single inline memory module (SIMM), video random access memory (VRAM), cache memory (including various levels), flash memory, register memory, etc. It will be understood that, in the case where the implementation is described as using a computer-readable storage medium, other types of computer-readable storage media may be used instead of the aforementioned computer-readable storage media, or other types of computer-readable storage media may be used in addition to the aforementioned computer-readable storage media.

[0040] As should be understood, various embodiments of this disclosure can be implemented as methods, apparatuses, systems, computing devices, computing entities, etc. Thus, embodiments of this disclosure can take the form of apparatuses, systems, computing devices, computing entities, etc., that execute instructions stored on a computer-readable storage medium to perform certain steps or operations. Therefore, embodiments of this disclosure can take the form of hardware embodiments, computer program product embodiments, and / or embodiments including combinations of computer program products and hardware that perform certain steps or operations.

[0041] Embodiments of this disclosure are described below with reference to block diagrams and flowcharts. Therefore, it should be understood that each block in the block diagrams and flowcharts can be implemented as a computer program product, a hardware implementation, a combination of hardware and computer program products, and / or an apparatus, system, computing device, computing entity, etc., that executes instructions, operations, steps, and interchangeable terms (e.g., executable instructions, instructions for execution, program code, etc.) on a computer-readable storage medium for execution. For example, code retrieval, loading, and execution can be performed sequentially, such that one instruction is retrieved, loaded, and executed at a time. In some examples, retrieval, loading, and / or execution can be performed in parallel, such that multiple instructions are retrieved, loaded, and / or executed together. Thus, such embodiments can produce machines specifically configured to perform the steps or operations specified in the block diagrams and flowcharts. Therefore, the block diagrams and flowcharts support various combinations of embodiments for performing specified instructions, operations, or steps.

[0042] Throughout this specification, references to “one embodiment” or “implementation” mean that a particular feature, structure, or characteristic described in connection with that embodiment may be included in at least one embodiment disclosed herein. Therefore, the phrases “in one embodiment,” “in an embodiment,” or “according to one embodiment” (or other phrases with similar meanings) appearing in various places throughout this specification do not necessarily all refer to the same embodiment. Furthermore, a particular feature, structure, or characteristic may be combined in any suitable manner in one or more embodiments. In this regard, as used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” should not be construed as necessarily preferred or advantageous over other embodiments. Additionally, a particular feature, structure, or characteristic may be combined in any suitable manner in one or more embodiments. Moreover, depending on the context of the discussion herein, singular terms may include corresponding plural forms, and plural terms may include corresponding singular forms. Similarly, hyphenated terms (e.g., "two-dimensional", "pre-defined", "pixel-specific", etc.) may occasionally be used interchangeably with their corresponding non-hyphenated versions (e.g., "two-dimensional", "pre-defined", "pixel-specific", etc.), and uppercase entries (e.g., "counter clock", "row select", "pixout", etc.) may be used interchangeably with their corresponding non-uppercase versions (e.g., "counter clock", "row select", "pixout", etc.). This occasional interchangeability should not be considered inconsistent with each other.

[0043] Furthermore, depending on the context of the discussion herein, singular terms may include corresponding plural forms, and plural terms may include corresponding singular forms. It should also be noted that the various figures shown and discussed herein (including component diagrams) are for illustrative purposes only and are not drawn to scale. Similarly, various waveforms and timing diagrams are shown for illustrative purposes only. For example, the dimensions of some components may be exaggerated relative to others for clarity. Additionally, reference numerals are repeated in the figures where deemed appropriate to indicate corresponding and / or similar components.

[0044] The terminology used herein is for the purpose of describing some embodiments and is not intended to limit the claimed subject matter. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising” and / or “comprising…” indicate the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0045] It will be understood that when an element or layer is referred to as being on, "connected to," or "attached to" another element or layer, it can be directly on, connected to, or attached to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being "directly on," "directly connected to," or "directly attached to" another element or layer, there are no intermediate elements or layers. The same reference numerals always denote the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0046] As used herein, the terms “first,” “second,” etc., serve as labels for nouns that follow them and do not imply any kind of ordering (e.g., spatial, temporal, logical, etc.) unless explicitly defined as such. Furthermore, the same reference numerals may be used across two or more figures to refer to parts, components, blocks, circuits, units, or modules having the same or similar functions. However, such usage is merely for the sake of simplicity and ease of discussion; it does not imply that the construction or architectural details of such components or units are identical in all embodiments, or that such commonly referenced parts / modules are the only way to implement some of the embodiments disclosed herein.

[0047] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this subject pertains. It will be further understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0048] As used herein, the term "module" means any combination of software, firmware, and / or hardware configured to provide the functionality described herein in conjunction with modules. For example, software may be implemented as a software package, code, and / or instruction set or instructions, and the term "hardware" as used in any implementation described herein may individually or in any combination include, for example, components, hardwired circuitry, programmable circuitry, state machine circuitry, and / or firmware storing instructions executed by programmable circuitry. Modules may be implemented collectively or individually as circuitry forming part of a larger system, such as, but not limited to, integrated circuits (ICs), system-on-a-chip (SoCs), components, etc.

[0049] The descriptions provided are intended to enable those skilled in the art to make and use the subjects disclosed herein and to incorporate them into the context of a particular application. While specific examples are given below, other and further examples may be devised without departing from their basic scope.

[0050] Various modifications and uses in different applications will be apparent to those skilled in the art, and the general principles defined herein can be applied to a wide range of implementations. Therefore, the subject matter disclosed herein is not intended to be limited to the presented implementations, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0051] The provided description sets forth numerous specific details to provide a more thorough understanding of the subject matter disclosed herein. However, it will be apparent to those skilled in the art that the subject matter disclosed herein can be practiced without being limited to these specific details. In other instances, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the subject matter disclosed herein.

[0052] Unless otherwise expressly stated, all features disclosed in this specification (e.g., any appended claims, abstract, and drawings) may be replaced by alternative features for the same, equivalent, or similar purposes. Therefore, unless otherwise expressly stated, each disclosed feature is merely an example of a general series of equivalent or similar features.

[0053] This document describes various features with reference to the accompanying drawings. It should be noted that the drawings are intended only to facilitate the description of the features. The various features described are not intended as an exhaustive description of the subject matter disclosed herein or as a limitation on the scope of the subject matter disclosed herein. Furthermore, the examples shown do not need to possess all the aspects or advantages shown. Aspects or advantages described in connection with a particular example are not necessarily limited to that example and can be practiced in any other example, even if not so shown or so explicitly described.

[0054] It should be noted that, if used, the labels left, right, front, back, top, bottom, forward, backward, clockwise, and counterclockwise are for convenience only and are not intended to suggest any particular fixed direction. Rather, the labels are used to reflect the relative position and / or orientation between the various parts of an object.

[0055] Data processing may include data buffering, aligning incoming data from multiple communication channels, forward error correction (FEC), etc. For example, data may be received by an analog front-end (AFE), which may prepare the incoming data for digital processing. The digital portion of the transceiver (e.g., a digital signal processor (DSP)) may provide skew management, equalization, reflection cancellation, and / or other functions. It should be understood that the processes described herein can provide numerous benefits, including both power and cost savings.

[0056] Furthermore, the terms "system," "component," "module," "interface," and "model" are generally intended to refer to computer-related entities, referring to hardware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process, processor, object, executable file, execution thread, program, and / or computer running on a processor. For illustration, both an application running on a controller and the controller itself can be components. One or more components may reside within a process and / or execution thread, and components may reside on one computer and / or be distributed across two or more computers.

[0057] Unless otherwise explicitly stated, each value and range may be interpreted as approximate, as the words "approximately" or "about" precede the value or range. Signals and their corresponding nodes or ports may be referred to by the same name and are interchangeable here for the purpose of reference.

[0058] While implementations may have already been described in terms of circuit functionality, the implementations of the subject matter disclosed herein are not limited. Possible implementations can be carried out in a single integrated circuit, a multi-chip module, a single card, a SoC, or a multi-card circuit package. As will be apparent to those skilled in the art, various implementations can also be implemented as part of a larger system. Such implementations can be used in conjunction with, for example, digital signal processors, microcontrollers, field-programmable gate arrays, application-specific integrated circuits, or general-purpose computers.

[0059] As will be apparent to those skilled in the art, the various functions of circuit elements can also be implemented as processing blocks in a software program. Such software can be implemented, for example, in a digital signal processor, microcontroller, or general-purpose computer. Such software can be implemented in the form of program code in a tangible medium (such as a magnetic recording medium, optical recording medium, solid-state memory, floppy disk, CD-ROM, hard disk drive, or any other non-transitory machine-readable storage medium), which, when loaded into and executed by a machine (such as a computer), becomes an apparatus for practicing the subject matter disclosed herein. When implemented on a general-purpose processor, the program code segments are combined with the processor to provide a unique device that operates similarly to a particular logic circuit. The described embodiments can also be embodied in the form of bit streams or sequences of other signal values ​​transmitted electrically or optically through a medium using methods and / or apparatus as described herein, magnetic field variations stored in a magnetic recording medium, etc.

[0060] Stacked memories can include three-dimensional dynamic random access memory (3D-DRAM), vertically stacked DRAM (VS-DRAM), and others. Stacked memories address the growing demand for high-density, high-performance memory in modern computing systems. By vertically stacking memory cells, 3D-DRAM offers the potential for greater storage capacity and improved energy efficiency compared to traditional planar DRAM architectures.

[0061] However, as 3D-DRAM structures become more complex and densely packaged, challenges arise in maintaining signal integrity and reducing noise during read and write operations. The placement and arrangement of bit lines, word lines, and other components can significantly affect the overall performance and reliability of memory devices.

[0062] One focal area in 3D-DRAM design is bit line configuration. Due to the limitations of local bit line placement, open bit line structures have been used in some 3D-DRAM designs. In this arrangement, each bit line typically uses an adjacent die to define a reference signal during device operation. While effective, this approach can introduce challenges related to noise interconnection and sense margin.

[0063] As 3D-DRAM density continues to increase, there remains a sustained interest in exploring alternative bitline architectures that offer advantages in signal quality, noise reduction, and overall device performance. Furthermore, considerations such as process margin and integration with other components, such as core and peripheral transistors, play a role in the development of 3D-DRAM designs.

[0064] Efforts to enhance 3D-DRAM technology typically involve balancing multiple factors, including cell density, power consumption, reliability, and manufacturability. Therefore, innovation in memory cell architecture, interconnect design, and manufacturing technologies continues to be an active area of ​​research and development in the 3D-DRAM field.

[0065] According to aspects of this disclosure, a three-dimensional dynamic random access memory (3D-DRAM) device with folded bit lines is provided, which improves the sensing margin of the associated sense amplifier. For example, the device may include an interleaved channel structure (e.g., an interleaved trench isolation structure, an interleaved semiconductor channel structure, an interleaved silicon (Si) channel structure). In some cases, the device may include a folded bit line (BL) architecture implemented by an interleaved channel structure. The folded bit line architecture can be implemented to improve the sensing margin (e.g., compared to an open bit line structure).

[0066] In some examples, the staggered channel structure can be based on staggered or offset trench isolation structures (e.g., staggered capacitive deep trench isolation (CDTI) structures). Based on the staggered channel structure, the device may include (e.g., with orientation relative to the staggered channel structure) angled or tilted local bit lines (LBLs) to achieve a folded bit line architecture.

[0067] According to aspects of this disclosure, a method for manufacturing a 3D-DRAM device is provided. The method may include forming an interleaved channel structure (e.g., interleaved CDTI, interleaved semiconductor channel structure). The method may include implementing a folded bit line (LBL) architecture implemented by the interleaved channel structure. The folded bit line architecture can improve sensing margin (e.g., compared to an open bit line structure). The method may include tilting the LBL to implement the folded bit line architecture. For example, the method may include forming the LBL at a certain degree relative to the interleaved channel structure and / or relative to the span of a global bit line.

[0068] The foregoing general description of the illustrative embodiments and the following detailed description are merely exemplary aspects of the teachings of this disclosure and are not limiting.

[0069] Figure 1Example architecture 100 is illustrated according to one or more implementations as described herein. Architecture 100 may depict a perspective or viewpoint of a stacked memory module. For example, architecture 100 may depict a top-down view of a stacked memory module. In some configurations, one or more aspects of architecture 100 may be implemented by or in combination with a manufacturing apparatus configured to (e.g., based on removal, etching, forming, deposition, etc.) form features and components of semiconductor fabrication.

[0070] In the illustrated example, architecture 100 may include a substrate 105, multiple trench isolation structures (e.g., isolation trench 120, isolation trench 125, isolation trench 130, isolation trench 135), local bit lines (e.g., local bit lines (LBL) 140, LBL 145), global bit lines (e.g., global bit lines (GBL) 160, GBL 165, GBL 170, GBL 175), sense amplifiers (e.g., sense amplifier 110, sense amplifier 115), one or more first connectors (e.g., connector 150), and one or more second connectors (e.g., connector 155). The global bit line GBL includes cell metals CM1 and CM2. Architecture 100 may also include cell contacts CC0, CC1.

[0071] Substrate 105 can be used as a substrate for the 3D-DRAM structure of architecture 100. In some cases, substrate 105 can be made of one or more semiconductor materials (e.g., silicon). Isolation trenches (e.g., isolation trench 120, isolation trench 125, isolation trench 130, isolation trench 135) can be formed in or on substrate 105 to electrically isolate different components of the memory structure.

[0072] Local bit lines (e.g., LBL 140, LBL 145) can be configured to connect individual memory cells to global bit lines. Global bit lines (e.g., GBL 160, GBL 165, GBL 170, GBL 175) can be used to transmit data signals between memory cells and sense amplifiers in a 3D-DRAM structure.

[0073] Sensing amplifiers (e.g., sensing amplifier 110, sensing amplifier 115) can be used to detect and amplify relatively small voltage differences on the bit lines during readout operations. As shown, the sensing amplifiers can be positioned at the ends of the global bit lines.

[0074] Connectors (e.g., connector 150, connector 155) can be used to establish electrical connections between different layers or components of a 3D-DRAM structure. For example, connectors can connect local bit lines to global bit lines, thereby establishing connections between memory cells connected to local bit lines and sense amplifiers.

[0075] In the example shown, the trench isolation structures (e.g., isolation trench 120, isolation trench 125, isolation trench 130, isolation trench 135) may be staggered. For ease of explanation, Figure 1 A set of vertically drawn isolation trenches can be referred to as a "column" of isolation trenches, because from Figure 1 From a top-down perspective, one isolation trench is formed above another isolation trench. For example, isolation trench 120 can form the top of a first row of isolation trenches, isolation trench 125 can form the top of a second row of isolation trenches, isolation trench 130 can form the top of a third row of isolation trenches, and isolation trench 135 can form the top of a fourth row of isolation trenches. As shown, the first row of isolation trenches can be formed at an offset position relative to the second row of isolation trenches (e.g., isolation trench 120 is formed at an offset position relative to isolation trench 125; isolation trench 125 is shifted upward relative to isolation trench 120). Similarly, the third row of isolation trenches can be formed at an offset position relative to the fourth row of isolation trenches (e.g., isolation trench 130 is formed at an offset position relative to isolation trench 135; isolation trench 135 is shifted upward relative to isolation trench 130). Based on the offset, at least a portion of the isolation trench 120 (e.g., along the width direction) can be aligned with the gap between the isolation trench 125 and the next isolation trench below the isolation trench 125. Similarly, based on the offset, at least a portion of the isolation trench 130 (e.g., along the width direction) can be aligned with the gap between the isolation trench 135 and the next isolation trench below the isolation trench 135.

[0076] As shown in the figure, a given isolation trench can be formed with a width and a length, where the width is less than the length. Similarly, a given local bitline can be formed with a width and a length, where the width is less than the length. Relative to Figure 1 From a top-down perspective, the global bitline extends in the x-direction. Additionally, as depicted, the isolation trench array is formed in the y-direction. Similarly, based on... Figure 1 The local bit lines are depicted in columns in the y direction (e.g., LBL 140 at the top of the bit lines depicted in the first column, LBL 145 at the top of the bit lines depicted in the second column, etc.).

[0077] The methods described herein may include tilting the LBL. For example, the method may include forming the LBL at an angle relative to the staggered channel structure and / or relative to the span of the global bit line.

[0078] In the illustrated example, at least a portion of the left end of LBL 140 may be formed within the gap between isolation trench 120 and the next isolation trench below isolation trench 120. Similarly, at least a portion of the right end of LBL 140 may be formed within the gap between isolation trench 125 and the next isolation trench below isolation trench 125. As shown, the LBLs of the depicted architecture 100 may be tilted during formation. For example, the LBLs of the first column depicted (e.g., LBL 140) may be formed at an angle relative to a given GBL or isolation trench (e.g., depending on the depicted viewpoint). As shown, the longitudinal orientation of isolation trench 120 may be formed at a zero angle or near-zero angle relative to the orientation of the depicted GBL, while the LBLs of the first column depicted (e.g., LBL 140) may be formed at an angle ranging from 10 degrees to 80 degrees.

[0079] In the illustrated example, at least a portion of the left end of LBL 145 may be formed within the gap between isolation trench 130 and the next isolation trench below isolation trench 130. Similarly, at least a portion of the right end of LBL 145 may be formed within the gap between isolation trench 135 and the next isolation trench below isolation trench 135. As shown, the LBLs of the depicted architecture 100 may be tilted during formation. For example, the LBLs of the depicted second column (e.g., LBL 145) may be formed at an angle relative to a given GBL or isolation trench. As shown, the longitudinal orientation of isolation trench 130 may be formed at a zero angle or near-zero angle relative to the orientation of the depicted GBL, while the LBLs of the depicted second column (e.g., LBL 145) may be formed at an angle ranging from 100 degrees to 170 degrees (e.g., -10 degrees to -80 degrees).

[0080] In the illustrated example, the LBL (e.g., LBL 140, LBL 145) may extend in the z-direction relative to the GBL (e.g., GBL 160, GBL 165, GBL 170, GBL 175) (e.g., from...). Figure 1 The depicted viewpoint extends into the page. The depicted connectors (e.g., connector 150, connector 155) can be positioned on top of the depicted LBL, and the GBL can extend laterally above the connectors.

[0081] The depicted staggered trench isolation configuration allows for folded bitline structures, which improve sense margin and noise immunity compared to open bitline structures. This arrangement enables more efficient use of space and can potentially improve overall memory performance.

[0082] Figure 2Details of architecture 200 according to one or more implementations as described herein are shown. Architecture 200 may depict a perspective view or viewpoint of stacked memory modules. For example, architecture 200 may depict a cross-sectional view or side view of stacked memory modules. In particular, architecture 200 may depict a cross-sectional view of folded bit lines based on interleaved trench isolation (e.g., interleaved capacitive deep trench isolation (CDTI)). For example, architecture 200 may depict... Figure 1 A cross-sectional view of architecture 100. In some configurations, one or more aspects of architecture 200 may be implemented by or in combination with a manufacturing apparatus configured to (e.g., based on removal, etching, forming, deposition, etc.) form features and components for semiconductor manufacturing.

[0083] In the illustrated example, architecture 200 may include a substrate 205, an LBL 210, at least one connector (e.g., connector 150, connector 155), a cover material (e.g., cover 220, cover 225, dielectric cover, semiconductor cover, metal cover, etc.), and a semiconductor 230. As shown, architecture 200 may include one or more capacitors (e.g., capacitor 235).

[0084] In the illustrated example, a transistor may include a semiconductor (e.g., semiconductor 230), a gate (e.g., gate 240), a gate oxide (e.g., gate oxide 245), and a dielectric (e.g., dielectric 250). Semiconductor 230 and capacitor 235 may form a memory cell of architecture 200. As shown, a given semiconductor may be formed adjacent to a gate (e.g., gate metal), wherein the gate oxide separates the semiconductor and the gate. For example, semiconductor 230 may be formed adjacent to gate 240 (e.g., gate metal), wherein gate oxide 245 separates semiconductor 230 from gate 240. As shown, gate 240 may be formed adjacent to a dielectric (e.g., dielectric 250). In some cases, gate 240 may surround dielectric 250. As shown, the depicted capacitor (e.g., capacitor 235) may be connected to a corresponding transistor (e.g., semiconductor 230 connected to capacitor 235).

[0085] As shown, architecture 200 may include a first semiconductor stack (e.g., semiconductor 230, capacitor 235) formed on top of substrate 205 and under cover 220, and a second semiconductor stack formed on top of substrate 205 and under cover 225. As shown, LBL 210 can connect a first set of memory cells (e.g., a first set of memory cells under cover 220, including semiconductor 230 and capacitor 235) to contact (CC) 215. Similarly, LBL 210 can connect a second set of memory cells (e.g., a second set of memory cells under cover 225) to contact 215. Contact 215 can connect LBL 210 to a global bit line. The global bit line can be connected to a sense amplifier.

[0086] Figure 3 Example architecture 300 is illustrated according to one or more implementations as described herein. Architecture 300 may depict a perspective view or viewpoint of stacked memory modules. For example, architecture 300 may depict a top-down view of stacked memory modules. In some configurations, one or more aspects of architecture 300 may be implemented by or in combination with a manufacturing apparatus configured to (e.g., based on removal, etching, forming, deposition, etc.) form features and components of semiconductor fabrication.

[0087] Architecture 300 may include substrate 305, multiple sense amplifiers (e.g., SA 310, SA 315) and multiple isolation trenches (e.g., isolation trench 320, isolation trench 325, isolation trench 330, isolation trench 335).

[0088] Architecture 300 may also include one or more local bit line (LBL) conductors. For example, architecture 300 may include LBL conductor 340 and LBL conductor 345. These LBL conductors may be formed of a conductive material such as polysilicon, metal, or semiconductor material.

[0089] In some cases, architecture 300 may include multiple connectors. For example, architecture 300 may include connectors 350 and 355. These connectors can be used to establish electrical connections between different components or layers within the memory structure. As shown, connector 350 may be connected to LBL conductor 340 (e.g., at the top portion of LBL conductor 340 as depicted in the top-down view) and connector 355 may be connected to LBL conductor 345 (e.g., at the top portion of LBL conductor 345 as depicted in the top-down view).

[0090] Architecture 300 may further include multiple Global Bit Lines (GBLs). As shown, architecture 300 may include GBL360, GBL365, GBL370, and GBL375. In the example shown, GBL360 and GBL365 may be connected to SA 310, while GBL370 and GBL375 may be connected to SA 315. These global bit lines can be used to transmit data signals between memory cells and sense amplifiers. In the depicted top-down view, the depicted LBL conductor may extend downwards into the page. Furthermore, memory cells may extend downwards into the page adjacent to and connected to the LBL conductor.

[0091] The arrangement of components in architecture 300 can facilitate a folded bitline structure. For example, GBL 360 and GBL 365 can be connected to SA 310, while GBL 370 and GBL 375 can be connected to SA 315. Compared to an open bitline structure, this configuration allows for improved noise immunity and sensing margin. Furthermore, this configuration allows for more efficient noise cancellation during read operations. For example, when SA 310 reads a signal on GBL 360, GBL 365 can be used as a voltage reference, and vice versa. Similarly, when SA 315 reads a signal on GBL 370, GBL 375 can be used as a voltage reference, and vice versa.

[0092] In some cases, local bit lines in architecture 300 can be tilted. For example, connector 350 can be connected to tilted local bit lines. This tilting configuration of local bit lines can facilitate folding bit line structures and allow for more efficient use of space within the memory architecture.

[0093] In the illustrated example, LBL conductors can be formed within the gaps between the isolation trenches. For example, LBL conductor 340 (e.g., and connector 350) can be formed within the gap between isolation trench 320 and the next isolation trench below it. Similarly, LBL conductor 345 (e.g., and connector 355) can be formed within the gap between isolation trench 325 and the next isolation trench below it. As shown, LBL conductors and connectors can be formed within the gap between isolation trench 330 and the next isolation trench below it. Similarly, LBL conductors and connectors can be formed within the gap between isolation trench 335 and the next isolation trench below it. In some embodiments, the angle of the connecting line connecting the center of LBL conductor 345 and the center of LBL conductor 340 is in the range of 10 degrees to 80 degrees relative to the orientation of the isolation trench.

[0094] In some implementations, based on offset isolation trenches, at least a portion of the GBL can be at least partially aligned with or across some isolation trenches and at least partially pass between other isolation trenches (e.g., at least partially aligned with or across the gap between other isolation trenches). For example, GBL 360 can be at least aligned with the gap between isolation trench 325 and the next isolation trench below isolation trench 325, and at least partially aligned with the gap between isolation trench 335 and the next isolation trench below isolation trench 335. Furthermore, GBL 360 can be at least partially aligned with or across isolation trenches 320 and 330. Similarly, GBL 365 can be at least aligned with the gap between isolation trench 320 and the next isolation trench below isolation trench 320, and at least partially aligned with the gap between isolation trench 330 and the next isolation trench below isolation trench 330. In addition, GBL 365 can at least partially align with or extend beyond the next isolation trench below isolation trench 325 and the next isolation trench below isolation trench 335.

[0095] The staggered arrangement of isolation trenches (e.g., isolation trench 325, isolation trench 330, isolation trench 335) can facilitate the formation of a folded bit line structure. This staggered configuration allows memory cells and bit lines to be positioned in a manner that supports a folded bit line architecture.

[0096] Figure 4 Example architecture 400 is shown according to one or more implementations as described herein. Architecture 400 may depict a perspective view or viewpoint of stacked memory modules. For example, architecture 400 may depict a cross-sectional view or side view of stacked memory modules. In particular, architecture 400 may depict a cross-sectional view of folded bit lines based on interleaved trench isolation (e.g., interleaved capacitive deep trench isolation (CDTI)). For example, architecture 400 may depict... Figure 3 A cross-sectional view of architecture 300. In some configurations, one or more aspects of architecture 400 may be implemented by or in combination with a manufacturing apparatus configured to (e.g., based on removal, etching, forming, deposition, etc.) form features and components for semiconductor manufacturing.

[0097] In the illustrated example, architecture 400 may include a substrate 405, a local bit line (LBL) 410, a connector 415 (e.g., a first connector), and a cap 420 (e.g., a cap material, a dielectric cap, a semiconductor cap, a metal cap, etc.). Architecture 400 may also include a connector 425 (e.g., a second connector) and an LBL 455. As shown, connector 415 may be connected to LBL 410. Connector 425 may be connected to LBL 455.

[0098] Architecture 400 may include multiple stacks of memory cells formed on top of substrate 405. In some cases, a first memory cell stack may be formed on the left side of architecture 400, while a second memory cell stack may be formed on the right side. Each stack may include one or more memory cells.

[0099] The memory cell in architecture 400 may include a semiconductor 430 connected to a capacitor 435. For example, the semiconductor 430 may be electrically connected to the capacitor 435 to form a single memory cell within a first stack.

[0100] In some cases, semiconductor 430 may be formed adjacent to gate 440. Gate oxide 445 may separate semiconductor 430 from gate 440. Gate 440 may be positioned adjacent to dielectric 450. In some implementations, gate 440 may surround dielectric 450.

[0101] The LBL of architecture 400 may include LBL 410, LBL 455, and LBL conductor 460. LBL conductor 460 may be formed of a conductive material such as metal, semiconductor, or polysilicon. In some cases, LBL 410 may connect a first memory cell stack (e.g., a first memory cell stack on the left, including semiconductor 430 and capacitor 435) to connector 415. Similarly, LBL 455 may connect a second memory cell stack (e.g., a second memory cell stack on the right) to connector 425. As shown, a first portion of LBL conductor 460 may connect a first memory cell stack to LBL 410. Similarly, a second portion of LBL conductor 460 may connect a second memory cell stack to LBL 455.

[0102] Architecture 400 can be based on an interleaved arrangement of capacitive deep trench isolation (CDTI), which can facilitate the formation of a folded bitline structure. This interleaved configuration allows memory cells and bitlines to be positioned in a manner that supports a folded bitline architecture. Compared to open bitline structures, interleaved CDTI can allow for improved sense margin and noise immunity. The improved sense margin can be achieved through the arrangement of local and global bitlines in a folded configuration. This configuration can allow for more efficient signal routing within the memory array and potentially improve overall memory performance.

[0103] The staggered arrangement of isolation trenches allows for more efficient use of space within the memory architecture and can improve overall memory performance. This staggered arrangement of isolation trenches can potentially lead to higher-density memory designs. In some cases, the staggered arrangement of isolation trenches can allow for a greater process margin regarding the sense amplifier pitch. This greater process margin can provide greater flexibility in manufacturing and can potentially increase yield. In some cases, the greater process margin regarding the sense amplifier pitch can enable better integration with core and peripheral transistors. For example, when integrating memory arrays with other components in a system-on-a-chip design, the additional margin regarding the sense amplifier pitch can allow for more efficient bonding processes.

[0104] In some cases, the combination of staggered isolation trenches and folded bitline architectures can produce memory designs that balance performance, density, and manufacturability. These design features can work together to address challenges in 3D-DRAM design, potentially leading to improved memory solutions for a wide range of applications.

[0105] Figure 5 A flowchart illustrating an example method 500 associated with the disclosed system according to an example implementation described herein is depicted. In some configurations, one or more aspects of method 500 may be implemented by or in combination with a manufacturing apparatus configured to (e.g., based on removal, etching, forming, deposition, etc.) form features and components of semiconductor fabrication. The depicted method 500 is merely one implementation, and one or more operations of method 500 may be rearranged, reordered, omitted, and / or otherwise modified to make other implementations possible and contemplated.

[0106] At 505, method 500 may include offsetting the isolation trenches. For example, the manufacturing apparatus may offset the position of the first set of isolation trenches relative to the position of the second set of isolation trenches based on a given view of the stacked memory system (e.g., a top-down view). In some cases, from the view of the stacked memory system, the manufacturing apparatus may offset the position of the third set of isolation trenches relative to the position of the fourth set of isolation trenches.

[0107] At 510, method 500 may include forming a first local bit line at a first angle. For example, the manufacturing equipment may form the first local bit line at a first angle relative to a first set of isolation trenches and a second set of isolation trenches.

[0108] At 515, method 500 may include forming a second local bit line at a second angle. For example, the manufacturing equipment may form the second local bit line at a second angle relative to a third set of isolation trenches and a fourth set of isolation trenches, the second angle being different from the first angle.

[0109] Figure 6 A flowchart illustrating an example method 600 associated with the disclosed system according to an example implementation described herein is depicted. In some configurations, one or more aspects of method 600 may be implemented by or in combination with a manufacturing apparatus configured to (e.g., based on removal, etching, forming, deposition, etc.) form features and components of semiconductor fabrication. The depicted method 600 is merely one implementation, and one or more operations of method 600 may be rearranged, reordered, omitted, and / or otherwise modified to make other implementations possible and contemplated.

[0110] At 605, method 600 may include offsetting the isolation trenches. For example, the manufacturing apparatus may offset the position of the first set of isolation trenches relative to the position of the second set of isolation trenches based on a given perspective of the stacked memory system (e.g., a top-down view).

[0111] At 610, method 600 may include forming a first partial bit line between the isolation trenches. For example, a manufacturing apparatus may form the first partial bit line between a first isolation trench and a second isolation trench in a first set of isolation trenches.

[0112] At 615, method 600 may include forming a second local bit line between the isolation trenches. For example, the manufacturing equipment may form the second local bit line between the third and fourth isolation trenches of the second set of isolation trenches.

[0113] In the examples described herein, the configurations and operations are example configurations and operations, and various additional configurations and operations may be involved that are not explicitly shown. In some examples, one or more aspects of the configurations and / or operations shown may be omitted. In some implementations, one or more operations may be performed by components other than those shown herein. Additionally or alternatively, the order and / or timing of operations may be changed.

[0114] Some implementations may be implemented in one or a combination of hardware, firmware, and software. Other implementations may be implemented as instructions stored on a computer-readable storage device that can be read and executed by at least one processor to perform the operations described herein. A computer-readable storage device may include any non-transitory memory mechanism for storing information in a machine-readable (e.g., computer) form. For example, a computer-readable storage device may include read-only memory (ROM), random access memory (RAM), disk storage media, optical storage media, flash memory devices, and other storage devices and media.

[0115] The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations. As used herein, the terms "computing device," "user equipment," "communication station," "station," "handheld device," "mobile device," "wireless device," and "user equipment (UE)" refer to wired and / or wireless communication devices such as switches, routers, network interface controllers, cellular phones, smartphones, tablets, netbooks, wireless terminals, laptops, femtocell base stations, high data rate (HDR) user stations, access points, printers, point-of-sale equipment, access terminals, or other personal communication system (PCS) devices. Such devices can be wireless, wired, mobile, and / or stationary.

[0116] As used herein, the term "communication" is intended to include sending, or receiving, or both. Similarly, when protection is required only for the functionality of one of those devices, a two-way exchange of data between two devices (where both devices send and receive during the exchange) can be described as "communication." As used herein with respect to wired and / or wireless communication signals, the term "communication" includes sending and / or receiving wired and / or wireless communication signals. For example, a communication unit capable of transmitting wired and / or wireless communication signals may include a wired / wireless transmitter that sends communication signals to at least one other communication unit, and / or a wired / wireless receiver that receives communication signals from at least one other communication unit.

[0117] Some implementations can be used with a variety of devices and systems, such as personal computers (PCs), desktop computers, mobile computers, laptop computers, notebook computers, tablet computers, server computers, handheld computers, handheld devices, personal digital assistant (PDA) devices, handheld PDA devices, onboard devices, offboard devices, hybrid devices, in-vehicle devices, off-vehicle devices, mobile or portable devices, consumer devices, non-mobile or non-portable devices, wireless communication stations, wireless communication devices, wireless access points (APs), wired or wireless routers, wired or wireless modems, video devices, audio devices, audio-video (A / V) devices, wired or wireless networks, wireless local area networks, wireless video local area networks (WVANs), local area networks (LANs), wireless LANs (WLANs), personal area networks (PANs), wireless PANs (WPANs), etc.

[0118] Some implementations can be used in conjunction with one-way and / or two-way radio communication systems, cellular wireless telephone communication systems, mobile phones, cell phones, wireless phones, personal communication system (PCS) devices, PDA devices that include wireless communication devices, mobile or portable global positioning system (GPS) devices, devices that include GPS receivers or transceivers or chips, devices that include RFID elements or chips, multiple-input multiple-output (MIMO) transceivers or devices, single-input multiple-output (SIMO) transceivers or devices, multiple-input single-output (MISO) transceivers or devices, devices with one or more internal antennas and / or external antennas, digital video broadcasting (DVB) devices or systems, multi-standard wireless devices or systems, wired or wireless handheld devices (e.g., smartphones), Wireless Application Protocol (WAP) devices, etc.

[0119] Some implementations can be used in conjunction with one or more types of wireless communication signals and / or systems that comply with one or more wireless communication protocols, such as radio frequency (RF), infrared (IR), frequency division multiplexing (FDM), orthogonal FDM (OFDM), time division multiplexing (TDM), time division multiple access (TDMA), extended TDMA (E-TDMA), General Packet Radio Service (GPRS), extended GPRS, code division multiple access (CDMA), wideband CDMA (WCDMA), CDMA 2000, single-carrier CDMA, multi-carrier CDMA, multi-carrier modulation (MDM), discrete multi-tone (DMT), and Bluetooth. TM Global Positioning System (GPS), Wi-Fi, Wi-Max, ZigBee TM Ultra-wideband (UWB), Global System for Mobile Communications (GSM), 2G, 2.5G, 3G, 3.5G, 4G, fifth-generation (5G) mobile networks, 3GPP, Long Term Evolution (LTE), LTE Advanced, Enhanced Data Rate Evolution of GSM (EDGE), etc. Other implementations can be used in a variety of other devices, systems, and / or networks.

[0120] Although an example processing system has been described above, the implementation of the subject matter and functional operations described herein can be implemented in other types of digital electronic circuits, or in computer software, firmware, or hardware (including the structures disclosed in this specification and their equivalents), or in one or more combinations thereof.

[0121] The embodiments of the subject matter and operations described herein can be implemented in digital electronic circuits, or in computer software, firmware, or hardware (including the structures disclosed herein and their equivalents), or in a combination of one or more of these. Embodiments of the subject matter described herein can be implemented as one or more computer programs (i.e., one or more components of computer program instructions) encoded on a computer storage medium for execution by or control of the operation of an information / data processing device. Alternatively or additionally, the program instructions can be encoded on artificially generated propagating signals (e.g., machine-generated electrical, optical, or electromagnetic signals) generated to encode information / data for transmission to a suitable receiver device for execution by the information / data processing device. The computer storage medium can be a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination of one or more of these, or can be included therein. Furthermore, while the computer storage medium is not a propagating signal, it can be a source or destination of computer program instructions encoded in artificially generated propagating signals. Computer storage media can also be one or more separate physical components or media (e.g., multiple CDs, disks or other storage devices), or be included in one or more separate physical components or media.

[0122] The operations described herein can be implemented as operations performed by an information / data processing device on information / data stored on one or more computer-readable storage devices or received from other sources.

[0123] The term "data processing apparatus" includes all kinds of devices, apparatuses, and machines for processing data, including, for example, programmable processors, computers, systems-on-a-chip, or a combination thereof. The apparatus may include special-purpose logic circuitry, such as FPGAs or ASICs. In addition to hardware, the apparatus may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, protocol stacks, database management systems, operating systems, cross-platform runtime environments, virtual machines, or one or more combinations thereof. The apparatus and execution environment can implement a variety of different computing model infrastructures, such as web services, distributed computing, and grid computing infrastructures.

[0124] Computer programs (also known as programs, software, software applications, scripts, or code) can be written in any programming language, including compiled or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as standalone programs or as components, subroutines, objects, or other units suitable for a computing environment. A computer program may, but does not necessarily, correspond to a file in a file system. A program may be stored as a part of a file that holds other programs or information / data (e.g., stored in one or more scripts in a markup language document), in a single file dedicated to the program in question, or in multiple coordinating files (e.g., files storing one or more components, subroutines, or code sections). Computer programs can be deployed to execute on one computer or on multiple computers located at a site or distributed across multiple sites and interconnected through a communication network.

[0125] The processes and logical flows described herein can be executed by one or more programmable processors that execute one or more computer programs to perform actions by manipulating input information / data and generating output. Processors suitable for executing computer programs include, for example, both general-purpose microprocessors and special-purpose microprocessors, as well as any type of digital computer, and any one or more processors. Typically, the processor receives instructions and information / data from read-only memory or random access memory, or both. The basic elements of a computer are a processor for performing actions according to instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include one or more mass storage devices (e.g., magnetic disks, magneto-optical disks, or optical disks) for storing data, or will be operatively coupled to receive information / data from one or more mass storage devices or transfer information / data to one or more mass storage devices, or both. However, a computer does not need to have such devices. Devices suitable for storing computer program instructions and information / data include all forms of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices such as EPROM, EEPROM, and flash memory devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; and CD-ROMs and DVD-ROMs. Processors and memory can be supplemented by dedicated logic circuits or incorporated into dedicated logic circuits.

[0126] To provide interaction with the user, the embodiments of the subject matter described herein can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) for displaying information / data to the user) and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback, such as visual feedback, auditory feedback, or tactile feedback; and input from the user can be received in any form, including acoustic, voice, or tactile input. Furthermore, the computer can interact with the user by sending documents to and receiving documents from the device used by the user; for example, by sending a web page to a web browser on the user's client device in response to a request received from a web browser.

[0127] The embodiments of the subject matter described herein can be implemented in a computing system that includes backend components (e.g., as an information / data server), middleware components (e.g., an application server), frontend components (e.g., a client computer with a graphical user interface or web browser through which a user can interact with the embodiments of the subject matter described herein), or any combination of one or more such backend components, middleware components, or frontend components. The components of the system can be interconnected via digital information / data communication (e.g., a communication network) of any form or medium. Examples of communication networks include local area networks (LANs) and wide area networks (WANs), interconnected networks (e.g., the Internet), and peer-to-peer networks (e.g., self-organizing peer-to-peer networks).

[0128] A computing system may include clients and servers. Clients and servers are typically geographically separated and usually interact via a communication network. The client-server relationship is established by computer programs running on respective computers and having a client-server relationship with each other. In some implementations, the server transmits information / data (e.g., HTML pages) to the client device (e.g., for the purpose of displaying information / data to a user interacting with the client device and receiving user input from them). Information / data generated at the client device (e.g., the result of user interaction) may be received at the server from the client device.

[0129] While this specification contains numerous details of specific implementations, these should not be construed as limiting the scope of any implementation or potentially claimed content, but rather as descriptions of features specific to particular implementations. Certain features described herein in the context of individual implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple implementations. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed in this way, one or more features from a claimed combination may be removed from the combination in some cases, and the claimed combination may be for sub-combinations or variations thereof.

[0130] Similarly, although the operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring these operations to be performed in the specific order shown or sequentially, or as requiring all the operations shown to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of the various system components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0131] Therefore, specific embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific order or sequence shown to achieve the desired result. In some embodiments, multitasking and parallel processing may be advantageous.

[0132] Benefiting from the teachings presented in the foregoing description and the accompanying drawings, those skilled in the art will conceive of numerous modifications and other examples as set forth herein. Therefore, it should be understood that the embodiments are not limited to the specific embodiments disclosed, and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terminology is used herein, it is used only in a general and descriptive sense and not for limiting purposes. Several exemplary implementations have been described. However, it will be understood that various modifications can be made without departing from the spirit and scope of this disclosure. Therefore, additional implementations are within the scope of the appended claims.

[0133] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 720,157, filed November 13, 2024, which is incorporated herein by reference for all purposes.

Claims

1. A stacked memory device, comprising: The first group of isolation trenches and the second group of isolation trenches are positioned relative to the second group of isolation trenches. A first local bit line formed at a first angle relative to the orientation of the first group of isolation trenches and the second group of isolation trenches; The third group of isolation trenches and the fourth group of isolation trenches, wherein the position of the third group of isolation trenches is offset relative to the position of the fourth group of isolation trenches; as well as The second local position line is formed at a second angle relative to the orientation of the third group of isolation trenches and the fourth group of isolation trenches, and the second angle is different from the first angle.

2. The stacked memory device of claim 1, wherein the first angle of the first local bit line is in the range of 10 degrees to 80 degrees relative to the orientation of the first set of isolation trenches and the second set of isolation trenches oriented at zero angle.

3. The stacked memory device according to claim 2, wherein: The first connector connects the first local bit line to the first global bit line. The first global bit line connects the first local bit line to the first sensing amplifier, and The first global bit line is positioned at zero angle.

4. The stacked memory device according to claim 1, wherein: The second angle of the second local bit line is in the range of 100 to 170 degrees relative to the orientation of the third and fourth sets of isolation trenches, which are oriented at zero angle.

5. The stacked memory device according to claim 4, wherein: The second connector connects the second local bit line to the second global bit line. The second global bit line connects the second local bit line to the second sensing amplifier, and The second global bit line is positioned at zero angle.

6. The stacked memory device of claim 1, wherein a first portion of the first local bit line is formed between a first isolation trench and a second isolation trench of the first set of isolation trenches.

7. The stacked memory device of claim 1, wherein a second portion of the first local bit line is formed between the third and fourth isolation trenches of the second set of isolation trenches.

8. The stacked memory device of claim 1, wherein the first local bit line is connected to the first column memory cell and the second column memory cell.

9. A stacked memory device, comprising: The first group of isolation trenches and the second group of isolation trenches are positioned relative to the second group of isolation trenches. A first local bit line is formed between the first isolation trench and the second isolation trench in the first group of isolation trenches; as well as A second local bit line is formed between the third and fourth isolation trenches of the second group of isolation trenches.

10. The stacked memory device of claim 9, wherein the position of the first local bit line is offset relative to the position of the second local bit line.

11. The stacked memory device of claim 9, wherein the angle of the connecting line connecting the center of the first local bit line and the center of the second local bit line is in the range of 10 degrees to 80 degrees relative to the orientation of the first set of isolation trenches and the second set of isolation trenches oriented at zero angle.

12. The stacked memory device according to claim 9, wherein: The first connector connects the first local bit line to the first global bit line, and The first global bit line connects the first local bit line to the first sense amplifier.

13. The stacked memory device of claim 12, wherein: The first global bit line is at least partially located between the first isolation trench and the second isolation trench, and The first global bit line is positioned at zero angle.

14. The stacked memory device according to claim 9, wherein: The second connector connects the second local bit line to the second global bit line, and The second global bit line connects the second local bit line to the second sense amplifier.

15. The stacked memory device of claim 14, wherein: The second global bit line is at least partially located between the third isolation trench and the fourth isolation trench, and The second global bit line is positioned at zero angle.

16. The stacked memory device of claim 9, wherein: The first local bit line is connected to the first column memory cell, and The second local bit line is connected to the second column memory cell.

17. A method comprising: The position of the first set of isolation trenches is offset relative to the position of the second set of isolation trenches; A first local bit line is formed at a first angle relative to the orientation of the first set of isolation trenches and the second set of isolation trenches; The position of the third set of isolation trenches is shifted relative to the position of the fourth set of isolation trenches; as well as A second local bit line is formed at a second angle relative to the orientation of the third group of isolation trenches and the fourth group of isolation trenches, the second angle being different from the first angle.

18. The method of claim 17, wherein the first angle of the first local bit line is in the range of 10 degrees to 80 degrees relative to the orientation of the first set of isolation trenches and the second set of isolation trenches oriented at zero angle.

19. The method of claim 17, wherein: The first connector connects the first local bit line to the first global bit line. The first global bit line connects the first local bit line to the first sensing amplifier, and The first global bit line is positioned at zero angle.

20. The method of claim 17, wherein: The second angle of the second local bit line is in the range of 100 to 170 degrees relative to the orientation of the third and fourth sets of isolation trenches, which are oriented at zero angle.

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