ADAPTIVE VIDEO ROTATION SPEED FOR VIDEO DELIVERY

Abstract

Systems and methods for adaptively adjusting the spin rate of a destabilizer buffer on a remote device in a distributed access architecture. The spin rate can be adjusted based on measurements of the buffer's fullness state taken over time. These measurements can be used to calculate a frequency offset value between the rate at which data leaves the buffer and the rate at which data enters the buffer, and / or to calculate the buffer's current working depth. Adaptive spin rate adjustments can be based on the frequency offset value and / or the current working depth.

Description

ADAPTIVE VIDEO ROTATION SPEED FOR VIDEO DELIVERY CROSS REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. provisional serial number 63 / 144,367 filed on February 1, 2021. BACKGROUND The subject matter of this application generally relates to the provision of video content using distributed access architectures (DAA) of a hybrid CATV network, and more particularly to architectures that distribute the functions of the cable modem termination system between a core and a remote device synchronized to the core, such as a remote PHY device or remote MACPHY device. Although cable television (CATV) networks originally delivered content to subscribers over long distances using only RF transmission, modern CATV transmission systems have replaced much of the RF transmission path with a more efficient optical network, creating a hybrid transmission system where cable content terminates as RF signals over coaxial cables but is transmitted over most of the distance between the content provider and the subscriber using optical signals. Specifically, CATV networks include a headend at the content provider to receive signals representing many content channels, multiplex them, and distribute them across a fiber optic network to one or more nodes, each serving a group of subscribers.The node then demultiplexes the received optical signal and converts it into an RF signal so that it can be received by viewers. The system at the headend that provides video channels to a subscriber typically comprises a plurality of EdgeQAM units operating in different frequency bands, which are combined and multiplexed before being output on the HFC network. A traditional HFC architecture includes a headend containing a cable modem termination system (CMTS), used to provide high-speed data services, such as video, cable Internet, Voice over Internet Protocol (VoIP), etc., to cable subscribers. A CMTS typically includes both Ethernet interfaces (or other more traditional high-speed data interfaces) and RF interfaces so that traffic from the Internet can be routed (or connected) through the Ethernet interface, via the CMTS, and then to the optical RF interfaces that connect to the cable company's hybrid fiber-coaxial (HFC) system. Downstream traffic is delivered from the CMTS to a cable modem in a subscriber's home, while upstream traffic is delivered from the cable modem in the subscriber's home back to the CMTS.Many modern CATV HFC systems have combined the functionality of the CMTS with the video delivery system into a single platform called the Converged Cable Access Platform (CCAP). In these traditional HFC architectures, video is modulated over the RF network using Video Edge QAM (VEQ). A VEQ receives single-program and multiple-program transport (SPTS and MPTS) streams encapsulated in Internet Protocol. The VEQ takes 7QQQnn / C7n7 / R / VI (IP) from various sources (unicast / multicast) and, after removing any jitter from the incoming network stream, statically or dynamically assigns these streams to a QAM channel through one or more ports, reassigns program identifiers (PIDs), and multiplexes the individual SPTSs into a single MPTS as needed. The VEQ can also perform local encryption of the video's elementary streams (ES). To supply an MPTS stream on a QAM channel in accordance with ISO 13818-1, the VEQ is required to retrieve the incoming program clock reference (POR) values ​​encoded within each SPTS and re-seal them with the VEQ's internal 27MHz clock so that all streams are supplied with the same time base. As networks have expanded and headends have become increasingly congested with equipment, many content providers have recently adopted distributed architectures to extend CMTS / CCAP functionality throughout the network. This distributed architecture keeps cable video and data signals in digital format for as long as possible and extends the digital signals deeper into the network beyond the CMTS / CCAP before converting them to RF. This is achieved by replacing the analog links between the headend and the access network with a digital fiber (Ethernet / PON) connection. One such distributed architecture is the Remote Distributed Access PHY (R-PHY) architecture, which relocates the physical layer (PHY) of a traditional CMTS or CCAP—including VEQs—by pushing the physical layer to the fiber nodes of the network. Therefore, while the core in the CMTS / CCAP performs upper-layer processing, the RPHY device at the node converts downstream video data packets sent by the core from digital to analog for radio frequency transmission, and also converts upstream RF data sent by cable modems from analog to digital for optical transmission to the core.Another distributed access architecture is Remote MAC PHY (R-MACPHY) where, not only is the physical layer of the traditional CMTS pushed into the network, but the Media Access Control (MAC) layer functionality, which is one of the two layers that make up the data link layer of a transport stream, is also assigned to one or more nodes in the network in what is called a Remote MACPHY Device (RMD). In DAA architectures, therefore, it is the remote video-capable devices, such as RMDs and RPDs, that include the VEQs which modulate a fully formed MPTS stream, sent by a core, to the RF network. One benefit of this arrangement is that RMD / RPD devices are generally lower power than traditional Edge QAM video devices located at a headend, and require fewer computing and memory resources. Similar to a VEQ located at a headend, a VEQ located in an RPD / RMD must map and modulate a fully formed, IP-encapsulated MPTS video stream that it receives from a headend onto one or more QAM channels (one stream per channel), eliminating network jitter in the process.However, the difference relative to a VEQ at a header end is that a VEQ on a remote device only receives a fully encapsulated MPTS sequence, therefore it does not need to multiplex several SPTS contents together. Furthermore, in DAA architectures, however, because the CMTS / CCAP functionality is divided between a core at the headend and multiple PHY or MACPHY devices throughout the network, protocols must be established to accurately preserve the synchronization of the reconstructed video data communicated across the network. Therefore, even though a remote device only receives MPTS video data that has already been synchronized together, the remote device must account for any differences between the clock rate at which it receives data and the clock rate at which it transmits data. For example, the remote DAA device may not be synchronized to the same time base as the CCAP core (asynchronous operation), or even when the CCAP core and the remote device are synchronized to a common clock (synchronous operation), the CCAP core and the remote device may lose their synchronization lock. Thus, what is desired are better systems and methods for accurately preserving the synchronization information associated with video data transmitted in distributed access architectures. Brief description of the figures For a better understanding of the invention, and to show how it can be carried out, reference will now be made, by way of example, to the accompanying figures, in which: Figure 1 shows an illustrative traditional HFC architecture that has video EQAM units, which package MPTS transport streams for sending to downstream nodes. Figure 2 shows an illustrative distributed access architecture that includes a video / CCAP core that sends packetized IP data to a remote physical device (RPD). Figure 3A shows an illustrative system where the video core / CCAP of Figure 2 transmits video data to the RPD in synchronous mode. Figure 3B shows an illustrative system where the video core / CCAP of Figure 2 transmits video data to the RPD in asynchronous mode. Figure 4 shows a first illustrative method for using an adaptive frequency rotation rate to ensure that the video data output of the asynchronous system in Figure 3B is properly synchronized and, at the same time, avoids buffer overflows. Figure 5 shows a second example of using an adaptive frequency rotation speed to ensure that the video data output of the asynchronous system in Figure 3B is properly synchronized while also preventing buffer overflows. Figures 6A and 6B show the results of using adaptive frequency rotation speeds as described in this description. DETAILED DESCRIPTION As mentioned earlier, video EQAM (VEQ) devices are used to receive a large number of video channels and output an RF-modulated signal (i.e., QAM, or quadrature amplitude modulation) that combines the multiple different channels received by the VEQ. Figure 1, for example, shows a traditional architecture whereby an HFC network includes a headend that supplies content to subscriber equipment such as subscriber premises, shown in the figure as a cable modem, but those skilled in the art will understand that subscriber equipment could include set-top boxes, gateways, cordless phones, computers, etc. zQQQnn / cznz / R / vi The HFC network 12 includes a headend 14, a plurality of concentrators 20, and associated with each concentrator, a plurality of nodes 22 and a plurality of subscriber equipment 24 such as cable modems. The headend 14 typically includes a cable modem termination system (CMTS) 13 and a plurality of video EQAM units 16. Each of the nodes 22 has one or more corresponding access points, and each subscriber may have one or more corresponding network elements 24, shown in Figure 1 as a cable modem. As also mentioned earlier, in these traditional HFC architectures 10, video is modulated on the RF network by the VEQs 16, which receive single- and multiple-program transport streams (SPTS and MPTS) encapsulated in Internet Protocol (IP) from various sources (content providers, etc.) via the content delivery network 26.The content delivery network is typically a switched network through which packetized IP data is routed from one address to another and can exhibit unpredictable and variable delays in received packets. Therefore, the VEQ 16 preferentially eliminates this fluctuation from the incoming network stream before allocating and modulating the video data across multiple QAM channels. As also mentioned earlier, delivering an MPTS stream on a QAM channel in accordance with ISO 13818-1 requires the VEQ to retrieve the encoded incoming Program Clock Reference (PCR) values ​​within each SPTS and re-seal them with the VEQ's internal 27MHz clock so that all streams are delivered on the same time base. Figure 2 illustrates an alternative distributed access (DAA) architecture in which the VEQ functionality is moved to a node. Specifically, Figure 2 shows what is known as a Remote Physical Architecture (R-PHY) 50, in which a video core / CCAP 54 sends data to a Remote Physical Device (RPD) 56, which in turn connects to one or more consumer premises equipment (CPE) devices 18, such as a set-top box, cable modem, etc. Although an R-PHY architecture is illustrated in Figure 2, it should be understood that the description herein is equally applicable to other DAA architectures, such as R-MACPHY architectures, for example. In some configurations, a master synchronization device 52 may be available to provide synchronization information to both the video core / CCAP 54 and the RPD 56.Specifically, the main synchronization master 52 has a first master port 60a connected to a secondary clock 62 on the CCAP core 54 and a second master port 60b connected to a secondary clock 64 on the RPD 56, although alternatively the respective secondary clocks of the CCAP core 54 and the RPD 56 can be connected to a single master port on the main synchronization master device 52. The CCAP core 54 can be connected to the main synchronization master 52 through one or more switches 66, while the RPD 56 can be connected to the main synchronization master 52 through one or more switches 68. Although Figure 2 shows only one RPD 56 connected to the main synchronization master 52, many such RPDs can be simultaneously connected to the main master 52, where each RPD has a secondary clock 64 that receives synchronization information from a port 60b on the main clock 52. Although the architecture in Figure 2 shows a common main master device 52 capable of synchronizing the video core / CCAP 54 with the RPD 56, the architecture in Figure 2 can also be configured to operate 7QQQnn / C7n7 / R / YI asynchronously, where the main master device 52 does not send common synchronization information to the core 54 / RPD 56. For example, the RPD 56 can be configured to operate asynchronously if the video core / CCAP 54 does not support IEEE 1588 synchronization protocols, or if it is desired that the RPD 56 be more resilient to hold periods in the event that the RPD and / or the core lose connection with the main synchronization master. Additionally, in an R-MACPHY system, an RMD will generally be set to asynchronous mode by default to eliminate the need for 15888 synchronization, as DOCSIS services do not require it, although the RMS input can be switched to synchronization mode if other services such as wireless backhaul require IEEE 1588 services, or if the oscillator of the video core 54 is of poor quality and requires an external synchronization source.Therefore, the system shown in Figure 2 can be configured to operate in either synchronized or asynchronous mode for processing video content, and the video core / CCAP 54 and RPD (RMD) 55 each preferably includes hardware capable of operating in either mode, with software that allows configuration by a video core itself and connected downstream devices in either of these alternative modes when configuring video channels. In synchronous mode, the RPD (or RMD) and its video core are synchronized to the same reference clock. In this synchronization mode, the RPD is only needed to detect lost video packets using Layer 2 Tunneling Protocol v3 (L2TPv3) sequence number monitoring and insert MPEG null packets for each missing packet. Figure 3A, for example, shows a system in a first configuration 100 where a video core 102 communicates with an RPD 104 in synchronous mode using a common master synchronization server 106. The synchronization server 106 maintains an identical synchronization lock (i.e., frequency and phase) with both the clock 108 in the video core 102 and the clock 110 in the RPD 104. The video core 102 has a video sequencer 112 that forwards the video data packet to the RPD 104 through an external downstream PHY interface (DEPI) using L2TPv3.Video packets sent from video core 102 to RPD 104 will normally include all the information necessary to decode the packetized elementary video transport stream, such as program identifiers (PIDs), program clock reference data (PCR), etc. The RPD 110, in turn, receives the video packets sent from the video core 108 into a destabilizing buffer 116 of a processing device 114. The destabilizing buffer 116 receives and outputs packet data at a rate that eliminates network jitter resulting from different data paths of received packets, or other sources of variable network delay between the video core and the RPD. Because some packets sent by the video sequencer 112 may be lost or strayed during transport to the RPD 104, the output packets from the destabilizing buffer 116 may be preferentially sent to a module 118 which, in the case of synchronous mode, inserts null packets into the data stream to account for these lost packets, in order to maintain the proper synchronization rate of the transmitted video.The transport sequence, with any necessary insertion of null packets, is then forwarded to a PHY 120 device, which can decode the packetized elementary sequence into a sequence of decoded video frames for downstream delivery to end users by outputting QAM-modulated data in a format expected by the equipment at the customer premises, such as... 7QQQnn / C7n7 / R / YI decoders. Alternatively, the PHY device can simply forward the packetized data, without decoding, to, for example, a cable modem for decoding by a user device such as a computer, tablet, cell phone, etc. In synchronization mode, because the RPD 104 and its video core 102 must synchronize to the same reference clock, the PCR clock frequency contained within the incoming MPTS matches the local clock of the remote device. Therefore, there is no frequency offset in the RPD between the incoming and outgoing streams, and as mentioned earlier, to maintain proper synchronization information in the transmitted video data, the RPD 104 only needs to eliminate network jitter, detect missing video packets using L2TPv3 sequence number monitoring, and insert MPEG NULL packets for each missing packet. Alternatively, however, the RPD and video core can be configured to operate in asynchronous mode. In asynchronous mode, the RPD 104 and its video core 102 do not synchronize to the same reference clock. Instead, the RPD 104 is required to detect the difference between its own clock 110 and the clock 108 of the video core 102 and be able to insert or remove MPEG packets as needed to maintain the expected MPEG bit rate, and also adjust the MPEG PCR values ​​due to the removal / insertion of MPEG packets. Figure 3B, for example, shows the hardware in Figure 2 configured to operate in asynchronous mode instead. In this configuration, the clock of video core 102 and the clock of RPD 104 are not synchronized and can therefore drift from each other. The video sequencer of video core 102 forwards packets from the elementary sequence of packetized video data to RPD 104, which again receives the data in the destigmatization buffer 116 to eliminate network jitter, as described earlier. However, unlike the configuration in Figure 2, the output packets from the destigmatization buffer 116 are forwarded to module 118, which adds null packets as needed and drops packets as needed to maintain the proper constant bit rate of the data received from the destigmatization buffer 116. Furthermore, because the RPD and its video core are not synchronized to the same reference clock, the PCR frequency in the incoming MPTS will be offset by the local RPD clock. Therefore, in addition to performing the functions common to those performed in synchronization mode, the RPD must also detect and correct the magnitude of the video core frequency offset. To this end, after adding / removing packets as needed, a PCR module 119 reseals the data packets with updated PCRs due to the removal / insertion of MPEG packets before forwarding the resealed packets to the PHY device 120. Another consideration in asynchronous mode is the limited size of the jitter buffer. Since there is a offset between the input and output frequencies, if the jitter buffer is not flagged, it can tend to overflow or empty depending on the sign of the frequency difference. Therefore, systems and methods must be employed to prevent the buffer from overflowing or emptying. The following section describes novel detection and correction methods for this frequency offset in asynchronous operation mode, taking into account 7QQQnn / C7n7 / R / YI takes into account its limited memory size (buffer), while simultaneously maintaining precise synchronization of the video data being processed. As previously mentioned, network jitter is eliminated by using a “destabilization” buffer 116 shown in Figure 3B. This destabilization buffer 116 is preferentially filled initially to its midpoint as the MPTS sequence supply begins. Destabilization is typically achieved by using a low-pass filter that averages the delays over a sufficiently long interval; therefore, the destabilization buffer 116 is preferably large enough to absorb fluctuations in buffer depth caused by fluctuations in the input current without underflow or overflow. The frequency differences between the incoming PCR and the local RPD clock (i.e., the egress rate) will manifest as a deviation in the destabilization buffer depth after low-pass filtering. This will produce the rate of deviation in the tail depth caused by frequency offset. This rate of deviation is directly proportional to the frequency offset between the incoming PCR and the local clocks. Specifically, the incoming frequency Fi is directly proportional to the incoming bit rate Bi. F¿ a Bi and the output frequency Fo is directly proportional to the output bit rate Bo Foa Bodonde the difference between the input and output frequencies is expressed in terms of a frequency offset 7QQQnn / C7n7 / R / YI of parts per million (PPM) dimensionless. F'Fux 106= Δ ppm. ^0 Therefore, Δ ppm 106dQ △ PPm~dt , , ----- - -- where 106Bo=íFcuaci Ft _ Bt Fo Bo Fi Bt -F- 1 = -A- 1 Fq Bo Fí ~ Fo_ B, — Bo Fq Bo Bí — BoFL- Fo—--- where —-—x 106= △ ppm Bq FodQ —— is ία rate of change of the tail depth at 5n 1) dt 10° ' ' To prevent the growth / shrinkage of the destabilizer buffer, the RPD must rotate its output frequency to match the input frequency. ISO / IEC 13818-1 specifies a maximum value for this frequency rotation rate. Therefore, the system clock frequency, measured in Hz, should and will comply with the following restrictions: 000 000 - 810 <= system clock frequency <= 27 000 000+810 rate of change of system clock frequency with time <= 75 x 10-3 Hz / s A typical frequency offset for a hardware-based video engine is + / - 5 ppm. However, for a software-based video engine where synchronization is provided by a standard crystal-based oscillator, this accuracy is likely to be substantially lower. The ISO 13818-1 specification allows for an accuracy of + / - 810 Hz on a 27 MHz clock, which equates to an offset of 30 ppm. If the 102 video core were to supply an asynchronous MPTS, with a frequency offset of 30 ppm and the RPD clock offset of 5 ppm in the opposite direction, the relative frequency offset would be 35 ppm. If no correction has been made to this frequency compensation, the time required to reach an overshoot / undershoot buffer condition depends on the size of the destabilization buffer in the RPD device. The available working depth of the destabilization buffer is given by: Qlen / 2 - Jmax, where Jmax is the maximum fluctuation Therefore, if no frequency correction is applied, the overflow / underflow time provided by the destabilization buffer is: t = (Qlen / 2 - Jmax) / |f and substituting for Eq. 1, t=(Qien / 2-Jmax) / Bo) (Eq. 2) The systems and methods described herein preferably rotate the output frequency to match that of the input frequency, at a speed high enough to prevent the destabilizer buffer from overflowing / underflowing, and do so at a speed that is as close as possible to the 75mHz / S limit, although if the buffer size is limited, the actual frequency rotation speed may have to exceed this limit. 7QQQnn / C7n7 / R / VI As mentioned previously, VEQs typically retrieve the PCR clock from the input sequences, apply the required rotation to correct any frequency offset between that clock and the VEQ's local 27MHz clock, and reseal the VEQ's PCR output with this corrected clock. An alternative to resealing PCRs is to apply a cumulative offset to each PCR to compensate for the frequency offset. When this cumulative PCR offset exceeds the transmission time of a single Transport Sequence Packet (TSP), a TSP can be added to or removed from the output MPTS sequence, and the PCR offset value can be reset to zero at this transmission time. PCR markers by TSP 188*8*27*10' QAM channel bit rate Equation 3. The applied frequency offset can be varied over time until the input and output MPTS bit rates are equal, i.e., synchronized. This initial rate of change of the PCR offset is proportional to the frequency rotation observed in the output sequence. By avoiding the need for an RPD / RMD to retrieve and reseal the MPTS PCR clocks, a significant memory and computational overhead is beneficially eliminated. The applied frequency rotation rate depends on an estimate of the ppm frequency offset. As shown previously, the frequency offset is directly proportional to the rate of change of the destabilizing buffer occupancy, i.e., Eq. 1. Therefore, after a brief adjustment period during which the high-frequency network fluctuation can be averaged, the rate of change of the fluctuating buffer occupancy can be calculated, providing an approximation of the actual ppm frequency offset. According to the preferred systems and methods described herein, this frequency offset can be reduced or eliminated over time in a manner that does not result in buffer overshoot or undershoot.More specifically, the preferred modes as described herein employ adaptive frequency rotation speed adjustment, which means varying the frequency rotation over time based on a measured state of the destabilization buffer. In some modes, the measured state of the destabilization buffer may indicate a current frequency offset, and this may be the basis for varying the rotation over time. Alternatively or additionally, the measured state of the destabilization buffer may be based on the remaining available buffer occupancy. With reference to Figure 4, a first embodiment may comprise a method 150 that, in step 152, determines an initial, or current, frequency offset between the input data entering the destabilization buffer 116 and the output data leaving the destabilization buffer 116. The frequency offset may be determined, for example, by measuring the fullness state of the destabilization buffer 116 over an interval and applying a low-pass filter during that interval to determine a deviation in the depth of the destabilization buffer. In a preferred embodiment, the deviation may be used to determine a current frequency offset value measured in ppm. In step 154, the initial, or current, frequency offset is used to select from a plurality of predetermined scalar rotation speed values. As an example, a predetermined rotation speed can be associated with each of a plurality of frequency offset intervals; for instance, one rotation speed can be applied if the measured frequency offset is less than or equal to 10 ppm, another rotation speed can be applied if the measured frequency offset is greater than 10 ppm but less than or equal to 35 ppm, and a third rotation speed can be selected if the measured frequency offset is greater than 35 ppm. Those skilled in the art will appreciate that other rotation speed values ​​can be used for each of these intervals, and a greater number of intervals can be used in various configurations.Preferably, the preselected rotation speeds for each of the intervals are pre-calculated to ensure that the frequency rotation speed is high enough so that the frequency offset is corrected before a buffer overshoot / undershoot event occurs. 7QQQnn / C7n7 / R / YI In step 156 the selected frequency rotation speed is applied, and after a period of time has elapsed, the procedure returns to step 152 so that another measurement of the frequency offset can be taken, which will have been reduced relative to the previous iteration, and the method can then continue until the frequency offset has been eliminated. In particular, the rate of change of the destabilization buffer depth will decrease as the frequency offset decreases, so the initial frequency rotation speed will have a more drastic effect on buffer occupancy. As the frequency offset approaches zero, the chosen rotation speed will have less effect. Therefore, periodic frequency rotation updates can be performed at a relatively low rate because frequency offset correction is a relatively slow process (i.e., possibly >60 minutes for large ppm frequency offsets). Instead of simply adjusting the rotation speed based on a frequency offset, as measured by changes in the destabilization buffer depth 116, the alternative implementation can adjust a rotation speed based on both the measured frequency offset and the measured remaining working depth of the destabilization buffer. In some specific modalities, a calculation can be used to determine a stepwise change in rotation speed as a function of a measured frequency offset and a measured state of a buffer's working depth. For example, the rotation speed (dFldT) can be based on a measured fractional frequency offset such as flows: dF , dF ¡ — = + / - (D · F) where D is the frequency deviation rate as a fraction,dt / pr dFr / y- = J + / ~D dt In (F) = + / -Dt + const Ft=θ+Z-Dt +const Ft= Fo e+ADt, where Fo = econst En (Ft / Fo) = + / -Dt + / -D = En (Ft / Fo) / ((Qien / 2 - Jmax) / Bo)) (substituent of Eq. 2) + / -D = (En (Ft / Fo). . Bo) / (Qien / 2 - Jmax) Therefore, a selected frequency rotation speed can be represented by the equation || = ((En (Ft / Fo) . . Bo. Fo) / (Qien / 2 - Jmax)) ' S (Eq. 4) where S is a linear approximation for the phase-locked loop (PLL) of the low-pass filter (e.g., S = 0.5). The value (Qien / 2 - Jmax) represents the available working depth of the buffer, where Qien / 2 represents the averaged distance (jitter removed) that the buffer is from being completely full or completely empty, and Jmax represents the maximum jitter experienced. Therefore, applying this equation can produce a desired initial / updated rotation speed as a function of a measured frequency offset and a measured available working depth of the buffer. 7QQQnn / C7n7 / R / VI With reference to Figure 5, for example, another way to apply an adaptive frequency rotation speed to a destabilization buffer can use method 160 in which, in step 162, a buffer state is measured over a time interval sufficient to average the network fluctuation in order to determine the buffer deviation due to frequency offset. In step 164, based on the measurements taken in step 162, values ​​are calculated for a measured frequency offset between the buffer's input and output data, as well as for a buffer working depth, which in some modes will reflect a maximum amount of jitter. In step 166, an initial / updated rotation speed is determined. In some modes, the rotation speed can be determined based on Equation 4 above. In step 168, the determined rotation speed is applied. After a period of time, the procedure returns to step 162 and continues until the frequency offset has been eliminated. Figures 6A and 6B show the results of the systems and procedures described herein. These figures show that the described systems and methods quickly adjust to prevent the buffer from being underpassed / overpassed, while also eliminating frequency compensation through a jitter buffer over time. Once the adaptive frequency rotation process described above is complete, the output frequency will match the input frequency. This means that the input and output bit rates will also match, thus eliminating the deviation in the depth of destabilizing buffer 116. However, destabilizing buffer 116 will be shifted from its center point, whereas for optimal destabilizing performance, the destabilizing buffer should be kept at 50% fullness. To recenter the destabilization buffer 116, the RPD / RMD 104 can utilize the permissible tolerance in PCR accuracy for accumulating DOCSIS markers, facilitating the addition / removal of TSPs to / from the output sequence. ISO / IEC 13818-1 defines this PCR tolerance as “the maximum permissible inaccuracy of received PCRs. This inaccuracy may be due to imprecision in PCR values ​​or modification of PCR during remultiplexing. It does not include errors in packet arrival time due to network fluctuations or other causes. The PCR tolerance is + / -500 ns.” Applying a deliberate error of + / -500 ms to successive PCRs, per PID, is equivalent to adjusting the PCR value by + / -13.5 marks, i.e., (500 x 10⁹ x 27 x 10⁶). Once this cumulative value exceeds the PCR marks per TSP value (see Eq. 3), a packet can be added / removed from the output sequence, and the PCR adjustment value will be incremented / decremented by the PCR marks per TSP value. Repeating this process will allow the destabilization buffers to gradually recenter without contravening the ISO 13818-1 specification. The preceding description outlined systems and methods by which a variant of an RPD / RMD 204 operating in asynchronous mode within a DAA architecture could apply PCR compensation to incoming video instead of re-sealing the video data with time values ​​from its own clock. This is a less computationally intensive means of maintaining synchronized video data presentation. Those skilled in the art will appreciate, however, that all the above techniques can also be implemented using a VEQ unit at a header end, as shown in Figure 1, for example. 7QQQnn / C7n7 / R / VI It will be appreciated that the invention is not limited to the particular embodiment described, and that variations may be made thereon without departing from the scope of the invention as defined in the appended claims, as interpreted in accordance with the principles of applicable law, including the doctrine of equivalents or any other principle that extends the enforceable scope of a claim beyond its literal scope. Unless the context indicates otherwise, a reference in a claim to the number of instances of an element, whether a reference to one instance or more than one instance, requires at least the stated number of instances of the element, but is not intended to exclude from the scope of the claim a structure or method having more instances of that element than stated.The word "comprises" or a derivative thereof, when used in a claim, is used in a non-exclusive sense that is not intended to exclude the presence of other elements or steps in a claimed structure or method.

Claims

1. A remote device that receives packetized video data from a video core via a packet-switched network, the device comprising: a clock configured to operate in asynchronous mode; a desaturation buffer that receives the video data from the packet-switched network and sends the video data to at least one module that adjusts the video data before sending the video data in a downstream direction; a processing device that applies a slew rate adjustment to the clock and the desaturation buffer, the slew rate adjustment varying over time based on a measured state of the desaturation buffer.

2. The remote device of claim 1 comprising an RPD.

3. The remote device of claim 1 comprising an RMD.

4. The remote device of claim 1 wherein the adjustment of the rotation speed is based on a frequency compensation determined by measuring a state of fullness of the destabilization buffer over time.

5. The remote device of claim 4 wherein the adjustment of the rotation speed is based on a measured current fullness state of the destabilization buffer.

6. The remote device of claim 1 wherein the at least one module applies an offset value to a PCR value in the video data received from the packet-switched network.

7. The remote device of claim 6 wherein the offset values ​​accumulate to produce a cumulative offset value, the cumulative offset value being used to selectively add and / or remove packages.

8. The remote device of claim 7 wherein the magnitude of the accumulated compensation value is reduced each time a package is selectively removed and / or added.

9. The remote device of claim 1 wherein adjusting the rotation speed eliminates a frequency offset by repeatedly measuring a destabilizing buffer fullness state over time.

10. The remote device of claim 9 wherein the destabilization buffer is recentered after the frequency compensation is removed.

11. A method for determining the timing values ​​to be applied to packetized video data received asynchronously from a video core via a packet-switched network, the method comprising: receiving video data from the packet-switched network into a deslatch buffer according to a first timebase and outputting video data from the deslatch buffer according to a second timebase and to at least one module that adds synchronization information to the video data before sending the video data in a downstream direction; applying a rotation speed adjustment to decrease a difference between the first timebase and the second timebase over an interval, the rotation speed adjustment varying with time based on a measured state of the deslatch buffer.

12. The method of claim 11 implemented in an RPD.

13. The method of claim 11 implemented in an RMD.

14. The method of claim 11 wherein the adjustment of the rotation speed is based on a frequency compensation determined by measuring a state of fullness of the destabilization buffer over time.

15. The method of claim 14 wherein the adjustment of the rotation speed is based on a measured current fullness state of the destabilization buffer.

16. The method of claim 11 wherein the at least one module applies a compensation value to a PCR value in the video data received from the packet-switched network.

17. The method of claim 16 wherein the compensation values ​​are accumulated to produce a cumulative compensation value, the cumulative compensation value being used to selectively add and / or remove packages.

18. The method of claim 17 wherein the magnitude of the accumulated compensation value is reduced each time a package is selectively removed and / or added.

19. The method of claim 11 wherein adjusting the rotation speed eliminates a frequency offset when repeatedly measuring a destabilizing buffer fullness state over time.

20. The method of claim 19 including the step of recentering the destabilization buffer after the frequency compensation is removed.

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