Reassigning a network address of a distributed unit

Abstract

Apparatuses, systems, and techniques to perform dynamic mapping between one or more Open Radio Access Network (O-RAN) radio units (RUs) and one or more O-RAN distributed units (DUs). For example, processors or computing systems to perform switching of mappings between open radio unit (O-RU) and open distributed unit (O-DU) in an open radio access network (O-RAN). In at least one embodiment, a processor including circuitry performs a program to cause reassigning of mappings between radio unit (RUs) and distributed unit (DUs) without the need of restarting or reconfiguration of RUs and / or DUs in an O-RAN network.

Description

TECHNICAL FIELD

[0001] At least one embodiment pertains to switching resources used to perform radio access network (RAN) operations. For example, processors or computing systems to perform switching of mappings between open radio unit (O-RU) and open distributed unit (O-DU) in an open radio access network (O-RAN). In at least one embodiment, a processor including circuitry performs a program to cause reassigning of mappings between radio unit (RUs) and distributed unit (DUs) without the need of restarting or reconfiguration of RUs and / or DUs in an O-RAN network.BACKGROUND

[0002] As radio traffic for wireless networks continues to increase (e.g., more users, requests for more data), there are several challenges with meeting this increase. For example, there is increased demand for spectrum resources. With more devices connecting to wireless networks (e.g., Fifth Generation “5G” networks) and consuming data at higher rates, there is a challenge of spectrum congestion, leading to slower network speeds and reduced reliability. As another example, network demand increases can cause a need for denser infrastructure, as wireless networks rely on a higher density of small cells and base stations to provide low-latency connectivity, which can be logistically challenging to implement (e.g., in urban areas). As more users are using a network, devices supporting such networks have increased workloads, which is another challenge. Accordingly, there exists a need to improve radio network technology.BRIEF DESCRIPTION OF THE DRAWINGS

[0003] FIG. 1 illustrates a computing environment for an O-RAN network, in accordance with at least one embodiment;

[0004] FIG. 2 illustrates a block diagram of a computing environment for an O-RAN network, in accordance with at least one embodiment;

[0005] FIG. 3 illustrates a process flow diagram for reassigning DU to RU, in accordance with at least one embodiment;

[0006] FIG. 4 illustrates a process flow diagram for updating a lookup table for reassigning mappings between DU and RU, in accordance with at least one embodiment;

[0007] FIG. 5 illustrates a process flow diagram for reassigning DU to RU without reconfiguration of RU and / or DU, in accordance with at least one embodiment;

[0008] FIG. 6 illustrates a lookup table for mapping between RUs to DUs, in accordance with at least one embodiment;

[0009] FIG. 7 illustrates yet another lookup table for mapping between RUs to DUs, in accordance with at least one embodiment;

[0010] FIG. 8 is an example processor, in accordance with at least one embodiment;

[0011] FIG. 9 is a block diagram illustrating a monitor and / or runtime comprising one or more libraries to provide one or more application programming interfaces (APIs), in accordance with at least one embodiment;

[0012] FIG. 10 illustrates an example data center system, according to at least one embodiment;

[0013] FIG. 11A illustrates an example of an autonomous vehicle, according to at least one embodiment;

[0014] FIG. 11B illustrates an example of camera locations and fields of view for the autonomous vehicle of FIG. 11A, according to at least one embodiment;

[0015] FIG. 11C is a block diagram illustrating an example system architecture for the autonomous vehicle of FIG. 11A, according to at least one embodiment;

[0016] FIG. 11D is a diagram illustrating a system for communication between cloud-based server(s) and the autonomous vehicle of FIG. 11A, according to at least one embodiment;

[0017] FIG. 12 is a block diagram illustrating a computer system, according to at least one embodiment;

[0018] FIG. 13 is a block diagram illustrating computer system, according to at least one embodiment;

[0019] FIG. 14 illustrates a computer system, according to at least one embodiment;

[0020] FIG. 15 illustrates a computer system, according at least one embodiment;

[0021] FIG. 16A illustrates a computer system, according to at least one embodiment;

[0022] FIG. 16B illustrates a computer system, according to at least one embodiment;

[0023] FIG. 16C illustrates a computer system, according to at least one embodiment;

[0024] FIG. 16D illustrates a computer system, according to at least one embodiment;

[0025] FIGS. 16E and 16F illustrate a shared programming model, according to at least one embodiment;

[0026] FIG. 17 illustrates exemplary integrated circuits and associated graphics processors, according to at least one embodiment;

[0027] FIGS. 18A and 18B illustrate exemplary integrated circuits and associated graphics processors, according to at least one embodiment;

[0028] FIGS. 19A and 19B illustrate additional exemplary graphics processor logic according to at least one embodiment;

[0029] FIG. 20 illustrates a computer system, according to at least one embodiment;

[0030] FIG. 21A illustrates a parallel processor, according to at least one embodiment;

[0031] FIG. 21B illustrates a partition unit, according to at least one embodiment;

[0032] FIG. 21C illustrates a processing cluster, according to at least one embodiment;

[0033] FIG. 21D illustrates a graphics multiprocessor, according to at least one embodiment;

[0034] FIG. 22 illustrates a multi-graphics processing unit (GPU) system, according to at least one embodiment;

[0035] FIG. 23 illustrates a graphics processor, according to at least one embodiment;

[0036] FIG. 24 is a block diagram illustrating a processor micro-architecture for a processor, according to at least one embodiment;

[0037] FIG. 25 illustrates at least portions of a graphics processor, according to one or more embodiments;

[0038] FIG. 26 illustrates at least portions of a graphics processor, according to one or more embodiments;

[0039] FIG. 27 illustrates at least portions of a graphics processor, according to one or more embodiments;

[0040] FIG. 28 is a block diagram of a graphics processing engine of a graphics processor in accordance with at least one embodiment;

[0041] FIG. 29 is a block diagram of at least portions of a graphics processor core, according to at least one embodiment;

[0042] FIGS. 30A and 30B illustrate thread execution logic including an array of processing elements of a graphics processor core according to at least one embodiment;

[0043] FIG. 31 illustrates a parallel processing unit (“PPU”), according to at least one embodiment;

[0044] FIG. 32 illustrates a general processing cluster (“GPC”), according to at least one embodiment;

[0045] FIG. 33 illustrates a memory partition unit of a parallel processing unit (“PPU”), according to at least one embodiment;

[0046] FIG. 34 illustrates a streaming multi-processor, according to at least one embodiment;

[0047] FIG. 35 illustrates a network for communicating data within a 5G wireless communications network, according to at least one embodiment;

[0048] FIG. 36 illustrates a network architecture for a 5G LTE wireless network, according to at least one embodiment;

[0049] FIG. 37 is a diagram illustrating some basic functionality of a mobile telecommunications network / system operating in accordance with LTE and 5G principles, according to at least one embodiment;

[0050] FIG. 38 illustrates a radio access network which may be part of a 5G network architecture, according to at least one embodiment;

[0051] FIG. 39 provides an example illustration of a 5G mobile communications system in which a plurality of different types of devices is used, according to at least one embodiment;

[0052] FIG. 40 illustrates an example high level system, according to at least one embodiment;

[0053] FIG. 41 illustrates an architecture of a system of a network, according to at least one embodiment;

[0054] FIG. 42 illustrates example components of a device, according to at least one embodiment;

[0055] FIG. 43 illustrates example interfaces of baseband circuitry, according to at least one embodiment;

[0056] FIG. 44 illustrates an example of an uplink channel, according to at least one embodiment;

[0057] FIG. 45 illustrates an architecture of a system of a network, according to at least one embodiment;

[0058] FIG. 46 illustrates a control plane protocol stack, according to at least one embodiment;

[0059] FIG. 47 illustrates a user plane protocol stack, according to at least one embodiment;

[0060] FIG. 48 illustrates components of a core network, according to at least one embodiment; and

[0061] FIG. 49 illustrates components of a system to support network function virtualization (NFV), according to at least one embodiment.DETAILED DESCRIPTION

[0062] In at least one embodiment, latency of a wireless network (e.g., O-RAN) can be increased if a RU needs to restart, reconfigure, or otherwise modify its settings based on communicating with a different DU (e.g., request, receive, and load a MAC address for the new DU). In such an embodiment, latency can also be introduced for the DU that is assigned to communication with different RU.

[0063] To reduce latency and improve performance, in at least one embodiment, apparatuses, systems, processors, computing devices, other systems can perform, use, or otherwise implement software that causes an RU to use a same DU address (e.g., MAC address) it was using to communicate with one DU with another DU (e.g., so that the RU does not need to restart when changing DUs). In at least one embodiment, software is performed by a network switch, which uses a look up table that stores a new DU address for an RU and an old (e.g., previous) media access control address (MAC) address for the old DU. In at least one embodiment, when a network switch communicates with an RU, it queries said look up table to switch a routing path of a packet from an old DU MAC address to a new DU MAC address. In at least one embodiment, by using said software to that switches routing from an old DU to a new DU, an RU does not need to restart, reconfigure, or otherwise modify its settings such that there is no latency introduced from RU changing its settings.

[0064] In at least one embodiment, hardware and software can perform operations for mapping (e.g., assigning, reassigning, indicating network addresses) between RUs and DUs in an Open Radio Access Network (O-RAN). In at least one embodiment, this mapping may need to be updated as a network condition (e.g., traffic, utilization, power budget, variation in traffic, network demand) changes to improve network performance In at least one embodiment, it can be advantageous to dynamically updating mappings between RUs and DUs without rebooting and / or reconfiguration to improve utilization of network, balancing load and reduce latency.

[0065] In at least one embodiment, systems and methods implemented in accordance with this disclosure are utilized to perform an application programming interface (API) to dynamically update mappings between one or more Open Radio Access Network (O-RAN) radio units (RUs) and one or more O-RAN distributed units (DUs) and / or otherwise perform operations described herein. In at least one embodiment, systems and methods implemented in accordance with this disclosure are utilized to perform an application programming interface (API) to cause one or more software programs indicated by an API to monitor utilization of DUs and dynamically update mappings between RUs and DUs and / or otherwise perform operations described herein.

[0066] In at least one embodiment, O-RAN allocates different signal processing operations between a radio unit (e.g., a unit for transmitting / receiving, O-RU 106 in O-RAN) and distributed unit (e.g., O-DU in O-RAN, a unit to compute intensive operations such as channel estimation) according to a 7.2 split. In at least one embodiment, a “7.2 split” is a version for how to allocate different signal processing operations to either an RU or DU. In at least one embodiment, in 7.2, an O-RU performs receiving / transmitting operations such as receiving an analog signal, sampling it, and converting an analog signal into a digital signal, whereas an O-DU performs more intensive operations such as channel estimation, demapping, and / or descrambling. In at least one embodiment, it is advantages to performing operations to dynamically update mapping between RUs and DUs to optimize bandwidth and balance load.

[0067] In at least one embodiment, one or more units in a system perform operations according to a functional split (e.g., allocation of functions between an RU and DU). In at least one embodiment, one or more APIs are to communicate split information to allocate functions between an RU and DU. In at least one embodiment, by allowing a DU and RU to handle different allocations of functions, a network can meet different criteria for different clients (e.g., autonomous vehicles will have different network performance compared to standard voice service). In at least one embodiment, it is advantages to performing operations to dynamically update mapping between RUs and DUs to optimize bandwidth and balance load.

[0068] In at least one embodiment, a processor is to perform an API to dynamically update mappings between DUs and RUs of an O-RAN. In at least one embodiment, a processor performing the API monitors DU's utilization information. In at least one embodiment, when the DU's utilization exceeds a threshold, the mapping between the DU and RU is updated to balance load. In at least one embodiment, when the DU's utilization drops below a threshold, the mapping between the DU and RU is updated to improve utilization.

[0069] In preceding and following descriptions, various techniques are described. For purposes of explanation, specific configurations and details are set forth in order to provide a thorough understanding of possible ways of implementing techniques. However, it will also be apparent that techniques described below may be practiced in different configurations without specific details. Furthermore, well-known features may be omitted or simplified to avoid obscuring techniques being described.

[0070] FIG. 1 illustrates a computing environment for an radio access network (e.g., an O-RAN network), in accordance with at least one embodiment. In at least one embodiment, computing environment 100 includes radio unit (RU) 102(a), 102(b), and 102(c), switch 104, distributed unit (DU) 106(a) and 106(b), service management and orchestration 108, a central unit (CU) 110, and core network 112. For example, 102(a), 102(b), and 102(c) can be O-RUs in an O-RAN network. In at least one embodiment, an RU includes software performed by one or more processors for the radio frequency (RF) functions in a network. In at least one embodiment, a RU includes antennas and transceivers that transmit and receive wireless signals to and from user devices (UEs) such as a mobile device, computing device, vehicle, or device including a processor. In at least one embodiment, an RU is located at the cell site or on a cell tower and handles tasks like signal amplification, modulation, and demodulation. In at least one embodiment, a DU is part of a central processing unit of a 5G network. In at least one embodiment, DU includes software performed by one or more processors to performs digital processing functions for data handling, routing, and network management. In at least one embodiment, a DU is located in a centralized data center or cloud-based infrastructure and connects to multiple RUs. In at least one embodiment, DU includes software performed by one or more processors to manage and control several RUs simultaneously to cause efficient resource allocation, signal coordination, and network optimization. In at least one embodiment, an RU and DU work in tandem to provide the high-speed, low-latency connectivity that is characteristic of 5G networks, enabling the delivery of advanced services and applications to users. In at least one embodiment, RU 102(a), 102(b), and 102(c), switch 104, distributed unit (DU) 106(a) and 106(b) are part of a O-RAN network and each unit can be re-allocated, moved, or otherwise reconfigured to provide different service to different UEs, different cells, or to different areas of a network.

[0071] In at least one embodiment, computer environment 100 includes a processor (not shown in FIG. 1) comprising one or more circuits to perform an API to cause monitoring of utilization information of one or more DUs (e.g., DU 106(a) and 106(b)). In at least one embodiment, RUs 102(a) and / or 102(b) and / or 102(c) receive / transmit signals. In at least one embodiment, switch 104 queries a translation lookup table (as shown in FIG. 6 and FIG. 7) to provide mapping between RUs 102(a) and / or 102(b) and / or 102(c) and DUs 106(a) and 106(b) to forward the signals. In at least one embodiment, DUs 106(a) and 106(b) and CU 110 process said signals. In at least one embodiment, core network 112 performs applications or operations based on those signals. In at least one embodiment, a monitor (not shown on FIG. 1) monitors utilization information of DUs 106(a) and 106(b) and reports to SMO 108 when utilization of DUs 106(a) and / or 106(b) exceeds a threshold or drops below a threshold. In at least one embodiment, SMO identifies a DU to be reassigned with the corresponding RUs 102(a) and / or 102(b) and / or 102 (c) when receives the report and communicate with switch 104 to cause switch 104 to update the translation lookup table (as shown in FIG. 6 and FIG. 7). In at least one embodiment, as signals are transmitted and received from RUs 102(a), 102(b), and / or 102(c), switch 104 queries the translation lookup table (as shown in FIG. 6 and FIG. 7) to provide updated mapping between RUs 102(a) and / or 102(b) and / or 102(c) and DUs 106(a) and 106(b) to forward the signals to the updated DU 106(a) and / or 106(b) to balance load or improve utilization. In at least one embodiment, updated DU 106(a) and / or 106(b) and CU 110 process said signals to perform requests for user device using RAN (e.g., O-RAN network) to connect to Internet. In at least one embodiment, 5G data packets include a unit of data made into a single packet that can travel in air or in an network path based on protocols. In at least one embodiment, 5G data packets include header information (e.g., protocol information to routing and processing a packet). In at least one embodiment, a packet is a data packet. In at least one embodiment, signals include data packets.

[0072] In at least one embodiment, Service Management and Orchestration (SMO) 108 includes software performed by one or more processors in an O-RAN to manage and coordinate of network services and resources. In at least one embodiment, SMO 108 performed by one or more processors controls allocation of radio and computing resources to cause increase utilization (e.g., optimal) when providing telecommunications services. In at least one embodiment, SMO 108 performed by one or more processors provides functions and services, RF configuration, spectrum allocation, and / or network slicing. In at least one embodiment, SMO 108 performed by one or more processors causes dynamic adaptation of network resources based on real-time demand and traffic conditions. In at least one embodiment, SMO 108 performed by one or more processors provides fault detection, performance monitoring, and policy enforcement.

[0073] In at least one embodiment, monitor for monitoring utilization information of DUs (not shown in FIG. 1) is located in SMO 108 or communicates with SMO 108. In at least one embodiment, monitor for monitoring utilization information of DUs (not shown in FIG. 1) is located in DUs 106(a) and / or 106(b). In at least one embodiment, monitor for monitoring utilization information of DUs (not shown in FIG. 1) is located in RUs 102(a) and / or 102(b) and / or 102(c). In at least one embodiment, monitor for monitoring utilization information of DUs (not shown in FIG. 1) is located in CU 110. In at least one embodiment, monitor for monitoring utilization information of DUs (not shown in FIG. 1) is located independently of SMO 108, DUs 106(a) and / or 106(b), RUs 102(a) and / or 102(b) and / or 102(c), and CU 110.

[0074] In at least one embodiment, DUs 106(a) and / or 106(b) are connected directly with RUs 102(a) and / or 102(b) and / or 102(c). In at least one embodiment, DUs 106(a) and / or 106(b) are connected with RUs 102(a) and / or 102(b) and / or 102(c) through switch 104. In at least one embodiment, switch 104 queries the translation lookup table every time a data packet needs forwarding between RUs 102(a) and / or 102(b) and / or 102(c) and DUs 106(a) and / or 106(b). In at least one embodiment, switch 104 queries the translation lookup table only when SMO 108 sends command for updating translation lookup table. In at least one embodiment, translation lookup table is located in switch 104. In at least one embodiment, translation lookup table is located in RUs 102(a) and / or 102(b) and / or 102(c). In at least one embodiment, translation lookup table is located in DUs 106(a) and / or 106(b). In at least one embodiment, translation lookup table is located in SMO 108. In at least one embodiment, translation lookup table is located in CU 110. In at least one embodiment, translation lookup table is located independently of SMO 108, DUs 106(a) and / or 106(b), RUs 102(a) and / or 102(b) and / or 102(c), and CU 110.

[0075] In at least one embodiment, SMO 108 sends instructions, commands, requests, or other communications to DUs 106(a) and / or 106(b) to update translation lookup table. In at least one embodiment, SMO 108 sends commands to switch 104 to update translation lookup table. In at least one embodiment, SMO 108 sends commands to RUs 102(a) and / or 102(b) and / or 102(c) to update translation lookup table. In at least one embodiment, switch 104 queries the translation lookup table when receiving a packet forwarding request. In at least one embodiment, DUs 106 (a) and / or 106(b) queries the translation lookup table when receiving a packet forwarding request. In at least one embodiment, RUs 102(a) and / or 102(b) and / or 102(c) queries the translation lookup table when receiving a packet forwarding request.

[0076] In at least one embodiment, threshold is determined based, at least in part, on an algorithm. In at least one embodiment, threshold is determined based, at least in part, on human selection. In at least one embodiment, threshold is determined based, at least in part, on using one or more neural networks. In at least one embodiment, threshold is determined based, at least in part, on using one or more artificial intelligence.

[0077] In at least one embodiment, antennas (as shown on RUs 102(a) and / or 102(b) and / or 102 (c)) receive and transmit 5G signals, e.g., including 5G data packets. In at least one embodiment, RUs 102(a) and / or 102(b) and / or 102(c) includes one or more processors to process, perform, or otherwise compute radio frequencies received or transmitted by a physical layer of a network (e.g., RAN), e.g., by antennas (as shown on RUs 102(a) and / or 102(b) and / or 102(c)). In at least one embodiment, RU 102(a) and / or 102(b) and / or 102(c) includes O-RAN RU (O-RU), which includes a logical node hosting low-physical (PHY) layer and radio frequency (RF) processing based on a lower layer functional split for processing 5G signals.

[0078] In at least one embodiment, DUs 106(a) and / or 106(b) are connected with RUs 102(a) and / or 102(b) and / or 102(c) via front haul (not shown on FIG. 1). In at least one embodiment, front haul (not shown on FIG. 1) includes fiber optic cable or other infrastructure between DUs 106(a) and / or 106(b) are connected with RUs 102(a) and / or 102(b) and / or 102(c). In at least one embodiment, front haul (not shown on FIG. 1) includes fiber optic cables and an interface performed by one or more processors to exchange, share, transmit, send, receive, or otherwise direct control, user, synchronization, and management plane data front haul interfaces. In at least one embodiment, control plane information can include real-time control between DUs 106(a) and / or 106(b) (e.g., an O-DU) and RUs 102(a) and / or 102(b) and / or 102(c) (e.g., O-RU). In at least one embodiment, user plane can include modulation information (e.g., in-phase and quadrant (IQ) sample data) transferred between DUs 106(a) and / or 106(b) (e.g., an O-DU) and RUs 102 (a) and / or 102(b) and / or 102(c) (e.g., O-RU). In at least one embodiment, management plane information can include non-real time management operations between DUs 106(a) and / or 106 (b) (e.g., an O-DU) and RUs102(a) and / or 102(b) and / or 102(c) (e.g., O-RU), and synchronization plane data can include traffic between DUs 106(a) and / or 106(b) (e.g., an O-DU) and RUs 102(a) and / or 102(b) and / or 102(c) (e.g., O-RU) to a synchronization controller, which can be a controller that uses Institute of Electrical and Electronics Engineers (IEEE)-1588 Grand Master.

[0079] In at least one embodiment, a single system on chip (SoC) or single server comprising one or more processors performs DUs 106(a) and / or 106(b) (e.g., an O-DU) and / or CU 110, wherein said SoC or single server performs O-RAN network functions. In at least one embodiment, DUs 106(a) and / or 106(b) (e.g., an O-DU) and / or CU 110 is a logical node that hosts sets of protocols, which are radio link control (RLC) protocol, medium access control (MAC) protocol, and physical interface (PHY). In at least one embodiment, C is gNB, which is a radio node that allows 5G connections between a 5G core network and 5G air interface (e.g., RUs 102(a) and / or 102(b) and / or 102(c) and its antennas on top of the RUs). In at least one embodiment, a logical node is an abstraction of hardware unit (e.g., DU or CU) that includes one or more processors to process data and data attributes, e.g., 5G signals and 5G data packets. In at least one embodiment, DUs 106(a) and / or 106(b) (e.g., an O-DU) and / or CU 110 is located on single server. In at least one embodiment, DUs 106(a) and / or 106(b) (e.g., an O-DU) and / or CU 110 is divided into two servers (e.g., in different locations) such that it can be deployed in a way to improve (e.g., optimize) network performance by locating components at desirable locations (e.g., close to optimal locations for processing, receiving, and / or transmitting).

[0080] In at least one embodiment, DUs 106(a) and / or 106(b) (e.g., an O-DU) perform network functions for an O-RAN. In at least one embodiment, DUs 106(a) and / or 106(b) (e.g., an O-DU) includes a logical node hosting radio link control (RLC), medium access control (MAC), and high-physical (PHY) layers based on a lower layer functional split. For example, DUs 106(a) and / or 106(b) (e.g., an O-DU) includes an O-DU in an O-RAN network processor 5G signals transmitted and received by an RUs 102(a) and / or 102(b) and / or 102(c). In at least one embodiment, DUs 106(a) and / or 106(b) is a disaggregated DU, e.g., DU-high and DU-low.

[0081] In at least one embodiment, a CU 110 performs 5G operations related to non-real time, higher layers such as L2 and L3. In at least one embodiment, CU 110 includes O-CU (e.g., O-RAN Central Unit), which is a logical node hosting radio resource control (RRC), service data adaptation protocol (SDAP), and packet data convergence protocol (PDCP) protocols. In at least one embodiment, CU 110 includes O-CU that includes two sub-components O-RAN Central Unit Control Plane (O-CU-CP) and O-RAN Central Unit User Plane (O-CU-UP).

[0082] In at least one embodiment, SMO 108 includes RAN intelligent controller (RIC) (not shown in FIG. 1), which is an example of a near real-time RIC. In at least one embodiment, SMO 108 includes one or more processors that perform software-defined component of an O-RAN network that is to control and optimize RAN functions (e.g., baseband functions and baseband signal processing). In at least one embodiment, SMO 108 comprises a RIC that includes both non-real-time and near-real-time components, both of which manage separate functions of RAN, e.g., to transmit, process, and receive 5G signals. In at least one embodiment, one or more processors perform a non-RT RIC to manage events and resources with a response time of one second or more. In at least one embodiment, one or more processors perform a near RT RIC to manage events and resources requiring a faster response, e.g., 10 milliseconds (ms).

[0083] In at least one embodiment, core network 112 includes one or more processors to perform applications (e.g., software for virtual reality, augmented reality, and machine learning for autonomous vehicles). For example, an end user device (not shown in FIG. 1) can use RUs 102 (a) and / or 102(b) and / or 102(c) to access a 5G network, where said end user device is running a video game that is hosted by core network 112. In at least one embodiment, core network 112 includes one or more devices that perform applications. In at least one embodiment, applications include software for virtual reality, augmented reality, drones, remote control, health care, internet of things (IoT), video games, wireless communication, machine learning for autonomous vehicles, and other applications that can be performed through a wireless network. In at least one embodiment, core network 112 includes one or more processors (e.g., CPU, GPU, FGPA, ASIC, or a combination thereof). In at least one embodiment, core network 112 is a mobile edge computing network because it is close (e.g., less than 5 miles) to end user devices of RUs 102(a) and / or 102(b) and / or 102(c) such that it performs applications related to processing tasks closer to an end user. In at least one embodiment, core network 112 includes an external application (e.g., MEC) that can subscribe to radio access network analytics information exposure (RAIE) function and / or network exposure function (NEF) to obtain radio access network and core network specific network analytics and utilize said analytics to dynamically optimize its performance.

[0084] In at least one embodiment, computing environment 100 includes service management and orchestration (SMO) 108 that includes one or more processors to perform operations to orchestrate management and automation of a RAN (e.g., O-RAN). In at least one embodiment, processors of SMO 108 use one or more APIs to orchestrate management and automation of DUs 106(a) and / or 106(b), CU 110, switch 104, and RUs 102(a) and / or 102(b) and / or 102(c).

[0085] In at least one embodiment, computing environment 100 includes a collection of one or more hardware and / or software computing resources with instructions that, when executed, perform one or more communication processes such as those described herein. In at least one embodiment, computing environment 100 is a software program executing on computer hardware, application executing on computer hardware, and / or variations thereof. In at least one embodiment, one or more processes of system 100 are performed by any suitable processing system or unit (e.g., graphics processing unit (GPU), general-purpose GPU (GPGPU), parallel processing unit (PPU), central processing unit (CPU)), a data processing unit (DPU), such as described below, and in any suitable manner, including sequential, parallel, and / or variations thereof. In at least one embodiment, system 100 uses a machine learning training framework such as PYTORCH, TENSORFLOW, BOOST, CAFFE, MICROSOFT COGNITIVE TOOLKIT / CNTK, MXNET, CHAINER, KERAS, DEEPLEARNING4J, and / or other training framework to implement and perform operations described herein to indicate an allocation of operations to process wireless signals and / or to perform said operations. In at least one embodiment, as an example, training a neural network model comprises use of a server (e.g., NVIDIA DGX servers) which further includes at least a GPU (e.g., AMD MI200, VEGAL10, VEGO20, AND ARCTURUS), an optimizer (e.g., ADAM OPTIMIZER), or discriminator architecture (e.g., discriminator architecture from face-vid2vid for training with GAN loss).

[0086] In at least one embodiment, a computing environment 100 is comprised of modules (e.g., modules 810-840, see FIG. 8) such that said a computing environment 100 performs an application programming interface (API) to dynamically update mapping between one or more Open Radio Access Network (O-RAN) radio units (RUs) and one or more O-RAN distributed units (DUs). In at least one embodiment, a module includes any combination of any type of logic (e.g., software, hardware, firmware) and / or circuitry configured to perform a function as described. In at least one embodiment, a module includes one or more circuits that form part of a larger system (e.g., an integrated circuit (IC), system-on-chip (SoC), central processing unit (CPU), graphics processing unit (GPU), data processing unit (DPU), etc.). In at least one embodiment, a controller includes any combination of any type of logic (e.g., software, hardware, firmware) and / or circuitry configured to perform a function as described. In at least one embodiment, software includes software packages, code, programming language, drivers, instructions, instruction sets, or some combination thereof. In at least one embodiment, hardware includes hardwired circuits, programmable circuits, state machine circuits, fixed function circuits, execution unit circuits, firmware with stored instructions executed by programmable circuits, or some combination thereof.

[0087] In at least one embodiment, a computing environment 100 is comprised of a logic unit, which includes firmware logic, hardware logic, or some combination thereof configured to provide any function as described further herein. In at least one embodiment, a logic unit includes circuitry that forms part of a larger computing environment 100 (e.g., IC, SoC, CPU, GPU, DPU). In at least one embodiment, a logic unit includes logic circuitry for implementation of firmware and / or hardware to perform an API to indicate and / or cause one or more software programs.

[0088] In at least one embodiment, a computing environment 100 is comprised of an engine, which includes a module and / or logic unit as described further herein. In at least one embodiment, a component includes a module and / or logic unit as described further herein. In at least one embodiment, an engine includes software logic, firmware logic, hardware logic, or some combination thereof configured to provide any function as described further herein. In at least one embodiment, a component includes software logic, firmware logic, hardware logic, or some combination thereof configured to provide any function as described further herein. In at least one embodiment, operations performed by hardware and / or firmware may alternatively be implemented via a software module, which may be embodied as a software package, code and / or instruction set. In at least one embodiment, a logic unit may also utilize a portion of software to implement its function.

[0089] In at least one embodiment, a fifth generation new radio (“5G-NR”) is a radio access technology for a mobile network. In at least one embodiment, as an example, a 5G-NR is compliant with global standards for an air interface of 5G networks. In at least one embodiment, 5G-NR systems 100, methods, and / or operations described herein may also be utilized to perform network operations in other networks, such as a wired network, 1st Generation, 2nd Generation, 3rd Generation, 4th Generation, 6th Generation networks and / or other further generations of networks (e.g., XG-NR).

[0090] In at least one embodiment, a network interface controller (NIC) is a hardware component that connects one or more computing systems to one or more computing networks. In at least one embodiment, NIC receives data to be processed by first processor or second processor (e.g., a hardware accelerator) and transmits data processed by first processor or second processor to another component in an O-RAN network (e.g., base station). In at least one embodiment, NIC receives data to be processed through one or more functions of acceleration abstraction layer interface and transmits data processed through one or more functions of acceleration abstraction layer interface. In at least one embodiment, NIC interacts with RUs 102(a) and / or 102(b) and / or 102(c) as part of providing 5G-NR service. In at least one embodiment, RUs 102(a) and / or 102 (b) and / or 102(c) is O-RAN compliant. In at least one embodiment, RUs 102(a) and / or 102(b) and / or 102(c) use varying radio frequencies. In at least one embodiment, a remote radio head (RRH), also called a remote radio unit (RRU) in wireless networks, is a remote radio transceiver that connects to an operator radio control panel via electrical or wireless interface. In at least one embodiment, a radio unit 106 includes an RRU. In at least one embodiment, RUs 102(a) and / or 102(b) and / or 102(c) include small-cell deployment where components of an L1 and L2 processing chain are implemented more centralized in DUs 106(a) and / or 106(b), connecting over 3GPP split 7.2-x / split 6 and / or other split variations described herein. As an example, a radio unit 106 is an ARTTHA5G RADIO UNIT, NEC'S MMWAVE MASSIVE MIMO AAS, SUB6 GHZ MASSIVE MIMO AAS, SUB6 GHZ RU, SUB6 GHZ RU, and / or other RUs 102(a) and / or 102(b) and / or 102(c) described herein.

[0091] In at least one embodiment, a computing environment 100 includes a processor to allocate signal processing operations between one or more units (e.g., DUs 106(a) and / or 106(b) and / or RUs 102(a) and / or 102(b) and / or 102(c)). For example RUs 102(a) and / or 102(b) and / or 102 (c) are unit to transmit and / or receive a signal, such as O-RU in O-RAN. For example, DUs 106 (a) and / or 106(b) are units to compute one or more intensive operations, such as channel estimation. For example, DUs 106(a) and / or 106(b) are O-DU in O-RAN.

[0092] For example, a computing environment 100 includes a processor comprising one or more circuits to perform an API to dynamically update mapping between one or more O-RAN RUs and one or more O-RAN DUs and / or otherwise perform operations described herein. For example, a computing environment 100 includes a processor comprising one or more circuits to perform an API to cause one or more software programs indicated by an API to monitor utilization information of the one or more O-RAN DUs and / or otherwise perform operations described herein. In at least one embodiment, a machine-readable medium having stored thereon a set of instructions, which if performed by one or more processors included in a computing environment 100, cause one or more processors to perform an API to dynamically update mapping between one or more O-RAN RUs and one or more O-RAN DUs and / or otherwise perform operations described herein. In at least one embodiment, a machine-readable medium having stored thereon a set of instructions, which if performed by one or more processors included in computing environment 100, cause one or more processors to perform an API to monitor utilization information of the one or more O-RAN DUS and / or otherwise perform operations described herein. In at least one embodiment, a computing environment 100 performs one or more operations, such as those described in connection with FIGS. 1-9. In at least one embodiment, a computing environment 100 performs one or more operations using hardware and / or software described in connection with FIGS. 10-50.

[0093] FIG. 2 illustrates a block diagram of a computing environment for an O-RAN network (e.g., including networks and system disclosed in FIG. 1), in accordance with at least one embodiment. In at least one embodiment, computing environment 200 includes radio unit (RU) 202(a), 202(b), and 202(c), switch 204, distributed unit (DU) 206(a) and 206(b), service management and orchestration 208 which includes a monitor 214, a central unit (CU) 210, and core network 212. In at least one embodiment, computer environment 200 includes a processor (not shown in FIG. 1) comprising one or more circuits to perform an API to cause monitoring of utilization information of one or more DUs (e.g., DU 206(a) and 206(b)). In at least one embodiment, RUs 202(a) and / or 202(b) and / or 202(c) receive / transmit signals. In at least one embodiment, switch 204 queries a translation lookup table (as shown in FIG. 6 and FIG. 7) to provide mapping between RUs 202(a) and / or 202(b) and / or 202(c) and DUs 206(a) and 206 (b) to forward the signals. In at least one embodiment, DUs 206(a) and 206(b) and CU 210 process said signals. In at least one embodiment, core network 212 performs applications or operations based on those signals. In at least one embodiment, a monitor 214 monitors utilization information of DUs 206(a) and 206(b) and reports to SMO 208 when utilization of DUs 206(a) and / or 206(b) exceeds a threshold or drops below a threshold. In at least one embodiment, SMO identifies a DU to be reassigned with the corresponding RUs 202(a) and / or 202(b) and / or 202 (c) when receives the report and communicate with switch 204 to cause switch 104 to update the translation lookup table (as shown in FIG. 6 and FIG. 7). In at least one embodiment, as signals are transmitted and received from RUs 202(a), 202(b), and / or 202(c), switch 204 queries the translation lookup table (as shown in FIG. 6 and FIG. 7) to provide updated mapping between RUs 202(a) and / or 202(b) and / or 202(c) and DUs 206(a) and 206(b) to forward the signals to the updated DU 206(a) and / or 206(b) to balance load or improve utilization. In at least one embodiment, updated DU 206(a) and / or 206(b) and CU 210 process said signals to perform requests for user device using RAN (e.g., O-RAN network) to connect to Internet. In at least one embodiment, 5G data packets include a unit of data made into a single packet that can travel in air or in an network path based on protocols. In at least one embodiment, 5G data packets include header information (e.g., protocol information to routing and processing a packet). In at least one embodiment, a packet is a data packet. In at least one embodiment, signals include data packets.

[0094] In at least one embodiment, monitor 214 for monitoring utilization information of DUs is located in SMO 208. In at least one embodiment, monitor 214 for monitoring utilization information of DUs is located in DUs 206(a) and / or 206(b). In at least one embodiment, monitor 214 for monitoring utilization information of DUs is located in RUs 202(a) and / or 202 (b) and / or 202(c). In at least one embodiment, monitor 214 for monitoring utilization information of DUs is located in CU 210. In at least one embodiment, monitor 214 for monitoring utilization information of DUs is located independently of SMO 208, DUs 206(a) and / or 206(b), RUs 202(a) and / or 202(b) and / or 202(c), and CU 210.

[0095] In at least one embodiment, DUs 206(a) and / or 206(b) are connected directly with RUs 202(a) and / or 202(b) and / or 202(c). In at least one embodiment, DUs 206(a) and / or 206(b) are connected with RUs 202(a) and / or 202(b) and / or 202(c) through switch 204. In at least one embodiment, switch 204 queries the translation lookup table every time a data packet needs forwarding between RUs 202(a) and / or 202(b) and / or 202(c) and DUs 206(a) and / or 206(b). In at least one embodiment, switch 204 queries the translation lookup table only when SMO 208 sends command for updating translation lookup table. In at least one embodiment, translation lookup table is located in switch 204. In at least one embodiment, translation lookup table is located in RUs 202(a) and / or 202(b) and / or 202(c). In at least one embodiment, translation lookup table is located in DUs 206(a) and / or 206(b). In at least one embodiment, translation lookup table is located in SMO 208. In at least one embodiment, translation lookup table is located in CU 210. In at least one embodiment, translation lookup table is located independently of SMO 208, DUs 206(a) and / or 206(b), RUs 202(a) and / or 202(b) and / or 202(c), and CU 210.

[0096] In at least one embodiment, SMO 208 sends commands to DUs 206(a) and / or 206(b) to update translation lookup table. In at least one embodiment, SMO 208 sends commands to switch 204 to update translation lookup table. In at least one embodiment, SMO 208 sends commands to RUs 202(a) and / or 202(b) and / or 202(c) to update translation lookup table. In at least one embodiment, switch 204 queries the translation lookup table when receiving a packet forwarding request. In at least one embodiment, DUs 206(a) and / or 206(b) queries the translation lookup table when receiving a packet forwarding request. In at least one embodiment, RUs 202(a) and / or 202(b) and / or 202(c) queries the translation lookup table when receiving a packet forwarding request.

[0097] In at least one embodiment, threshold is determined based, at least in part, on an algorithm. In at least one embodiment, threshold is determined based, at least in part, on human selection. In at least one embodiment, threshold is determined based, at least in part, on using one or more neural networks. In at least one embodiment, threshold is determined based, at least in part, on using one or more artificial intelligence.

[0098] In at least one embodiment, antennas (as shown on RUs 202(a) and / or 202(b) and / or 202 (c)) receive and transmit 5G signals, e.g., including 5G data packets. In at least one embodiment, RUs 202(a) and / or 202(b) and / or 202(c) includes one or more processors to process, perform, or otherwise compute radio frequencies received or transmitted by a physical layer of a network (e.g., RAN), e.g., by antennas (as shown on RUs 202(a) and / or 202(b) and / or 202(c)). In at least one embodiment, RU 202(a) and / or 202(b) and / or 202(c) includes O-RAN RU (O-RU), which includes a logical node hosting low-physical (PHY) layer and radio frequency (RF) processing based on a lower layer functional split for processing 5G signals.

[0099] In at least one embodiment, DUs 206(a) and / or 206(b) are connected with RUs 202(a) and / or 202(b) and / or 202(c) via front haul (not shown on FIG. 2). In at least one embodiment, front haul (not shown on FIG. 2) includes fiber optic cable or other infrastructure between DUs 206(a) and / or 106(b) are connected with RUs 202(a) and / or 202(b) and / or 202(c). In at least one embodiment, front haul (not shown on FIG. 2) includes fiber optic cables and an interface performed by one or more processors to exchange, share, transmit, send, receive, or otherwise direct control, user, synchronization, and management plane data front haul interfaces. In at least one embodiment, control plane information can include real-time control between DUs 206(a) and / or 206(b) (e.g., an O-DU) and RUs 202(a) and / or 202(b) and / or 202(c) (e.g., O-RU). In at least one embodiment, user plane can include modulation information (e.g., in-phase and quadrant (IQ) sample data) transferred between DUs 206(a) and / or 206(b) (e.g., an O-DU) and RUs 202 (a) and / or 202(b) and / or 202(c) (e.g., O-RU). In at least one embodiment, management plane information can include non-real time management operations between DUs 206(a) and / or 206 (b) (e.g., an O-DU) and RUs 202(a) and / or 202(b) and / or 202(c) (e.g., O-RU), and synchronization plane data can include traffic between DUs 206(a) and / or 206(b) (e.g., an O-DU) and RUs 202(a) and / or 202(b) and / or 202(c) (e.g., O-RU) to a synchronization controller, which can be a controller that uses Institute of Electrical and Electronics Engineers (IEEE)-1588 Grand Master.

[0100] In at least one embodiment, a single system on chip (SoC) or single server comprising one or more processors performs DUs 206(a) and / or 206(b) (e.g., an O-DU) and / or CU 210, wherein said SoC or single server performs O-RAN network functions. In at least one embodiment, DUs 206(a) and / or 206(b) (e.g., an O-DU) and / or CU 210 is a logical node that hosts sets of protocols, which are radio link control (RLC) protocol, medium access control (MAC) protocol, and physical interface (PHY). In at least one embodiment, C is gNB, which is a radio node that allows 5G connections between a 5G core network and 5G air interface (e.g., RUs 202(a) and / or 202(b) and / or 202(c) and its antennas on top of the RUs). In at least one embodiment, a logical node is an abstraction of hardware unit (e.g., DU or CU) that includes one or more processors to process data and data attributes, e.g., 5G signals and 5G data packets. In at least one embodiment, DUs 206(a) and / or 206(b) (e.g., an O-DU) and / or CU 210 is located on single server. In at least one embodiment, DUs206(a) and / or 206(b) (e.g., an O-DU) and / or CU 210 is divided into two servers (e.g., in different locations) such that it can be deployed in a way to improve (e.g., optimize) network performance by locating components at desirable locations (e.g., close to optimal locations for processing, receiving, and / or transmitting).

[0101] In at least one embodiment, DUs 206(a) and / or 206(b) (e.g., an O-DU) perform network functions for an O-RAN. In at least one embodiment, DUs 206(a) and / or 206(b) (e.g., an O-DU) includes a logical node hosting radio link control (RLC), medium access control (MAC), and high-physical (PHY) layers based on a lower layer functional split. For example, DUs 206(a) and / or 206(b) (e.g., an O-DU) includes an O-DU in an O-RAN network processor 5G signals transmitted and received by an RUs 202(a) and / or 202(b) and / or 202(c). In at least one embodiment, DUs 206(a) and / or 206(b) is a disaggregated DU, e.g., DU-high and DU-low.

[0102] In at least one embodiment, a CU 210 performs 5G operations related to non-real time, higher layers such as L2 and L3. In at least one embodiment, CU 210 includes O-CU (e.g., O-RAN Central Unit), which is a logical node hosting radio resource control (RRC), service data adaptation protocol (SDAP), and packet data convergence protocol (PDCP) protocols. In at least one embodiment, CU 110 includes O-CU that includes two sub-components O-RAN Central Unit Control Plane (O-CU-CP) and O-RAN Central Unit User Plane (O-CU-UP).

[0103] In at least one embodiment, SMO 208 includes RAN intelligent controller (RIC) (not shown in FIG. 1), which is an example of a near real-time RIC. In at least one embodiment, SMO 208 includes one or more processors that perform software-defined component of an O-RAN network that is to control and optimize RAN functions (e.g., baseband functions and baseband signal processing). In at least one embodiment, SMO 208 comprises a RIC that includes both non-real-time and near-real-time components, both of which manage separate functions of RAN, e.g., to transmit, process, and receive 5G signals. In at least one embodiment, one or more processors perform a non-RT RIC to manage events and resources with a response time of one second or more. In at least one embodiment, one or more processors perform a near RT RIC to manage events and resources requiring a faster response, e.g., 10 milliseconds (ms).

[0104] In at least one embodiment, core network 212 includes one or more processors to perform applications (e.g., software for virtual reality, augmented reality, and machine learning for autonomous vehicles). For example, an end user device (not shown in FIG. 1) can use RUs 202 (a) and / or 202(b) and / or 202(c) to access a 5G network, where said end user device is running a video game that is hosted by core network 212. In at least one embodiment, core network 212 includes one or more devices that perform applications. In at least one embodiment, applications include software for virtual reality, augmented reality, drones, remote control, health care, internet of things (IoT), video games, wireless communication, machine learning for autonomous vehicles, and other applications that can be performed through a wireless network. In at least one embodiment, core network 212 includes one or more processors (e.g., CPU, GPU, FGPA, ASIC, or a combination thereof). In at least one embodiment, core network 212 is a mobile edge computing network because it is close (e.g., less than 5 miles) to end user devices of RUs 202(a) and / or 202(b) and / or 202(c) such that it performs applications related to processing tasks closer to an end user. In at least one embodiment, core network 212 includes an external application (e.g., MEC) that can subscribe to radio access network analytics information exposure (RAIE) function and / or network exposure function (NEF) to obtain radio access network and core network specific network analytics and utilize said analytics to dynamically optimize its performance.

[0105] In at least one embodiment, computing environment 200 includes service management and orchestration (SMO) 208 that includes one or more processors to perform operations to orchestrate management and automation of a RAN (e.g., O-RAN). In at least one embodiment, processors of SMO 208 use one or more APIs to orchestrate management and automation of DUs 206(a) and / or 206(b), CU 210, switch 204, and RUs 202(a) and / or 202(b) and / or 202(c).

[0106] FIG. 3 illustrates a process flow diagram for reassigning DU to RU, in accordance with at least one embodiment. In at least one embodiment, the process in FIG. 3 is performed by a monitor (e.g., monitor 214 in FIG. 2). In at least one embodiment, one or more processors, systems, or devices shown FIGS. 1-2 can perform process 300. In at least one embodiment, a process 300 begins 302 when invoked by one or more processors, such as in response to an API. In at least one embodiment, a system (e.g., 100, 200, 800) using a process 300 performs software defined processing with different software libraries.

[0107] In at least one embodiment, some or all of process 300 (or any other processes described herein, or variations and / or combinations thereof) is performed under control of one or more computer systems configured with computer executable instructions and is implemented as code (e.g., computer executable instructions, one or more computer programs, or one or more applications) executing collectively on one or more processors, by hardware, software, or combinations thereof. In at least one embodiment, code is stored on a computer-readable storage medium in form of a computer program comprising a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, a computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some computer-readable instructions usable to perform process 300 are not stored solely using transitory signals (e.g., a propagating transient electric or electromagnetic transmission). In at least one embodiment, a non-transitory computer-readable medium does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within transceivers of transitory signals. In at least one embodiment, process 300 is performed at least in part on a computer system such as those described elsewhere in this disclosure. In at least one embodiment, logic (e.g., hardware, software, or a combination of hardware and software) performs process 300.

[0108] In at least one embodiment, a process 300 begins 302 with monitoring utilization information of DUs (e.g., DUs 106(a), and / or 106(b) and / or 106(c) in FIG. 1 and / or DUs 206 (a), and / or 206(b) and / or 206(c) in FIG. 2). In at least one embodiment, the process continues to decide if the utilization exceeds a threshold at 304. In at least one embodiment, if the utilization does not exceeds a threshold, then the process returns to 300. In at least one embodiment, if the utilization exceeds a threshold, the process continues to report the exceeding of threshold to a SMO / controller (e.g., SMO 108 in FIG. 1 and / or SMO 208 in FIG. 2) at 306. Alternatively, in at least one embodiment, if the utilization is above a threshold for lower limit, then the process returns to 300. Similarly, in at least one embodiment, at step 304, if the utilization is below a threshold of lower limit, the process continues to report to a SMO / controller (e.g., SMO 108 in FIG. 1 and / or SMO 208 in FIG. 2) at 306. In at least one embodiment, the process continues to reassigns DU (e.g., 106(a) and / or 106(b) in FIGS. 1 and / or 206(a) and / or 206(b) in FIG. 2) to RU (e.g., RUs 102(a) and / or 102(b) and / or 102(c) and / or RUs 202(a) and / or 202(b) and / or 202(c) in FIG. 2) at 308. The process ends after 308.

[0109] In at least one embodiment, threshold is determined based, at least in part, on an algorithm. In at least one embodiment, threshold is determined based, at least in part, on human selection. In at least one embodiment, threshold is determined based, at least in part, on using one or more neural networks. In at least one embodiment, threshold is determined based, at least in part, on using one or more artificial intelligence. Detailed process for step 308 is illustrated in FIG. 4 below. In at least one embodiment, a processor performs a process 300 and / or operations described herein, such as those described in connection with FIGS. 1-9. In at least one embodiment, hardware performs process 300 and / or operations described herein, such as hardware described in connection with FIGS. 10-49.

[0110] FIG. 4 illustrates a process flow diagram for updating a lookup table for reassigning mappings between DU and RU, in accordance with at least one embodiment. In at least one embodiment, the process in FIG. 4 is performed by a SMO or controller (e.g., SMO 108 in FIG. 1 and / or SMO 208 in FIG. 2). In at least one embodiment, a process 400 begins 402 when invoked by one or more processors, such as in response to an API. In at least one embodiment, a system (e.g., 100, 200, 800) using a process 400 performs software defined processing with different software libraries.

[0111] In at least one embodiment, some or all of process 400 (or any other processes described herein, or variations and / or combinations thereof) is performed under control of one or more computer systems configured with computer executable instructions and is implemented as code (e.g., computer executable instructions, one or more computer programs, or one or more applications) executing collectively on one or more processors, by hardware, software, or combinations thereof. In at least one embodiment, code is stored on a computer-readable storage medium in form of a computer program comprising a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, a computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some computer-readable instructions usable to perform process 400 are not stored solely using transitory signals (e.g., a propagating transient electric or electromagnetic transmission). In at least one embodiment, a non-transitory computer-readable medium does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within transceivers of transitory signals. In at least one embodiment, process 400 is performed at least in part on a computer system such as those described elsewhere in this disclosure. In at least one embodiment, logic (e.g., hardware, software, or a combination of hardware and software) performs process 400.

[0112] In at least one embodiment, a process 400 begins 402 with receiving an indication that utilization has exceeded a threshold. In at least one embodiment, the process continues to identify a DU for RU at 404. In at least one embodiment, an alternative DU is identified based, at least in part, on an algorithm. In at least one embodiment, an alternative DU is identified based, at least in part, on utilization information for all the DUs. In at least one embodiment, an alternative DU is identified based, at least in part, on using one or more neural networks. In at least one embodiment, an alternative DU is identified based, at least in part, on using one or more artificial intelligence. In at least one embodiment, the process continues to cause switch (e.g., switch 104 in FIG. 1 or switch 204 in FIG. 2) to update media access control (MAC) address of DU in a lookup table (e.g., translation lookup table as shown in FIG. 6 and FIG. 7) at 406. In at least one embodiment, translation lookup table is located in the switch. In at least one embodiment, translation lookup table is located in RU (e.g., RUs 102(a) and / or 102(b) and / or 102(c) in FIG. 1 and / or RUs 202 (a) and / or 202(b) and / or 202(c) in FIG. 2). In at least one embodiment, translation lookup table is located in DU (e.g., DUs 106(a) and / or 106(b) in FIG. 1 and / or DUs 206(a) and / or 206(b) in FIG. 2). In at least one embodiment, translation lookup table is located in SMO (e.g., SMO 108 in FIG. 1 or SMO 208 in FIG. 2). In at least one embodiment, translation lookup table is located in CU (e.g., CU 110 in FIG. 1 or CU 210 in FIG. 2). In at least one embodiment, translation lookup table is located independently of SMO, DU, RU, and CU.

[0113] In at least one embodiment, SMO (e.g., SMO 108 in FIG. 1 or SMO 208 in FIG. 2) sends commands to DU (e.g., DUs 106(a) and / or 106(b) in FIG. 1 and / or DUs 206(a) and / or 206(b) in FIG. 2) to update MAC address of DU in translation lookup table. In at least one embodiment, SMO (e.g., SMO 108 in FIG. 1 or SMO 208 in FIG. 2) sends commands to switch (e.g., switch 104 in FIG. 1 or switch 204 in FIG. 2) to update MAC address of DU in translation lookup table. In at least one embodiment, SMO (e.g., SMO 108 in FIG. 1 or SMO 208 in FIG. 2) sends commands to RU (e.g., RUs 102(a) and / or 102(b), and / or 202(c) in FIG. 1 and / or RUs 202(a) and / or 202(b) and / or 202(c) in FIG. 2) to update MAC address of DU in translation lookup table.

[0114] In at least one embodiment, the process continues to update the lookup table (e.g., translation lookup table as shown in FIG. 6 and FIG. 7) at 408. The process ends after 408. Detailed process for step 408 is illustrated in FIG. 5 below. In at least one embodiment, a processor performs a process 400 and / or operations described herein, such as those described in connection with FIGS. 1-9. In at least one embodiment, hardware performs process 400 and / or operations described herein, such as hardware described in connection with FIGS. 10-50.

[0115] FIG. 5 illustrates a process flow diagram for reassigning DU to RU without reconfiguration of RU and / or DU, in accordance with at least one embodiment. In at least one embodiment, the process in FIG. 5 is be performed by a switch (e.g., switch 104 in FIG. 1 and / or switch 204 in FIG. 2). In at least one embodiment, the process in FIG. 5 is performed by a DU (DUs 106(a) and / or 106(b) in FIG. 1 and / or DUs 206(a) and / or 206(b) in FIG. 2). In at least one embodiment, the process in FIG. 5 is be performed by a RU (e.g., RUs 102(a) and / or 102(b) and / or 102(c) in FIG. 1 and / or RUs 202(a) and / or 202(b) and / or 202(c) in FIG. 2). In at least one embodiment, the process in FIG. 5 is be performed by a CU (e.g., CU 110 in FIG. 1 and / or CU 210 in FIG. 2). In at least one embodiment, a process 500 begins 502 when invoked by one or more processors, such as in response to an API. In at least one embodiment, a system (e.g., 100, 200, 800) using a process 500 performs software defined processing with different software libraries.

[0116] In at least one embodiment, some or all of process 500 (or any other processes described herein, or variations and / or combinations thereof) is performed under control of one or more computer systems configured with computer executable instructions and is implemented as code (e.g., computer executable instructions, one or more computer programs, or one or more applications) executing collectively on one or more processors, by hardware, software, or combinations thereof. In at least one embodiment, code is stored on a computer-readable storage medium in form of a computer program comprising a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, a computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some computer-readable instructions usable to perform process 500 are not stored solely using transitory signals (e.g., a propagating transient electric or electromagnetic transmission). In at least one embodiment, a non-transitory computer-readable medium does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within transceivers of transitory signals. In at least one embodiment, process 500 is performed at least in part on a computer system such as those described elsewhere in this disclosure. In at least one embodiment, logic (e.g., hardware, software, or a combination of hardware and software) performs process 500.

[0117] In at least one embodiment, a process 500 begins 502 with receiving request to update DU MAC address in a lookup table. In at least one embodiment, the process continues to update DU MAC address in the lookup table at 504. In at least one embodiment, SMO (e.g., SMO 108 in FIG. 1 or SMO 208 in FIG. 2) sends commands to DU (e.g., DUs 106(a) and / or 106(b) in FIG. 1 and / or DUs 206(a) and / or 206(b) in FIG. 2) to update MAC address of DU in translation lookup table. In at least one embodiment, SMO (e.g., SMO 108 in FIG. 1 or SMO 208 in FIG. 2) sends commands to switch (e.g., switch 104 in FIG. 1 or switch 204 in FIG. 2) to update MAC address of DU in translation lookup table. In at least one embodiment, SMO (e.g., SMO 108 in FIG. 1 or SMO 208 in FIG. 2) sends commands to RU (e.g., RUs 102(a) and / or 102(b), and / or 202(c) in FIG. 1 and / or RUs 202(a) and / or 202(b) and / or 202(c) in FIG. 2) to update MAC address of DU in translation lookup table.

[0118] In at least one embodiment, the process continues to receive requests from RU (e.g., RUs 102(a) and / or 102(b), and / or 202(c) in FIG. 1 and / or RUs 202(a) and / or 202(b) and / or 202(c) in FIG. 2) to provide data packets to DU (e.g., DUs 106(a) and / or 106(b) in FIG. 1 and / or DUs 206(a) and / or 206(b) in FIG. 2) at 506. Alternatively, in at least one embodiment, the process continues to receive requests from RU (e.g., RUs 102(a) and / or 102(b), and / or 202(c) in FIG. 1 and / or RUs 202(a) and / or 202(b) and / or 202(c) in FIG. 2) to transmit data packets to DU (e.g., DUs 106(a) and / or 106(b) in FIG. 1 and / or DUs 206(a) and / or 206(b) in FIG. 2) at 506. Alternatively, in at least one embodiment, the process continues to receive requests from RU (e.g., RUs 102(a) and / or 102(b), and / or 202(c) in FIG. 1 and / or RUs 202(a) and / or 202(b) and / or 202(c) in FIG. 2) to exchange data packets to DU (e.g., DUs 106(a) and / or 106(b) in FIG. 1 and / or DUs 206(a) and / or 206(b) in FIG. 2) at 506.

[0119] In at least one embodiment, the process continues to query the lookup table (e.g., translation lookup table as shown in FIG. 6 and FIG. 7) for the DU MAC address at 508. In at least one embodiment, switch (e.g., switch 104 in FIG. 1 and switch 204 in FIG. 2) queries the translation lookup table when receiving a packet forwarding request. In at least one embodiment, DU (e.g., DUs 106(a) and / or 106(b) in FIG. 1 and / or DUs 206(a) and / or 206(b) in FIG. 2) queries the translation lookup table when receiving a packet forwarding request. In at least one embodiment, RU (e.g., RUs 102(a) and / or 102(b), and / or 202(c) in FIG. 1 and / or RUs 202(a) and / or 202(b) and / or 202(c) in FIG. 2) queries the translation lookup table when receiving a packet forwarding request. In at least one embodiment, switch (e.g., switch 104 in FIG. 1 and switch 204 in FIG. 2) queries the translation lookup table (e.g., translation lookup table as shown in FIG. 6 and FIG. 7) every time when receiving a packet forwarding request. In at least one embodiment, switch (e.g., switch 104 in FIG. 1 and switch 204 in FIG. 2) queries the translation lookup table (e.g., translation lookup table as shown in FIG. 6 and FIG. 7) only when SMO (e.g., SMO 108 in FIG. 1 or SMO 208 in FIG. 2) sends command to switch (e.g., switch 104 in FIG. 1 and switch 204 in FIG. 2) for updating translation lookup table (e.g., translation lookup table as shown in FIG. 6 and FIG. 7).

[0120] In at least one embodiment, the process continues to communicate between RU (e.g., RUs 102(a) and / or 102(b), and / or 202(c) in FIG. 1 and / or RUs 202(a) and / or 202(b) and / or 202(c) in FIG. 2) and DU (e.g., DUs 106(a) and / or 106(b) in FIG. 1 and / or DUs 206(a) and / or 206(b) in FIG. 2) based on the updated MAC address (i.e., updated DU MAC address) at 510. In at least one embodiment, the process ends after step 510.

[0121] FIG. 6 illustrates a lookup table for mapping between RU (e.g., RUs 102(a) and / or 102(b) and / or 102(c) in FIG. 1 and / or RUs 202(a) and / or 202(b) and / or 202(c) in FIG. 2) to DU (e.g., DUs 106(a) and / or 106(b) in FIG. 1 and / or DUs 206(a) and / or 206(b) in FIG. 2), in accordance with at least one embodiment. FIG. 7 illustrates yet another lookup table for mapping between RU (e.g., RUs 102(a) and / or 102(b) and / or 102(c) in FIG. 1 and / or RUs 202(a) and / or 202(b) and / or 202(c) in FIG. 2) to DU (e.g., DUs 106(a) and / or 106(b) in FIG. 1 and / or DUs 206(a) and / or 206(b) in FIG. 2), in accordance with at least one embodiment. In at least one embodiment, translation lookup table is located in the switch (e.g., switch 104 in FIG. 1 or switch 204 in FIG. 2). In at least one embodiment, translation lookup table is located in RU (e.g., RUs 102(a) and / or 102(b) and / or 102(c) in FIG. 1 and / or RUs 202(a) and / or 202(b) and / or 202(c) in FIG. 2). In at least one embodiment, translation lookup table is located in DU (e.g., DUs 106(a) and / or 106(b) in FIG. 1 and / or DUs 206(a) and / or 206(b) in FIG. 2). In at least one embodiment, translation lookup table is located in SMO (e.g., SMO 108 in FIG. 1 or SMO 208 in FIG. 2). In at least one embodiment, translation lookup table is located in CU (e.g., CU 110 in FIG. 1 or CU 210 in FIG. 2). In at least one embodiment, translation lookup table is located independently of SMO, DU, RU, and CU.

[0122] In at least one embodiment, as shown in FIG. 6 and FIG. 7, RU (e.g., RUs 102(a) and / or 102(b) and / or 102(c) in FIG. 1 and / or RUs 202(a) and / or 202(b) and / or 202(c) in FIG. 2) uses a placeholder DU MAC address to communicate with DU (e.g., DUs 106(a) and / or 106(b) in FIG. 1 and / or DUs 206(a) and / or 206(b) in FIG. 2). In at least one embodiment, as shown in FIG. 6 and FIG. 7, placeholder DU MAC address translates into actual DU MAC address for communication between RU and DU. In at least one embodiment, RU does not know the reassignment of DU when the actual DU MAC address changes because the placeholder DU MAC address that RU uses to communicate with DU does not change, thus avoiding rebooting / restarting / reconfiguration process for RU when switching to a different DU and reducing latency. In at least one embodiment, for example as shown in FIG. 6, RU3 communicates with DU using a placeholder DU MAC address 00:RU:03:DU:00:CC and the placeholder DU MAC address translates into actual DU MAC address 00:RU:00:DU:00:01. In at least one embodiment, for example as shown in FIG. 7, actual DU MAC address for RU3 updates to 00:RU:00:DU:00:02 to balance load and / or improve utilization, while RU3 still uses the same placeholder DU MAC address 00:RU:03:DU:00:CC to communicates with a new DU (with DU MAC address 00:RU:00:DU:00:02) without rebooting / restarting / reconfiguration to reduce latency.

[0123] FIG. 8 is an example processor 800, in accordance with at least one embodiment. In at least one embodiment, processor 800 performs a processes 300, 400, 500 and / or operations described herein, such as those described in connection with FIGS. 1-7, and 9. In at least one embodiment, hardware performs process 300, 400, 500 and / or operations described herein, such as hardware described in connection with FIGS. 10-50. In at least one embodiment, processor 2500 is any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variations thereof. In at least one embodiment, processor 800 comprises a monitoring module 810, controlling module 820, switching module 830, and CPU module 840. In at least one embodiment, monitoring module 810, controlling module 820, switching module 830, and / or CPU module 840 are part of processor 800 and / or one or more other processors. In at least one embodiment, monitoring module 810, controlling module 820, switching module 830, and / or CPU module 840 are distributed among multiple processors that communicate over a bus, network, by writing to shared memory, and / or any suitable communication process such as those described herein.

[0124] In at least one embodiment, as used in any implementation described herein, unless otherwise clear from context or stated explicitly to contrary, a module refers to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide functionality described herein. In at least one embodiment, software may be embodied as a software package, code and / or instruction set or instructions, and “hardware”, as used in any implementation described herein, may include, for example, singly or in any combination, hardwired circuitry, programmable circuitry, state machine circuitry, fixed function circuitry, execution unit circuitry, and / or firmware that stores instructions executed by programmable circuitry. In at least one embodiment, modules may, collectively or individually, be embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), system on-chip (SoC), and so forth. In at least one embodiment, a module performs one or more processes in connection with any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variations thereof.

[0125] In at least one embodiment, monitoring module 810 a module that performs monitoring of utilization information of DU (e.g., DUs 106(a) and / or 106(b) in FIG. 1 and / or DUs 206(a) and / or 206(b) in FIG. 2). In at least one embodiment, monitoring module 810 performs one or more processes such as those described herein by at least including or otherwise encoding instructions that cause performance of or otherwise can be utilized to perform said one or more processes (e.g., by processor 800).

[0126] In at least one embodiment, controlling module 820 is a module that performs controlling MAC address of DU (e.g., DUs 106(a) and / or 106(b) in FIG. 1 and / or DUs 206(a) and / or 206 (b) in FIG. 2). In at least one embodiment, controlling module 820 performs one or more processes such as those described herein by at least including or otherwise encoding instructions that cause performance of or otherwise can be utilized to perform said one or more processes (e.g., by processor 800).

[0127] In at least one embodiment, switching module 830 is a module that performs updating MAC address of DU (e.g., DUs 106(a) and / or 106(b) in FIG. 1 and / or DUs 206(a) and / or 206 (b) in FIG. 2). In at least one embodiment, switching module 830 performs one or more processes such as those described herein by at least including or otherwise encoding instructions that cause performance of or otherwise can be utilized to perform said one or more processes (e.g., by processor 800).

[0128] In at least one embodiment, CPU module 840 is a module that performs any of the processes described herein. In at least one embodiment, CPU module 840 performs one or more processes such as those described herein by at least including or otherwise encoding instructions that cause performance of or otherwise can be utilized to perform said one or more processes (e.g., by processor 800).

[0129] FIG. 9 is a block diagram illustrating a monitor 914 (e.g., monitor 214 in FIG. 2) and / or runtime comprising one or more libraries to provide one or more application programming interfaces (APIs), in accordance with at least one embodiment. In at least one embodiment, a software program 902 is a software module. In at least one embodiment, a software program 902 comprises one or more software modules. In at least one embodiment, a one or more software module is as further described non-exclusively in FIG. 8. In at least one embodiment, one or more APIs 910 are sets of software instructions that, if executed, cause one or more processors to perform one or more computational operations. In at least one embodiment, one or more APIs 910 are distributed or otherwise provided as a part of one or more libraries 906, runtimes 904, drivers 904, and / or any other grouping of software and / or executable code further described herein. In at least one embodiment, one or more APIs 910 perform one or more computational operations in response to invocation by software programs 902. In at least one embodiment, a software program 702 is a collection of software code, commands, instructions, or other sequences of text to instruct a computing device to perform one or more computational operations and / or invoke one or more other sets of instructions, such as APIs 910 or API functions 912, to be executed. In at least one embodiment, functionality provided by one or more APIs 910 includes software functions 912, such as those usable to accelerate one or more portions of software programs 902 using one or more parallel processing units (PPUs), such as graphics processing units (GPUs). In at least one embodiment, a software program is a monitoring program, further illustrated non-exclusively in FIGS. 3 and / or 4 and / or 5.

[0130] In at least one embodiment, APIs 910 are hardware interfaces to one or more circuits to perform one or more computational operations. In at least one embodiment, one or more software APIs 910 described herein are implemented as one or more circuits to perform one or more techniques described below in conjunction with FIGS. 1-5. In at least one embodiment, one or more software programs 902 comprise instructions that, if executed, cause one or more hardware devices and / or circuits to perform one or more techniques further described below in conjunction with FIGS. 3-5.

[0131] In at least one embodiment, software programs 902, such as user-implemented software programs, utilize one or more application programming interfaces (APIs) 910 to perform various computing operations, such as memory reservation, matrix multiplication, arithmetic operations, or any computing operation performed by parallel processing units (PPUs), such as graphics processing units (GPUs), as further described herein. In at least one embodiment, one or more APIs 910 provide a set of callable functions 912, referred to herein as APIs, API functions, and / or functions, that individually perform one or more computing operations, such as computing operations related to parallel computing. For example, in an embodiment, one or more APIs 910 provide functions 912 to cause a monitor 914 to monitor utilization information of DUs.

[0132] In at least one embodiment, one or more software programs 902 interact or otherwise communicate with one or more APIs 910 to perform one or more computing operations using one or more PPUs, such as GPUs. In at least one embodiment, one or more computing operations using one or more PPUs comprise at least one or more groups of computing operations to be accelerated by execution at least in part by said one or more PPUs. In at least one embodiment, one or more software programs 702 interact with one or more APIs 910 to facilitate parallel computing using a remote or local interface.

[0133] In at least one embodiment, an interface is software instructions that, if executed, provide access to one or more functions 912 provided by one or more APIs 910. In at least one embodiment, a software program 902 uses a local interface when a software developer compiles one or more software programs 902 in conjunction with one or more libraries 906 comprising or otherwise providing access to one or more APIs 910. In at least one embodiment, one or more software programs 902 are compiled statically in conjunction with pre-compiled libraries 906 or uncompiled source code comprising instructions to perform one or more APIs 910. In at least one embodiment, one or more software programs 902 are compiled dynamically and said one or more software programs utilize a linker to link to one or more pre-compiled libraries 906 comprising one or more APIs 910.

[0134] In at least one embodiment, a software program 902 uses a remote interface when a software developer executes a software program that utilizes or otherwise communicates with a library 906 comprising one or more APIs 910 over a network or other remote communication medium. In at least one embodiment, one or more libraries 906 comprising one or more APIs 910 are to be performed by a remote computing service, such as a computing resource services provider. In another embodiment, one or more libraries 906 comprising one or more APIs 910 are to be performed by any other computing host providing said one or more APIs 910 to one or more software programs 902.

[0135] In at least one embodiment, a processor performing or using one or more software programs 902 call, use, perform, or otherwise implement one or more APIs 910 to allocate and otherwise manage memory to be used by said software programs 902. In at least one embodiment, one or more software programs 902 utilize one or more APIs 910 to allocate and otherwise manage memory to be used by one or more portions of said software programs 902 to be accelerated using one or more PPUs, such as GPUs or any other accelerator or processor further described herein. Those software programs 902 request a neural network to perform image generation, feature information generation, and / or depth information generation using functions 912 provided, in an embodiment, by one or more APIs 910.

[0136] In at least one embodiment, an API 910 is an API to facilitate parallel computing. In at least one embodiment, an API 910 is any other API further described herein. In at least one embodiment, an API 910 is provided by a driver and / or runtime 904. In at least one embodiment, an API 910 is provided by a CUDA user-mode driver. In at least one embodiment, an API 910 is provided by a CUDA runtime. In at least one embodiment, a driver 904 is data values and software instructions that, if executed, perform or otherwise facilitate operation of one or more functions 912 of an API 910 during load and execution of one or more portions of a software program 902. In at least one embodiment, a runtime 904 is data values and software instructions that, if executed, perform or otherwise facilitate operation of one or more functions 912 of an API 910 during execution of a software program 902. In at least one embodiment, one or more software programs 902 utilize one or more APIs 910 implemented or otherwise provided by a driver and / or runtime 904 to perform combined arithmetic operations by said one or more software programs 902 during execution by one or more PPUs, such as GPUs.

[0137] In at least one embodiment, one or more software programs 902 utilize one or more APIs 910 provided by a driver and / or runtime 904 to perform combined arithmetic operations of one or more PPUs, such as GPUs. In at least one embodiment, one or more APIs 910 provide combined arithmetic operations through a driver and / or runtime 904, as described above. In at least one embodiment, one or more software programs 902 utilize one or more APIs 910 provided by a driver and / or runtime 904 to allocate or otherwise reserve one or more blocks of memory of one or more PPUs, such as GPUs. In at least one embodiment, one or more software programs 902 utilize one or more APIs 910 provided by a driver and / or runtime 904 to allocate or otherwise reserve blocks of memory. In at least one embodiment, one or more APIs 910 are to perform combined operations, as described below in conjunction with any of FIGS. 1-5.

[0138] To improve software programs 902 usability and / or optimization of one or more portions of said software programs 902 to be accelerated by one or more PPUs, such as GPUs, in an embodiment, one or more APIs 910 provide one or more API functions 912 to perform a neural network usable or used by one or more computing devices as described above and further described above in conjunction with FIGS. 1-5. In at least one embodiment, an exemplary block diagram 900 depicts a processor, comprising one or more circuits to perform one or more software programs to combine two or more application programming interfaces (APIs) into a single API. In at least one embodiment, an exemplary block diagram 900 depicts a system, comprising one or more processors to perform one or more software programs to combine two or more application programming interfaces (APIs) into a single API. In at least one embodiment, a processor uses an API to cause a neural network to select a thread selection mechanism and / or otherwise perform operations described herein. In at least one embodiment, an exemplary block diagram 900 illustrates an API to invoke a neural network to cause image generation.

[0139] In at least one embodiment, a processor uses an exemplary API to invoke one or more neural networks, where said processor comprises circuitry to use one or more first neural networks to generate one or more first images from a viewpoint outside of an object based, at least in part, on depth information generated using one or more second neural networks and feature information generated by one or more third neural networks and / or otherwise perform operations described herein. In at least one embodiment, parts, methods and / or a system described in connection with FIG. 9 are as further illustrated non-exclusively in any FIGS. 1-9.

[0140] As one skilled in the art will appreciate in light of this disclosure, certain embodiments may be capable of achieving certain advantages, including some or all of the following: improving the field of computing and job scheduler systems for allocation of jobs in clusters of nodes. Therefore, according to the above-disclosed embodiments, a priority queue can be generated using a resource quota assigned to one or more users of a cluster and resource utilization of the one or more users of the cluster.Data Center

[0141] FIG. 10 illustrates an example data center 1000, in which at least one embodiment may be used. In at least one embodiment, data center 1000 includes a data center infrastructure layer 1010, a framework layer 1020, a software layer 1030 and an application layer 1040.

[0142] In at least one embodiment, as shown in FIG. 10, data center infrastructure layer 1010 may include a resource orchestrator 1012, grouped computing resources 1014, and node computing resources (“node C.R.s”) 1016(1)-1016(N), where “N” represents any whole, positive integer. In at least one embodiment, node C.R.s 1016(1)-1016(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid state or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more node C.R.s from among node C.R.s 1016(1)-1016(N) may be a server having one or more of above-mentioned computing resources.

[0143] In at least one embodiment, grouped computing resources 1014 may include separate groupings of node C.R.s housed within one or more racks (not shown), or many racks housed in data centers at various geographical locations (also not shown). In at least one embodiment, separate groupings of node C.R.s within grouped computing resources 1014 may include grouped compute, network, memory, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node C.R.s including CPUs or processors may grouped within one or more racks to provide compute resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0144] In at least one embodiment, resource orchestrator 1012 may configure or otherwise control one or more node C.R.s 1016(1)-1016(N) and / or grouped computing resources 1014. In at least one embodiment, resource orchestrator 1012 may include a software design infrastructure (“SDI”) management entity for data center 1000. In at least one embodiment, resource orchestrator may include hardware, software, or some combination thereof.

[0145] In at least one embodiment, as shown in FIG. 10, framework layer 1020 includes a job scheduler 1032, a configuration manager 1034, a resource manager 1036 and a distributed file system 1038. In at least one embodiment, framework layer 1020 may include a framework to support software 1032 of software layer 1030 and / or one or more application(s) 1042 of application layer 1040. In at least one embodiment, software 1032 or application(s) 1042 may respectively include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud and Microsoft Azure. In at least one embodiment, framework layer 1020 may be, but is not limited to, a type of free and open-source software web application framework such as Apache Spark™ (hereinafter “Spark”) that may utilize distributed file system 1038 for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler 1032 may include a Spark driver to facilitate scheduling of workloads supported by various layers of data center 1000. In at least one embodiment, configuration manager 1034 may be capable of configuring different layers such as software layer 1030 and framework layer 1020 including Spark and distributed file system 1038 for supporting large-scale data processing. In at least one embodiment, resource manager 1036 may be capable of managing clustered or grouped computing resources mapped to or allocated for support of distributed file system 1038 and job scheduler 1032. In at least one embodiment, clustered or grouped computing resources may include grouped computing resource 1014 at data center infrastructure layer 1010. In at least one embodiment, resource manager 1036 may coordinate with resource orchestrator 1012 to manage these mapped or allocated computing resources.

[0146] In at least one embodiment, software 1032 included in software layer 1030 may include software used by at least portions of node C.R.s 1016(1)-1016(N), grouped computing resources 1014, and / or distributed file system 1038 of framework layer 1020. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web page search software, e-mail virus scan software, database software, and streaming video content software.

[0147] In at least one embodiment, application(s) 1042 included in application layer 1040 may include one or more types of applications used by at least portions of node C.R.s 1016(1)-1016 (N), grouped computing resources 1014, and / or distributed file system 1038 of framework layer 1020. In at least one embodiment, one or more types of applications may include, but are not limited to, any number of a genomics application, a cognitive compute, and a machine learning application, including training or inferencing software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.) or other machine learning applications used in conjunction with one or more embodiments.

[0148] In at least one embodiment, any of configuration manager 1034, resource manager 1036, and resource orchestrator 1012 may implement any number and type of self-modifying actions based on any amount and type of data acquired in any technically feasible fashion. In at least one embodiment, self-modifying actions may relieve a data center operator of data center 1000 from making possibly bad configuration decisions and possibly avoiding underutilized and / or poor performing portions of a data center.

[0149] In at least one embodiment, data center 1000 may include tools, services, software, or other resources to train one or more machine learning models or predict or infer information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture using software and computing resources described above with respect to data center 1000. In at least one embodiment, trained machine learning models corresponding to one or more neural networks may be used to infer or predict information using resources described above with respect to data center 1000 by using weight parameters calculated through one or more training techniques described herein.

[0150] In at least one embodiment, data center 1000 may use CPUs, application-specific integrated circuits (ASICs), GPUs, FPGAs, or other hardware to perform training and / or inferencing using above-described resources. Moreover, one or more software and / or hardware resources described above may be configured as a service to allow users to train or performing inferencing of information, such as image recognition, speech recognition, or other artificial intelligence services.

[0151] In at least one embodiment, data center 1000 is included in computer environment 100 from FIG. 1 and includes a processor (e.g., processor 800) comprising one or more circuits to perform an API to perform one or more processes 300-500. In at least one embodiment, data center 1000 performs one or more processes 300-500 as shown in FIGS. 3-5. In at least one embodiment, data center 1000 includes one or more components disclosed in FIGS. 1-9 to perform its operations.

[0152] FIG. 11A illustrates an example of an autonomous vehicle 1100, according to at least one embodiment. In at least one embodiment, autonomous vehicle 1100 (alternatively referred to herein as “vehicle 1100”) may be, without limitation, a passenger vehicle, such as a car, a truck, a bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, vehicle 1100 may be a semi-tractor-trailer truck used for hauling cargo. In at least one embodiment, vehicle 1100 may be an airplane, robotic vehicle, or other kind of vehicle.

[0153] Autonomous vehicles may be described in terms of automation levels, defined by National Highway Traffic Safety Administration (“NHTSA”), a division of US Department of Transportation, and Society of Automotive Engineers (“SAE”) “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, published on Jun. 15, 2018, Standard No. J3016-201609, published on Sep. 30, 2016, and previous and future versions of this standard). In one or more embodiments, vehicle 1100 may be capable of functionality in accordance with one or more of level 1-level 5 of autonomous driving levels. For example, in at least one embodiment, vehicle 1100 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on embodiment.

[0154] In at least one embodiment, vehicle 1100 may include, without limitation, components such as a chassis, a vehicle body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of a vehicle. In at least one embodiment, vehicle 1100 may include, without limitation, a propulsion system 1150, such as an internal combustion engine, hybrid electric power plant, an all-electric engine, and / or another propulsion system type. In at least one embodiment, propulsion system 1150 may be connected to a drive train of vehicle 1100, which may include, without limitation, a transmission, to enable propulsion of vehicle 1100. In at least one embodiment, propulsion system 1150 may be controlled in response to receiving signals from a throttle / accelerator(s) 1152.

[0155] In at least one embodiment, a steering system 1154, which may include, without limitation, a steering wheel, is used to steer a vehicle 1100 (e.g., along a desired path or route) when a propulsion system 1150 is operating (e.g., when vehicle is in motion). In at least one embodiment, a steering system 1154 may receive signals from steering actuator(s) 1156. In at least one embodiment, steering wheel may be optional for full automation (Level 5) functionality. In at least one embodiment, a brake sensor system 1146 may be used to operate vehicle brakes in response to receiving signals from brake actuator(s) 1148 and / or brake sensors.

[0156] In at least one embodiment, controller(s) 1136, which may include, without limitation, one or more system on chips (“SoCs”) (not shown in FIG. 11A) and / or graphics processing unit(s) (“GPU(s)”), provide signals (e.g., representative of commands) to one or more components and / or systems of vehicle 1100. For instance, in at least one embodiment, controller(s) 1136 may send signals to operate vehicle brakes via brake actuators 1148, to operate steering system 1154 via steering actuator(s) 1156, to operate propulsion system 1150 via throttle / accelerator(s) 1152. In at least one embodiment, controller(s) 1136 may include one or more onboard (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals, and output operation commands (e.g., signals representing commands) to enable autonomous driving and / or to assist a human driver in driving vehicle 1100. In at least one embodiment, controller(s) 1136 may include a first controller 1136 for autonomous driving functions, a second controller 1136 for functional safety functions, a third controller 1136 for artificial intelligence functionality (e.g., computer vision), a fourth controller 1136 for infotainment functionality, a fifth controller 1136 for redundancy in emergency conditions, and / or other controllers. In at least one embodiment, a single controller 1136 may handle two or more of above functionalities, two or more controllers 1136 may handle a single functionality, and / or any combination thereof.

[0157] In at least one embodiment, controller(s) 1136 provide signals for controlling one or more components and / or systems of vehicle 1100 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data may be received from, for example and without limitation, global navigation satellite systems (“GNSS”) sensor(s) 1158 (e.g., Global Positioning System sensor(s)), RADAR sensor(s) 1160, ultrasonic sensor(s) 1162, LIDAR sensor(s) 1164, inertial measurement unit (“IMU”) sensor(s) 1166 (e.g., accelerometer(s), gyroscope(s), magnetic compass(es), magnetometer(s), etc.), microphone(s) 1196, stereo camera(s) 1168, wide-view camera(s) 1170 (e.g., fisheye cameras), infrared camera(s) 1172, surround camera(s) 1174 (e.g., 360 degree cameras), long-range cameras (not shown in FIG. 11A), mid-range camera(s) (not shown in FIG. 11A), speed sensor(s) 1144 (e.g., for measuring speed of vehicle 1100), vibration sensor(s) 1142, steering sensor(s) 1140, brake sensor(s) (e.g., as part of brake sensor system 1146), and / or other sensor types.

[0158] In at least one embodiment, one or more of controller(s) 1136 may receive inputs (e.g., represented by input data) from an instrument cluster 1132 of vehicle 1100 and provide outputs (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1134, an audible annunciator, a loudspeaker, and / or via other components of vehicle 1100. In at least one embodiment, outputs may include information such as vehicle velocity, speed, time, map data (e.g., a High Definition map (not shown in FIG. 11A), location data (e.g., vehicle's 1100 location, such as on a map), direction, location of other vehicles (e.g., an occupancy grid), information about objects and status of objects as perceived by controller(s) 1136, etc. For example, in at least one embodiment, HMI display 1134 may display information about presence of one or more objects (e.g., a street sign, caution sign, traffic light changing, etc.), and / or information about driving maneuvers vehicle has made, is making, or will make (e.g., changing lanes now, taking exit 34B in two miles, etc.).

[0159] In at least one embodiment, vehicle 1100 further includes a network interface 1124 which may use wireless antenna(s) 1126 and / or modem(s) to communicate over one or more networks. For example, in at least one embodiment, network interface 1124 may be capable of communication over Long-Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile communication (“GSM”), IMT-CDMA Multi-Carrier (“CDMA2000”), etc. In at least one embodiment, wireless antenna(s) 1126 may also enable communication between objects in environment (e.g., vehicles, mobile devices, etc.), using local area network(s), such as Bluetooth, Bluetooth Low Energy (“LE”), Z-Wave, ZigBee, etc., and / or low power wide-area network(s) (“LPWANs”), such as LoRaWAN, SigFox, etc.

[0160] In at least one embodiment, vehicle 1100 is included in computer environment 100 from FIG. 1 and includes a processor (e.g., processor 800) comprising one or more circuits to perform an API to perform one or more processes 300-500. In at least one embodiment, vehicle 1100 performs one or more processes 300-500 as shown in FIGS. 3-5. In at least one embodiment, vehicle 1100 includes one or more components disclosed in FIGS. 1-9 to perform its operations.

[0161] FIG. 11B illustrates an example of camera locations and fields of view for autonomous vehicle 1100 of FIG. 11A, according to at least one embodiment. In at least one embodiment, cameras and respective fields of view are one example embodiment and are not intended to be limiting. For instance, in at least one embodiment, additional and / or alternative cameras may be included and / or cameras may be located at different locations on vehicle 1100.

[0162] In at least one embodiment, camera types for cameras may include, but are not limited to, digital cameras that may be adapted for use with components and / or systems of vehicle 1100. In at least one embodiment, camera(s) may operate at automotive safety integrity level (“ASIL”) B and / or at another ASIL. In at least one embodiment, camera types may be capable of any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on embodiment. In at least one embodiment, cameras may be capable of using rolling shutters, global shutters, another type of shutter, or a combination thereof. In at least one embodiment, color filter array may include a red clear clear clear (“RCCC”) color filter array, a red clear clear blue (“RCCB”) color filter array, a red blue green clear (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer sensors (“RGGB”) color filter array, a monochrome sensor color filter array, and / or another types of color filter arrays. In at least one embodiment, clear pixel cameras, such as cameras with an RCCC, an RCCB, and / or an RBGC color filter array, may be used in an effort to increase light sensitivity.

[0163] In at least one embodiment, one or more of camera(s) may be used to perform advanced driver assistance systems (“ADAS”) functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a Multi-Function Mono Camera may be installed to provide functions including lane departure warning, traffic sign assist and intelligent headlamp control. In at least one embodiment, one or more of camera(s) (e.g., all of cameras) may record and provide image data (e.g., video) simultaneously.

[0164] In at least one embodiment, one or more cameras may be mounted in a mounting assembly, such as a custom designed (three-dimensional (“3D”) printed) assembly, in order to cut out stray light and reflections from within a car (e.g., reflections from dashboard reflected in windshield mirrors) which may interfere with a camera's image data capture abilities. With reference to wing-mirror mounting assemblies, in at least one embodiment, wing-mirror assemblies may be custom 3D printed so that camera mounting plate matches shape of wing-mirror. In at least one embodiment, camera(s) may be integrated into wing-mirror. In at least one embodiment, for side-view cameras, camera(s) may also be integrated within four pillars at each corner of car.

[0165] In at least one embodiment, cameras with a field of view that include portions of environment in front of vehicle 1100 (e.g., front-facing cameras) may be used for surround view, to help identify forward facing paths and obstacles, as well as aid in, with help of one or more of controllers 1136 and / or control SoCs, providing information critical to generating an occupancy grid and / or determining preferred vehicle paths. In at least one embodiment, front-facing cameras may be used to perform many of same ADAS functions as LIDAR, including, without limitation, emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, front-facing cameras may also be used for ADAS functions and systems including, without limitation, Lane Departure Warnings (“LDW”), Autonomous Cruise Control (“ACC”), and / or other functions such as traffic sign recognition.

[0166] In at least one embodiment, a variety of cameras may be used in a front-facing configuration, including, for example, a monocular camera platform that includes a CMOS (“complementary metal oxide semiconductor”) color imager. In at least one embodiment, wide-view camera 1170 may be used to perceive objects coming into view from periphery (e.g., pedestrians, crossing traffic or bicycles). Although only one wide-view camera 1170 is illustrated in FIG. 11B, in other embodiments, there may be any number (including zero) of wide-view camera(s) 1170 on vehicle 1100. In at least one embodiment, any number of long-range camera(s) 1198 (e.g., a long-view stereo camera pair) may be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, long-range camera(s) 1198 may also be used for object detection and classification, as well as basic object tracking.

[0167] In at least one embodiment, any number of stereo camera(s) 1168 may also be included in a front-facing configuration. In at least one embodiment, one or more of stereo camera(s) 1168 may include an integrated control unit comprising a scalable processing unit, which may provide a programmable logic (“FPGA”) and a multi-core micro-processor with an integrated Controller Area Network (“CAN”) or Ethernet interface on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of environment of vehicle 1100, including a distance estimate for all points in image. In at least one embodiment, one or more of stereo camera(s) 1168 may include, without limitation, compact stereo vision sensor(s) that may include, without limitation, two camera lenses (one each on left and right) and an image processing chip that may measure distance from vehicle 1100 to target object and use generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo camera(s) 1168 may be used in addition to, or alternatively from, those described herein.

[0168] In at least one embodiment, cameras with a field of view that include portions of environment to side of vehicle 1100 (e.g., side-view cameras) may be used for surround view, providing information used to create and update occupancy grid, as well as to generate side impact collision warnings. For example, in at least one embodiment, surround camera(s) 1174 (e.g., four surround cameras 1174 as illustrated in FIG. 11B) could be positioned on vehicle 1100. In at least one embodiment, surround camera(s) 1174 may include, without limitation, any number and combination of wide-view camera(s) 1170, fisheye camera(s), 360 degree camera(s), and / or like. For instance, in at least one embodiment, four fisheye cameras may be positioned on front, rear, and sides of vehicle 1100. In at least one embodiment, vehicle 1100 may use three surround camera(s) 1174 (e.g., left, right, and rear), and may leverage one or more other camera(s) (e.g., a forward-facing camera) as a fourth surround-view camera.

[0169] In at least one embodiment, cameras with a field of view that include portions of environment to rear of vehicle 1100 (e.g., rear-view cameras) may be used for park assistance, surround view, rear collision warnings, and creating and updating occupancy grid. In at least one embodiment, a wide variety of cameras may be used including, but not limited to, cameras that are also suitable as a front-facing camera(s) (e.g., long-range cameras 1198 and / or mid-range camera(s) 1176, stereo camera(s) 1168), infrared camera(s) 1172, etc.), as described herein.

[0170] In at least one embodiment, vehicle 1100 is included in computer environment 100 from FIG. 1 and includes a processor (e.g., processor 800) comprising one or more circuits to perform an API to perform one or more processes 300-500. In at least one embodiment, vehicle 1100 performs one or more processes 300-500 as shown in FIGS. 3-5. In at least one embodiment, vehicle 1100 includes one or more components disclosed in FIGS. 1-9 to perform its operations.

[0171] FIG. 11C is a block diagram illustrating an example system architecture for autonomous vehicle 1100 of FIG. 11A, according to at least one embodiment. In at least one embodiment, each of components, features, and systems of vehicle 1100 in FIG. 11C are illustrated as being connected via a bus 1102. In at least one embodiment, bus 1102 may include, without limitation, a CAN data interface (alternatively referred to herein as a “CAN bus”). In at least one embodiment, a CAN may be a network inside vehicle 1100 used to aid in control of various features and functionality of vehicle 1100, such as actuation of brakes, acceleration, braking, steering, windshield wipers, etc. In at least one embodiment, bus 1102 may be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 1102 may be read to find steering wheel angle, ground speed, engine revolutions per minute (“RPMs”), button positions, and / or other vehicle status indicators. In at least one embodiment, bus 1102 may be a CAN bus that is ASIL B compliant.

[0172] In at least one embodiment, in addition to, or alternatively from CAN, FlexRay and / or Ethernet may be used. In at least one embodiment, there may be any number of busses 1102, which may include, without limitation, zero or more CAN busses, zero or more FlexRay busses, zero or more Ethernet busses, and / or zero or more other types of busses using a different protocol. In at least one embodiment, two or more busses 1102 may be used to perform different functions, and / or may be used for redundancy. For example, a first bus 1102 may be used for collision avoidance functionality and a second bus 1102 may be used for actuation control. In at least one embodiment, each bus 1102 may communicate with any of components of vehicle 1100, and two or more busses 1102 may communicate with same components. In at least one embodiment, each of any number of system(s) on chip(s) (“SoC(s)”) 1104, each of controller(s) 1136, and / or each computer within vehicle may have access to same input data (e.g., inputs from sensors of vehicle 1100), and may be connected to a common bus, such CAN bus.

[0173] In at least one embodiment, vehicle 1100 may include one or more controller(s) 1136, such as those described herein with respect to FIG. 11A. In at least one embodiment, controller(s) 1136 may be used for a variety of functions. In at least one embodiment, controller(s) 1136 may be coupled to any of various other components and systems of vehicle 1100, and may be used for control of vehicle 1100, artificial intelligence of vehicle 1100, infotainment for vehicle 1100, and / or like.

[0174] In at least one embodiment, vehicle 1100 may include any number of SoCs 1104. Each of SoCs 1104 may include, without limitation, central processing units (“CPU(s)”) 1106, graphics processing units (“GPU(s)”) 1108, processor(s) 1110, cache(s) 1112, accelerator(s) 1114, data store(s) 1116, and / or other components and features not illustrated. In at least one embodiment, SoC(s) 1104 may be used to control vehicle 1100 in a variety of platforms and systems. For example, in at least one embodiment, SoC(s) 1104 may be combined in a system (e.g., system of vehicle 1100) with a High Definition (“HD”) map 1122 which may obtain map refreshes and / or updates via network interface 1124 from one or more servers (not shown in FIG. 11C).

[0175] In at least one embodiment, CPU(s) 1106 may include a CPU cluster or CPU complex (alternatively referred to herein as a “CCPLEX”). In at least one embodiment, CPU(s) 1106 may include multiple cores and / or level two (“L2”) caches. For instance, in at least one embodiment, CPU(s) 1106 may include eight cores in a coherent multi-processor configuration. In at least one embodiment, CPU(s) 1106 may include four dual-core clusters where each cluster has a dedicated L2 cache (e.g., a 2 MB L2 cache). In at least one embodiment, CPU(s) 1106 (e.g., CCPLEX) may be configured to support simultaneous cluster operation enabling any combination of clusters of CPU(s) 1106 to be active at any given time.

[0176] In at least one embodiment, one or more of CPU(s) 1106 may implement power management capabilities that include, without limitation, one or more of following features: individual hardware blocks may be clock-gated automatically when idle to save dynamic power; each core clock may be gated when core is not actively executing instructions due to execution of Wait for Interrupt (“WFI”) / Wait for Event (“WFE”) instructions; each core may be independently power-gated; each core cluster may be independently clock-gated when all cores are clock-gated or power-gated; and / or each core cluster may be independently power-gated when all cores are power-gated. In at least one embodiment, CPU(s) 1106 may further implement an enhanced algorithm for managing power states, where allowed power states and expected wakeup times are specified, and hardware / microcode determines best power state to enter for core, cluster, and CCPLEX. In at least one embodiment, processing cores may support simplified power state entry sequences in software with work offloaded to microcode. In at least one embodiment, processing cores are referred to as compute units or computing units.

[0177] In at least one embodiment, GPU(s) 1108 may include an integrated GPU (alternatively referred to herein as an “iGPU”). In at least one embodiment, GPU(s) 1108 may be programmable and may be efficient for parallel workloads. In at least one embodiment, GPU(s) 1108, in at least one embodiment, may use an enhanced tensor instruction set. In on embodiment, GPU(s) 1108 may include one or more streaming microprocessors, where each streaming microprocessor may include a level one (“L1”) cache (e.g., an L1 cache with at least 96 KB storage capacity), and two or more of streaming microprocessors may share an L2 cache (e.g., an L2 cache with a 512 KB storage capacity). In at least one embodiment, GPU(s) 1108 may include at least eight streaming microprocessors. In at least one embodiment, GPU(s) 1108 may use compute application programming interface(s) (API(s)). In at least one embodiment, GPU(s) 1108 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA).

[0178] In at least one embodiment, one or more of GPU(s) 1108 may be power-optimized for best performance in automotive and embedded use cases. For example, in on embodiment, GPU(s) 1108 could be fabricated on a Fin field-effect transistor (“FinFET”). In at least one embodiment, each streaming microprocessor may incorporate a number of mixed-precision processing cores partitioned into multiple blocks. For example, and without limitation, 64 PF32 cores and 32 PF64 cores could be partitioned into four processing blocks. In at least one embodiment, each processing block could be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA TENSOR COREs for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a warp scheduler, a dispatch unit, and / or a 64 KB register file. In at least one embodiment, streaming microprocessors may include independent parallel integer and floating-point data paths to provide for efficient execution of workloads with a mix of computation and addressing calculations. In at least one embodiment, streaming microprocessors may include independent thread scheduling capability to enable finer-grain synchronization and cooperation between parallel threads. In at least one embodiment, streaming microprocessors may include a combined L1 data cache and shared memory unit in order to improve performance while simplifying programming.

[0179] In at least one embodiment, one or more of GPU(s) 1108 may include a high bandwidth memory (“HBM) and / or a 16 GB HBM2 memory subsystem to provide, in some examples, about 900 GB / second peak memory bandwidth. In at least one embodiment, in addition to, or alternatively from, HBM memory, a synchronous graphics random-access memory (“SGRAM”) may be used, such as a graphics double data rate type five synchronous random-access memory (“GDDR5”).

[0180] In at least one embodiment, GPU(s) 1108 may include unified memory technology. In at least one embodiment, address translation services (“ATS”) support may be used to allow GPU(s) 1108 to access CPU(s) 1106 page tables directly. In at least one embodiment, embodiment, when GPU(s) 1108 memory management unit (“MMU”) experiences a miss, an address translation request may be transmitted to CPU(s) 1106. In response, CPU(s) 1106 may look in its page tables for virtual-to-physical mapping for address and transmits translation back to GPU(s) 1108, in at least one embodiment. In at least one embodiment, unified memory technology may allow a single unified virtual address space for memory of both CPU(s) 1106 and GPU(s) 1108, thereby simplifying GPU(s) 1108 programming and porting of applications to GPU(s) 1108.

[0181] In at least one embodiment, GPU(s) 1108 may include any number of access counters that may keep track of frequency of access of GPU(s) 1108 to memory of other processors. In at least one embodiment, access counter(s) may help ensure that memory pages are moved to physical memory of processor that is accessing pages most frequently, thereby improving efficiency for memory ranges shared between processors.

[0182] In at least one embodiment, one or more of SoC(s) 1104 may include any number of cache(s) 1112, including those described herein. For example, in at least one embodiment, cache(s) 1112 could include a level three (“L3”) cache that is available to both CPU(s) 1106 and GPU(s) 1108 (e.g., that is connected to both CPU(s) 1106 and GPU(s) 1108). In at least one embodiment, cache(s) 1112 may include a write-back cache that may keep track of states of lines, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, L3 cache may include 4 MB or more, depending on embodiment, although smaller cache sizes may be used.

[0183] In at least one embodiment, one or more of SoC(s) 1104 may include one or more accelerator(s) 1114 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, SoC(s) 1104 may include a hardware acceleration cluster that may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4 MB of SRAM), may enable hardware acceleration cluster to accelerate neural networks and other calculations. In at least one embodiment, hardware acceleration cluster may be used to complement GPU(s) 1108 and to off-load some of tasks of GPU(s) 1108 (e.g., to free up more cycles of GPU(s) 1108 for performing other tasks). In at least one embodiment, accelerator(s) 1114 could be used for targeted workloads (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.) that are stable enough to be amenable to acceleration. In at least one embodiment, a CNN may include a region-based or regional convolutional neural networks (“RCNNs”) and Fast RCNNs (e.g., as used for object detection) or other type of CNN.

[0184] In at least one embodiment, accelerator(s) 1114 (e.g., hardware acceleration cluster) may include a deep learning accelerator(s) (“DLA). DLA(s) may include, without limitation, one or more Tensor processing units (“TPUs) that may be configured to provide an additional ten trillion operations per second for deep learning applications and inferencing. In at least one embodiment, TPUs may be accelerators configured to, and optimized for, performing image processing functions (e.g., for CNNs, RCNNs, etc.). DLA(s) may further be optimized for a specific set of neural network types and floating point operations, as well as inferencing. In at least one embodiment, design of DLA(s) may provide more performance per millimeter than a typical general-purpose GPU, and typically vastly exceeds performance of a CPU. In at least one embodiment, TPU(s) may perform several functions, including a single-instance convolution function, supporting, for example, INT8, INT16, and FP16 data types for both features and weights, as well as post-processor functions. In at least one embodiment, DLA(s) may quickly and efficiently execute neural networks, especially CNNs, on processed or unprocessed data for any of a variety of functions, including, for example and without limitation: a CNN for object identification and detection using data from camera sensors; a CNN for distance estimation using data from camera sensors; a CNN for emergency vehicle detection and identification and detection using data from microphones 1196; a CNN for facial recognition and vehicle owner identification using data from camera sensors; and / or a CNN for security and / or safety related events.

[0185] In at least one embodiment, DLA(s) may perform any function of GPU(s) 1108, and by using an inference accelerator, for example, a designer may target either DLA(s) or GPU(s) 1108 for any function. For example, in at least one embodiment, designer may focus processing of CNNs and floating point operations on DLA(s) and leave other functions to GPU(s) 1108 and / or other accelerator(s) 1114.

[0186] In at least one embodiment, accelerator(s) 1114 (e.g., hardware acceleration cluster) may include a programmable vision accelerator(s) (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, PVA(s) may be designed and configured to accelerate computer vision algorithms for advanced driver assistance system (“ADAS”) 1138, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. PVA(s) may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA(s) may include, for example and without limitation, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0187] In at least one embodiment, RISC cores may interact with image sensors (e.g., image sensors of any of cameras described herein), image signal processor(s), and / or like. In at least one embodiment, each of RISC cores may include any amount of memory. In at least one embodiment, RISC cores may use any of a number of protocols, depending on embodiment. In at least one embodiment, RISC cores may execute a real-time operating system (“RTOS”). In at least one embodiment, RISC cores may be implemented using one or more integrated circuit devices, application specific integrated circuits (“ASICs”), and / or memory devices. For example, in at least one embodiment, RISC cores could include an instruction cache and / or a tightly coupled RAM.

[0188] In at least one embodiment, DMA may enable components of PVA(s) to access system memory independently of CPU(s) 1106. In at least one embodiment, DMA may support any number of features used to provide optimization to PVA including, but not limited to, supporting multi-dimensional addressing and / or circular addressing. In at least one embodiment, DMA may support up to six or more dimensions of addressing, which may include, without limitation, block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0189] In at least one embodiment, vector processors may be programmable processors that may be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, PVA core may include a processor subsystem, DMA engine(s) (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, vector processing subsystem may operate as a primary processing engine of PVA and may include a vector processing unit (“VPU”), an instruction cache, and / or vector memory (e.g., “VMEM”). In at least one embodiment, VPU core may include a digital signal processor such as, for example, a single instruction, multiple data (“SIMD”), very long instruction word (“VLIW”) digital signal processor. In at least one embodiment, a combination of SIMD and VLIW may enhance throughput and speed.

[0190] In at least one embodiment, each of vector processors may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each of vector processors may be configured to execute independently of other vector processors. In at least one embodiment, vector processors that are included in a particular PVA may be configured to employ data parallelism. For instance, in at least one embodiment, plurality of vector processors included in a single PVA may execute same computer vision algorithm, but on different regions of an image. In at least one embodiment, vector processors included in a particular PVA may simultaneously execute different computer vision algorithms, on same image, or even execute different algorithms on sequential images or portions of an image. In at least one embodiment, among other things, any number of PVAs may be included in hardware acceleration cluster and any number of vector processors may be included in each of PVAs. In at least one embodiment, PVA(s) may include additional error correcting code (“ECC”) memory, to enhance overall system safety.

[0191] In at least one embodiment, accelerator(s) 1114 (e.g., hardware acceleration cluster) may include a computer vision network on-chip and static random-access memory (“SRAM”), for providing a high-bandwidth, low latency SRAM for accelerator(s) 1114. In at least one embodiment, on-chip memory may include at least 4 MB SRAM, consisting of, for example and without limitation, eight field-configurable memory blocks, that may be accessible by both PVA and DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, PVA and DLA may access memory via a backbone that provides PVA and DLA with high-speed access to memory. In at least one embodiment, backbone may include a computer vision network on-chip that interconnects PVA and DLA to memory (e.g., using APB).

[0192] In at least one embodiment, computer vision network on-chip may include an interface that determines, before transmission of any control signal / address / data, that both PVA and DLA provide ready and valid signals. In at least one embodiment, an interface may provide for separate phases and separate channels for transmitting control signals / addresses / data, as well as burst-type communications for continuous data transfer. In at least one embodiment, an interface may comply with International Organization for Standardization (“ISO”) 26262 or International Electrotechnical Commission (“IEC”) 61508 standards, although other standards and protocols may be used.

[0193] In at least one embodiment, one or more of SoC(s) 1104 may include a real-time ray-tracing hardware accelerator. In at least one embodiment, real-time ray-tracing hardware accelerator may be used to quickly and efficiently determine positions and extents of objects (e.g., within a world model), to generate real-time visualization simulations, for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulation, for comparison to LIDAR data for purposes of localization and / or other functions, and / or for other uses.

[0194] In at least one embodiment, accelerator(s) 1114 (e.g., hardware accelerator cluster) have a wide array of uses for autonomous driving. In at least one embodiment, PVA may be a programmable vision accelerator that may be used for key processing stages in ADAS and autonomous vehicles. In at least one embodiment, PVA's capabilities are a good match for algorithmic domains needing predictable processing, at low power and low latency. In other words, PVA performs well on semi-dense or dense regular computation, even on small data sets, which need predictable run-times with low latency and low power. In at least one embodiment, autonomous vehicles, such as vehicle 1100, PVAs are designed to run classic computer vision algorithms, as they are efficient at object detection and operating on integer math.

[0195] For example, according to at least one embodiment of technology, PVA is used to perform computer stereo vision. In at least one embodiment, semi-global matching-based algorithm may be used in some examples, although this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching on-the-fly (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA may perform computer stereo vision function on inputs from two monocular cameras.

[0196] In at least one embodiment, PVA may be used to perform dense optical flow. For example, in at least one embodiment, PVA could process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, PVA is used for time-of-flight depth processing, by processing raw time of flight data to provide processed time of flight data, for example.

[0197] In at least one embodiment, DLA may be used to run any type of network to enhance control and driving safety, including for example and without limitation, a neural network that outputs a measure of confidence for each object detection. In at least one embodiment, confidence may be represented or interpreted as a probability, or as providing a relative “weight” of each detection compared to other detections. In at least one embodiment, confidence enables a system to make further decisions regarding which detections should be considered as true positive detections rather than false positive detections. In at least one embodiment, a system may set a threshold value for confidence and consider only detections exceeding threshold value as true positive detections. In an embodiment in which an automatic emergency braking (“AEB”) system is used, false positive detections would cause vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, highly confident detections may be considered as triggers for AEB. In at least one embodiment, DLA may run a neural network for regressing confidence value. In at least one embodiment, neural network may take as its input at least some subset of parameters, such as bounding box dimensions, ground plane estimate obtained (e.g., from another subsystem), output from IMU sensor(s) 1166 that correlates with vehicle 1100 orientation, distance, 3D location estimates of object obtained from neural network and / or other sensors (e.g., LIDAR sensor(s) 1164 or RADAR sensor(s) 1160), among others.

[0198] In at least one embodiment, one or more of SoC(s) 1104 may include data store(s) 1116 (e.g., memory). In at least one embodiment, data store(s) 1116 may be on-chip memory of SoC(s) 1104, which may store neural networks to be executed on GPU(s) 1108 and / or DLA. In at least one embodiment, data store(s) 1116 may be large enough in capacity to store multiple instances of neural networks for redundancy and safety. In at least one embodiment, data store(s) 1112 may comprise L2 or L3 cache(s).

[0199] In at least one embodiment, one or more of SoC(s) 1104 may include any number of processor(s) 1110 (e.g., embedded processors). In at least one embodiment, processor(s) 1110 may include a boot and power management processor that may be a dedicated processor and subsystem to handle boot power and management functions and related security enforcement. In at least one embodiment, boot and power management processor may be a part of SoC(s) 1104 boot sequence and may provide runtime power management services. In at least one embodiment, boot power and management processor may provide clock and voltage programming, assistance in system low power state transitions, management of SoC(s) 1104 thermals and temperature sensors, and / or management of SoC(s) 1104 power states. In at least one embodiment, each temperature sensor may be implemented as a ring-oscillator whose output frequency is proportional to temperature, and SoC(s) 1104 may use ring-oscillators to detect temperatures of CPU(s) 1106, GPU(s) 1108, and / or accelerator(s) 1114. In at least one embodiment, if temperatures are determined to exceed a threshold, then boot and power management processor may enter a temperature fault routine and put SoC(s) 1104 into a lower power state and / or put vehicle 1100 into a chauffeur to safe stop mode (e.g., bring vehicle 1100 to a safe stop).

[0200] In at least one embodiment, processor(s) 1110 may further include a set of embedded processors that may serve as an audio processing engine. In at least one embodiment, audio processing engine may be an audio subsystem that enables full hardware support for multi-channel audio over multiple interfaces, and a broad and flexible range of audio I / O interfaces. In at least one embodiment, audio processing engine is a dedicated processor core with a digital signal processor with dedicated RAM.

[0201] In at least one embodiment, processor(s) 1110 may further include an always on processor engine that may provide necessary hardware features to support low power sensor management and wake use cases. In at least one embodiment, always on processor engine may include, without limitation, a processor core, a tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0202] In at least one embodiment, processor(s) 1110 may further include a safety cluster engine that includes, without limitation, a dedicated processor subsystem to handle safety management for automotive applications. In at least one embodiment, safety cluster engine may include, without limitation, two or more processor cores, a tightly coupled RAM, support peripherals (e.g., timers, an interrupt controller, etc.), and / or routing logic. In a safety mode, two or more cores may operate, in at least one embodiment, in a lockstep mode and function as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, processor(s) 1110 may further include a real-time camera engine that may include, without limitation, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, processor(s) 1110 may further include a high-dynamic range signal processor that may include, without limitation, an image signal processor that is a hardware engine that is part of camera processing pipeline.

[0203] In at least one embodiment, processor(s) 1110 may include a video image compositor that may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions needed by a video playback application to produce final image for player window. In at least one embodiment, video image compositor may perform lens distortion correction on wide-view camera(s) 1170, surround camera(s) 1174, and / or on in-cabin monitoring camera sensor(s). In at least one embodiment, in-cabin monitoring camera sensor(s) are preferably monitored by a neural network running on another instance of SoC 1104, configured to identify in cabin events and respond accordingly. In at least one embodiment, an in-cabin system may perform, without limitation, lip reading to activate cellular service and place a phone call, dictate emails, change vehicle's destination, activate or change vehicle's infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain functions are available to driver when vehicle is operating in an autonomous mode and are disabled otherwise.

[0204] In at least one embodiment, video image compositor may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, where motion occurs in a video, noise reduction weights spatial information appropriately, decreasing weight of information provided by adjacent frames. In at least one embodiment, where an image or portion of an image does not include motion, temporal noise reduction performed by video image compositor may use information from previous image to reduce noise in current image.

[0205] In at least one embodiment, video image compositor may also be configured to perform stereo rectification on input stereo lens frames. In at least one embodiment, video image compositor may further be used for user interface composition when operating system desktop is in use, and GPU(s) 1108 are not required to continuously render new surfaces. In at least one embodiment, when GPU(s) 1108 are powered on and active doing 3D rendering, video image compositor may be used to offload GPU(s) 1108 to improve performance and responsiveness.

[0206] In at least one embodiment, one or more of SoC(s) 1104 may further include a mobile industry processor interface (“MIPI”) camera serial interface for receiving video and input from cameras, a high-speed interface, and / or a video input block that may be used for camera and related pixel input functions. In at least one embodiment, one or more of SoC(s) 1104 may further include an input / output controller(s) that may be controlled by software and may be used for receiving I / O signals that are uncommitted to a specific role.

[0207] In at least one embodiment, one or more of SoC(s) 1104 may further include a broad range of peripheral interfaces to enable communication with peripherals, audio encoders / decoders (“codecs”), power management, and / or other devices. SoC(s) 1104 may be used to process data from cameras (e.g., connected over Gigabit Multimedia Serial Link and Ethernet), sensors (e.g., LIDAR sensor(s) 1164, RADAR sensor(s) 1160, etc. that may be connected over Ethernet), data from bus 1102 (e.g., speed of vehicle 1100, steering wheel position, etc.), data from GNSS sensor(s) 1158 (e.g., connected over Ethernet or CAN bus), etc. In at least one embodiment, one or more of SoC(s) 1104 may further include dedicated high-performance mass storage controllers that may include their own DMA engines, and that may be used to free CPU(s) 1106 from routine data management tasks.

[0208] In at least one embodiment, SoC(s) 1104 may be an end-to-end platform with a flexible architecture that spans automation levels 3-5, thereby providing a comprehensive functional safety architecture that leverages and makes efficient use of computer vision and ADAS techniques for diversity and redundancy, provides a platform for a flexible, reliable driving software stack, along with deep learning tools. In at least one embodiment, SoC(s) 1104 may be faster, more reliable, and even more energy-efficient and space-efficient than conventional systems. For example, in at least one embodiment, accelerator(s) 1114, when combined with CPU(s) 1106, GPU(s) 1108, and data store(s) 1116, may provide for a fast, efficient platform for level 3-5 autonomous vehicles.

[0209] In at least one embodiment, computer vision algorithms may be executed on CPUs, which may be configured using high-level programming language, such as C programming language, to execute a wide variety of processing algorithms across a wide variety of visual data. However, in at least one embodiment, CPUs are oftentimes unable to meet performance requirements of many computer vision applications, such as those related to execution time and power consumption, for example. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real-time, which is used in in-vehicle ADAS applications and in practical Level 3-5 autonomous vehicles.

[0210] Embodiments described herein allow for multiple neural networks to be performed simultaneously and / or sequentially, and for results to be combined together to enable Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executing on DLA or discrete GPU (e.g., GPU(s) 1120) may include text and word recognition, allowing supercomputer to read and understand traffic signs, including signs for which neural network has not been specifically trained. In at least one embodiment, DLA may further include a neural network that is able to identify, interpret, and provide semantic understanding of sign, and to pass that semantic understanding to path planning modules running on CPU Complex.

[0211] In at least one embodiment, multiple neural networks may be run simultaneously, as for Level 3, 4, or 5 driving. For example, in at least one embodiment, a warning sign consisting of “Caution: flashing lights indicate icy conditions,” along with an electric light, may be independently or collectively interpreted by several neural networks. In at least one embodiment, sign itself may be identified as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), text “flashing lights indicate icy conditions” may be interpreted by a second deployed neural network, which informs vehicle's path planning software (preferably executing on CPU Complex) that when flashing lights are detected, icy conditions exist. In at least one embodiment, flashing light may be identified by operating a third deployed neural network over multiple frames, informing vehicle's path-planning software of presence (or absence) of flashing lights. In at least one embodiment, all three neural networks may run simultaneously, such as within DLA and / or on GPU(s) 1108.

[0212] In at least one embodiment, a CNN for facial recognition and vehicle owner identification may use data from camera sensors to identify presence of an authorized driver and / or owner of vehicle 1100. In at least one embodiment, an always on sensor processing engine may be used to unlock vehicle when owner approaches driver door and turn on lights, and, in security mode, to disable vehicle when owner leaves vehicle. In this way, SoC(s) 1104 provide for security against theft and / or carjacking.

[0213] In at least one embodiment, a CNN for emergency vehicle detection and identification may use data from microphones 1196 to detect and identify emergency vehicle sirens. In at least one embodiment, SoC(s) 1104 use CNN for classifying environmental and urban sounds, as well as classifying visual data. In at least one embodiment, CNN running on DLA is trained to identify relative closing speed of emergency vehicle (e.g., by using Doppler effect). In at least one embodiment, CNN may also be trained to identify emergency vehicles specific to local area in which vehicle is operating, as identified by GNSS sensor(s) 1158. In at least one embodiment, when operating in Europe, CNN will seek to detect European sirens, and when in United States CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program may be used to execute an emergency vehicle safety routine, slowing vehicle, pulling over to side of road, parking vehicle, and / or idling vehicle, with assistance of ultrasonic sensor(s) 1162, until emergency vehicle(s) passes.

[0214] In at least one embodiment, vehicle 1100 may include CPU(s) 1118 (e.g., discrete CPU(s), or dCPU(s)), that may be coupled to SoC(s) 1104 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, CPU(s) 1118 may include an X86 processor, for example. CPU(s) 1118 may be used to perform any of a variety of functions, including arbitrating potentially inconsistent results between ADAS sensors and SoC(s) 1104, and / or monitoring status and health of controller(s) 1136 and / or an infotainment system on a chip (“infotainment SoC”) 1130, for example.

[0215] In at least one embodiment, vehicle 1100 may include GPU(s) 1120 (e.g., discrete GPU(s), or dGPU(s)), that may be coupled to SoC(s) 1104 via a high-speed interconnect (e.g., NVIDIA's NVLINK). In at least one embodiment, GPU(s)1120 may provide additional artificial intelligence functionality, such as by executing redundant and / or different neural networks and may be used to train and / or update neural networks based at least in part on input (e.g., sensor data) from sensors of vehicle 1100.

[0216] In at least one embodiment, vehicle 1100 may further include network interface 1124 which may include, without limitation, wireless antenna(s) 1126 (e.g., one or more wireless antennas 1126 for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 1124 may be used to enable wireless connectivity over Internet with cloud (e.g., with server(s) and / or other network devices), with other vehicles, and / or with computing devices (e.g., client devices of passengers). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 110 and other vehicle and / or an indirect link may be established (e.g., across networks and over Internet). In at least one embodiment, direct links may be provided using a vehicle-to-vehicle communication link. In at least one embodiment, vehicle-to-vehicle communication link may provide vehicle 1100 information about vehicles in proximity to vehicle 1100 (e.g., vehicles in front of, on side of, and / or behind vehicle 1100). In at least one embodiment, aforementioned functionality may be part of a cooperative adaptive cruise control functionality of vehicle 1100.

[0217] In at least one embodiment, network interface 1124 may include an SoC that provides modulation and demodulation functionality and enables controller(s) 1136 to communicate over wireless networks. In at least one embodiment, network interface 1124 may include a radio frequency front-end for up-conversion from baseband to radio frequency, and down conversion from radio frequency to baseband. In at least one embodiment, frequency conversions may be performed in any technically feasible fashion. For example, frequency conversions could be performed through well-known processes, and / or using super-heterodyne processes. In at least one embodiment, radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, network interface may include wireless functionality for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0218] In at least one embodiment, vehicle 1100 may further include data store(s) 1128 which may include, without limitation, off-chip (e.g., off SoC(s) 1104) storage. In at least one embodiment, data store(s) 1128 may include, without limitation, one or more storage elements including RAM, SRAM, dynamic random-access memory (“DRAM”), video random-access memory (“VRAM”), Flash, hard disks, and / or other components and / or devices that may store at least one bit of data.

[0219] In at least one embodiment, vehicle 1100 may further include GNSS sensor(s) 1158 (e.g., GPS and / or assisted GPS sensors), to assist in mapping, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensor(s) 1158 may be used, including, for example and without limitation, a GPS using a USB connector with an Ethernet to Serial (e.g., RS-232) bridge.

[0220] In at least one embodiment, vehicle 1100 may further include RADAR sensor(s) 1160. RADAR sensor(s) 1160 may be used by vehicle 1100 for long-range vehicle detection, even in darkness and / or severe weather conditions. In at least one embodiment, RADAR functional safety levels may be ASIL B. RADAR sensor(s) 1160 may use CAN and / or bus 1102 (e.g., to transmit data generated by RADAR sensor(s) 1160) for control and to access object tracking data, with access to Ethernet to access raw data in some examples. In at least one embodiment, wide variety of RADAR sensor types may be used. For example, and without limitation, RADAR sensor(s) 1160 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more of RADAR sensors(s) 1160 are Pulse Doppler RADAR sensor(s).

[0221] In at least one embodiment, RADAR sensor(s) 1160 may include different configurations, such as long-range with narrow field of view, short-range with wide field of view, short-range side coverage, etc. In at least one embodiment, long-range RADAR may be used for adaptive cruise control functionality. In at least one embodiment, long-range RADAR systems may provide a broad field of view realized by two or more independent scans, such as within a 250 m range. In at least one embodiment, RADAR sensor(s) 1160 may help in distinguishing between static and moving objects, and may be used by ADAS system 1138 for emergency brake assist and forward collision warning. In at least one embodiment, sensors 1160(s) included in a long-range RADAR system may include, without limitation, monostatic multimodal RADAR with multiple (e.g., six or more) fixed RADAR antennae and a high-speed CAN and FlexRay interface. In at least one embodiment, with six antennae, central four antennae may create a focused beam pattern, designed to record vehicle's 1100 surroundings at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, other two antennae may expand field of view, making it possible to quickly detect vehicles entering or leaving vehicle's 1100 lane.

[0222] In at least one embodiment, mid-range RADAR systems may include, as an example, a range of up to 160 m (front) or 80 m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, short-range RADAR systems may include, without limitation, any number of RADAR sensor(s) 1160 designed to be installed at both ends of rear bumper. When installed at both ends of rear bumper, in at least one embodiment, a RADAR sensor system may create two beams that constantly monitor blind spot in rear and next to vehicle. In at least one embodiment, short-range RADAR systems may be used in ADAS system 1138 for blind spot detection and / or lane change assist.

[0223] In at least one embodiment, vehicle 1100 may further include ultrasonic sensor(s) 1162. In at least one embodiment, ultrasonic sensor(s) 1162, which may be positioned at front, back, and / or sides of vehicle 1100, may be used for park assist and / or to create and update an occupancy grid. In at least one embodiment, a wide variety of ultrasonic sensor(s) 1162 may be used, and different ultrasonic sensor(s) 1162 may be used for different ranges of detection (e.g., 2.5 m, 4 m). In at least one embodiment, ultrasonic sensor(s) 1162 may operate at functional safety levels of ASIL B.

[0224] In at least one embodiment, vehicle 1100 may include LIDAR sensor(s) 1164. LIDAR sensor(s) 1164 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, LIDAR sensor(s) 1164 may be functional safety level ASIL B. In at least one embodiment, vehicle 1100 may include multiple LIDAR sensors 1164 (e.g., two, four, six, etc.) that may use Ethernet (e.g., to provide data to a Gigabit Ethernet switch).

[0225] In at least one embodiment, LIDAR sensor(s) 1164 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available LIDAR sensor(s) 1164 may have an advertised range of approximately 100 m, with an accuracy of 2 cm-3 cm, and with support for a 100 Mbps Ethernet connection, for example. In at least one embodiment, one or more non-protruding LIDAR sensors 1164 may be used. In such an embodiment, LIDAR sensor(s) 1164 may be implemented as a small device that may be embedded into front, rear, sides, and / or corners of vehicle 1100. In at least one embodiment, LIDAR sensor(s) 1164, in such an embodiment, may provide up to a 120-degree horizontal and 35-degree vertical field-of-view, with a 200 m range even for low-reflectivity objects. In at least one embodiment, front-mounted LIDAR sensor(s) 1164 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0226] In at least one embodiment, LIDAR technologies, such as 3D flash LIDAR, may also be used. 3D Flash LIDAR uses a flash of a laser as a transmission source, to illuminate surroundings of vehicle 1100 up to approximately 200 m. In at least one embodiment, a flash LIDAR unit includes, without limitation, a receptor, which records laser pulse transit time and reflected light on each pixel, which in turn corresponds to range from vehicle 1100 to objects. In at least one embodiment, flash LIDAR may allow for highly accurate and distortion-free images of surroundings to be generated with every laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one at each side of vehicle 1100. In at least one embodiment, 3D flash LIDAR systems include, without limitation, a solid-state 3D staring array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, flash LIDAR device may use a 5 nanosecond class I (eye-safe) laser pulse per frame and may capture reflected laser light in form of 3D range point clouds and co-registered intensity data.

[0227] In at least one embodiment, vehicle may further include IMU sensor(s) 1166. In at least one embodiment, IMU sensor(s) 1166 may be located at a center of rear axle of vehicle 1100, in at least one embodiment. In at least one embodiment, IMU sensor(s) 1166 may include, for example and without limitation, accelerometer(s), magnetometer(s), gyroscope(s), magnetic compass(es), and / or other sensor types. In at least one embodiment, such as in six-axis applications, IMU sensor(s) 1166 may include, without limitation, accelerometers and gyroscopes. In at least one embodiment, such as in nine-axis applications, IMU sensor(s) 1166 may include, without limitation, accelerometers, gyroscopes, and magnetometers.

[0228] In at least one embodiment, IMU sensor(s) 1166 may be implemented as a miniature, high performance GPS-Aided Inertial Navigation System (“GPS / INS”) that combines micro-electro-mechanical systems (“MEMS”) inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude. In at least one embodiment, IMU sensor(s) 1166 may enable vehicle 1100 to estimate heading without requiring input from a magnetic sensor by directly observing and correlating changes in velocity from GPS to IMU sensor(s) 1166. In at least one embodiment, IMU sensor(s) 1166 and GNSS sensor(s) 1158 may be combined in a single integrated unit.

[0229] In at least one embodiment, vehicle 1100 may include microphone(s) 1196 placed in and / or around vehicle 1100. In at least one embodiment, microphone(s) 1196 may be used for emergency vehicle detection and identification, among other things.

[0230] In at least one embodiment, vehicle 1100 may further include any number of camera types, including stereo camera(s) 1168, wide-view camera(s) 1170, infrared camera(s) 1172, surround camera(s) 1174, long-range camera(s) 1198, mid-range camera(s) 1176, and / or other camera types. In at least one embodiment, cameras may be used to capture image data around an entire periphery of vehicle 1100. In at least one embodiment, types of cameras used depends vehicle 1100. In at least one embodiment, any combination of camera types may be used to provide necessary coverage around vehicle 1100. In at least one embodiment, number of cameras may differ depending on embodiment. For example, in at least one embodiment, vehicle 1100 could include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, cameras may support, as an example and without limitation, Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet. In at least one embodiment, each of camera(s) is described with more detail previously herein with respect to FIG. 11A and FIG. 11B.

[0231] In at least one embodiment, vehicle 1100 may further include vibration sensor(s) 1142. In at least one embodiment, vibration sensor(s) 1142 may measure vibrations of components of vehicle 1100, such as axle(s). For example, in at least one embodiment, changes in vibrations may indicate a change in road surfaces. In at least one embodiment, when two or more vibration sensors 1142 are used, differences between vibrations may be used to determine friction or slippage of road surface (e.g., when difference in vibration is between a power-driven axle and a freely rotating axle).

[0232] In at least one embodiment, vehicle 1100 may include ADAS system 1138. ADAS system 1138 may include, without limitation, an SoC, in some examples. In at least one embodiment, ADAS system 1138 may include, without limitation, any number and combination of an autonomous / adaptive / automatic cruise control (“ACC”) system, a cooperative adaptive cruise control (“CACC”) system, a forward crash warning (“FCW”) system, an automatic emergency braking (“AEB”) system, a lane departure warning (“LDW)” system, a lane keep assist (“LKA”) system, a blind spot warning (“BSW”) system, a rear cross-traffic warning (“RCTW”) system, a collision warning (“CW”) system, a lane centering (“LC”) system, and / or other systems, features, and / or functionality.

[0233] In at least one embodiment, ACC system may use RADAR sensor(s) 1160, LIDAR sensor(s) 1164, and / or any number of camera(s). In at least one embodiment, ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, longitudinal ACC system monitors and controls distance to vehicle immediately ahead of vehicle 1100 and automatically adjust speed of vehicle 1100 to maintain a safe distance from vehicles ahead. In at least one embodiment, lateral ACC system performs distance keeping, and advises vehicle 1100 to change lanes when necessary. In at least one embodiment, lateral ACC is related to other ADAS applications such as LC and CW.

[0234] In at least one embodiment, CACC system uses information from other vehicles that may be received via network interface 1124 and / or wireless antenna(s) 1126 from other vehicles via a wireless link, or indirectly, over a network connection (e.g., over Internet). In at least one embodiment, direct links may be provided by a vehicle-to-vehicle (“V2V”) communication link, while indirect links may be provided by an infrastructure-to-vehicle (“I2V”) communication link. In general, V2V communication concept provides information about immediately preceding vehicles (e.g., vehicles immediately ahead of and in same lane as vehicle 1100), while I2V communication concept provides information about traffic further ahead. In at least one embodiment, CACC system may include either or both I2V and V2V information sources. In at least one embodiment, given information of vehicles ahead of vehicle 1100, CACC system may be more reliable, and it has potential to improve traffic flow smoothness and reduce congestion on a road.

[0235] In at least one embodiment, FCW system is designed to alert driver to a hazard, so that driver may take corrective action. In at least one embodiment, FCW system uses a front-facing camera and / or RADAR sensor(s) 1160, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, that is electrically coupled to driver feedback, such as a display, speaker, and / or vibrating component. In at least one embodiment, FCW system may provide a warning, such as in form of a sound, visual warning, vibration and / or a quick brake pulse.

[0236] In at least one embodiment, AEB system detects an impending forward collision with another vehicle or other object, and may automatically apply brakes if driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, AEB system may use front-facing camera(s) and / or RADAR sensor(s) 1160, coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when AEB system detects a hazard, AEB system typically first alerts driver to take corrective action to avoid collision and, if driver does not take corrective action, AEB system may automatically apply brakes in an effort to prevent, or at least mitigate, impact of predicted collision. In at least one embodiment, AEB system, may include techniques such as dynamic brake support and / or crash imminent braking.

[0237] In at least one embodiment, LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert driver when vehicle 1100 crosses lane markings. In at least one embodiment, LDW system does not activate when driver indicates an intentional lane departure, by activating a turn signal. In at least one embodiment, LDW system may use front-side facing cameras, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, that is electrically coupled to driver feedback, such as a display, speaker, and / or vibrating component. In at least one embodiment, LKA system is a variation of LDW system. LKA system provides steering input or braking to correct vehicle 1100 if vehicle 1100 starts to exit lane.

[0238] In at least one embodiment, BSW system detects and warns driver of vehicles in an automobile's blind spot. In at least one embodiment, BSW system may provide a visual, audible, and / or tactile alert to indicate that merging or changing lanes is unsafe. In at least one embodiment, BSW system may provide an additional warning when driver uses a turn signal. In at least one embodiment, BSW system may use rear-side facing camera(s) and / or RADAR sensor(s) 1160, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, that is electrically coupled to driver feedback, such as a display, speaker, and / or vibrating component.

[0239] In at least one embodiment, RCTW system may provide visual, audible, and / or tactile notification when an object is detected outside rear-camera range when vehicle 1100 is backing up. In at least one embodiment, RCTW system includes AEB system to ensure that vehicle brakes are applied to avoid a crash. In at least one embodiment, RCTW system may use one or more rear-facing RADAR sensor(s) 1160, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, that is electrically coupled to driver feedback, such as a display, speaker, and / or vibrating component.

[0240] In at least one embodiment, conventional ADAS systems may be prone to false positive results which may be annoying and distracting to a driver, but typically are not catastrophic, because conventional ADAS systems alert driver and allow driver to decide whether a safety condition truly exists and act accordingly. In at least one embodiment, vehicle 1100 itself decides, in case of conflicting results, whether to heed result from a primary computer or a secondary computer (e.g., first controller 1136 or second controller 1136). For example, in at least one embodiment, ADAS system 1138 may be a backup and / or secondary computer for providing perception information to a backup computer rationality module. In at least one embodiment, backup computer rationality monitor may run a redundant diverse software on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, outputs from ADAS system 1138 may be provided to a supervisory MCU. In at least one embodiment, if outputs from primary computer and secondary computer conflict, supervisory MCU determines how to reconcile conflict to ensure safe operation.

[0241] In at least one embodiment, primary computer may be configured to provide supervisory MCU with a confidence score, indicating primary computer's confidence in chosen result. In at least one embodiment, if confidence score exceeds a threshold, supervisory MCU may follow primary computer's direction, regardless of whether secondary computer provides a conflicting or inconsistent result. In at least one embodiment, where confidence score does not meet threshold, and where primary and secondary computer indicate different results (e.g., a conflict), supervisory MCU may arbitrate between computers to determine appropriate outcome.

[0242] In at least one embodiment, supervisory MCU may be configured to run a neural network(s) that is trained and configured to determine, based at least in part on outputs from primary computer and secondary computer, conditions under which secondary computer provides false alarms. In at least one embodiment, neural network(s) in supervisory MCU may learn when secondary computer's output may be trusted, and when it cannot. For example, in at least one embodiment, when secondary computer is a RADAR-based FCW system, a neural network(s) in supervisory MCU may learn when FCW system is identifying metallic objects that are not, in fact, hazards, such as a drainage grate or manhole cover that triggers an alarm. In at least one embodiment, when secondary computer is a camera-based LDW system, a neural network in supervisory MCU may learn to override LDW when bicyclists or pedestrians are present and a lane departure is, in fact, safest maneuver. In at least one embodiment, supervisory MCU may include at least one of a DLA or GPU suitable for running neural network(s) with associated memory. In at least one embodiment, supervisory MCU may comprise and / or be included as a component of SoC(s) 1104.

[0243] In at least one embodiment, ADAS system 1138 may include a secondary computer that performs ADAS functionality using traditional rules of computer vision. In at least one embodiment, secondary computer may use classic computer vision rules (if-then), and presence of a neural network(s) in supervisory MCU may improve reliability, safety, and performance. For example, in at least one embodiment, diverse implementation and intentional non-identity makes overall system more fault-tolerant, especially to faults caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if there is a software bug or error in software running on primary computer, and non-identical software code running on secondary computer provides same overall result, then supervisory MCU may have greater confidence that overall result is correct, and bug in software or hardware on primary computer is not causing material error.

[0244] In at least one embodiment, output of ADAS system 1138 may be fed into primary computer's perception block and / or primary computer's dynamic driving task block. For example, in at least one embodiment, if ADAS system 1138 indicates a forward crash warning due to an object immediately ahead, perception block may use this information when identifying objects. In at least one embodiment, secondary computer may have its own neural network which is trained and thus reduces risk of false positives, as described herein.

[0245] In at least one embodiment, vehicle 1100 may further include infotainment SoC 1130 (e.g., an in-vehicle infotainment system (IVI)). Although illustrated and described as an SoC, infotainment system 1130, in at least one embodiment, may not be an SoC, and may include, without limitation, two or more discrete components. In at least one embodiment, infotainment SoC 1130 may include, without limitation, a combination of hardware and software that may be used to provide audio (e.g., music, a personal digital assistant, navigational instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation systems, rear-parking assistance, a radio data system, vehicle related information such as fuel level, total distance covered, brake fuel level, oil level, door open / close, air filter information, etc.) to vehicle 1100. For example, infotainment SoC 1130 could include radios, disk players, navigation systems, video players, USB and Bluetooth connectivity, carputers, in-car entertainment, WiFi, steering wheel audio controls, hands free voice control, a heads-up display (“HUD”), HMI display 1134, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, infotainment SoC 1130 may further be used to provide information (e.g., visual and / or audible) to user(s) of vehicle, such as information from ADAS system 1138, autonomous driving information such as planned vehicle maneuvers, trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0246] In at least one embodiment, infotainment SoC 1130 may include any amount and type of GPU functionality. In at least one embodiment, infotainment SoC 1130 may communicate over bus 1102 (e.g., CAN bus, Ethernet, etc.) with other devices, systems, and / or components of vehicle 1100. In at least one embodiment, infotainment SoC 1130 may be coupled to a supervisory MCU such that GPU of infotainment system may perform some self-driving functions in event that primary controller(s) 1136 (e.g., primary and / or backup computers of vehicle 1100) fail. In at least one embodiment, infotainment SoC 1130 may put vehicle 1100 into a chauffeur to safe stop mode, as described herein.

[0247] In at least one embodiment, vehicle 1100 may further include instrument cluster 1132 (e.g., a digital dash, an electronic instrument cluster, a digital instrument panel, etc.). In at least one embodiment, instrument cluster 1132 may include, without limitation, a controller and / or supercomputer (e.g., a discrete controller or supercomputer). In at least one embodiment, instrument cluster 1132 may include, without limitation, any number and combination of a set of instrumentation such as a speedometer, fuel level, oil pressure, tachometer, odometer, turn indicators, gearshift position indicator, seat belt warning light(s), parking-brake warning light(s), engine-malfunction light(s), supplemental restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared among infotainment SoC 1130 and instrument cluster 1132. In at least one embodiment, instrument cluster 1132 may be included as part of infotainment SoC 1130, or vice versa.

[0248] In at least one embodiment, vehicle 1100 is included in computer environment 100 from FIG. 1 and includes a processor (e.g., processor 800) comprising one or more circuits to perform an API to perform one or more processes 300-500. In at least one embodiment, vehicle 1100 performs one or more processes 300-500 as shown in FIGS. 3-5. In at least one embodiment, vehicle 1100 includes one or more components disclosed in FIGS. 1-9 to perform its operations.

[0249] FIG. 11D is a diagram of a system 1177 for communication between cloud-based server(s) and autonomous vehicle 1100 of FIG. 11A, according to at least one embodiment. In at least one embodiment, system 1177 may include, without limitation, server(s) 1178, network(s) 1190, and any number and type of vehicles, including vehicle 1100. server(s) 1178 may include, without limitation, a plurality of GPUs 1184(A)-1184(H) (collectively referred to herein as GPUs 1184), PCIe switches 1182(A)-1182(H) (collectively referred to herein as PCIe switches 1182), and / or CPUs 1180(A)-1180(B) (collectively referred to herein as CPUs 1180). GPUs 1184, CPUs 1180, and PCIe switches 1182 may be interconnected with high-speed interconnects such as, for example and without limitation, NVLink interfaces 1188 developed by NVIDIA and / or PCIe connections 1186. In at least one embodiment, GPUs 1184 are connected via an NVLink and / or NVSwitch SoC and GPUs 1184 and PCIe switches 1182 are connected via PCIe interconnects. In at least one embodiment, although eight GPUs 1184, two CPUs 1180, and four PCIe switches 1182 are illustrated, this is not intended to be limiting. In at least one embodiment, each of server(s) 1178 may include, without limitation, any number of GPUs 1184, CPUs 1180, and / or PCIe switches 1182, in any combination. For example, in at least one embodiment, server(s) 1178 could each include eight, sixteen, thirty-two, and / or more GPUs 1184.

[0250] In at least one embodiment, server(s) 1178 may receive, over network(s) 1190 and from vehicles, image data representative of images showing unexpected or changed road conditions, such as recently commenced roadwork. In at least one embodiment, server(s) 1178 may transmit, over network(s) 1190 and to vehicles, neural networks 1192, updated neural networks 1192, and / or map information 1194, including, without limitation, information regarding traffic and road conditions. In at least one embodiment, updates to map information 1194 may include, without limitation, updates for HD map 1122, such as information regarding construction sites, potholes, detours, flooding, and / or other obstructions. In at least one embodiment, neural networks 1192, updated neural networks 1192, and / or map information 1194 may have resulted from new training and / or experiences represented in data received from any number of vehicles in environment, and / or based at least in part on training performed at a data center (e.g., using server(s) 1178 and / or other servers).

[0251] In at least one embodiment, server(s) 1178 may be used to train machine learning models (e.g., neural networks) based at least in part on training data. In at least one embodiment, training data may be generated by vehicles, and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is tagged (e.g., where associated neural network benefits from supervised learning) and / or undergoes other pre-processing. In at least one embodiment, any amount of training data is not tagged and / or pre-processed (e.g., where associated neural network does not require supervised learning). In at least one embodiment, once machine learning models are trained, machine learning models may be used by vehicles (e.g., transmitted to vehicles over network(s) 1190, and / or machine learning models may be used by server(s) 1178 to remotely monitor vehicles.

[0252] In at least one embodiment, server(s) 1178 may receive data from vehicles and apply data to up-to-date real-time neural networks for real-time intelligent inferencing. In at least one embodiment, server(s) 1178 may include deep-learning supercomputers and / or dedicated AI computers powered by GPU(s) 1184, such as a DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, server(s) 1178 may include deep learning infrastructure that use CPU-powered data centers.

[0253] In at least one embodiment, deep-learning infrastructure of server(s) 1178 may be capable of fast, real-time inferencing, and may use that capability to evaluate and verify health of processors, software, and / or associated hardware in vehicle 1100. For example, in at least one embodiment, deep-learning infrastructure may receive periodic updates from vehicle 1100, such as a sequence of images and / or objects that vehicle 1100 has located in that sequence of images (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, deep-learning infrastructure may run its own neural network to identify objects and compare them with objects identified by vehicle 1100 and, if results do not match and deep-learning infrastructure concludes that AI in vehicle 1100 is malfunctioning, then server(s) 1178 may transmit a signal to vehicle 1100 instructing a fail-safe computer of vehicle 1100 to assume control, notify passengers, and complete a safe parking maneuver.

[0254] In at least one embodiment, server(s) 1178 may include GPU(s) 1184 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3). In at least one embodiment, combination of GPU-powered servers and inference acceleration may make real-time responsiveness possible. In at least one embodiment, such as where performance is less critical, servers powered by CPUs, FPGAs, and other processors may be used for inferencing.Computer Systems

[0255] FIG. 12 is a block diagram illustrating an exemplary computer system, which may be a system with interconnected devices and components, a system-on-a-chip (SOC) or some combination thereof 1200 formed with a processor that may include execution units to execute an instruction, according to at least one embodiment. In at least one embodiment, computer system 1200 may include, without limitation, a component, such as a processor 1202 to employ execution units including logic to perform algorithms for process data, in accordance with present disclosure, such as in embodiment described herein. In at least one embodiment, computer system 1200 may include processors, such as PENTIUM® Processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs having other microprocessors, engineering workstations, set-top boxes and like) may also be used. In at least one embodiment, computer system 1200 may execute a version of WINDOWS' operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (UNIX and Linux for example), embedded software, and / or graphical user interfaces, may also be used.

[0256] Embodiments may be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, embedded applications may include a microcontroller, a digital signal processor (“DSP”), system on a chip, network computers (“NetPCs”), set-top boxes, network hubs, wide area network (“WAN”) switches, or any other system that may perform one or more instructions in accordance with at least one embodiment.

[0257] In at least one embodiment, computer system 1200 may include, without limitation, processor 1202 that may include, without limitation, one or more execution units 1208 to perform machine learning model training and / or inferencing according to techniques described herein. In at least one embodiment, system 12 is a single processor desktop or server system, but in another embodiment system 12 may be a multiprocessor system. In at least one embodiment, processor 1202 may include, without limitation, a complex instruction set computer (“CISC”) microprocessor, a reduced instruction set computing (“RISC”) microprocessor, a very long instruction word (“VLIW”) microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor, for example. In at least one embodiment, processor 1202 may be coupled to a processor bus 1210 that may transmit data signals between processor 1202 and other components in computer system 1200.

[0258] In at least one embodiment, processor 1202 may include, without limitation, a Level 1 (“L1”) internal cache memory (“cache”) 1204. In at least one embodiment, processor 1202 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor 1202. Other embodiments may also include a combination of both internal and external caches depending on particular implementation and needs. In at least one embodiment, register file 1206 may store different types of data in various registers including, without limitation, integer registers, floating point registers, status registers, and instruction pointer register.

[0259] In at least one embodiment, execution unit 1208, including, without limitation, logic to perform integer and floating point operations, also resides in processor 1202. In at least one embodiment, processor 1202 may also include a microcode (“ucode”) read only memory (“ROM”) that stores microcode for certain macro instructions. In at least one embodiment, execution unit 1208 may include logic to handle a packed instruction set 1209. In at least one embodiment, by including packed instruction set 1209 in instruction set of a general-purpose processor 1202, along with associated circuitry to execute instructions, operations used by many multimedia applications may be performed using packed data in a general-purpose processor 1202. In one or more embodiments, many multimedia applications may be accelerated and executed more efficiently by using full width of a processor's data bus for performing operations on packed data, which may eliminate need to transfer smaller units of data across processor's data bus to perform one or more operations one data element at a time.

[0260] In at least one embodiment, execution unit 1208 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1200 may include, without limitation, a memory 1220. In at least one embodiment, memory 1220 may be implemented as a Dynamic Random Access Memory (“DRAM”) device, a Static Random Access Memory (“SRAM”) device, flash memory device, or other memory device. In at least one embodiment, memory 1220 may store instruction(s) 1219 and / or data 1221 represented by data signals that may be executed by processor 1202.

[0261] In at least one embodiment, system logic chip may be coupled to processor bus 1210 and memory 1220. In at least one embodiment, system logic chip may include, without limitation, a memory controller hub (“MCH”) 1216, and processor 1202 may communicate with MCH 1216 via processor bus 1210. In at least one embodiment, MCH 1216 may provide a high bandwidth memory path 1218 to memory 1220 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, MCH 1216 may direct data signals between processor 1202, memory 1220, and other components in computer system 1200 and to bridge data signals between processor bus 1210, memory 1220, and a system I / O 1222. In at least one embodiment, system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1216 may be coupled to memory 1220 through a high bandwidth memory path 1218 and graphics / video card 1212 may be coupled to MCH 1216 through an Accelerated Graphics Port (“AGP”) interconnect 1214.

[0262] In at least one embodiment, computer system 1200 may use system I / O 1222 that is a proprietary hub interface bus to couple MCH 1216 to I / O controller hub (“ICH”) 1230. In at least one embodiment, ICH 1230 may provide direct connections to some I / O devices via a local I / O bus. In at least one embodiment, local I / O bus may include, without limitation, a high-speed I / O bus for connecting peripherals to memory 1220, chipset, and processor 1202. Examples may include, without limitation, an audio controller 1229, a firmware hub (“flash BIOS”) 1228, a wireless transceiver 1226, a data storage 1224, a legacy I / O controller 1223 containing user input and keyboard interfaces, a serial expansion port 1227, such as Universal Serial Bus (“USB”), and a network controller 1234. In at least one embodiment, data storage 1224 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0263] In at least one embodiment, FIG. 12 illustrates a system, which includes interconnected hardware devices or “chips”, whereas in other embodiments, FIG. 12 may illustrate an exemplary System on a Chip (“SoC”). In at least one embodiment, devices illustrated in FIG. 12 may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe) or some combination thereof. In at least one embodiment, one or more components of system 1200 are interconnected using compute express link (CXL) interconnects.

[0264] In at least one embodiment, system 1200 is included in computer environment 100 from FIG. 1 and includes a processor (e.g., processor 800) comprising one or more circuits to perform an API to perform one or more processes 300-500. In at least one embodiment, system 1200 performs one or more processes 300-500 as shown in FIGS. 3-5. In at least one embodiment, system 1200 includes one or more components disclosed in FIGS. 1-9 to perform its operations.

[0265] FIG. 13 is a block diagram illustrating an electronic device 1300 for utilizing a processor 1310, according to at least one embodiment. In at least one embodiment, electronic device 1300 may be, for example and without limitation, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0266] In at least one embodiment, system 1300 may include, without limitation, processor 1310 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 1310 coupled using a bus or interface, such as a 1° C. bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, 3), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, FIG. 13 illustrates a system, which includes interconnected hardware devices or “chips”, whereas in other embodiments, FIG. 13 may illustrate an exemplary System on a Chip (“SoC”). In at least one embodiment, devices illustrated in FIG. 13 may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe) or some combination thereof. In at least one embodiment, one or more components of FIG. 13 are interconnected using compute express link (CXL) interconnects.

[0267] In at least one embodiment, FIG. 13 may include a display 1324, a touch screen 1325, a touch pad 1330, a Near Field Communications unit (“NFC”) 1345, a sensor hub 1340, a thermal sensor 1339, an Express Chipset (“EC”) 1335, a Trusted Platform Module (“TPM”) 1338, BIOS / firmware / flash memory (“BIOS, FW Flash”) 1322, a DSP 1360, a drive “SSD or HDD”) 1320 such as a Solid State Disk (“SSD”) or a Hard Disk Drive (“HDD”), a wireless local area network unit (“WLAN”) 1350, a Bluetooth unit 1352, a Wireless Wide Area Network unit (“WWAN”) 1356, a Global Positioning System (GPS) 1355, a camera (“USB 3.0 camera”) 1354 such as a USB 3.0 camera, or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”) 1315 implemented in, for example, LPDDR3 standard. These components may each be implemented in any suitable manner.

[0268] In at least one embodiment, other components may be communicatively coupled to processor 1310 through components discussed above. In at least one embodiment, an accelerometer 1341, Ambient Light Sensor (“ALS”) 1342, compass 1343, and a gyroscope 1344 may be communicatively coupled to sensor hub 1340. In at least one embodiment, thermal sensor 1339, a fan 1337, a keyboard 1336, and a touch pad 1330 may be communicatively coupled to EC 1335. In at least one embodiment, speaker 1363, a headphone 1364, and a microphone (“mic”) 1365 may be communicatively coupled to an audio unit (“audio codec and class d amp”) 1364, which may in turn be communicatively coupled to DSP 1360. In at least one embodiment, audio unit 1364 may include, for example and without limitation, an audio coder / decoder (“codec”) and a class D amplifier. In at least one embodiment, SIM card (“SIM”) 1357 may be communicatively coupled to WWAN unit 1356. In at least one embodiment, components such as WLAN unit 1350 and Bluetooth unit 1352, as well as WWAN unit 1356 may be implemented in a Next Generation Form Factor (“NGFF”).

[0269] In at least one embodiment, device 1300 is included in computer environment 100 from FIG. 1 and includes a processor (e.g., processor 800) comprising one or more circuits to perform an API to perform one or more processes 300-500. In at least one embodiment, device 1300 performs one or more processes 300-500 as shown in FIGS. 3-5. In at least one embodiment, device 1300 includes one or more components disclosed in FIGS. 1-9 to perform its operations.

[0270] FIG. 14 illustrates a computer system 1400, according to at least one embodiment. In at least one embodiment, computer system 1400 is configured to implement various processes and methods described throughout this disclosure.

[0271] In at least one embodiment, computer system 1400 comprises, without limitation, at least one central processing unit (“CPU”) 1402 that is connected to a communication bus 1410 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), peripheral component interconnect express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol(s). In at least one embodiment, computer system 1400 includes, without limitation, a main memory 1404 and control logic (e.g., implemented as hardware, software, or a combination thereof) and data are stored in main memory 1404 which may take form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“network interface”) 1422 provides an interface to other computing devices and networks for receiving data from and transmitting data to other systems from computer system 1400.

[0272] In at least one embodiment, computer system 1400, in at least one embodiment, includes, without limitation, input devices 1408, parallel processing system 1412, and display devices 1406 which can be implemented using a conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light emitting diode (“LED”), plasma display, or other suitable display technologies. In at least one embodiment, user input is received from input devices 1408 such as keyboard, mouse, touchpad, microphone, and more. In at least one embodiment, each of foregoing modules can be situated on a single semiconductor platform to form a processing system.

[0273] In at least one embodiment, system 1400 is included in computer environment 100 from FIG. 1 and includes a processor (e.g., processor 800) comprising one or more circuits to perform an API to perform one or more processes 300-500. In at least one embodiment, system 1400 performs one or more processes 300-500 as shown in FIGS. 3-5. In at least one embodiment, system 1400 includes one or more components disclosed in FIGS. 1-9 to perform its operations.

[0274] FIG. 15 illustrates a computer system 1500, according to at least one embodiment. In at least one embodiment, computer system 1500 includes, without limitation, a computer 1510 and a USB stick 1520. In at least one embodiment, computer 1510 may include, without limitation, any number and type of processor(s) (not shown) and a memory (not shown). In at least one embodiment, computer 1510 includes, without limitation, a server, a cloud instance, a laptop, and a desktop computer.

[0275] In at least one embodiment, USB stick 1520 includes, without limitation, a processing unit 1530, a USB interface 1540, and USB interface logic 1550. In at least one embodiment, processing unit 1530 may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit 1530 may include, without limitation, any number and type of processing cores (not shown). In at least one embodiment, processing core 1530 comprises an application specific integrated circuit (“ASIC”) that is optimized to perform any amount and type of operations associated with machine learning. For instance, in at least one embodiment, processing core 1530 is a tensor processing unit (“TPC”) that is optimized to perform machine learning inference operations. In at least one embodiment, processing core 1530 is a vision processing unit (“VPU”) that is optimized to perform machine vision and machine learning inference operations.

[0276] In at least one embodiment, USB interface 1540 may be any type of USB connector or USB socket. For instance, in at least one embodiment, USB interface 1540 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, USB interface 1540 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1550 may include any amount and type of logic that enables processing unit 1530 to interface with or devices (e.g., computer 1510) via USB connector 1540.

[0277] In at least one embodiment, system 1500 is included in computer environment 100 from FIG. 1 and includes a processor (e.g., processor 800) comprising one or more circuits to perform an API to perform one or more processes 300-500. In at least one embodiment, system 1500 performs one or more processes 300-500 as shown in FIGS. 3-5. In at least one embodiment, system 1500 includes one or more components disclosed in FIGS. 1-9 to perform its operations.

[0278] FIG. 16A illustrates an exemplary architecture in which a plurality of GPUs 1610-1613 is communicatively coupled to a plurality of multi-core processors 1605-1606 over high-speed links 1640-1643 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, high-speed links 1640-1643 support a communication throughput of 4 GB / s, 30 GB / s, 80 GB / s or higher. Various interconnect protocols may be used including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0.

[0279] In addition, and in one embodiment, two or more of GPUs 1610-1613 are interconnected over high-speed links 1629-1630, which may be implemented using same or different protocols / links than those used for high-speed links 1640-1643. Similarly, two or more of multi-core processors 1605-1606 may be connected over high-speed link 1628 which may be symmetric multi-processor (SMP) buses operating at 20 GB / s, 30 GB / s, 120 GB / s or higher. Alternatively, all communication between various system components shown in FIG. 16A may be accomplished using same protocols / links (e.g., over a common interconnection fabric).

[0280] In one embodiment, each multi-core processor 1605-1606 is communicatively coupled to a processor memory 1601-1602, via memory interconnects 1626-1627, respectively, and each GPU 1610-1613 is communicatively coupled to GPU memory 1620-1623 over GPU memory interconnects 1650-1653, respectively. Memory interconnects 1626-1627 and 1650-1653 may utilize same or different memory access technologies. By way of example, and not limitation, processor memories 1601-1602 and GPU memories 1620-1623 may be volatile memories such as dynamic random access memories (DRAMs) (including stacked DRAMs), Graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or High Bandwidth Memory (HBM) and / or may be non-volatile memories such as 3D XPoint or Nano-Ram. In one embodiment, some portion of processor memories 1601-1602 may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0281] As described herein, although various processors 1605-1606 and GPUs 1610-1613 may be physically coupled to a particular memory 1601-1602, 1620-1623, respectively, a unified memory architecture may be implemented in which a same virtual system address space (also referred to as “effective address” space) is distributed among various physical memories. For example, processor memories 1601-1602 may each comprise 64 GB of system memory address space and GPU memories 1620-1623 may each comprise 32 GB of system memory address space (resulting in a total of 256 GB addressable memory in this example).

[0282] FIG. 16B illustrates additional details for an interconnection between a multi-core processor 1607 and a graphics acceleration module 1646 in accordance with one exemplary embodiment. Graphics acceleration module 1646 may include one or more GPU chips integrated on a line card which is coupled to processor 1607 via high-speed link 1640. Alternatively, graphics acceleration module 1646 may be integrated on a same package or chip as processor 1607.

[0283] In at least one embodiment, illustrated processor 1607 includes a plurality of cores 1660A-1660D, each with a translation lookaside buffer 1661A-1661D and one or more caches 1662A-1662D. In at least one embodiment, cores 1660A-1660D may include various other components for executing instructions and processing data which are not illustrated. Caches 1662A-1662D may comprise level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 1656 may be included in caches 1662A-1662D and shared by sets of cores 1660A-1660D. For example, one embodiment of processor 1607 includes 24 cores, each with its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, one or more L2 and L3 caches are shared by two adjacent cores. Processor 1607 and graphics acceleration module 1646 connect with system memory 1614, which may include processor memories 1601-1602 of FIG. 16A.

[0284] Coherency is maintained for data and instructions stored in various caches 1662A-1662D, 1656 and system memory 1614 via inter-core communication over a coherence bus 1664. For example, each cache may have cache coherency logic / circuitry associated therewith to communicate to over coherence bus 1664 in response to detected reads or writes to particular cache lines. In one implementation, a cache snooping protocol is implemented over coherence bus 1664 to snoop cache accesses.

[0285] In one embodiment, a proxy circuit 1625 communicatively couples graphics acceleration module 1646 to coherence bus 1664, allowing graphics acceleration module 1646 to participate in a cache coherence protocol as a peer of cores 1660A-1660D. An interface 1635 provides connectivity to proxy circuit 1625 over high-speed link 1640 (e.g., a PCIe bus, NVLink, etc.) and an interface 1637 connects graphics acceleration module 1646 to link 1640.

[0286] In one implementation, an accelerator integration circuit 1636 provides cache management, memory access, context management, and interrupt management services on behalf of a plurality of graphics processing engines 1631, 1632, N of graphics acceleration module 1646. Graphics processing engines 1631, 1632, N may each comprise a separate graphics processing unit (GPU). Alternatively, graphics processing engines 1631, 1632, N may comprise different types of graphics processing engines within a GPU such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, graphics acceleration module 1646 may be a GPU with a plurality of graphics processing engines 1631-1632, N or graphics processing engines 1631-1632, N may be individual GPUs integrated on a common package, line card, or chip.

[0287] In one embodiment, accelerator integration circuit 1636 includes a memory management unit (MMU) 1639 for performing various memory management functions such as virtual-to-physical memory translations (also referred to as effective-to-real memory translations) and memory access protocols for accessing system memory 1614. MMU 1639 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective to physical / real address translations. In one implementation, a cache 1638 stores commands and data for efficient access by graphics processing engines 1631-1632, N. In one embodiment, data stored in cache 1638 and graphics memories 1633-1634, M is kept coherent with core caches 1662A-1662D, 1656 and system memory 1614. As mentioned, this may be accomplished via proxy circuit 1625 on behalf of cache 1638 and memories 1633-1634, M (e.g., sending updates to cache 1638 related to modifications / accesses of cache lines on processor caches 1662A-1662D, 1656 and receiving updates from cache 1638).

[0288] A set of registers 1645 store context data for threads executed by graphics processing engines 1631-1632, N and a context management circuit 1648 manages thread contexts. For example, context management circuit 1648 may perform save and restore operations to save and restore contexts of various threads during contexts switches (e.g., where a first thread is saved and a second thread is stored so that a second thread can be execute by a graphics processing engine). For example, on a context switch, context management circuit 1648 may store current register values to a designated region in memory (e.g., identified by a context pointer). It may then restore register values when returning to a context. In one embodiment, an interrupt management circuit 1647 receives and processes interrupts received from system devices.

[0289] In one implementation, virtual / effective addresses from a graphics processing engine 1631 are translated to real / physical addresses in system memory 1614 by MMU 1639. One embodiment of accelerator integration circuit 1636 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1646 and / or other accelerator devices. Graphics accelerator module 1646 may be dedicated to a single application executed on processor 1607 or may be shared between multiple applications. In one embodiment, a virtualized graphics execution environment is presented in which resources of graphics processing engines 1631-1632, N are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into “slices” which are allocated to different VMs and / or applications based on processing requirements and priorities associated with VMs and / or applications.

[0290] In at least one embodiment, accelerator integration circuit 1636 performs as a bridge to a system for graphics acceleration module 1646 and provides address translation and system memory cache services. In addition, accelerator integration circuit 1636 may provide virtualization facilities for a host processor to manage virtualization of graphics processing engines 1631-1632, interrupts, and memory management.

[0291] Because hardware resources of graphics processing engines 1631-1632, N are mapped explicitly to a real address space seen by host processor 1607, any host processor can address these resources directly using an effective address value. One function of accelerator integration circuit 1636, in one embodiment, is physical separation of graphics processing engines 1631-1632, N so that they appear to a system as independent units.

[0292] In at least one embodiment, one or more graphics memories 1633-1634, M are coupled to each of graphics processing engines 1631-1632, N, respectively. Graphics memories 1633-1634, M store instructions and data being processed by each of graphics processing engines 1631-1632, N. Graphics memories 1633-1634, M may be volatile memories such as DRAMs (including stacked DRAMs), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories such as 3D XPoint or Nano-Ram.

[0293] In one embodiment, to reduce data traffic over link 1640, biasing techniques are used to ensure that data stored in graphics memories 1633-1634, M is data which will be used most frequently by graphics processing engines 1631-1632, N and preferably not used by cores 1660A-1660D (at least not frequently). Similarly, a biasing mechanism attempts to keep data needed by cores (and preferably not graphics processing engines 1631-1632, N) within caches 1662A-1662D, 1656 of cores and system memory 1614.

[0294] FIG. 16C illustrates another exemplary embodiment in which accelerator integration circuit 1636 is integrated within processor 1607. In this embodiment, graphics processing engines 1631-1632, N communicate directly over high-speed link 1640 to accelerator integration circuit 1636 via interface 1637 and interface 1635 (which, again, may be utilize any form of bus or interface protocol). Accelerator integration circuit 1636 may perform same operations as those described with respect to FIG. 16B, but potentially at a higher throughput given its close proximity to coherence bus 1664 and caches 1662A-1662D, 1656. One embodiment supports different programming models including a dedicated-process programming model (no graphics acceleration module virtualization) and shared programming models (with virtualization), which may include programming models which are controlled by accelerator integration circuit 1636 and programming models which are controlled by graphics acceleration module 1646.

[0295] In at least one embodiment, graphics processing engines 1631-1632, N are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 1631-1632, N, providing virtualization within a VM / partition.

[0296] In at least one embodiment, graphics processing engines 1631-1632, N, may be shared by multiple VM / application partitions. In at least one embodiment, shared models may use a system hypervisor to virtualize graphics processing engines 1631-1632, N to allow access by each operating system. For single-partition systems without a hypervisor, graphics processing engines 1631-1632, N are owned by an operating system. In at least one embodiment, an operating system can virtualize graphics processing engines 1631-1632, N to provide access to each process or application.

[0297] In at least one embodiment, graphics acceleration module 1646 or an individual graphics processing engine 1631-1632, N selects a process element using a process handle. In one embodiment, process elements are stored in system memory 1614 and are addressable using an effective address to real address translation techniques described herein. In at least one embodiment, a process handle may be an implementation-specific value provided to a host process when registering its context with graphics processing engine 1631-1632, N (that is, calling system software to add a process element to a process element linked list). In at least one embodiment, a lower 16-bits of a process handle may be an offset of the process element within a process element linked list.

[0298] FIG. 16D illustrates an exemplary accelerator integration slice 1690. As used herein, a “slice” comprises a specified portion of processing resources of accelerator integration circuit 1636. Application effective address space 1682 within system memory 1614 stores process elements 1683. In one embodiment, process elements 1683 are stored in response to GPU invocations 1681 from applications 1680 executed on processor 1607. A process element 1683 contains process state for corresponding application 1680. A work descriptor (WD) 1684 contained in process element 1683 can be a single job requested by an application or may contain a pointer to a queue of jobs. In at least one embodiment, WD 1684 is a pointer to a job request queue in an application's address space 1682.

[0299] Graphics acceleration module 1646 and / or individual graphics processing engines 1631-1632, N can be shared by all or a subset of processes in a system. In at least one embodiment, an infrastructure for setting up process state and sending a WD 1684 to a graphics acceleration module 1646 to start a job in a virtualized environment may be included.

[0300] In at least one embodiment, a dedicated-process programming model is implementation-specific. In this model, a single process owns graphics acceleration module 1646 or an individual graphics processing engine 1631. Because graphics acceleration module 1646 is owned by a single process, a hypervisor initializes accelerator integration circuit 1636 for an owning partition and an operating system initializes accelerator integration circuit 1636 for an owning process when graphics acceleration module 1646 is assigned.

[0301] In operation, a WD fetch unit 1691 in accelerator integration slice 1690 fetches next WD 1684 which includes an indication of work to be done by one or more graphics processing engines of graphics acceleration module 1646. Data from WD 1684 may be stored in registers 1645 and used by MMU 1639, interrupt management circuit 1647 and / or context management circuit 1648 as illustrated. For example, one embodiment of MMU 1639 includes segment / page walk circuitry for accessing segment / page tables 1686 within OS virtual address space 1685. Interrupt management circuit 1647 may process interrupt events 1692 received from graphics acceleration module 1646. When performing graphics operations, an effective address 1693 generated by a graphics processing engine 1631-1632, N is translated to a real address by MMU 1639.

[0302] In one embodiment, a same set of registers 1645 are duplicated for each graphics processing engine 1631-1632, N and / or graphics acceleration module 1646 and may be initialized by a hypervisor or operating system. Each of these duplicated registers may be included in an accelerator integration slice 1690. Exemplary registers that may be initialized by a hypervisor are shown in Table 1.

[0303] TABLE 1Hypervisor Initialized Registers1Slice Control Register2Real Address (RA) Scheduled Processes Area Pointer3Authority Mask Override Register4Interrupt Vector Table Entry Offset5Interrupt Vector Table Entry Limit6State Register7Logical Partition ID8Real address (RA) Hypervisor Accelerator Utilization Record Pointer9Storage Description Register

[0304] Exemplary registers that may be initialized by an operating system are shown in Table 2.

[0305] TABLE 2Operating System Initialized Registers1Process and Thread Identification2Effective Address (EA) Context Save / Restore Pointer3Virtual Address (VA) Accelerator Utilization Record Pointer4Virtual Address (VA) Storage Segment Table Pointer5Authority Mask6Work descriptor

[0306] In one embodiment, each WD 1684 is specific to a particular graphics acceleration module 1646 and / or graphics processing engines 1631-1632, N. It contains all information required by a graphics processing engine 1631-1632, N to do work or it can be a pointer to a memory location where an application has set up a command queue of work to be completed.

[0307] FIG. 16E illustrates additional details for one exemplary embodiment of a shared model. This embodiment includes a hypervisor real address space 1698 in which a process element list 1699 is stored. Hypervisor real address space 1698 is accessible via a hypervisor 1696 which virtualizes graphics acceleration module engines for operating system 1695.

[0308] In at least one embodiment, shared programming models allow for all or a subset of processes from all or a subset of partitions in a system to use a graphics acceleration module 1646. There are two programming models where graphics acceleration module 1646 is shared by multiple processes and partitions: time-sliced shared and graphics directed shared.

[0309] In this model, system hypervisor 1696 owns graphics acceleration module 1646 and makes its function available to all operating systems 1695. For a graphics acceleration module 1646 to support virtualization by system hypervisor 1696, graphics acceleration module 1646 may adhere to the following: 1) An application's job request must be autonomous (that is, state does not need to be maintained between jobs), or graphics acceleration module 1646 must provide a context save and restore mechanism. 2) An application's job request is guaranteed by graphics acceleration module 1646 to complete in a specified amount of time, including any translation faults, or graphics acceleration module 1646 provides an ability to preempt processing of a job. 3) Graphics acceleration module 1646 must be guaranteed fairness between processes when operating in a directed shared programming model.

[0310] In at least one embodiment, application 1680 is required to make an operating system 1695 system call with a graphics acceleration module 1646 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP). In at least one embodiment, graphics acceleration module 1646 type describes a targeted acceleration function for a system call. In at least one embodiment, graphics acceleration module 1646 type may be a system-specific value. In at least one embodiment, WD is formatted specifically for graphics acceleration module 1646 and can be in a form of a graphics acceleration module 1646 command, an effective address pointer to a user-defined structure, an effective address pointer to a queue of commands, or any other data structure to describe work to be done by graphics acceleration module 1646. In one embodiment, an AMR value is an AMR state to use for a current process. In at least one embodiment, a value passed to an operating system is similar to an application setting an AMR. If accelerator integration circuit 1636 and graphics acceleration module 1646 implementations do not support a User Authority Mask Override Register (UAMOR), an operating system may apply a current UAMOR value to an AMR value before passing an AMR in a hypervisor call. Hypervisor 1696 may optionally apply a current Authority Mask Override Register (AMOR) value before placing an AMR into process element 1683. In at least one embodiment, CSRP is one of registers 1645 containing an effective address of an area in an application's address space 1682 for graphics acceleration module 1646 to save and restore context state. This pointer is optional if no state is required to be saved between jobs or when a job is preempted. In at least one embodiment, context save / restore area may be pinned system memory.

[0311] Upon receiving a system call, operating system 1695 may verify that application 1680 has registered and been given authority to use graphics acceleration module 1646. Operating system 1695 then calls hypervisor 1696 with information shown in Table 3.

[0312] TABLE 3OS to Hypervisor Call Parameters1A work descriptor (WD)2An Authority Mask Register (AMR) value (potentially masked)3An effective address (EA) Context Save / Restore Area Pointer (CSRP)4A process ID (PID) and optional thread ID (TID)5A virtual address (VA) accelerator utilization record pointer (AURP)6Virtual address of storage segment table pointer (SSTP)7A logical interrupt service number (LISN)

[0313] Upon receiving a hypervisor call, hypervisor 1696 verifies that operating system 1695 has registered and been given authority to use graphics acceleration module 1646. Hypervisor 1696 then puts process element 1683 into a process element linked list for a corresponding graphics acceleration module 1646 type. A process element may include information shown in Table 4.

[0314] TABLE 4Process Element Information1A work descriptor (WD)2An Authority Mask Register (AMR) value (potentially masked).3An effective address (EA) Context Save / Restore Area Pointer (CSRP)4A process ID (PID) and optional thread ID (TID)5A virtual address (VA) accelerator utilization record pointer (AURP)6Virtual address of storage segment table pointer (SSTP)7A logical interrupt service number (LISN)8Interrupt vector table, derived from hypervisor call parameters9A state register (SR) value10A logical partition ID (LPID)11A real address (RA) hypervisor accelerator utilization record pointer12Storage Descriptor Register (SDR)

[0315] In at least one embodiment, hypervisor initializes a plurality of accelerator integration slice 1690 registers 1645.

[0316] As illustrated in FIG. 16F, in at least one embodiment, a unified memory is used, addressable via a common virtual memory address space used to access physical processor memories 1601-1602 and GPU memories 1620-1623. In this implementation, operations executed on GPUs 1610-1613 utilize a same virtual / effective memory address space to access processor memories 1601-1602 and vice versa, thereby simplifying programmability. In one embodiment, a first portion of a virtual / effective address space is allocated to processor memory 1601, a second portion to second processor memory 1602, a third portion to GPU memory 1620, and so on. In at least one embodiment, an entire virtual / effective memory space (sometimes referred to as an effective address space) is thereby distributed across each of processor memories 1601-1602 and GPU memories 1620-1623, allowing any processor or GPU to access any physical memory with a virtual address mapped to that memory.

[0317] In one embodiment, bias / coherence management circuitry 1694A-1694E within one or more of MMUs 1639A-1639E ensures cache coherence between caches of one or more host processors (e.g., 1605) and GPUs 1610-1613 and implements biasing techniques indicating physical memories in which certain types of data should be stored. While multiple instances of bias / coherence management circuitry 1694A-1694E are illustrated in FIG. 16F, bias / coherence circuitry may be implemented within an MMU of one or more host processors 1605 and / or within accelerator integration circuit 1636.

[0318] One embodiment allows GPU-attached memory 1620-1623 to be mapped as part of system memory, and accessed using shared virtual memory (SVM) technology, but without suffering performance drawbacks associated with full system cache coherence. In at least one embodiment, an ability for GPU-attached memory 1620-1623 to be accessed as system memory without onerous cache coherence overhead provides a beneficial operating environment for GPU offload. This arrangement allows host processor 1605 software to setup operands and access computation results, without overhead of tradition I / O DMA data copies. Such traditional copies involve driver calls, interrupts and memory mapped I / O (MMIO) accesses that are all inefficient relative to simple memory accesses. In at least one embodiment, an ability to access GPU attached memory 1620-1623 without cache coherence overheads can be critical to execution time of an offloaded computation. In cases with substantial streaming write memory traffic, for example, cache coherence overhead can significantly reduce an effective write bandwidth seen by a GPU 1610-1613. In at least one embodiment, efficiency of operand setup, efficiency of results access, and efficiency of GPU computation may play a role in determining effectiveness of a GPU offload.

[0319] In at least one embodiment, selection of GPU bias and host processor bias is driven by a bias tracker data structure. A bias table may be used, for example, which may be a page-granular structure (i.e., controlled at a granularity of a memory page) that includes 1 or 2 bits per GPU-attached memory page. In at least one embodiment, a bias table may be implemented in a stolen memory range of one or more GPU-attached memories 1620-1623, with or without a bias cache in GPU 1610-1613 (e.g., to cache frequently / recently used entries of a bias table). Alternatively, an entire bias table may be maintained within a GPU.

[0320] In at least one embodiment, a bias table entry associated with each access to GPU-attached memory 1620-1623 is accessed prior to actual access to a GPU memory, causing the following operations. First, local requests from GPU 1610-1613 that find their page in GPU bias are forwarded directly to a corresponding GPU memory 1620-1623. Local requests from a GPU that find their page in host bias are forwarded to processor 1605 (e.g., over a high-speed link as discussed above). In one embodiment, requests from processor 1605 that find a requested page in host processor bias complete a request like a normal memory read. Alternatively, requests directed to a GPU-biased page may be forwarded to GPU 1610-1613. In at least one embodiment, a GPU may then transition a page to a host processor bias if it is not currently using a page. In at least one embodiment, bias state of a page can be changed either by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, a purely hardware-based mechanism.

[0321] One mechanism for changing bias state employs an API call (e.g., OpenCL), which, in turn, calls a GPU's device driver which, in turn, sends a message (or enqueues a command descriptor) to a GPU directing it to change a bias state and, for some transitions, perform a cache flushing operation in a host. In at least one embodiment, cache flushing operation is used for a transition from host processor 1605 bias to GPU bias, but is not for an opposite transition.

[0322] In one embodiment, cache coherency is maintained by temporarily rendering GPU-biased pages uncacheable by host processor 1605. To access these pages, processor 1605 may request access from GPU 1610 which may or may not grant access right away. Thus, to reduce communication between processor 1605 and GPU 1610 it is beneficial to ensure that GPU-biased pages are those which are required by a GPU but not host processor 1605 and vice versa.

[0323] FIG. 17 illustrates exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to what is illustrated, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0324] FIG. 17 is a block diagram illustrating an exemplary system on a chip integrated circuit 1700 that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, integrated circuit 1700 includes one or more application processor(s) 1705 (e.g., CPUs), at least one graphics processor 1710, and may additionally include an image processor 1715 and / or a video processor 1720, any of which may be a modular IP core. In at least one embodiment, integrated circuit 1700 includes peripheral or bus logic including a USB controller 1725, UART controller 1730, an SPI / SDIO controller 1735, and an I.sup.2S / I.sup.2C controller 1740. In at least one embodiment, integrated circuit 1700 can include a display device 1745 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1750 and a mobile industry processor interface (MIPI) display interface 1755.

[0325] In at least one embodiment, storage may be provided by a flash memory subsystem 1760 including flash memory and a flash memory controller. In at least one embodiment, memory interface may be provided via a memory controller 1765 for access to SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits additionally include an embedded security engine 1770.

[0326] In at least one embodiment, circuit 1700 is included in computer environment 100 from FIG. 1 and includes a processor (e.g., processor 800) comprising one or more circuits to perform an API to perform one or more processes 300-500. In at least one embodiment, circuit 1700 performs one or more processes 300-500 as shown in FIGS. 3-5. In at least one embodiment circuit 1700 includes one or more components disclosed in FIGS. 1-9 to perform its operations.

[0327] FIGS. 18A-18B illustrate exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to what is illustrated, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0328] FIGS. 18A-18B are block diagrams illustrating exemplary graphics processors for use within an SoC, according to embodiments described herein. FIG. 18A illustrates an exemplary graphics processor 1810 of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. FIG. 18B illustrates an additional exemplary graphics processor 1840 of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, graphics processor 1810 of FIG. 18A is a low power graphics processor core. In at least one embodiment, graphics processor 1840 of FIG. 18B is a higher performance graphics processor core. In at least one embodiment, each of graphics processors 1810, 1840 can be variants of graphics processor 1710 of FIG. 17.

[0329] In at least one embodiment, graphics processor 1810 includes a vertex processor 1805 and one or more fragment processor(s) 1815A-1815N (e.g., 1815A, 1815B, 1815C, 1815D, through 1815N-1, and 1815N). In at least one embodiment, graphics processor 1810 can execute different shader programs via separate logic, such that vertex processor 1805 is optimized to execute operations for vertex shader programs, while one or more fragment processor(s) 1815A-1815N execute fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, vertex processor 1805 performs a vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, fragment processor(s) 1815A-1815N use primitive and vertex data generated by vertex processor 1805 to produce a framebuffer that is displayed on a display device. In at least one embodiment, fragment processor(s) 1815A-1815N are optimized to execute fragment shader programs as provided for in an OpenGL API, which may be used to perform similar operations as a pixel shader program as provided for in a Direct 3D API.

[0330] In at least one embodiment, graphics processor 1810 additionally includes one or more memory management units (MMUs) 1820A-1820B, cache(s) 1825A-1825B, and circuit interconnect(s) 1830A-1830B. In at least one embodiment, one or more MMU(s) 1820A-1820B provide for virtual to physical address mapping for graphics processor 1810, including for vertex processor 1805 and / or fragment processor(s) 1815A-1815N, which may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more cache(s) 1825A-1825B. In at least one embodiment, one or more MMU(s) 1820A-1820B may be synchronized with other MMUs within system, including one or more MMUs associated with one or more application processor(s) 1705, image processors 1715, and / or video processors 1720 of FIG. 17, such that each processor 1705-1720 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnect(s) 1830A-1830B enable graphics processor 1810 to interface with other IP cores within SoC, either via an internal bus of SoC or via a direct connection.

[0331] In at least one embodiment, graphics processor 1840 includes one or more MMU(s) 1820A-1820B, caches 1825A-1825B, and circuit interconnects 1830A-1830B of graphics processor 1810 of FIG. 18A. In at least one embodiment, graphics processor 1840 includes one or more shader core(s) 1855A-1855N (e.g., 1855A, 1855B, 1855C, 1855D, 1855E, 1855F, through 1855N-1, and 1855N), which provides for a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, a number of shader cores can vary. In at least one embodiment, graphics processor 1840 includes an inter-core task manager 1845, which acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1855A-1855N and a tiling unit 1858 to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within a scene or to optimize use of internal caches.

[0332] In at least one embodiment, graphic processor 1800 is included in computer environment 100 from FIG. 1 and includes a processor (e.g., processor 800) comprising one or more circuits to perform an API to perform one or more processes 300-500. In at least one embodiment, graphic processor 1800 performs one or more processes 300-500 as shown in FIGS. 3-5. In at least one embodiment graphic processor 1800 includes one or more components disclosed in FIGS. 1-9 to perform its operations.

[0333] FIGS. 19A-19B illustrate additional exemplary graphics processor logic according to embodiments described herein. FIG. 19A illustrates a graphics core 1900 that may be included within graphics processor 1710 of FIG. 17, in at least one embodiment, and may be a unified shader core 1855A-1855N as in FIG. 18B in at least one embodiment. FIG. 19B illustrates a highly-parallel general-purpose graphics processing unit 1930 suitable for deployment on a multi-chip module in at least one embodiment.

[0334] In at least one embodiment, graphics core 1900 includes a shared instruction cache 1902, a texture unit 1918, and a cache / shared memory 1920 that are common to execution resources within graphics core 1900. In at least one embodiment, graphics core 1900 can include multiple slices 1901A-1901N or partition for each core, and a graphics processor can include multiple instances of graphics core 1900. Slices 1901A-1901N can include support logic including a local instruction cache 1904A-1904N, a thread scheduler 1906A-1906N, a thread dispatcher 1908A-1908N, and a set of registers 1910A-1910N. In at least one embodiment, slices 1901A-1901N can include a set of additional function units (AFUs 1912A-1912N), floating-point units (FPU 1914A-1914N), integer arithmetic logic units (ALUs 1916-1916N), address computational units (ACU 1913A-1913N), double-precision floating-point units (DPFPU 1915A-1915N), and matrix processing units (MPU 1917A-1917N).

[0335] In at least one embodiment, FPUs 1914A-1914N can perform single-precision (32-bit) and half-precision (16-bit) floating point operations, while DPFPUs 1915A-1915N perform double precision (64-bit) floating point operations. In at least one embodiment, ALUs 1916A-1916N can perform variable precision integer operations at 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed precision operations. In at least one embodiment, MPUs 1917A-1917N can also be configured for mixed precision matrix operations, including half-precision floating point and 8-bit integer operations. In at least one embodiment, MPUs 1917-1917N can perform a variety of matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix to matrix multiplication (GEMM). In at least one embodiment, AFUs 1912A-1912N can perform additional logic operations not supported by floating-point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

[0336] In at least one embodiment, graphic processor 1800 is included in computer environment 100 from FIG. 1 and includes a processor (e.g., processor 800) comprising one or more circuits to perform an API to perform one or more processes 300-500. In at least one embodiment, graphic processor 1800 performs one or more processes 300-500 as shown in FIGS. 3-5. In at least one embodiment graphic processor 1800 includes one or more components disclosed in FIGS. 1-9 to perform its operations.

[0337] FIG. 19B illustrates a general-purpose processing unit (GPGPU) 1930 that can be configured to enable highly-parallel compute operations to be performed by an array of graphics processing units, in at least one embodiment. In at least one embodiment, GPGPU 1930 can be linked directly to other instances of GPGPU 1930 to create a multi-GPU cluster to improve training speed for deep neural networks. In at least one embodiment, GPGPU 1930 includes a host interface 1932 to enable a connection with a host processor. In at least one embodiment, host interface 1932 is a PCI Express interface. In at least one embodiment, host interface 1932 can be a vendor specific communications interface or communications fabric. In at least one embodiment, GPGPU 1930 receives commands from a host processor and uses a global scheduler 1934 to distribute execution threads associated with those commands to a set of compute clusters 1936A-1936H. In at least one embodiment, compute clusters 1936A-1936H share a cache memory 1938. In at least one embodiment, cache memory 1938 can serve as a higher-level cache for cache memories within compute clusters 1936A-1936H.

[0338] In at least one embodiment, GPGPU 1930 includes memory 1944A-1944B coupled with compute clusters 1936A-1936H via a set of memory controllers 1942A-1942B. In at least one embodiment, memory 1944A-1944B can include various types of memory devices including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0339] In at least one embodiment, compute clusters 1936A-1936H each include a set of graphics cores, such as graphics core 1900 of FIG. 19A, which can include multiple types of integer and floating point logic units that can perform computational operations at a range of precisions including suited for machine learning computations. For example, in at least one embodiment, at least a subset of floating point units in each of compute clusters 1936A-1936H can be configured to perform 16-bit or 32-bit floating point operations, while a different subset of floating point units can be configured to perform 64-bit floating point operations.

[0340] In at least one embodiment, multiple instances of GPGPU 1930 can be configured to operate as a compute cluster. In at least one embodiment, communication used by compute clusters 1936A-1936H for synchronization and data exchange varies across embodiments. In at least one embodiment, multiple instances of GPGPU 1930 communicate over host interface 1932. In at least one embodiment, GPGPU 1930 includes an I / O hub 1939 that couples GPGPU 1930 with a GPU link 1940 that enables a direct connection to other instances of GPGPU 1930. In at least one embodiment, GPU link 1940 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1930. In at least one embodiment GPU link 1940 couples with a high-speed interconnect to transmit and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1930 are located in separate data processing systems and communicate via a network device that is accessible via host interface 1932. In at least one embodiment GPU link 1940 can be configured to enable a connection to a host processor in addition to or as an alternative to host interface 1932.

[0341] In at least one embodiment, GPGPU 1930 can be configured to train neural networks. In at least one embodiment, GPGPU 1930 can be used within an inferencing platform. In at least one embodiment, in which GPGPU 1930 is used for inferencing, GPGPU may include fewer compute clusters 1936A-1936H relative to when GPGPU is used for training a neural network. In at least one embodiment, memory technology associated with memory 1944A-1944B may differ between inferencing and training configurations, with higher bandwidth memory technologies devoted to training configurations. In at least one embodiment, inferencing configuration of GPGPU 1930 can support inferencing specific instructions. For example, in at least one embodiment, an inferencing configuration can provide support for one or more 8-bit integer dot product instructions, which may be used during inferencing operations for deployed neural networks.

[0342] In at least one embodiment, graphic processor 1900 is included in computer environment 100 from FIG. 1 and includes a processor (e.g., processor 800) comprising one or more circuits to perform an API to perform one or more processes 300-500. In at least one embodiment, graphic processor 1900 performs one or more processes 300-500 as shown in FIGS. 3-5. In at least one embodiment graphic processor 1900 includes one or more components disclosed in FIGS. 1-9 to perform its operations.

[0343] FIG. 20 is a block diagram illustrating a computing system 2000 according to at least one embodiment. In at least one embodiment, computing system 2000 includes a processing subsystem 2001 having one or more processor(s) 2002 and a system memory 2004 communicating via an interconnection path that may include a memory hub 2005. In at least one embodiment, memory hub 2005 may be a separate component within a chipset component or may be integrated within one or more processor(s) 2002. In at least one embodiment, memory hub 2005 couples with an I / O subsystem 2011 via a communication link 2006. In at least one embodiment, I / O subsystem 2011 includes an I / O hub 2007 that can enable computing system 2000 to receive input from one or more input device(s) 2008. In at least one embodiment, I / O hub 2007 can enable a display controller, which may be included in one or more processor(s) 2002, to provide outputs to one or more display device(s) 2010A. In at least one embodiment, one or more display device(s) 2010A coupled with I / O hub 2007 can include a local, internal, or embedded display device.

[0344] In at least one embodiment, processing subsystem 2001 includes one or more parallel processor(s) 2012 coupled to memory hub 2005 via a bus or other communication link 2013. In at least one embodiment, communication link 2013 may be one of any number of standards based communication link technologies or protocols, such as, but not limited to PCI Express, or may be a vendor specific communications interface or communications fabric. In at least one embodiment, one or more parallel processor(s) 2012 form a computationally focused parallel or vector processing system that can include a large number of processing cores and / or processing clusters, such as a many integrated core (MIC) processor. In at least one embodiment, one or more parallel processor(s) 2012 form a graphics processing subsystem that can output pixels to one of one or more display device(s) 2010A coupled via I / O Hub 2007. In at least one embodiment, one or more parallel processor(s) 2012 can also include a display controller and display interface (not shown) to enable a direct connection to one or more display device(s) 2010B.

[0345] In at least one embodiment, a system storage unit 2014 can connect to I / O hub 2007 to provide a storage mechanism for computing system 2000. In at least one embodiment, an I / O switch 2016 can be used to provide an interface mechanism to enable connections between I / O hub 2007 and other components, such as a network adapter 2018 and / or wireless network adapter 2019 that may be integrated into platform, and various other devices that can be added via one or more add-in device(s) 2020. In at least one embodiment, network adapter 2018 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 2019 can include one or more of a Wi-Fi, Bluetooth, near field communication (NFC), or other network device that includes one or more wireless radios.

[0346] In at least one embodiment, computing system 2000 can include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and like, may also be connected to I / O hub 2007. In at least one embodiment, communication paths interconnecting various components in FIG. 20 may be implemented using any suitable protocols, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCI-Express), or other bus or point-to-point communication interfaces and / or protocol(s), such as NV-Link high-speed interconnect, or interconnect protocols.

[0347] In at least one embodiment, one or more parallel processor(s) 2012 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitutes a graphics processing unit (GPU). In at least one embodiment, one or more parallel processor(s) 2012 incorporate circuitry optimized for general purpose processing. In at least embodiment, components of computing system 2000 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processor(s) 2012, memory hub 2005, processor(s) 2002, and I / O hub 2007 can be integrated into a system on chip (SoC) integrated circuit. In at least one embodiment, components of computing system 2000 can be integrated into a single package to form a system in package (SIP) configuration. In at least one embodiment, at least a portion of components of computing system 2000 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system.

[0348] In at least one embodiment, graphic system 2000 is included in computer environment 100 from FIG. 1 and includes a processor (e.g., processor 800) comprising one or more circuits to perform an API to perform one or more processes 300-500. In at least one embodiment, system 2000 performs one or more processes 300-500 as shown in FIGS. 3-5. In at least one embodiment system 2000 includes one or more components disclosed in FIGS. 1-9 to perform its operations.Processors

[0349] FIG. 21A illustrates a parallel processor 2100 according to at least on embodiment. In at least one embodiment, various components of parallel processor 2100 may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGA). In at least one embodiment, illustrated parallel processor 2100 is a variant of one or more parallel processor(s) 2012 shown in FIG. 20 according to an exemplary embodiment.

[0350] In at least one embodiment, parallel processor 2100 includes a parallel processing unit 2102. In at least one embodiment, parallel processing unit 2102 includes an I / O unit 2104 that enables communication with other devices, including other instances of parallel processing unit 2102. In at least one embodiment, I / O unit 2104 may be directly connected to other devices. In at least one embodiment, I / O unit 2104 connects with other devices via use of a hub or switch interface, such as memory hub 2105. In at least one embodiment, connections between memory hub 2105 and I / O unit 2104 form a communication link. In at least one embodiment, I / O unit 2104 connects with a host interface 2106 and a memory crossbar 2116, where host interface 2106 receives commands directed to performing processing operations and memory crossbar 2116 receives commands directed to performing memory operations.

[0351] In at least one embodiment, when host interface 2106 receives a command buffer via I / O unit 2104, host interface 2106 can direct work operations to perform those commands to a front end 2108. In at least one embodiment, front end 2108 couples with a scheduler 2110, which is configured to distribute commands or other work items to a processing cluster array 2112. In at least one embodiment, scheduler 2110 ensures that processing cluster array 2112 is properly configured and in a valid state before tasks are distributed to processing cluster array 2112 of processing cluster array 2112. In at least one embodiment, scheduler 2110 is implemented via firmware logic executing on a microcontroller. In at least one embodiment, microcontroller implemented scheduler 2110 is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity, enabling rapid preemption and context switching of threads executing on processing array 2112. In at least one embodiment, host software can prove workloads for scheduling on processing array 2112 via one of multiple graphics processing doorbells. In at least one embodiment, workloads can then be automatically distributed across processing array 2112 by scheduler 2110 logic within a microcontroller including scheduler 2110.

[0352] In at least one embodiment, processing cluster array 2112 can include up to “N” processing clusters (e.g., cluster 2114A, cluster 2114B, through cluster 2114N). In at least one embodiment, each cluster 2114A-2114N of processing cluster array 2112 can execute a large number of concurrent threads. In at least one embodiment, scheduler 2110 can allocate work to clusters 2114A-2114N of processing cluster array 2112 using various scheduling and / or work distribution algorithms, which may vary depending on workload arising for each type of program or computation. In at least one embodiment, scheduling can be handled dynamically by scheduler 2110, or can be assisted in part by compiler logic during compilation of program logic configured for execution by processing cluster array 2112. In at least one embodiment, different clusters 2114A-2114N of processing cluster array 2112 can be allocated for processing different types of programs or for performing different types of computations.

[0353] In at least one embodiment, processing cluster array 2112 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 2112 is configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, processing cluster array 2112 can include logic to execute processing tasks including filtering of video and / or audio data, performing modeling operations, including physics operations, and performing data transformations.

[0354] In at least one embodiment, processing cluster array 2112 is configured to perform parallel graphics processing operations. In at least one embodiment, processing cluster array 2112 can include additional logic to support execution of such graphics processing operations, including, but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing cluster array 2112 can be configured to execute graphics processing related shader programs such as, but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit 2102 can transfer data from system memory via I / O unit 2104 for processing. In at least one embodiment, during processing, transferred data can be stored to on-chip memory (e.g., parallel processor memory 2122) during processing, then written back to system memory.

[0355] In at least one embodiment, when parallel processing unit 2102 is used to perform graphics processing, scheduler 2110 can be configured to divide a processing workload into approximately equal sized tasks, to better enable distribution of graphics processing operations to multiple clusters 2114A-2114N of processing cluster array 2112. In at least one embodiment, portions of processing cluster array 2112 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations, to produce a rendered image for display. In at least one embodiment, intermediate data produced by one or more of clusters 2114A-2114N may be stored in buffers to allow intermediate data to be transmitted between clusters 2114A-2114N for further processing.

[0356] In at least one embodiment, processing cluster array 2112 can receive processing tasks to be executed via scheduler 2110, which receives commands defining processing tasks from front end 2108. In at least one embodiment, processing tasks can include indices of data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how data is to be processed (e.g., what program is to be executed). In at least one embodiment, scheduler 2110 may be configured to fetch indices corresponding to tasks or may receive indices from front end 2108. In at least one embodiment, front end 2108 can be configured to ensure processing cluster array 2112 is configured to a valid state before a workload specified by incoming command buffers (e.g., batch-buffers, push buffers, etc.) is initiated.

[0357] In at least one embodiment, each of one or more instances of parallel processing unit 2102 can couple with parallel processor memory 2122. In at least one embodiment, parallel processor memory 2122 can be accessed via memory crossbar 2116, which can receive memory requests from processing cluster array 2112 as well as I / O unit 2104. In at least one embodiment, memory crossbar 2116 can access parallel processor memory 2122 via a memory interface 2118. In at least one embodiment, memory interface 2118 can include multiple partition units (e.g., partition unit 2120A, partition unit 2120B, through partition unit 2120N) that can each couple to a portion (e.g., memory unit) of parallel processor memory 2122. In at least one embodiment, a number of partition units 2120A-2120N is configured to be equal to a number of memory units, such that a first partition unit 2120A has a corresponding first memory unit 2124A, a second partition unit 2120B has a corresponding memory unit 2124B, and an Nth partition unit 2120N has a corresponding Nth memory unit 2124N. In at least one embodiment, a number of partition units 2120A-2120N may not be equal to a number of memory devices.

[0358] In at least one embodiment, memory units 2124A-2124N can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 2124A-2124N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, render targets, such as frame buffers or texture maps may be stored across memory units 2124A-2124N, allowing partition units 2120A-2120N to write portions of each render target in parallel to efficiently use available bandwidth of parallel processor memory 2122. In at least one embodiment, a local instance of parallel processor memory 2122 may be excluded in favor of a unified memory design that utilizes system memory in conjunction with local cache memory.

[0359] In at least one embodiment, any one of clusters 2114A-2114N of processing cluster array 2112 can process data that will be written to any of memory units 2124A-2124N within parallel processor memory 2122. In at least one embodiment, memory crossbar 2116 can be configured to transfer an output of each cluster 2114A-2114N to any partition unit 2120A-2120N or to another cluster 2114A-2114N, which can perform additional processing operations on an output. In at least one embodiment, each cluster 2114A-2114N can communicate with memory interface 2118 through memory crossbar 2116 to read from or write to various external memory devices. In at least one embodiment, memory crossbar 2116 has a connection to memory interface 2118 to communicate with I / O unit 2104, as well as a connection to a local instance of parallel processor memory 2122, enabling processing units within different processing clusters 2114A-2114N to communicate with system memory or other memory that is not local to parallel processing unit 2102. In at least one embodiment, memory crossbar 2116 can use virtual channels to separate traffic streams between clusters 2114A-2114N and partition units 2120A-2120N.

[0360] In at least one embodiment, multiple instances of parallel processing unit 2102 can be provided on a single add-in card, or multiple add-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 2102 can be configured to inter-operate even if different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 2102 can include higher precision floating point units relative to other instances. In at least one embodiment, systems incorporating one or more instances of parallel processing unit 2102 or parallel processor 2100 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0361] FIG. 21B is a block diagram of a partition unit 2120 according to at least one embodiment. In at least one embodiment, partition unit 2120 is an instance of one of partition units 2120A-2120N of FIG. 21A. In at least one embodiment, partition unit 2120 includes an L2 cache 2121, a frame buffer interface 2125, and a ROP 2126 (raster operations unit). L2 cache 2121 is a read / write cache that is configured to perform load and store operations received from memory crossbar 2116 and ROP 2126. In at least one embodiment, read misses and urgent write-back requests are output by L2 cache 2121 to frame buffer interface 2125 for processing. In at least one embodiment, updates can also be sent to a frame buffer via frame buffer interface 2125 for processing. In at least one embodiment, frame buffer interface 2125 interfaces with one of memory units in parallel processor memory, such as memory units 2124A-2124N of FIG. 21 (e.g., within parallel processor memory 2122).

[0362] In at least one embodiment, ROP 2126 is a processing unit that performs raster operations such as stencil, z test, blending, and like. In at least one embodiment, ROP 2126 then outputs processed graphics data that is stored in graphics memory. In at least one embodiment, ROP 2126 includes compression logic to compress depth or color data that is written to memory and decompress depth or color data that is read from memory. In at least one embodiment, compression logic can be lossless compression logic that makes use of one or more of multiple compression algorithms. In at least one embodiment, type of compression that is performed by ROP 2126 can vary based on statistical characteristics of data to be compressed. For example, in at least one embodiment, delta color compression is performed on depth and color data on a per-tile basis.

[0363] In In at least one embodiment, ROP 2126 is included within each processing cluster (e.g., cluster 2114A-2114N of FIG. 21) instead of within partition unit 2120. In at least one embodiment, read and write requests for pixel data are transmitted over memory crossbar 2116 instead of pixel fragment data. In at least one embodiment, processed graphics data may be displayed on a display device, such as one of one or more display device(s) 2010 of FIG. 20, routed for further processing by processor(s) 2002, or routed for further processing by one of processing entities within parallel processor 2100 of FIG. 21A.

[0364] FIG. 21C is a block diagram of a processing cluster 2114 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is an instance of one of processing clusters 2114A-2114N of FIG. 21. In at least one embodiment, processing cluster 2114 can be configured to execute many threads in parallel, where term “thread” refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single-instruction, multiple-data (SIMD) instruction issue techniques are used to support parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single-instruction, multiple-thread (SIMT) techniques are used to support parallel execution of a large number of generally synchronized threads, using a common instruction unit configured to issue instructions to a set of processing engines within each one of processing clusters.

[0365] In at least one embodiment, operation of processing cluster 2114 can be controlled via a pipeline manager 2132 that distributes processing tasks to SIMT parallel processors. In at least one embodiment, pipeline manager 2132 receives instructions from scheduler 2110 of FIG. 21 and manages execution of those instructions via a graphics multiprocessor 2134 and / or a texture unit 2136. In at least one embodiment, graphics multiprocessor 2134 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of differing architectures may be included within processing cluster 2114. In at least one embodiment, one or more instances of graphics multiprocessor 2134 can be included within a processing cluster 2114. In at least one embodiment, graphics multiprocessor 2134 can process data and a data crossbar 2140 can be used to distribute processed data to one of multiple possible destinations, including other shader units. In at least one embodiment, pipeline manager 2132 can facilitate distribution of processed data by specifying destinations for processed data to be distributed via data crossbar 2140.

[0366] In at least one embodiment, each graphics multiprocessor 2134 within processing cluster 2114 can include an identical set of functional execution logic (e.g., arithmetic logic units, load-store units, etc.). In at least one embodiment, functional execution logic can be configured in a pipelined manner in which new instructions can be issued before previous instructions are complete. In at least one embodiment, functional execution logic supports a variety of operations including integer and floating point arithmetic, comparison operations, Boolean operations, bit-shifting, and computation of various algebraic functions. In at least one embodiment, same functional-unit hardware can be leveraged to perform different operations and any combination of functional units may be present.

[0367] In at least one embodiment, instructions transmitted to processing cluster 2114 constitute a thread. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, thread group executes a program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within a graphics multiprocessor 2134. In at least one embodiment, a thread group may include fewer threads than a number of processing engines within graphics multiprocessor 2134. In at least one embodiment, when a thread group includes fewer threads than a number of processing engines, one or more of processing engines may be idle during cycles in which that thread group is being processed. In at least one embodiment, a thread group may also include more threads than a number of processing engines within graphics multiprocessor 2134. In at least one embodiment, when a thread group includes more threads than number of processing engines within graphics multiprocessor 2134, processing can be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed concurrently on a graphics multiprocessor 2134.

[0368] In at least one embodiment, graphics multiprocessor 2134 includes an internal cache memory to perform load and store operations. In at least one embodiment, graphics multiprocessor 2134 can forego an internal cache and use a cache memory (e.g., L1 cache 2148) within processing cluster 2114. In at least one embodiment, each graphics multiprocessor 2134 also has access to L2 caches within partition units (e.g., partition units 2120A-2120N of FIG. 21) that are shared among all processing clusters 2114 and may be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 2134 may also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 2102 may be used as global memory. In at least one embodiment, processing cluster 2114 includes multiple instances of graphics multiprocessor 2134 can share common instructions and data, which may be stored in L1 cache 2148.

[0369] In at least one embodiment, each processing cluster 2114 may include an MMU 2145 (memory management unit) that is configured to map virtual addresses into physical addresses. In at least one embodiment, one or more instances of MMU 2145 may reside within memory interface 2118 of FIG. 21. In at least one embodiment, MMU 2145 includes a set of page table entries (PTEs) used to map a virtual address to a physical address of a tile and optionally a cache line index. In at least one embodiment, MMU 2145 may include address translation lookaside buffers (TLB) or caches that may reside within graphics multiprocessor 2134 or L1 cache or processing cluster 2114. In at least one embodiment, physical address is processed to distribute surface data access locality to allow efficient request interleaving among partition units. In at least one embodiment, cache line index may be used to determine whether a request for a cache line is a hit or miss.

[0370] In at least one embodiment, a processing cluster 2114 may be configured such that each graphics multiprocessor 2134 is coupled to a texture unit 2136 for performing texture mapping operations, e.g., determining texture sample positions, reading texture data, and filtering texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within graphics multiprocessor 2134 and is fetched from an L2 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor 2134 outputs processed tasks to data crossbar 2140 to provide processed task to another processing cluster 2114 for further processing or to store processed task in an L2 cache, local parallel processor memory, or system memory via memory crossbar 2116. In at least one embodiment, preROP 2142 (pre-raster operations unit) is configured to receive data from graphics multiprocessor 2134, direct data to ROP units, which may be located with partition units as described herein (e.g., partition units 2120A-2120N of FIG. 21). In at least one embodiment, PreROP 2142 unit can perform optimizations for color blending, organize pixel color data, and perform address translations.

[0371] In at least one embodiment, processor 2100 is included in computer environment 100 from FIG. 1 and includes a processor (e.g., processor 800) comprising one or more circuits to perform an API to perform one or more processes 300-500. In at least one embodiment, processor 2100 performs one or more processes 300-500 as shown in FIGS. 3-5. In at least one embodiment processor 2100 includes one or more components disclosed in FIGS. 1-9 to perform its operations.

[0372] FIG. 21D shows a graphics multiprocessor 2134 according to at least one embodiment. In at least one embodiment, graphics multiprocessor 2134 couples with pipeline manager 2132 of processing cluster 2114. In at least one embodiment, graphics multiprocessor 2134 has an execution pipeline including but not limited to an instruction cache 2152, an instruction unit 2154, an address mapping unit 2156, a register file 2158, one or more general purpose graphics processing unit (GPGPU) cores 2162, and one or more load / store units 2166. GPGPU cores 2162 and load / store units 2166 are coupled with cache memory 2172 and shared memory 2170 via a memory and cache interconnect 2168.

[0373] In at least one embodiment, instruction cache 2152 receives a stream of instructions to execute from pipeline manager 2132. In at least one embodiment, instructions are cached in instruction cache 2152 and dispatched for execution by instruction unit 2154. In at least one embodiment, instruction unit 2154 can dispatch instructions as thread groups (e.g., warps), with each thread of thread group assigned to a different execution unit within GPGPU core 2162. In at least one embodiment, an instruction can access any of a local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 2156 can be used to translate addresses in a unified address space into a distinct memory address that can be accessed by load / store units 2166.

[0374] In at least one embodiment, register file 2158 provides a set of registers for functional units of graphics multiprocessor 2134. In at least one embodiment, register file 2158 provides temporary storage for operands connected to data paths of functional units (e.g., GPGPU cores 2162, load / store units 2166) of graphics multiprocessor 2134. In at least one embodiment, register file 2158 is divided between each of functional units such that each functional unit is allocated a dedicated portion of register file 2158. In at least one embodiment, register file 2158 is divided between different warps being executed by graphics multiprocessor 2134.

[0375] In at least one embodiment, GPGPU cores 2162 can each include floating point units (FPUs) and / or integer arithmetic logic units (ALUs) that are used to execute instructions of graphics multiprocessor 2134. GPGPU cores 2162 can be similar in architecture or can differ in architecture. In at least one embodiment, a first portion of GPGPU cores 2162 include a single precision FPU and an integer ALU while a second portion of GPGPU cores include a double precision FPU. In at least one embodiment, FPUs can implement IEEE 754-2008 standard for floating point arithmetic or enable variable precision floating point arithmetic. In at least one embodiment, graphics multiprocessor 2134 can additionally include one or more fixed function or special function units to perform specific functions such as copy rectangle or pixel blending operations. In at least one embodiment one or more of GPGPU cores can also include fixed or special function logic.

[0376] In at least one embodiment, GPGPU cores 2162 include SIMD logic capable of performing a single instruction on multiple sets of data. In at least one embodiment GPGPU cores 2162 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for GPGPU cores can be generated at compile time by a shader compiler or automatically generated when executing programs written and compiled for single program multiple data (SPMD) or SIMT architectures. In at least one embodiment, multiple threads of a program configured for an SIMT execution model can executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads that perform same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[0377] In at least one embodiment, memory and cache interconnect 2168 is an interconnect network that connects each functional unit of graphics multiprocessor 2134 to register file 2158 and to shared memory 2170. In at least one embodiment, memory and cache interconnect 2168 is a crossbar interconnect that allows load / store unit 2166 to implement load and store operations between shared memory 2170 and register file 2158. In at least one embodiment, register file 2158 can operate at a same frequency as GPGPU cores 2162, thus data transfer between GPGPU cores 2162 and register file 2158 is very low latency. In at least one embodiment, shared memory 2170 can be used to enable communication between threads that execute on functional units within graphics multiprocessor 2134. In at least one embodiment, cache memory 2172 can be used as a data cache for example, to cache texture data communicated between functional units and texture unit 2136. In at least one embodiment, shared memory 2170 can also be used as a program managed cached. In at least one embodiment, threads executing on GPGPU cores 2162 can programmatically store data within shared memory in addition to automatically cached data that is stored within cache memory 2172.

[0378] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to host / processor cores to accelerate graphics operations, machine-learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. In at least one embodiment, GPU may be communicatively coupled to host processor / cores over a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, GPU may be integrated on same package or chip as cores and communicatively coupled to cores over an internal processor bus / interconnect (i.e., internal to package or chip). In at least one embodiment, regardless of manner in which GPU is connected, processor cores may allocate work to GPU in form of sequences of commands / instructions contained in a work descriptor. In at least one embodiment, GPU then uses dedicated circuitry / logic for efficiently processing these commands / instructions.

[0379] In at least one embodiment, processor 2100 is included in computer environment 100 from FIG. 1 and includes a processor (e.g., processor 800) comprising one or more circuits to perform an API to perform one or more processes 300-500. In at least one embodiment, processor 2100 performs one or more processes 300-500 as shown in FIGS. 3-5. In at least one embodiment processor 2100 includes one or more components disclosed in FIGS. 1-9 to perform its operations.

[0380] FIG. 22 illustrates a multi-GPU computing system 2200, according to at least one embodiment. In at least one embodiment, multi-GPU computing system 2200 can include a processor 2202 coupled to multiple general purpose graphics processing units (GPGPUs) 2206A-D via a host interface switch 2204. In at least one embodiment, host interface switch 2204 is a PCI express switch device that couples processor 2202 to a PCI express bus over which processor 2202 can communicate with GPGPUs 2206A-D. GPGPUs 2206A-D can interconnect via a set of high-speed point to point GPU to GPU links 2216. In at least one embodiment, GPU to GPU links 2216 connect to each of GPGPUs 2206A-D via a dedicated GPU link. In at least one embodiment, P2P GPU links 2216 enable direct communication between each of GPGPUs 2206A-D without requiring communication over host interface bus 2204 to which processor 2202 is connected. In at least one embodiment, with GPU-to-GPU traffic directed to P2P GPU links 2216, host interface bus 2204 remains available for system memory access or to communicate with other instances of multi-GPU computing system 2200, for example, via one or more network devices. While in at least one embodiment GPGPUs 2206A-D connect to processor 2202 via host interface switch 2204, in at least one embodiment processor 2202 includes direct support for P2P GPU links 2216 and can connect directly to GPGPUs 2206A-D.

[0381] In at least one embodiment, computing system 2200 is included in computer environment 100 from FIG. 1 and includes a processor (e.g., processor 800) comprising one or more circuits to perform an API to perform one or more processes 300-500. In at least one embodiment, computing system 2200 performs one or more processes 300-500 as shown in FIGS. 3-5. In at least one embodiment computing system 2200 includes one or more components disclosed in FIGS. 1-9 to perform its operations.

[0382] FIG. 23 is a block diagram of a graphics processor 2300, according to at least one embodiment. In at least one embodiment, graphics processor 2300 includes a ring interconnect 2302, a pipeline front-end 2304, a media engine 2337, and graphics cores 2380A-2380N. In at least one embodiment, ring interconnect 2302 couples graphics processor 2300 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2300 is one of many processors integrated within a multi-core processing system.

[0383] In at least one embodiment, graphics processor 2300 receives batches of commands via ring interconnect 2302. In at least one embodiment, incoming commands are interpreted by a command streamer 2303 in pipeline front-end 2304. In at least one embodiment, graphics processor 2300 includes scalable execution logic to perform 3D geometry processing and media processing via graphics core(s) 2380A-2380N. In at least one embodiment, for 3D geometry processing commands, command streamer 2303 supplies commands to geometry pipeline 2336. In at least one embodiment, for at least some media processing commands, command streamer 2303 supplies commands to a video front end 2334, which couples with a media engine 2337. In at least one embodiment, media engine 2337 includes a Video Quality Engine (VQE) 2330 for video and image post-processing and a multi-format encode / decode (MFX) 2333 engine to provide hardware-accelerated media data encode and decode. In at least one embodiment, geometry pipeline 2336 and media engine 2337 each generate execution threads for thread execution resources provided by at least one graphics core 2380A.

[0384] In at least one embodiment, graphics processor 2300 includes scalable thread execution resources featuring modular cores 2380A-2380N (sometimes referred to as core slices), each having multiple sub-cores 2350A-550N, 2360A-2360N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 2300 can have any number of graphics cores 2380A through 2380N. In at least one embodiment, graphics processor 2300 includes a graphics core 2380A having at least a first sub-core 2350A and a second sub-core 2360A. In at least one embodiment, graphics processor 2300 is a low power processor with a single sub-core (e.g., 2350A). In at least one embodiment, graphics processor 2300 includes multiple graphics cores 2380A-2380N, each including a set of first sub-cores 2350A-2350N and a set of second sub-cores 2360A-2360N. In at least one embodiment, each sub-core in first sub-cores 2350A-2350N includes at least a first set of execution units 2352A-2352N and media / texture samplers 2354A-2354N. In at least one embodiment, each sub-core in second sub-cores 2360A-2360N includes at least a second set of execution units 2362A-2362N and samplers 2364A-2364N. In at least one embodiment, each sub-core 2350A-2350N, 2360A-2360N shares a set of shared resources 2370A-2370N. In at least one embodiment, shared resources include shared cache memory and pixel operation logic.

[0385] In at least one embodiment, graphics processor 2300 is included in computer environment 100 from FIG. 1 and includes a processor (e.g., processor 800) comprising one or more circuits to perform an API to perform one or more processes 300-500. In at least one embodiment, graphics processor 2300 performs one or more processes 300-500 as shown in FIGS. 3-5. In at least one embodiment graphics processor 2300 includes one or more components disclosed in FIGS. 1-9 to perform its operations.

[0386] FIG. 24 is a block diagram illustrating micro-architecture for a processor 2400 that may include logic circuits to perform instructions, according to at least one embodiment. In at least one embodiment, processor 2400 may perform instructions, including x86 instructions, ARM instructions, specialized instructions for application-specific integrated circuits (ASICs), etc. In at least one embodiment, processor 2410 may include registers to store packed data, such as 64-bit wide MMX™ registers in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, Calif. In at least one embodiment, MMX registers, available in both integer and floating point forms, may operate with packed data elements that accompany single instruction, multiple data (“SIMD”) and streaming SIMD extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers relating to SSE2, SSE3, SSE4, AVX, or beyond (referred to generically as “SSEx”) technology may hold such packed data operands. In at least one embodiment, processors 2410 may perform instructions to accelerate machine learning or deep learning algorithms, training, or inferencing.

[0387] In at least one embodiment, processor 2400 includes an in-order front end (“front end”) 2401 to fetch instructions to be executed and prepare instructions to be used later in processor pipeline. In at least one embodiment, front end 2401 may include several units. In at least one embodiment, an instruction prefetcher 2426 fetches instructions from memory and feeds instructions to an instruction decoder 2428 which in turn decodes or interprets instructions. For example, in at least one embodiment, instruction decoder 2428 decodes a received instruction into one or more operations called “micro-instructions” or “micro-operations” (also called “micro ops” or “uops”) that machine may execute. In at least one embodiment, instruction decoder 2428 parses instruction into an opcode and corresponding data and control fields that may be used by micro-architecture to perform operations in accordance with at least one embodiment. In at least one embodiment, a trace cache 2430 may assemble decoded uops into program ordered sequences or traces in a uop queue 2434 for execution. In at least one embodiment, when trace cache 2430 encounters a complex instruction, a microcode ROM 2432 provides uops needed to complete operation.

[0388] In at least one embodiment, some instructions may be converted into a single micro-op, whereas others need several micro-ops to complete full operation. In at least one embodiment, if more than four micro-ops are needed to complete an instruction, instruction decoder 2428 may access microcode ROM 2432 to perform instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-ops for processing at instruction decoder 2428. In at least one embodiment, an instruction may be stored within microcode ROM 2432 should a number of micro-ops be needed to accomplish operation. In at least one embodiment, trace cache 2430 refers to an entry point programmable logic array (“PLA”) to determine a correct micro-instruction pointer for reading microcode sequences to complete one or more instructions from microcode ROM 2432 in accordance with at least one embodiment. In at least one embodiment, after microcode ROM 2432 finishes sequencing micro-ops for an instruction, front end 2401 of machine may resume fetching micro-ops from trace cache 2430.

[0389] In at least one embodiment, out-of-order execution engine (“out of order engine”) 2403 may prepare instructions for execution. In at least one embodiment, out-of-order execution logic has a number of buffers to smooth out and re-order flow of instructions to optimize performance as they go down pipeline and get scheduled for execution. out-of-order execution engine 2403 includes, without limitation, an allocator / register renamer 2440, a memory uop queue 2442, an integer / floating point uop queue 2444, a memory scheduler 2446, a fast scheduler 2402, a slow / general floating point scheduler (“slow / general FP scheduler”) 2404, and a simple floating point scheduler (“simple FP scheduler”) 2406. In at least one embodiment, fast schedule 2402, slow / general floating point scheduler 2404, and simple floating point scheduler 2406 are also collectively referred to herein as “uop schedulers 2402, 2404, 2406.” In at least one embodiment, allocator / register renamer 2440 allocates machine buffers and resources that each uop needs in order to execute. In at least one embodiment, allocator / register renamer 2440 renames logic registers onto entries in a register file. In at least one embodiment, allocator / register renamer 2440 also allocates an entry for each uop in one of two uop queues, memory uop queue 2442 for memory operations and integer / floating point uop queue 2444 for non-memory operations, in front of memory scheduler 2446 and uop schedulers 2402, 2404, 2406. In at least one embodiment, uop schedulers 2402, 2404, 2406, determine when a uop is ready to execute based on readiness of their dependent input register operand sources and availability of execution resources uops need to complete their operation. In at least one embodiment, fast scheduler 2402 of at least one embodiment may schedule on each half of main clock cycle while slow / general floating point scheduler 2404 and simple floating point scheduler 2406 may schedule once per main processor clock cycle. In at least one embodiment, uop schedulers 2402, 2404, 2406 arbitrate for dispatch ports to schedule uops for execution.

[0390] In at least one embodiment, execution block b11 includes, without limitation, an integer register file / bypass network 2408, a floating point register file / bypass network (“FP register file / bypass network”) 2410, address generation units (“AGUs”) 2412 and 2414, fast Arithmetic Logic Units (ALUs) (“fast ALUs”) 2416 and 2418, a slow Arithmetic Logic Unit (“slow ALU”) 2420, a floating point ALU (“FP”) 2422, and a floating point move unit (“FP move”) 2424. In at least one embodiment, integer register file / bypass network 2408 and floating point register file / bypass network 2410 are also referred to herein as “register files 2408, 2410.” In at least one embodiment, AGUSs 2412 and 2414, fast ALUs 2416 and 2418, slow ALU 2420, floating point ALU 2422, and floating point move unit 2424 are also referred to herein as “execution units 2412, 2414, 2416, 2418, 2420, 2422, and 2424.” In at least one embodiment, execution block b11 may include, without limitation, any number (including zero) and type of register files, bypass networks, address generation units, and execution units, in any combination.

[0391] In at least one embodiment, register files 2408, 2410 may be arranged between uop schedulers 2402, 2404, 2406, and execution units 2412, 2414, 2416, 2418, 2420, 2422, and 2424. In at least one embodiment, integer register file / bypass network 2408 performs integer operations. In at least one embodiment, floating point register file / bypass network 2410 performs floating point operations. In at least one embodiment, each of register files 2408, 2410 may include, without limitation, a bypass network that may bypass or forward just completed results that have not yet been written into register file to new dependent uops. In at least one embodiment, register files 2408, 2410 may communicate data with each other. In at least one embodiment, integer register file / bypass network 2408 may include, without limitation, two separate register files, one register file for low-order thirty-two bits of data and a second register file for high order thirty-two bits of data. In at least one embodiment, floating point register file / bypass network 2410 may include, without limitation, 128-bit wide entries because floating point instructions typically have operands from 64 to 128 bits in width.

[0392] In at least one embodiment, execution units 2412, 2414, 2416, 2418, 2420, 2422, 2424 may execute instructions. In at least one embodiment, register files 2408, 2410 store integer and floating point data operand values that micro-instructions need to execute. In at least one embodiment, processor 2400 may include, without limitation, any number and combination of execution units 2412, 2414, 2416, 2418, 2420, 2422, 2424. In at least one embodiment, floating point ALU 2422 and floating point move unit 2424, may execute floating point, MMX, SIMD, AVX and SSE, or other operations, including specialized machine learning instructions. In at least one embodiment, floating point ALU 2422 may include, without limitation, a 64-bit by 64-bit floating point divider to execute divide, square root, and remainder micro ops. In at least one embodiment, instructions involving a floating point value may be handled with floating point hardware. In at least one embodiment, ALU operations may be passed to fast ALUs 2416, 2418. In at least one embodiment, fast ALUS 2416, 2418 may execute fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to slow ALU 2420 as slow ALU 2420 may include, without limitation, integer execution hardware for long-latency type of operations, such as a multiplier, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations may be executed by AGUS 2412, 2414. In at least one embodiment, fast ALU 2416, fast ALU 2418, and slow ALU 2420 may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2416, fast ALU 2418, and slow ALU 2420 may be implemented to support a variety of data bit sizes including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, floating point ALU 2422 and floating point move unit 2424 may be implemented to support a range of operands having bits of various widths. In at least one embodiment, floating point ALU 2422 and floating point move unit 2424 may operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0393] In at least one embodiment, uop schedulers 2402, 2404, 2406, dispatch dependent operations before parent load has finished executing. In at least one embodiment, as uops may be speculatively scheduled and executed in processor 2400, processor 2400 may also include logic to handle memory misses. In at least one embodiment, if a data load misses in data cache, there may be dependent operations in flight in pipeline that have left scheduler with temporarily incorrect data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, dependent operations might need to be replayed and independent ones may be allowed to complete. In at least one embodiment, schedulers and replay mechanism of at least one embodiment of a processor may also be designed to catch instruction sequences for text string comparison operations.

[0394] In at least one embodiment, term “registers” may refer to on-board processor storage locations that may be used as part of instructions to identify operands. In at least one embodiment, registers may be those that may be usable from outside of processor (from a programmer's perspective). In at least one embodiment, registers might not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform functions described herein. In at least one embodiment, registers described herein may be implemented by circuitry within a processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, integer registers store 32-bit integer data. A register file of at least one embodiment also contains eight multimedia SIMD registers for packed data.

[0395] In at least one embodiment, processor 2400 is included in computer environment 100 from FIG. 1 and includes a processor (e.g., processor 800) comprising one or more circuits to perform an API to perform one or more processes 300-500. In at least one embodiment, processor 2400 performs one or more processes 300-500 as shown in FIGS. 3-5. In at least one embodiment processor 2400 includes one or more components disclosed in FIGS. 1-9 to perform its operations.

[0396] FIG. 25 is a block diagram of a processing system, according to at least one embodiment. In at least one embodiment, system 2500 includes one or more processors 2502 and one or more graphics processors 2508, and may be a single processor desktop system, a multiprocessor workstation system, or a server system having a large number of processors 2502 or processor cores 2507. In at least one embodiment, system 2500 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0397] In at least one embodiment, system 2500 can include, or be incorporated within a server-based gaming platform, a game console, including a game and media console, a mobile gaming console, a handheld game console, or an online game console. In at least one embodiment, system 2500 is a mobile phone, smart phone, tablet computing device or mobile Internet device. In at least one embodiment, processing system 2500 can also include, couple with, or be integrated within a wearable device, such as a smart watch wearable device, smart eyewear device, augmented reality device, or virtual reality device. In at least one embodiment, processing system 2500 is a television or set top box device having one or more processors 2502 and a graphical interface generated by one or more graphics processors 2508.

[0398] In at least one embodiment, one or more processors 2502 each include one or more processor cores 2507 to process instructions which, when executed, perform operations for system and user software. In at least one embodiment, each of one or more processor cores 2507 is configured to process a specific instruction set 2509. In at least one embodiment, instruction set 2509 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computing via a Very Long Instruction Word (VLIW). In at least one embodiment, processor cores 2507 may each process a different instruction set 2509, which may include instructions to facilitate emulation of other instruction sets. In at least one embodiment, processor core 2507 may also include other processing devices, such a Digital Signal Processor (DSP).

[0399] In at least one embodiment, processor 2502 includes cache memory 2504. In at least one embodiment, processor 2502 can have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among various components of processor 2502. In at least one embodiment, processor 2502 also uses an external cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC)) (not shown), which may be shared among processor cores 2507 using known cache coherency techniques. In at least one embodiment, register file 2506 is additionally included in processor 2502 which may include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and an instruction pointer register). In at least one embodiment, register file 2506 may include general-purpose registers or other registers.

[0400] In at least one embodiment, one or more processor(s) 2502 are coupled with one or more interface bus(es) 2510 to transmit communication signals such as address, data, or control signals between processor 2502 and other components in system 2500. In at least one embodiment interface bus 2510, in one embodiment, can be a processor bus, such as a version of a Direct Media Interface (DMI) bus. In at least one embodiment, interface 2510 is not limited to a DMI bus, and may include one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express), memory busses, or other types of interface busses. In at least one embodiment processor(s) 2502 include an integrated memory controller 2516 and a platform controller hub 2530. In at least one embodiment, memory controller 2516 facilitates communication between a memory device and other components of system 2500, while platform controller hub (PCH) 2530 provides connections to I / O devices via a local I / O bus.

[0401] In at least one embodiment, memory device 2520 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as process memory. In at least one embodiment memory device 2520 can operate as system memory for system 2500, to store data 2522 and instructions 2521 for use when one or more processors 2502 executes an application or process. In at least one embodiment, memory controller 2516 also couples with an optional external graphics processor 2512, which may communicate with one or more graphics processors 2508 in processors 2502 to perform graphics and media operations. In at least one embodiment, a display device 2511 can connect to processor(s) 2502. In at least one embodiment display device 2511 can include one or more of an internal display device, as in a mobile electronic device or a laptop device or an external display device attached via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, display device 2511 can include a head mounted display (HMD) such as a stereoscopic display device for use in virtual reality (VR) applications or augmented reality (AR) applications.

[0402] In at least one embodiment, platform controller hub 2530 enables peripherals to connect to memory device 2520 and processor 2502 via a high-speed I / O bus. In at least one embodiment, I / O peripherals include, but are not limited to, an audio controller 2546, a network controller 2534, a firmware interface 2528, a wireless transceiver 2526, touch sensors 2525, a data storage device 2524 (e.g., hard disk drive, flash memory, etc.). In at least one embodiment, data storage device 2524 can connect via a storage interface (e.g., SATA) or via a peripheral bus, such as a Peripheral Component Interconnect bus (e.g., PCI, PCI Express). In at least one embodiment, touch sensors 2525 can include touch screen sensors, pressure sensors, or fingerprint sensors. In at least one embodiment, wireless transceiver 2526 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, firmware interface 2528 enables communication with system firmware, and can be, for example, a unified extensible firmware interface (UEFI). In at least one embodiment, network controller 2534 can enable a network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) couples with interface bus 2510. In at least one embodiment, audio controller 2546 is a multi-channel high definition audio controller. In at least one embodiment, system 2500 includes an optional legacy I / O controller 2540 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to system. In at least one embodiment, platform controller hub 2530 can also connect to one or more Universal Serial Bus (USB) controllers 2542 connect input devices, such as keyboard and mouse 2543 combinations, a camera 2544, or other USB input devices.

[0403] In at least one embodiment, an instance of memory controller 2516 and platform controller hub 2530 may be integrated into a discreet external graphics processor, such as external graphics processor 2512. In at least one embodiment, platform controller hub 2530 and / or memory controller 2516 may be external to one or more processor(s) 2502. For example, in at least one embodiment, system 2500 can include an external memory controller 2516 and platform controller hub 2530, which may be configured as a memory controller hub and peripheral controller hub within a system chipset that is in communication with processor(s) 2502.

[0404] In at least one embodiment, system 2500 is included in computer environment 100 from FIG. 1 and includes a processor (e.g., processor 800) comprising one or more circuits to perform an API to perform one or more processes 300-500. In at least one embodiment, system 2500 performs one or more processes 300-500 as shown in FIGS. 3-5. In at least one embodiment system 2500 includes one or more components disclosed in FIGS. 1-9 to perform its operations.

[0405] FIG. 26 is a block diagram of a processor 2600 having one or more processor cores 2602A-2602N, an integrated memory controller 2614, and an integrated graphics processor 2608, according to at least one embodiment. In at least one embodiment, processor 2600 can include additional cores up to and including additional core 2602N represented by dashed lined boxes. In at least one embodiment, each of processor cores 2602A-2602N includes one or more internal cache units 2604A-2604N. In at least one embodiment, each processor core also has access to one or more shared cached units 2606.

[0406] In at least one embodiment, internal cache units 2604A-2604N and shared cache units 2606 represent a cache memory hierarchy within processor 2600. In at least one embodiment, cache memory units 2604A-2604N may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, where a highest level of cache before external memory is classified as an LLC. In at least one embodiment, cache coherency logic maintains coherency between various cache units 2606 and 2604A-2604N.

[0407] In at least one embodiment, processor 2600 may also include a set of one or more bus controller units 2616 and a system agent core 2610. In at least one embodiment, one or more bus controller units 2616 manage a set of peripheral buses, such as one or more PCI or PCI express busses. In at least one embodiment, system agent core 2610 provides management functionality for various processor components. In at least one embodiment, system agent core 2610 includes one or more integrated memory controllers 2614 to manage access to various external memory devices (not shown).

[0408] In at least one embodiment, one or more of proc...

Claims

1. One or more processors, comprising:circuitry to cause one or more network addresses of one or more first distributed units (DUs) used by one or more Radio Units (RUs) to be reassigned to one or more second DUs as a result of utilization information of the first one or more DUs indicating that utilization of the one or more first DUs exceed a threshold, wherein the one or more network addresses used by the one or more RUs include one or more placeholder network addresses to communicate with the one or more first DUs.

2. The one or more processors of claim 1, wherein communications using the one or more placeholder network addresses are mapped, via a translation lookup table, to respective actual network addresses of the one or more first distributed units (DUs) or the one or more second DUs, and a mapping in the translation lookup table is updated to reassign one or more communications from a first DU to a second DU.

3. The one or more processors of claim 1, wherein a lookup table is to be queried when the one or more RUs communicate with the one or more first DUs or the one or more second DUs.

4. The one or more processors of claim 1, wherein the circuitry is to cause a network switch to query a lookup table and cause the one or more network addresses of the one or more first DUs to be reassigned to the one or more second DUs based, at least in part, on one or more media access control (MAC) addresses of the one or more first DUs.

5. The one or more processors of claim 1, wherein the circuitry is to cause a network switch to perform software to monitor the utilization information of the one or more first DUs.

6. The one or more processors of claim 1, wherein the threshold is based, at least in part, on one or more neural networks.

7. The one or more processors of claim 1, wherein the circuitry is to cause the utilization of the one or more first DUs exceeding the threshold to be reported to a service management and orchestration (SMO) platform.

8. A system, comprising:one or more processors to cause one or more network addresses of one or more first distributed units (DUs) used by one or more Radio Units (RUs) to be reassigned to one or more second DUs as a result of utilization information of the one or more first DUs indicating that utilization of the one or more first DUs exceed a threshold, wherein the one or more network addresses used by the one or more RUs include one or more placeholder network addresses to communicate with the one or more first DUs.

9. The system of claim 8, wherein communications using the one or more placeholder network addresses are mapped, via a translation lookup table, to respective actual network addresses of the one or more first DUs or the one or more second DUs, and a mapping in the translation lookup table is updated to reassign one or more communications from a first DU to a second DU.

10. The system of claim 8, wherein a lookup table is to be queried when the one or more RUs communicate with the one or more first DUs or the one or more second DUs.

11. The system of claim 8, wherein the one or more processors are to cause a network switch to query a lookup table and to cause the one or more network addresses of the one or more first DUs to be reassigned to the one or more second DUs based, at least in part, on one or more media access control (MAC) addresses of the one or more first DUs.

12. The system of claim 8, wherein the one or more processors are to cause a network switch to perform software to monitor the utilization information of the one or more first DUs.

13. The system of claim 8, wherein the threshold is to be based, at least in part, on using one or more neural networks.

14. The system of claim 8, wherein the one or more processors are to cause the utilization of the one or more first DUs exceeding the threshold to be reported to a service management and orchestration (SMO) platform.

15. A method, comprising:causing one or more network addresses of one or more first distributed units (DUs) used by one or more Radio Units (RUs) to be reassigned to one or more second DUs as a result of utilization information of the one or more first DUs indicating that utilization of the one or more first DUs exceeds a threshold, wherein the one or more network addresses used by the one or more RUs include one or more placeholder network addresses to communicate with the one or more first DUs.

16. The method of claim 15, wherein communications using the one or more placeholder network addresses are mapped, via a translation lookup table, to respective actual network addresses of the one or more first DUs or the one or more second DUs, and a mapping in the translation lookup table is updated to reassign one or more communications from a first DU to a second DU.

17. The method of claim 15, wherein a lookup table is to be queried when the one or more RUs communicate with the one or more first DUs or the one or more second DUs.

18. The method of claim 15, further comprising causing a network switch to query a lookup table and to cause the one or more network addresses of the one or more first DUs to be reassigned to the one or more second DUs based, at least in part, on one or more media access control (MAC) addresses of the one or more first DUs.

19. The method of claim 15, further comprising causing network switch to perform software to monitor the utilization information of the one or more first DUs, wherein one or more processors are to cause network switch to perform software to monitor the utilization information of the one or more first DUs.

20. The method of claim 15, further comprising causing the utilization of the one or more first DUs exceeding the threshold to be reported to a service management and orchestration (SMO) platform.

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