Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises a substrate and a driver circuit layer disposed on the substrate. The substrate comprises a display region (100) and a non-display region (200). The driver circuit layer comprises a pixel driver circuit (PE) located in the display region (100) as well as a gate driver circuit and at least one initial power supply line which are located in the non-display region (200). At least a portion of the initial power supply line extends in a first direction (D1). The gate driver circuit is configured to provide a driving signal to the pixel driver circuit (PE). The initial power supply line is configured to provide an initial signal to the pixel driver circuit (PE). The orthographic projection of the at least one initial power supply line on the substrate at least partially overlaps with the orthographic projection of the gate driver circuit on the substrate.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, the present disclosure provides a display substrate, comprising: a base and a driving circuit layer disposed on the base, wherein the base comprises: a display area and a non-display area, the driving circuit layer comprising: a pixel driving circuit located in the display area, a gate driving circuit located in the non-display area, and at least one initial power supply line, wherein at least a portion of the initial power supply line extends along a first direction;

[0006] The gate driving circuit is configured to provide a driving signal to the pixel driving circuit, and the initial power supply line is configured to provide an initial signal to the pixel driving circuit;

[0007] An orthographic projection of at least one of the initial power supply lines on the substrate at least partially overlaps with an orthographic projection of the gate driving circuit on the substrate.

[0008] In an exemplary embodiment, the gate driving circuit includes: a plurality of driving circuits arranged along a second direction, the first direction intersecting the second direction;

[0009] An orthographic projection of at least one of the initial power supply lines on the substrate at least partially overlaps with an orthographic projection of a driving circuit close to the display area among the plurality of driving circuits on the substrate.

[0010] In an exemplary embodiment, the pixel driving circuit includes: a light emitting transistor and a write transistor, and the plurality of driving circuits include: a light emitting driving circuit and a scan driving circuit, the light emitting driving circuit being electrically connected to the light emitting transistor, the scan driving circuit being electrically connected to the write transistor, and the scan driving circuit being located on a side of the light emitting driving circuit close to the display area;

[0011] An orthographic projection of at least one initial power supply line on the substrate at least partially overlaps with an orthographic projection of the scan driving circuit on the substrate.

[0012] In an exemplary embodiment, the pixel driving circuit includes: a light-emitting transistor, a write transistor, and a control transistor; the plurality of driving circuits include: a light-emitting driving circuit, a scan driving circuit, and a control driving circuit; the light-emitting driving circuit is electrically connected to the light-emitting transistor, the scan driving circuit is electrically connected to the write transistor, and the control driving circuit is electrically connected to the control transistor; the write transistor and the control transistor are of opposite transistor types; the light-emitting driving circuit and the control driving circuit are located on a side of the scan driving circuit away from the display area;

[0013] An orthographic projection of at least one of the initial power supply lines on the substrate at least partially overlaps with an orthographic projection of the scan driving circuit on the substrate.

[0014] In an exemplary embodiment, the at least one initial power supply line includes: a first initial power supply line to an Nth initial power supply line, where N is a positive integer greater than or equal to 1;

[0015] When N is greater than or equal to 2, N initial power supply lines are arranged along the second direction, and the orthographic projections of K adjacent initial power supply lines away from the display area on the substrate at least partially overlap with the orthographic projection of the scan drive circuit on the substrate, and K is a positive integer less than or equal to N.

[0016] In an exemplary embodiment, the driving circuit layer further includes: a first clock signal line, a second clock signal line, a first initial signal line, a first power line, and a second power line located in the non-display area, the first clock signal line, the second clock signal line, the first initial signal line, the first power line, and the second power line extending at least partially along the first direction;

[0017] The scan driving circuit is electrically connected to the first clock signal line, the second clock signal line, the first power line, the second power line and the first initial signal line respectively;

[0018] The second clock signal line is located on the side of the first clock signal line away from the display area, the second power line is located on the side of the first clock signal line close to the display area, the first initial signal line is located on the side of the second power line close to the display area, the first power line is located on the side of the first initial signal line close to the display area, and the at least one initial power supply line is located on the side of the first power line close to the display area.

[0019] In an exemplary embodiment, the driving circuit layer further includes: a second initial signal line located in the non-display area, the second initial signal line at least partially extending along the first direction;

[0020] The light emitting driving circuit is electrically connected to the second initial signal line, and the second initial signal line is located between the second power line and the first initial signal line.

[0021] In an exemplary embodiment, the driving circuit layer further includes: a first output signal line and a second output signal line located in the non-display area, the first output signal line and the second output signal line at least partially extending along the second direction;

[0022] The first output signal line is located on a side of the scan driving circuit close to the display area and is electrically connected to the scan driving circuit and the pixel driving circuit respectively;

[0023] The second output signal line passes through the scan driving circuit and is electrically connected to the pixel driving circuit and one of the light emitting driving circuit and the control driving circuit.

[0024] In an exemplary embodiment, the driving circuit layer further includes: a first output connection line and a second output connection line located in the display area and the non-display area, the first output connection line and the second output connection line at least partially extending along the second direction;

[0025] The first output connection line is electrically connected to the first output signal line and the pixel driving circuit respectively;

[0026] The second output connection line is electrically connected to the second output signal line and the pixel driving circuit respectively.

[0027] In an exemplary embodiment, when N=2, the driving circuit layer further includes: a third output connection line and a fourth output connection line, the third output connection line and the fourth output connection line at least partially extending along the second direction;

[0028] The third output connection line is electrically connected to the first initial power supply line and the pixel driving circuit respectively;

[0029] The fourth output connection line is electrically connected to the second initial power supply line and the pixel driving circuit respectively.

[0030] In an exemplary embodiment, the boundary of the display area includes an arc-shaped boundary, and the non-display area outside the arc-shaped boundary is called a rounded corner area;

[0031] The scan driving circuit includes: a plurality of scan shift registers and a plurality of virtual scan shift registers, the plurality of scan shift registers are cascaded, and the plurality of virtual scan shift registers are interspersed between the plurality of scan shift registers;

[0032] The plurality of dummy scan shift registers are at least partially located in the rounded corner area.

[0033] In an exemplary embodiment, the scan shift register includes: a plurality of transistors and a plurality of capacitors;

[0034] The orthographic projection of the initial power supply line overlapping with the scan driving circuit on the substrate at least partially overlaps with the orthographic projections of the plurality of capacitors on the substrate.

[0035] In an exemplary embodiment, a distance between the initial power supply line overlapping with the scan driving circuit and the display area is smaller than a distance between at least one of the plurality of capacitors and the display area.

[0036] In an exemplary embodiment, the number of transistors in the dummy scan shift register is less than or equal to the number of transistors in the scan shift register;

[0037] The width of the virtual scan shift register is smaller than or equal to the width of the scan shift register.

[0038] In an exemplary embodiment, the distance between the boundary of the second clock signal line located on the side of the virtual scan shift register away from the display area and the boundary of the initial power supply line close to the display area among the at least one initial power supply line is smaller than the distance between the boundary of the second clock signal line located on the side of the scan shift register away from the display area and the boundary of the initial power supply line close to the display area among the at least one initial power supply line is.

[0039] In an exemplary embodiment, the driving circuit layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer stacked in sequence;

[0040] The semiconductor layer includes at least: an active layer of a plurality of transistors;

[0041] The first conductive layer at least includes: control electrodes of multiple transistors and first plates of multiple capacitors;

[0042] The second conductive layer at least includes: second plates of a plurality of capacitors, a first output signal line, and a third output signal line;

[0043] The third conductive layer at least includes: a second power line, a first electrode and a second electrode of at least one transistor, and a fourth output signal line;

[0044] The fourth conductive layer at least includes: a first initial signal line, a second initial signal line and a first power line.

[0045] In an exemplary embodiment, the driving circuit layer further includes: a fifth conductive layer located on a side of the fourth conductive layer away from the substrate;

[0046] The fifth conductive layer at least includes: a first output connection line, a second output connection line, a third output connection line and a fourth output connection line.

[0047] In an exemplary embodiment, the initial power supply line has a single-layer structure, and the initial power supply line is located in the fourth conductive layer.

[0048] In an exemplary embodiment, the initial power supply line includes: a first initial subsegment and a second initial subsegment connected to each other, an orthographic projection of the first initial subsegment on the substrate at least partially overlapping with an orthographic projection of the second initial subsegment on the substrate;

[0049] The first initial sub-segment is located in the third conductive layer, and the second initial sub-segment is located in the fourth conductive layer.

[0050] In an exemplary embodiment, the first clock signal line and the second clock signal line have a single-layer structure, and the first clock signal line and the second clock signal line are located in a fourth conductive layer.

[0051] In an exemplary embodiment, the clock signal line includes: a first clock sub-segment and a second clock sub-segment connected to each other, the clock signal line including the first clock signal line and the second clock signal line, an orthographic projection of the first clock sub-segment on the substrate at least partially overlapping with an orthographic projection of the second clock sub-segment on the substrate;

[0052] The first clock sub-segment is located on the third conductive layer, and the second clock sub-segment is located on the fourth conductive layer close to the substrate.

[0053] In an exemplary embodiment, the second output signal line has a single-layer structure, and the second output signal line is located in the second conductive layer.

[0054] In an exemplary embodiment, the driving circuit layer further includes: a sixth conductive layer located between the second conductive layer and the third conductive layer;

[0055] The second output signal line includes a plurality of first output sub-segments and a plurality of second output sub-segments, adjacent first output sub-segments are electrically connected via the second output sub-segments, adjacent second output sub-segments are electrically connected including the first output sub-segments, the orthographic projections of the second output sub-segments on the substrate at least partially overlap with the orthographic projections of the electrically connected first output sub-segments on the substrate, and the orthographic projections of the first output sub-segments on the substrate at least partially overlap with the orthographic projections of the electrically connected second output sub-segments on the substrate;

[0056] The first output sub-segment is located in the second conductive layer, and the second output sub-segment is located in the sixth conductive layer.

[0057] In a second aspect, the present disclosure further provides a display device comprising the above-mentioned display substrate.

[0058] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0060] FIG1A is a schematic structural diagram of a display substrate;

[0061] FIG1B is a schematic diagram showing area division of a display substrate;

[0062] FIG2 is a schematic structural diagram of another display substrate;

[0063] FIG3A is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0064] FIG3B is an operation timing diagram of the pixel driving circuit provided in FIG3A ;

[0065] FIG4A is a schematic diagram of an equivalent circuit of another pixel driving circuit;

[0066] FIG4B is an operation timing diagram of the pixel driving circuit provided in FIG4A ;

[0067] FIG5A is a first structural diagram of a display substrate provided by an embodiment of the present disclosure;

[0068] FIG5B is a partial schematic diagram of the display substrate provided in FIG5A ;

[0069] FIG6A is a second structural schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0070] FIG6B is a partial schematic diagram of the display substrate provided in FIG6A ;

[0071] FIG7A is an equivalent circuit diagram of a shift register in a display substrate;

[0072] FIG7B is a timing diagram of the shift register provided in FIG7A ;

[0073] FIG8A is an equivalent circuit diagram of a virtual scan shift register;

[0074] FIG8B is an equivalent circuit diagram of another virtual scan shift register;

[0075] FIG9A is a partial schematic diagram of a display substrate;

[0076] FIG9B is a partial schematic diagram of the display substrate in the rounded corner area provided in FIG9A ;

[0077] FIG10A is another partial schematic diagram of a display substrate;

[0078] FIG10B is another partial schematic diagram of a display substrate;

[0079] FIG11 is a partial schematic diagram of the display substrate in the rounded corner area provided in FIG10A and FIG10B ;

[0080] FIG12 is a partial schematic diagram of yet another display substrate;

[0081] FIG13 is a schematic structural diagram of a second output signal line;

[0082] FIG14 is a schematic diagram of FIG9A after the semiconductor layer pattern is formed;

[0083] FIG15 is a schematic diagram of the first conductive layer pattern of FIG9A;

[0084] FIG16 is a schematic diagram of FIG9A after forming a first conductive layer pattern;

[0085] FIG17 is a schematic diagram of the second conductive layer pattern of FIG9A;

[0086] FIG18 is a schematic diagram of FIG9A after forming a second conductive layer pattern;

[0087] FIG19 is a schematic diagram of FIG9A after forming a third insulating layer pattern;

[0088] FIG20 is a schematic diagram of a third conductive layer pattern in FIG9A ;

[0089] FIG21 is a schematic diagram of FIG9A after forming a third conductive layer pattern;

[0090] FIG22 is a schematic diagram of FIG9A after forming a fourth insulating layer pattern;

[0091] FIG23 is a schematic diagram of the fourth conductive layer of FIG9A;

[0092] FIG24 is a schematic diagram of forming a fourth conductive layer in FIG9A ;

[0093] FIG25 is a schematic diagram of FIG10A after the semiconductor layer pattern is formed;

[0094] FIG26 is a schematic diagram of the first conductive layer pattern of FIG10A;

[0095] FIG27 is a schematic diagram of FIG10A after forming a first conductive layer pattern;

[0096] FIG28 is a schematic diagram of FIG10A after forming a third insulating layer pattern;

[0097] FIG29 is a schematic diagram of a third conductive layer pattern in FIG10A;

[0098] FIG30 is a schematic diagram of FIG10A after forming a third conductive layer pattern;

[0099] FIG31 is a schematic diagram of the fourth conductive layer of FIG10A;

[0100] FIG32 is a schematic diagram of forming a fourth conductive layer in FIG10A;

[0101] FIG33 is a schematic diagram of FIG10B after the semiconductor layer pattern is formed;

[0102] FIG34 is a schematic diagram of the first conductive layer pattern of FIG10B ;

[0103] FIG35 is a schematic diagram of FIG10B after forming a first conductive layer pattern;

[0104] FIG36 is a schematic diagram of FIG10B after forming a third insulating layer pattern;

[0105] FIG37 is a schematic diagram of the third conductive layer pattern of FIG10B;

[0106] FIG38 is a schematic diagram of FIG10B after forming a third conductive layer pattern;

[0107] FIG39 is a schematic diagram of the fourth conductive layer of FIG10B;

[0108] FIG. 40 is a schematic diagram illustrating forming a fourth conductive layer in FIG. 10B . DETAILED DESCRIPTION

[0109] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0110] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0111] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0112] In this specification, for convenience, terms such as "center," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to describe the positional relationships of components with reference to the accompanying drawings. This is intended solely to facilitate description and simplify the description of this specification and is not intended to indicate or imply that the device or element referred to must have, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of components may vary depending on the direction in which they are described. Therefore, the terms are not limited to those described in this specification and may be appropriately replaced as appropriate.

[0113] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0114] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0115] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0116] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0117] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0118] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0119] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0120] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0121] Display substrates offer advantages such as high resolution, high response speed, high brightness, and a high aperture ratio, and have broad application prospects. To achieve a better visual experience, narrow bezels are a key development direction for displays. Display substrates contain driver circuits that drive pixel driver circuits to generate light, thereby enabling display. However, display substrates cannot achieve narrow bezels.

[0122] Figure 1A is a schematic diagram of the structure of a display substrate, Figure 1B is a schematic diagram of the region division of a display substrate, and Figure 2 is a schematic diagram of the structure of another display substrate. As shown in Figures 1A, 1B, and 2, the display substrate may include a display area 100 and a non-display area 200. The boundary of the display area 100 includes at least one curved boundary C, and the non-display area includes a rounded corner region CR located outside the curved boundary C.

[0123] In an exemplary embodiment, the shape of the boundary of the display area may be a rounded rectangle, which is not limited in the present disclosure.

[0124] The display substrate provided by the present disclosure can achieve large-angle bending function on all four sides, improve the module fitting wrinkle problem, and improve product yield.

[0125] In an exemplary embodiment, as shown in FIG1A and FIG2 , a display area may include pixel units P arranged in an array, at least one pixel unit including at least three sub-pixels, and at least one sub-pixel including a pixel driving circuit and a light-emitting device. The pixel driving circuit within the same sub-pixel is electrically connected to the light-emitting device and is configured to drive the light-emitting device to emit light.

[0126] In an exemplary embodiment, a pixel unit may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel, or may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, which is not limited in the present disclosure.

[0127] In an exemplary embodiment, the shape of the sub-pixels in the pixel unit can be rectangular, diamond, pentagonal, or hexagonal. When the pixel unit includes three sub-pixels, the three sub-pixels can be arranged in a horizontal parallel, vertical parallel, or triangular pattern. When the pixel unit includes four sub-pixels, the four sub-pixels can be arranged in a horizontal parallel, vertical parallel, or square pattern. This disclosure is not limited hereto.

[0128] In an exemplary embodiment, the light emitting device may be an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED), wherein the OLED may include a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked together.

[0129] In an exemplary embodiment, the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, and the hole blocking layers of all sub-pixels may be a common layer connected together. The light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0130] In an exemplary embodiment, as shown in FIG. 1A , the non-display area 200 may include a binding area located on one side of the display area 100 and a bezel area located on the other side of the display area 100 .

[0131] In an exemplary embodiment, the binding area may include a lead area, a bending area, and a composite circuit area arranged in sequence along a direction away from the display area, the lead area is connected to the display area 100, the bending area is connected to the lead area, and the composite circuit area is connected to the bending area.

[0132] In an exemplary embodiment, a plurality of lead lines may be provided in the lead area, one end of a portion of the plurality of lead lines being connected to a plurality of data fan-out lines in the display area 100, one end of another portion of the plurality of lead lines being connected to a plurality of data lines in the display area 100, and the other ends of the plurality of lead lines crossing the bending area to connect to the integrated circuit in the composite circuit area, so that the integrated circuit applies data signals to the data lines through the lead lines and the data fan-out lines.

[0133] In an exemplary embodiment, the bending region can be bent at a curvature to reverse the surface of the composite circuit region. That is, the surface of the composite circuit region facing upward can be transformed to face downward by bending the bending region. In an exemplary embodiment, when the bending region is bent, the composite circuit region can overlap with the display area 100.

[0134] In an exemplary embodiment, the composite circuit area may include an anti-static area, a driver chip area, and a binding pin area. The integrated circuit (IC) may be bound and connected to the driver chip area, and the flexible printed circuit (FPC) may be bound and connected to the binding pin area.

[0135] In an exemplary embodiment, the integrated circuit can generate the drive signals required to drive the sub-pixels and can provide the drive signals to the sub-pixels in the display area 100. For example, the drive signals can be data signals that drive the brightness of the sub-pixels. In an exemplary embodiment, the integrated circuit can be bonded to the driver chip area using an anisotropic conductive film or other means. In an exemplary embodiment, the bonding pin area can be provided with pads including a plurality of pins (PINs), and the flexible circuit board can be bonded to the pads.

[0136] In an exemplary embodiment, as shown in FIG2 , a display substrate may include a timing controller, a data driving circuit, a gate driving circuit, and a pixel array. The timing controller is connected to the data driving circuit and the gate driving circuit, respectively. The data driving circuit is connected to the data signal lines Data, respectively. The gate driving circuit is connected to the gate lines, and the gate lines may include one or more of the emission signal lines EM, the scanning signal lines Gate, or Scan. The pixel driving circuit may be connected to the gate lines and the data signal lines, respectively.

[0137] In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver circuit to the data driver circuit, clock signals, start signals, etc. suitable for the specifications of the gate driver circuit to the gate driver circuit, and clock signals, emission stop signals, etc. suitable for the specifications of the light driver circuit to the light driver circuit. The data driver circuit may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines. For example, the data driver circuit may sample grayscale values ​​using the clock signal and apply data voltages corresponding to the grayscale values ​​to the data signal lines on a pixel row basis.

[0138] In an exemplary embodiment, the gate drive circuit can generate a scan signal to be provided to the gate line by receiving a clock signal, a start signal, etc. from a timing controller. For example, the gate drive circuit can sequentially provide a signal having an on-level pulse to the gate line. For example, the gate drive circuit can be configured in the form of a shift register and can sequentially transmit the start signal provided in the form of an on-level pulse to the next stage circuit under the control of the clock signal to generate the scan signal.

[0139] In example embodiments, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure.

[0140] In an exemplary embodiment, FIG3A is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in FIG3A , the pixel driving circuit may include seven transistors (first transistor M1 to seventh transistor M7), one capacitor C, and eight signal lines (data signal line Data, scan signal line Gate, reset signal line Reset, emission signal line EM, first initial signal line INIT1, second initial signal line INIT2, high-level power line VDD, and low-level power line VSS).

[0141] As shown in FIG3A , the first plate of capacitor C is connected to the high-level power supply line VDD, and the second plate of capacitor C is connected to the first node N1. The control electrode of the first transistor M1 is connected to the reset signal line Reset, the first electrode of the first transistor M1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor is connected to the first node N1. The control electrode of the second transistor M2 is connected to the scan signal line Gate, the first electrode of the second transistor M2 is connected to the first node N1, and the second electrode of the second transistor M2 is connected to the second node N2. The control electrode of the third transistor M3 is connected to the first node N1, the first electrode of the third transistor M3 is connected to the second node N2, and the second electrode of the third transistor M3 is connected to the third node N3. The control electrode of the fourth transistor M4 is connected to the scan signal line GATE, the first electrode of the fourth transistor M4 is connected to the data signal line Data, and the second electrode of the fourth transistor M4 is connected to the second node N2. The control electrode of the fifth transistor M5 is connected to the light-emitting signal line EM, the first electrode of the fifth transistor M5 is connected to the high-level power line VDD, and the second electrode of the fifth transistor M5 is connected to the second node N2. The control electrode of the sixth transistor M6 is connected to the light-emitting signal line EM, the first electrode of the sixth transistor M6 is connected to the third node N3, and the second electrode of the sixth transistor M6 is connected to the first electrode of the light-emitting device L. The control electrode of the seventh transistor M7 is connected to the reset signal line Reset or the scan signal line Gate, the first electrode of the seventh transistor M7 is connected to the second initial signal line INIT2, the second electrode of the seventh transistor M7 is connected to the first electrode of the light-emitting device L, and the second electrode of the light-emitting device is connected to the low-level power line VSS. FIG3A is described using the control electrode of the seventh transistor M7 and the reset signal line Reset as an example.

[0142] In an exemplary embodiment, the first transistor M1 may be referred to as a node reset transistor, and when the reset signal line Reset inputs an active level signal, the first transistor M1 transmits an initialization voltage to the first node N1 to initialize the charge amount of the first node N1.

[0143] In an exemplary embodiment, the second transistor M2 may be referred to as a compensation transistor, and when the control signal line SL inputs an active level signal, the second transistor M2 transmits a signal of the second node N2 to the first node N1 to compensate for the signal of the first node N1 .

[0144] In an exemplary embodiment, the third transistor M3 may be referred to as a driving transistor, and the third transistor M3 determines a driving current flowing between the high-level power line VDD and the low-level power line VSS according to a potential difference between the control electrode and the first electrode.

[0145] In an exemplary embodiment, the fourth transistor M4 may be referred to as a write transistor or the like, and when the scan signal line Gate inputs an active level signal, the fourth transistor M4 inputs a data voltage of the data signal line Data to the third node N3 .

[0146] In an exemplary embodiment, the fifth transistor M5 and the sixth transistor M6 may be referred to as light emitting transistors. When the light emitting signal line EM inputs an active level signal, the fifth transistor M5 and the sixth transistor M6 form a driving current path between the high-level power line VDD and the low-level power line VSS to enable the light emitting device to emit light.

[0147] In an exemplary embodiment, the seventh transistor M7 can be called an anode reset transistor. When the reset signal line Reset or the scan signal line Gate inputs an active level signal, the seventh transistor M7 transmits an initialization voltage to the first electrode of the light emitting device L to initialize the charge amount of the first electrode of the light emitting device L.

[0148] In an exemplary embodiment, the signal of the high-level power line VDD is a continuously provided high-level signal, and the signal of the low-level power line VSS is a low-level signal.

[0149] Transistors can be divided into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0150] In an exemplary embodiment, the first transistor M1 to the seventh transistor M7 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor M1 to the seventh transistor M7 may include P-type transistors and N-type transistors.

[0151] In an exemplary embodiment, the first transistor M1 to the seventh transistor M7 may be low-temperature polysilicon thin-film transistors, or may be oxide thin-film transistors, or may be low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor is low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0152] In an exemplary embodiment, when the display substrate is an LTPO display substrate, the first transistor T1 and the second transistor T2 may be N-type transistors, and the remaining transistors may be P-type transistors. When the display substrate is an LTPS display substrate, the first transistor M1 to the seventh transistor M7 may be P-type transistors.

[0153] In an exemplary embodiment, when the display substrate is an LTPO display substrate, and the first transistor T1 and the second transistor T2 are N-type transistors, the first transistor T1 and the second transistor T2 can also be called control transistors. Similarly, the N-type transistor in the pixel driving circuit can be called a control transistor.

[0154] FIG3B is an operating timing diagram of the pixel driving circuit provided in FIG3A . FIG3B is illustrated by taking the example of the transistors in FIG3A as P-type transistors. The following describes an exemplary embodiment of the present disclosure using the operating process of the pixel driving circuit illustrated in FIG3B . In an exemplary embodiment, the operating process of the pixel driving circuit may include:

[0155] The first phase A1, known as the reset phase, is characterized by high-level signals on the scanning signal line Gate and the emission signal line EM, while the reset signal line Reset is low. The reset signal line Reset is high, turning on the first transistor M1. The signal on the first initialization signal line INIT1 is supplied to the first node N1, initializing the capacitor C and clearing the existing data voltage in the capacitor C. The seventh transistor M7 is turned on, and the initialization voltage on the second initialization signal line INIT2 is supplied to the first electrode of the light-emitting device L, initializing (resetting) the first electrode of the light-emitting device L and clearing the pre-stored voltage therein, completing initialization. The signals on the scanning signal line Gate and the emission signal line EM are high, turning off the second transistor M2, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6. During this phase, the light-emitting device L does not emit light.

[0156] In the second phase A2, known as the data writing phase or threshold compensation phase, the scan signal line Gate is a low-level signal, the signals on the luminescence signal line EM and the reset signal line Reset are high-level signals, and the data signal line Data outputs a data voltage. During this phase, since the first node N1 is a low-level signal, the third transistor M3 is turned on. The scan signal line Gate is a low-level signal, turning on the second transistor T2 and the fourth transistor M4. The second and fourth transistors M2 and M4 are turned on, causing the data voltage output by the data signal line Data to be supplied to the first node N1 via the second node N, the turned-on third transistor M3, the third node N3, and the turned-on second transistor M2. The difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor M3 is charged into the capacitor C until the voltage at the first node N1 reaches Vd - |Vth|, where Vd is the data voltage output by the data signal line Data and Vth is the threshold voltage of the third transistor M3. This ensures that the light-emitting device L does not emit light. The reset signal line Reset is a high-level signal, turning off the first transistor M1. The signal of the light emitting signal line EM is a high level signal, and the fifth transistor M5 and the sixth transistor M6 are turned off.

[0157] In the third phase A3, referred to as the light-emitting phase, the signals on the scanning signal line Gate and the reset signal line Reset are high-level signals, and the signal on the light-emitting signal line EM is low-level. The signal on the light-emitting signal line EM is low-level, and the fifth transistor M5 and the sixth transistor M6 are turned on. The power supply voltage output from the high-level power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor M5, the third transistor M3, and the sixth transistor M6, thereby driving the light-emitting device L to emit light.

[0158] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage of the first node N1 is Vd-|Vth|, the driving current of the third transistor M3 is:

[0159] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2

[0160] Wherein, I is the driving current flowing through the third transistor M3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor M3, Vth is the threshold voltage of the third transistor M3, Vd is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the high-level power supply line VDD.

[0161] In an exemplary embodiment, FIG4A is a schematic diagram of an equivalent circuit of another pixel driving circuit. As shown in FIG4A , the pixel driving circuit may include eight transistors (first transistor M1 to eighth transistor M8), one capacitor C, and nine signal lines (a data signal line Data, a control signal line Scan, a scan signal line Gate, a reset signal line Reset, an emission signal line EM, a first initial signal line INIT1, a second initial signal line INIT2, a high-level power line VDD, and a low-level power line VSS).

[0162] In an exemplary embodiment, the pixel driving circuit provided in FIG. 4A is applicable to an LTPO display substrate.

[0163] In an exemplary embodiment, a first plate of capacitor C is connected to a high-level power supply line VDD, and a second plate of capacitor C is connected to a first node N1. A control electrode of first transistor M1 is connected to reset signal line Reset, a first electrode of first transistor M1 is connected to a first initialization signal line INIT1, and a second electrode of first transistor M1 is connected to a fourth node N4. A control electrode of second transistor M2 is connected to scan signal line Gate, a first electrode of second transistor M2 is connected to a fourth node N4, and a second electrode of second transistor M2 is connected to a second node N2. A control electrode of third transistor M3 is connected to first node N1, a first electrode of third transistor M3 is connected to a second node N2, and a second electrode of third transistor M3 is connected to a third node N3. A control electrode of fourth transistor M4 is connected to scan signal line Gate, a first electrode of fourth transistor M4 is connected to a data signal line Data, and a second electrode of fourth transistor M4 is connected to a third node N3. A control electrode of fifth transistor M5 is connected to emission signal line EM, a first electrode of fifth transistor M5 is connected to a high-level power supply line VDD, and a second electrode of fifth transistor M5 is connected to a third node N3. A control electrode of the sixth transistor M6 is connected to the light emitting signal line EM, a first electrode of the sixth transistor M6 is connected to the second node N2, and a second electrode of the sixth transistor M6 is connected to the first electrode of the light emitting device L. A control electrode of the seventh transistor M7 is connected to the reset signal line Reset, a first electrode of the seventh transistor M7 is connected to the second initial signal line INIT2, a second electrode of the seventh transistor M7 is connected to the first electrode of the light emitting device L, and a second electrode of the light emitting device L is connected to the low-level power supply line VSS. A control electrode of the eighth transistor M8 is connected to the control signal line SCAN, a first electrode of the eighth transistor M8 is connected to the first node N1, and a second electrode of the eighth transistor M8 is connected to the fourth node N4.

[0164] In an exemplary embodiment, the control electrode of the seventh transistor M7 may also be connected to the scan signal line Gate, the first electrode of the seventh transistor M7 is connected to the second initial signal line INIT2, the second electrode of the seventh transistor M7 is connected to the first electrode of the light-emitting device L, and the second electrode of the light-emitting device L is connected to the low-level power line VSS.

[0165] In an exemplary embodiment, the first transistor M1 may be referred to as a node reset transistor, and when the reset signal line RESET inputs an active level signal, the first transistor M1 transmits an initialization voltage to the first node N1 to initialize the charge amount of the first node N1.

[0166] In an exemplary embodiment, the eighth transistor M8 can be called a compensation reset transistor. When the control signal line Scan inputs a valid level signal, the eighth transistor M8 transmits the signal of the fourth node N4 to the first node N1, which not only initializes the charge amount of the first node, but also performs threshold compensation on the third transistor M3.

[0167] In an exemplary embodiment, the second transistor M2 may be referred to as a compensation transistor, and when an active level signal is input to the scan signal line Gate, the second transistor M2 allows a signal of the second node N2 to be written to the fourth node N4.

[0168] In an exemplary embodiment, the third transistor M3 may be referred to as a driving transistor, and the third transistor M3 determines a driving current flowing between the high-level power terminal VDD and the low-level power terminal VSS according to a potential difference between the control electrode and the first electrode.

[0169] In an exemplary embodiment, the fourth transistor M4 may be referred to as a write transistor, and when the scan signal line GATE inputs an active level signal, the fourth transistor M4 allows the data voltage of the data signal line Data to be input to the pixel driving circuit.

[0170] In an exemplary embodiment, the fifth transistor M5 and the sixth transistor M6 may be referred to as light emitting transistors. When the light emitting signal line EM inputs an active level signal, the fifth transistor M5 and the sixth transistor M6 form a driving current path between the high-level power line VDD and the low-level power line VSS to enable the light emitting device to emit light.

[0171] In an exemplary embodiment, the seventh transistor M7 can be called an anode reset transistor. When the reset signal line Reset or the scan signal line Gate inputs an active level signal, the seventh transistor M7 transmits an initialization voltage to the first electrode of the light emitting device L to initialize the charge amount of the first electrode of the light emitting device L.

[0172] In an exemplary embodiment, the signal of the high-level power line VDD is a continuously provided high-level signal, and the signal of the low-level power line VSS is a low-level signal.

[0173] In an exemplary embodiment, the eighth transistor M8 is a metal oxide transistor and is an N-type transistor, and the first to seventh transistors M1 to M7 are low-temperature polysilicon transistors and are P-type transistors.

[0174] In example embodiments, the eighth transistor M8 may be referred to as a control transistor.

[0175] In an exemplary embodiment, the eighth transistor M8 is an oxide transistor, which can reduce leakage current, improve the performance of the pixel driving circuit, and reduce power consumption of the pixel driving circuit.

[0176] FIG4B is a timing diagram of the operation of the pixel driving circuit provided in FIG4A. The following describes an exemplary embodiment of the present disclosure through the operation process of the pixel driving circuit illustrated in FIG4B. The operation process of the pixel driving circuit may include:

[0177] The first phase A1 is called the reset phase. The signals on the control signal line Scan, the emission signal line EM, and the scan signal line Gate are all high-level signals, and the signal on the reset signal line Reset is low-level. The reset signal line Reset is low-level, the first transistor M1 is turned on, the signal on the first initialization signal line INIT1 is supplied to the fourth node N4, the seventh transistor M7 is turned on, and the initial voltage on the second initialization signal line INIT2 is supplied to the first electrode of the light-emitting device L, initializing (resetting) the first electrode of the light-emitting device L. For example, the pre-stored voltage within the first electrode is cleared, completing the initialization and ensuring that the light-emitting device L does not emit light. The signal on the control signal line Scan is high-level, the eighth transistor M8 is turned on, and the signal on the fourth node N4 is supplied to the first node N1, initializing the capacitor C and clearing the existing data voltage in the capacitor C. The signals on the scan signal line Gate and the emission signal line EM are high-level signals, and the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are turned off. During this phase, the light-emitting device L does not emit light.

[0178] In the second phase A2, also known as the data writing phase or threshold compensation phase, the signal on the scan signal line Gate is a low-level signal, the signals on the reset signal line Reset, the luminescence signal line EM, and the control signal line Scan are high-level signals, and the data signal line Data outputs a data voltage. During this phase, since the first node N1 is a low-level signal, the third transistor M3 is turned on. The signal on the scan signal line Gate is a low-level signal, the second transistor M2 and the fourth transistor M4 are turned on, the signal on the control signal line Scan is a high-level signal, and the eighth transistor M8 is turned on. The second transistor M2, the fourth transistor M4, and the eighth transistor M8 are turned on, so that the data voltage output by the data signal line Data is provided to the first node N1 through the third node N3, the turned-on third transistor M3, the second node N2, the turned-on second transistor M2, the fourth node N4, and the turned-on eighth transistor M8. The difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor M3 is charged into the capacitor C until the voltage at the first node N1 reaches Vd-|Vth|, where Vd is the data voltage output by the data signal line Data and Vth is the threshold voltage of the third transistor M3. The signal of the reset signal line Reset is a low-level signal, and the first transistor M1 and the seventh transistor M7 are turned off. The signal of the emission signal line EM is a high-level signal, and the fifth transistor M5 and the sixth transistor M6 are turned off.

[0179] In the third phase A3, known as the light-emitting phase, the signals on the control signal line Scan and the light-emitting signal line EM are both low-level signals, while the signals on the scan signal line Gate and the reset signal line Reset are high-level signals. The signal on the reset signal line Reset is low-level, and the first transistor M1 and the seventh transistor M7 are turned off. The control signal line SCAN is low-level, the signals on the scan signal line GATE and the reset signal line Reset are high-level signals, and the second transistor M2, the fourth transistor M4, and the eighth transistor M8 are turned off. The signal on the light-emitting signal line EM is low-level, and the fifth transistor M5 and the sixth transistor M6 are turned on. The power supply voltage output by the high-level power supply terminal VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor M5, the third transistor M3, and the sixth transistor M6, driving the light-emitting device L to emit light.

[0180] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage of the first node N1 is Vd-|Vth|, the driving current of the third transistor M3 is:

[0181] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2

[0182] Wherein, I is the driving current flowing through the third transistor M3, that is, the driving current driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor M3, Vth is the threshold voltage of the third transistor M3, Vd is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the high-level power supply terminal VDD.

[0183] Figure 5A is a schematic diagram of the structure of the display substrate provided in an embodiment of the present disclosure, Figure 5B is a partial schematic diagram of the display substrate provided in Figure 5A, Figure 6A is a schematic diagram of the structure of the display substrate provided in an embodiment of the present disclosure, and Figure 6B is a partial schematic diagram of the display substrate provided in Figure 6A. As shown in Figures 5A, 5B, 6A, and 6B, the display substrate provided in an embodiment of the present disclosure may include: a substrate and a driving circuit layer disposed on the substrate, the substrate may include: a display area 100 and a non-display area 200, the driving circuit layer may include: a pixel driving circuit PE located in the display area 100, a gate driving circuit located in the non-display area 200, and at least one initial power supply line, the initial power supply line extending at least partially along the first direction D1.

[0184] In an exemplary embodiment, at least one initial power supply line includes: a first initial power supply line to an Nth initial power supply line, where N is a positive integer greater than or equal to 1; when N is greater than or equal to 2, the N initial power supply lines are arranged along the second direction D2. Figures 5A, 5B, 6A and 6B are illustrated using two initial power supply lines, and the two initial power supply lines are the first initial power supply line INITL1 and the second initial power supply line INITL2, respectively.

[0185] In an exemplary embodiment, the gate driving circuit is configured to provide a driving signal to the pixel driving circuit P, and the initial power supply line is configured to provide an initial signal to the pixel driving circuit.

[0186] In an exemplary embodiment, the orthographic projection of at least one initial power supply line on the substrate at least partially overlaps with the orthographic projection of the gate driving circuit on the substrate. Figures 5A, 5B, 6A and 6B are explained using the example of the second initial power supply line INITL2 overlapping with the gate driving circuit.

[0187] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0188] In example embodiments, the display substrate may be an LTPO display substrate or an LTPS display substrate.

[0189] In an exemplary embodiment, the driving circuits in the display substrate may be two, three, or more types, depending on the structure of the display substrate, which is not limited in the present disclosure.

[0190] In exemplary embodiments, the light emitting device may be an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED).

[0191] In an exemplary embodiment, the display area includes a first side and a second side disposed opposite each other, and the gate driver circuit can be located on the first side and / or the second side of the display area. Figures 5A and 6A illustrate an example in which the gate driver circuit is located on one side of the display area.

[0192] In an exemplary embodiment, the driving circuit layer may further include: at least one initial signal line at least partially located in the display area, the initial signal line may extend at least partially along the second direction, the at least one initial signal line corresponds one-to-one with at least one initial power supply line, and the initial signal line is electrically connected to the corresponding initial power supply line.

[0193] In an exemplary embodiment, the display substrate may further include: a light-emitting structure layer disposed on a side of the drive circuit layer away from the substrate; and an encapsulation structure layer disposed on a side of the light-emitting structure layer away from the substrate. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited in this disclosure.

[0194] In an exemplary embodiment, the light-emitting structure layer may include an anode, a pixel definition layer, an organic light-emitting layer and a cathode 304. The anode is connected to the pixel driving circuit through a via, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of corresponding color under the drive of the anode and the cathode.

[0195] In an exemplary embodiment, the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0196] In an exemplary embodiment, the touch structure layer may include a first touch insulation layer arranged on the packaging structure layer, a first touch metal layer arranged on the first touch insulation layer, a second touch insulation layer covering the first touch metal layer, a second touch metal layer 44 arranged on the second touch insulation layer, and a touch protection layer covering the second touch metal layer. The first touch metal layer may include multiple bridging electrodes, the second touch metal layer may include multiple first touch electrodes and second touch electrodes, and the first touch electrode or the second touch electrode may be connected to the bridging electrode through a via.

[0197] The present disclosure can reduce the area occupied by the frame region of the display substrate and achieve a narrow frame by at least partially overlapping the orthographic projection of at least one initial power supply line on the substrate with the orthographic projection of the gate driving circuit on the substrate.

[0198] In an exemplary embodiment, the gate driving circuit may include: a plurality of driving circuits arranged along a second direction, wherein the first direction intersects the second direction. An orthographic projection of at least one initial power supply line on the substrate at least partially overlaps an orthographic projection of a driving circuit on the substrate that is close to the display area among the plurality of driving circuits.

[0199] In an exemplary embodiment, the positional relationship of the plurality of driving circuits may be determined according to the structure and function of the display substrate, which is not limited in the present disclosure.

[0200] In an exemplary embodiment, the driving circuit may include a plurality of cascaded shift registers.

[0201] In an exemplary embodiment, as shown in Figures 6A and 6B , the pixel driving circuit includes a light-emitting transistor and a write transistor. The multiple driving circuits may include a light-emitting driving circuit and a scan driving circuit. The light-emitting driving circuit is electrically connected to the light-emitting transistor, and the scan driving circuit is electrically connected to the write transistor. The scan driving circuit is located on a side of the light-emitting driving circuit closer to the display area 100. In this case, the orthographic projection of at least one initial power supply line on the substrate at least partially overlaps with the orthographic projection of the scan driving circuit on the substrate. Figures 6A and 6B illustrate the overlap of the second initial power supply line INITL2 and the scan driving circuit as an example.

[0202] In an exemplary embodiment, the light emitting driving circuit may include a plurality of cascaded light emitting shift registers EM-GOA, and the scan driving circuit may include a plurality of scan shift registers Pgate-GOA and a plurality of dummy scan shift registers DPgate-GOA.

[0203] In an exemplary embodiment, the driving circuit layer may further include: a light emitting signal line and a scan signal line at least partially located in the display area. The light emitting shift register is electrically connected to the pixel driving circuit via the light emitting signal line, the scan shift register is electrically connected to the pixel driving circuit via the scan signal line, and the dummy scan shift register is not electrically connected to the scan signal line.

[0204] In an exemplary embodiment, as shown in Figures 5A and 5B, the pixel driving circuit includes: a light-emitting transistor, a write transistor, and a control transistor. The multiple driving circuits may include: a light-emitting driving circuit, a scan driving circuit, and a control driving circuit. The light-emitting driving circuit is electrically connected to the light-emitting transistor, the scan driving circuit is electrically connected to the write transistor, and the control driving circuit is electrically connected to the control transistor. The write transistor and the control transistor are of opposite transistor types. The light-emitting driving circuit and the control driving circuit are located on the side of the scan driving circuit away from the display area. The orthographic projection of at least one initial power supply line on the substrate at least partially overlaps with the orthographic projection of the scan driving circuit on the substrate. Figures 6A and 6B illustrate the overlap of the second initial power supply line INITL2 with the scan driving circuit as an example.

[0205] In an exemplary embodiment, the control transistor may be an N-type transistor in a pixel driving circuit.

[0206] In an exemplary embodiment, the light emitting driving circuit can be located on a side of the control driving circuit close to the display area, or can be located on a side of the control driving circuit away from the display area. Figures 5A and 5B show that the light emitting driving circuit is located on a side of the control driving circuit away from the display area.

[0207] In an exemplary embodiment, as shown in FIG6B , the light emitting driving circuit may include: a plurality of cascaded light emitting shift registers EM-GOA, the control driving circuit may include: a plurality of cascaded control shift registers Ngate-GOA, and the scanning driving circuit may include: a plurality of scanning shift registers Pgate-GOA and a plurality of virtual scanning shift registers DPgate-GOA.

[0208] In an exemplary embodiment, as shown in FIG5B and FIG6B , a plurality of scan shift registers Pgate-GOA are cascaded, a plurality of DPgate-GOA virtual scan shift registers are interspersed between the plurality of scan shift registers Pgate-GOA, and the plurality of virtual scan shift registers are at least partially located in the rounded corner area.

[0209] In an exemplary embodiment, orthographic projections of K adjacent initial power supply lines that are away from the display area on the substrate at least partially overlap with an orthographic projection of the scan driving circuit on the substrate, where K is a positive integer less than or equal to N. Exemplarily, the orthographic projections of the first and second initial power supply lines on the substrate may both at least partially overlap with an orthographic projection of the scan driving circuit on the substrate.

[0210] In an exemplary embodiment, the scanning shift register or the virtual scanning shift register may include: multiple transistors and multiple capacitors. The circuit structure of the scanning shift register or the virtual scanning shift register may be 8T2C, which is not limited in the present disclosure.

[0211] Figure 7A is an equivalent circuit diagram of a shift register in a display substrate, and Figure 7B is a timing diagram of the shift register provided in Figure 7A. The shift register can be a scanning shift register or a virtual scanning shift register. As shown in Figure 7A, the shift register includes: first transistors T1 to T8, a first capacitor C1, and a second capacitor C2.

[0212] In an exemplary embodiment, a control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK1, a first electrode of the first transistor T1 is electrically connected to the input terminal IN, and a second electrode of the first transistor T1 is electrically connected to the first node G1; a control electrode of the second transistor T2 is electrically connected to the first node G1, a first electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK1, and a second electrode of the second transistor T2 is electrically connected to the second node G2; a control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, a first electrode of the third transistor T3 is electrically connected to the second power supply terminal V2, and a second electrode of the third transistor T3 is electrically connected to the second node G2; a control electrode of the fourth transistor T4 is electrically connected to the second node G2, a first electrode of the fourth transistor T4 is electrically connected to the first power supply terminal V1, and a second electrode of the fourth transistor T4 is electrically connected to the output terminal OUT; a control electrode of the fifth transistor T5 is electrically connected to the third node G3, a first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal V1, and a second electrode of the fourth transistor T4 is electrically connected to the output terminal OUT; The second clock signal terminal CK2 is electrically connected, and the second electrode of the fifth transistor T5 is electrically connected to the output terminal OUT; the control electrode of the sixth transistor T6 is electrically connected to the second node G2, the first electrode of the sixth transistor T6 is electrically connected to the first power supply terminal VH, and the second electrode of the sixth transistor T6 is electrically connected to the first electrode of the seventh transistor T7; the control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CK2, and the second electrode of the seventh transistor T7 is electrically connected to the first node G1; the control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2, the first electrode of the eighth transistor T8 is electrically connected to the first node G1, and the second electrode of the eighth transistor T8 is electrically connected to the third node G3; the first plate C11 of the first capacitor C1 is electrically connected to the first power supply terminal V1, and the second plate C12 of the first capacitor C1 is electrically connected to the second node G2; the first plate C21 of the second capacitor C2 is electrically connected to the output terminal OUT, and the second plate C22 of the second capacitor C2 is electrically connected to the third node G3.

[0213] In example embodiments, the first to eighth transistors T1 to T8 may be P-type transistors or may be N-type transistors.

[0214] In an exemplary embodiment, the first power terminal V1 continuously provides a high-level signal, and the second power terminal V2 continuously provides a low-level signal.

[0215] Taking the first transistor T1 to the eighth transistor T8 as P-type transistors as an example, as shown in FIG7B , the operation process of the shift register provided by an exemplary embodiment includes the following stages:

[0216] During input phase B1, the signals at the first clock signal terminal CK1 and the input terminal IN are low-level signals, while the signal at the second clock signal terminal CK2 is high-level. Since the signal at the first clock signal terminal CK1 is low-level, the first transistor T1 is turned on, and the signal at the input terminal IN is transmitted to the first node G1 via the first transistor T1. Since the signal at the eighth transistor T8 receives the low-level signal from the second power supply terminal V2, the eighth transistor T8 is turned on. The level at the third node G3 can be adjusted by turning on the fifth transistor T5, and the signal at the second clock signal terminal CK2 is transmitted to the output terminal OUT via the fifth transistor T5. That is, during input phase B1, the signal at the second clock signal terminal CK2 is high-level at the output terminal OUT. Furthermore, since the signal at the first clock signal terminal CK1 is low-level, the third transistor T3 is turned on, and the low-level signal at the second power supply terminal V2 is transmitted to the second node G2 via the third transistor T3. At this time, the fourth transistor T4 and the sixth transistor T6 are both turned on. Since the signal at the second clock signal terminal CK2 is high-level, the seventh transistor T7 is turned off.

[0217] During output phase B2, the signal at the first clock signal terminal CK1 is a high-level signal, the signal at the second clock signal terminal CK2 is a low-level signal, and the signal at the input terminal IN is a high-level signal. The fifth transistor T5 is turned on, and the signal at the second clock signal terminal CK2 is transmitted via the fifth transistor T5 as the signal at the output terminal OUT. During output phase B2, the voltage level at the end of the second capacitor C2 connected to the output terminal OUT changes to the signal at the second power supply terminal V2. Due to the bootstrap effect of the second capacitor C2, the eighth transistor T8 is turned off, allowing the fifth transistor T5 to be more effectively turned on, and the signal at the output terminal OUT is a low-level signal. Furthermore, the signal at the first clock signal terminal CK1 is a high-level signal, causing both the first transistor T1 and the third transistor T3 to be turned off. The second transistor T2 is turned on, and the high-level signal at the first clock signal terminal CK1 is transmitted to the second node G2 via the second transistor T2. As a result, the fourth transistor T4 and the sixth transistor T6 are both turned off. Since the signal at the second clock signal terminal CK2 is a low-level signal, the seventh transistor T7 is turned on.

[0218] During buffering phase B3, the signals at both the first clock signal terminal CK1 and the second clock signal terminal CK2 are high-level signals, the signal at the input terminal IN is high-level, the fifth transistor T5 is turned on, and the second clock signal terminal CK2 is output via the fifth transistor T5. Due to the bootstrap effect of the second capacitor C2, the level of the first node G1 becomes V2-Vth. Furthermore, the signal at the first clock signal terminal CK1 is high-level, causing the first transistor T1 and the third transistor T3 to be turned off. The eighth transistor T8 is turned on, and the second transistor T2 is turned on. The high-level signal at the first clock signal terminal CK1 is transmitted to the second node G2 via the second transistor T2, thereby turning off the fourth transistor T4 and the sixth transistor T6. Since the signal at the second clock signal terminal CK2 is high-level, the seventh transistor T7 is turned off.

[0219] In the first sub-phase B41 of the stable phase B4, the signal at the first clock signal terminal CK1 is a low-level signal, while the signals at the second clock signal terminal CK2 and the input terminal IN are high-level signals. Because the signal at the first clock signal terminal CK1 is a low-level signal, the first transistor T1 is turned on, and the signal at the input terminal IN is transmitted to the first node G1 via the first transistor T1. The second transistor T2 is turned off. Because the eighth transistor T8 is turned on, the fifth transistor T5 is turned off. Because the signal at the first clock signal terminal CK1 is a low-level signal, the third transistor T3 is turned on, and the fourth and sixth transistors T4 and T6 are both turned on. The high-level signal at the first power supply terminal V1 is transmitted to the output terminal OUT via the fourth transistor T4. Therefore, the signal at the output terminal OUT is a high-level signal.

[0220] In the second sub-phase B42 of the stable phase B4, the signal at the first clock signal terminal CK1 is a high-level signal, the signal at the second clock signal terminal CK2 is a low-level signal, and the signal at the input terminal IN is a high-level signal. The fifth transistor T5 and the second transistor T2 are both turned off. The signal at the first clock signal terminal CK1 is a high-level signal, so the first transistor T1 and the third transistor T3 are both turned off. Due to the holding effect of the first capacitor C1, the fourth transistor T4 and the sixth transistor T6 are both turned on, and the high-level signal is transmitted to the output terminal OUT via the fourth transistor T4. That is, the signal at the output terminal OUT is a high-level signal.

[0221] In the second sub-phase B42, since the signal at the second clock signal terminal CK2 is a low-level signal, the seventh transistor T7 is turned on, so that the high-level signal is transmitted to the third node G3 and the first node G1 via the sixth transistor T6 and the seventh transistor T7, so that the signals at the third node G3 and the first node G1 remain high-level signals.

[0222] In the third sub-phase B43, the signals at the first clock signal terminal CK1 and the second clock signal CK2 are both high-level signals, and the signal at the input terminal IN is also high-level. The fifth transistor T5 and the second transistor T2 are turned off. The signal at the first clock signal terminal CK1 is high-level, so the first transistor T1 and the third transistor T3 are both turned off, and the fourth transistor T4 and the sixth transistor T6 are both turned on. The high-level signal is transmitted to the output terminal OUT via the fourth transistor T4, that is, the signal at the output terminal OUT is also high-level.

[0223] In an exemplary embodiment, the number of transistors in the dummy scan shift register may be less than or equal to the number of transistors in the scan shift register.

[0224] In an exemplary embodiment, the width of the dummy scan shift register may be smaller than or equal to the width of the scan shift register.

[0225] In an exemplary embodiment, when the number of transistors of the virtual scanning shift register is equal to the number of transistors in the scanning shift register, the circuit structure of the virtual scanning shift register can be the same as the circuit structure of the scanning shift register. At this time, the width of the virtual scanning shift register can be equal to the width of the scanning shift register, and the width is the length in a direction perpendicular to the extension direction of the second power line VGL to which the shift register is connected. The shift register includes a virtual scanning shift register or a scanning shift register.

[0226] In an exemplary embodiment, when the number of transistors of the dummy scan shift register is smaller than the number of transistors in the scan shift register, the width of the dummy scan shift register may be smaller than the width of the scan shift register.

[0227] In an exemplary embodiment, in order to ensure the display effect of the rounded corner area, more pixel driving circuits are retained near the rounded corner area. The present disclosure can save enough area for the wiring of the scan shift register by reducing the width of the virtual scan shift register, thereby reducing the area occupied by the rounded corner area and realizing a narrow frame of the display substrate.

[0228] In an exemplary embodiment, FIG8A is an equivalent circuit diagram of a virtual scan shift register, and FIG8B is an equivalent circuit diagram of another virtual scan shift register. When the number of transistors in the virtual scan shift register is less than the number of transistors in the scan shift register, the circuit structure of the virtual scan shift register can be FIG8A or FIG8B, wherein the circuit structures provided in FIG8A and FIG8B do not include capacitors.

[0229] In an exemplary embodiment, as shown in FIG8A , the dummy scan shift register may include a first transistor DT1, a second transistor DT2, and a fourth transistor DT4 to an eighth transistor DT8. The control electrode, the first electrode, and the second electrode of the first transistor DT1 are electrically connected to the second power supply terminal V2, the control electrode, the first electrode, and the second electrode of the second transistor DT2 are electrically connected to the second power supply terminal V2, the control electrode, the first electrode, and the second electrode of the fourth transistor DT4 are electrically connected to the second power supply terminal V2, the first electrode and the second electrode of the fifth transistor DT5 are electrically connected to the second power supply terminal V2, the control electrode of the fifth transistor DT5 is electrically connected to the second electrode of the eighth transistor DT8, the control electrode and the first electrode of the sixth transistor DT6 are electrically connected to the second power supply terminal V2, the second electrode of the sixth transistor DT6 is electrically connected to the first electrode of the seventh transistor DT7, the control electrode and the second electrode of the seventh transistor DT7 are electrically connected to the second power supply terminal V2, and the control electrode and the first electrode of the eighth transistor DT8 are electrically connected to the second power supply terminal V2.

[0230] In an exemplary embodiment, as shown in FIG8B , the dummy scan shift register may include a first transistor DT1, a second transistor DT2, and sixth to eighth transistors DT6 to DT8. The control electrode, first electrode, and second electrode of the first transistor DT1 are electrically connected to the second power supply terminal V2, the control electrode, first electrode, and second electrode of the second transistor DT2 are electrically connected to the second power supply terminal V2, the control electrode and first electrode of the sixth transistor DT6 are electrically connected to the second power supply terminal V2, the second electrode of the sixth transistor DT6 is electrically connected to the first electrode of the seventh transistor DT7, the control electrode and second electrode of the seventh transistor DT7 are electrically connected to the second power supply terminal V2, and the control electrode, first electrode, and second electrode of the eighth transistor DT8 are electrically connected to the second power supply terminal V2.

[0231] In an exemplary embodiment, the circuit structure of the light emitting shift register or the control register may be 13T3C or 10T3C, which is not limited in the present disclosure.

[0232] In an exemplary embodiment, the display substrate may further include other film layers, such as spacers and columns, etc., which is not limited in the present disclosure.

[0233] Figure 9A is a partial schematic diagram of a display substrate, Figure 9B is a partial schematic diagram of the display substrate in the rounded corner area provided by Figure 9A, Figure 10A is another partial schematic diagram of the display substrate, Figure 10B is another partial schematic diagram of the display substrate, and Figure 11 is a partial schematic diagram of the display substrate in the rounded corner area provided by Figures 10A and 10B. As shown in Figures 9A to 11, in an exemplary embodiment, the driving circuit layer may further include: a first initial signal line GSTV, a first clock signal line GCK1, a second clock signal line GCK2, a first power line VGH, and a second power line VGL located in the non-display area, and the scan driving circuit is electrically connected to the first clock signal line GCK1, the second clock signal line GCK2, the first power line VGH, the second power line VGL, and the first initial signal line GSTV, respectively.

[0234] In example embodiments, as shown in FIGS. 9A to 11 , the first clock signal line GCK1 , the second clock signal line GCK2 , the first initial signal line GSTV, the first power line VGH, and the second power line VGL may at least partially extend in the first direction D1 .

[0235] In an exemplary embodiment, the input terminal of the first-stage shift register is electrically connected to the first initial signal line, and the output terminal of the i-th stage shift register is electrically connected to the input terminal of the i+1-th stage shift register; the first clock signal terminal of the i-th stage shift register is electrically connected to the first clock signal line, and the second clock signal terminal is electrically connected to the second clock signal line, the first clock signal terminal of the i+1-th stage shift register is electrically connected to the second clock signal line, and the second clock signal terminal is electrically connected to the first clock signal line, the first power supply terminal of the i-th stage shift register is electrically connected to the first power supply line, and the second power supply terminal of the i-th stage shift register is electrically connected to the second power supply line.

[0236] In an exemplary embodiment, as shown in Figures 9A to 11, the second clock signal line GCK2 is located on the side of the first clock signal line GCK1 away from the display area, the second power line VGL is located on the side of the first clock signal line close to the display area, the first initial signal line GSTV is located on the side of the second power line VGL close to the display area, the first power line VGH is located on the side of the first initial signal line GSTV close to the display area, and at least one initial power supply line is located on the side of the first power line VGH close to the display area. Figures 9A to 11 illustrate two initial power supply lines, a first initial power supply line INITL1 and a second initial power supply line INTIL2, as examples.

[0237] In an exemplary embodiment, as shown in FIG. 9A to FIG. 11 , the driving circuit layer may further include a second initial signal line ESTV located in the non-display area, the second initial signal line ESTV extending at least partially along the first direction D1. The light emitting driving circuit is electrically connected to the second initial signal line ESTV, and the second initial signal line ESTV is located between the second power line VGL and the first initial signal line GSTV.

[0238] In an exemplary embodiment, as shown in FIG. 9A , the driving circuit layer may further include first and second output signal lines OUTL1 and OUTL2 located in the non-display area, the first and second output signal lines OUTL1 and OUTL2 at least partially extending along the second direction D2 .

[0239] In an exemplary embodiment, as shown in FIG. 9A , the first output signal line OUTL1 is located on a side of the scan driving circuit close to the display area, and is electrically connected to the scan driving circuit and the pixel driving circuit, respectively.

[0240] In an exemplary embodiment, as shown in FIG. 9A , the second output signal line OUTL2 passes through the scan driving circuit and is electrically connected to the pixel driving circuit and one of the light emitting driving circuit and the control driving circuit.

[0241] In an exemplary embodiment, the orthographic projection of the initial power supply line that overlaps with the scan driving circuit on the substrate at least partially overlaps with the orthographic projections of the multiple capacitors on the substrate. As shown in Figure 9A, the orthographic projection of the second initial signal line INITL2 on the substrate at least partially overlaps with the orthographic projections of the multiple capacitors on the substrate.

[0242] In an exemplary embodiment, the distance between the initial power supply line that overlaps with the scan driver circuit and the boundary of the display area is shorter than the distance between at least one of the multiple capacitors and the boundary of the display area. Taking FIG8A as an example, the distance between the second initial power supply line INITL2 and the boundary of the display area is shorter than the distance between at least one of the multiple capacitors and the boundary of the display area. This means that the second initial power supply line INITL2 overlaps with the capacitor but not with the transistor, thereby improving the reliability of the scan shift register.

[0243] In an exemplary embodiment, in combination with Figures 9B, 10A, 10B and 11, a distance L2 between a boundary of the second clock signal line located on a side of the virtual scan shift register away from the display area and a boundary of the initial power supply line of at least one initial power supply line close to the display area close to the display area is smaller than a distance L1 between a boundary of the second clock signal line located on a side of the scan shift register away from the display area and a boundary of the initial power supply line of at least one initial power supply line close to the display area close to the display area.

[0244] In an exemplary embodiment, Figure 12 is a partial schematic diagram of another display substrate. As shown in Figure 12, the driving circuit layer may further include: a first output connection line CL1 and a second output connection line CL2 located in the display area and the non-display area, and the first output connection line CL1 and the second output connection line CL extend at least partially along the second direction.

[0245] In an exemplary embodiment, the first output connection lines may be electrically connected to the first output signal line OUTL1 and the pixel driving circuit, respectively, and the second output connection lines may be electrically connected to the second output signal line OUTL2 and the pixel driving circuit, respectively.

[0246] In an exemplary embodiment, the first output connection line is electrically connected to the pixel driving circuit via a scan signal line. The second output connection line is electrically connected to the pixel driving circuit via a light emitting signal line or a control signal line. When the second output signal line connected to the second output connection line is electrically connected to the light emitting driving circuit, the second output connection line is electrically connected to the pixel driving circuit via the light emitting signal line. When the second output signal line connected to the second output connection line is electrically connected to the control driving circuit, the second output connection line is electrically connected to the pixel driving circuit via the control signal line.

[0247] In an exemplary embodiment, when N=2, as shown in FIG12 , the driving circuit layer may further include: a third output connection line CL3 and a fourth output connection line CL4, wherein a small portion of the third output connection line CL3 and the fourth output connection lines CL4 extend along the second direction D2. The third output connection line CL3 is electrically connected to the first initial power supply line and the pixel driving circuit, respectively; and the fourth output connection line CL4 is electrically connected to the second initial power supply line and the pixel driving circuit, respectively.

[0248] In an exemplary embodiment, the driving circuit layer may include: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer stacked in sequence;

[0249] The semiconductor layer includes at least: an active layer of a plurality of transistors;

[0250] The first conductive layer at least includes: control electrodes of multiple transistors and first plates of multiple capacitors;

[0251] The second conductive layer at least includes: second plates of a plurality of capacitors, a first output signal line, and a third output signal line;

[0252] The third conductive layer at least includes: a second power supply line, a first electrode and a second electrode of at least one transistor, and a fourth output signal line;

[0253] The fourth conductive layer at least includes: a first initial signal line, a second initial signal line and a first power line.

[0254] In an exemplary embodiment, the driving circuit layer further includes: a fifth conductive layer located on a side of the fourth conductive layer away from the substrate;

[0255] The fifth conductive layer at least includes a first output connection line and a second output connection line.

[0256] In an exemplary embodiment, the first output connection line and the second output connection line are located in the fifth conductive layer to further reduce the space occupied by the non-display area. The first output connection line is connected from the non-display area to the display area, and a cross-layer connection is made within the display area to connect to the corresponding pixel driving circuit.

[0257] In an exemplary embodiment, a dummy line may be interspersed between the first output connection line and the second output connection line, wherein the dummy line is a signal line that does not provide a signal. The interspersed dummy line between the first output connection line and the second output connection line can ensure uniform etching of the fifth conductive layer and thus ensure the reliability of the display substrate.

[0258] In an exemplary embodiment, the initial power supply line may have a single-layer structure, or may have a multi-layer structure, which is not limited in the present disclosure.

[0259] In an exemplary embodiment, the initial power supply line has a single-layer structure, and the initial power supply line is located in the fourth conductive layer.

[0260] In an exemplary embodiment, when the display substrate is an LTPO display substrate, the initial power supply line may have a single-layer structure.

[0261] In an exemplary embodiment, the initial power supply line includes a first initial subsegment and a second initial subsegment connected to each other, and an orthographic projection of the first initial subsegment on the substrate at least partially overlaps with an orthographic projection of the second initial subsegment on the substrate.

[0262] In an exemplary embodiment, the first initial sub-segment is located in the third conductive layer, and the second initial sub-segment is located in the fourth conductive layer.

[0263] In an exemplary embodiment, the initial power supply line adopts a stacked design to reduce load differences of the initial power supply line and meet jumper rules of the display substrate to avoid static electricity risks in the display substrate.

[0264] In an exemplary embodiment, the first clock signal line and the second clock signal line may have a single-layer structure or a multi-layer structure, which is not limited in the present disclosure.

[0265] In an exemplary embodiment, the first clock signal line and the second clock signal line are a single-layer structure, and the first clock signal line and the second clock signal line are located in the fourth conductive layer.

[0266] In an exemplary embodiment, the clock signal line may include: a first clock sub-segment and a second clock sub-segment connected to each other, the clock signal line including the first clock signal line and the second clock signal line, an orthographic projection of the first clock sub-segment on the substrate at least partially overlapping with an orthographic projection of the second clock sub-segment on the substrate;

[0267] In an exemplary embodiment, the first clock sub-segment is located on the third conductive layer, and the second clock sub-segment is located on the fourth conductive layer close to the side of the substrate.

[0268] In an exemplary embodiment, the first clock signal line and the second clock signal line adopt a stacked design to reduce the load difference between the first clock signal line and the second clock signal line, and can also meet the jumper rules of the display substrate to avoid static electricity risks in the display substrate.

[0269] In an exemplary embodiment, the second output signal line may have a single-layer structure, or may have a multi-layer structure, which is not limited in the present disclosure.

[0270] In an exemplary embodiment, the second output signal line has a single-layer structure, and the second output signal line is located in the second conductive layer.

[0271] In an exemplary embodiment, FIG13 is a schematic diagram of the structure of a second output signal line. As shown in FIG13 , the driving circuit layer further includes a sixth conductive layer located between the second conductive layer and the third conductive layer. The second output signal line includes a plurality of first output sub-segments OUTL2A and a plurality of second output sub-segments OUTL2B. Adjacent first output sub-segments OUTL2A are electrically connected via the second output sub-segments OUTL2B, and adjacent second output sub-segments OUTL2B are electrically connected via the first output sub-segments OUTL2A. The orthographic projections of the second output sub-segments OUTL2B on the substrate at least partially overlap with the orthographic projections of the electrically connected first output sub-segments OUTL2A on the substrate. The orthographic projections of the first output sub-segments OUTL2A on the substrate at least partially overlap with the orthographic projections of the electrically connected second output sub-segments OUTL2B on the substrate. The first output sub-segments OUTL2A are located in the second conductive layer, and the second output sub-segments OUTL2B are located in the sixth conductive layer.

[0272] In an exemplary embodiment, the second output signal line includes a first output sub-segment and a second output sub-segment located in different film layers, which can avoid the risk of static electricity caused by the length of the second output signal line.

[0273] The "patterning process" referred to in this disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metal, inorganic, or transparent conductive materials. For organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be achieved by any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be achieved by any one or more of spraying, spin coating, and inkjet printing; and etching can be achieved by any one or more of dry etching and wet etching, all of which are not limited in this disclosure. A "thin film" refers to a thin layer of a material produced on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire production process, it can also be referred to as a "layer." If the "thin film" requires a patterning process during the entire production process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process. The "thickness" of the film layer refers to the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0274] The following is an exemplary description of the preparation process of the display substrate provided by FIG. 9A , in which FIG. 9A is described by taking the second output signal line as a single-layer structure as an example.

[0275] (1) Forming a semiconductor layer pattern on a substrate. In an exemplary embodiment, forming the semiconductor layer pattern may include: depositing a semiconductor thin film on the substrate, and patterning the semiconductor thin film through a patterning process to form a semiconductor layer pattern, as shown in FIG14 , which is a schematic diagram of FIG9A after the semiconductor layer pattern is formed.

[0276] In exemplary embodiments, as shown in FIG. 14 , the semiconductor layer pattern may include an active layer T11 of a first transistor to an active layer T81 of an eighth transistor.

[0277] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0278] In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The first and second flexible material layers may be made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The first and second inorganic material layers may be made of silicon nitride (SiNx) or silicon oxide (SiOx) to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers. The semiconductor layer may be made of amorphous silicon (a-Si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: first coating a layer of polyimide on a glass carrier, and forming a first flexible (PI1) layer after curing; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing a layer of amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating the amorphous silicon layer with another layer of polyimide, and forming a second flexible (PI2) layer after curing; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thereby completing the preparation of the substrate.

[0279] In an exemplary embodiment, the semiconductor layer film can be made of various materials such as amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, polythiophene, etc., that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology and organic technology.

[0280] In an exemplary embodiment, as shown in Figure 14, the active layer T21 of the second transistor and the active layer T31 of the third transistor can be an integral structure, the active layer T41 of the fourth transistor and the active layer T51 of the fifth transistor can be an integral structure, the active layer T61 of the sixth transistor and the active layer T71 of the seventh transistor can be an integral structure, and the active layer T11 of the first transistor and the active layer T81 of the eighth transistor are separately provided.

[0281] In an exemplary embodiment, as shown in FIG14 , in the first direction D1, the active layer T81 of the eighth transistor and the integrated structure of the active layer T61 of the sixth transistor and the active layer T71 of the seventh transistor are located on the same side of the active layer T11 of the first transistor, and in the second direction D2, the active layer T11 of the first transistor, the active layer T81 of the eighth transistor, the integrated structure of the active layer T41 of the fourth transistor and the active layer T51 of the fifth transistor, and the integrated structure of the active layer T61 of the sixth transistor and the active layer T71 of the seventh transistor are located on the same side of the active layer T11 of the first transistor. The active layer T21 of the second transistor and the active layer T31 of the third transistor are located on the same side of the integrated structure, the active layer T41 of the fourth transistor and the active layer T51 of the fifth transistor, and the integrated structure of the active layer T61 of the sixth transistor and the active layer T71 of the seventh transistor are located on the same side of the active layer T81 of the eighth transistor, and the active layer T11 of the first transistor of the scanning shift register at this level is located on the side of the active layer T81 of the eighth transistor of the scanning shift register at this level close to the scanning shift register of the previous level.

[0282] In an exemplary embodiment, the active layer T11 of the first transistor may extend along the second direction D2 and have a strip-shaped structure. The integrated structure of the active layer T21 of the second transistor and the active layer T31 of the third transistor, the integrated structure of the active layer T61 of the sixth transistor and the active layer T71 of the seventh transistor, and the active layer T81 of the eighth transistor may have an "I" shape. The integrated structure of the active layer T41 of the fourth transistor and the active layer T51 of the fifth transistor may include two "I"-shaped structures, and the two "I"-shaped structures are arranged along the second direction D2.

[0283] In example embodiments, the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region. In an exemplary embodiment, the second region T21_2 of the active layer of the second transistor may serve as the second region T31_2 of the active layer of the third transistor, the second region T41_2 of the active layer of the fourth transistor may serve as the second region T51_2 of the active layer of the fifth transistor, the second region T61_2 of the active layer of the sixth transistor may serve as the first region T71_1 of the active layer of the seventh transistor, and the first region T11_1 and the second region T11_2 of the active layer of the first transistor, the first region T21_1 of the active layer of the second transistor, the first region T31_1 of the active layer of the third transistor, the first region T41_1 of the active layer of the fourth transistor, the first region T51_1 of the active layer of the fifth transistor, the first region T61_1 of the active layer of the sixth transistor, the first region T71_2 of the active layer of the seventh transistor, and the first region T81_1 and the second region T81_2 of the active layer of the eighth transistor may be separately provided.

[0284] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a first insulating film and a first conductive film on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process to form a first insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the first insulating layer, as shown in Figures 15 and 16, where Figure 15 is a schematic diagram of the first conductive layer pattern of Figure 9A, and Figure 16 is a schematic diagram of Figure 9A after the first conductive layer pattern is formed. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0285] 15 and 16 , the first conductive layer pattern may include at least the control electrodes T12 to T82 of the first to eighth transistors, the first and second plates C11 and C21 of the first and second capacitors, and a first connection line VL1 .

[0286] In an exemplary embodiment, as shown in Figures 15 and 16, the first plate C11 of the first capacitor, the control electrode T42 of the fourth transistor, and the control electrode T62 of the sixth transistor are an integrated structure, and the first plate C21 of the second capacitor and the control electrode T52 of the fifth transistor are an integrated structure.

[0287] In an exemplary embodiment, as shown in Figures 15 and 16, the first plate C11 of the first capacitor and the first plate C21 of the second capacitor can be arranged along the first direction D1, and the first plate C11 of the first capacitor can be located on a side of the first plate C21 of the second capacitor close to the previous stage scan shift register.

[0288] In an exemplary embodiment, as shown in FIG. 15 and FIG. 16 , the area of ​​the first plate C21 of the second capacitor may be greater than the area of ​​the first plate C11 of the first capacitor.

[0289] In an exemplary embodiment, as shown in Figures 15 and 16, the first plate C11 of the first capacitor may be square in shape and may be located on a side of the control electrode T42 of the fourth transistor and the control electrode T62 of the sixth transistor that is closer to the display area. The control electrode T42 of the fourth transistor and the control electrode T62 of the sixth transistor may be strip-shaped and extend along the second direction D2.

[0290] In an exemplary embodiment, as shown in Figures 15 and 16 , the first electrode C21 of the second capacitor may be square in shape and may be located on the side of the control electrode T52 of the fifth transistor that is closer to the display area. The control electrode T52 of the fifth transistor may include multiple strips extending along the second direction D2. The integrated structure of the control electrode T52 of the fifth transistor and the first electrode C21 of the second capacitor may form a comb structure, with the control electrode T52 of the fifth transistor serving as the teeth of the comb and the first electrode C21 of the second capacitor serving as the back of the comb.

[0291] In an exemplary embodiment, as shown in Figures 15 and 16 , the control electrode T12 of the first transistor may be located on a side of the first plate C11 of the first capacitor away from the display area. The control electrode T12 of the first transistor may be shaped like a clockwise "F" with an opening facing the control electrode T22 of the second transistor.

[0292] In example embodiments, as shown in FIG. 15 and FIG. 16 , the control electrode T22 of the second transistor and the control electrode T32 of the third transistor may be a stripe-shaped structure extending along the second direction D2 .

[0293] In an exemplary embodiment, as shown in FIG. 15 and FIG. 16 , the control electrode T72 of the seventh transistor may be in the shape of an “n” rotated counterclockwise, with two sides of “n” having different lengths.

[0294] In an exemplary embodiment, as shown in FIG. 15 and FIG. 16 , the control electrode T82 of the eighth transistor at least partially extends along the second direction D2 and has a zigzag shape.

[0295] In an exemplary embodiment, as shown in FIG. 15 and FIG. 16 , the first connection line VL1 may be in a strip shape extending along the second direction D2 and located on a side of the control electrode T42 of the fourth transistor close to the previous stage shift register.

[0296] In an exemplary embodiment, as shown in Figures 15 and 16, the control electrode T12 of the first transistor is arranged across the active layer of the first transistor, the control electrode T22 of the second transistor is arranged across the active layer of the second transistor, the control electrode T32 of the third transistor is arranged across the active layer of the third transistor, the control electrode T42 of the fourth transistor is arranged across the active layer of the fourth transistor, the control electrode T52 of the fifth transistor is arranged across the active layer of the fifth transistor, the control electrode T62 of the sixth transistor is arranged across the active layer of the sixth transistor, and the control electrode T72 of the seventh transistor is arranged across the active layer of the seventh transistor. The extension direction of the control electrode of at least one transistor is perpendicular to the extension direction of the active layer.

[0297] In this exemplary embodiment, after forming the first conductive layer pattern, the semiconductor layer can be conductively processed using the first conductive layer as a shield. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first through seventh transistors T1 through T7, while the semiconductor layer in the area not shielded by the first conductive layer is conductively processed. That is, the first and second regions of the first through seventh transistors T1 through T7 are both conductively processed. The integrated structure of the second region of the active layer of the sixth transistor and the first region of the active layer of the seventh transistor is reused as the second electrode T64 of the sixth transistor and the first electrode T73 of the seventh transistor.

[0298] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a second insulating film and a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film through a patterning process to form a second insulating layer covering the first conductive layer pattern, and a second conductive layer pattern disposed on the second insulating layer, as shown in Figures 17 and 18, where Figure 17 is a schematic diagram of the second conductive layer pattern of Figure 9A, and Figure 18 is a schematic diagram of Figure 9A after the second conductive layer pattern is formed. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0299] In an exemplary embodiment, as shown in FIG. 17 and FIG. 18 , the second conductive layer pattern may include at least a second plate C12 of the first capacitor, a second plate C22 of the second capacitor, a first output signal line OUTL1 , a second output signal line OUTL2 , and a third output signal line OUTL3 .

[0300] In an exemplary embodiment, as shown in FIG. 17 and FIG. 18 , the second plate C22 of the second capacitor and the first output signal line OUTL1 may be an integral structure, and the first output signal line OUTL1 is located on a side of the second plate C22 of the second capacitor close to the display area.

[0301] In an exemplary embodiment, as shown in Figures 17 and 18, the outline of the second plate C12 of the first capacitor can be a sickle shape rotated to the left, and the orthographic projection of the second plate C12 of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the first plate C11 of the first capacitor on the substrate.

[0302] In an exemplary embodiment, as shown in Figures 17 and 18, the outline of the second plate C22 of the second capacitor can be rectangular, the corners of the rectangle can be chamfered, and the orthographic projection of the second plate C22 of the second capacitor on the substrate at least partially overlaps with the orthographic projection of the first plate C21 of the second capacitor on the substrate.

[0303] In an exemplary embodiment, as shown in FIG. 17 and FIG. 18 , the first output signal line OUTL1 , the second output signal line OUTL2 , and the third output signal line OUTL3 may at least partially extend along the second direction D2 and may have a zigzag line shape.

[0304] In an exemplary embodiment, as shown in Figures 17 and 18, the second output signal line OUTL2 can be located on a side of the first output signal line OUTL1 close to the previous level scan shift register, the third output signal line OUTL3 can be located on a side of the first output signal line OUTL1 close to the next level scan shift register, and the third output signal line OUTL3 is located on a side of the second plate C12 of the first capacitor close to the display area.

[0305] (4) Forming a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern may include: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, patterning the third insulating film using a patterning process to form a third insulating layer covering the second conductive layer, wherein a plurality of via patterns are provided on the third insulating layer, as shown in FIG19 , which is a schematic diagram of FIG9A after the third insulating layer pattern is formed.

[0306] In an exemplary embodiment, as shown in FIG. 19 , the plurality of via hole patterns may include at least first to twenty-second via holes H1 to H22 .

[0307] In an exemplary embodiment, as shown in FIG19 , the orthographic projection of the first via hole H1 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the first transistor on the substrate, the third insulating layer, the second insulating layer and the first insulating layer within the first via hole H1 are etched away to expose the surface of the first region of the active layer of the first transistor, and the first via hole H1 is configured to connect the first electrode of the subsequently formed first transistor T1 to the first region of the active layer of the first transistor through the via hole.

[0308] In an exemplary embodiment, as shown in FIG19 , the orthographic projection of the second via hole H2 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the first transistor on the substrate, the third insulating layer, the second insulating layer and the first insulating layer within the second via hole H2 are etched away to expose the surface of the second region of the active layer of the first transistor, and the second via hole H2 is configured to connect the second electrode of the subsequently formed first transistor T1 to the second region of the active layer of the first transistor through the via hole.

[0309] In an exemplary embodiment, as shown in FIG19 , the orthographic projection of the third via H3 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the second transistor on the substrate, the third insulating layer, the second insulating layer and the first insulating layer within the third via H3 are etched away to expose the surface of the first region of the active layer of the second transistor, and the third via H3 is configured to connect the first electrode of the subsequently formed second transistor to the first region of the active layer of the second transistor through the via.

[0310] In an exemplary embodiment, as shown in FIG19 , the orthographic projection of the fourth via H4 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the second transistor (also the second region of the active layer of the third transistor) on the substrate, the third insulating layer, the second insulating layer and the first insulating layer within the fourth via H4 are etched away to expose the surface of the second region of the active layer of the second transistor (also the second region of the active layer of the third transistor), and the fourth via H4 is configured to connect the second electrode of the subsequently formed second transistor (also the second electrode of the third transistor) to the second region of the active layer of the second transistor (also the second region of the active layer of the third transistor) through the via.

[0311] In an exemplary embodiment, as shown in FIG19 , the orthographic projection of the fifth via H5 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the third transistor on the substrate, the third insulating layer, the second insulating layer and the first insulating layer within the fifth via H5 are etched away to expose the surface of the first region of the active layer of the third transistor, and the fifth via H5 is configured to connect the first electrode of the subsequently formed third transistor to the first region of the active layer of the third transistor through the via.

[0312] In an exemplary embodiment, as shown in FIG19 , the orthographic projection of the sixth via H6 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the fourth transistor on the substrate, the third insulating layer, the second insulating layer and the first insulating layer within the sixth via H6 are etched away to expose the surface of the first region of the active layer of the fourth transistor, and the sixth via H6 is configured to connect the first electrode of the subsequently formed fourth transistor to the first region of the active layer of the fourth transistor through the via.

[0313] In an exemplary embodiment, as shown in Figure 19, the orthographic projection of the seventh via H7 on the substrate is located within the range of the orthographic projection of the second area of ​​the active layer of the fourth transistor (also the second area of ​​the active layer of the fifth transistor) on the substrate, and the third insulating layer, the second insulating layer and the first insulating layer in the seventh via H7 are etched away to expose the surface of the second area of ​​the active layer of the fourth transistor (also the second area of ​​the active layer of the fifth transistor), and the seventh via H7 is configured to connect the second electrode of the subsequently formed fourth transistor (also the second electrode of the fifth transistor) to the second area of ​​the active layer of the fourth transistor (also the second area of ​​the active layer of the fifth transistor) through the via.

[0314] In an exemplary embodiment, as shown in FIG19 , the orthographic projection of the eighth via H8 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the fifth transistor on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the eighth via H8 are etched away to expose the surface of the first region of the active layer of the fourth transistor, and the eighth via H8 is configured to connect the first electrode of the subsequently formed fifth transistor to the first region of the active layer of the fifth transistor through the via.

[0315] In an exemplary embodiment, as shown in Figure 19, the orthographic projection of the ninth via H9 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the sixth transistor on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the ninth via H9 are etched away to expose the surface of the first area of ​​the active layer of the fourth transistor, and the ninth via H9 is configured to connect the first electrode of the subsequently formed sixth transistor to the first area of ​​the active layer of the sixth transistor through the via.

[0316] In an exemplary embodiment, as shown in Figure 19, the orthographic projection of the tenth via H10 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the seventh transistor on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the tenth via H10 are etched away to expose the surface of the second region of the active layer of the fourth transistor, and the tenth via H10 is configured to connect the second electrode of the subsequently formed seventh transistor to the second region of the active layer of the seventh transistor through the via.

[0317] In an exemplary embodiment, as shown in Figure 19, the orthographic projection of the eleventh via H11 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the eighth transistor on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the eleventh via H11 are etched away to expose the surface of the first region of the active layer of the fourth transistor, and the eleventh via H11 is configured to connect the first electrode of the subsequently formed eighth transistor to the first region of the active layer of the eighth transistor through the via.

[0318] In an exemplary embodiment, as shown in Figure 19, the orthographic projection of the twelfth via H12 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the eighth transistor on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the twelfth via H12 are etched away to expose the surface of the first region of the active layer of the fourth transistor, and the twelfth via H12 is configured to connect the second electrode of the subsequently formed eighth transistor to the second region of the active layer of the eighth transistor through the via.

[0319] In an exemplary embodiment, as shown in FIG19 , the orthographic projection of the thirteenth via H13 on the substrate is located within the range of the orthographic projection of the control electrode of the first transistor on the substrate, the third insulating layer and the second insulating layer in the thirteenth via H13 are etched away to expose the surface of the control electrode of the first transistor, and the thirteenth via H13 is configured to connect the first clock sub-segment of the second clock signal line formed subsequently and the first electrode of the second transistor to the control electrode of the first transistor through the via.

[0320] In an exemplary embodiment, as shown in FIG19 , the orthographic projection of the fourteenth via H14 on the substrate is located within the range of the orthographic projection of the control electrode of the second transistor on the substrate, the third insulating layer and the second insulating layer in the fourteenth via H14 are etched away to expose the surface of the control electrode of the second transistor, and the fourteenth via H14 is configured to connect the second electrode of the subsequently formed first transistor (which is also the second electrode of the seventh transistor and the first electrode of the eighth transistor) to the control electrode of the first transistor through the via.

[0321] In an exemplary embodiment, as shown in FIG19 , the orthographic projection of the fifteenth via H15 on the substrate is located within the range of the orthographic projection of the control electrode of the third transistor on the substrate, the third insulating layer and the second insulating layer in the fifteenth via H15 are etched away to expose the surface of the control electrode of the second transistor, and the fifteenth via H15 is configured to connect the first clock sub-segment of the second clock signal line formed subsequently to the control electrode of the third transistor through the via.

[0322] In an exemplary embodiment, as shown in Figure 19, the orthographic projection of the sixteenth via H16 on the substrate is located within the range of the orthographic projection of the control electrode of the fifth transistor on the substrate, the third insulating layer and the second insulating layer in the sixteenth via H16 are etched away to expose the surface of the control electrode of the fifth transistor, and the sixteenth via H16 is configured to connect the second electrode of the subsequently formed eighth transistor to the control electrode of the fifth transistor through the via.

[0323] In an exemplary embodiment, as shown in FIG19 , the orthographic projection of the seventeenth via H17 on the substrate is located within the range of the orthographic projection of the control electrode of the sixth transistor on the substrate, the third insulating layer and the second insulating layer in the seventeenth via H17 are etched away to expose the surface of the control electrode of the sixth transistor, and the seventeenth via H17 is configured to connect the second electrode of the subsequently formed second transistor (which is also the second electrode of the third transistor) to the control electrode of the sixth transistor through the via.

[0324] In an exemplary embodiment, as shown in FIG19 , the orthographic projection of the eighteenth via H18 on the substrate is located within the range of the orthographic projection of the control electrode of the seventh transistor on the substrate, the third insulating layer and the second insulating layer in the eighteenth via H18 are etched away to expose the surface of the control electrode of the seventh transistor, and the eighteenth via H18 is configured to connect the first electrode, the first clock signal line, and the first clock sub-segment of the subsequently formed fifth transistor to the control electrode of the seventh transistor through the via.

[0325] In an exemplary embodiment, as shown in FIG19 , the orthographic projection of the nineteenth via H19 on the substrate is located within the range of the orthographic projection of the control electrode of the eighth transistor on the substrate, the third insulating layer and the second insulating layer in the nineteenth via H19 are etched away to expose the surface of the control electrode of the eighth transistor, and the nineteenth via H19 is configured to connect the first electrode of the subsequently formed third transistor to the control electrode of the eighth transistor through the via.

[0326] In an exemplary embodiment, as shown in FIG19 , the orthographic projection of the twentieth via hole H20 on the substrate is located within the range of the orthographic projection of the first connecting line on the substrate, the third insulating layer and the second insulating layer in the twentieth via hole H20 are etched away to expose the surface of the first connecting line, and the twentieth via hole H20 is configured to connect the first electrode of the subsequently formed first transistor to the first connecting line through the via hole.

[0327] In an exemplary embodiment, as shown in FIG19 , the orthographic projection of the twenty-first via H21 on the substrate is located within the range of the orthographic projection of the second plate of the first capacitor on the substrate, the third insulating layer in the twenty-first via H21 is etched away to expose the surface of the second plate of the first capacitor, and the twenty-first via H21 is configured to connect the first electrode of the subsequently formed fourth transistor to the second plate of the first capacitor through the via.

[0328] In an exemplary embodiment, as shown in FIG19 , the orthographic projection of the twenty-second via H22 on the substrate is located within the range of the orthographic projection of the second plate of the second capacitor on the substrate, the third insulating layer in the twenty-second via H22 is etched away to expose the surface of the second plate of the second capacitor, and the twenty-second via H22 is configured to connect the second electrode of the subsequently formed fourth transistor (which is also the second electrode of the fifth transistor) to the second plate of the second capacitor through the via.

[0329] In an exemplary embodiment, as shown in Figure 19, the orthographic projection of the twenty-third via H23 on the substrate is located within the range of the orthographic projection of the third output signal line on the substrate, the third insulating layer in the twenty-third via H23 is etched away to expose the surface of the third output signal line, and the twenty-third via H23 is configured to connect the first initial sub-segment of the first initial power supply line formed subsequently to the third output signal line through the via.

[0330] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on the third insulating layer, as shown in Figures 20 and 21 , where Figure 20 is a schematic diagram of the third conductive layer pattern of Figure 9A , and Figure 21 is a schematic diagram of Figure 9A after the third conductive layer pattern is formed. In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0331] In an exemplary embodiment, as shown in Figures 20 and 21, the third conductive layer pattern may include at least: a first clock sub-segment GCK1A of a first clock signal line, a first clock sub-segment GCK2A of a second clock signal line, a second power line VGL, a first initial sub-segment INITL1A of a first initial power supply line, a first initial sub-segment INITL2A of a second initial power supply line, a fourth output signal line OUTL4, the first electrode T13 and the second electrode T14 of a first transistor to the first electrode T53 and the second electrode T54 of a fifth transistor, the first electrode T63 of a sixth transistor, the second electrode T74 of a seventh transistor, and the first electrode T83 and the second electrode T84 of an eighth transistor.

[0332] In an exemplary embodiment, as shown in Figures 20 and 21, the shape of the first clock sub-segment GCK2A of the second clock signal line can be a line shape extending at least partially along the first direction D1, and the first clock sub-segment GCK2A of the second clock signal line is connected to the control electrode of the first transistor through the thirteenth via, and is connected to the control electrode of the third transistor through the fifteenth via.

[0333] In an exemplary embodiment, as shown in Figures 20 and 21, the shape of the first clock sub-segment GCK1A of the first clock signal line can be a line shape extending at least partially along the first direction D1, and is located on a side of the first clock sub-segment GCK2A of the second clock signal line close to the display area. The first clock sub-segment GCK1A of the first clock signal line is connected to the control electrode of the seventh transistor through the eighteenth via.

[0334] In an exemplary embodiment, as shown in Figures 20 and 21, the first clock sub-segment GCK2A of the second clock signal line and the first clock sub-segment GCK1A of the first clock signal line can be designed with equal width, or can be designed with unequal width, can be a straight line, or can be a broken line, which not only facilitates the layout of the scan drive circuit, but also reduces the parasitic capacitance between the signal lines. The present disclosure is not limited here.

[0335] In an exemplary embodiment, as shown in Figures 20 and 21, the second power line VGL and the first electrode T33 of the third transistor are an integral structure. The shape of the second power line VGL can be a line extending at least partially along the first direction D1, and is located on a side of the first clock sub-segment GCK1A of the first clock signal line close to the display area. The first electrode T33 of the third transistor is located on a side of the second power line VGL close to the display area. The first electrode T33 of the third transistor is connected to the first area of ​​the active layer of the third transistor through a fifth via, and is connected to the control electrode of the eighth transistor through a nineteenth via.

[0336] In an exemplary embodiment, the width of the second power line VGL may be smaller than the width of the first clock sub-segment GCK2A of the second clock signal line or the first clock sub-segment GCK1A of the first clock signal line.

[0337] In an exemplary embodiment, as shown in Figures 20 and 21, the first electrode T13 of the first transistor can extend along the second direction D2, the first electrode T13 of the first transistor is connected to the first region of the active layer of the first transistor through a first via, and is connected to the first connecting line through a twentieth via, and the first connecting line is connected to the second electrode of the fourth transistor of the previous level scanning shift register (which is also connected to the second electrode of the fifth transistor) to achieve cascade connection with the current level scanning shift register and the previous level scanning shift register.

[0338] In an exemplary embodiment, as shown in Figures 20 and 21, the second electrode T14 of the first transistor, the second electrode T74 of the seventh transistor, and the first electrode T83 of the eighth transistor can be an integral structure, and can be connected to the second area of ​​the active layer of the first transistor through the second via, to the control electrode of the second transistor through the fourteenth via, to the second area of ​​the active layer of the seventh transistor through the tenth via, and to the first area of ​​the active layer of the eighth transistor through the eleventh via.

[0339] In an exemplary embodiment, as shown in Figures 20 and 21, the first electrode T23 of the second transistor may be in the shape of a line extending along the first direction D1. The first electrode T23 of the second transistor may be connected to the first region of the active layer of the second transistor through a third via hole, and connected to the control electrode of the first transistor through a thirteenth via hole.

[0340] In an exemplary embodiment, as shown in Figures 20 and 21, the second electrode T24 of the second transistor and the second electrode T34 of the third transistor are an integrated structure and can be in the shape of a line extending along the second direction D2. The integrated structure of the second electrode T24 of the second transistor and the second electrode T34 of the third transistor can be connected to the second region of the active layer of the second transistor (also the second region of the active layer of the third transistor) through a fourth via hole, and connected to the control electrode of the sixth transistor through a seventeenth via hole.

[0341] In an exemplary embodiment, as shown in Figures 20 and 21, the second electrode T24 of the second transistor and the second electrode T34 of the third transistor are an integrated structure and can be in the shape of a line extending along the second direction D2. The integrated structure of the second electrode T24 of the second transistor and the second electrode T34 of the third transistor can be connected to the second region of the active layer of the second transistor (also the second region of the active layer of the third transistor) through a fourth via hole, and connected to the control electrode of the sixth transistor through a seventeenth via hole.

[0342] In an exemplary embodiment, as shown in Figures 20 and 21, the first electrode T43 of the fourth transistor and the first electrode T63 of the sixth transistor can be an integral structure and can extend at least partially along the second direction D2. The integral structure of the first electrode T43 of the fourth transistor and the first electrode T63 of the sixth transistor can be connected to the first region of the active layer of the fourth transistor through a sixth via, connected to the first region of the active layer of the sixth transistor through a ninth via, and connected to the second plate of the first capacitor through a twenty-first via.

[0343] In an exemplary embodiment, as shown in Figures 20 and 21, the second electrode T44 of the fourth transistor and the second electrode T54 of the fifth transistor are integrated into a structure and may be shaped like a horizontally flipped "F." The integrated structure of the second electrode T44 of the fourth transistor and the second electrode T54 of the fifth transistor may be connected to the second region of the active layer of the fourth transistor (also the second region of the active layer of the fifth transistor) via a seventh via, and connected to the second plate of the second capacitor via a twenty-second via.

[0344] In an exemplary embodiment, as shown in Figures 20 and 21, the first electrode T53 of the fifth transistor may be shaped like an "n" with its opening facing the display area. The first electrode T53 of the fifth transistor may be connected to the first region of the active layer of the fifth transistor through an eighth via hole, and to the control electrode of the seventh transistor through an eighteenth via hole.

[0345] In an exemplary embodiment, as shown in Figures 20 and 21, the second electrode T84 of the eighth transistor may extend at least partially along the second direction D2. The second electrode T84 of the eighth transistor may be connected to the second region of the active layer of the eighth transistor through a twelfth via hole and to the control electrode of the fifth transistor through a sixteenth via hole.

[0346] In an exemplary embodiment, as shown in Figures 20 and 21, the first initial sub-segment INITL2A of the second initial power supply line and the fourth output signal line OUTL4 are an integrated structure, and the fourth output signal line OUTL4 is located on a side of the first initial sub-segment INITL2A of the second initial power supply line close to the display area.

[0347] In an exemplary embodiment, as shown in Figures 20 and 21, the shape of the first initial sub-segment INITL2A of the second initial power supply line can be a line shape extending at least partially along the first direction D1, and include a plurality of power supply electrodes arranged at intervals. The first initial sub-segment INITL2A of the second initial power supply line can be located on a side of the integrated structure of the second electrode T44 of the fourth transistor and the second electrode T54 of the fifth transistor close to the display area.

[0348] In an exemplary embodiment, as shown in FIG. 20 and FIG. 21 , the fourth output signal line OUTL4 may at least partially extend along the second direction D2 .

[0349] In an exemplary embodiment, as shown in FIG20 and FIG21 , the orthographic projection of the first initial subsegment INITL2A of the second initial power supply line on the substrate at least partially overlaps with the orthographic projections of the second plate of the first capacitor and the second plate of the second capacitor on the substrate.

[0350] In an exemplary embodiment, as shown in Figures 20 and 21, the shape of the first initial sub-segment INITL1A of the first initial power supply line may be a line shape extending at least partially along the first direction D1 and include a plurality of power supply electrodes arranged at intervals. The first initial sub-segment INITL1A of the first initial power supply line may be located on a side of the first initial sub-segment INITL2A of the second initial power supply line close to the display area.

[0351] In an exemplary embodiment, as shown in Figures 20 and 21, the first initial sub-segment INITL1A of the first initial power supply line and the first initial sub-segment INITL2A of the second initial power supply line can be designed with equal width, or can be designed with unequal width, can be a straight line, or can be a broken line, which not only facilitates the layout of the scan drive circuit, but also reduces the parasitic capacitance between the signal lines. The present disclosure is not limited here.

[0352] (6) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the third conductive layer, wherein a plurality of vias are provided on the fourth insulating layer, as shown in FIG. 22 , which is a schematic diagram of FIG. 9A after the fourth insulating layer pattern is formed.

[0353] In an exemplary embodiment, the plurality of via holes include at least a twenty-fourth via hole H24 to a twenty-eighth via hole H28 .

[0354] In an exemplary embodiment, as shown in FIG22 , the orthographic projection of the twenty-fourth via H24 on the substrate is located within the range of the orthographic projection of the first electrode of the fourth transistor on the substrate, the fourth insulating layer of the twenty-fourth via H24 is etched away to expose the surface of the first electrode of the fourth transistor, and the twenty-fourth via H24 is configured to connect a subsequently formed first power line to the first electrode of the fourth transistor through the via.

[0355] In an exemplary embodiment, as shown in Figure 22, the orthographic projection of the twenty-fifth via H25 on the substrate is located within the range of the orthographic projection of the first clock sub-segment of the second clock signal line on the substrate, the fourth insulating layer of the twenty-fourth via H24 is etched away to expose the surface of the first clock sub-segment of the second clock signal line, and the twenty-fourth via H24 is configured to connect the subsequently formed second clock sub-segment of the second clock signal line with the first clock sub-segment of the second clock signal line through the via.

[0356] In an exemplary embodiment, as shown in Figure 22, the orthographic projection of the twenty-sixth via H26 on the substrate is located within the range of the orthographic projection of the first clock sub-segment of the first clock signal line on the substrate, the fourth insulating layer of the twenty-fifth via H25 is etched away to expose the surface of the first clock sub-segment of the first clock signal line, and the twenty-fifth via H25 is configured to connect the subsequently formed second clock sub-segment of the first clock signal line with the first clock sub-segment of the first clock signal line through the via.

[0357] In an exemplary embodiment, as shown in Figure 22, the orthographic projection of the twenty-seventh via H27 on the substrate is located within the range of the orthographic projection of the first initial sub-segment of the second initial power supply line on the substrate, the fourth insulating layer of the twenty-seventh via H27 is etched away, exposing the surface of the first initial sub-segment of the second initial power supply line, and the twenty-seventh via H27 is configured to connect the second initial sub-segment of the second initial power supply line formed subsequently to the first initial sub-segment of the second initial power supply line through the via.

[0358] In an exemplary embodiment, as shown in Figure 22, the orthographic projection of the twenty-eighth via H28 on the substrate is located within the range of the orthographic projection of the first initial sub-segment of the first initial power supply line on the substrate, the fourth insulating layer of the twenty-eighth via H28 is etched away to expose the surface of the first initial sub-segment of the first initial power supply line, and the twenty-eighth via H28 is configured to connect the subsequently formed second initial sub-segment of the first initial power supply line to the first initial sub-segment of the first initial power supply line through the via.

[0359] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the fourth insulating layer, as shown in FIG23 and FIG24 , where FIG23 is a schematic diagram of the fourth conductive layer of FIG9A , and FIG24 is a schematic diagram of forming the fourth conductive layer of FIG9A . In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0360] In an exemplary embodiment, as shown in Figures 23 and 24, the fourth conductive layer pattern may include at least: a second clock sub-segment GCK1B of the first clock signal line, a second clock sub-segment GCK2B of the second clock signal line, a first power line VGH, a second initial sub-segment INITL1B of the first initial power supply line, a second initial sub-segment INITL2B of the second initial power supply line, a first initial signal line GSTV, and a second initial signal line ESTV.

[0361] In an exemplary embodiment, as shown in Figures 23 and 24, the shape of the second clock sub-segment GCK2B of the second clock signal line can be a line shape extending at least partially along the first direction D1, and the orthographic projection of the second clock sub-segment GCK2B of the second clock signal line on the substrate at least partially overlaps with the orthographic projection of the first clock sub-segment of the second clock signal line on the substrate, and is connected to the first clock sub-segment of the second clock signal line through the twenty-fifth via to form a second clock signal line.

[0362] In an exemplary embodiment, as shown in Figures 23 and 24, the shape of the second clock sub-segment GCK1B of the first clock signal line can be a line shape extending at least partially along the first direction D1, and the orthographic projection of the second clock sub-segment GCK1B of the first clock signal line on the substrate at least partially overlaps with the orthographic projection of the first clock sub-segment of the first clock signal line on the substrate, and is connected to the first clock sub-segment of the first clock signal line through the twenty-sixth via to form the first clock signal line.

[0363] In an exemplary embodiment, as shown in Figures 23 and 24, the second initial sub-segment GCK2B of the second clock signal line and the second clock sub-segment GCK1B of the first clock signal line can be designed with equal width, or can be designed with unequal width, can be a straight line, or can be a broken line, which not only facilitates the layout of the scan drive circuit, but also reduces the parasitic capacitance between the signal lines. The present disclosure is not limited here.

[0364] In an exemplary embodiment, as shown in Figures 23 and 24, the second initial signal line ESTV is located on a side of the second clock sub-segment GCK1B of the first clock signal line close to the display area, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first electrode of the third transistor on the substrate.

[0365] In an exemplary embodiment, as shown in FIG23 and FIG24 , the first initial signal line GSTV is located on a side of the second initial signal line ESTV close to the display area, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the control electrode of the eighth transistor on the substrate.

[0366] In an exemplary embodiment, as shown in Figures 23 and 24, the second initial signal line ESTV and the first initial signal line GSTV can be designed with equal width, or can be designed with unequal width, can be straight lines, or can be broken lines, which not only facilitates the layout of the scan drive circuit, but also reduces the parasitic capacitance between the signal lines. The present disclosure is not limited here.

[0367] In an exemplary embodiment, as shown in Figures 23 and 24, the shape of the first power line VGH can be a line shape extending at least partially along the first direction D1, and the orthographic projection of the first power line VGH on the substrate at least partially overlaps with the second electrode of the fourth transistor (also the second electrode of the fifth transistor) and the orthographic projection of the first electrode of the fourth transistor on the substrate, and is connected to the first electrode of the fourth transistor through the twenty-fourth via.

[0368] In an exemplary embodiment, as shown in Figures 23 and 24, the shape of the second initial sub-segment INITL2B of the second initial power supply line can be a line shape extending at least partially along the first direction D1, and the orthographic projection of the second initial sub-segment INITL2B of the second initial power supply line on the substrate at least partially overlaps with the orthographic projection of the first initial sub-segment of the second initial power supply line on the substrate, and is connected to the first initial sub-segment of the second initial power supply line through the twenty-seventh via hole to form a second initial power supply line.

[0369] In an exemplary embodiment, as shown in Figures 23 and 24, the shape of the second initial sub-segment INITL1B of the first initial power supply line can be a line shape extending at least partially along the first direction D1, and the orthographic projection of the second initial sub-segment INITL1B of the first initial power supply line on the substrate at least partially overlaps with the orthographic projection of the first initial sub-segment of the first initial power supply line on the substrate, and is connected to the first initial sub-segment of the first initial power supply line through the twenty-eighth via hole to form the first initial power supply line.

[0370] In an exemplary embodiment, as shown in Figures 23 and 24, the second initial sub-segment INITL2B of the second initial power supply line and the second initial sub-segment INITL1B of the first initial power supply line can be designed with equal width, or can be designed with unequal width, can be a straight line, or can be a broken line, which not only facilitates the layout of the scan drive circuit, but also reduces the parasitic capacitance between the signal lines. The present disclosure is not limited here.

[0371] (8) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer pattern may include: sequentially depositing a fifth insulating film and a fifth conductive film on the substrate having the aforementioned pattern formed thereon, patterning the fifth conductive film through a patterning process to form a fourth insulating layer covering the fourth conductive layer pattern, and forming the fifth conductive layer pattern disposed on the fourth insulating layer. In an exemplary embodiment, the fifth conductive layer may be referred to as a third source / drain metal (SD3) layer.

[0372] In example embodiments, the fifth conductive layer pattern may include at least a first output connection line, a second output connection line, a third output connection line, and a fourth output connection line.

[0373] In an exemplary embodiment, the first output connection line is connected to the first output signal line, the second output connection line is connected to the second output signal line, the third output connection line is connected to the third output signal line, and the fourth output connection line is connected to the fourth output signal line.

[0374] At this point, the driving circuit layer is completed on the substrate. The driving circuit layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a fifth insulating layer, and a fifth conductive layer sequentially arranged on the substrate.

[0375] In an exemplary embodiment, the semiconductor layer may be a metal oxide layer. The metal oxide layer may be an oxide comprising indium and tin, an oxide comprising tungsten and indium, an oxide comprising tungsten, indium and zinc, an oxide comprising titanium and indium, an oxide comprising titanium, indium and tin, an oxide comprising indium and zinc, an oxide comprising silicon, indium and tin, or an oxide comprising indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer. The active layer thin film may be made of various materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, polythiophene, etc., that is, the present disclosure is applicable to transistors manufactured based on oxide oxide technology, silicon technology, and organic technology.

[0376] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0377] In exemplary embodiments, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer may be formed of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first insulating layer and the second insulating layer may be referred to as gate insulating (GI) layers, the third insulating layer and the fourth insulating layer may be referred to as interlayer insulating (ILD) layers, and the fifth insulating layer may be referred to as a passivation (PVX) layer.

[0378] In an exemplary embodiment, when the second output signal line has a double-layer structure, the second conductive layer pattern formed in step (3) includes the first output sub-segment of the second output signal line, and between steps (3) and (4), the following steps may be included: forming a sixth conductive layer pattern. Forming the sixth conductive layer pattern may include: sequentially depositing a sixth insulating film and a sixth conductive film on the substrate on which the aforementioned pattern is formed, patterning the sixth conductive film through a patterning process to form a sixth insulating layer covering the second conductive layer pattern, and a sixth conductive layer pattern disposed on the sixth insulating layer.

[0379] In example embodiments, the sixth conductive layer pattern may include at least a second output sub-segment of the second output signal line.

[0380] In an exemplary embodiment, step (4) forms a fourth insulating layer covering the sixth conductive layer, and subsequent steps are the same as the process of forming FIG. 9A in the aforementioned embodiment, which will not be described in detail in this disclosure.

[0381] In an exemplary embodiment, the sixth conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0382] In exemplary embodiments, the sixth insulating layer may be formed of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.

[0383] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer is prepared on the driving circuit layer. The preparation process of the light emitting structure layer may include the following operations.

[0384] (9) Forming a light-emitting structure layer. In an exemplary embodiment, forming the light-emitting structure layer may include: coating a first flat film on the substrate having the aforementioned pattern formed thereon, patterning the first flat film using a patterning process to form a first flat layer, depositing an anode conductive film on the substrate having the aforementioned pattern formed thereon, patterning the anode conductive film using a patterning process to form an anode conductive layer disposed on the flat layer, the anode conductive layer including at least a plurality of anode patterns, coating a pixel definition film on the substrate having the aforementioned pattern formed thereon, patterning the pixel definition film using a patterning process to form a pixel definition layer, forming an organic light-emitting layer on the substrate having the aforementioned pattern formed thereon by first using an evaporation or inkjet printing process, then forming a cathode on the organic light-emitting layer, and then forming an encapsulation structure layer.

[0385] In an exemplary embodiment, the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0386] In exemplary embodiments, the material of the pixel definition layer may include polyimide, acryl, or polyethylene terephthalate.

[0387] In exemplary embodiments, the planarization layer may employ an organic material.

[0388] In an exemplary embodiment, the anode thin film may employ indium tin oxide (ITO) or indium zinc oxide (IZO).

[0389] In exemplary embodiments, the cathode film may be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy made of any one or more of the foregoing metals.

[0390] The following is an exemplary description of the preparation process using FIG. 10A , which shows a virtual scanning shift register. The virtual scanning shift register includes a first transistor DT1 , a second transistor DT2 , and fourth to eighth transistors DT4 to DT8 .

[0391] (1) Forming a semiconductor layer pattern on a substrate. In an exemplary embodiment, forming the semiconductor layer pattern may include: depositing a semiconductor thin film on the substrate, and patterning the semiconductor thin film through a patterning process to form a semiconductor layer pattern, as shown in FIG. 25 , which is a schematic diagram of FIG. 10A after the semiconductor layer pattern is formed.

[0392] In exemplary embodiments, as shown in FIG. 25 , the semiconductor layer pattern may include an active layer DT11 of a first transistor, an active layer DT21 of a second transistor, and active layers DT41 to DT81 of fourth to eighth transistors.

[0393] In an exemplary embodiment, the positions and structures of the active layers DT11 of the first transistor, DT21 of the second transistor, and DT61 of the sixth transistor through DT81 of the eighth transistor in FIG25 are identical to those of the active layers T11 of the first transistor, T21 of the second transistor, and T61 of the sixth transistor through T81 of the eighth transistor in FIG14 . The difference is that the active layers DT41 of the fourth transistor and DT51 of the fifth transistor in FIG25 may be integrally formed in an “I” shape.

[0394] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a first insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a first insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the first insulating layer, as shown in FIG26 and FIG27 , FIG26 is a schematic diagram of the first conductive layer pattern of FIG10A , and FIG27 is a schematic diagram of FIG10A after the first conductive layer pattern is formed. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0395] In exemplary embodiments, as shown in FIG. 26 and FIG. 27 , the first conductive layer pattern may include at least the control electrodes DT12 , DT22 , DT42 to DT82 of the first to eighth transistors, and a first connection line VL1 .

[0396] In an exemplary embodiment, as shown in Figures 26 and 27, the control electrode DT42 of the fourth transistor, the control electrode DT62 of the sixth transistor to the control electrode DT82 of the eighth transistor are an integrated structure, and the control electrode DT12 of the first transistor, the control electrode DT22 of the second transistor and the control electrode DT52 of the fifth transistor can be set separately.

[0397] In an exemplary embodiment, shapes of the control electrodes T12 and DT22 of the first and second transistors and the first connection line VL1 in FIG. 26 are the same as those in FIG. 15 .

[0398] In an exemplary embodiment, as shown in Figures 26 and 27, the control electrode DT42 of the fourth transistor may be a comb structure with an opening toward the display area, the control electrodes DT62 of the sixth transistor to the control electrodes DT82 of the eighth transistor are located on the side of the comb back of the control electrode DT42 of the fourth transistor away from the display area, the control electrode DT62 of the sixth transistor and the control electrode DT72 of the seventh transistor may be a line shape extending along the second direction D2, and the control electrode DT82 of the eighth transistor may be an "n" type with an opening toward the display area.

[0399] (3) Forming a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern may include: depositing a second insulating film and a third insulating film on the substrate on which the aforementioned pattern is formed, patterning the second insulating film and the third insulating film using a patterning process to form a second insulating layer and a third insulating layer covering the first conductive layer, wherein a plurality of via patterns are provided on the third insulating layer, as shown in FIG. 28 , which is a schematic diagram of FIG. 10A after the third insulating layer pattern is formed.

[0400] In an exemplary embodiment, as shown in FIG28 , the plurality of via patterns may include at least the first via H1 to the seventeenth via H17. The first via H1 to the eleventh via H11 are opened in the first insulating layer to the third insulating layer, and the twelfth via H12 to the seventeenth via H17 are opened in the second insulating layer and the third insulating layer. The first via H1 exposes the first region of the active layer of the first transistor, the second via H2 exposes the second region of the active layer of the first transistor, the third via H3 exposes the first region of the active layer of the second transistor, the fourth via H4 exposes the second region of the active layer of the second transistor, the fifth via H5 exposes the first region of the active layer of the fourth transistor, the sixth via H6 exposes the second region of the active layer of the fourth transistor (the second region of the active layer of the fifth transistor), and the seventh via H7 exposes the second region of the active layer of the fourth transistor (the second region of the active layer of the fifth transistor). The first area of ​​the active layer of the fifth transistor is exposed, the eighth via hole H8 exposes the first area of ​​the active layer of the sixth transistor, the ninth via hole H9 exposes the second area of ​​the active layer of the seventh transistor, the tenth via hole H10 exposes the first area of ​​the active layer of the eighth transistor, the eleventh via hole H11 exposes the second area of ​​the active layer of the eighth transistor, the twelfth via hole H12 exposes the control electrode of the first transistor, the thirteenth via hole H13 exposes the control electrode of the second transistor, the fourteenth via hole H14 exposes the control electrode of the sixth transistor, the fifteenth via hole H15 exposes the control electrode of the fifth transistor, the sixteenth via hole H16 exposes the control electrode of the fourth transistor, and the seventeenth via hole H17 exposes the first connecting line.

[0401] (4) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on the third insulating layer, as shown in Figures 29 and 30 . Figure 29 is a schematic diagram of the third conductive layer pattern of Figure 10A , and Figure 30 is a schematic diagram of Figure 10A after the third conductive layer pattern is formed. In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0402] In an exemplary embodiment, as shown in Figures 29 and 30, the third conductive layer pattern may include at least: a first clock sub-segment GCK1A of a first clock signal line, a first clock sub-segment GCK2A of a second clock signal line, a second power line VGL, a first initial sub-segment INITL1A of a first initial power supply line, a first initial sub-segment INITL2A of a second initial power supply line, a first electrode T13 and a second electrode T14 of a first transistor, a first electrode T23 and a second electrode T24 of a second transistor, a first electrode T43 and a second electrode T44 of a fourth transistor, a first electrode T53 and a second electrode T54 of a fifth transistor, a first electrode T63 of a sixth transistor, a second electrode T74 of a seventh transistor, and a first electrode T83 and a second electrode T84 of an eighth transistor.

[0403] In an exemplary embodiment, the first clock sub-segment GCK2A of the second clock signal line, the first clock sub-segment GCK1A of the first clock signal line, the second power line VGL, the first initial sub-segment INITL1A of the first initial power supply line, and the first initial sub-segment INITL2A of the second initial power supply line in Figures 29 and 30 are the same as the first clock sub-segment GCK2A of the second clock signal line, the first clock sub-segment GCK1A of the first clock signal line, the second power line VGL, the first initial sub-segment INITL1A of the first initial power supply line, and the first initial sub-segment INITL2A of the second initial power supply line in Figures 20 and 21.

[0404] In an exemplary embodiment, as shown in Figures 29 and 30, the second power line VGL is integrated with the second electrode of the first transistor, the first electrode T23 and the second electrode T24 of the second transistor, the second electrode T74 of the seventh transistor, and the first electrode T83 of the eighth transistor. The second electrode of the first transistor, the first electrode T23 and the second electrode T24 of the second transistor, the second electrode T74 of the seventh transistor, and the first electrode T83 of the eighth transistor are located on a side of the second power line VGL close to the display area. The integrated structure of the second power line VGL, the second electrode of the first transistor, the first electrode T23 and the second electrode T24 of the second transistor, the second electrode T74 of the seventh transistor, and the first electrode T83 of the eighth transistor are connected to the first area of ​​the active layer of the first transistor through the second via hole, to the first area of ​​the active layer of the second transistor through the third via hole, to the second area of ​​the active layer of the second transistor through the fourth via hole, to the second area of ​​the active layer of the seventh transistor through the ninth via hole, to the first area of ​​the active layer of the eighth transistor through the tenth via hole H10, and to the control electrode of the first transistor through the twelfth via hole.

[0405] In an exemplary embodiment, the first electrode T13 of the first transistor shown in FIG. 29 and FIG. 30 is the same as the first electrode T13 of the first transistor in FIG. 20 and FIG. 21 .

[0406] In an exemplary embodiment, as shown in Figures 29 and 30, the first electrode T43 and the second electrode T44 of the fourth transistor, the first electrode T53 and the second electrode T54 of the fifth transistor, the first electrode T63 of the sixth transistor, and the second electrode T84 of the eighth transistor are an integrated structure, and are connected to the first area of ​​the active layer of the fourth transistor through a fifth via, connected to the second area of ​​the active layer of the fourth transistor (the second area of ​​the active layer of the fifth transistor) through a sixth via, connected to the first area of ​​the active layer of the fifth transistor through a seventh via, connected to the first area of ​​the active layer of the sixth transistor through an eighth via, connected to the second area of ​​the active layer of the eighth transistor through an eleventh via, connected to the control electrode of the second transistor through a thirteenth via, connected to the control electrode of the fifth transistor through a fifteenth via, and connected to the control electrode of the fourth transistor through a sixteenth via.

[0407] (5) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth insulating film and a fourth conductive film in sequence on the substrate having the aforementioned pattern formed thereon, patterning the fourth insulating film and the fourth conductive film using a patterning process to form a fourth insulating layer covering the third conductive layer and a fourth conductive layer disposed on the fourth insulating layer, as shown in FIG31 and FIG32 , FIG31 is a schematic diagram of the fourth conductive layer of FIG10A , and FIG32 is a schematic diagram of forming the fourth conductive layer of FIG10A . In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0408] In an exemplary embodiment, as shown in Figures 31 and 32, the fourth conductive layer pattern may include at least: a second clock sub-segment GCK1B of the first clock signal line, a second clock sub-segment GCK2B of the second clock signal line, a first power line VGH, a second initial sub-segment INITL1B of the first initial power supply line, a second initial sub-segment INITL2B of the second initial power supply line, a first initial signal line GSTV, and a second initial signal line ESTV. The second clock sub-segment GCK1B of the first clock signal line, the second clock sub-segment GCK2B of the second clock signal line, the first power line VGH, the second initial sub-segment INITL1B of the first initial power supply line, the second initial sub-segment INITL2B of the second initial power supply line, the first initial signal line GSTV and the second initial signal line ESTV in Figures 31 and 32 have the same structure as the second clock sub-segment GCK1B of the first clock signal line, the second clock sub-segment GCK2B of the second clock signal line, the first power line VGH, the second initial sub-segment INITL1B of the first initial power supply line, the second initial sub-segment INITL2B of the second initial power supply line, the first initial signal line GSTV and the second initial signal line ESTV in Figures 23 and 24, the difference lies in the spacing between the signal lines.

[0409] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer is prepared on the driving circuit layer. The preparation process of the light emitting structure layer is consistent with the preparation process provided in the above embodiment and will not be repeated here.

[0410] The following is an exemplary description of the preparation process using FIG. 10B , which shows a virtual scanning shift register. The virtual scanning shift register includes a first transistor DT1 , a second transistor DT2 , and sixth to eighth transistors DT6 to DT8 .

[0411] (1) Forming a semiconductor layer pattern on a substrate. In an exemplary embodiment, forming the semiconductor layer pattern may include: depositing a semiconductor thin film on the substrate, and patterning the semiconductor thin film through a patterning process to form a semiconductor layer pattern, as shown in FIG33 , which is a schematic diagram of FIG10B after the semiconductor layer pattern is formed.

[0412] In exemplary embodiments, as shown in FIG. 33 , the semiconductor layer pattern may include an active layer DT11 of a first transistor, an active layer DT21 of a second transistor, and active layers DT61 to DT81 of sixth to eighth transistors.

[0413] In an exemplary embodiment, the active layer DT11 of the first transistor, the active layer DT21 of the second transistor, and the active layer DT61 of the sixth transistor to the active layer DT81 of the eighth transistor in FIG33 are the same in position and structure as the active layer T11 of the first transistor, the active layer T21 of the second transistor, and the active layer T61 of the sixth transistor to the active layer T81 of the eighth transistor in FIG14.

[0414] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a first insulating film and a first conductive film on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process to form a first insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the first insulating layer, as shown in Figures 34 and 35, where Figure 34 is a schematic diagram of the first conductive layer pattern of Figure 10B, and Figure 35 is a schematic diagram of Figure 10B after the first conductive layer pattern is formed. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0415] In an exemplary embodiment, as shown in Figures 34 and 35, the first conductive layer pattern may include at least: a control electrode DT12 of the first transistor, a control electrode DT22 of the second transistor, a control electrode DT62 of the sixth transistor to a control electrode DT82 of the eighth transistor, a first connection line VL1 and a second connection line VL2.

[0416] In an exemplary embodiment, as shown in FIG. 34 and FIG. 35 , the control electrodes T62 of the sixth transistor to DT82 of the eighth transistor are an integrated structure, as are the control electrodes DT12 of the first transistor and DT22 of the second transistor.

[0417] In an exemplary embodiment, shapes of the control electrodes T12 and DT22 of the first and second transistors and the first connection line VL1 in FIG. 34 are the same as those in FIG. 25 .

[0418] (3) Forming a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern may include: depositing a second insulating film and a third insulating film on the substrate on which the aforementioned pattern is formed, patterning the second insulating film and the third insulating film using a patterning process to form a second insulating layer and a third insulating layer covering the first conductive layer, wherein a plurality of via patterns are provided on the third insulating layer, as shown in FIG36 , which is a schematic diagram of FIG10B after the third insulating layer pattern is formed.

[0419] 36 , the plurality of via patterns may include at least first to thirteenth vias H1 to H13 . The first to eighth vias H1 to H8 are opened in the first to third insulating layers, and the ninth to thirteenth vias H9 to H13 are opened in the second and third insulating layers. Among them, the first via hole H1 exposes the first area of ​​the active layer of the first transistor, the second via hole H2 exposes the second area of ​​the active layer of the first transistor, the third via hole H3 exposes the first area of ​​the active layer of the second transistor, the fourth via hole H4 exposes the second area of ​​the active layer of the second transistor, the fifth via hole H5 exposes the first area of ​​the active layer of the sixth transistor, the sixth via hole H6 exposes the second area of ​​the active layer of the seventh transistor, the seventh via hole H7 exposes the first area of ​​the active layer of the eighth transistor, the eighth via hole H8 exposes the second area of ​​the active layer of the eighth transistor, the ninth via hole H9 exposes the control electrode of the first transistor, the tenth via hole H10 exposes the control electrode of the second transistor, the eleventh via hole H11 exposes the integrated structure of the control electrodes of the sixth transistor, the seventh transistor and the eighth transistor, the twelfth via hole H12 exposes the first connecting line, and the thirteenth via hole H13 exposes the second connecting line.

[0420] (4) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on the third insulating layer, as shown in Figures 37 and 38 , where Figure 37 is a schematic diagram of the third conductive layer pattern of Figure 10B , and Figure 38 is a schematic diagram of Figure 10B after the third conductive layer pattern is formed. In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0421] In an exemplary embodiment, as shown in Figures 37 and 38, the third conductive layer pattern may include at least: a first clock sub-segment GCK1A of the first clock signal line, a first clock sub-segment GCK2A of the second clock signal line, a second power line VGL, a first initial sub-segment INITL1A of the first initial power supply line, a first initial sub-segment INITL2A of the second initial power supply line, a first electrode T13 and a second electrode T14 of the first transistor, a first electrode T23 and a second electrode T24 of the second transistor, a first electrode T63 of the sixth transistor, a second electrode T74 of the seventh transistor, and a first electrode T83 and a second electrode T84 of the eighth transistor.

[0422] In an exemplary embodiment, the first clock sub-segment GCK2A of the second clock signal line, the first clock sub-segment GCK1A of the first clock signal line, the second power line VGL, the first initial sub-segment INITL1A of the first initial power supply line, and the first initial sub-segment INITL2A of the second initial power supply line in Figures 37 and 38 are the same as the first clock sub-segment GCK2A of the second clock signal line, the first clock sub-segment GCK1A of the first clock signal line, the second power line VGL, the first initial sub-segment INITL1A of the first initial power supply line, and the first initial sub-segment INITL2A of the second initial power supply line in Figures 20 and 21.

[0423] In an exemplary embodiment, as shown in Figures 37 and 38, the second power line VGL is integrated with the second electrode of the first transistor, the first electrode T23 and the second electrode T24 of the second transistor, the second electrode T74 of the seventh transistor, and the first electrode T83 of the eighth transistor. The integrated structure of the second power line VGL, the second electrode of the first transistor, the first electrode T23 and the second electrode T24 of the second transistor, the second electrode T74 of the seventh transistor, and the first electrode T83 of the eighth transistor in Figures 37 and 28 is the same as the second power line VGL, the second electrode of the first transistor, the first electrode T23 and the second electrode T24 of the second transistor, the second electrode T74 of the seventh transistor, and the first electrode T83 of the eighth transistor in Figures 30 and 31, and is connected to the first region of the active layer of the first transistor through the second via hole, to the first region of the active layer of the second transistor through the third via hole, to the second region of the active layer of the second transistor through the fourth via hole, to the second region of the active layer of the seventh transistor through the sixth via hole, to the first region of the active layer of the eighth transistor through the seventh via hole, and to the control electrode of the first transistor through the ninth via hole.

[0424] In an exemplary embodiment, as shown in Figures 37 and 38, the first electrode T13 of the first transistor, the first electrode T63 of the sixth transistor, and the second electrode T84 of the eighth transistor are an integrated structure, and are connected to the first area of ​​the active layer of the first transistor through the first via, to the first connecting line through the twelfth via, to the first area of ​​the active layer of the sixth transistor through the fifth via, to the second area of ​​the active layer of the eighth transistor through the eighth via, the integrated structure of the control electrode of the sixth transistor, the control electrode of the seventh transistor, and the control electrode of the eighth transistor is exposed through the eleventh via, and is connected to the second connecting line through the thirteenth via.

[0425] (5) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth insulating film and a fourth conductive film in sequence on the substrate having the aforementioned pattern formed thereon, patterning the fourth insulating film and the fourth conductive film using a patterning process to form a fourth insulating layer covering the third conductive layer and a fourth conductive layer disposed on the fourth insulating layer, as shown in Figures 39 and 40, where Figure 39 is a schematic diagram of the fourth conductive layer of Figure 10B, and Figure 40 is a schematic diagram of the fourth conductive layer formed in Figure 10B. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0426] In an exemplary embodiment, as shown in Figures 39 and 40, the fourth conductive layer pattern may include at least: a second clock sub-segment GCK1B of the first clock signal line, a second clock sub-segment GCK2B of the second clock signal line, a first power line VGH, a second initial sub-segment INITL1B of the first initial power supply line, a second initial sub-segment INITL2B of the second initial power supply line, a first initial signal line GSTV, and a second initial signal line ESTV. The second clock sub-segment GCK1B of the first clock signal line, the second clock sub-segment GCK2B of the second clock signal line, the first power line VGH, the second initial sub-segment INITL1B of the first initial power supply line, the second initial sub-segment INITL2B of the second initial power supply line, the first initial signal line GSTV and the second initial signal line ESTV in Figures 39 and 40 have the same structure as the second clock sub-segment GCK1B of the first clock signal line, the second clock sub-segment GCK2B of the second clock signal line, the first power line VGH, the second initial sub-segment INITL1B of the first initial power supply line, the second initial sub-segment INITL2B of the second initial power supply line, the first initial signal line GSTV and the second initial signal line ESTV in Figures 23 and 24, and the difference lies in the spacing between the signal lines.

[0427] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer is prepared on the driving circuit layer. The preparation process of the light emitting structure layer is consistent with the preparation process provided in the above embodiment and will not be repeated here.

[0428] The width of the scanning shift register in the display substrate provided by the embodiment of the present disclosure may be approximately 200 micrometers to 220 micrometers. For example, the width of the scanning shift register in the display substrate may be approximately 210 micrometers.

[0429] After simulation, the load at the same position of the display substrate provided by the embodiment of the present disclosure and the reference display substrate, as well as the rising and falling time of the data signal, were compared, and it was found that there was little difference between the two. That is, the display substrate provided by the embodiment of the present disclosure reduces the area occupied by the border area of ​​the display substrate without affecting the image quality, thereby achieving a narrow border.

[0430] The display substrate of the embodiment of the present disclosure can be applied to display products of any resolution.

[0431] An embodiment of the present disclosure further provides a display device, including: a display substrate.

[0432] In an exemplary embodiment, the display device may be a monitor, a television, a mobile phone, a tablet computer, a navigator, a digital photo frame, a wearable display product, or any product or component having a display function.

[0433] The display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be repeated here.

[0434] The drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure, and other structures may refer to general designs.

[0435] For the sake of clarity, the thickness and size of layers or microstructures in the drawings used to describe the embodiments of the present disclosure are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0436] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display substrate, comprising: A substrate and a driving circuit layer disposed on the substrate, the substrate comprising: a display area and a non-display area, the driving circuit layer comprising: a pixel driving circuit located in the display area, a gate driving circuit located in the non-display area and at least one initial power supply line, the initial power supply line at least partially extending along a first direction; The gate driving circuit is configured to provide a driving signal to the pixel driving circuit, and the initial power supply line is configured to provide an initial signal to the pixel driving circuit; An orthographic projection of at least one of the initial power supply lines on the substrate at least partially overlaps with an orthographic projection of the gate driving circuit on the substrate.

2. The display substrate according to claim 1, wherein: The gate driving circuit includes: a plurality of driving circuits arranged along a second direction, the first direction intersecting with the second direction; An orthographic projection of at least one of the initial power supply lines on the substrate at least partially overlaps with an orthographic projection of a driving circuit close to the display area among the plurality of driving circuits on the substrate.

3. The display substrate according to claim 2, wherein: The pixel driving circuit includes: a light emitting transistor and a writing transistor, the multiple driving circuits include: a light emitting driving circuit and a scanning driving circuit, the light emitting driving circuit is electrically connected to the light emitting transistor, the scanning driving circuit is electrically connected to the writing transistor, and the scanning driving circuit is located on a side of the light emitting driving circuit close to the display area; An orthographic projection of at least one initial power supply line on the substrate at least partially overlaps with an orthographic projection of the scan driving circuit on the substrate.

4. The display substrate according to claim 2, wherein: The pixel driving circuit comprises: a light emitting transistor, a writing transistor and a control transistor, the multiple driving circuits comprise: a light emitting driving circuit, a scanning driving circuit and a control driving circuit, the light emitting driving circuit is electrically connected to the light emitting transistor, the scanning driving circuit is electrically connected to the writing transistor, the control driving circuit is electrically connected to the control transistor, and the transistor types of the writing transistor and the control transistor are opposite; the light emitting driving circuit and the control driving circuit are located on a side of the scanning driving circuit away from the display area; An orthographic projection of at least one of the initial power supply lines on the substrate at least partially overlaps with an orthographic projection of the scan driving circuit on the substrate.

5. The display substrate according to claim 3 or 4, wherein: The at least one initial power supply line includes: a first initial power supply line to an Nth initial power supply line, where N is a positive integer greater than or equal to 1; When N is greater than or equal to 2, N initial power supply lines are arranged along the second direction, and the orthographic projections of K adjacent initial power supply lines away from the display area on the substrate at least partially overlap with the orthographic projection of the scan drive circuit on the substrate, and K is a positive integer less than or equal to N.

6. The display substrate according to claim 5, wherein: The driving circuit layer further includes: a first clock signal line, a second clock signal line, a first initial signal line, a first power line, and a second power line located in the non-display area, wherein the first clock signal line, the second clock signal line, the first initial signal line, the first power line, and the second power line at least partially extend along a first direction; The scan driving circuit is electrically connected to the first clock signal line, the second clock signal line, the first power line, the second power line and the first initial signal line respectively; The second clock signal line is located on a side of the first clock signal line away from the display area, the second power line is located on a side of the first clock signal line close to the display area, the first initial signal line is located on a side of the second power line close to the display area, the first power line is located on a side of the first initial signal line close to the display area, and the at least one initial power supply line is located on a side of the first power line close to the display area.

7. The display substrate according to claim 6, wherein: The driving circuit layer further includes: a second initial signal line located in the non-display area, the second initial signal line at least partially extending along the first direction; The light emitting driving circuit is electrically connected to the second initial signal line, and the second initial signal line is located between the second power line and the first initial signal line.

8. The display substrate according to claim 7, wherein: The driving circuit layer further includes: a first output signal line and a second output signal line located in the non-display area, wherein the first output signal line and the second output signal line at least partially extend along the second direction; The first output signal line is located on a side of the scan driving circuit close to the display area, and is electrically connected to the scan driving circuit and the pixel driving circuit respectively; The second output signal line passes through the scan driving circuit and is electrically connected to the pixel driving circuit and one of the light emitting driving circuit and the control driving circuit.

9. The display substrate according to claim 8, wherein: The driving circuit layer further includes: a first output connection line and a second output connection line located in the display area and the non-display area, wherein the first output connection line and the second output connection line at least partially extend along the second direction; The first output connection lines are electrically connected to the first output signal lines and the pixel driving circuit respectively; The second output connection lines are electrically connected to the second output signal lines and the pixel driving circuit respectively.

10. The display substrate according to claim 9, wherein: When N=2, the driving circuit layer further includes: a third output connection line and a fourth output connection line, wherein the third output connection line and the fourth output connection line at least partially extend along the second direction; The third output connection line is electrically connected to the first initial power supply line and the pixel driving circuit respectively; The fourth output connection line is electrically connected to the second initial power supply line and the pixel driving circuit respectively.

11. The display substrate according to any one of claims 6 to 10, wherein: The boundary of the display area includes an arc-shaped boundary, and the non-display area outside the arc-shaped boundary is called a rounded corner area; The scanning driving circuit comprises: a plurality of scanning shift registers and a plurality of virtual scanning shift registers, the plurality of scanning shift registers are cascaded, and the plurality of virtual scanning shift registers are interspersed between the plurality of scanning shift registers; A plurality of dummy scan shift registers are at least partially located in the rounded corner area.

12. The display substrate according to claim 11, wherein: The scanning shift register comprises: a plurality of transistors and a plurality of capacitors; The orthographic projection of the initial power supply line overlapping with the scan driving circuit on the substrate at least partially overlaps with the orthographic projection of the plurality of capacitors on the substrate.

13. The display substrate according to claim 12, wherein: The distance between the initial power supply line overlapping with the scan driving circuit and the boundary of the display area is smaller than the distance between at least one of the plurality of capacitors and the boundary of the display area.

14. The display substrate according to claim 12 or 13, wherein the number of transistors in the virtual scan shift register is less than or equal to the number of transistors in the scan shift register; The width of the virtual scan shift register is smaller than or equal to the width of the scan shift register.

15. The display substrate according to claim 14, wherein: The distance between the boundary of the second clock signal line located on the side of the virtual scan shift register away from the display area and the boundary of the initial power line of at least one initial power line close to the display area close to the display area is smaller than the distance between the boundary of the second clock signal line located on the side of the scan shift register away from the display area and the boundary of the initial power line of at least one initial power line close to the display area close to the display area.

16. The display substrate according to claim 12, wherein: The driving circuit layer comprises: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked in sequence; The semiconductor layer at least includes: an active layer of a plurality of transistors; The first conductive layer at least includes: control electrodes of a plurality of transistors and first plates of a plurality of capacitors; The second conductive layer at least includes: second plates of a plurality of capacitors, a first output signal line and a third output signal line; The third conductive layer at least includes: a second power supply line, a first electrode and a second electrode of at least one transistor, and a fourth output signal line; The fourth conductive layer at least includes: a first initial signal line, a second initial signal line and a first power line.

17. The display substrate according to claim 16, wherein: The driving circuit layer further comprises: a fifth conductive layer located on a side of the fourth conductive layer away from the substrate; The fifth conductive layer at least includes: a first output connection line, a second output connection line, a third output connection line and a fourth output connection line.

18. The display substrate according to claim 16, wherein: The initial power supply line is a single-layer structure, and the initial power supply line is located in the fourth conductive layer.

19. The display substrate according to claim 16, wherein: The initial power supply line comprises: a first initial sub-segment and a second initial sub-segment connected to each other, wherein an orthographic projection of the first initial sub-segment on the substrate at least partially overlaps with an orthographic projection of the second initial sub-segment on the substrate; The first initial sub-segment is located in the third conductive layer, and the second initial sub-segment is located in the fourth conductive layer.

20. The display substrate according to claim 16, wherein: The first clock signal line and the second clock signal line are of a single-layer structure, and the first clock signal line and the second clock signal line are located in a fourth conductive layer.

21. The display substrate according to claim 16, wherein: The clock signal line comprises: a first clock sub-segment and a second clock sub-segment connected to each other, the clock signal line comprises a first clock signal line and a second clock signal line, and an orthographic projection of the first clock sub-segment on the substrate at least partially overlaps with an orthographic projection of the second clock sub-segment on the substrate; The first clock sub-segment is located on the third conductive layer, and the second clock sub-segment is located on the fourth conductive layer close to the substrate.

22. The display substrate according to claim 16, wherein: The second output signal line is a single-layer structure, and the second output signal line is located in the second conductive layer.

23. The display substrate according to claim 16, wherein: The driving circuit layer further includes: a sixth conductive layer located between the second conductive layer and the third conductive layer; The second output signal line comprises a plurality of first output sub-segments and a plurality of second output sub-segments, adjacent first output sub-segments are electrically connected via the second output sub-segments, adjacent second output sub-segments are electrically connected via the first output sub-segments, the orthographic projections of the second output sub-segments on the substrate at least partially overlap with the orthographic projections of the electrically connected first output sub-segments on the substrate, and the orthographic projections of the first output sub-segments on the substrate at least partially overlap with the orthographic projections of the electrically connected second output sub-segments on the substrate; The first output sub-segment is located at the second conductive layer, and the second output sub-segment is located at the sixth conductive layer.

24. A display device comprising the display substrate according to any one of claims 1 to 23.

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