Display substrate and manufacturing method therefor, and display device

Abstract

Embodiments of the present disclosure provide a display substrate and a manufacturing method therefor, and a display device. The display substrate comprises a plurality of repeating units, and each repeating unit comprises a display region and a light-transmitting region; the display region comprises a plurality of sub-pixels, and each sub-pixel comprises a pixel driving circuit; the pixel driving circuit comprises a first transistor, a second transistor, a third transistor, and a storage capacitor; a first electrode of the first transistor is connected to a data signal line, and a second electrode of the first transistor is connected to a gate electrode of the second transistor and a first end of the storage capacitor, respectively; a first electrode of the second transistor is connected to a first power line, and a second electrode of the second transistor is connected to a second electrode of the third transistor and a second end of the storage capacitor, respectively; a first electrode of the third transistor is connected to a compensation signal line; in at least one sub-pixel, a gate electrode of the first transistor and a gate electrode of the third transistor are connected to a same scanning signal line.

Description

Display substrate and manufacturing method thereof, and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on April 26, 2023, with application number 202310466298.4 and invention name “Display substrate, preparation method thereof, and display device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) are active light-emitting display devices. They offer advantages such as active illumination, ultra-thinness, wide viewing angles, high brightness, high contrast, low power consumption, extremely fast response times, lightweight design, customizable form factors, and flexible displays. They are becoming a highly promising next-generation display technology. Active Matrix (AM) OLEDs are current-driven devices that use independent thin film transistors (TFTs) to control each sub-pixel, allowing each sub-pixel to emit light continuously and independently.

[0004] With the continuous development of display technology, OLED technology is increasingly being used in transparent displays. Transparent display is an important personalized display field in display technology. It refers to the display of images in a transparent state. Viewers can not only see the image in the display device, but also the scene behind the display device, which can realize virtual reality (VR), augmented reality (AR) and 3D display functions. Transparent display devices using OLED technology usually divide each sub-pixel into a display area and a light-transmitting area. The display area is equipped with pixel driving circuits and light-emitting devices to realize image display, and the light-transmitting area allows light to pass through.

[0005] Summary of the Invention

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0007] An embodiment of the present disclosure provides a display substrate, comprising a plurality of regularly arranged repeating units, the repeating units comprising a display area and a light-transmitting area located on at least one side of the display area, the display area being configured to display an image, and the light-transmitting area being configured to transmit light; the display area comprising a plurality of sub-pixels forming at least two pixel rows and two pixel columns, the sub-pixels comprising a pixel driving circuit; the pixel driving circuit comprising a first transistor, a second transistor, a third transistor and a storage capacitor, the first electrode of the first transistor being connected to a data signal line, the second electrode of the first transistor being respectively connected to a gate electrode of the second transistor and a first end of the storage capacitor, the first electrode of the second transistor being connected to a first power line, the second electrode of the second transistor being respectively connected to a second electrode of the third transistor and a second end of the storage capacitor, the first electrode of the third transistor being connected to a compensation signal line, and in the pixel driving circuit of at least one sub-pixel, the gate electrode of the first transistor and the gate electrode of the third transistor being connected to the same scanning signal line.

[0008] In an exemplary embodiment, in the plurality of pixel driving circuits of at least one pixel row, gate electrodes of the plurality of first transistors and gate electrodes of the plurality of third transistors are connected to the same scan signal line.

[0009] In an exemplary embodiment, in the plurality of pixel driving circuits of at least one repeating unit, gate electrodes of the plurality of first transistors and gate electrodes of the plurality of third transistors are connected to the same scan signal line.

[0010] In an exemplary embodiment, in at least one repeating unit, the scanning signal line extends from the display area to the light-transmitting area, and the scanning signal line includes a single line segment of a single-line structure and a double line segment of a double-line structure. The single line segment is arranged in the light-transmitting area, and the double line segment is arranged in the display area. The double line segments are respectively connected to the pixel driving circuits of multiple sub-pixels in the repeating unit.

[0011] In an exemplary embodiment, the double-line segment includes a first sub-line and a second sub-line extending along the pixel row direction, the first sub-line and the second sub-line are arranged along the pixel column direction, the first sub-line is respectively connected to the pixel driving circuits of multiple sub-pixels in one pixel row, and the second sub-line is respectively connected to the pixel driving circuits of multiple sub-pixels in another adjacent pixel row.

[0012] In an exemplary embodiment, the double-line segment further includes a first connecting line and a second connecting line, the first connecting line being connected to one end of the first sub-line and the second sub-line respectively, the second connecting line being connected to the other end of the first sub-line and the second sub-line respectively, and the first connecting line, the first sub-line, the second connecting line and the second sub-line forming a ring structure.

[0013] In an exemplary embodiment, the single line segment is located in an extending direction of the first sub-line or the second sub-line.

[0014] In an exemplary embodiment, the first connection line is connected to a single line segment in the light-transmitting area on one side of the display area in the pixel row direction, and the second connection line is connected to a single line segment in the light-transmitting area on the other side of the display area in the pixel row direction.

[0015] In an exemplary embodiment, in at least one repeating unit, the single segment and the double segment are interconnected as an integral structure.

[0016] In an exemplary embodiment, orthographic projections of the first power line, the data signal line, and the compensation signal line on the display substrate plane at least partially overlap with an orthographic projection of the ring structure on the display substrate plane.

[0017] In an exemplary embodiment, in at least one repeating unit, the active layers of the third transistors of two sub-pixels in adjacent pixel rows are an interconnected integral structure, and the orthographic projection of the active layer of the third transistor on the plane of the display substrate at least partially overlaps with the orthographic projection of the annular structure on the plane of the display substrate.

[0018] In an exemplary embodiment, in at least one repeating unit, the plurality of sub-pixels are mirror-symmetrical with respect to the scanning signal line.

[0019] In an exemplary embodiment, the first end of the storage capacitor includes a first plate and a third plate, the second end of the storage capacitor includes a second plate, the orthographic projection of the second plate on the plane of the display substrate at least partially overlaps with the orthographic projection of the first plate on the plane of the display substrate, the first plate and the second plate form a first capacitor, the orthographic projection of the second plate on the plane of the display substrate at least partially overlaps with the orthographic projection of the third plate on the plane of the display substrate, the third plate and the second plate form a second capacitor, the first plate is respectively connected to the third plate, the second electrode of the first transistor and the gate electrode of the second transistor, the second plate is respectively connected to the second electrode of the second transistor and the second electrode of the third transistor, and the first capacitor and the second capacitor constitute a storage capacitor with a parallel structure.

[0020] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display area includes a driving circuit layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving circuit layer away from the substrate, the driving circuit layer includes at least a first conductive layer, a second conductive layer and a third conductive layer arranged in sequence along a direction away from the substrate, the first electrode is arranged in the first conductive layer, the second electrode is arranged in the second conductive layer, the third electrode is arranged in the third conductive layer, and the third electrode is connected to the first electrode through a via; at least one repeating unit also includes a electrode connecting electrode, the electrode connecting electrode is arranged in the light-transmitting area, and the electrode connecting electrode is connected to the first electrode.

[0021] In an exemplary embodiment, in at least one repeating unit, the electrode connecting electrode and the first electrode plate are connected to each other as an integral structure.

[0022] In an exemplary embodiment, the light-emitting structure layer includes at least a fourth conductive layer arranged on a side of the third conductive layer away from the substrate, the fourth conductive layer includes at least a first anode and an anode connecting electrode, the first anode is arranged in a plurality of sub-pixels in the display area, the anode connecting electrode is arranged in the light-transmitting area, the anode connecting electrode is connected to the plate connecting electrode through an anode via, and the anode via is arranged in the light-transmitting area; in at least one sub-pixel, the first anode includes a first sub-anode and a second sub-anode arranged in isolation, the first end of the anode connecting electrode is connected to the first sub-anode, and the second end of the anode connecting electrode is connected to the second sub-anode.

[0023] In an exemplary embodiment, the third conductive layer further includes a second power line and a first auxiliary electrode, the second power line is disposed in the display area, the first auxiliary electrode is disposed in the light-transmitting area, and the first auxiliary electrode is connected to the second power line.

[0024] In an exemplary embodiment, in at least one repeating unit, the first auxiliary electrode and the second power line are connected to each other as an integral structure.

[0025] In an exemplary embodiment, an orthographic projection of the second power line on the plane of the display substrate at least partially overlaps with an orthographic projection of the loop structure of the scan signal line on the plane of the display substrate.

[0026] An embodiment of the present disclosure further provides a display device, comprising the aforementioned display substrate.

[0027] The present disclosure also provides a method for preparing a display substrate, wherein the display substrate includes a plurality of regularly arranged repeating units, the repeating units including a display area and a light-transmitting area located on at least one side of the display area, the display area being configured to display an image, and the light-transmitting area being configured to transmit light; the display area including a plurality of sub-pixels forming at least two pixel rows and two pixel columns, the sub-pixels including a pixel driving circuit; the preparation method comprising:

[0028] A pixel driving circuit is formed in the sub-pixel; the pixel driving circuit includes a first transistor, a second transistor, a third transistor and a storage capacitor, the first electrode of the first transistor is connected to the data signal line, the second electrode of the first transistor is respectively connected to the gate electrode of the second transistor and the first end of the storage capacitor, the first electrode of the second transistor is connected to the first power line, the second electrode of the second transistor is respectively connected to the second electrode of the third transistor and the second end of the storage capacitor, the first electrode of the third transistor is connected to the compensation signal line, and the gate electrode of the first transistor and the gate electrode of the third transistor are connected to the same scanning signal line.

[0029] Of course, it is not necessary to achieve all of the advantages described above simultaneously for any product or method of the present invention to be implemented. Other features and advantages of the present invention will be described in the following embodiments and, in part, will become apparent from the embodiments or be learned through practice of the present invention. The objectives and other advantages of the embodiments of the present disclosure may be achieved and obtained through the structures particularly pointed out in the description, claims, and drawings.

[0030] Other aspects will become apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0032] FIG1 is a schematic structural diagram of a display device;

[0033] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0034] FIG3 is a schematic diagram showing the arrangement of sub-pixels in a substrate according to an exemplary embodiment of the present disclosure;

[0035] FIG4 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0036] FIG5 is an equivalent circuit diagram of a pixel driving circuit in a display unit according to an exemplary embodiment of the present disclosure;

[0037] FIG6 is a schematic structural diagram of a scanning signal line according to an exemplary embodiment of the present disclosure;

[0038] FIG7 is a schematic diagram of an embodiment of the present disclosure after forming a first conductive layer pattern;

[0039] 8A and 8B are schematic diagrams of a semiconductor layer pattern formed according to an embodiment of the present disclosure;

[0040] 9A and 9B are schematic diagrams of an embodiment of the present disclosure after forming a second conductive layer pattern;

[0041] FIG10 is a schematic diagram of an embodiment of the present disclosure after forming a third insulating layer pattern;

[0042] 11A and 11B are schematic diagrams of an embodiment of the present disclosure after forming a third conductive layer pattern;

[0043] FIG12 is a schematic diagram of an embodiment of the present disclosure after forming patterns of a fourth insulating layer and a first planar layer;

[0044] 13A and 13B are schematic diagrams of an embodiment of the present disclosure after forming a fourth conductive layer pattern;

[0045] 14A and 14B are schematic diagrams of an embodiment of the present disclosure after forming a fifth conductive layer pattern;

[0046] FIG15 is a schematic diagram of an embodiment of the present disclosure after forming a pixel definition layer pattern;

[0047] FIG. 16 is a schematic diagram of repairing a short circuit defect of a display substrate according to an exemplary embodiment of the present disclosure.

[0048] Description of the accompanying drawings:

[0049] 11—first electrode plate; 12—electrode connecting the electrode plate; 13—compensation connecting line;

[0050] 21—first active layer; 22—second active layer; 23—third active layer;

[0051] 31—scanning signal line; 31-1—double line segment; 31-2—single line segment;

[0052] 32—second electrode; 33—second gate electrode; 34—power connection electrode;

[0053] 35—First power supply auxiliary line; 36—Second power supply auxiliary line; 37—Power supply connection line;

[0054] 38—electrode connecting wire; 41—first connecting electrode; 42—second connecting electrode;

[0055] 43—third connecting electrode; 44—fourth connecting electrode; 45—fifth connecting electrode;

[0056] 46—sixth connecting electrode; 47—third electrode plate; 51—first power line;

[0057] 52—second power line; 53—data signal line; 54—compensation signal line;

[0058] 55—auxiliary electrode line; 52—first auxiliary electrode; 61—first anode;

[0059] 61-1—first sub-anode; 61-2—second sub-anode; 62—anode connecting electrode;

[0060] 72—second anode; 72-1—third sub-anode; 72-1—fourth sub-anode;

[0061] 73—third auxiliary electrode; 80—repeating unit; 100—repeating unit;

[0062] 110—display area; 120—light-transmitting area; 200—short-circuit point;

[0063] 300—Cutoff point. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0065] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0066] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0067] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0068] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0069] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0070] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0071] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0072] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0073] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0074] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0075] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0076] Figure 1 is a schematic diagram of the structure of a display device. As shown in Figure 1, the OLED display device may include a timing controller, a data driver, a scan driver, and a pixel array. The timing controller is respectively connected to the data driver and the scan driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The pixel array may include a plurality of sub-pixels Pxij. Each sub-pixel Pxij may be connected to a corresponding data signal line and a corresponding scan signal line. i and j may be natural numbers. At least one sub-pixel Pxij may include at least a circuit unit and a display unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to the scan signal line and the data signal line. The display unit may include at least a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the circuit unit. Sub-pixel Pxij may refer to a sub-pixel whose pixel driving circuit is connected to the i-th scan signal line and the j-th data signal line. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, and may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan driver to the scan driver. The data driver can generate data voltages to be provided to data signal lines 531, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines 531 to Dn on a per-pixel basis, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially provide scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next-level circuit under the control of a clock signal. m can be a natural number. In an exemplary embodiment, the pixel array can be provided on a display substrate.

[0077] FIG2 is a schematic diagram of a planar structure of a display substrate. As shown in FIG2 , in an exemplary embodiment, the display substrate may include a plurality of regularly arranged repeating units 100, and at least one repeating unit 100 may include a display area 110 and a light-transmitting area 120. The display area 110 may include a plurality of sub-pixels, and at least one sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, and the light-emitting unit may include at least a light-emitting device. The light-emitting device of the light-emitting unit is connected to the pixel driving circuit of the corresponding circuit unit, and the display area 110 is configured to display an image. The light-transmitting area 120 may be located on at least one side of the display area 110 in the repeating unit 100. The light-transmitting area 120 is configured to transmit light, so that the repeating unit 100 can realize image display in a transparent state, i.e., transparent display. In an exemplary embodiment, the repeating unit is the basic unit that constitutes the display substrate. The display substrate is formed by repeating and continuously arranging it along at least one direction, i.e., the display substrate is spliced ​​by a plurality of repeating units.

[0078] Currently, existing transparent display devices suffer from issues such as low resolution and transparency. Furthermore, transparent display devices using OLED technology, particularly large-scale transparent display devices, have high requirements for signal line defects and pixel-level yield. These defective signal lines require repair. The inventors of this application have discovered that existing repair processes can only repair signal lines in certain locations, failing to fully repair the entire signal line. Consequently, the repair success rate is low, reducing product yield.

[0079] An exemplary embodiment of the present disclosure provides a display substrate, comprising a plurality of regularly arranged repeating units, the repeating units comprising a display area and a light-transmitting area located on at least one side of the display area, the display area being configured to display an image, and the light-transmitting area being configured to transmit light; the display area comprising a plurality of sub-pixels forming at least two pixel rows and two pixel columns, the sub-pixels comprising a pixel driving circuit; the pixel driving circuit comprising a first transistor, a second transistor, a third transistor, and a storage capacitor, wherein a first electrode of the first transistor is connected to a data signal line, a second electrode of the first transistor is respectively connected to a gate electrode of the second transistor and a first end of the storage capacitor, a first electrode of the second transistor is connected to a first power line, a second electrode of the second transistor is respectively connected to a second electrode of the third transistor and a second end of the storage capacitor, and a first electrode of the third transistor is connected to a compensation signal line; and in the pixel driving circuit of at least one sub-pixel, the gate electrode of the first transistor and the gate electrode of the third transistor are connected to the same scan signal line.

[0080] In an exemplary embodiment, in the plurality of pixel driving circuits of at least one pixel row, the gate electrodes of the plurality of first transistors and the gate electrodes of the plurality of third transistors are connected to the same scan signal line.

[0081] In an exemplary embodiment, in the plurality of pixel driving circuits of at least one repeating unit, gate electrodes of the plurality of first transistors and gate electrodes of the plurality of third transistors are connected to the same scan signal line.

[0082] In an exemplary embodiment, in at least one repeating unit, the scanning signal line extends from the display area to the light-transmitting area, and the scanning signal line includes a single line segment of a single-line structure and a double line segment of a double-line structure. The single line segment is arranged in the light-transmitting area, and the double line segment is arranged in the display area. The double line segments are respectively connected to the pixel driving circuits of multiple sub-pixels in the repeating unit.

[0083] In an exemplary embodiment, in at least one repeating unit, the plurality of sub-pixels are mirror-symmetrical with respect to the scanning signal line.

[0084] The display substrate of the present disclosure is described below by way of some exemplary embodiments.

[0085] In an exemplary embodiment, the display substrate may include a plurality of regularly arranged repeating units in a direction parallel to the display substrate. At least one repeating unit may include a display area 110 and a light-transmitting area 120. The display area 110 is configured to display an image, and the light-transmitting area 120 is configured to transmit light, thereby achieving a transparent display. In a direction perpendicular to the display substrate, the display substrate may include at least a driving circuit layer disposed on a base and a light-emitting structure layer disposed on a side of the driving circuit layer away from the base. In at least one repeating unit, the driving circuit layer of the display area 110 may include a plurality of circuit units, and the light-emitting structure layer of the display area 110 may include a plurality of light-emitting units. The circuit units may include at least a pixel driving circuit, and the light-emitting units may include at least a light-emitting device, which is connected to the pixel driving circuit of the corresponding circuit unit.

[0086] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In exemplary embodiments, the position of the orthographic projection of the light-emitting unit on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position of the orthographic projection of the circuit unit on the substrate.

[0087] In the exemplary embodiment of the present disclosure, the position of the circuit unit's orthographic projection on the substrate corresponds one-to-one to the position of the light-emitting unit's orthographic projection on the substrate. The circuit unit and the light-emitting unit constitute a sub-pixel. Therefore, in the following content, sub-pixels are uniformly used to refer to the circuit unit and the light-emitting unit.

[0088] Figure 3 is a schematic diagram of the arrangement of subpixels in a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a repeating unit. As shown in Figure 3, the repeating unit may include a display area 110 and a light-transmitting area 120. The display area 110 may be located on one side of the light-transmitting area 120 in a first direction X. In an exemplary embodiment, the display area 110 may include four subpixels: a first subpixel P1, a second subpixel P2, a third subpixel P3, and a fourth subpixel P4. The four subpixels are arranged in a square pattern, which can effectively increase the aperture ratio and the area of ​​the light-transmitting area.

[0089] In an exemplary embodiment, the second subpixel P2 may be disposed on one side of the first subpixel P1 in the first direction X, the third subpixel P3 may be disposed on one side of the first subpixel P1 in the second direction Y, and the fourth subpixel P4 may be disposed on one side of the third subpixel P3 in the first direction X. A plurality of subpixels sequentially disposed along the first direction X may be referred to as a pixel row, and a plurality of subpixels sequentially disposed along the second direction Y may be referred to as a pixel column. The first direction X intersects the second direction Y.

[0090] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a blue subpixel (B) that emits blue light, the third subpixel P3 may be a white subpixel (W) that emits white light, and the fourth subpixel P4 may be a green subpixel (G) that emits green light. In some possible embodiments, the arrangement of RGBW can be adjusted according to actual needs and is not specifically limited in this disclosure.

[0091] In an exemplary embodiment, each sub-pixel may include a circuit unit and a light-emitting unit arranged on a side of the circuit unit away from the substrate, the circuit unit may include at least a pixel driving circuit, the light-emitting unit may include at least a light-emitting device, and the light-emitting device of the light-emitting unit is connected to the pixel driving circuit of the corresponding circuit unit.

[0092] Figure 4 is a schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a pixel driver circuit within a repeating unit. As shown in Figure 4 , the repeating unit may include a display area 110 and a light-transmitting area 120. Display area 110 may include a first subpixel P1, a second subpixel P2, a third subpixel P3, and a fourth subpixel P4 arranged in a square pattern. At least one subpixel may include a pixel driver circuit and a light-emitting device.

[0093] In an exemplary embodiment, at least one repeating unit may include one scan signal line 31, one first power line 51, one second power line 52, four data signal lines 53, and one compensation signal line 54. In an exemplary embodiment, the scan signal line 31 may be provided in the display region 110 and the light-transmitting region 120, and the first power line 51, the second power line 52, the data signal line 53, and the compensation signal line 54 may be provided in the display region 110.

[0094] In an exemplary embodiment, at least one pixel driving circuit includes at least a first transistor T1 as a data writing transistor, a second transistor T2 as a driving transistor, a third transistor T3 as a sensing transistor, and a storage capacitor C.

[0095] In an exemplary embodiment, in at least one sub-pixel, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected to the same scan signal line 31 .

[0096] In an exemplary embodiment, in at least one pixel row, the gate electrodes of the two first transistors T1 and the gate electrodes of the two third transistors T3 are connected to the same scan signal line 31 .

[0097] In an exemplary embodiment, in at least one repetition unit, the gate electrodes of the four first transistors T1 and the gate electrodes of the four third transistors T3 are connected to the same scan signal line 31 .

[0098] In an exemplary embodiment, the shape of the scanning signal line 31 can be a line shape with the main portion extending along the first direction X, and can be set in the middle area of ​​the repeating unit in the second direction Y. The multiple sub-pixels in the repeating unit can be mirror-symmetrical with respect to the scanning signal line 31.

[0099] In an exemplary embodiment, the first power line 51 , the second power line 52 , the data signal line 53 , and the compensation signal line 54 may be in the shape of lines whose main portions extend along the second direction Y. One first power line 51 , two data signal lines 53 , one compensation signal line 54 , two data signal lines 53 , and one second power line 52 may be sequentially arranged along the first direction X. In at least one repeating unit, the first power line 51 may be located on one side of the display area 110 in the first direction X, the second power line 52 may be located on the other side of the display area 110 in the first direction X, the compensation signal line 54 may be located between the first power line 51 and the second power line 52 , two of the four data signal lines 53 may be located between the first power line 51 and the compensation signal line 54 , and the other two of the four data signal lines 53 may be located between the second power line 52 and the compensation signal line 54 .

[0100] In an exemplary embodiment, the positions of the first power line 51 and the second power line 52 can be substantially mirror-symmetrical with respect to the compensation signal line 54, and the two data signal lines 53 located on the opposite side of the first direction X of the compensation signal line 54 and the two data signal lines 53 located on the side of the first direction X of the compensation signal line 54 can be substantially mirror-symmetrical with respect to the compensation signal line 54.

[0101] In an exemplary embodiment, a single scan signal line 31 may define two adjacent pixel rows. The side of the scan signal line 31 opposite the second direction Y is a first pixel row, and the side of the scan signal line 31 in the second direction Y is a second pixel row. The first power line 51, the compensation signal line 54, and the second power line 52 may define two pixel columns. The first power line 51 and the compensation signal line 54 may define a first pixel column, and the second power line 52 and the compensation signal line 54 may define a second pixel column. Thus, the scan signal line 31, the first power line 51, the second power line 52, and the compensation signal line 54 define four sub-pixels.

[0102] In an exemplary embodiment, the sub-pixel located at the first pixel row and the first pixel column position (the upper left of the display unit) can be referred to as the first sub-pixel P1, the sub-pixel located at the first pixel row and the second pixel column position (the upper right of the display unit) can be referred to as the second sub-pixel P2, the sub-pixel located at the second pixel row and the first pixel column position (the lower left of the display unit) can be referred to as the third sub-pixel P3, and the sub-pixel located at the second pixel row and the second pixel column position (the lower right of the display unit) can be referred to as the fourth sub-pixel P4.

[0103] In an exemplary embodiment, the pixel driving circuit structure in the first pixel column and the pixel driving circuit structure in the second pixel column can be basically mirror-symmetrical with respect to the compensation signal line 54, that is, the pixel driving circuit structure of the first sub-pixel P1 and the pixel driving circuit structure of the second sub-pixel P2 can be basically mirror-symmetrical with respect to the compensation signal line 54, and the pixel driving circuit structure of the third sub-pixel P3 and the pixel driving circuit structure of the fourth sub-pixel P4 can be basically mirror-symmetrical with respect to the compensation signal line 54.

[0104] Figure 5 is an equivalent circuit diagram of a pixel driving circuit in a display unit according to an exemplary embodiment of the present disclosure. As shown in Figure 5 , at least one display unit may include four pixel driving circuits, which may be arranged in a square and may have a 3T1C structure.

[0105] In an exemplary embodiment, at least one pixel driving circuit may include three transistors (a first transistor T1, a second transistor T2, and a third transistor T3) and a storage capacitor C, and the pixel driving circuit is respectively connected to the scanning signal line 31, the first power line 51, the data signal line 53, and the compensation signal line 54.

[0106] In an exemplary embodiment, the pixel driving circuit may include a first node N1 and a second node N2. The first node N1 is connected to the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the first end of the storage capacitor C, respectively. The second node N2 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the second end of the storage capacitor C, respectively.

[0107] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1 , a second end of the storage capacitor C is connected to the second node N2 , and the storage capacitor C is used to store the potential of the gate electrode of the second transistor T2 .

[0108] In the exemplary embodiment, a gate electrode of the first transistor T1 is connected to the scan signal line 31, a first electrode of the first transistor T1 is connected to the data signal line 53, and a second electrode of the first transistor T1 is connected to the first node N1. When a turn-on signal is applied to the scan signal line 31, the first transistor T1 inputs a data signal of the data signal line 53 to the gate electrode of the second transistor T2.

[0109] In an exemplary embodiment, a gate electrode of the second transistor T2 is connected to the first node N1, a first electrode of the second transistor T2 is connected to the first power line 51, and a second electrode of the second transistor T2 is connected to the second node N2. The second transistor T2 generates a corresponding current at its second electrode under the control of the data signal received at its gate electrode.

[0110] In an exemplary embodiment, a gate electrode of the third transistor T3 is connected to the scan signal line 31, a first electrode of the third transistor T3 is connected to the compensation signal line 54, and a second electrode of the third transistor T3 is connected to the second node N2. When a turn-on signal is applied to the scan signal line 31, the third transistor T3 extracts the threshold voltage Vth and mobility of the second transistor T2 in response to the compensation timing to compensate for the threshold voltage Vth.

[0111] In an exemplary embodiment, in the pixel driving circuit of at least one sub-pixel, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected to the same scan signal line 31 .

[0112] In an exemplary embodiment, in two pixel driving circuits of at least one pixel row, the gate electrodes of the two first transistors T1 and the gate electrodes of the two third transistors T3 are connected to the same scan signal line 31 .

[0113] In an exemplary embodiment, in the four pixel driving circuits of at least one repeating unit, the gate electrodes of the four first transistors T1 and the gate electrodes of the four third transistors T3 are connected to the same scan signal line 31 .

[0114] In an exemplary embodiment, the light-emitting device EL may be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode). The first electrode of the light-emitting device EL is connected to the second node N2, and the second electrode of the light-emitting device EL is connected to the second power line 52. The light-emitting device EL emits light of corresponding brightness in response to the current of the second electrode of the second transistor T2.

[0115] In an exemplary embodiment, the signal of the first power line 51 is a continuously provided high-level signal, and the signal of the second power line 52 is a continuously provided low-level signal.

[0116] In an exemplary embodiment, the first to third transistors T1 to T3 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first to third transistors T1 to T3 may include P-type transistors and N-type transistors.

[0117] In an exemplary embodiment, the first transistor T1 to the third transistor T3 may be low-temperature polysilicon thin-film transistors, or oxide thin-film transistors, or both. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, can leverage the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0118] As shown in Figures 4 and 5, in an exemplary embodiment, the scan signal line 31 may be in the shape of a line with a main portion extending along a first direction X, and may be provided in the display area 110 and the light-transmitting area 120. In the first direction X, the scan signal line 31 may extend from the display area 110 to the light-transmitting area 120, or alternatively, from the light-transmitting area 120 to the display area 110. In the second direction Y, the scan signal line 31 may be provided in the middle region of the repeating unit in the second direction Y, between the first subpixel P1 and the third subpixel P3, and between the second subpixel P2 and the fourth subpixel P4. With respect to the scan signal line 31, the multiple subpixels in the repeating unit are mirror-symmetrical with respect to the scan signal line 31. That is, the first subpixel P1 and the third subpixel P3 may be substantially mirror-symmetrical with respect to the scan signal line 31, and the second subpixel P2 and the fourth subpixel P4 may be substantially mirror-symmetrical with respect to the scan signal line 31.

[0119] Figure 6 is a schematic diagram of the structure of a scan signal line according to an exemplary embodiment of the present disclosure. As shown in Figure 6, in this exemplary embodiment, the scan signal line 31 may include a double-line segment 31-1 with a double-line structure and a single-line segment 31-2 with a single-line structure. The double-line segment 31-1 may be located in the display area 110, and the single-line segment 31-2 may be located in the light-transmitting area 120. In other words, the display area 110 is provided with two signal lines, each of which is connected to the pixel driving circuits of multiple sub-pixels in the repeating unit, while the light-transmitting area 120 is provided with only one signal line.

[0120] In an exemplary embodiment, the double line segment 31-1 of the display area 110 may include a first sub-line 31a and a second sub-line 31b extending along a first direction X (pixel row direction). The first sub-line 31a and the second sub-line 31b are arranged along a second direction Y (pixel column direction). The second sub-line 31b may be disposed on one side of the first sub-line 31a in the second direction Y. The first sub-line 31a may be connected to the pixel driving circuits of two sub-pixels in the first pixel row, respectively, and the second sub-line 31b may be connected to the pixel driving circuits of two sub-pixels in the second pixel row, respectively. This enables the connection of the double line segment 31-1 with multiple pixel driving circuits in a repeating unit.

[0121] In an exemplary embodiment, the first sub-line 31a is connected to the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 in the first sub-pixel P1 and the second sub-pixel P2, respectively, and the second sub-line 31b is connected to the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 in the third sub-pixel P3 and the fourth sub-pixel P4, respectively, so that the double line segment 31-1 can control the conduction or disconnection of multiple first transistors T1 and third transistors T3 in the repeating unit.

[0122] In an exemplary embodiment, the double line segment 31-1 of the display area 110 may further include a first connecting line 31c and a second connecting line 31d. The first connecting line 31 may be connected to the ends of the first sub-line 31a and the second sub-line 31b in the opposite direction of the first direction X, respectively. The second connecting line 31d may be connected to the ends of the first sub-line 31a and the second sub-line 31b in the first direction X, respectively. Such that the first connecting line 31c, the first sub-line 31a, the second connecting line 31d and the second sub-line 31b are connected in sequence to form a ring structure.

[0123] In an exemplary embodiment, the single line segment 31-2 can be located in the extension direction of the first sub-line 31a or the second sub-line 31b, the first connecting line 31c can be connected to the single line segment 31-2 of the light-transmitting area 120 in the opposite direction of the first direction X of the display area 110, and the second connecting line 31d can be connected to the single line segment 31-2 of the light-transmitting area 120 in the first direction X of the display area 110. The double line segment 31-1 and the single line segment 31-2 constitute a continuous scanning signal line 31.

[0124] In an exemplary embodiment, in at least one repeating unit, the double line segment 31 - 1 of the display region 110 and the single line segment 31 - 2 of the light-transmitting region 120 may be an integral structure connected to each other.

[0125] In an exemplary embodiment, in at least one sub-pixel, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected to the same scan signal line 31, the first electrode of the first transistor T1 is connected to the data signal line 53, the second electrode of the first transistor T1 is connected to the gate electrode of the second transistor and the first end of the storage capacitor C, respectively, the first electrode of the second transistor T2 is connected to the first power line 51, the second electrode of the second transistor T2 is connected to the second electrode of the third transistor T3 and the second end of the storage capacitor C, respectively, and the first electrode of the third transistor T3 is connected to the compensation signal line 54.

[0126] In an exemplary embodiment, at least one repeating unit may further include a compensation connection line 13, and the shape of the compensation connection line 13 may be a strip shape extending along the first direction X, and may be located between the first pixel row and the second pixel row, and the extension length of the compensation connection line 13 in the first pixel column is substantially the same as the extension length in the second pixel column, and the compensation connection line 13 in the first pixel column and the compensation connection line 13 in the second pixel column may be substantially mirror-symmetrical relative to the compensation signal line 54.

[0127] In an exemplary embodiment, at the intersection of the compensation connection line 13 and the compensation signal line 54, the compensation signal line 54 is connected to the compensation connection line 13 through a via. The end of the compensation connection line 13 located in the first pixel column is connected to the first electrode of the third transistor T3 in the first pixel column, and the end of the compensation connection line 13 located in the second pixel column is connected to the first electrode of the third transistor T3 in the second pixel column. This implements a one-to-four compensation connection line structure, allowing one compensation signal line to write compensation signals to each of the four pixel drive circuits in the display unit.

[0128] In an exemplary embodiment, at least one repeating unit may also include at least one first power auxiliary line 35, the orthographic projection of the first power auxiliary line 35 on the substrate at least partially overlaps with the orthographic projection of the first power line 51 on the substrate, and the first power line 51 is connected to the first power auxiliary line 35 through a via to form a double-layer first power routing structure.

[0129] In an exemplary embodiment, at least one repeating unit may also include at least one second power auxiliary line 36, the orthographic projection of the second power auxiliary line 36 on the substrate at least partially overlaps with the orthographic projection of the second power line 52 on the substrate, and the second power line 52 is connected to the second power auxiliary line 36 through a via to form a double-layer second power routing structure.

[0130] In an exemplary embodiment, the first end of the storage capacitor C may include a first electrode plate and a third electrode plate, and the second end of the storage capacitor C may include a second electrode plate. The orthographic projection of the second electrode plate on the substrate at least partially overlaps the orthographic projection of the first electrode plate on the substrate, and the first electrode plate and the second electrode plate form a first capacitor. The orthographic projection of the second electrode plate on the substrate at least partially overlaps the orthographic projection of the third electrode plate on the substrate, and the third electrode plate and the second electrode plate form a second capacitor. The first electrode plate and the third electrode plate are connected, and the first capacitor and the second capacitor form a parallel storage capacitor.

[0131] In an exemplary embodiment, the display area 110 may include a driving circuit layer disposed on the substrate and a light-emitting structure disposed on a side of the driving circuit layer away from the substrate, perpendicular to the substrate. The driving circuit layer may include at least a first conductive layer, a second conductive layer, and a third conductive layer disposed sequentially away from the substrate. The first electrode may be disposed in the first conductive layer, the second electrode may be disposed in the second conductive layer, and the third electrode may be disposed in the third conductive layer, with the third electrode connected to the first electrode via a via. The light-emitting structure layer may include at least a fourth conductive layer disposed on a side of the third conductive layer away from the substrate, a fifth conductive layer disposed on a side of the fourth conductive layer away from the substrate, and a cathode layer disposed on a side of the fifth conductive layer away from the substrate. The fourth conductive layer may include at least a first anode disposed in multiple sub-pixels of the display area 110, and the fifth conductive layer may include at least a second anode disposed in multiple sub-pixels of the display area 110.

[0132] In an exemplary embodiment, in at least one repeating unit, the light-transmitting region 120 may further include at least one auxiliary cathode 80, which is connected to the second power line 52. The auxiliary cathode 80 is configured to provide a low-level signal to the cathode and to reduce the diffraction effect of the light-transmitting region.

[0133] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0134] In an exemplary embodiment, taking four sub-pixels (first sub-pixel P1, second sub-pixel P2, third sub-pixel P3 and fourth sub-pixel P4) of a repeating unit as an example, the preparation process of the display substrate of the exemplary embodiment of the present disclosure may include the following operations.

[0135] (1) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern includes: depositing a first conductive film on a substrate, patterning the first conductive film through a patterning process, and forming a first conductive layer pattern on the substrate, as shown in FIG7 . In an exemplary embodiment, the first conductive layer may be referred to as a light shielding layer (SHL).

[0136] In an exemplary embodiment, the first conductive layer of each sub-pixel in the display substrate may include at least a first plate 11 and a plate connecting electrode 12 .

[0137] In an exemplary embodiment, the shape of the first electrode plate 11 can be rectangular, and the corners of the rectangle can be chamfered. The first electrode plate 11 can serve as a plate of a storage capacitor, and the first electrode plate 11 is configured to form a first capacitor with a subsequently formed second electrode plate.

[0138] In an exemplary embodiment, the first electrode plate 11 is further configured to shield the second transistor from light, reduce the intensity of light irradiating the second transistor, reduce leakage current of the second transistor, and thereby reduce the effect of light on the characteristics of the second transistor.

[0139] In an exemplary embodiment, the plate connecting electrode 12 may be shaped as a strip with a main portion extending along the first direction X. A first end of the plate connecting electrode 12 is connected to the first plate 11, and a second end of the plate connecting electrode 12 extends into the adjacent light-transmitting region 120 in a direction away from the first plate 11. The plate connecting electrode 12 is configured to be connected to a subsequently formed sixth connecting electrode and to the anode connecting electrode through the sixth connecting electrode.

[0140] In an exemplary embodiment, the second end of the plate-connecting electrode 12 may form a rectangular anode connection block 12-1, so that the plate-connecting electrode 12 as a whole is in a "T" shape, and the anode connection block 12-1 is located in the light-transmitting region 120. The connection block 12-1 is configured to accommodate an eleventh via hole to be formed subsequently, so that a sixth connection electrode to be formed subsequently is connected to the plate-connecting electrode 12 through the via hole.

[0141] In an exemplary embodiment, the plate-connecting electrode 12 in the first subpixel P1 may be located on a side opposite to the first plate 11 in the subpixel in the first direction X, and the first plate 11 and the plate-connecting electrode 12 in the first subpixel P1 may be connected to each other as an integral structure. The plate-connecting electrode 12 in the second subpixel P2 may be located on a side opposite to the first plate 11 in the subpixel in the first direction X, and the first plate 11 and the plate-connecting electrode 12 in the second subpixel P2 may be connected to each other as an integral structure. The plate-connecting electrode 12 in the third subpixel P3 may be located on a side opposite to the first plate 11 in the subpixel in the first direction X, and the first plate 11 and the plate-connecting electrode 12 in the third subpixel P3 may be connected to each other as an integral structure. The plate-connecting electrode 12 in the fourth subpixel P4 may be located on a side opposite to the first plate 11 in the subpixel in the first direction X, and the first plate 11 and the plate-connecting electrode 12 in the fourth subpixel P4 may be connected to each other as an integral structure.

[0142] In an exemplary embodiment, the first conductive layer in at least one repeating unit may further include a compensation connection line 13. The compensation connection line 13 may be in the shape of a strip having a main portion extending along a first direction X. In the first direction X, the compensation connection line 13 may be arranged across the first pixel column and the second pixel column. In the second direction Y, the compensation connection line 13 may be arranged between the first pixel row and the second pixel row. The compensation connection line 13 is configured to, on the one hand, be connected to a subsequently formed compensation signal line, thereby realizing a one-to-four compensation signal line structure in a repeating unit. On the other hand, the compensation signal line 13 is connected to the first region of the third active layer in each sub-pixel via a subsequently formed connection electrode, so that the compensation signal line can provide a compensation signal to the third transistor in each sub-pixel.

[0143] In an exemplary embodiment, the first conductive layer pattern in the first subpixel P1 and the first conductive layer pattern in the third subpixel P3 may be substantially mirror-symmetrical with respect to a horizontal reference line, and the first conductive layer pattern in the second subpixel P2 and the first conductive layer pattern in the fourth subpixel P4 may be substantially mirror-symmetrical with respect to the horizontal reference line. The first conductive layer pattern in the first subpixel P1 and the first conductive layer pattern in the second subpixel P2 may be substantially mirror-symmetrical with respect to a vertical reference line, and the first conductive layer pattern in the third subpixel P3 and the first conductive layer pattern in the fourth subpixel P4 may be substantially mirror-symmetrical with respect to the vertical reference line. The horizontal reference line may be a straight line extending along the first direction X and bisecting the display area 110 in the second direction Y, and the vertical reference line may be a straight line extending along the second direction Y and bisecting the display area 110 in the first direction X.

[0144] After this patterning process, the first electrode 11 , the electrode connecting electrode 12 and the compensation connecting line 13 are formed in the display area 110 , and the light-transmitting area 120 has no corresponding film layer.

[0145] (2) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on the substrate on which the aforementioned pattern is formed, patterning the semiconductor film through a patterning process to form a first insulating layer covering the first conductive layer, and a semiconductor layer disposed on the first insulating layer, as shown in FIG8A and FIG8B , where FIG8B is a schematic diagram of the semiconductor layer in FIG8A .

[0146] In an exemplary embodiment, the semiconductor layer of each sub-pixel in the display substrate may include at least a first active layer 21, a second active layer 22, and a third active layer 23, the first active layer 21 serving as an active layer of the first transistor T1, the second active layer 22 serving as an active layer of the second transistor T2, and the third active layer 23 serving as an active layer of the third transistor T3.

[0147] In an exemplary embodiment, for the first subpixel P1 and the second subpixel P2, the first active layer 21 and the third active layer 23 can be disposed on one side of the first electrode plate 11 of the subpixel in the second direction Y, and the second active layer 22 can be disposed in an end region of the first electrode plate 11 of the subpixel away from the first active layer 21 and the third active layer 23. The orthographic projection of the second active layer 22 on the substrate is within the range of the orthographic projection of the first electrode plate 11 of the subpixel on the substrate. This allows the first electrode plate 11, acting as a shielding layer, to shield the channel region of the second transistor T2, preventing light from affecting the channel and ensuring the electrical performance of the second transistor T2. The third active layer 23 of the first subpixel P1 can be disposed on one side of the first active layer 21 of the subpixel in the first direction X, and the third active layer 23 of the second subpixel P2 can be disposed on a side of the first active layer 21 of the subpixel opposite to the first direction X.

[0148] In an exemplary embodiment, for the third subpixel P3 and the fourth subpixel P4, the first active layer 21 and the third active layer 23 can be disposed on the side of the first electrode plate 11 of the subpixel opposite to the second direction Y, and the second active layer 22 can be disposed in the end region of the first electrode plate 11 of the subpixel away from the first active layer 21 and the third active layer 23. The orthographic projection of the second active layer 22 on the substrate is within the orthographic projection of the first electrode plate 11 of the subpixel on the substrate. This allows the first electrode plate 11, acting as a shielding layer, to shield the channel region of the second transistor T2, preventing light from affecting the channel and ensuring the electrical performance of the second transistor T2. The third active layer 23 of the third subpixel P3 can be disposed on the side of the first active layer 21 of the subpixel opposite to the first direction X, and the third active layer 23 of the fourth subpixel P4 can be disposed on the side of the first active layer 21 of the subpixel in the first direction X.

[0149] In an exemplary embodiment, the third active layer 23 of the first subpixel P1 and the third active layer 23 of the third subpixel P3 may be interconnected as a single unitary structure, and the third active layer 23 of the second subpixel P2 and the third active layer 23 of the fourth subpixel P4 may be interconnected as a single unitary structure. That is, the third active layers 23 of two subpixels in adjacent pixel rows are interconnected as a single unitary structure. By providing a shared source electrode for the second transistors of two adjacent subpixels in a pixel column, the present disclosure not only saves space but also reduces the number of via connection structures, simplifying the manufacturing process.

[0150] In an exemplary embodiment, the first active layer 21 and the third active layer 23 may be in an "I" shape, and the second active layer 22 may be in a rectangular shape. The corners of the rectangle may be chamfered, and the sides of the rectangle may be grooved.

[0151] In example embodiments, the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.

[0152] In the exemplary embodiment, the orthographic projection of the first active layer 21 on the substrate does not overlap with the orthographic projection of the first electrode plate 11 on the substrate, and the orthographic projection of the third active layer 23 on the substrate does not overlap with the orthographic projection of the first electrode plate 11 on the substrate. By providing a non-overlapping region between the first active layer 21 and the first electrode plate 11, and between the third active layer 23 and the first electrode plate 11, the present disclosure facilitates designing the channel width-to-length ratios of the first and third transistors according to relevant requirements.

[0153] In an exemplary embodiment, the first active layer 21 and the third active layer 23 in the first subpixel P1 and the first active layer 21 and the third active layer 23 in the third subpixel P3 may be substantially mirror-symmetrical with respect to a vertical reference line, and the first active layer 21 and the third active layer 23 in the second subpixel P2 and the first active layer 21 and the third active layer 23 in the fourth subpixel P4 may be substantially mirror-symmetrical with respect to the vertical reference line.

[0154] In exemplary embodiments, the semiconductor layer may be formed of a metal oxide, such as an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, an oxide containing indium, gallium, and zinc, etc. The semiconductor layer may be a single layer, a double layer, or a multilayer.

[0155] In an exemplary embodiment, after this patterning process, a semiconductor layer pattern is formed in the display region 110 , and the film layer in the light-transmitting region 120 includes a first insulating layer.

[0156] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a second insulating film and a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film through a patterning process to form a second insulating layer covering the semiconductor layer, and a second conductive layer pattern disposed on the second insulating layer, as shown in FIG9A and FIG9B , where FIG9B is a schematic diagram of the second conductive layer in FIG9A .

[0157] In an exemplary embodiment, the second conductive layer in at least one repeating unit may include at least one scan signal line 31. The scan signal line 31 may be in the shape of a line extending along the first direction X and may be disposed in the middle of the repeating unit in the second direction Y, that is, between the first subpixel P1 and the second subpixel P2 and the third subpixel P3 and the fourth subpixel P4. The region where the scan signal line 31 overlaps with the plurality of first active layers may serve as the gate electrodes of the plurality of first transistors T1, and the region where the scan signal line 31 overlaps with the plurality of third active layers may serve as the gate electrodes of the plurality of third transistors T3.

[0158] In an exemplary embodiment, the scan signal line 31 may include a double line segment 31-1 and a single line segment 31-2. The double line segment 31-1 may be located in the display area 110, and the single line segment 31-2 may be located in the light-transmitting area 120. That is, the display area 110 is provided with two signal lines, while the light-transmitting area 120 is provided with only one signal line.

[0159] In an exemplary embodiment, the double line segment 31-1 of the display area 110 may include a first sub-line 31a and a second sub-line 31b extending along the first direction X. The first sub-line 31a and the second sub-line 31b are arranged along the second direction Y. The second sub-line 31b may be disposed on one side of the first sub-line 31a in the second direction Y. The first sub-line 31a may be connected to the pixel driving circuits of two sub-pixels in the first pixel row, respectively, and the second sub-line 31b may be connected to the pixel driving circuits of two sub-pixels in the second pixel row, respectively. This enables connection between the double line segment 31-1 and multiple pixel driving circuits in a repeating unit.

[0160] In an exemplary embodiment, the orthographic projection of the first sub-line 31a on the substrate at least partially overlaps with the orthographic projections of the first active layer 21 and the third active layer 23 in the first sub-pixel P1 and the second sub-pixel P2 on the substrate, respectively, and the overlapping areas serve as the gate electrodes of the first transistor T1 and the third transistor T3, respectively, that is, the first sub-line 31a is simultaneously connected to the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 in the first sub-pixel P1 and the second sub-pixel P2. The orthographic projection of the second sub-line 31b on the substrate at least partially overlaps with the orthographic projections of the first active layer 21 and the third active layer 23 in the third sub-pixel P3 and the fourth sub-pixel P4 on the substrate, respectively. The overlapping areas serve as the gate electrodes of the first transistor T1 and the third transistor T3, respectively. That is, the second sub-line 31b is simultaneously connected to the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 in the third sub-pixel P3 and the fourth sub-pixel P4, respectively, so that the double line segment 31-1 transmitting the same scan signal simultaneously controls the conduction or disconnection of all the first transistors T1 and all the third transistors T3 in the four sub-pixels of the repeating unit.

[0161] In an exemplary embodiment, the double line segment 31-1 of the display area 110 may further include a first connecting line 31c and a second connecting line 31d. The first connecting line 31c may be connected to the ends of the first sub-line 31a and the second sub-line 31b in the opposite direction of the first direction X, respectively. The second connecting line 31d may be connected to the ends of the first sub-line 31a and the second sub-line 31b in the first direction X, respectively. The first connecting line 31c, the first sub-line 31a, the second connecting line 31d, and the second sub-line 31b are sequentially connected to form a ring structure. In an exemplary embodiment, the ring shape may be a rectangular ring or a polygonal ring.

[0162] In an exemplary embodiment, the single line segment 31-2 may be located in the extending direction of the first sub-line 31a or the second sub-line 31b, the first connecting line 31c may be connected to the single line segment 31-2 in the light-transmitting region 120 in the opposite direction of the first direction X of the display area 110, and the second connecting line 31d may be connected to the single line segment 31-2 in the light-transmitting region 120 in the first direction X of the display area 110. The double line segment 31-1 and the single line segment 31-2 constitute a continuous scan signal line 31. Thus, the double line segment 31-1 in the display area 110 and the single line segment 31-2 in the light-transmitting region 120 constitute a continuous scan signal line 31.

[0163] In an exemplary embodiment, for multiple repeating units arranged sequentially in the first direction X, the double line segment 31-1 and the single line segment 31-2 in each repeating unit can be an integrated structure connected to each other, and the multiple double line segments 31-1 and the multiple single line segments 31-2 in the multiple repeating units can be an integrated structure connected to each other.

[0164] In an exemplary embodiment, in at least one repeating unit, the orthographic projection of the third active layer of the integrated structure in two sub-pixels of adjacent pixel rows on the substrate at least partially overlaps with the orthographic projection of the ring structure of the scan signal line 31 on the substrate.

[0165] In an exemplary embodiment, in at least one repeating unit, the orthographic projection of the compensation connection line 13 on the substrate may be located within the range of the orthographic projection of the region enclosed by the ring structure of the scan signal line 31 on the substrate.

[0166] In an exemplary embodiment, the second conductive layer of each sub-pixel in the display substrate may include at least a second electrode 32 , a second gate electrode 33 , and a power connection electrode 34 .

[0167] In an exemplary embodiment, the shape of the second electrode plate 32 can be rectangular, the corners of the rectangle can be chamfered, and it can be set at a position close to the scanning signal line 31 of the sub-pixel. The positive projection of the second electrode plate 32 on the substrate at least partially overlaps with the positive projection of the first electrode plate 11 on the substrate. The second electrode plate 32 can serve as an intermediate electrode plate of the storage capacitor, and the first electrode plate 11 and the second electrode plate 32 form a first capacitor.

[0168] In an exemplary embodiment, an opening may be provided on a side of the second electrode plate 32 away from the third active layer, and the opening is configured to accommodate a seventh via hole formed subsequently, so that the third electrode plate formed subsequently is connected to the first electrode plate 11 through the via hole.

[0169] In an exemplary embodiment, the second gate electrode 33 may be in the shape of a strip extending along the second direction Y, and may be located on the side of the second electrode 32 of the sub-pixel away from the scanning signal line 31. The first end of the second gate electrode 33 is connected to the second electrode 32 of the sub-pixel, and the second end of the second gate electrode 33 extends in a direction away from the scanning signal line 31. The orthographic projection of the second gate electrode 33 on the substrate at least partially overlaps with the orthographic projection of the second active layer 22 on the substrate. The second gate electrode 33 serves as the gate electrode of the second transistor T2.

[0170] In an exemplary embodiment, the second electrode plate 32 and the second gate electrode 33 may be an integral structure connected to each other.

[0171] In an exemplary embodiment, the power connection electrode 34 may be rectangular in shape and may be located on a side of the second gate electrode 33 of the sub-pixel away from the scanning signal line 31 . The power connection electrode 34 is configured to be connected to the first electrode of the second transistor T2 through a second connection electrode formed subsequently.

[0172] In an exemplary embodiment, the second conductive layer in at least one repeating unit may further include a first power auxiliary line 35 , a second power auxiliary line 36 , a power connection line 37 , and an electrode connection line 38 .

[0173] In an exemplary embodiment, the first auxiliary power supply line 35 may be in the shape of a strip extending along the second direction Y. It may be disposed in each of the first subpixel P1 and the third subpixel P3, and located on the side of the second electrode plate 32 opposite to the first direction X. The first auxiliary power supply line 35 is configured to connect to a subsequently formed first power supply line, forming a double-layer routing structure with the first power supply line. In an exemplary embodiment, there may be multiple first auxiliary power supply lines 35, and the multiple first auxiliary power supply lines 35 may be spaced apart along the second direction Y.

[0174] In an exemplary embodiment, the second auxiliary power supply line 36 may be in the form of a strip extending along the second direction Y. It may be disposed in the second subpixel P2 and the fourth subpixel P4, respectively, on one side of the second electrode plate 32 in the first direction X. The second auxiliary power supply line 36 is configured to connect to a subsequently formed second power supply line, forming a double-layer routing structure with the second power supply line. In an exemplary embodiment, there may be multiple second auxiliary power supply lines 36, and the multiple second auxiliary power supply lines 36 may be spaced apart along the second direction Y.

[0175] In an exemplary embodiment, the power connection line 37 may be in the shape of a strip extending along the first direction X, and may be provided in each of the first subpixel P1 and the third subpixel P3, and may be located on a side of the second gate electrode 33 of the subpixel away from the scan signal line 31. A first end of the power connection line 37 is connected to the first auxiliary power line 35, and a second end of the power connection line 37 extends along the first direction X and is connected to the power connection electrodes 34 in the first subpixel P1 and the third subpixel P3, respectively, thereby transmitting the first power signal to the power connection electrodes 34 in the first subpixel P1 and the third subpixel P3.

[0176] In an exemplary embodiment, the electrode connection line 38 may be in the shape of a strip extending along the first direction X and may be located between the power connection electrodes 34 of adjacent sub-pixels in the first direction X. The two ends of the electrode connection line 38 in the first pixel row are respectively connected to the power connection electrode 34 of the first sub-pixel P1 and the power connection electrode 34 of the second sub-pixel P2, and the two ends of the electrode connection line 38 in the second pixel row are respectively connected to the power connection electrode 34 of the third sub-pixel P3 and the power connection electrode 34 of the fourth sub-pixel P4, thereby enabling the first power signal to be transmitted to the power connection electrodes 34 in the second sub-pixel P2 and the fourth sub-pixel P4.

[0177] In an exemplary embodiment, the power connection lines 37 and the electrode connection lines 38 are configured to implement a one-to-four structure of the first power lines in one repeating unit.

[0178] In an exemplary embodiment, two power connection electrodes 34 , at least one first power auxiliary line 35 , one power connection line 37 , and one electrode connection line 38 in one pixel row may be an integrated structure connected to each other.

[0179] In an exemplary embodiment, a strip-shaped opening (through hole) extending along the first direction X may be provided in the middle of the electrode connection line 38, so that the electrode connection line 38 forms a ring structure to reduce the overlapping area between the electrode connection line 38 and the subsequently formed data signal line and compensation signal line, reduce the parasitic capacitance between the first power line and the data signal line, reduce the parasitic capacitance between the first power line and the compensation signal line, and improve the display effect.

[0180] In an exemplary embodiment, for the second electrode 32, the second gate electrode 33 and the power connection electrode 34 in the second conductive layer, these patterns in the first sub-pixel P1 and the patterns in the second sub-pixel P2 can be substantially mirror-symmetrical with respect to the vertical reference line, and these patterns in the third sub-pixel P3 and the patterns in the fourth sub-pixel P4 can be substantially mirror-symmetrical with respect to the vertical reference line.

[0181] In an exemplary embodiment, the second conductive layer pattern in the first subpixel P1 and the second conductive layer pattern in the third subpixel P3 can be substantially mirror-symmetrical relative to the horizontal reference line, and the second conductive layer pattern in the second subpixel P2 and the second conductive layer pattern in the fourth subpixel P4 can be substantially mirror-symmetrical relative to the horizontal reference line.

[0182] In an exemplary embodiment, for the double line segment 31 - 1 in the second conductive layer, the double line segment pattern may be substantially mirror-symmetrical with respect to a horizontal reference line and may be substantially mirror-symmetrical with respect to a vertical reference line.

[0183] In an exemplary embodiment, this process can simultaneously pattern the second conductive film and the second insulating film so that the second insulating layer pattern is the same as the second conductive layer pattern.

[0184] In an exemplary embodiment, after forming the first conductive layer pattern, the semiconductor layer can be conductorized using the first conductive layer as a shield. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the third transistor T3, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized.

[0185] In an exemplary embodiment, the scanning signal line 31 is formed in the display area 110 and the light-transmitting area 120, and the second electrode 32, the second gate electrode 33, the power connection electrode 34, the first power auxiliary line 35, the second power auxiliary line 36, the power connection line 37 and the electrode connection line 38 are formed in the display area 110. Therefore, after this patterning process, the film layer of the light-transmitting area 120 includes a first insulating layer and a second insulating layer, and a single line segment of the scanning signal line is arranged on the second insulating layer.

[0186] (4) Forming a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern may include: depositing a third insulating film on the substrate having the aforementioned pattern formed thereon, patterning the third insulating film through a patterning process to form a third insulating layer pattern covering the second conductive layer, wherein a plurality of vias are provided on the third insulating layer, as shown in FIG. 10 .

[0187] In an exemplary embodiment, the multiple via holes of each sub-pixel in the display substrate include at least: a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole V5, a sixth via hole V6, a seventh via hole V7, an eighth via hole V8, a ninth via hole V9, a tenth via hole V10 and an eleventh via hole V11.

[0188] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the third insulating layer and the second insulating layer in the first via hole V1 are etched away to expose the surface of the first region of the first active layer, and the first via hole V1 is configured to connect a subsequently formed data signal line to the first region of the first active layer through the via hole.

[0189] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate may be located within the range of the orthographic projection of the region surrounded by the ring structure of the scan signal line 31 on the substrate.

[0190] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second region of the first active layer on the substrate, the third insulating layer and the second insulating layer in the second via hole V2 are etched away to expose the surface of the second region of the first active layer, and the second via hole V2 is configured to connect a subsequently formed first connecting electrode to the second region of the first active layer through the via hole.

[0191] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the orthographic projection of the first region of the second active layer on the substrate. The third insulating layer and the second insulating layer within the third via hole V3 are etched away, exposing the surface of the first region of the second active layer. The third via hole V3 is configured to connect a subsequently formed second connection electrode to the first region of the second active layer through the via hole. In an exemplary embodiment, multiple third via holes V3 may be provided to increase connection reliability.

[0192] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the orthographic projection of the second region of the second active layer on the substrate. The third insulating layer and the second insulating layer within the fourth via hole V4 are etched away, exposing the surface of the second region of the second active layer. The fourth via hole V4 is configured to connect a subsequently formed third connection electrode to the second region of the second active layer through the via hole. In an exemplary embodiment, multiple fourth via holes V4 may be provided to increase connection reliability.

[0193] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first region of the third active layer on the substrate, the third insulating layer and the second insulating layer within the fifth via hole V5 are etched away to expose the surface of the first region of the third active layer, and the fifth via hole V5 is configured to connect a subsequently formed fourth connecting electrode to the first region of the third active layer through the via hole.

[0194] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate may be located within the range of the orthographic projection of the region surrounded by the ring structure of the scan signal line 31 on the substrate.

[0195] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the second region of the third active layer on the substrate, the third insulating layer and the second insulating layer within the sixth via hole V6 are etched away to expose the surface of the second region of the third active layer, and the sixth via hole V6 is configured to connect a subsequently formed fifth connecting electrode to the second region of the third active layer through the via hole.

[0196] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the first electrode plate 11 on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the seventh via V7 are etched away to expose the surface of the first electrode plate 11, and the seventh via V7 is configured to connect the subsequently formed third electrode plate to the first electrode plate 11 through the via.

[0197] In an exemplary embodiment, the orthographic projection of the eighth via hole V8 on the substrate is located within the range of the orthographic projection of the second electrode plate 32 on the substrate, the third insulating layer in the eighth via hole V8 is etched away to expose the surface of the second electrode plate 32, and the eighth via hole V8 is configured to connect the subsequently formed first connecting electrode to the second electrode plate 32 through the via hole.

[0198] In an exemplary embodiment, the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the end of the compensation connection line 13 close to the third active layer on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the ninth via hole V9 are etched away to expose the surface of the compensation connection line 13, and the ninth via hole V9 is configured to connect the subsequently formed fourth connection electrode to the compensation connection line 13 through the via hole.

[0199] In an exemplary embodiment, the orthographic projection of the ninth via hole V9 on the substrate may be located within the range of the orthographic projection of the region surrounded by the ring structure of the scan signal line 31 on the substrate.

[0200] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the power connection electrode 34 on the substrate, the third insulating layer in the tenth via hole V10 is etched away, exposing the surface of the power connection electrode 34, and the tenth via hole V10 is configured to connect the subsequently formed second connection electrode to the power connection electrode 34 through the via hole.

[0201] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the connecting block 12-1 of the plate connecting electrode 12 on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the eleventh via hole V11 are etched away to expose the surface of the connecting block 12-1, and the eleventh via hole V11 is configured to connect the subsequently formed sixth connecting electrode to the connecting block 12-1 through the via hole.

[0202] In an exemplary embodiment, the at least one repeating unit may further include a twelfth via hole V12 , a thirteenth via hole V13 , and a fourteenth via hole V14 .

[0203] In an exemplary embodiment, a twelfth via hole V12 may be provided in the first subpixel P1 and the third subpixel P3. The orthographic projection of the twelfth via hole V12 on the substrate is within the range of the orthographic projection of the first auxiliary power supply line 35 on the substrate. The third insulating layer within the twelfth via hole V12 is etched away, exposing the surface of the first auxiliary power supply line 35. The twelfth via hole V12 is configured to connect a subsequently formed first power supply line to the first auxiliary power supply line 35 through the via hole. In an exemplary embodiment, there may be multiple twelfth via holes V12, and the multiple twelfth via holes V12 may be arranged sequentially along the second direction Y to increase connection reliability.

[0204] In an exemplary embodiment, a thirteenth via hole V13 may be provided in the second subpixel P2 and the fourth subpixel P4. The orthographic projection of the thirteenth via hole V13 on the substrate is within the range of the orthographic projection of the second auxiliary power supply line 36 on the substrate. The third insulating layer within the thirteenth via hole V13 is etched away, exposing the surface of the second auxiliary power supply line 36. The thirteenth via hole V13 is configured to connect a subsequently formed second power supply line to the second auxiliary power supply line 36 through the via hole. In an exemplary embodiment, there may be multiple thirteenth via holes V13. Multiple thirteenth via holes V13 may be arranged sequentially along the first direction X to form a via hole group. Multiple via hole groups may be arranged sequentially along the second direction Y to increase connection reliability.

[0205] In an exemplary embodiment, the orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the middle portion of the compensation connection line 13 on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the fourteenth via hole V14 are etched away to expose the surface of the compensation connection line 13, and the fourteenth via hole V14 is configured to connect a subsequently formed compensation signal line to the compensation connection line 13 through the via hole.

[0206] In an exemplary embodiment, the orthographic projection of the fourteenth via hole V14 on the substrate may be located within the range of the orthographic projection of the region surrounded by the ring structure of the scan signal line 31 on the substrate.

[0207] In an exemplary embodiment, the patterning process may use a half tone mask process.

[0208] After this patterning process, the film layer of the light-transmitting region 120 includes a first insulating layer, a second insulating layer and a third insulating layer.

[0209] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, patterning the third conductive film through a patterning process, and forming a third conductive layer pattern on the third insulating layer, as shown in FIG. 11A and FIG. 11B , where FIG. 11B is a schematic diagram of the third conductive layer in FIG. 1A .

[0210] In an exemplary embodiment, the third conductive layer of each repeating unit in the display substrate may include at least one first power line 51 , one second power line 52 , four data signal lines 53 , one compensation signal line 54 , two auxiliary electrode lines 55 and two first auxiliary electrodes 56 .

[0211] In an exemplary embodiment, the first power line 51, the second power line 52, the data signal line 53, and the compensation signal line 54 may be shaped as straight lines with the main portion extending along the second direction Y. The first power line 51 may be located on one side of the display area 110 in the first direction X, the second power line 52 may be located on the other side of the display area 110 in the first direction X, the compensation signal line 54 may be located between the first power line 51 and the second power line 52, two of the four data signal lines 53 may be located between the first power line 51 and the compensation signal line 54, and the other two of the four data signal lines 53 may be located between the second power line 52 and the compensation signal line 54.

[0212] In an exemplary embodiment, the first power line 51 may be located on one side of the display area 110 in the opposite direction of the first direction X, and the second power line 52 may be located on one side of the display area 110 in the first direction X. The first power line 51 and the compensation signal line 54 may define a first pixel column, and the two data signal lines 53 are disposed in the first pixel column. The second power line 52 and the compensation signal line 54 may define a second pixel column, and the two data signal lines 53 are disposed in the second pixel column.

[0213] In an exemplary embodiment, the present disclosure arranges the first power line 51 and the second power line 52 on both sides of the display area 110. In a repeating unit, the first power line 51 and the second power line 52 are separated by two pixel driving circuits. In two adjacent repeating units in the first direction X, the first power line 51 and the second power line 52 are separated by a light-transmitting area 120, so that the distance between the two is relatively far, which can effectively prevent a short circuit caused by the overlap of the two, and minimize the risk of high-current burn-in caused by a short circuit.

[0214] In an exemplary embodiment, the positions of the first power line 51 and the second power line 52 can be substantially mirror-symmetrical with respect to the compensation signal line 54, and the two data signal lines 53 in the first pixel column and the two data signal lines 53 in the second pixel column can be substantially mirror-symmetrical with respect to the compensation signal line 54.

[0215] In an exemplary embodiment, the first power line 51 can be connected to multiple first power auxiliary lines 35 through multiple twelfth vias V12 respectively. The first power line 51 and the first power auxiliary line 35 form a double-layer routing structure, which ensures the reliability of power signal transmission, can effectively reduce the resistance of the first power line, effectively reduce the voltage drop of the first power signal, and improve the display effect.

[0216] In an exemplary embodiment, the second power line 52 can be connected to multiple second power auxiliary lines 36 through multiple thirteenth vias V13 respectively. The second power line 52 and the second power auxiliary line 36 form a double-layer routing structure, which ensures the reliability of power signal transmission, can effectively reduce the resistance of the second power line, effectively reduce the voltage drop of the second power signal, and improve the display effect.

[0217] In an exemplary embodiment, each data signal line 53 may be connected to the first region of the first active layer in one sub-pixel through the first via hole V1 , thereby enabling the data signal line 53 to write the data signal into the first electrode of the first transistor T1 .

[0218] In an exemplary embodiment, the four data signal lines 53 may include a first data signal line, a second data signal line, a third data signal line, and a fourth data signal line. The first data signal line may be located on one side of the first power line 51 in the first direction X and may be connected to the first region of the first active layer in the first subpixel P1 through a first via hole V1. The second data signal line may be located on one side of the compensation signal line 54 in the opposite direction of the first direction X and may be connected to the first region of the first active layer in the third subpixel P3 through a first via hole V1. The third data signal line may be located on one side of the compensation signal line 54 in the first direction X and may be connected to the first region of the first active layer in the fourth subpixel P4 through a first via hole V1. The fourth data signal line may be located on one side of the second power line 52 in the opposite direction of the first direction X and may be connected to the first region of the first active layer in the second subpixel P2 through a first via hole V1.

[0219] In an exemplary embodiment, the compensation signal line 54 can be connected to the compensation connection line 13 via the fourteenth via hole V14, so that the compensation signal line 54 can provide a compensation signal to the pixel driving circuit in each sub-pixel through the compensation connection line 13. As a result, the four pixel driving circuits in a display area 110 can share a single compensation connection line 13, i.e., the compensation connection lines in a repeating unit form a one-to-four structure. By designing the compensation signal lines as a one-to-four structure, the display substrate of the present disclosure reduces the number of signal lines and the space occupied. The structure is simple, the layout is rational, and the layout space is fully utilized, improving space utilization and facilitating improved resolution and transparency.

[0220] In an exemplary embodiment, since the compensation signal line 54 is arranged between the first pixel column and the second pixel column, the compensation signal line 54 is connected to the third transistors T3 in the first pixel column and the second pixel column through the compensation connection line 13, and the third transistor T3 of the first pixel column and the third transistor T3 of the second pixel column are symmetrically arranged with respect to the compensation signal line 54, such a symmetrical structure can ensure that the RC delay of the compensation signal written into the third transistor T3 is substantially the same, thereby ensuring display uniformity.

[0221] In an exemplary embodiment, two auxiliary electrode lines 55 and two first auxiliary electrodes 56 may be disposed in the light-transmitting region 120 of the repeating unit. The auxiliary electrode lines 55 may be in the shape of a strip extending along the first direction X. The first ends of the auxiliary electrode lines 55 are connected to the second power lines 52, and the second ends of the auxiliary electrode lines 55 extend away from the second power lines 52 and then connect to the auxiliary electrodes 55. The first auxiliary electrodes 56 may be in the shape of a rectangle and are configured to connect to the second auxiliary electrodes formed subsequently. Since the first auxiliary electrodes 56 are connected to the second power lines 52 via the auxiliary electrode lines 55, and the second auxiliary electrodes are configured to connect to the cathode formed subsequently, the connection between the second power lines 52 and the cathode can be achieved.

[0222] In an exemplary embodiment, two auxiliary electrode lines 55 and two first auxiliary electrodes 56 may be disposed in the light-transmitting region 120 on one side in the first direction X of the second subpixel P2 and the fourth subpixel P4 .

[0223] In an exemplary embodiment, the extension lengths of the two auxiliary electrode lines 55 in the first direction X may be the same or different, and the areas of the two first auxiliary electrodes 56 may be the same or different.

[0224] In an exemplary embodiment, the second power line 52 , the two auxiliary electrode lines 55 , and the two first auxiliary electrodes 56 may be an integral structure connected to each other.

[0225] In an exemplary embodiment, taking into account the voltage drop (IR Drop) problem existing in large-size transparent displays, the embodiment of the present disclosure specifically sets a second power line for transmitting a low-voltage signal in each repeating unit. The second power line is connected to the cathode in the subsequently formed light-emitting structure layer through an auxiliary electrode, which can effectively reduce the voltage drop of the second power signal, effectively solve the voltage drop problem existing in large-size transparent displays, and ensure display uniformity.

[0226] In an exemplary embodiment, the third conductive layer of each subpixel in the display substrate may include at least first, second, third, fourth, fifth, and sixth connection electrodes 41 , 42 , 43 , 44 , 45 , and 46 , and a third plate 47 .

[0227] In an exemplary embodiment, the shape of the first connection electrode 41 can be a strip shape with a main portion extending along the second direction Y, the first end of the first connection electrode 41 is connected to the second region of the first active layer through the second via hole V2, and the second end of the first connection electrode 41 is connected to the second electrode plate 32 through the eighth via hole V8, so that the second electrode of the first transistor T1 of each sub-pixel and the second electrode plate 32 have the same potential.

[0228] In an exemplary embodiment, the second connection electrode 42 may be in the shape of a strip with a main portion extending along the second direction Y. A first end of the second connection electrode 42 is connected to the first region of the second active layer via a third via hole V3, and a second end of the second connection electrode 42 is connected to the power connection electrode 34 via a tenth via hole V10. Since the power connection electrode 34 is connected to the first auxiliary power line 35 via a power connection line 37, and the first auxiliary power line 35 is connected to the first power line via a via hole, the first power line is connected to the first region of the second active layer. The first power line can write a first power signal to the first electrode of the second transistor T2 of each sub-pixel.

[0229] In an exemplary embodiment, the shape of the third connection electrode 43 can be a strip shape with a main portion extending along the second direction Y, a first end of the third connection electrode 43 is connected to the third electrode plate 47, and a second end of the third connection electrode 43 is connected to the second region of the second active layer through a fourth via hole V4, so that the second electrode of the second transistor T2 of each sub-pixel and the third electrode plate 47 have the same potential.

[0230] In an exemplary embodiment, the fourth connection electrode 44 may be in the shape of a strip with a main portion extending along the first direction X. A first end of the fourth connection electrode 44 is connected to the first region of the third active layer via a fifth via hole V5, and a second end of the fourth connection electrode 44 is connected to the compensation connection line 13 via a ninth via hole V9. Since the compensation connection line 13 is connected to the compensation signal line via the via hole, the compensation signal line is connected to the first region of the third active layer. The compensation signal line can write a compensation signal into the first electrode of the third transistor T3 of each sub-pixel.

[0231] In an exemplary embodiment, the shape of the fifth connection electrode 45 can be a strip shape with a main portion extending along the second direction Y, the first end of the fifth connection electrode 45 is connected to the third electrode plate 47, and the second end of the fifth connection electrode 45 is connected to the second region of the third active layer through the sixth via hole V6, so that the second electrode of the third transistor T3 of each sub-pixel and the third electrode plate 47 have the same potential.

[0232] In an exemplary embodiment, the shape of the sixth connecting electrode 46 can be rectangular, and the orthographic projection of the sixth connecting electrode 46 on the substrate at least partially overlaps with the orthographic projection of the connecting block 12-1 of the plate connecting electrode on the substrate. The sixth connecting electrode 46 is connected to the connecting block 12-1 through the eleventh via V11, and the sixth connecting electrode 46 is configured to be connected to the anode connecting electrode formed subsequently.

[0233] In an exemplary embodiment, the third electrode plate 47 may be rectangular, with chamfered corners. The third electrode plate 47 may be located near the scan signal line 31 of the sub-pixel. The third electrode plate 47 is connected to the first electrode plate 11 via a seventh via hole V7. The orthographic projection of the third electrode plate 47 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 32 on the substrate. The third electrode plate 47 may serve as the upper plate of the storage capacitor, and the second electrode plate 32 and the third electrode plate 47 form a second capacitor.

[0234] In an exemplary embodiment, the third connection electrode 43 , the fifth connection electrode 45 , and the third electrode plate 47 may be an integral structure connected to each other.

[0235] In an exemplary embodiment, since the first connecting electrode 41 is connected to the second electrode plate 32, and the second electrode plate 32 is connected to the second gate electrode 33, the first connecting electrode 41 causes the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the first end of the storage capacitor (including the second electrode plate 32) to have the same potential, and the first connecting electrode 41 can serve as the first node N1 of the pixel driving circuit.

[0236] In an exemplary embodiment, since the third connection electrode 43 is connected to the second region of the second active layer, the fifth connection electrode 45 is connected to the second region of the third active layer, the third connection electrode 43 and the fifth connection electrode 45 are connected to the third electrode plate 47, and the first electrode plate 11 and the third electrode plate 47 are connected, the third connection electrode 43 and the fifth connection electrode 45 cause the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the second end of the storage capacitor (including the first electrode plate 11 and the third electrode plate 47) to have the same potential, and the third connection electrode 43 and the fifth connection electrode 45 can serve as the second node N2 in the pixel driving circuit.

[0237] In an exemplary embodiment, since the second plate 32 has a potential of the first node N1, and the first plate 11 and the third plate 47 have a potential of the second node N2, the second node N2 having a potential of the first node N1 and the first plate 11 having a potential of the second node N2 constitute a first capacitor of the pixel driving circuit, and the second node N2 having a potential of the first node N1 and the third plate 47 having a potential of the second node N2 constitute a second capacitor of the pixel driving circuit, with the first capacitor and the second capacitor being connected in parallel. The present disclosure utilizes the first conductive layer, the second conductive layer, and the third conductive layer to form a parallel structure of the first and second capacitors. The parallel structure of the first and second capacitors constitutes a complete storage capacitor of the pixel driving circuit. This can effectively increase the capacitance of the storage capacitor and reduce the plate area while maintaining the capacitance of the storage capacitor, effectively reducing the occupied area.

[0238] In an exemplary embodiment, since the first power auxiliary line 35 is connected to the two power connection electrodes 34 in a pixel row through the power connection line 37 and the electrode connection line 38, and the first power line 51 is connected to the first power auxiliary line 35, the four pixel driving circuits in a display area 110 can share one first power line 51, that is, the first power line in a repeating unit is a one-to-four structure, which can reduce the occupied space of the display area, increase the area ratio of the light-transmitting area, and improve the resolution and transparency.

[0239] In an exemplary embodiment, in at least one repeating unit, the orthographic projections of the first power line 51 , the second power line 52 , the data signal line 53 and the compensation signal line 54 on the substrate at least partially overlap with the orthographic projection of the ring structure of the scan signal line 31 on the substrate.

[0240] After this patterning process, the film layer of the light-transmitting region 120 includes a first insulating layer, a second insulating layer and a third insulating layer.

[0241] (6) Forming a fourth insulating layer and a first planar layer pattern. In an exemplary embodiment, forming the fourth insulating layer and the first planar layer pattern may include: first depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, then coating the first planar film, patterning the fourth insulating film and the first planar film through a patterning process to form a fourth insulating layer covering the third conductive layer and a first planar layer pattern disposed on the fourth insulating layer, wherein a plurality of vias are disposed on the fourth insulating layer and the first planar layer, as shown in FIG. 12 .

[0242] In an exemplary embodiment, the first planar layer is only provided in the display area 110 , and the first planar layer in the light-transmitting area 120 is completely removed, including the area where the plate connecting electrode 12 and the first auxiliary electrode 56 are located.

[0243] In an exemplary embodiment, at least one repeating unit may include four twenty-first via holes V21 and two twenty-second via holes V22 .

[0244] In an exemplary embodiment, the orthographic projection of each twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the sixth connecting electrode 46 on the substrate, the fourth insulating layer in the twenty-first via hole V21 is etched away to expose the surface of the sixth connecting electrode 46, and the twenty-first via hole V21 is configured to connect the subsequently formed anode connecting electrode to the sixth connecting electrode 46 through the via hole.

[0245] In an exemplary embodiment, the orthographic projection of each twenty-second via V22 on the substrate is located within the range of the orthographic projection of the first auxiliary electrode 56 on the substrate, the fourth insulating layer in the twenty-second via V22 is etched away to expose the surface of the first auxiliary electrode 56, and the twenty-second via V22 is configured to connect the subsequently formed second auxiliary electrode to the first auxiliary electrode 56 through the via.

[0246] In an exemplary embodiment, the patterning process may use a half tone mask process.

[0247] After this patterning process, the film layers of the light-transmitting region 120 include a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer.

[0248] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film through a patterning process to form a fourth conductive layer pattern, as shown in FIG13A and FIG13B , where FIG13B is a schematic diagram of the fourth conductive layer in FIG3A .

[0249] In an exemplary embodiment, the fourth conductive layer of each sub-pixel in the display substrate may include at least a first anode 61 and an anode connection electrode 62 .

[0250] In an exemplary embodiment, the first anode 61 in at least one sub-pixel may include a first sub-anode 61-1 and a second sub-anode 61-2 that are isolated from each other. The shapes of the first sub-anode 61-1 and the second sub-anode 61-2 may be rectangular, and may be located in the display area 110 and arranged on the first flat layer. The first sub-anode 61-1 and the second sub-anode 61-2 may be arranged sequentially along the second direction Y.

[0251] In an exemplary embodiment, the anode connection electrode 62 may be C-shaped, may be located in the light-transmitting region 120, and may be disposed on the fourth insulating layer. A first end of the anode connection electrode 62 is connected to the first sub-anode 61-1, and a second end of the anode connection electrode 62 is connected to the second sub-anode 61-2. The area between the first and second ends is connected to the sixth connection electrode 46 via a twenty-first via hole V21. In an exemplary embodiment, the anode connection electrode 62 interconnects the first sub-anode 61-1 and the second sub-anode 61-2. Because the sixth connection electrode 46 is connected to the plate connection electrode 12, which is connected to the first plate 11, the anode connection electrode 62 connects the first anode 61 to the first plate 11 of the storage capacitor.

[0252] In an exemplary embodiment, when a bright spot defect occurs on the display substrate, the anode connection electrode 62 can be cut off by laser cutting so that one of the first sub-anode 61-1 and the second sub-anode 61-2 is connected to the first electrode plate 11 and the other is floating, thereby repairing the bright spot defect.

[0253] In an exemplary embodiment, the twenty-first via hole V21 can be called an anode via hole, and the orthographic projection of the anode via hole on the substrate does not overlap with the orthographic projections of the first sub-anode 61-1 and the second sub-anode 61-2 on the substrate. This not only improves the success rate of repairing bright spot defects and avoids the impact of the repair on the pixel driving circuit, but also ensures the flatness of the anode, improves the light output quality of the light-emitting device, and improves the display effect.

[0254] In an exemplary embodiment, the four first anodes 61 are arranged in a square. The upper left first anode 61 is connected to the pixel driving circuit in the first sub-pixel P1, the upper right first anode 61 is connected to the pixel driving circuit in the second sub-pixel P2, the lower left first anode 61 is connected to the pixel driving circuit in the third sub-pixel P3, and the lower right first anode 61 is connected to the pixel driving circuit in the fourth sub-pixel P4. In some possible implementations, the arrangement of the anodes can be adjusted according to actual needs and is not specifically limited in this disclosure.

[0255] In an exemplary embodiment, the first sub-anode 61 - 1 , the second sub-anode 61 - 2 , and the anode connection electrode 62 of each sub-pixel may be an integral structure connected to each other.

[0256] In an exemplary embodiment, the fourth conductive layer of at least one repeating unit may further include a second auxiliary electrode 63. The second auxiliary electrode 63 may be rectangular in shape, and the orthographic projection of the second auxiliary electrode 63 on the substrate at least partially overlaps with the orthographic projection of the first auxiliary electrode 56 on the substrate. The second auxiliary electrode 63 may be connected to the first auxiliary electrode 56 through a twenty-second via hole V22, and the second auxiliary electrode 63 is configured to be connected to a third auxiliary electrode formed subsequently.

[0257] In an exemplary embodiment, the fourth conductive layer may be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0258] After this patterning process, the film layer in the light-transmitting area 120 remains unchanged.

[0259] (8) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer pattern may include: depositing a fifth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fifth conductive film through a patterning process to form a fifth conductive layer pattern, as shown in FIG14A and FIG14B , where FIG14B is a schematic diagram of the fifth conductive layer in FIG4A .

[0260] In an exemplary embodiment, the fifth conductive layer of each sub-pixel in the display substrate may include at least the second anode 72 .

[0261] In an exemplary embodiment, the second anode 72 may include a third sub-anode 72-1 and a fourth sub-anode 72-2 that are isolated from each other. The third sub-anode 72-1 and the fourth sub-anode 72-2 may be rectangular in shape and may be located in the display area 110 and respectively arranged on the first sub-anode 61-1 and the second sub-anode 61-2. The third sub-anode 72-1 and the fourth sub-anode 72-2 may be arranged in sequence along the second direction Y. The orthographic projection of the third sub-anode 72-1 on the substrate at least partially overlaps with the orthographic projection of the first sub-anode 61-1 on the substrate. The third sub-anode 72-1 is connected to the first sub-anode 61-1. The orthographic projection of the fourth sub-anode 72-2 on the substrate at least partially overlaps with the orthographic projection on the substrate. The fourth sub-anode 72-2 is connected to the second sub-anode 61-2.

[0262] In an exemplary embodiment, the fifth conductive layer of at least one repeating unit may further include a third auxiliary electrode 73. The third auxiliary electrode 73 may be rectangular in shape, the second auxiliary electrode 63 may be disposed on the second auxiliary electrode 63, the orthographic projection of the second auxiliary electrode 63 on the substrate at least partially overlaps with the orthographic projection of the second auxiliary electrode 63 on the substrate, the second auxiliary electrode 63 is connected to the second auxiliary electrode 63, and the third auxiliary electrode 73 is configured to be connected to a cathode formed subsequently.

[0263] In an exemplary embodiment, the third auxiliary electrode 73 can adopt an isolation column (RIB) structure, and the cross-sectional shape of the third auxiliary electrode 73 can be an inverted trapezoid, so that the subsequently formed organic light-emitting layer can be disconnected at the side edge of the third auxiliary electrode 73 to form an isolated and isolated organic light-emitting block, which effectively avoids the interference of the organic light-emitting block on the outgoing light, improves the quality of the outgoing light, and is conducive to improving the display quality.

[0264] In an exemplary embodiment, the stacked first auxiliary electrode 56 , the second auxiliary electrode 63 , and the third auxiliary electrode 73 constitute an auxiliary cathode.

[0265] In an exemplary embodiment, the fifth conductive layer may be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0266] After this patterning process, the film layer in the light-transmitting area 120 remains unchanged.

[0267] (9) Forming a pixel definition layer. In an exemplary embodiment, forming a pixel definition layer pattern may include: coating a pixel definition film on the substrate having the aforementioned pattern formed thereon, and patterning the pixel definition film through a patterning process to form a pixel definition layer, as shown in FIG. 15 .

[0268] In an exemplary embodiment, a first pixel opening K1 and a second pixel opening K2 are provided on the pixel definition layer of each sub-pixel in the display substrate. The pixel definition film in the first pixel opening K1 is removed to expose a portion of the surface of the third sub-anode 72-1 in the second anode 72. The pixel definition film in the second pixel opening K2 is removed to expose a portion of the surface of the fourth sub-anode 72-2 in the second anode 72.

[0269] In an exemplary embodiment, the orthographic projection of the first pixel opening K1 on the substrate is located within the range of the orthographic projection of the third sub-anode 72-1 on the substrate, and the orthographic projection of the second pixel opening K2 on the substrate is located within the range of the orthographic projection of the fourth sub-anode 72-2 on the substrate.

[0270] In an exemplary embodiment, in a plane parallel to the substrate, the shapes of the first pixel opening K1 and the second pixel opening K2 may be similar to the shape of the sub-anode, and in a plane perpendicular to the substrate, the cross-sectional shape of the first pixel opening K1 and the second pixel opening K2 may be rectangular or trapezoidal, etc.

[0271] In an exemplary embodiment, an auxiliary electrode opening K3 is opened on the pixel definition layer of at least one repeating unit, and the pixel definition film in the auxiliary electrode opening K3 is removed to expose a portion of the surface of the third auxiliary electrode 73. The orthographic projection of the auxiliary electrode opening K3 on the substrate is within the range of the orthographic projection of the third auxiliary electrode 73 on the substrate.

[0272] In an exemplary embodiment, the auxiliary electrode opening K3 may have a shape similar to that of the third auxiliary electrode 73 in a plane parallel to the substrate, and may have a rectangular or trapezoidal cross-section in a plane perpendicular to the substrate.

[0273] In an exemplary embodiment, the pixel definition layer of the light-transmitting area 120 is substantially removed to form a light-transmitting opening T. A groove may be provided on a side of the light-transmitting opening T close to the display area 110 , and the pixel definition block provided in the groove may shield the anode connection electrode 62 .

[0274] In an exemplary embodiment, the pixel definition layer may be made of polyimide, acryl, polyethylene terephthalate, or the like.

[0275] (10) Forming an organic light-emitting layer and cathode pattern. In an exemplary embodiment, forming the organic light-emitting layer and cathode pattern may include: first forming an organic light-emitting layer pattern in the display area 110, wherein the organic light-emitting layer is connected to the third sub-anode 72-1 and the fourth sub-anode 72-2 through the first pixel opening K1 and the second pixel opening K2, respectively. Subsequently, a cathode is formed, wherein the cathode is connected to the organic light-emitting layer in the display area 110, and is connected to the third auxiliary electrode 73 in the light-transmitting area 120 through the auxiliary electrode opening K3. Since the third auxiliary electrode 73 is connected to the second power line, the cathode is connected to the second power line.

[0276] In an exemplary embodiment, the organic light-emitting layer may include an emission layer (EML), and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the organic light-emitting layer may be formed using a fine metal mask (FMM) or open mask evaporation, or using an inkjet process.

[0277] In an exemplary embodiment, the preparation process of the display substrate may further include forming an encapsulation layer pattern. Forming the encapsulation layer pattern may include: first depositing a first inorganic thin film using an open mask to form a first encapsulation layer. Subsequently, inkjet printing an organic material on the first encapsulation layer using an inkjet printing process, and after curing into a film, forming a second encapsulation layer. Subsequently, an open mask is used to deposit a second inorganic thin film to form a third encapsulation layer, and the first encapsulation layer, the second encapsulation layer and the third encapsulation layer constitute an encapsulation layer. The first encapsulation layer and the third encapsulation layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiC), silicon carbonitride (SiCN) and silicon oxynitride (SiON), and can be a single layer, a multilayer or a composite layer. The second encapsulation layer can be made of a resin material to form a laminated structure of inorganic material / organic material / inorganic material. The organic material layer is arranged between the two inorganic material layers to ensure that external water vapor cannot enter the light-emitting structure layer.

[0278] In an exemplary embodiment, the preparation process of the display substrate may further include forming a color filter layer and a black matrix, wherein the black matrix has a plurality of opening regions arranged in a matrix, and the color filter layer is filled in the opening regions.

[0279] At this point, the preparation of the display substrate according to the exemplary embodiment of the present disclosure is completed.

[0280] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si).

[0281] In an exemplary embodiment, the first conductive layer, the second conductive layer, and the third conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multilayer, or a composite layer. The first planar layer can be made of an organic material, such as a resin.

[0282] FIG16 is a schematic diagram of a short circuit repair of a display substrate according to an exemplary embodiment of the present disclosure. As shown in FIG16 , when a short circuit point 200 appears between a scan connection line 31 and other signal lines (such as a data signal line 53), the first sub-lines on both sides of the short circuit point 200 can be cut off by laser cutting, forming two truncation points 300 on both sides of the short circuit point 200 to isolate the short circuit point 200. Since the scan connection line 31 in the display area is a double-line segment 31-1 with a double-line structure and a dual-channel function, the truncation point 300 will not affect the pixel drive circuit. This not only ensures that all pixel drive circuits in the repeated area of ​​the scan signal line drive can be repaired, but also short circuit points 200 in all positions can be repaired, thus achieving full signal short circuit repair, avoiding product scrapping, and effectively improving product yield.

[0283] From the structure and preparation process of the display substrate described above, it can be seen that the display substrate provided by the present disclosure adopts a 3T1C pixel driving circuit with one scanning signal line, and one scanning signal line is connected to the first transistor and the third transistor in the pixel driving circuit. By reducing the number of scanning signal lines, it is possible not only to simplify the structure of the pixel driving circuit and reduce the occupied area of ​​the pixel driving circuit, which is conducive to achieving high-resolution display, but also to effectively increase the light-transmitting area of ​​the light-transmitting area and improve the space ratio of the light-transmitting area, which is conducive to achieving high-transparency display. In addition, since a repeating unit only requires one scanning signal line to drive, the number of its corresponding gate driving circuit (GOA) and clock signal line (CLK) can be reduced exponentially, effectively reducing the occupied area of ​​the gate driving circuit and the clock signal line, which is conducive to achieving a narrow frame and improving product advantages.

[0284] The exemplary embodiment of the present disclosure sets a single-line structure in the light-transmitting area and a double-line structure in the display area, which not only ensures that the scanning signal line drives all pixel driving circuits in the repeated area, but also realizes a dual-channel function, can repair signal lines at all positions, realizes full signal short-circuit repair, and effectively improves product yield.

[0285] The exemplary embodiment of the present disclosure utilizes a first conductive layer, a second conductive layer, and a third conductive layer to form a first capacitor and a second capacitor of a three-layer metal layout sandwich structure. The first capacitor and the second capacitor of the parallel structure constitute a storage capacitor. On the one hand, this can effectively increase the capacitance value of the storage capacitor. On the other hand, it can reduce the plate area while ensuring the capacitance value of the storage capacitor, effectively reducing the occupied area of ​​the pixel driving circuit, which is conducive to achieving high-resolution display.

[0286] The exemplary embodiment of the present disclosure saves the number of signal lines and reduces the occupied space by setting a one-to-four structure for the first power line and a one-to-four structure for the compensation signal line. It has a simple structure and a reasonable layout, fully utilizes the layout space, improves space utilization, and is conducive to improving resolution.

[0287] The exemplary embodiment of the present disclosure sets an anode connecting electrode to connect the first sub-anode and the second sub-anode respectively, which not only improves the success rate of repairing bright spot defects, avoids the impact of the repair on the pixel driving circuit, and does not cause other defects, but also has a high repair success rate. It can also ensure the flatness of the anode, improve the light output quality of the light-emitting device, and improve the display effect.

[0288] The exemplary embodiment of the present disclosure provides a second power line and an auxiliary electrode, and the second power line is connected to the cathode through the auxiliary electrode, which can effectively reduce the voltage drop of the second power source and ensure display uniformity.

[0289] The exemplary embodiment of the present disclosure changes the light-transmitting area into an irregular shape by arranging the anode connecting electrode and the auxiliary electrode in the light-transmitting area. When light passes through the irregularly shaped light-transmitting area, the positions and directions of the diffraction stripes generated are different. Therefore, the diffraction stripes generated by the light will not diffuse in one direction, but will diffuse in multiple directions, thereby greatly weakening the diffraction effect, avoiding the blurring of objects behind the screen, and improving the transparent display effect.

[0290] The preparation process of the exemplary embodiment of the present disclosure is well compatible with the existing preparation process, and the process is simple to implement, easy to implement, high in production efficiency, low in production cost, and high in yield rate.

[0291] The structure and preparation process shown above in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0292] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0293] The present disclosure also provides a method for preparing a display substrate, for preparing the display substrate provided in the above embodiment. In an exemplary embodiment, the display substrate includes a plurality of regularly arranged repeating units, wherein the repeating units include a display area and a light-transmitting area located on at least one side of the display area, wherein the display area is configured to display an image, and the light-transmitting area is configured to transmit light; the display area includes a plurality of sub-pixels forming at least two pixel rows and two pixel columns, wherein the sub-pixels include a pixel driving circuit; the preparation method includes:

[0294] A pixel driving circuit is formed in the sub-pixel; the pixel driving circuit includes a first transistor, a second transistor, a third transistor and a storage capacitor, the first electrode of the first transistor is connected to the data signal line, the second electrode of the first transistor is respectively connected to the gate electrode of the second transistor and the first end of the storage capacitor, the first electrode of the second transistor is connected to the first power line, the second electrode of the second transistor is respectively connected to the second electrode of the third transistor and the second end of the storage capacitor, the first electrode of the third transistor is connected to the compensation signal line, and the gate electrode of the first transistor and the gate electrode of the third transistor are connected to the same scanning signal line.

[0295] The present disclosure further provides a display device including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the embodiments of the present invention are not limited thereto.

[0296] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the present invention. Any person skilled in the art may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the present invention shall still be based on the scope defined by the appended claims.

Claims

1. A display substrate, comprising a plurality of regularly arranged repeating units, wherein the repeating units include a display area and a light-transmitting area located at least on one side of the display area, wherein the display area is configured to display an image, and the light-transmitting area is configured to transmit light; the display area includes a plurality of sub-pixels forming at least two pixel rows and two pixel columns, and the sub-pixels include a pixel driving circuit; the pixel driving circuit includes a first transistor, a second transistor, a third transistor and a storage capacitor, wherein a first electrode of the first transistor is connected to a data signal line, a second electrode of the first transistor is respectively connected to a gate electrode of the second transistor and a first end of the storage capacitor, a first electrode of the second transistor is connected to a first power line, a second electrode of the second transistor is respectively connected to a second electrode of the third transistor and a second end of the storage capacitor, a first electrode of the third transistor is connected to a compensation signal line, and in the pixel driving circuit of at least one sub-pixel, a gate electrode of the first transistor and a gate electrode of the third transistor are connected to the same scanning signal line.

2. The display substrate according to claim 1, wherein: In the plurality of pixel driving circuits of at least one pixel row, gate electrodes of the plurality of first transistors and gate electrodes of the plurality of third transistors are connected to the same scanning signal line.

3. The display substrate according to claim 1, wherein: In the plurality of pixel driving circuits of at least one repeating unit, gate electrodes of the plurality of first transistors and gate electrodes of the plurality of third transistors are connected to the same scanning signal line.

4. The display substrate according to claim 1, wherein: In at least one repeating unit, the scanning signal line extends from the display area to the light-transmitting area, and the scanning signal line includes a single line segment of a single-line structure and a double line segment of a double-line structure. The single line segment is arranged in the light-transmitting area, and the double line segment is arranged in the display area. The double line segments are respectively connected to pixel driving circuits of multiple sub-pixels in the repeating unit.

5. The display substrate according to claim 4, wherein: The double line segment includes a first sub-line and a second sub-line extending along the pixel row direction, the first sub-line and the second sub-line are arranged along the pixel column direction, the first sub-line is respectively connected to the pixel driving circuits of multiple sub-pixels in one pixel row, and the second sub-line is respectively connected to the pixel driving circuits of multiple sub-pixels in another adjacent pixel row.

6. The display substrate according to claim 5, wherein: The double line segment also includes a first connecting line and a second connecting line, the first connecting line is respectively connected to one end of the first sub-line and the second sub-line, the second connecting line is respectively connected to the other end of the first sub-line and the second sub-line, and the first connecting line, the first sub-line, the second connecting line and the second sub-line form a ring structure.

7. The display substrate according to claim 6, wherein: The single line segment is located in the extension direction of the first sub-line or the second sub-line.

8. The display substrate according to claim 6, wherein: The first connection line is connected to a single line segment in the light-transmitting area on one side of the display area in the pixel row direction, and the second connection line is connected to a single line segment in the light-transmitting area on the other side of the display area in the pixel row direction.

9. The display substrate according to claim 8, wherein: In at least one repeating unit, the single line segment and the double line segment are interconnected as an integral structure.

10. The display substrate according to claim 6, wherein: The orthographic projections of the first power line, the data signal line and the compensation signal line on the plane of the display substrate at least partially overlap with the orthographic projection of the ring structure on the plane of the display substrate.

11. The display substrate according to claim 6, wherein: In at least one repeating unit, the active layers of the third transistors of two sub-pixels in adjacent pixel rows are interconnected as an integrated structure, and the orthographic projection of the active layer of the third transistor on the plane of the display substrate at least partially overlaps with the orthographic projection of the annular structure on the plane of the display substrate.

12. The display substrate according to claim 1, wherein: In at least one repeating unit, a plurality of sub-pixels are mirror-symmetric with respect to the scanning signal line.

13. The display substrate according to any one of claims 1 to 12, wherein: The first end of the storage capacitor includes a first electrode plate and a third electrode plate, and the second end of the storage capacitor includes a second electrode plate, the orthographic projection of the second electrode plate on the plane of the display substrate at least partially overlaps with the orthographic projection of the first electrode plate on the plane of the display substrate, the first electrode plate and the second electrode plate form a first capacitor, the orthographic projection of the second electrode plate on the plane of the display substrate at least partially overlaps with the orthographic projection of the third electrode plate on the plane of the display substrate, the third electrode plate and the second electrode plate form a second capacitor, the first electrode plate is respectively connected to the third electrode plate, the second electrode of the first transistor and the gate electrode of the second transistor, the second electrode plate is respectively connected to the second electrode of the second transistor and the second electrode of the third transistor, and the first capacitor and the second capacitor constitute a storage capacitor with a parallel structure.

14. The display substrate according to claim 13, wherein: In a direction perpendicular to the display substrate, the display area includes a driving circuit layer arranged on the substrate and a light-emitting structure layer arranged on a side of the driving circuit layer away from the substrate, the driving circuit layer includes at least a first conductive layer, a second conductive layer and a third conductive layer arranged in sequence along a direction away from the substrate, the first electrode plate is arranged in the first conductive layer, the second electrode plate is arranged in the second conductive layer, the third electrode plate is arranged in the third conductive layer, and the third electrode plate is connected to the first electrode plate through a via; at least one repeating unit also includes a electrode connecting electrode, the electrode connecting electrode is arranged in the light-transmitting area, and the electrode connecting electrode is connected to the first electrode plate.

15. The display substrate according to claim 14, wherein: In at least one repeating unit, the plate connecting electrode and the first plate are an integrated structure connected to each other.

16. The display substrate according to claim 14, wherein: The light emitting structure layer at least includes a fourth conductive layer disposed on a side of the third conductive layer away from the substrate, the fourth conductive layer at least includes a first anode and an anode connecting electrode, the first anode is disposed in a plurality of sub-pixels in the display area, the anode connecting electrode is disposed in the light-transmitting area, the anode connecting electrode is connected to the plate connecting electrode through an anode via hole, and the anode via hole is disposed in the light-transmitting area; In at least one sub-pixel, the first anode includes a first sub-anode and a second sub-anode that are isolated from each other, the first end of the anode connecting electrode is connected to the first sub-anode, and the second end of the anode connecting electrode is connected to the second sub-anode.

17. The display substrate according to claim 14, wherein: The third conductive layer further includes a second power line and a first auxiliary electrode, the second power line is disposed in the display area, the first auxiliary electrode is disposed in the light-transmitting area, and the first auxiliary electrode is connected to the second power line.

18. The display substrate according to claim 17, wherein: In at least one repeating unit, the first auxiliary electrode and the second power line are interconnected as an integral structure.

19. The display substrate according to claim 17, wherein: The orthographic projection of the second power line on the plane of the display substrate at least partially overlaps with the orthographic projection of the ring structure of the scanning signal line on the plane of the display substrate.

20. A display device comprising the display substrate according to any one of claims 1 to 19.

21. A method for preparing a display substrate, the display substrate comprising a plurality of regularly arranged repeating units, the repeating units comprising a display area and a light-transmitting area located at least on one side of the display area, the display area being configured to display an image, and the light-transmitting area being configured to transmit light; The display area includes a plurality of sub-pixels forming at least two pixel rows and two pixel columns, the sub-pixels including a pixel driving circuit; The preparation method comprises: forming a pixel driving circuit in the sub-pixel; The pixel driving circuit includes a first transistor, a second transistor, a third transistor and a storage capacitor, the first electrode of the first transistor is connected to the data signal line, the second electrode of the first transistor is respectively connected to the gate electrode of the second transistor and the first end of the storage capacitor, the first electrode of the second transistor is connected to the first power line, the second electrode of the second transistor is respectively connected to the second electrode of the third transistor and the second end of the storage capacitor, the first electrode of the third transistor is connected to the compensation signal line, and the gate electrode of the first transistor and the gate electrode of the third transistor are connected to the same scanning signal line.

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