Apparatus and method for controlling relay

Abstract

An apparatus for controlling a relay according to an aspect of the present invention comprises: a processor configured to output a basic control signal for controlling the operation of a relay and a recovery signal having differential signal levels according to whether the processor is in a recovery state; a monitoring unit configured to monitor the operation state of the processor and output a determination control signal having differential signal levels according to the operation state of the processor and a retain signal for maintaining the operation state of the relay; and a relay state determination unit configured to, on the basis of a signal level of the recovery signal or the determination control signal, output one of the basic control signal and the retain signal as a relay control signal for controlling on / off of the relay.

Description

Relay control device and method

[0001] This application claims priority to Korean Patent Application No. 10-2023-0077694, filed on June 16, 2023, and all contents disclosed in the specification and drawings of the said application are incorporated herein by reference.

[0002] The present invention relates to a relay control device and method, and more specifically, to a relay control device and method capable of maintaining the operating state of a relay even when a processor is reset due to a system error or the like.

[0003] As the demand for portable electronic devices such as laptops, video cameras, and mobile phones that use electricity as a power source rapidly increases, and as mobile robots, electric bicycles, electric carts, and electric vehicles become more widely commercialized, research into high-performance secondary batteries capable of repeated charging and discharging is actively being conducted.

[0004] Commercialized secondary batteries include nickel-cadmium batteries, nickel-metal hydride batteries, nickel-zinc batteries, and lithium secondary batteries. Among these, lithium secondary batteries have the advantage of being able to charge and discharge freely and have a very low self-discharge rate because they have almost no memory effect compared to nickel-based secondary batteries. In addition, they have the characteristics of high energy density and high operating voltage, so they are being studied more intensively than other types of secondary batteries and are being applied more widely in actual products.

[0005] Recently, secondary batteries are widely used not only in small devices such as portable electronic devices, but also in medium and large devices such as electric vehicles and energy storage systems (ESS).

[0006] In this case, a battery module in which a number of electrically connected secondary batteries are housed together inside a module case is mainly applied, and furthermore, when high power or large capacity is required, a battery pack in which a number of such battery modules are electrically connected is also applied.

[0007] Secondary battery cells, cell assemblies, battery modules, or battery packs (collectively referred to as "batteries") are important factors for power efficiency and safety, so research is actively being conducted on BMS, which monitors the electrical characteristics of the battery and performs feedback control such as charging and discharging using the monitoring results, as well as battery peripheral devices such as relays that control the electrical connection between the battery and the load (motor, electric heater, in-vehicle electrical components, etc.).

[0008] The power system, specifically the processor installed in the power system, controls the on / off of the relay that mediates between the battery and the load according to safety issues such as energy efficiency, stable operation of the battery, and suppression of overcharge / discharge, thereby inducing the supply of optimized power to the load side.

[0009] Electric vehicles (EVs) or hybrid electric vehicles (HEVs) equipped with these power systems are inherently exposed to external environments characterized by strong vibration and varying temperatures and humidity. Furthermore, numerous devices in recent electric vehicles, including air conditioning and heating systems, as well as cameras, navigation systems, brake systems, and suspension systems, are comprised of electrical and electronic components.

[0010] Therefore, the power system, which is installed in electric vehicles and is composed of electrical and electronic components, is constantly exposed to physical or electromagnetic influences, and errors may occur in the processor of the power system.

[0011] When an error occurs in the processor, the processor is designed to be restored to a normal state through a reset state by operating a built-in algorithm, etc., but during this process, a problem occurs in which the processor cannot properly control the relay.

[0012] In particular, if the processor fails to properly control the relay while the vehicle is driving, a fatal safety accident may occur, so it is highly necessary to design the relay so that it remains on and not off even if a system error occurs.

[0013] The present invention was created to solve the above-described problems in the above background, and the purpose of the present invention is to provide a relay control device and method that can maintain the connection state of a relay even when a processor is reset due to a system error, etc., by applying an improved configuration that is relatively simple and can be operated clearly.

[0014] The technical problems to be solved by the present invention are not limited to the problems described above, and other problems not mentioned will be clearly understood by those skilled in the art from the description of the invention described below.

[0015] A relay control device according to one aspect of the present invention may include a processor configured to output a basic control signal for controlling the operation of a relay and a recovery signal having a differential signal level depending on whether the processor is in a recovery state; a monitoring unit configured to monitor an operating state of the processor and output a decision control signal having a differential signal level depending on the operating state of the processor and a retain signal for maintaining the operating state of the relay; and a relay state determination unit configured to output one of the basic control signal and the retain signal as a relay control signal for controlling on / off of the relay based on a signal level of the decision control signal or the recovery signal.

[0016] In addition, the monitoring unit of the present invention may be configured to output a switching control signal, which is a decision control signal having a different signal level from the decision control signal output when the processor is in a normal state, to the relay state determination unit when the operating state of the processor is in a reset state.

[0017] Furthermore, the processor of the present invention may be configured to output, to the relay state determination unit, a transition recovery signal, which is a recovery signal having a different signal level from the recovery signal output in a state other than the recovery state, when its operating state is a recovery state in which it is switched from a reset state to a normal state.

[0018] Preferably, the processor of the present invention may be configured to output the recovery signal, whose signal level has transitioned, to the relay status determination unit when a first reference time has elapsed after the switching recovery signal is output.

[0019] In addition, the monitoring unit of the present invention may be configured to output the switching control signal only when both software monitoring using feedback information for a request and hardware monitoring using whether a trigger signal is received fail.

[0020] Furthermore, the relay status determination unit of the present invention may be configured to output the basic control signal as the relay control signal when the switching recovery signal is received.

[0021] Preferably, the relay status determination unit of the present invention may be configured to output the basic control signal as the relay control signal when the switching control signal is not received, and to output the retain signal as the relay control signal when the switching control signal is received.

[0022] In addition, the monitoring unit of the present invention may be configured to output the retain signal having a signal level corresponding to the basic control signal output by the processor in a normal state immediately before the reset state when the operating state of the processor is a reset state.

[0023] According to an embodiment, the monitoring unit of the present invention may be configured to output the retain signal at a second signal level when the reset state of the processor continues for a second reference time, but to output the retain signal at a first signal level after the second reference time.

[0024] A battery pack according to another aspect of the present invention may include a relay control device according to one aspect of the present invention.

[0025] A vehicle according to another aspect of the present invention may include a relay control device according to one aspect of the present invention.

[0026] A relay control method according to another aspect of the present invention may include a basic signal receiving step of receiving a basic control signal for controlling the operation of a relay and a recovery signal having a differential signal level depending on whether a processor is in a recovery state; a control signal receiving step of receiving a decision control signal having a differential signal level depending on the operating state of the processor and a retain signal for maintaining the operating state of the relay; and a control signal output step of outputting one of the basic control signal and the retain signal as a relay control signal for controlling on / off of the relay based on a signal level of the decision control signal or the recovery signal.

[0027] According to the present invention, not only can the normal state and reset state of the processor be accurately selected, but the selection result can also be organically incorporated into the relay control, thereby further optimizing both the clarity and efficiency of the relay control.

[0028] In addition, according to one aspect of the present invention, even if the processor is reset, the operating state of one or more relays can be effectively maintained, thereby fundamentally preventing operational interruptions or safety accidents caused by the reset of the processor and the subsequent opening of the relay.

[0029] Furthermore, according to one aspect of the present invention, a retain signal is generated to correspond to a control signal output by a processor in a normal state immediately before a reset state, and the relay is controlled using this retain signal, thereby more effectively maintaining the relay state before the reset state.

[0030] In addition, according to one aspect of the present invention, when the operating state of the processor is restored, an architecture is implemented in which the processor itself outputs a recovery signal, thereby providing an advantage in which the operating state of one or more relays can be accurately controlled again by the processor.

[0031] In addition, the present invention may have various other effects, which will be described in each embodiment configuration, or the description of effects that can be easily inferred by those skilled in the art will be omitted.

[0032] The following drawings attached to this specification illustrate preferred embodiments of the present invention, and together with the detailed description of the invention described below, serve to more effectively understand the technical idea of ​​the present invention, and therefore, the present invention should not be interpreted as being limited to the matters described in these drawings.

[0033] Fig. 1 is a block diagram showing a detailed configuration of a relay control device according to one embodiment of the present invention.

[0034] Fig. 2 is a block diagram showing the detailed configuration of the relay status determination unit illustrated in Fig. 1.

[0035] Fig. 3 is a block diagram showing a detailed configuration according to another embodiment of the relay status determination unit illustrated in Fig. 1.

[0036] Figure 4 is a flowchart illustrating a processing process according to one embodiment of the present invention.

[0037] Figure 5 is a flowchart illustrating a processing process according to another embodiment of the present invention.

[0038] Figure 6 is a flowchart illustrating a processing process according to another embodiment of the present invention.

[0039] Figure 7 is a flowchart illustrating a processing process performed when the processor enters a recovery state.

[0040] FIG. 8 is a diagram illustrating a signal system according to one embodiment of the present invention in each of a normal state and a reset state.

[0041] FIG. 9 is a diagram explaining a signal system according to another embodiment of the present invention according to each of a normal state and a reset state.

[0042] Fig. 10 is a drawing explaining a signal system according to another embodiment of the present invention.

[0043] FIG. 11 is a diagram illustrating a signal system according to one embodiment of the present invention for controlling multiple relays.

[0044] FIG. 12 is a diagram illustrating a signal system according to one embodiment of the present invention according to the recovery state of the processor.

[0045] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. Prior to this, it should be noted that the terms and words used in this specification and claims should not be construed as limited to their conventional or dictionary meanings. Based on the principle that the inventor can appropriately define the concepts of terms to best explain his or her invention, they should be interpreted in a way that conforms to the technical spirit of the present invention.

[0046] Therefore, the embodiments described in this specification and the configurations illustrated in the drawings are only the most preferred embodiments of the present invention and do not represent all of the technical ideas of the present invention. Therefore, it should be understood that there may be various equivalents and modified examples that can replace them at the time of filing this application.

[0047] In addition, when describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description is omitted.

[0048] Throughout the specification, whenever a part is said to "include" a component, this does not mean that it excludes other components, but rather that it may include other components, unless otherwise stated.

[0049] Additionally, terms such as processor described in the specification mean a unit that processes at least one function or operation, which may be implemented by hardware, software, or a combination of hardware and software.

[0050] Additionally, throughout the specification, when a part is said to be "connected" to another part, this includes not only cases where it is "directly connected" but also cases where it is "indirectly connected" with other elements in between.

[0051]

[0052] FIG. 1 is a block diagram showing a detailed configuration of a relay control device (100) according to one embodiment of the present invention, and FIGS. 2 and 3 are block diagrams showing a detailed configuration of a relay status determination unit (130) shown in FIG. 1.

[0053] First, with reference to FIG. 1 and related drawings, etc., the detailed configuration of the relay control device (100) according to the present invention and the processing performed by these configurations will be described in detail, and the relay status determination unit (130) will be described in detail later.

[0054] As illustrated in FIG. 1, the relay control device (100) of the present invention may be configured to include a processor (110), a monitoring unit (120), and a relay status determination unit (130).

[0055] Specifically, the relay status determination unit (130) may be configured to include a flip-flop (131), a buffer unit (132), a gate unit (133), and a second buffer unit (134), as illustrated in FIGS. 2 and 3, depending on the embodiment.

[0056] The relay control device (100) of the present invention is a device that controls the on / off of a relay (200) by organically grafting a signal (hereinafter referred to as a “basic control signal”) originally output by the processor (110) to control the operation of the relay (200) and a signal system based on the monitoring results of the processor (110) to output a signal (hereinafter referred to as a “relay control signal”) that finally controls the relay (200).

[0057] The drawing shows a first relay (210) corresponding to a high side relay, which is a high voltage side relay, and a second relay (220) corresponding to a low side relay, which is a low voltage side relay, but this is only an example and it is obvious that a different number and type of relay (200) may be applied.

[0058] The processor (110) provided in the relay control device (100) is a configuration for executing various control logics performed in the present invention, and may optionally include an ASIC (application-specific integrated circuit), chipset, logic circuit, register, communication modem, data processing device, etc., which are well known in this technical field.

[0059] Additionally, when the control logic is implemented as software, it can be implemented by executing a set of program modules stored in memory, etc., by the processor (110). The memory can be located inside or outside the processor (110) and can be communicatively connected to the processor (110) by various well-known means.

[0060] Before going into a detailed description of the present invention, it is obvious that the relay control device (100) and the relay state determination unit (130) according to the present invention can be implemented through various combinational applications of electronic elements, parts, etc., such as storage means, operation processing means, input / output means, etc. Therefore, each component of the relay control device (100) illustrated in FIG. 1 and the relay state determination unit (130) illustrated in FIG. 2, etc. should be understood as functionally or logically distinct components rather than physically distinct components.

[0061] That is, since each component illustrated in the above drawing corresponds to a logical configuration for effectively explaining the technical idea of ​​the present invention, even if each component is configured integrated or separated, if the function performed by the logical configuration of the present invention can be realized, it should be interpreted as being within the scope of the present invention, and of course, if it is a component that performs the same or similar function, it should be interpreted as being within the scope of the present invention regardless of whether or not the name is consistent.

[0062]

[0063] The relay control device (100) according to the present invention is basically configured to control the on / off of the relay (200) by outputting a relay control signal (RCS), which is a signal that ultimately controls the relay (200), to the relay (200) based on the basic control signal (CS) output by the processor (110) when the operating state of the processor (110) is normal.

[0064] Specifically, when a first basic control signal (CS1) for controlling a first relay (210) and a second basic control signal (CS2) for controlling a second relay (220) are output by the processor (110) (S400, see FIG. 4), a first relay control signal (RCS1) and a second relay control signal (RCS2) based on these signals are output to the first relay (210) and the second relay (220), respectively (S440), thereby controlling the on / off of the first relay (210) and the second relay (220) (S450).

[0065] Since the relay (200) is controlled in an ON / OFF manner rather than in a step-by-step control or linear control, the basic control signal (CS) or / and the relay control signal (RCS) can be configured to have a signal level higher than a preset reference (high level or second signal level) or a signal level lower than the preset reference (low level or first signal level).

[0066] Depending on the embodiment, the basic control signal (CS) or / and relay control signal (RCS) may have a digital signal system through processing such as sampling and quantization.

[0067] In addition, since the input signal can be inverted and output using a simple circuit configuration or gate, a high level (low level) signal can be converted to a low level (high level) signal at any time.

[0068] Therefore, even if a signal of a certain level is mapped to a certain action, it should be interpreted as being self-evident at the level of ordinary skill in the art that the same specific action can be controlled using a signal of the opposite level.

[0069] It goes without saying that these interpretation criteria can be equally applied to various signals used in the present invention, including the signals described below, specifically, the retain signal (RS) output from the monitoring unit (120) of the present invention to maintain the operating state of the relay (200), the decision control signal (DS) having a differential signal level depending on the operating state of the processor (110), and the recovery signal (R) output by the processor (110).

[0070] The monitoring unit (120) of the present invention is configured to monitor the operating state (normal state or reset state, etc.) of the processor (110), and is preferably designed as a configuration independent from the processor (110) in order to fundamentally eliminate dependence on the processor (110).

[0071] The monitoring unit (120) of the present invention monitors the operating state of the processor (110) (S420) and outputs a decision control signal (DS) having a differential signal level according to the operating state of the processor (110) (S430, S435).

[0072] As an example of this, FIG. 4, FIG. 8, etc. illustrate an example of outputting a high-level (second signal level) decision control signal (DS) when the operating state of the processor (110) is normal, and an example of outputting a low-level (first signal level) decision control signal (DS) when the operating state of the processor (110) is reset.

[0073] In addition, the monitoring unit (120) of the present invention is configured to output a retain signal (RS) for maintaining the operating state of the relay (200) independently of the decision control signal (DS) (S410). The retain signal (RS) may have a different signal level depending on the embodiment or the main purpose of control.

[0074] Specifically, in the case of an embodiment in which the relay (200) is turned ON and maintained regardless of the previous (before) state of the relay (200) when the processor (110) is in a reset state, the retain signal (RS) may be configured to continuously have a high level (second signal level) (see FIG. 8).

[0075] Additionally, the retain signal (RS) may be configured to have a low level when the processor (110) is in a normal state and a high level when the processor (110) is in a reset state, depending on the embodiment (see FIG. 9).

[0076] In the case of an embodiment that aims to increase energy efficiency and suppress overcharge / discharge, etc., in order to turn off the relay (200) after a reference time (second reference time), the signal level of the retain signal (RS) is configured to be a high level (second signal level) during the second reference time (see FIGS. 10 and 11) during which the reset state of the processor (110) is maintained, but after the second reference time (t3), the signal level of the retain signal (RS) is configured to be a low level (first signal level).

[0077] In the case of an embodiment in which the state of the relay (200) when the processor (110) is in a normal state (just before the reset state) is maintained even in the reset state, that is, in the case of an embodiment in which the relay (200) is maintained in an ON state when it is ON, and in the case of an embodiment in which the relay (200) is maintained in an OFF state when it is OFF, the monitoring unit (120) of the present invention may be configured to output a retain signal (RS) having a signal level corresponding to the basic control signal (CS) output by the processor (110) when it is in a normal state just before the reset state.

[0078] Meanwhile, the decision control signal (DS) output by the monitoring unit (120) of the present invention and input to the relay status determination unit (130) of the present invention functions as a signal that determines whether or not to output a signal from the relay status determination unit (130).

[0079] The relay status determination unit (130) of the present invention receives a basic control signal (CS) from the processor (110) and the decision control signal (DS) and the retain signal (RS) from the monitoring unit (120). According to an embodiment, the relay status determination unit (130) of the present invention may be configured to receive a recovery signal (R) from the processor (110). This will be described in detail later.

[0080] When three types of signals (basic control signal (CS), retain signal (RS), and decision control signal (DS)) are input to the relay state determination unit (130) of the present invention, the relay state determination unit (130) of the present invention outputs one of the basic control signal (CS) and the retain signal (RS) as the relay control signal (RCS) depending on whether the signal level of the decision control signal (DS) is high or low.

[0081] As described above, the decision control signal (DS) has a differential signal level depending on the operating state (normal state or reset state) of the processor (110), so the decision control signal (DS) represents the operating state of the processor (110) at the current point in time.

[0082] That is, when the operating state of the processor (110) is in a reset state, the monitoring unit (120) of the present invention outputs a decision control signal (DS) having a different signal level from the decision control signal (DS) output when the processor (110) is in a normal state.

[0083] In the following description, in order to make the relative distinction clear, the decision control signal (DS) output when the operating state of the processor (110) is in the reset state is referred to as a 'transition control signal'.

[0084] The relay status determination unit (130) of the present invention outputs the retain signal (RS) among the basic control signal (CS) and the retain signal (RS) as the relay control signal (RCS) when the decision control signal (DS) input from the monitoring unit (120) is a switching control signal (DS), i.e., a signal representing that the operating state of the processor (110) is a reset state (e.g., a signal of low level (first signal level)) (S435).

[0085] In contrast, the relay status determination unit (130) of the present invention outputs the basic control signal (CS) among the basic control signal (CS) and the retain signal (RS) as the relay control signal (RCS) when the switching control signal (DS) is not received from the monitoring unit (120), that is, when the decision control signal (DS) input from the monitoring unit (120) is a signal representing that the operating state of the processor (110) is normal (e.g., a signal of high level (second signal level)) (S430).

[0086] When the relay control signal (RCS) generated by accurately reflecting the operating state of the processor (110) is output to the relay (200), the relay (200) of the present invention is controlled by the input relay control signal (RCS) (S450).

[0087] It goes without saying that the processing of the present invention described above can be applied cyclically if a preset termination condition such as a forced termination, a full system down, or an emergency event occurs is not met (S460).

[0088] When the relay (200) is composed of a first relay (210) and a second relay (220), the relay status determination unit (130) of the present invention outputs a first relay control signal (RCS1) determined as one of a first basic control signal (CS1) and a retain signal (RS) according to the signal level of the decision control signal (DS) to the first relay (210), and outputs a second relay control signal (RCS2) determined as one of a second basic control signal (CS2) and a retain signal (RS) according to the signal level of the decision control signal (DS) from a corresponding viewpoint to the second relay (220).

[0089] Hereinafter, the details of the embodiment of the present invention described above will be supplementarily described with reference to FIG. 8. FIG. 8 is a diagram explaining a signal system according to one embodiment of the present invention in each of a normal state and a reset state.

[0090] t1 in Fig. 8 illustrates the point in time when the processor (110) (MCU, etc.) enters a reset state due to a system error, etc., and t2 illustrates the point in time when the processor (110) is restored to a normal state after the reset state.

[0091] As illustrated in Fig. 8, when the processor (110) is in the initial normal state (S420), the decision control signal (DS) output from the monitoring unit (120) of the present invention (S430) is a high level (second signal level), so the relay state determination unit (130) of the present invention outputs the basic control signal (CS) among the basic control signal (CS) input from the processor (110) (S400) and the retain signal (RS) input from the monitoring unit (120) (S410) as a relay control signal (RCS) based on the decision control signal (DS) (S440).

[0092] Therefore, the relay control signal (RCS) that finally controls the relay (200) until the initial normal state ~t1 of the processor (110) is based on the basic control signal (CS).

[0093] When the processor (110) is reset at time t1 (S420), the monitoring unit (120) outputs a decision control signal (DS) that has a differential signal level (e.g., low level (first signal level)) from the decision control signal (DS) in the normal state, i.e., a transition control signal (DS) (S435).

[0094] When a transition control signal (DS), which is a decision control signal (DS) having a differential level compared to the decision control signal (DS) output when the processor (110) is in a normal state, is input to the relay state determination unit (130) (S435), the relay state determination unit (130) of the present invention outputs the retain signal (RS) input from the monitoring unit (120) as a relay control signal (RCS) (S445).

[0095] Therefore, the relay control signal (RCS) output from the relay status determination unit (130) in the [t1, t2] section is based on the retain signal (RS).

[0096] When the processor (110) is restored to a normal state at time t2, the monitoring unit (120) of the present invention outputs a decision control signal (DS) (e.g., high level) representing this, and when this signal is received, the relay state determination unit (130) of the present invention outputs the basic control signal (CS) among the basic control signal (CS) and the retain signal (RS) as a relay control signal (RCS).

[0097] Therefore, after the time point t2 when the normal state is restored, the relay control signal (RCS) of the present invention becomes based on the basic control signal (CS) again.

[0098] The embodiment illustrated in FIG. 8 corresponds to an embodiment in which the monitoring unit (120) of the present invention is set to output a retain signal (RS) having a high level regardless of the operating state of the processor (110).

[0099] As previously explained, the relay control signal (RCS) is selectively determined as one of the basic control signal (CS) and the retain signal (RS) based on the decision control signal (DS). Therefore, even if the retain signal (RS) is set to maintain a high level regardless of the operating state of the processor (110), the retain signal (RS) is reflected as the relay control signal (RCS) only when the processor (110) is switched to the reset state, thereby maintaining the relay (200) in the on state.

[0100] According to this embodiment of the present invention, the signal level of the retain signal (RS) is maintained at a constant signal level without being linked to the operating state of the processor (110), so there is an advantage in that the circuit design can be implemented simply.

[0101]

[0102] FIG. 5 is a flowchart illustrating a processing process according to another embodiment of the present invention, and FIG. 9 is a drawing illustrating an example of a signal system according to this embodiment.

[0103] The embodiment of the present invention illustrated in FIG. 5 differs from the embodiment described above with reference to FIG. 4, etc., in that the monitoring unit (120) is configured to output a high-level retain signal (RS) only when the processor (110) is monitored to be in a reset state.

[0104] When the processor (110) is in a normal state (S510), as described above, the monitoring unit (120) of the present invention outputs a high-level decision control signal (DS) (S530), and the relay status determination unit (130) of the present invention outputs the basic control signal (CS) input from the processor (110) (S500) as a relay control signal (RCS) (S540). The relay (200) is turned on and off by the relay control signal (RCS) output in this manner (S550).

[0105] On the other hand, when the processor (110) is in a reset state (S510), the monitoring unit (120) of the present invention outputs a retain signal (RS) of a high level (second signal level) (S520), and independently of this, the monitoring unit (120) of the present invention outputs a decision control signal (DS) of a low level (first signal level) (S520).

[0106] In this way, when a low-level decision control signal (DS) is input to the relay state determination unit (130), the relay state determination unit (130) outputs the retain signal (RS) among the basic control signal (CS) and the retain signal (RS) as a relay control signal (RCS) (S545), and the relay (200) is controlled by this relay control signal (RCS) (S550).

[0107] In this embodiment, as shown in the lower part of Fig. 9, in the initial normal state (~t1), the relay control signal (RCS) is output based on the basic control signal (CS), and in the t1~t2 section, the relay control signal (RCS) is output based on the retain signal (RS).

[0108] When the processor (110) is restored to a normal state at time t2, the monitoring unit (120) of the present invention outputs a decision control signal (DS) (e.g., high level) representing this, and when this signal is received, the relay state determination unit (130) of the present invention outputs the basic control signal (CS) among the basic control signal (CS) and the retain signal (RS) as a relay control signal (RCS).

[0109] Therefore, after the time point t2 when the normal state is restored, the relay control signal (RCS) of the present invention becomes based on the basic control signal (CS) again. As illustrated in Fig. 9, in the case of this embodiment, when the processor (110) is restored to the normal state (t2), the retain signal (RS) can be switched to a low level.

[0110] Meanwhile, as described above, the retain signal (RS) of the present invention can be set to have a signal level corresponding to the basic control signal (CS) output by the processor (110) in a normal state immediately before the reset state when the operating state of the processor (110) is a reset state.

[0111] According to this implementation configuration, when the relay (200) is open (open, OFF) immediately before the reset state (normal state), the relay (200) can be controlled to remain open even in the reset state, and when the relay (200) is closed (closed, ON) immediately before the reset state (normal state), the relay (200) can be controlled to remain closed even in the reset state, so that the state of the relay (200) can be maintained identical to the normal state immediately before the reset state, thereby having the advantage of maintaining operational consistency.

[0112]

[0113] Fig. 6 is a flowchart illustrating a processing process according to another embodiment of the present invention. Figs. 10 and 11 are supplementary drawings illustrating a signal system according to the embodiment illustrated in Fig. 6.

[0114] The processing illustrated in FIG. 6 is based on the assumption that the processor (110) is in a reset state and a switching control signal (DS), i.e., a decision control signal (DS) indicating that the processor (110) is in a reset state, is output by the monitoring unit (120).

[0115] When a high-level retain signal (RS) is generated by the monitoring unit (120) (S600), this retain signal (RS) is output to the relay status determination unit (130) (S610). The relay status determination unit (130) outputs a relay control signal (RCS) determined as the retain signal (RS) (S620) to the relay (200) based on the switching control signal (DS) (S630).

[0116] Through this processing, the relay (200) of the present invention is controlled to an on state (S640).

[0117] If the processor (110) is not restored to normal state after time t1, the decision control signal (DS) continues to maintain a low level (first signal level), and thus the signal switching of the relay control signal (RCS) does not occur. That is, after time t1, the relay control signal (RCS) is output based on the retain signal (RS) having a high level, and as a result, the relay (200) remains in an on state.

[0118] As illustrated in FIG. 10, the monitoring unit (120) of the present invention outputs the retain signal (RS) at a second signal level (high level) during the second reference time (β) when the reset state continues for a second reference time (β) based on the time point (t1) when the processor (110) is in a reset state (S650, S600), but after the second reference time (after t3), the signal level of the retain signal (RS) becomes a first signal level (low level) (S660).

[0119] In this way, when the retain signal (RS) that has been switched to a low level after the second reference time (△t) has elapsed based on t1 is output to the relay status determination unit (130) (S670), the relay status determination unit (130) outputs this retain signal (RS) as a relay control signal (RCS) (S680, S685).

[0120] In this way, the relay control signal (RCS) based on the low level is output to the relay (200), and the relay (200) is controlled to be OFF (S690).

[0121] According to the embodiment of the present invention, if the processor (110) is not restored to a normal state even after a reference time has elapsed, the relay (200) can be turned off, thereby preventing unnecessary energy waste. In addition, the fact that the processor (110) is not restored to a normal state for a medium to long term period of time may indicate the possibility that an actual fatal error or defect has occurred, and thus, safety accidents, etc. related thereto can be prevented in advance by the embodiment of the present invention.

[0122] FIG. 11 is a drawing showing an example of a signal system generated or output when the relay (200) to be controlled is the first relay (210) and the second relay (220), and is substantially the same as the signal system shown in FIG. 10.

[0123] Part D indicated in Fig. 11 refers to a signal delay that occurs during the process in which the processor (110) transitions from a normal state to a reset state. This part is omitted in Figs. 8 to 10.

[0124] The first and second output signals (Q1, Q2) illustrated in Fig. 11 are signal values ​​output in conjunction with the signal transition of the decision control signal (DS) described above, and correspond to signals output from the flip-flop (131) when the relay state determination unit (130) of the present invention is configured to include a flip-flop (131) as illustrated in Figs. 2 and 3. A description thereof will be provided later.

[0125] Meanwhile, the monitoring unit (120) of the present invention may be configured to output the switching control signal using the results of at least one of software monitoring that determines the current state of the processor (110) using feedback information for a request and hardware monitoring that uses whether a trigger signal is received.

[0126] As described above, the monitoring unit (120) of the present invention is configured to output a transition control signal (DS), which is a decision control signal (DS) representing a state in which the operating state of the processor (110) is not a normal state, i.e., a reset state.

[0127] This switching control signal (DS) corresponds to an important parameter signal that determines the signal to be determined as the relay control signal (RCS) in the relay status determination unit (130) as described above.

[0128] Therefore, in order to more precisely implement monitoring of the operating state of the processor (110), the monitoring unit (120) of the present invention is preferably configured to output the switching control signal (DS) only when both the software monitoring (S / W) that determines the current operating state of the processor (110) and the hardware monitoring (H / W) that utilizes whether a trigger signal is received fail.

[0129] Software monitoring can be applied by sending requests (questions, etc.) for a certain period of time through a WDT (Window Watchdog) and checking whether corresponding feedback (answers, etc.) is received, and hardware monitoring can be applied by allocating one or more lines or channels and checking whether a specific signal is normally triggered.

[0130]

[0131] Hereinafter, an embodiment of the present invention in which a relay (200) is controlled by a recovery signal (R) output by a processor (110) will be described with reference to FIG. 7 and FIG. 12, etc.

[0132] When the processor (110) is in a reset state, the operating state of the relay (200) is controlled to be maintained by the unique processing of the present invention using a signal system such as a retain signal (RS) and a decision control signal (DS) as described above (S700).

[0133] The processor (110) of the present invention can be configured to output a recovery signal (R) independently from outputting a basic control signal (CS) for controlling the operation of the relay (200).

[0134] The above recovery signal (R) is a signal representing that the processor (110) is in a recovery state, and refers to a signal or signal system indicating that the processor (110) itself is in a state of escaping from a reset state (reboot state, etc.) and entering a normal state (hereinafter referred to as a 'recovery state').

[0135] As illustrated in FIG. 12, when the processor (110) is in a state other than a recovery state, the recovery signal (R) may be configured to have a signal level of a second signal level (high level), and when the processor (110) is in a recovery state, the recovery signal (R) may be configured to have a signal level of a first signal level (low level).

[0136] Hereinafter, the recovery signal (R) output when the processor (110) is in a recovery state is referred to as a 'switch recovery signal', and the recovery signal (R) output when the processor (110) is in a state other than a recovery state is referred to as a 'non-switch recovery signal'.

[0137] The embodiment illustrated in Fig. 12 is an embodiment in which the switching recovery signal (R) is set to the first signal level (low level) and the non-switching recovery signal (R) is set to the second signal level (high level).

[0138] The processor (110) of the present invention can immediately output a recovery signal (R) (transition recovery signal (R)) to the relay state determination unit (130) when its operating state changes from a reset state to a recovery state.

[0139] In this case, the decision control signal (DS) output by the monitoring unit (120) may be set differently depending on the embodiment. For example, when the processor (110) enters a recovery state, i.e., when a transition recovery signal (R) is output, the signal level of the decision control signal (DS) output by the monitoring unit (120) may be configured to transition from a low level to a high level.

[0140] As another example, even if a transition recovery signal (R) is output by the processor (110) (t2), the signal level of the decision control signal (DS) may not be immediately transitioned, and after the first reference time (β) has elapsed, when the signal level of the recovery signal (R) transitions again (from the first signal level to the second signal level) (t2`=t2+β), the signal level of the decision control signal (DS) may be configured to transition accordingly. FIG. 12 illustrates a signal system for the latter embodiment.

[0141] That is, the processor (110) of the present invention can be configured to output a recovery signal whose signal level has transitioned to the relay state determination unit (130) when a first reference time (β) has elapsed after the switching recovery signal (R) is output so that a switching or transition of another related signal system can occur.

[0142] In the latter embodiment, when a recovery signal (R) (transition recovery signal) of low level (first signal level) is input to the relay state determination unit (130) of the present invention, and then a recovery signal (R) of high level (second signal level) is input (S710), the relay state determination unit (130) of the present invention is configured to output the basic control signal (CS) among the basic control signal (CS) and the retain signal (RS) as the relay control signal (RCS) (S740).

[0143] When a relay control signal (RCS) is output by this method, the relay (200) of the present invention is turned on and off by the relay control signal (RCS) (S750).

[0144] After that, if the processor (110) is not reset (S770), the on / off of the relay (200) is controlled in a cyclic manner, such as steps 740 and 750 of FIG. 7, and if the processor (110) is reset again (S770), control processing according to the reset state of the processor (110) is performed (S700) through the configuration and method described above.

[0145] Meanwhile, if the recovery signal (R) of the low level (first signal level), that is, the transition recovery signal (R), is not input or if the recovery signal (R) whose signal level has transitioned after the transition recovery signal (R) is input, that is, the non-transition recovery signal (R), is not input (S710), it is considered that the restoration to a complete normal state has not yet been completed, and the relay state determination unit (130) of the present invention outputs the retain signal (RS) among the basic control signal (CS) and the retain signal (RS) as a relay control signal (RCS) (S720), and the relay (200) can be configured to be controlled by this relay control signal (RCS) (S730).

[0146] Therefore, as shown in the lower part of Fig. 12, the relay control signal (RCS) that ultimately controls the relay (200) is generated based on the basic control signal (CS) in the initial normal state (~t1), is generated based on the retain signal (RS) in the reset state and restoration state (t1~t2`), and is generated based on the basic control signal (CS) again from the time point (t2`~) when the normal state is restored again.

[0147] In this case, when the processor (110) is configured to output a recovery signal (R), the relay status determination unit (130) of the present invention may be configured to output one of the basic control signal (CS) and the retain signal (RS) as a relay control signal (RCS) that controls the on / off of the relay (200) based on the signal level of the decision control signal (DS) or the recovery signal (R) described above.

[0148] According to one embodiment of the present invention, a relay control device (100) can control the operating state of a relay (200) based on a decision control signal (DS) output from a monitoring unit (120) when the processor (110) is reset one or more times.

[0149] Thereafter, when the operating state of the processor (110) is switched to a recovery state, the signal levels of the basic control signal (CS), the first output signal (Q1), the second output signal (Q2), etc. are restored to the original signal levels based on the recovery signal (R) output by the processor (110), thereby allowing the operating state of the relay (200) to be controlled by the processor (110).

[0150]

[0151] Hereinafter, with reference to FIGS. 2 and 3, a specific embodiment of a relay status determination unit (130), which is a component of a relay control device (100) according to the present invention, will be described.

[0152] As shown in FIGS. 2 and 3, the relay status determination unit (130) of the present invention can be configured to include a flip-flop (131), a buffer unit (132), a gate unit (133), and a second buffer unit (134).

[0153] A flip-flop (131) is a logic circuit that can store and maintain 1 bit of information. Depending on the embodiment, the flip-flop (131) illustrated in FIG. 3 can be implemented as a D flip-flop, an RS flip-flop, a JK flip-flop, or a T flip-flop.

[0154] A flip-flop (131) may have a clock terminal (C) to which an output signal of a second buffer unit (134) in which a decision control signal (DS) and a recovery signal (R) are signal-processed is input, and a data terminal (D) to which a second basic control signal (CS2) is input, as input terminals, and may include a first output terminal (Q) and a second output terminal (Q`).

[0155] The first output signal (Q1) output from the first output terminal (Q) is determined according to the signal level of the second basic control signal (CS2) and the decision control signal (DS) or recovery signal (R), which are signals input to the flip-flop (131), and the second output signal (Q2) output from the second output terminal (Q`) can be designed to have a signal level opposite to that of the first output signal (Q1) (first signal level vs. second signal level).

[0156] As a specific example, when the decision control signal (DS) is converted from a high level to a low level or the recovery signal (R) is converted from a low level to a high level through the internal design of the flip-flop (131), the first output signal (Q1) can be configured to be converted from a low level to a high level in conjunction therewith. In this case, the second output signal (Q2) is designed to have an opposite level to the first output signal (Q1), so the second output signal (Q2) becomes a low-level signal.

[0157] The buffer unit (132) receives the first and second basic control signals (CS1, CS2) from the processor (110), the first and second output signals (Q1, Q2) from the flip-flop (131), and the retain signal (RS) from the monitoring unit (120).

[0158] The buffer unit (132) is configured to output the first and second relay control signals (RCS1, RCS1), which are signals that ultimately control the on / off of the first and second relays (210, 220), to the first and second relays (210, 220) through a circuit architecture that implements the technical idea of ​​the present invention described above.

[0159] More specifically, the buffer unit (132) may include a plurality of buffers. One of them, the first buffer, may be configured to receive a retain signal (RS) and a first output signal (Q1) and determine whether to output the retain signal (RS) based on the signal level of the first output signal (Q1).

[0160] For example, when the signal level of the first output signal (Q1) is the second signal level (high level), the retain signal (RS) can be output through the first buffer, and when the signal level of the first output signal (Q1) is the first signal level (low level), the retain signal (RS) can be designed not to be output.

[0161] Among the multiple buffers, the second buffer may be designed to receive the first basic control signal (CS1) and the second output signal (Q2), and determine whether to output the first basic control signal (CS1) based on the signal level of the second output signal (Q2).

[0162] For example, when the signal level of the second output signal (Q2) is the second signal level (high level), the first basic control signal (CS1) can be output through the second buffer, and when the signal level of the second output signal (Q2) is the first signal level (low level), the first basic control signal (CS1) can be designed not to be output.

[0163] In addition, the output channel (line) of the first buffer and the output channel (line) of the second buffer can be configured to be integrated with each other. In this case, since the first buffer and the second buffer receive the first output signal (Q1) and the second output signal (Q2) having opposite signal levels as described above, when the retain signal (RS) is output from the first buffer, the first basic control signal (CS1) can be prevented from being output from the second buffer.

[0164] As explained above, the fact that the retain signal (RS) is output from the first buffer means that the signal level of the first output signal (Q1) input to the first buffer is the second signal level (high level), and the second output signal (Q2) input to the second buffer is a low-level signal that is the opposite level of the first output signal (Q1). In this way, by inputting the low-level second output signal (Q2) to the second buffer, the first basic control signal (CS1) is configured not to be output from the second buffer.

[0165] Accordingly, depending on the signal levels of the first and second output signals (Q1, Q1), one of the first basic control signal (CS1) and the retain signal (RS) can be output as the first relay control signal (RCS1) through the buffer unit (132). As described above, the first and second output signals (Q1, Q2) are based on whether the signal transition of the decision control signal (DS) or the recovery signal (R) output by the monitoring unit (120) occurs, and the decision control signal (DS) and the recovery signal (R) are based on the operating state of the processor (110).

[0166] Therefore, the relay control device (100) according to the present invention monitors the operating state of the processor (110), outputs a decision control signal (DS) according to the monitoring result, outputs a first or / and second output signal (Q1, Q2), determines one of the first basic control signal (CS1) and the retain signal (RS), and ultimately controls the on / off of the first relay (210) through processing in which the determined signal is output as the first relay control signal (RCS1).

[0167] In addition, in the case of an embodiment using a recovery signal (R) for the recovery state of the processor (110), the on / off of the first relay (210) is finally controlled through processing such as the recovery state of the processor (110), output of the transition recovery signal (R), signal level transition, output of the first or / and second output signal (Q1, Q2), signal determination of one of the first basic control signal (CS1) and the retain signal (RS), and output of the determined signal as the first relay control signal (RCS1).

[0168] In this way, the relay control device (100) according to the present invention can accurately reflect the operating state of the processor (110) and output the first relay control signal (RCS1) controlling the first relay (210) as a different dual signal system according to the operating state.

[0169] The second relay control signal (RCS2) that ultimately controls the second relay (220) can also be output in a manner in which one of the second basic control signal (CS2) or the retain signal (RS) is selected through a plurality of buffers (e.g., the third buffer, the fourth buffer, etc.) that implement the technical configuration described above. Since the third and fourth buffers correspond to the first and second buffers described above, a detailed description thereof will be omitted.

[0170] The second buffer unit (134) of the present invention is configured to process a recovery signal (R) output from a processor (110) and a decision control signal (DS) output from a monitoring unit (120), and can be implemented through a combinational configuration of one or more lower buffers and / or inverters (NOT gates) that implement signal delay, signal passing, signal suppression, signal inversion, etc.

[0171] This second buffer section (134) is configured to output a decision control signal (DS) or a recovery signal (R) to the clock terminal (C) of the flip-flop (131) when the decision control signal (DS) or the recovery signal (R) is input as described above, and can perform functions such as outputting a specific signal according to the signal level of the decision control signal (DS) and the recovery signal (R) (transition recovery signal) as illustrated in FIG. 12.

[0172] Through the configuration of the present invention, when the operating state of the processor (110) is switched to a recovery state, the signal levels of the basic control signal (CS), the first output signal (Q1), the second output signal (Q2), etc. are restored to the original signal levels based on the recovery signal (R) output by the processor (110), thereby allowing the operating state of the relay (200) to be controlled by the processor (110).

[0173]

[0174] According to an embodiment, the relay status determination unit (130) of the present invention may further include a gate unit (133) that mediates between at least one of the first relay (210) and the second relay (220) and the buffer unit (132), as illustrated in FIG. 3. As an example of this, FIG. 3 illustrates an example in which a gate unit (133) is provided between the buffer unit (132) and the second relay (220).

[0175] The gate unit (133) may be designed to receive a third relay control signal (RCS3) from the buffer unit (132), receive a retain signal (RS) from the monitoring unit (120), and output a second relay control signal (RCS2) to the second relay (300) based on the signal levels of the third relay control signal (RCS3) and the retain signal (RS).

[0176] As in the previous embodiment, when the operating state of the processor (110) is a reset state, the retain signal (RS) can be output from the fourth buffer of the buffer unit (132), so the third relay control signal (RCS3) can be the retain signal (RS) output from the fourth buffer.

[0177] Therefore, since the gate unit (133) receives the retain signal (RS) output from each of the buffer unit (132) and the monitoring unit (120), if the gate unit (133) is implemented as an AND gate, it is configured to output a high-level signal only when both received signals are high-level, thereby further improving the accuracy of the signal system.

[0178]

[0179] The relay control device (100) according to the present invention can be applied to a BMS (Battery Management System). That is, the BMS according to the present invention can include the relay control device (100) described above. In this configuration, at least some of the components of the relay control device (100) can be implemented by supplementing or adding functions of the components included in a conventional BMS. For example, the processor (110), monitoring unit (120), and relay status determination unit (130) of the relay control device (100) can be implemented as components of the BMS.

[0180] In addition, the relay control device (100) according to the present invention may be provided in a battery pack. That is, the battery pack according to the present invention may include the relay control device (100) described above and one or more battery cells. In addition, the battery pack may further include electrical components (relays, fuses, etc.) and a case, etc.

[0181] Furthermore, the relay control device (100) according to the present invention can be installed in a vehicle. Accordingly, the relay control device (100) can control the relay so that the relay connecting the battery and the vehicle remains closed, not open, even when the processor (110) is reset due to a systematic error while the vehicle is driving.

[0182]

[0183] Although the present invention has been described above with reference to limited embodiments and drawings, the present invention is not limited thereto, and it is obvious that various modifications and variations are possible within the scope of the technical idea of ​​the present invention and the equivalent scope of the patent claims to be described below by a person having ordinary skill in the art to which the present invention pertains.

[0184] The drawings attached for the purpose of explaining the present invention and illustrating embodiments thereof may be illustrated in a somewhat exaggerated form to emphasize or highlight the technical contents of the present invention. However, it should be interpreted that it is obvious that various modified application examples may be possible at the level of a person skilled in the art in consideration of the contents described above and matters illustrated in the drawings.

[0185] In addition, it is self-evident that expressions such as first, second, upper, lower, or top and bottom in the description of the present invention are merely instrumental conceptual terms used to relatively distinguish each component (element) from each other, and are not terms used to indicate a specific order, priority, etc., or terms used to physically distinguish each component (element) on an absolute basis.

[0186] (Explanation of symbols)

[0187] 100: Relay control device

[0188] 110: Processor

[0189] 120: Monitoring Department

[0190] 130: Relay status determination unit

[0191] 131: Flip-flop

[0192] 132: Buffer section

[0193] 133: Gate section

[0194] 134: Second buffer section

[0195] 200: Relay

[0196] 210: 1st Relay

[0197] 220: 2nd Relay

[0198] CS: Basic control signal

[0199] CS1(2): First (2) basic control signal

[0200] DS: Decision control signal

[0201] RS: Retain signal

[0202] RCS: Relay Control Signal

[0203] RCS1(2): 1st (2nd) relay control signal

[0204] R: Recovery signal

[0205] Q1(2): First (2) output signal

Claims

1. A processor configured to output a basic control signal for controlling the operation of a relay and a recovery signal having a differential signal level depending on whether the processor is in a recovery state; A monitoring unit configured to monitor the operating status of the processor and output a decision control signal having a differential signal level according to the operating status of the processor and a retain signal for maintaining the operating status of the relay; and A relay control device characterized by including a relay state determination unit configured to output one of the basic control signal and the retain signal as a relay control signal that controls the on / off of the relay based on the signal level of the decision control signal or the recovery signal.

2. In paragraph 1, The above monitoring unit, A relay control device characterized in that, when the operating state of the processor is a reset state, a switching control signal, which is a decision control signal having a different signal level from the decision control signal output when the processor is in a normal state, is output to the relay state determination unit.

3. In paragraph 1, The above processor, A relay control device characterized in that, when its own operating state is a recovery state in which it transitions from a reset state to a normal state, it outputs a transition recovery signal, which is a recovery signal having a different signal level from the recovery signal output in a state other than the recovery state, to the relay state determination unit.

4. In paragraph 3, The above processor, A relay control device characterized in that it is configured to output the recovery signal, the signal level of which has transitioned, to the relay status determination unit when the first reference time has elapsed after the above-mentioned transition recovery signal is output.

5. In paragraph 2, The above monitoring unit, A relay control device characterized in that it is configured to output the switching control signal only when both software monitoring using feedback information for a request and hardware monitoring using receipt of a trigger signal fail.

6. In paragraph 3, The above relay status determination unit is, A relay control device characterized in that, when the above-mentioned switching recovery signal is received, the basic control signal is output as the relay control signal.

7. In paragraph 2, The above relay status determination unit is, A relay control device characterized in that it is configured to output the basic control signal as the relay control signal when the above-mentioned switching control signal is not received, and to output the retain signal as the relay control signal when the above-mentioned switching control signal is received.

8. In paragraph 1, The above monitoring unit, A relay control device characterized in that, when the operating state of the processor is a reset state, it is configured to output the retain signal having a signal level corresponding to the basic control signal output by the processor in a normal state immediately before the reset state.

9. In paragraph 1, The above monitoring unit, A relay control device characterized in that, when the reset state of the processor continues for a second reference time, the retain signal is output at a second signal level, but after the second reference time, the retain signal is output at a first signal level.

10. A battery pack comprising a relay control device according to any one of claims 1 to 9.

11. A vehicle including a relay control device according to any one of paragraphs 1 to 9.

12. A basic signal receiving step for receiving a basic control signal for controlling the operation of the relay and a recovery signal having a differential signal level depending on whether the processor is in a recovery state; A control signal receiving step for receiving a decision control signal having a differential signal level according to the operating state of the processor and a retain signal for maintaining the operating state of the relay; and A relay control method characterized by including a control signal output step for outputting one of the basic control signal and the retain signal as a relay control signal for controlling on / off of the relay based on the signal level of the decision control signal or the recovery signal.

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