Atomic-operation processing method and apparatus, and electronic device and storage medium

Abstract

The present disclosure relates to an atomic-operation processing method and apparatus, and an electronic device and a storage medium. The method comprises: in response to at least three threads performing atomic operations of the same target type on the same target element in a memory, wherein the atomic operations of the target type conform to associative laws, in a first processing stage, grouping an original value of the target element and at least three numerical values corresponding to the at least three threads, and performing the atomic operations of the target type on the groups in parallel so as to obtain input values for a second processing stage; and according to the input values for the second processing stage, obtaining final atomic operation results corresponding to the at least three threads.

Description

Atomic operation processing method, device, electronic device and storage medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure is based on and claims the priority of Chinese patent application with application number 202310827118.0 and application date July 6, 2023. The entire contents of the Chinese patent application are hereby introduced into this disclosure in their entirety. Technical Field

[0003] The present disclosure relates to the field of computer technology, and in particular to an atomic operation processing method, device, electronic device, and storage medium. Background Art

[0004] A GPU (Graphics Processing Unit) can support thousands of threads running in parallel, and these threads may need to access certain data structures in parallel. In many scenarios, each thread may want to monopolize this data and perform a series of operations before other threads access the same data, which can be achieved through atomic operations. A data structure can have many elements, each residing at different memory addresses. If a group of threads happen to access different elements in the data structure, that is, the destination addresses of the atomic operations from different threads are different, then the atomic operations from different threads can be executed in parallel.

[0005] However, if the atomic operations of a group of threads target the same memory address, then in order to correctly execute the atomic operations of each thread, the atomic operations of each thread must be performed sequentially. That is, the atomic operation of the first thread must be completed before the atomic operation of the second thread can be started, and the atomic operation of the second thread must be completed before the atomic operation of the third thread can be started, and so on. This results in low system throughput and slow program execution.

[0006] Summary of the Invention

[0007] The embodiments of the present disclosure provide a technical solution for processing atomic operations.

[0008] According to one aspect of an embodiment of the present disclosure, a method for processing atomic operations is provided, including: in response to at least three threads performing atomic operations of the same target type on the same target element in memory, and the atomic operations of the target type conform to the associative law, in a first processing stage, the original value of the target element and at least three numerical values ​​corresponding to the at least three threads are grouped, and the atomic operations of the target type are performed on each group in parallel to obtain input values ​​for a second processing stage; based on the input values ​​of the second processing stage, final atomic operation results corresponding to the at least three threads are obtained.

[0009] In one possible implementation, the obtaining of the final atomic operation results corresponding to the at least three threads based on the input values ​​of the second processing stage includes: in response to the number of input values ​​of the i-th processing stage being greater than or equal to 3, grouping the input values ​​of the i-th processing stage, and performing the atomic operation of the target type on each group in parallel to obtain the input value of the i+1-th processing stage, where i is an integer greater than or equal to 2; in response to the number of input values ​​of the i-th processing stage being 2, performing the atomic operation of the target type on the 2 input values ​​of the i-th processing stage to obtain the final atomic operation results corresponding to the at least three threads, where i is an integer greater than or equal to 2.

[0010] In one possible implementation, in response to the number of input values ​​of any processing stage being greater than or equal to 3 and the number of input values ​​of the processing stage being an even number, the input values ​​of the processing stage are grouped in pairs; or, in response to the number of input values ​​of any processing stage being greater than or equal to 3 and the number of input values ​​of the processing stage being an odd number, one of the input values ​​of the processing stage is used as the input value of the next processing stage of the processing stage, and the other input values ​​of the processing stage are grouped in pairs.

[0011] In a possible implementation, the atomic operation of the target type is any one of the following operations: an atomic addition operation, an atomic replacement operation, an atomic AND operation, an atomic OR operation, and an atomic XOR operation.

[0012] In one possible implementation, in response to at least three threads performing atomic operations of the same target type on the same target element in the memory, and the atomic operations of the target type conform to the associative law, in the first processing stage, before grouping the original value of the target element and the at least three numerical values ​​corresponding to the at least three threads, the method further includes: in response to at least three threads performing atomic subtraction operations on the same target element in the memory, respectively inverting the at least three numerical values ​​corresponding to the at least three threads, and converting the atomic subtraction operation into an atomic addition operation.

[0013] In a possible implementation, in the first processing stage, the original value of the target element and the at least three values ​​corresponding to the at least three threads are grouped, and the atomic operation of the target type is performed on each group in parallel to obtain the input value of the second processing stage, including: in the first processing stage, the original value of the target element and the at least three values ​​corresponding to the at least three threads are divided into groups, and through The computing units parallelize the The atomic operation of the target type is performed on the groups to obtain the input value of the second processing stage, where T represents the number of threads that perform the atomic operation of the same target type on the same target element in the memory. Indicates rounding down.

[0014] In a possible implementation, obtaining the final atomic operation results corresponding to the at least three threads according to the input values ​​of the second processing stage includes: in response to the number of input values ​​of the i-th processing stage being greater than or equal to 3, dividing the input values ​​of the i-th processing stage into groups, and through The computing units parallelize the groups to perform atomic operations of the target type to obtain input values ​​of the i+1th processing stage, where i is an integer greater than or equal to 2, and N represents the number of input values ​​of the i-th processing stage; in response to the number of input values ​​of the i-th processing stage being 2, performing atomic operations of the target type on the two input values ​​of the i-th processing stage through a computing unit to obtain final atomic operation results corresponding to the at least three threads, where i is an integer greater than or equal to 2.

[0015] In one possible implementation, T threads are processed by a computing architecture including T computing units, wherein any one of the T computing units includes two input terminals and one output terminal, and the T computing units correspond to different threads among the T threads; the two input terminals of a computing unit in the first processing stage respectively input the original value of a memory element corresponding to the computing unit and the numerical value corresponding to the thread corresponding to the computing unit, wherein the original value of the memory element corresponding to the computing unit represents the memory element on which the thread corresponding to the computing unit performs an atomic operation; for any other computing unit in the first processing stage, one input terminal of the computing unit inputs the numerical value corresponding to the thread corresponding to the computing unit, and the other input terminal is connected to a selection unit corresponding to the computing unit, and the selection unit is used to select one item from the original value of the memory element corresponding to the computing unit and the input factor corresponding to the computing unit, wherein the input factor corresponding to any computing unit is the numerical value corresponding to the thread corresponding to any computing unit other than the computing unit in the first processing stage, and the input factors corresponding to different computing units are different.

[0016] In a possible implementation, the output end of a computing unit in a non-last processing stage is connected to the input end of a selection unit corresponding to a computing unit in a subsequent processing stage, the output end of each computing unit in a non-last processing stage is respectively connected to the input end of only a single selection unit, and the output ends of different computing units are connected to different selection units; for any computing unit in the i-th processing stage, when a numerical value corresponding to a thread corresponding to the computing unit is input into one input end of the computing unit, the other input end of the computing unit is connected to the selection unit corresponding to the computing unit, and the selection unit is used to select one item from the memory element corresponding to the computing unit and the output of the computing unit in the previous processing stage; wherein, in non-first Among the computing units in the processing stages, there is at most one computing unit whose one input end inputs the numerical value corresponding to the thread corresponding to the computing unit, and the other input end of the computing unit and the two input ends of the other computing units are all connected to the selection unit; for any computing unit in the i-th processing stage, when both input ends of the computing unit are connected to the selection unit, one selection unit corresponding to the computing unit is used to select one item from the numerical value corresponding to the thread corresponding to the computing unit and the output of the computing unit in the previous processing stage, and the other selection unit corresponding to the computing unit is used to select one item from the memory element corresponding to the computing unit and the output of the computing unit in the previous processing stage, where i is an integer greater than or equal to 2.

[0017] In one possible implementation, when the T threads perform atomic operations of the same target type on the same target element in the memory, the selection unit of the first processing stage is used to select the input factor corresponding to the computing unit, and each selection unit other than the first processing stage is used to select the output of the computing unit of the previous processing stage; when the T threads perform atomic operations on different elements in the memory, the selection unit of the first processing stage is used to select the memory element corresponding to the computing unit; for any computing unit of the i-th processing stage, when the computing unit has only one input end connected to the selection unit, the selection unit corresponding to the computing unit is used to select the memory element corresponding to the computing unit; for any computing unit of the i-th processing stage, when both input ends of the computing unit are connected to the selection unit, one selection unit corresponding to the computing unit is used to select the numerical value corresponding to the thread corresponding to the computing unit, and the other selection unit corresponding to the computing unit is used to select the memory element corresponding to the computing unit.

[0018] According to one aspect of an embodiment of the present disclosure, a processing device for atomic operations is provided, including: a first processing module, configured to perform atomic operations of the same target type on the same target element in memory in response to at least three threads, and the atomic operations of the target type conform to the associative law. In a first processing stage, the original value of the target element and at least three numerical values ​​corresponding to the at least three threads are grouped, and the atomic operations of the target type are performed on each group in parallel to obtain input values ​​for a second processing stage; a second processing module, configured to obtain final atomic operation results corresponding to the at least three threads based on the input values ​​of the second processing stage.

[0019] In one possible implementation, the second processing module is configured as follows: in response to the number of input values ​​of the i-th processing stage being greater than or equal to 3, grouping the input values ​​of the i-th processing stage, and performing the atomic operation of the target type on each group in parallel to obtain the input value of the i+1-th processing stage, where i is an integer greater than or equal to 2; in response to the number of input values ​​of the i-th processing stage being 2, performing the atomic operation of the target type on the 2 input values ​​of the i-th processing stage to obtain the final atomic operation results corresponding to the at least three threads, where i is an integer greater than or equal to 2.

[0020] In one possible implementation, in response to the number of input values ​​of any processing stage being greater than or equal to 3 and the number of input values ​​of the processing stage being an even number, the input values ​​of the processing stage are grouped in pairs; or, in response to the number of input values ​​of any processing stage being greater than or equal to 3 and the number of input values ​​of the processing stage being an odd number, one of the input values ​​of the processing stage is used as the input value of the next processing stage of the processing stage, and the other input values ​​of the processing stage are grouped in pairs.

[0021] In a possible implementation, the atomic operation of the target type is any one of the following operations: an atomic addition operation, an atomic replacement operation, an atomic AND operation, an atomic OR operation, and an atomic XOR operation.

[0022] In one possible implementation, the device also includes: a conversion module, configured to, in response to at least three threads performing an atomic subtraction operation on the same target element in the memory, invert at least three numerical values ​​corresponding to the at least three threads respectively, and convert the atomic subtraction operation into an atomic addition operation.

[0023] In a possible implementation, the first processing module is configured to: in the first processing stage, divide the original value of the target element and the at least three values ​​corresponding to the at least three threads into groups, and through The computing units parallelize the The atomic operation of the target type is performed on the groups to obtain the input value of the second processing stage, where T represents the number of threads that perform the atomic operation of the same target type on the same target element in the memory. Indicates rounding down.

[0024] In a possible implementation, the second processing module is configured to: in response to the number of input values ​​of the i-th processing stage being greater than or equal to 3, divide the input values ​​of the i-th processing stage into groups, and through The computing units parallelize the groups to perform atomic operations of the target type to obtain input values ​​of the i+1th processing stage, where i is an integer greater than or equal to 2, and N represents the number of input values ​​of the i-th processing stage; in response to the number of input values ​​of the i-th processing stage being 2, performing atomic operations of the target type on the two input values ​​of the i-th processing stage through a computing unit to obtain final atomic operation results corresponding to the at least three threads, where i is an integer greater than or equal to 2.

[0025] In one possible implementation, T threads are processed by a computing architecture including T computing units, wherein any one of the T computing units includes two input terminals and one output terminal, and the T computing units correspond to different threads among the T threads; the two input terminals of a computing unit in the first processing stage respectively input the original value of a memory element corresponding to the computing unit and the numerical value corresponding to the thread corresponding to the computing unit, wherein the original value of the memory element corresponding to the computing unit represents the memory element on which the thread corresponding to the computing unit performs an atomic operation; for any other computing unit in the first processing stage, one input terminal of the computing unit inputs the numerical value corresponding to the thread corresponding to the computing unit, and the other input terminal is connected to a selection unit corresponding to the computing unit, and the selection unit is used to select one item from the original value of the memory element corresponding to the computing unit and the input factor corresponding to the computing unit, wherein the input factor corresponding to any computing unit is the numerical value corresponding to the thread corresponding to any computing unit other than the computing unit in the first processing stage, and the input factors corresponding to different computing units are different.

[0026] In a possible implementation, the output end of a computing unit in a non-last processing stage is connected to the input end of a selection unit corresponding to a computing unit in a subsequent processing stage, the output end of each computing unit in a non-last processing stage is respectively connected to the input end of only a single selection unit, and the output ends of different computing units are connected to different selection units; for any computing unit in the i-th processing stage, when a numerical value corresponding to a thread corresponding to the computing unit is input into one input end of the computing unit, the other input end of the computing unit is connected to the selection unit corresponding to the computing unit, and the selection unit is used to select one item from the memory element corresponding to the computing unit and the output of the computing unit in the previous processing stage; wherein, in non-first Among the computing units in the processing stages, there is at most one computing unit whose one input end inputs the numerical value corresponding to the thread corresponding to the computing unit, and the other input end of the computing unit and the two input ends of the other computing units are all connected to the selection unit; for any computing unit in the i-th processing stage, when both input ends of the computing unit are connected to the selection unit, one selection unit corresponding to the computing unit is used to select one item from the numerical value corresponding to the thread corresponding to the computing unit and the output of the computing unit in the previous processing stage, and the other selection unit corresponding to the computing unit is used to select one item from the memory element corresponding to the computing unit and the output of the computing unit in the previous processing stage, where i is an integer greater than or equal to 2.

[0027] In one possible implementation, when the T threads perform atomic operations of the same target type on the same target element in the memory, the selection unit of the first processing stage is used to select the input factor corresponding to the computing unit, and each selection unit other than the first processing stage is used to select the output of the computing unit of the previous processing stage; when the T threads perform atomic operations on different elements in the memory, the selection unit of the first processing stage is used to select the memory element corresponding to the computing unit; for any computing unit of the i-th processing stage, when the computing unit has only one input end connected to the selection unit, the selection unit corresponding to the computing unit is used to select the memory element corresponding to the computing unit; for any computing unit of the i-th processing stage, when both input ends of the computing unit are connected to the selection unit, one selection unit corresponding to the computing unit is used to select the numerical value corresponding to the thread corresponding to the computing unit, and the other selection unit corresponding to the computing unit is used to select the memory element corresponding to the computing unit.

[0028] According to one aspect of an embodiment of the present disclosure, an electronic device is provided, comprising: one or more processors; a memory for storing executable instructions; wherein the one or more processors are configured to call the executable instructions stored in the memory to execute the above method.

[0029] According to one aspect of an embodiment of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the above method is implemented.

[0030] According to one aspect of an embodiment of the present disclosure, a computer program product is provided, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in an electronic device, a processor in the electronic device executes the above method.

[0031] In an embodiment of the present disclosure, in response to at least three threads performing atomic operations of the same target type on the same target element in the memory, and the atomic operations of the target type conform to the associative law, in a first processing stage, the original value of the target element and at least three numerical values ​​corresponding to the at least three threads are grouped, and the atomic operations of the target type are performed on each group in parallel to obtain the input value of the second processing stage, and based on the input value of the second processing stage, the final atomic operation results corresponding to the at least three threads are obtained. Therefore, when at least three threads perform atomic operations of the same target type on the same target element in the memory and the atomic operations of the target type conform to the associative law, the system throughput can be improved and the program execution speed can be improved by grouping and performing the atomic operations of each group in parallel.

[0032] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, rather than limiting the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and, together with the specification, are used to explain the technical solutions of the present disclosure.

[0034] FIG1 is a schematic diagram showing a group of threads executing atomic operations in parallel on different elements in memory in the related art.

[0035] FIG2 is a schematic diagram showing a group of threads executing atomic operations in parallel on the same element in memory in the related art.

[0036] FIG3 shows a flowchart of a method for processing atomic operations provided by an embodiment of the present disclosure.

[0037] FIG4 shows a schematic diagram of a computing architecture including three computing units in a processing method for atomic operations provided by an embodiment of the present disclosure.

[0038] FIG5 is a schematic diagram showing an atomic operation processing method provided by an embodiment of the present disclosure, in which three threads perform an atomic operation of the same target type on the same target element in the memory.

[0039] FIG6 is a schematic diagram showing three threads performing atomic operations on different elements in memory in the atomic operation processing method provided by an embodiment of the present disclosure.

[0040] FIG7 shows a schematic diagram of a computing architecture including four computing units in a processing method for atomic operations provided by an embodiment of the present disclosure.

[0041] FIG8 is a schematic diagram showing an atomic operation processing method provided by an embodiment of the present disclosure, in which four threads perform an atomic operation of the same target type on the same target element in the memory.

[0042] FIG9 is a schematic diagram showing four threads performing atomic operations on different elements in memory in the atomic operation processing method provided by an embodiment of the present disclosure.

[0043] FIG10 shows a schematic diagram of a computing architecture including five computing units in the atomic operation processing method provided by an embodiment of the present disclosure.

[0044] FIG11 is a schematic diagram showing six threads performing atomic operations of the same target type on the same target element in memory in the atomic operation processing method provided by an embodiment of the present disclosure.

[0045] FIG12 is a schematic diagram showing five threads performing atomic operations on different elements in memory in the atomic operation processing method provided by an embodiment of the present disclosure.

[0046] FIG13 shows a schematic diagram of a computing architecture including eight computing units in the atomic operation processing method provided by an embodiment of the present disclosure.

[0047] FIG14 is a schematic diagram showing an atomic operation processing method provided by an embodiment of the present disclosure, in which eight threads perform atomic operations of the same target type on the same target element in the memory.

[0048] FIG15 shows a schematic diagram of eight threads performing atomic operations on different elements in memory in the atomic operation processing method provided by an embodiment of the present disclosure.

[0049] FIG16 shows a block diagram of a processing device for atomic operations provided by an embodiment of the present disclosure.

[0050] FIG17 shows a block diagram of an electronic device 1900 provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the accompanying drawings, identical reference numerals indicate elements with identical or similar functions. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise noted. The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as superior or preferable to other embodiments. The term "and / or" herein is simply a description of an association between associated objects, indicating that three relationships can exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the term "at least one" herein means any combination of at least two of any one or more of a plurality of elements. For example, "comprising at least one of A, B, and C" can mean comprising any one or more elements selected from the set consisting of A, B, and C. Furthermore, to better illustrate the present disclosure, numerous specific details are provided in the following detailed description. Those skilled in the art will appreciate that the present disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail to highlight the main points of the present disclosure.

[0052] Figure 1 shows a schematic diagram of a group of threads performing atomic operations in parallel on different elements in memory, as described in the related art. In Figure 1, a represents the address of an element, and t represents a thread. In the example shown in Figure 1, four threads, t0, t1, t2, and t3, perform atomic addition operations on four different elements in memory (i.e., the elements in a0, a1, a2, and a3). Because the four threads perform atomic addition operations on different elements in memory, the atomic addition operations of the four threads can be performed in parallel. Specifically, the data in thread 0 (t0) is added to the data in address 0 (a0) and written back to address 0; the data in thread 1 (t1) is added to the data in address 1 (a1) and written back to address 1; the data in thread 2 (t2) is added to the data in address 2 (a2) and written back to address 2; and the data in thread 3 (t3) is added to the data in address 3 (a3) ​​and written back to address 3.

[0053] Figure 2 shows a schematic diagram of a group of threads performing atomic operations in parallel on the same element in memory in the related art. In Figure 2, a represents the address of the element, and t represents the thread. In the example shown in Figure 2, four threads t0, t1, t2, and t3 perform atomic addition operations on the same element in memory (i.e., the element in a0). Since the four threads perform atomic addition operations on the same element in memory, the atomic addition operations of the four threads need to be performed serially. As shown in Figure 4, in the first processing stage, the data in thread 0 (t0) is added to the data in address 0 (a0); in the second processing stage, the data in thread 1 (t1) is added to the data in address 0 (a0); in the third processing stage, the data in thread 2 (t2) is added to the data in address 0 (a0); and in the fourth processing stage, the data in thread 3 (t3) is added to the data in address 0 (a0).

[0054] The embodiments of the present disclosure provide a method, apparatus, electronic device and storage medium for processing atomic operations, which perform atomic operations of the same target type on the same target element in memory in response to at least three threads, and the atomic operations of the target type conform to the associative law. In a first processing stage, the original value of the target element and at least three numerical values ​​corresponding to the at least three threads are grouped, and the atomic operations of the target type are performed on each group in parallel to obtain the input value of the second processing stage, and based on the input value of the second processing stage, the final atomic operation results corresponding to the at least three threads are obtained. Therefore, when at least three threads perform atomic operations of the same target type on the same target element in memory and the atomic operations of the target type conform to the associative law, the system throughput can be improved and the program execution speed can be improved by grouping and performing the atomic operations of each group in parallel.

[0055] The processing method of atomic operations provided by the embodiments of the present disclosure is described in detail below with reference to the accompanying drawings.

[0056] Figure 3 shows a flowchart of the method for processing atomic operations provided by an embodiment of the present disclosure. In one possible implementation, the execution subject of the method for processing atomic operations may be a processing device for atomic operations. For example, the method for processing atomic operations may be executed by a terminal device or a server or other electronic device. The terminal device may be a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device or a wearable device, etc. In some possible implementations, the method for processing atomic operations may be implemented by a processor calling computer-readable instructions stored in a memory. As shown in Figure 3, the method for processing atomic operations includes steps S31 to S32.

[0057] In step S31, in response to at least three threads performing atomic operations of the same target type on the same target element in the memory, and the atomic operations of the target type conform to the associative law, in the first processing stage, the original value of the target element and at least three numerical values ​​corresponding to the at least three threads are grouped, and the atomic operations of the target type are performed on each group in parallel to obtain the input value of the second processing stage.

[0058] In step S32, final atomic operation results corresponding to the at least three threads are obtained according to the input values ​​of the second processing stage.

[0059] In the embodiment of the present disclosure, an element in the memory may be a byte, and different elements may correspond to different memory addresses, that is, elements in different memory addresses may be different elements.

[0060] In an embodiment of the present disclosure, when at least three threads perform atomic operations of the same target type on the same target element in memory, and the atomic operations of the target type conform to the associative law, in the first processing stage, the original value of the target element and the at least three numerical values ​​corresponding to the at least three threads are grouped. Each group may include two values. Any group may include the original value of the target element and a numerical value corresponding to one thread, or may include two numerical values ​​corresponding to two threads. Moreover, the original value of the target element and any of the at least three numerical values ​​corresponding to the at least three threads belong to at most only one group, and only one group includes the original value of the target element.

[0061] In one possible implementation, when the number of threads performing atomic operations of the same target type on the same target element in memory is odd, the original value of the target element and the numerical value corresponding to each thread are divided into groups. For example, if thread 0, thread 1, and thread 2 perform atomic operations of the same target type on the same target element in memory, then the original value of the target element and the numerical value corresponding to thread 0 can be divided into group 1, and the numerical value corresponding to thread 1 and the numerical value corresponding to thread 2 can be divided into group 2. For another example, if thread 0, thread 1, thread 2, thread 3, and thread 4 perform atomic operations of the same target type on the same target element in memory, then the original value of the target element and the numerical value corresponding to thread 0 can be divided into group 1, the numerical value corresponding to thread 1 and the numerical value corresponding to thread 2 can be divided into group 2, and the numerical value corresponding to thread 3 and the numerical value corresponding to thread 4 can be divided into group 3.

[0062] In another possible implementation, when the number of threads performing atomic operations of the same target type on the same target element in memory is even, the value corresponding to one thread is not grouped into a group, and the value corresponding to that thread is directly used as the input value for the second processing stage. For example, if threads 0, 1, 2, and 3 perform atomic operations of the same target type on the same target element in memory, the original value of the target element and the value corresponding to thread 0 can be grouped into group 1, the value corresponding to thread 1 and the value corresponding to thread 2 can be grouped into group 2, and the value corresponding to thread 3 can be directly used as the input value for the second processing stage. For another example, if threads 0, 1, 2, 3, 4, and 5 perform atomic operations of the same target type on the same target element in memory, the original value of the target element and the value corresponding to thread 0 can be grouped into group 1, the value corresponding to thread 1 and the value corresponding to thread 2 can be grouped into group 2, the value corresponding to thread 3 and the value corresponding to thread 4 can be grouped into group 3, and the value corresponding to thread 5 can be directly used as the input value for the second processing stage.

[0063] In an embodiment of the present disclosure, by performing atomic operations of the same target type on the same target element in memory by at least three threads, and the atomic operations of the target type conform to the associative law, in a first processing stage, the original value of the target element and at least three numerical values ​​corresponding to the at least three threads are grouped, and the atomic operations of the target type are performed on each group in parallel to obtain the input value of the second processing stage, thereby improving the system throughput and the program execution speed through the grouping and parallel processing of the first processing stage.

[0064] For example, if threads 0, 1, and 2 perform atomic operations of the same target type on the same target element in memory, in the first processing phase, the original value of the target element and the value corresponding to thread 0 are grouped into group 1, while the value corresponding to thread 1 and the value corresponding to thread 2 are grouped into group 2. The atomic operations for group 1 and group 2 are then performed in parallel. By performing atomic operations on two groups in parallel in the first processing phase, one processing phase can be saved for the entire process.

[0065] For example, if threads 0, 1, 2, and 3 perform atomic operations of the same target type on the same target element in memory, in the first processing phase, the original value of the target element and the value corresponding to thread 0 are grouped into group 1, while the value corresponding to thread 1 and the value corresponding to thread 2 are grouped into group 2. The atomic operations for groups 1 and 2 are then performed in parallel. By performing atomic operations on two groups in parallel in the first processing phase, one processing phase can be saved for the entire process.

[0066] For example, if threads 0, 1, 2, 3, and 4 perform atomic operations of the same target type on the same target element in memory, in the first processing stage, the original value of the target element and the value corresponding to thread 0 are grouped into group 1, the value corresponding to thread 1 and the value corresponding to thread 2 are grouped into group 2, and the value corresponding to thread 3 and the value corresponding to thread 4 are grouped into group 3. The atomic operations for groups 1, 2, and 3 are then performed in parallel. By performing atomic operations on three groups in parallel in the first processing stage, two processing stages can be saved for the entire process.

[0067] For example, if threads 0, 1, 2, 3, 4, and 5 perform atomic operations of the same target type on the same target element in memory, in the first processing stage, the original value of the target element and the value corresponding to thread 0 are grouped into group 1, the value corresponding to thread 1 and the value corresponding to thread 2 are grouped into group 2, and the value corresponding to thread 3 and the value corresponding to thread 4 are grouped into group 3. The atomic operations for groups 1, 2, and 3 are then performed in parallel. By performing atomic operations on three groups in parallel in the first processing stage, two processing stages can be saved for the entire process.

[0068] For example, threads 0, 1, 2, 3, 4, 5, 6, 7, and 8 perform atomic operations of the same target type on the same target element in memory. In the first processing stage, the original value of the target element and the value corresponding to thread 0 are grouped into group 1, the value corresponding to thread 1 and the value corresponding to thread 2 are grouped into group 2, the value corresponding to thread 3 and the value corresponding to thread 4 are grouped into group 3, the value corresponding to thread 5 and the value corresponding to thread 6 are grouped into group 4, and the value corresponding to thread 7 and the value corresponding to thread 8 are grouped into group 5. The atomic operations on group 1, group 2, group 3, group 4, and group 5 are performed in parallel. Therefore, by performing atomic operations on five groups in parallel in the first processing stage, four processing stages can be saved for the entire process.

[0069] In a possible implementation, the atomic operation of the target type is any one of the following operations: atomic add, atomic exchange, atomic AND, atomic OR, and atomic XOR.

[0070] In this implementation, when at least three threads perform atomic addition operations on the same target element in the memory, in the first processing stage, the original value of the target element and the at least three numerical values ​​corresponding to the at least three threads can be grouped, and the atomic addition operations can be performed on each group in parallel to obtain the input value of the second processing stage, and based on the input value of the second processing stage, the final atomic addition operation results corresponding to the at least three threads are obtained. Therefore, when at least three threads perform atomic addition operations on the same target element in the memory, the system throughput can be improved and the program execution speed can be improved by grouping and performing the atomic addition operations on each group in parallel.

[0071] In this implementation, when at least three threads perform an atomic replacement operation on the same target element in the memory, in the first processing stage, the original value of the target element and the at least three numerical values ​​corresponding to the at least three threads can be grouped, and the atomic replacement operation can be performed on each group in parallel to obtain the input value of the second processing stage, and based on the input value of the second processing stage, the final atomic replacement operation results corresponding to the at least three threads are obtained. Therefore, when at least three threads perform an atomic replacement operation on the same target element in the memory, the system throughput can be improved and the program execution speed can be improved by grouping and performing the atomic replacement operation on each group in parallel.

[0072] In this implementation, when at least three threads perform atomic AND operations on the same target element in the memory, in the first processing stage, the original value of the target element and at least three numerical values ​​corresponding to the at least three threads can be grouped, and the atomic AND operations can be performed on each group in parallel to obtain the input value of the second processing stage, and based on the input value of the second processing stage, the final atomic AND operation results corresponding to the at least three threads are obtained. Therefore, when at least three threads perform atomic AND operations on the same target element in the memory, the system throughput can be improved and the program execution speed can be improved by grouping and performing the atomic AND operations on each group in parallel.

[0073] In this implementation, when at least three threads perform atomic OR operations on the same target element in memory, in the first processing stage, the original value of the target element and at least three numerical values ​​corresponding to the at least three threads can be grouped, and the atomic OR operations can be performed on each group in parallel to obtain the input value of the second processing stage, and based on the input value of the second processing stage, the final atomic OR operation results corresponding to the at least three threads are obtained. Therefore, when at least three threads perform atomic OR operations on the same target element in memory, the system throughput can be improved and the program execution speed can be improved by grouping and performing the atomic OR operations on each group in parallel.

[0074] In this implementation, when at least three threads perform atomic XOR operations on the same target element in the memory, in the first processing stage, the original value of the target element and the at least three numerical values ​​corresponding to the at least three threads can be grouped, and atomic XOR operations can be performed on each group in parallel to obtain the input value of the second processing stage, and based on the input value of the second processing stage, the final atomic XOR operation results corresponding to the at least three threads are obtained. Therefore, when at least three threads perform atomic XOR operations on the same target element in the memory, the system throughput can be improved and the program execution speed can be improved by grouping and performing atomic XOR operations on each group in parallel.

[0075] In one possible implementation, in response to at least three threads performing atomic operations of the same target type on the same target element in the memory, and the atomic operations of the target type conform to the associative law, in the first processing stage, before grouping the original value of the target element and the at least three numerical values ​​corresponding to the at least three threads, the method further includes: in response to at least three threads performing atomic subtraction operations on the same target element in the memory, respectively inverting the at least three numerical values ​​corresponding to the at least three threads, and converting the atomic subtraction operation into an atomic addition operation.

[0076] In this implementation, an atomic subtraction operation can be converted to an atomic addition operation by inverting the signal bits of the source operands. For example, bd can be converted to b+(-d) to convert an atomic subtraction operation to an atomic addition operation.

[0077] In this implementation, in response to at least three threads performing atomic subtraction operations on the same target element in the memory, at least three values ​​corresponding to the at least three threads are respectively inverted, and the atomic subtraction operations are converted into atomic addition operations. Therefore, when at least three threads perform atomic subtraction operations on the same target element in the memory, the system throughput can be improved and the program execution speed can be improved by grouping and performing the atomic subtraction operations of each group in parallel.

[0078] In one possible implementation, in response to at least three threads performing atomic operations of the same target type on the same target element in the memory, and the atomic operations of the target type conform to the associative law, in the first processing stage, before grouping the original value of the target element and the at least three numerical values ​​corresponding to the at least three threads, the method further includes: in response to at least three threads performing atomic operations on the same target element in the memory, and some of the at least three threads performing atomic addition operations on the target element and other threads performing atomic subtraction operations on the target element, inverting the numerical values ​​corresponding to the threads performing the atomic subtraction operations, and converting the atomic subtraction operations into atomic addition operations.

[0079] In the embodiment of the present disclosure, the atomic operations of the target type may be performed in parallel or serially from the second processing stage to the last processing stage, which is not limited here.

[0080] In one possible implementation, the obtaining of the final atomic operation results corresponding to the at least three threads based on the input values ​​of the second processing stage includes: in response to the number of input values ​​of the i-th processing stage being greater than or equal to 3, grouping the input values ​​of the i-th processing stage, and performing the atomic operation of the target type on each group in parallel to obtain the input value of the i+1-th processing stage, where i is an integer greater than or equal to 2; in response to the number of input values ​​of the i-th processing stage being 2, performing the atomic operation of the target type on the 2 input values ​​of the i-th processing stage to obtain the final atomic operation results corresponding to the at least three threads, where i is an integer greater than or equal to 2.

[0081] In this implementation, if the number of input values ​​of the i-th processing stage is greater than or equal to 3, the input values ​​of the i-th processing stage can be grouped, and the atomic operation of the target type can be performed on each group in parallel to obtain the input value of the i+1-th processing stage. For example, when the number of threads performing atomic operations of the same target type on the same target element in the memory is 6, and the number of input values ​​of the second processing stage is 4, then the 4 input values ​​of the second processing stage can be divided into two groups, and the atomic operation of the target type can be performed on the two groups in parallel. For another example, when the number of threads performing atomic operations of the same target type on the same target element in the memory is 7, and the number of input values ​​of the second processing stage is 4, then the 4 input values ​​of the second processing stage can be divided into two groups, and the atomic operation of the target type can be performed on the two groups in parallel.

[0082] In this implementation, if the number of input values ​​of the i-th processing stage is 2, then the atomic operation of the target type can be performed on the two input values ​​of the i-th processing stage to obtain the final atomic operation results corresponding to the at least three threads. For example, when the number of threads performing atomic operations of the same target type on the same target element in the memory is 3, and the number of input values ​​of the second processing stage is 2, then the atomic operation of the target type can be performed on the two input values ​​of the second processing stage to obtain the final atomic operation results corresponding to the three threads. For another example, when the number of threads performing atomic operations of the same target type on the same target element in the memory is 6, and the number of input values ​​of the third processing stage is 2, then the atomic operation of the target type can be performed on the two input values ​​of the third processing stage to obtain the final atomic operation results corresponding to the six threads.

[0083] In this implementation, in response to the number of input values ​​of the i-th processing stage being greater than or equal to 3, the input values ​​of the i-th processing stage are grouped, and the atomic operation of the target type is performed on each group in parallel to obtain the input value of the i+1-th processing stage. In response to the number of input values ​​of the i-th processing stage being 2, the atomic operation of the target type is performed on the 2 input values ​​of the i-th processing stage to obtain the final atomic operation results corresponding to the at least three threads, wherein i is an integer greater than or equal to 2. This enables the system throughput to be improved and the program execution speed to be improved by grouping and performing atomic operations on each group in parallel in the i-th processing stage.

[0084] In one possible implementation, in response to the number of input values ​​of any processing stage being greater than or equal to 3 and the number of input values ​​of the processing stage being an even number, the input values ​​of the processing stage are grouped in pairs; or, in response to the number of input values ​​of any processing stage being greater than or equal to 3 and the number of input values ​​of the processing stage being an odd number, one of the input values ​​of the processing stage is used as the input value of the next processing stage of the processing stage, and the other input values ​​of the processing stage are grouped in pairs.

[0085] In this implementation, in response to the number of input values ​​of any processing stage being greater than or equal to 3 and the number of input values ​​of the processing stage being an even number, the input values ​​of the processing stage are grouped in pairs; or, in response to the number of input values ​​of any processing stage being greater than or equal to 3 and the number of input values ​​of the processing stage being an odd number, one of the input values ​​of the processing stage is used as the input value of the next processing stage of the processing stage, and the other input values ​​of the processing stage are grouped in pairs, thereby maximizing the number of atomic operations performed in parallel and thus maximizing the program execution speed.

[0086] In a possible implementation, in the first processing stage, the original value of the target element and the at least three values ​​corresponding to the at least three threads are grouped, and the atomic operation of the target type is performed on each group in parallel to obtain the input value of the second processing stage, including: in the first processing stage, the original value of the target element and the at least three values ​​corresponding to the at least three threads are divided into groups, and through The computing units parallelize the The atomic operation of the target type is performed on the groups to obtain the input value of the second processing stage, where T represents the number of threads that perform the atomic operation of the same target type on the same target element in the memory. Indicates rounding down.

[0087] For example, if the number of threads performing atomic operations of the same target type on the same target element in memory is 3, in the first processing stage, the original value of the target element and the 3 numerical values ​​corresponding to the 3 threads are divided into 2 groups, and the atomic operations of the target type are performed on the 2 groups in parallel by 2 computing units. For another example, if the number of threads performing atomic operations of the same target type on the same target element in memory is 8, in the first processing stage, the original value of the target element and the 8 numerical values ​​corresponding to the 8 threads are divided into 4 groups, and the numerical value corresponding to the remaining thread is directly used as the input value of the second processing stage, and the atomic operations of the target type are performed on the 4 groups in parallel by 4 computing units.

[0088] In this implementation, in the first processing stage at least The system performs atomic operations of the target type in parallel on multiple computing units, instead of performing atomic operations of the target type serially in more processing stages through one computing unit, thereby improving system throughput and program execution speed.

[0089] In a possible implementation, obtaining the final atomic operation results corresponding to the at least three threads according to the input values ​​of the second processing stage includes: in response to the number of input values ​​of the i-th processing stage being greater than or equal to 3, dividing the input values ​​of the i-th processing stage into groups, and through The computing units parallelize the groups to perform atomic operations of the target type to obtain input values ​​of the i+1th processing stage, where i is an integer greater than or equal to 2, and N represents the number of input values ​​of the i-th processing stage; in response to the number of input values ​​of the i-th processing stage being 2, performing atomic operations of the target type on the two input values ​​of the i-th processing stage through a computing unit to obtain final atomic operation results corresponding to the at least three threads, where i is an integer greater than or equal to 2.

[0090] For example, if the number of input values ​​in the i-th processing stage is 4, the input values ​​in the i-th processing stage are divided into 2 groups, and the atomic operation of the target type is performed on the 2 groups in parallel by 2 computing units. For another example, if the number of input values ​​in the i-th processing stage is 7, the input values ​​in the i-th processing stage are divided into 3 groups, and the remaining input value is used as the input value of the (i+1)-th processing stage, and the atomic operation of the target type is performed on the 3 groups in parallel by 3 computing units.

[0091] In this implementation, in the i-th processing stage, The system performs atomic operations of the target type in parallel on multiple computing units, instead of performing atomic operations of the target type serially in more processing stages through one computing unit, thereby improving system throughput and program execution speed.

[0092] In one possible implementation, T threads are processed by a computing architecture including T computing units, wherein any one of the T computing units includes two input terminals and one output terminal, and the T computing units correspond to different threads among the T threads; the two input terminals of a computing unit in the first processing stage respectively input the original value of a memory element corresponding to the computing unit and the numerical value corresponding to the thread corresponding to the computing unit, wherein the original value of the memory element corresponding to the computing unit represents the memory element on which the thread corresponding to the computing unit performs an atomic operation; for any other computing unit in the first processing stage, one input terminal of the computing unit inputs the numerical value corresponding to the thread corresponding to the computing unit, and the other input terminal is connected to a selection unit corresponding to the computing unit, and the selection unit is used to select one item from the original value of the memory element corresponding to the computing unit and the input factor corresponding to the computing unit, wherein the input factor corresponding to any computing unit is the numerical value corresponding to the thread corresponding to any computing unit other than the computing unit in the first processing stage, and the input factors corresponding to different computing units are different.

[0093] The number of computing units can scale with the number of threads. For example, a computing architecture with four computing units can process four threads, a computing architecture with eight computing units can process eight threads, a computing architecture with twelve computing units can process twelve threads, and so on. By adopting this implementation, it is possible to use the same computing architecture to accommodate both situations where different threads perform the same type of atomic operation on the same element and situations where different threads perform atomic operations on different elements.

[0094] In another possible implementation, different computing architectures may be used for situations where different threads perform the same type of atomic operation on the same element and situations where different threads perform atomic operations on different elements. That is, a computing architecture may be designed that is only applicable to situations where different threads perform the same type of atomic operation on the same element, and that is, a computing architecture that is applicable to situations where different threads perform the same type of atomic operation on the same element may not be applicable to situations where different threads perform atomic operations on different elements. In this implementation, when different threads perform atomic operations on different elements, a parallel architecture in the related art may be used for processing.

[0095] In a possible implementation, the output end of a computing unit in a non-last processing stage is connected to the input end of a selection unit corresponding to a computing unit in a subsequent processing stage, the output end of each computing unit in a non-last processing stage is respectively connected to the input end of only a single selection unit, and the output ends of different computing units are connected to different selection units; for any computing unit in the i-th processing stage, when a numerical value corresponding to a thread corresponding to the computing unit is input into one input end of the computing unit, the other input end of the computing unit is connected to the selection unit corresponding to the computing unit, and the selection unit is used to select one item from the memory element corresponding to the computing unit and the output of the computing unit in the previous processing stage; wherein, in non-first Among the computing units in the processing stages, there is at most one computing unit whose one input end inputs the numerical value corresponding to the thread corresponding to the computing unit, and the other input end of the computing unit and the two input ends of the other computing units are all connected to the selection unit; for any computing unit in the i-th processing stage, when both input ends of the computing unit are connected to the selection unit, one selection unit corresponding to the computing unit is used to select one item from the numerical value corresponding to the thread corresponding to the computing unit and the output of the computing unit in the previous processing stage, and the other selection unit corresponding to the computing unit is used to select one item from the memory element corresponding to the computing unit and the output of the computing unit in the previous processing stage, where i is an integer greater than or equal to 2.

[0096] In this implementation, the outputs of computing units in non-final processing stages are connected to the inputs of selection units corresponding to computing units in subsequent processing stages. For example, the output of a computing unit in the first processing stage may be connected to the input of a selection unit corresponding to a computing unit in the second processing stage, or may be connected to the input of a selection unit corresponding to a computing unit in the third processing stage, and so on.

[0097] In this implementation, the output end of each computing unit other than the last processing stage is connected to the input end of the selection unit of the subsequent processing stage, the output end of each computing unit other than the last processing stage is respectively connected to the input end of only a single selection unit, and the output ends of different computing units are connected to different selection units.

[0098] In this implementation, each computing unit other than the first processing stage may have both input terminals connected to the selection unit, or may have one input terminal connected to the selection unit and the other input terminal input a value corresponding to the thread corresponding to the computing unit.

[0099] By adopting this implementation method, it is possible to use the same computing architecture to take into account both the situation where different threads perform the same type of atomic operations on the same element and the situation where different threads perform atomic operations on different elements.

[0100] In one possible implementation, when the T threads perform atomic operations of the same target type on the same target element in the memory, the selection unit of the first processing stage is used to select the input factor corresponding to the computing unit, and each selection unit other than the first processing stage is used to select the output of the computing unit of the previous processing stage; when the T threads perform atomic operations on different elements in the memory, the selection unit of the first processing stage is used to select the memory element corresponding to the computing unit; for any computing unit of the i-th processing stage, when the computing unit has only one input end connected to the selection unit, the selection unit corresponding to the computing unit is used to select the memory element corresponding to the computing unit; for any computing unit of the i-th processing stage, when both input ends of the computing unit are connected to the selection unit, one selection unit corresponding to the computing unit is used to select the numerical value corresponding to the thread corresponding to the computing unit, and the other selection unit corresponding to the computing unit is used to select the memory element corresponding to the computing unit.

[0101] In this implementation, when the T threads perform atomic operations on different elements in the memory, for any computing unit in the i-th processing stage, if only one input terminal of the computing unit is connected to a selection unit, the selection unit corresponding to the computing unit is used to select the memory element corresponding to the computing unit. When the T threads perform atomic operations on different elements in the memory, for any computing unit in the i-th processing stage, if both input terminals of the computing unit are connected to a selection unit, one selection unit corresponding to the computing unit is used to select the value corresponding to the thread corresponding to the computing unit, and the other selection unit corresponding to the computing unit is used to select the memory element corresponding to the computing unit.

[0102] Using the architecture provided by this implementation method, when multiple threads perform atomic operations on different elements in the memory, the selection unit of the first processing stage is used to select the memory element corresponding to the computing unit, and the various selection units other than the first processing stage are used to select the memory element or the numerical value corresponding to the thread, thereby achieving the same program execution efficiency and throughput as traditional parallel methods.

[0103] The atomic operation processing method provided by the embodiments of the present disclosure can be applied to technical fields such as GPU, SIMD (Single Instruction Multiple Data) structure, atomic operation, etc., and is not limited here.

[0104] The following describes the atomic operation processing method provided by the embodiment of the present disclosure through a specific application scenario.

[0105] Figure 4 shows a schematic diagram of a computing architecture including three computing units in the processing method of atomic operations provided by an embodiment of the present disclosure. In Figure 4, the computing architecture includes computing unit c0, computing unit c2, and computing unit c1. Among them, the input of computing unit c0 is the original value of the element corresponding to thread t0 (i.e., the element in address a0), and the numerical value corresponding to thread t0 (i.e., the numerical value carried by thread t0 to be subjected to the target type of atomic operation with the element in address a0). One input end of computing unit c2 inputs the numerical value corresponding to thread t2, and the other input end is connected to the selection unit s2 corresponding to computing unit c2. The selection unit s2 is used to select one item from the original value of the element corresponding to computing unit c2 (i.e., the element in address a2) and the numerical value corresponding to thread t1, wherein the numerical value corresponding to thread t1 is the input factor corresponding to computing unit c2. One input end of computing unit c1 is connected to the first selection unit s11 corresponding to computing unit c1, and the other input end is connected to the second selection unit s12 corresponding to computing unit c1. The first selection unit s11 is used to select one of the output of the calculation unit c0 and the original value of the element corresponding to the calculation unit c1 (i.e., the element at address a1). The second selection unit s12 is used to select one of the values ​​corresponding to the thread t1 corresponding to the calculation unit c1 and the output of the calculation unit c2.

[0106] Figure 5 shows a schematic diagram of an atomic operation of the same target type performed by three threads on the same target element in the memory in the processing method of the atomic operation provided by an embodiment of the present disclosure. In Figure 5, a0=a1=a2. As shown in Figure 5, when three threads perform an atomic operation of the same target type on the same target element in the memory, the selection unit s2 selects the value corresponding to the thread t1, the first selection unit s11 selects the output of the calculation unit c0, and the second selection unit s12 selects the output of the calculation unit c2. In the example shown in Figure 5, the atomic operations of the same target type performed by three threads on the same target element in the memory can be processed through two processing stages. Compared with the prior art that requires three processing stages to process the atomic operations of the same target type performed by three threads on the same target element in the memory, one processing stage is reduced.

[0107] Figure 6 shows a schematic diagram of three threads performing atomic operations on different elements in the memory in the processing method of atomic operations provided by an embodiment of the present disclosure. In Figure 6, a0, a1, and a2 are not equal to each other. As shown in Figure 6, when the three threads perform atomic operations on different elements in the memory, the selection unit s2 selects the original value of the element corresponding to the calculation unit c2 (i.e., the element in the address a2), the first selection unit s11 selects the original value of the element corresponding to the calculation unit c1 (i.e., the element in the address a1), and the second selection unit s12 selects the numerical value corresponding to the thread t1 corresponding to the calculation unit c1. In the example shown in Figure 6, the calculations of the three computing units are independent of each other, and therefore, the atomic operations of the three threads on different elements in the memory can be processed in parallel through one processing stage.

[0108] Figure 7 shows a schematic diagram of a computing architecture including four computing units in the processing method of atomic operations provided by an embodiment of the present disclosure. In Figure 7, the computing architecture includes computing unit c0, computing unit c2, computing unit c1, and computing unit c3. Among them, the input of computing unit c0 is the original value of the element corresponding to thread t0 (i.e., the element in address a0), and the numerical value corresponding to thread t0 (i.e., the numerical value carried by thread t0 to be subjected to the target type atomic operation with the element in address a0). One input end of computing unit c2 inputs the numerical value corresponding to thread t2, and the other input end is connected to the selection unit s2 corresponding to computing unit c2. The selection unit s2 is used to select one item from the original value of the element corresponding to computing unit c2 (i.e., the element in address a2) and the numerical value corresponding to thread t1, wherein the numerical value corresponding to thread t1 is the input factor corresponding to computing unit c2. One input end of computing unit c1 is connected to the first selection unit s11 corresponding to computing unit c1, and the other input end is connected to the second selection unit s12 corresponding to computing unit c1. The first selection unit s11 is used to select one from the output of calculation unit c0 and the original value of the element corresponding to calculation unit c1 (i.e., the element at address a1). The second selection unit s12 is used to select one from the value corresponding to thread t1 corresponding to calculation unit c1 and the output of calculation unit c2. One input terminal of calculation unit c3 inputs the value corresponding to thread t3, and the other input terminal is connected to the selection unit s3 corresponding to calculation unit c3. Selection unit s3 is used to select one from the output of calculation unit c1 and the original value of the element corresponding to calculation unit c3 (i.e., the element at address a3).

[0109] Figure 8 shows a schematic diagram of an atomic operation of the same target type performed by four threads on the same target element in memory in the processing method of atomic operations provided by an embodiment of the present disclosure. In Figure 8, a0=a1=a2=a3. As shown in Figure 8, when four threads perform an atomic operation of the same target type on the same target element in memory, the selection unit s2 selects the value corresponding to the thread t1, the first selection unit s11 selects the output of the calculation unit c0, the second selection unit s12 selects the output of the calculation unit c2, and the selection unit s3 selects the output of the calculation unit c1. In the example shown in Figure 8, the atomic operations of the same target type performed by four threads on the same target element in memory can be processed through three processing stages. Compared with the prior art that requires four processing stages to process the atomic operations of the same target type performed by four threads on the same target element in memory, one processing stage is reduced.

[0110] Figure 9 shows a schematic diagram of four threads performing atomic operations on different elements in the memory in the processing method of atomic operations provided by an embodiment of the present disclosure. In Figure 9, a0, a1, a2, and a3 are not equal to each other. As shown in Figure 9, when four threads perform atomic operations on different elements in the memory, the selection unit s2 selects the original value of the element corresponding to the calculation unit c2 (i.e., the element in address a2), the first selection unit s11 selects the original value of the element corresponding to the calculation unit c1 (i.e., the element in address a1), the second selection unit s12 selects the numerical value corresponding to the thread t1 corresponding to the calculation unit c1, and the selection unit s3 selects the original value of the element corresponding to the calculation unit c3 (i.e., the element in address a3). In the example shown in Figure 9, the calculations of the four computing units are independent of each other, and therefore, the atomic operations of the four threads on different elements in the memory can be processed in parallel through one processing stage.

[0111] Figure 10 shows a schematic diagram of a computing architecture including five computing units in the processing method for atomic operations provided by an embodiment of the present disclosure. In Figure 10, the computing architecture includes computing unit c0, computing unit c2, computing unit c4, computing unit c1, and computing unit c3. Among them, the input of computing unit c0 is the original value of the element corresponding to thread t0 (i.e., the element in address a0), and the numerical value corresponding to thread t0 (i.e., the numerical value carried by thread t0 to be subjected to the target type of atomic operation with the element in address a0). One input end of computing unit c2 inputs the numerical value corresponding to thread t2, and the other input end is connected to the selection unit s2 corresponding to computing unit c2. The selection unit s2 is used to select one item from the original value of the element corresponding to computing unit c2 (i.e., the element in address a2) and the numerical value corresponding to thread t1, wherein the numerical value corresponding to thread t1 is the input factor corresponding to computing unit c2.

[0112] One input of computation unit c4 receives the value corresponding to thread t4, and the other input is connected to selection unit s4 corresponding to computation unit c4. Selection unit s4 is used to select one of the values ​​corresponding to the element corresponding to computation unit c4 (i.e., the element at address a4) and the value corresponding to thread t3, where the value corresponding to thread t3 is the input factor corresponding to computation unit c4. One input of computation unit c1 is connected to first selection unit s11 corresponding to computation unit c1, and the other input is connected to second selection unit s12 corresponding to computation unit c1. First selection unit s11 is used to select one of the values ​​corresponding to the output of computation unit c0 and the original value of the element corresponding to computation unit c1 (i.e., the element at address a1). Second selection unit s12 is used to select one of the values ​​corresponding to thread t1 corresponding to computation unit c1 and the output of computation unit c2. One input of computation unit c3 is connected to first selection unit s31 corresponding to computation unit c3, and the other input is connected to second selection unit s32 corresponding to computation unit c3. The first selection unit s31 is used to select one of the output of the calculation unit c1 and the original value of the element corresponding to the calculation unit c3 (i.e., the element at address a3). The second selection unit s32 is used to select one of the values ​​corresponding to the thread t3 corresponding to the calculation unit c3 and the output of the calculation unit c4.

[0113] Figure 11 shows a schematic diagram of six threads performing atomic operations of the same target type on the same target element in memory in the atomic operation processing method provided by an embodiment of the present disclosure. In Figure 11, a0=a1=a2=a3=a4. As shown in Figure 11, when five threads perform atomic operations of the same target type on the same target element in memory, selection unit s2 selects the value corresponding to thread t1, selection unit s4 selects the value corresponding to thread t3, first selection unit s11 corresponding to calculation unit c1 selects the output of calculation unit c0, second selection unit s12 corresponding to calculation unit c1 selects the output of calculation unit c2, first selection unit s31 corresponding to calculation unit c3 selects the output of calculation unit c1, and second selection unit s32 corresponding to calculation unit c3 selects the output of calculation unit c4. In the example shown in Figure 11, the atomic operations of the same target type on the same target element in memory by five threads can be processed through three processing stages. Compared with the prior art, which requires five processing stages to process the atomic operations of the same target type on the same target element in memory by five threads, two processing stages are reduced.

[0114] Figure 12 shows a schematic diagram of five threads performing atomic operations on different elements in memory in the processing method of atomic operations provided by an embodiment of the present disclosure. In Figure 12, a0, a1, a2, a3, and a4 are not equal to each other. As shown in Figure 12, when five threads perform atomic operations on different elements in memory, selection unit s2 selects the original value of the element corresponding to calculation unit c2 (i.e., the element in address a2), selection unit s4 selects the original value of the element corresponding to calculation unit c4 (i.e., the element in address a4), the first selection unit s11 corresponding to calculation unit c1 selects the original value of the element corresponding to calculation unit c1 (i.e., the element in address a1), the second selection unit s12 corresponding to calculation unit c1 selects the numerical value corresponding to thread t1 corresponding to calculation unit c1, the first selection unit s31 corresponding to calculation unit c3 selects the original value of the element corresponding to calculation unit 3 (i.e., the element in address a3), and the second selection unit s32 corresponding to calculation unit c3 selects the numerical value corresponding to thread t3 corresponding to calculation unit c3. In the example shown in FIG12 , the calculations of the five computing units are independent of each other. Therefore, the atomic operations of the five threads on different elements in the memory can be processed in parallel through one processing stage.

[0115] Figure 13 shows a schematic diagram of a computing architecture including 8 computing units in the processing method of atomic operations provided by an embodiment of the present disclosure. In Figure 13, the computing architecture includes computing unit c0, computing unit c2, computing unit c4, computing unit c6, computing unit c1, computing unit c3, computing unit c5 and computing unit c7. Among them, the input of computing unit c0 is the original value of the element corresponding to thread t0 (i.e., the element in address a0) and the numerical value corresponding to thread t0 (i.e., the numerical value carried by thread t0 to be subjected to the target type atomic operation with the element in address a0). One input end of computing unit c2 inputs the numerical value corresponding to thread t2, and the other input end is connected to the selection unit s2 corresponding to computing unit c2. The selection unit s2 is used to select one item from the original value of the element corresponding to computing unit c2 (i.e., the element in address a2) and the numerical value corresponding to thread t1, wherein the numerical value corresponding to thread t1 is the input factor corresponding to computing unit c2. One input end of computing unit c4 inputs the numerical value corresponding to thread t4, and the other input end is connected to the selection unit s4 corresponding to computing unit c4. Selection unit s4 is used to select one of the original values ​​of the element corresponding to computation unit c4 (i.e., the element at address a4) and the value corresponding to thread t3, where the value corresponding to thread t3 is the input factor corresponding to computation unit c4. Computation unit c6 has one input terminal connected to the value corresponding to thread t6, and its other input terminal is connected to selection unit s6 corresponding to computation unit c6. Selection unit s6 is used to select one of the original values ​​of the element corresponding to computation unit c6 (i.e., the element at address a6) and the value corresponding to thread t5, where the value corresponding to thread t5 is the input factor corresponding to computation unit c6. Computation unit c1 has one input terminal connected to the first selection unit s11 corresponding to computation unit c1, and its other input terminal is connected to the second selection unit s12 corresponding to computation unit c1. The first selection unit s11 is used to select one of the outputs of computation unit c0 and the original value of the element corresponding to computation unit c1 (i.e., the element at address a1). The second selection unit s12 is used to select one of the values ​​corresponding to thread t1 corresponding to computation unit c1 and the output of computation unit c2. One input of computation unit c3 is connected to a first selection unit s31 corresponding to computation unit c3, and the other input is connected to a second selection unit s32 corresponding to computation unit c3. The first selection unit s31 is used to select one of the values ​​from the output of computation unit c4 and the original value of the element corresponding to computation unit c3 (i.e., the element at address a3). The second selection unit s32 is used to select one of the values ​​from the value corresponding to thread t3 corresponding to computation unit c3 and the output of computation unit c6. One input of computation unit c5 is connected to a first selection unit s51 corresponding to computation unit c5, and the other input is connected to a second selection unit s52 corresponding to computation unit c5.Among them, the first selection unit s51 is used to select one from the output of calculation unit c1 and the original value of the element corresponding to calculation unit c5 (i.e., the element at address a5). The second selection unit s52 is used to select one from the value corresponding to thread t5 corresponding to calculation unit c5 and the output of calculation unit c3. One input terminal of calculation unit c7 inputs the value corresponding to thread t7, and the other input terminal is connected to the selection unit s7 corresponding to calculation unit c7. Selection unit s7 is used to select one from the output of calculation unit c5 and the original value of the element corresponding to calculation unit c7 (i.e., the element at address a7).

[0116] Figure 14 shows a schematic diagram of eight threads performing atomic operations of the same target type on the same target element in memory in the processing method of atomic operations provided by an embodiment of the present disclosure. In Figure 14, a0=a1=a2=a3=a4=a5=a6=a7. As shown in Figure 14, when eight threads perform atomic operations of the same target type on the same target element in memory, selection unit s2 selects the value corresponding to thread t1, selection unit s4 selects the value corresponding to thread t3, selection unit s6 selects the value corresponding to thread t5, first selection unit s11 corresponding to computing unit c1 selects the output of computing unit c0, second selection unit s12 corresponding to computing unit c1 selects the output of computing unit c2, first selection unit s31 corresponding to computing unit c3 selects the output of computing unit c4, second selection unit s32 corresponding to computing unit c3 selects the output of computing unit c6, second selection unit s52 corresponding to computing unit c5 selects the output of computing unit c1, first selection unit s51 corresponding to computing unit c5 selects the output of computing unit c3, and selection unit s7 selects the output of computing unit c5. In the example shown in FIG14 , atomic operations of the same target type on the same target element in memory by eight threads can be processed in four processing stages. This reduces the number of processing stages compared to the prior art, which requires eight processing stages to process atomic operations of the same target type on the same target element in memory by eight threads.

[0117] Figure 15 shows a schematic diagram of 8 threads performing atomic operations on different elements in memory in the processing method of atomic operations provided by an embodiment of the present disclosure. In Figure 15, a0, a1, a2, a3, a4, a5, a6, and a7 are not equal to each other. As shown in Figure 15, when 8 threads perform atomic operations on different elements in memory, the selection unit s2 selects the original value of the element corresponding to the calculation unit c2 (i.e., the element in address a2), the selection unit s4 selects the original value of the element corresponding to the calculation unit c4 (i.e., the element in address a4), the selection unit s6 selects the original value of the element corresponding to the calculation unit c6 (i.e., the element in address a6), the first selection unit s11 corresponding to the calculation unit c1 selects the original value of the element corresponding to the calculation unit c1 (i.e., the element in address a1), and the second selection unit s12 corresponding to the calculation unit c1 selects the original value of the element corresponding to the calculation unit c1. The first selection unit s31 corresponding to computing unit c3 selects the original value of the element corresponding to computing unit 31 (i.e., the element at address a3). The second selection unit s32 corresponding to computing unit c3 selects the original value corresponding to thread t3 corresponding to computing unit c3. The first selection unit s51 corresponding to computing unit c5 selects the original value of the element corresponding to computing unit 5 (i.e., the element at address a5). The second selection unit s52 corresponding to computing unit c5 selects the original value corresponding to thread t5 corresponding to computing unit c5. Selection unit s7 selects the original value of the element corresponding to computing unit 7 (i.e., the element at address a7). In the example shown in Figure 15, the calculations of the eight computing units are independent of each other. Therefore, the atomic operations of eight threads on different elements in memory can be processed in parallel through one processing stage.

[0118] It is understood that the above-mentioned various method embodiments mentioned in this disclosure can be combined with each other to form combined embodiments without violating the principle logic. Due to space limitations, this disclosure will not go into details. It is understood by those skilled in the art that in the above-mentioned methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0119] In addition, the present disclosure also provides a processing device, electronic device, computer-readable storage medium, and computer program product for atomic operations, all of which can be used to implement any atomic operation processing method provided by the present disclosure. The corresponding technical solutions and technical effects can be found in the corresponding records in the method section and will not be repeated here.

[0120] Figure 16 shows a block diagram of an atomic operation processing device provided by an embodiment of the present disclosure. As shown in Figure 16, the atomic operation processing device includes: a first processing module 161, configured to perform an atomic operation of the same target type on the same target element in the memory in response to at least three threads, and the atomic operation of the target type complies with the associative law. In the first processing stage, the original value of the target element and the at least three numerical values ​​corresponding to the at least three threads are grouped, and the atomic operation of the target type is performed on each group in parallel to obtain the input value of the second processing stage; a second processing module 162, configured to obtain the final atomic operation result corresponding to the at least three threads based on the input value of the second processing stage.

[0121] In one possible implementation, the second processing module 162 is configured as follows: in response to the number of input values ​​of the i-th processing stage being greater than or equal to 3, grouping the input values ​​of the i-th processing stage, and performing the atomic operation of the target type on each group in parallel to obtain the input value of the i+1-th processing stage, where i is an integer greater than or equal to 2; in response to the number of input values ​​of the i-th processing stage being 2, performing the atomic operation of the target type on the 2 input values ​​of the i-th processing stage to obtain the final atomic operation results corresponding to the at least three threads, where i is an integer greater than or equal to 2.

[0122] In one possible implementation, in response to the number of input values ​​of any processing stage being greater than or equal to 3 and the number of input values ​​of the processing stage being an even number, the input values ​​of the processing stage are grouped in pairs; or, in response to the number of input values ​​of any processing stage being greater than or equal to 3 and the number of input values ​​of the processing stage being an odd number, one of the input values ​​of the processing stage is used as the input value of the next processing stage of the processing stage, and the other input values ​​of the processing stage are grouped in pairs.

[0123] In a possible implementation, the atomic operation of the target type is any one of the following operations: an atomic addition operation, an atomic replacement operation, an atomic AND operation, an atomic OR operation, and an atomic XOR operation.

[0124] In one possible implementation, the device also includes: a conversion module, configured to, in response to at least three threads performing an atomic subtraction operation on the same target element in the memory, invert at least three numerical values ​​corresponding to the at least three threads respectively, and convert the atomic subtraction operation into an atomic addition operation.

[0125] In a possible implementation, the first processing module 161 is configured to: in the first processing stage, divide the original value of the target element and the at least three values ​​corresponding to the at least three threads into groups, and through The computing units parallelize the The atomic operation of the target type is performed on the groups to obtain the input value of the second processing stage, where T represents the number of threads that perform the atomic operation of the same target type on the same target element in the memory. Indicates rounding down.

[0126] In a possible implementation, the second processing module 162 is configured to: in response to the number of input values ​​of the i-th processing stage being greater than or equal to 3, divide the input values ​​of the i-th processing stage into groups, and through The computing units parallelize the groups to perform atomic operations of the target type to obtain input values ​​of the i+1th processing stage, where i is an integer greater than or equal to 2, and N represents the number of input values ​​of the i-th processing stage; in response to the number of input values ​​of the i-th processing stage being 2, performing atomic operations of the target type on the two input values ​​of the i-th processing stage through a computing unit to obtain final atomic operation results corresponding to the at least three threads, where i is an integer greater than or equal to 2.

[0127] In one possible implementation, T threads are processed by a computing architecture including T computing units, wherein any one of the T computing units includes two input terminals and one output terminal, and the T computing units correspond to different threads among the T threads; the two input terminals of a computing unit in the first processing stage respectively input the original value of a memory element corresponding to the computing unit and the numerical value corresponding to the thread corresponding to the computing unit, wherein the original value of the memory element corresponding to the computing unit represents the memory element on which the thread corresponding to the computing unit performs an atomic operation; for any other computing unit in the first processing stage, one input terminal of the computing unit inputs the numerical value corresponding to the thread corresponding to the computing unit, and the other input terminal is connected to a selection unit corresponding to the computing unit, and the selection unit is used to select one item from the original value of the memory element corresponding to the computing unit and the input factor corresponding to the computing unit, wherein the input factor corresponding to any computing unit is the numerical value corresponding to the thread corresponding to any computing unit other than the computing unit in the first processing stage, and the input factors corresponding to different computing units are different.

[0128] In a possible implementation, the output end of a computing unit in a non-last processing stage is connected to the input end of a selection unit corresponding to a computing unit in a subsequent processing stage, the output end of each computing unit in a non-last processing stage is respectively connected to the input end of only a single selection unit, and the output ends of different computing units are connected to different selection units; for any computing unit in the i-th processing stage, when a numerical value corresponding to a thread corresponding to the computing unit is input into one input end of the computing unit, the other input end of the computing unit is connected to the selection unit corresponding to the computing unit, and the selection unit is used to select one item from the memory element corresponding to the computing unit and the output of the computing unit in the previous processing stage; wherein, in non-first Among the computing units in the processing stages, there is at most one computing unit whose one input end inputs the numerical value corresponding to the thread corresponding to the computing unit, and the other input end of the computing unit and the two input ends of the other computing units are all connected to the selection unit; for any computing unit in the i-th processing stage, when both input ends of the computing unit are connected to the selection unit, one selection unit corresponding to the computing unit is used to select one item from the numerical value corresponding to the thread corresponding to the computing unit and the output of the computing unit in the previous processing stage, and the other selection unit corresponding to the computing unit is used to select one item from the memory element corresponding to the computing unit and the output of the computing unit in the previous processing stage, where i is an integer greater than or equal to 2.

[0129] In one possible implementation, when the T threads perform atomic operations of the same target type on the same target element in the memory, the selection unit of the first processing stage is used to select the input factor corresponding to the computing unit, and each selection unit other than the first processing stage is used to select the output of the computing unit of the previous processing stage; when the T threads perform atomic operations on different elements in the memory, the selection unit of the first processing stage is used to select the memory element corresponding to the computing unit; for any computing unit of the i-th processing stage, when the computing unit has only one input end connected to the selection unit, the selection unit corresponding to the computing unit is used to select the memory element corresponding to the computing unit; for any computing unit of the i-th processing stage, when both input ends of the computing unit are connected to the selection unit, one selection unit corresponding to the computing unit is used to select the numerical value corresponding to the thread corresponding to the computing unit, and the other selection unit corresponding to the computing unit is used to select the memory element corresponding to the computing unit.

[0130] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. Its specific implementation and technical effects can refer to the description of the above method embodiments. For the sake of brevity, they will not be repeated here.

[0131] The present disclosure also provides a computer-readable storage medium having computer program instructions stored thereon, wherein the computer program instructions, when executed by a processor, implement the above method. The computer-readable storage medium may be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium.

[0132] The embodiment of the present disclosure further provides a computer program, comprising a computer-readable code. When the computer-readable code is executed in an electronic device, a processor in the electronic device executes the above method.

[0133] An embodiment of the present disclosure further provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in an electronic device, a processor in the electronic device executes the above method.

[0134] An embodiment of the present disclosure also provides an electronic device, comprising: one or more processors; a memory for storing executable instructions; wherein the one or more processors are configured to call the executable instructions stored in the memory to execute the above method.

[0135] The electronic device can be provided as a terminal, a server or other form of device. Figure 17 shows a block diagram of an electronic device 1900 provided in an embodiment of the present disclosure. For example, the electronic device 1900 can be provided as a server. Referring to Figure 17, the electronic device 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions that can be executed by the processing component 1922, such as an application. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above method. The electronic device 1900 may also include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output interface 1958 (I / O interface). The electronic device 1900 can operate based on an operating system stored in the memory 1932, such as Microsoft's server operating system (Windows Server™), Apple's graphical user interface-based operating system (Mac OS X™), a multi-user multi-process computer operating system (Unix™), a free and open source Unix-like operating system (Linux™), an open source Unix-like operating system (FreeBSD™), or the like.

[0136] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by the processing component 1922 of the electronic device 1900 to perform the above method.

[0137] The present disclosure may be a system, method and / or computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0138] A computer-readable storage medium can be a tangible device that can hold and store instructions for use by an instruction execution device. A computer-readable storage medium can be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination thereof. As used herein, a computer-readable storage medium is not to be construed as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through an electrical wire.

[0139] The computer-readable program instructions described herein can be downloaded to each computing / processing device from a computer-readable storage medium, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device. The computer program instructions for performing the disclosed operation can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, and conventional procedural programming languages ​​such as "C" language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer, partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be personalized using the state information of the computer-readable program instructions, which may execute the computer-readable program instructions to implement various aspects of the present disclosure.

[0140] Here, various aspects of the present disclosure are described with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each block of the flowchart and / or block diagram and the combination of the blocks in the flowchart and / or block diagram can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer or other programmable data processing device, thereby producing a machine so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device for implementing the function / action specified in one or more blocks in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, which enables the computer, programmable data processing device and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes an article of manufacture, which includes instructions for implementing various aspects of the function / action specified in one or more blocks in the flowchart and / or block diagram. Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0141] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems, methods and computer program products according to multiple embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and the part of the module, program segment or instruction contains one or more executable instructions for realizing the prescribed logical function. In some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the prescribed function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0142] The computer program product may be implemented in hardware, software, or a combination thereof. In one embodiment, the computer program product is implemented as a computer storage medium. In another embodiment, the computer program product is implemented as a software product, such as a software development kit (SDK).

[0143] The above description of the various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced with each other and will not be repeated herein for the sake of brevity.

[0144] If the technical solutions of the embodiments of the present disclosure involve personal information, products implementing the technical solutions of the embodiments of the present disclosure must clearly inform individuals of the personal information processing rules and obtain their voluntary consent before processing personal information. If the technical solutions of the embodiments of the present disclosure involve sensitive personal information, products implementing the technical solutions of the embodiments of the present disclosure must obtain the individual's separate consent before processing sensitive personal information, and must also meet the "explicit consent" requirement. For example, a clear and prominent sign can be provided on a personal information collection device, such as a camera, to inform individuals that they have entered the personal information collection area and that their personal information will be collected. If individuals voluntarily enter the collection area, they are deemed to have consented to the collection of their personal information. Alternatively, if the personal information processing device uses a prominent sign / information to inform individuals of the personal information processing rules, authorization can be obtained through a pop-up message or by requesting individuals to upload their personal information. The personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the type of personal information processed. The above description of various embodiments of the present disclosure is illustrative and not exhaustive, and is not intended to limit the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used in this document are selected to best explain the principles of the embodiments, practical applications or technical improvements in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. Industrial Applicability

[0145] In an embodiment of the present disclosure, in response to at least three threads performing atomic operations of the same target type on the same target element in the memory, and the atomic operations of the target type conform to the associative law, in a first processing stage, the original value of the target element and at least three numerical values ​​corresponding to the at least three threads are grouped, and the atomic operations of the target type are performed on each group in parallel to obtain the input value of the second processing stage, and based on the input value of the second processing stage, the final atomic operation results corresponding to the at least three threads are obtained. Therefore, when at least three threads perform atomic operations of the same target type on the same target element in the memory and the atomic operations of the target type conform to the associative law, the system throughput can be improved and the program execution speed can be improved by grouping and performing the atomic operations of each group in parallel.

Claims

1. A method for processing an atomic operation, comprising: In response to at least three threads performing an atomic operation of the same target type on the same target element in the memory, and the atomic operation of the target type complies with the associative law, in a first processing stage, the original value of the target element and at least three values ​​corresponding to the at least three threads are grouped, and the atomic operation of the target type is performed on each group in parallel to obtain an input value for a second processing stage; According to the input value of the second processing stage, the final atomic operation results corresponding to the at least three threads are obtained.

2. The method according to claim 1, wherein obtaining the final atomic operation results corresponding to the at least three threads according to the input values ​​of the second processing stage comprises: In response to the number of input values ​​of the i-th processing stage being greater than or equal to 3, grouping the input values ​​of the i-th processing stage, and performing the atomic operation of the target type on each group in parallel to obtain input values ​​of the i+1-th processing stage, where i is an integer greater than or equal to 2; In response to the number of input values ​​of the i-th processing stage being 2, performing an atomic operation of the target type on the two input values ​​of the i-th processing stage to obtain final atomic operation results corresponding to the at least three threads, where i is an integer greater than or equal to 2.

3. According to the method of claim 1 or 2, in response to the number of input values ​​of any processing stage being greater than or equal to 3, and the number of input values ​​of the processing stage being an even number, the input values ​​of the processing stage are grouped in pairs; or, in response to the number of input values ​​of any processing stage being greater than or equal to 3, and the number of input values ​​of the processing stage being an odd number, one of the input values ​​of the processing stage is used as the input value of the next processing stage of the processing stage, and the other input values ​​of the processing stage are grouped in pairs.

4. According to the method described in any one of claims 1 to 3, the atomic operation of the target type is any one of the following operations: an atomic addition operation, an atomic replacement operation, an atomic AND operation, an atomic OR operation, and an atomic XOR operation.

5. The method according to any one of claims 1 to 4, wherein in response to at least three threads performing an atomic operation of the same target type on the same target element in the memory, and the atomic operation of the target type complies with the associative law, in a first processing stage, before grouping the original value of the target element and the at least three values ​​corresponding to the at least three threads, the method further comprises: In response to at least three threads performing an atomic subtraction operation on a same target element in a memory, at least three values ​​corresponding to the at least three threads are respectively negated, and the atomic subtraction operation is converted into an atomic addition operation.

6. The method according to any one of claims 1 to 5, wherein in the first processing stage, the original value of the target element and the at least three values ​​corresponding to the at least three threads are grouped, and the atomic operation of the target type is performed on each group in parallel to obtain the input value of the second processing stage, comprising: In the first processing stage, the original value of the target element and the at least three values ​​corresponding to the at least three threads are divided into groups, and through The computing units perform the The groups perform the atomic operation of the target type to obtain the input value of the second processing stage, where T represents the number of threads that perform the atomic operation of the same target type on the same target element in the memory, Indicates rounding down.

7. The method according to claim 6, wherein obtaining the final atomic operation results corresponding to the at least three threads according to the input values ​​of the second processing stage comprises: In response to the number of input values ​​of the i-th processing stage being greater than or equal to 3, dividing the input values ​​of the i-th processing stage into groups, and through The computing units perform the groups to perform the atomic operation of the target type to obtain the input value of the i+1th processing stage, where i is an integer greater than or equal to 2, and N represents the number of input values ​​of the i-th processing stage; In response to the number of input values ​​of the i-th processing stage being 2, an atomic operation of the target type is performed on the two input values ​​of the i-th processing stage by a computing unit to obtain final atomic operation results corresponding to the at least three threads, where i is an integer greater than or equal to 2.

8. The method of claim 7, wherein T threads are processed by a computing architecture comprising T computing units, wherein: Any computing unit of the T computing units includes two input terminals and one output terminal, and the T computing units correspond to different threads of the T threads respectively; The two input ends of a computing unit in the first processing stage respectively input the original value of the memory element corresponding to the computing unit and the numerical value corresponding to the thread corresponding to the computing unit, wherein the original value of the memory element corresponding to the computing unit represents the memory element on which the thread corresponding to the computing unit performs an atomic operation; For any other computing unit in the first processing stage, one input end of the computing unit inputs the numerical value corresponding to the thread corresponding to the computing unit, and the other input end is connected to the selection unit corresponding to the computing unit, and the selection unit is used to select one item from the original value of the memory element corresponding to the computing unit and the input factor corresponding to the computing unit, wherein the input factor corresponding to any computing unit is the numerical value corresponding to the thread corresponding to any computing unit other than the computing unit in the first processing stage, and the input factors corresponding to different computing units are different.

9. The method according to claim 8, wherein the output end of the computing unit in the non-last processing stage is connected to the input end of the selection unit corresponding to the computing unit in the subsequent processing stage, the output end of each computing unit in the non-last processing stage is respectively connected to the input end of only a single selection unit, and the output ends of different computing units are connected to different selection units; For any computing unit of the i-th processing stage, when a numerical value corresponding to a thread corresponding to the computing unit is inputted at one input end of the computing unit, another input end of the computing unit is connected to a selection unit corresponding to the computing unit, and the selection unit is used to select one item from a memory element corresponding to the computing unit and an output of a computing unit of a previous processing stage; wherein, Among the computing units other than the first processing stage, at most one computing unit has an input terminal inputting a value corresponding to a thread corresponding to the computing unit, and another input terminal of the computing unit and two input terminals of other computing units are connected to the selection unit; For any computing unit of the i-th processing stage, when both input ends of the computing unit are connected to the selection unit, one selection unit corresponding to the computing unit is used to select one item from the numerical value corresponding to the thread corresponding to the computing unit and the output of the computing unit of the previous processing stage, and the other selection unit corresponding to the computing unit is used to select one item from the memory element corresponding to the computing unit and the output of the computing unit of the previous processing stage, where i is an integer greater than or equal to 2.

10. The method according to claim 9, When the T threads perform an atomic operation of the same target type on the same target element in the memory, the selection unit of the first processing stage is used to select an input factor corresponding to the computing unit, and each selection unit other than the first processing stage is used to select an output of a computing unit of a previous processing stage; In the case where the T threads perform atomic operations on different elements in the memory, the selection unit of the first processing stage is used to select the memory element corresponding to the computing unit; for any computing unit of the i-th processing stage, when only one input end of the computing unit is connected to the selection unit, the selection unit corresponding to the computing unit is used to select the memory element corresponding to the computing unit; for any computing unit of the i-th processing stage, when both input ends of the computing unit are connected to the selection unit, one selection unit corresponding to the computing unit is used to select the numerical value corresponding to the thread corresponding to the computing unit, and the other selection unit corresponding to the computing unit is used to select the memory element corresponding to the computing unit.

11. A processing device for atomic operations, comprising: A first processing module is configured to, in response to at least three threads performing an atomic operation of the same target type on the same target element in the memory, and the atomic operation of the target type complies with the associative law, group the original value of the target element and the at least three values ​​corresponding to the at least three threads in a first processing stage, and perform the atomic operation of the target type on each group in parallel to obtain an input value for a second processing stage; The second processing module is configured to obtain final atomic operation results corresponding to the at least three threads according to the input value of the second processing stage.

12. An electronic device comprising: one or more processors; A memory for storing executable instructions; wherein the one or more processors are configured to call the executable instructions stored in the memory to execute the method according to any one of claims 1 to 10.

13. A computer-readable storage medium having computer program instructions stored thereon, wherein the computer program instructions, when executed by a processor, implement the method according to any one of claims 1 to 10.

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