Pixel driving circuit and display panel

Abstract

A pixel driving circuit and a display panel. The pixel driving circuit comprises a threshold voltage extraction module electrically connected to a driving transistor and a first voltage end, and a data writing module electrically connected to a control end of the driving transistor. The first voltage end is used to extract a threshold voltage of the driving transistor, and a data signal is coupled to the control end of the driving transistor by means of the data writing module, so that the capturing of the threshold voltage of the driving transistor is separated from the writing of the data signal.

Description

Pixel driving circuit and display panel Technical Field

[0001] The present application relates to the field of display technology, and in particular to a pixel driving circuit and a display panel. Background Art

[0002] As shown in Figure 1, an existing pixel driver circuit employs a compensation transistor between the control and input terminals of a driver transistor. When the compensation transistor is turned on, the driver transistor is connected in a diode configuration, compensating for the driver transistor's threshold voltage. However, due to the slow speed at which data signals are written to the driver transistor, transmission losses of the voltage VDD applied by multiple pixel driver circuits occur during transmission, and differences in driver transistors due to manufacturing processes, the gate-source voltage differences of the driver transistors in multiple pixel driver circuits can also vary. This results in poor adaptability of display panels using high-frequency drive methods, resulting in excessively high dark-state voltage and uneven low-grayscale display. SUMMARY OF THE INVENTION

[0003] Embodiments of the present application provide a pixel driving circuit and a display panel, which can improve the problems of low grayscale display unevenness and excessively high dark-state voltage in a display panel using the pixel driving circuit.

[0004] An embodiment of the present application provides a pixel driving circuit, comprising a light-emitting device, a driving transistor, a threshold voltage extraction module, and a data writing module. The light-emitting device is electrically connected between a first voltage terminal and a second voltage terminal; the control terminal of the driving transistor is electrically connected to a first node, the input terminal of the driving transistor is electrically connected to the first voltage terminal via a second node, and the output terminal of the driving transistor is electrically connected to the light-emitting device via a third node; the threshold voltage extraction module is electrically connected to the driving transistor and the first voltage terminal, and extracts the threshold voltage of the driving transistor from a first voltage transmitted from the first voltage terminal; the data writing module is electrically connected to the first node and a data line, and couples a data signal transmitted by the data line to the first node according to a data writing control signal.

[0005] An embodiment of the present application further provides a display panel, which includes a plurality of sub-pixels, and each of the sub-pixels includes any of the above-mentioned pixel driving circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIG1 is a schematic structural diagram of an existing pixel driving circuit;

[0007] 2A to 2C are schematic structural diagrams of a pixel driving circuit provided in an embodiment of the present application;

[0008] 3A to 3C are timing diagrams of corresponding pixel driving circuits provided in an embodiment of the present application;

[0009] FIG4 is a schematic structural diagram of a display panel provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0010] To make the purpose, technical solutions and effects of this application clearer and more specific, the following further describes this application in detail with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are only used to explain this application and are not intended to limit this application.

[0011] Optionally, in some embodiments of the present application, the threshold voltage extraction module includes a first compensation transistor, a second compensation transistor, and a first capacitor. The control terminal of the first compensation transistor is electrically connected to the first gate control line, the input terminal of the first compensation transistor is electrically connected to the first voltage terminal, and the output terminal of the first compensation transistor is electrically connected to the second node; the control terminal of the second compensation transistor is electrically connected to the second gate control line, the input terminal of the second compensation transistor is electrically connected to the third node, and the output terminal of the second compensation transistor is electrically connected to the first node; and the first capacitor is connected in series between the first voltage terminal and the first node.

[0012] Optionally, in some embodiments of the present application, the data writing module includes a data transistor and a second capacitor. The control terminal of the data transistor is electrically connected to the third gate control line, and the input terminal of the data transistor is electrically connected to the data line; the second capacitor is connected in series between the output terminal of the data transistor and the first node.

[0013] Optionally, in some embodiments of the present application, the pixel driving circuit further includes a first reset module, which is electrically connected to the first node and the output end of the data transistor, and the first reset module resets the first node and the output end of the data transistor through a first reset signal.

[0014] Optionally, in some embodiments of the present application, the first reset module includes a first reset transistor and a second reset transistor. The control terminal of the first reset transistor is electrically connected to the fourth gate control line, the input terminal of the first reset transistor is electrically connected to the first reset line that transmits the first reset signal, and the output terminal of the first reset transistor is electrically connected to the first node; the control terminal of the second reset transistor is electrically connected to the fourth gate control line, the input terminal of the second reset transistor is electrically connected to the first node, and the output terminal of the first reset transistor is electrically connected to the output terminal of the data transistor.

[0015] Optionally, in some embodiments of the present application, the first reset transistor and the second reset transistor include oxide transistors.

[0016] Optionally, in some embodiments of the present application, the pixel driving circuit further includes a switch control module, the switch control module includes a switch transistor, the control end of the switch transistor is electrically connected to the light-emitting control line, the input end of the switch transistor is electrically connected to the third node, and the output end of the switch transistor is electrically connected to the light-emitting device.

[0017] Optionally, in some embodiments of the present application, the pixel driving circuit further includes a second reset module, the second reset module includes a third reset transistor, the control end of the third reset transistor is electrically connected to the reset control line, the input end of the third reset transistor is electrically connected to the second reset line, and the output end of the third reset transistor is electrically connected to the light-emitting device.

[0018] Optionally, in some embodiments of the present application, the pixel driving circuit further includes a third reset module, the third reset module includes a fourth reset transistor, the control end of the fourth reset transistor is electrically connected to the reset control line, the input end of the fourth reset transistor is electrically connected to the third reset line, and the output end of the fourth reset transistor is electrically connected to the second node.

[0019] The present application provides a pixel driving circuit and a display panel. The pixel driving circuit includes a light-emitting device, a driving transistor, a threshold voltage extraction module, and a data writing module. The driving transistor and the light-emitting device are electrically connected between a first voltage terminal and a second voltage terminal. The threshold voltage extraction module is electrically connected to the driving transistor and the first voltage terminal. The data writing module is electrically connected to the control terminal of the driving transistor. The threshold voltage of the driving transistor is extracted using a first voltage transmitted from the first voltage terminal. A data signal is coupled to the control terminal of the driving transistor via the data writing module. This allows the capture of the threshold voltage of the driving transistor to be separated from the writing of the data signal, thereby increasing the speed at which the data signal is written to the control terminal of the driving transistor and extending the time for extracting the threshold voltage of the driving transistor. This allows a display panel using the pixel driving circuit to achieve a difference in potential at the control terminal of the driving transistor included in each sub-pixel according to the position of the sub-pixel when extracting the threshold voltage of the driving transistor. This allows the gate-source voltage difference of the driving transistors of multiple sub-pixels to be consistent when controlling the light-emitting device to emit light, thereby improving the problems of uneven low-grayscale display and excessively high dark-state voltage.

[0020] Specifically, Figures 2A to 2C are structural schematic diagrams of a pixel driving circuit provided in an embodiment of the present application. An embodiment of the present application provides a pixel driving circuit, which includes a light-emitting module, a driving module, a threshold voltage extraction module, and a data writing module.

[0021] The light emitting module includes a light emitting device Le, and the light emitting device Le is electrically connected between a first voltage terminal VDD and a second voltage terminal VSS.

[0022] Optionally, the anode of the light emitting device Le is electrically connected to the first voltage terminal VDD, and the cathode of the light emitting device Le is electrically connected to the second voltage terminal VSS, wherein a first voltage supplied by the first voltage terminal VDD is greater than a second voltage supplied by the second voltage terminal VSS.

[0023] Optionally, the light emitting device Le includes an organic light emitting diode, a sub-millimeter light emitting diode, a micro light emitting diode, etc. Optionally, the light emitting device Le can be used as a backlight source or a display pixel.

[0024] The driving module is electrically connected to the light emitting device Le, and is configured to generate a driving current to drive the light emitting device Le to emit light.

[0025] Optionally, the driving module includes a driving transistor Tdr, the control end of the driving transistor Tdr is electrically connected to the first node N1, the input end of the driving transistor Tdr is electrically connected to the first voltage end VDD through the second node N2, and the output end of the driving transistor Tdr is electrically connected to the light-emitting device Le through the third node N3.

[0026] Optionally, the driving module includes a silicon transistor, an oxide transistor, etc. Optionally, the driving module includes a P-type transistor or an N-type transistor.

[0027] 2A to 2C , the threshold voltage extraction module is electrically connected to the driving transistor Tdr and the first voltage terminal VDD, and the threshold voltage extraction module extracts the threshold voltage of the driving transistor Tdr through the first voltage.

[0028] Optionally, the threshold voltage extraction module includes a first compensation transistor Tc1, a second compensation transistor Tc2 and a first capacitor C1.

[0029] The control end of the first compensation transistor Tc1 is electrically connected to the first gate control line SL1, the input end of the first compensation transistor Tc1 is electrically connected to the first voltage end VDD, and the output end of the first compensation transistor Tc1 is electrically connected to the second node N2; the first compensation transistor Tc1 is configured to transmit the first voltage to the second node N2 according to the composite control signal Mc transmitted by the first gate control line SL1.

[0030] The control terminal of the second compensation transistor Tc2 is electrically connected to the second gate control line SL2, the input terminal of the second compensation transistor Tc2 is electrically connected to the third node N3, and the output terminal of the second compensation transistor Tc2 is electrically connected to the first node N1. When the first compensation transistor Tc1 transmits the first voltage to the second node N2 according to the composite control signal Mc, the second compensation transistor Tc2 is configured to transmit the first voltage to the first node N1 according to the first gate control signal Scan11 transmitted from the second gate control line SL2.

[0031] The first capacitor C1 is connected in series between the first voltage terminal VDD and the first node N1. When the second compensation transistor Tc2 transmits the first voltage to the first node N1, the first capacitor C1 is configured to store the threshold voltage of the driving transistor Tdr to extract the threshold voltage of the driving transistor Tdr.

[0032] Optionally, the first compensation transistor Tc1 and the second compensation transistor Tc2 include silicon transistors, oxide transistors, etc. Optionally, the first compensation transistor Tc1 and the second compensation transistor Tc2 include P-type transistors or N-type transistors.

[0033] When the pixel driving circuit is applied to a display panel, since the first voltage terminal VDD simultaneously provides the first voltage to multiple sub-pixels included in the display panel, the pixel driving circuit included in each sub-pixel will receive different values ​​of the first voltage depending on its position (that is, the voltage value corresponding to the first voltage received by the pixel driving circuit included in the sub-pixel close to the first voltage terminal VDD is large, and therefore, the first voltage transmitted to the first node N1 in the pixel driving circuit included in the sub-pixel close to the first voltage terminal VDD also has a large voltage value; due to the loss of the first voltage during transmission, the voltage value corresponding to the first voltage received by the pixel driving circuit included in the sub-pixel far from the first voltage terminal VDD is small, and therefore, the first voltage transmitted to the first node N1 in the pixel driving circuit included in the sub-pixel far from the first voltage terminal VDD also has a small voltage value), and the potential at the first node N1 of the pixel driving circuit included in the sub-pixel at different positions will be different. When the driving transistor Tdr drives the light-emitting device Le to emit light, the driving current generated by the driving transistor Tdr flows from the first voltage terminal VDD to the second voltage terminal VSS. In addition, the first voltages received by the sub-pixels at different positions are different. Therefore, the potentials at the first node N1 in the pixel driving circuit included in the sub-pixels at different positions obtained based on the different first voltages received by the sub-pixels at different positions are also different. Therefore, when the driving transistor Tdr drives the light-emitting device Le to emit light, the gate-source voltage difference of the driving transistors Tdr included in the multiple sub-pixels (i.e., the voltage difference between the first node N1 and the second node N2) tends to be consistent or equal. Therefore, the brightness of the light-emitting device Le driven to emit light in the multiple pixel driving circuits tends to be consistent or equal, so that the brightness difference of the display screen is reduced, thereby improving the problem of high-brightness display unevenness caused by the voltage drop caused by the first voltage affected by factors such as transmission loss.

[0034] In the prior art, the threshold voltage of the driving transistor Tdr is extracted using the data transistor Tda and the compensation transistor Tc. However, when the data signal is transmitted to the control terminal of the driving transistor Tdr via the data transistor Tda and the compensation transistor Tc, the degree of conduction of the driving transistor Tdr varies depending on the magnitude of the data signal written to the control terminal of the driving transistor Tdr. Therefore, when the conduction degree of the driving transistor Tdr is insufficient, the data signal is written to the control terminal of the driving transistor Tdr slowly. When the driving transistor Tdr is fully conductive, the data signal is written to the control terminal of the driving transistor Tdr quickly. During the scan time corresponding to each row, the pixel driving circuit often needs to go through a reset phase, a data writing phase, and a light-emitting phase. Therefore, during the scan time corresponding to each row, the time available for the data transistor Tda and the compensation transistor Tc to be simultaneously turned on to achieve the threshold voltage extraction of the driving transistor Tdr is limited. The slow speed of writing the data signal to the control terminal of the driving transistor Tdr further affects the effect of the data signal being transmitted to the control terminal of the driving transistor Tdr, resulting in the threshold voltage of the driving transistor Tdr not being accurately extracted, and then resulting in the threshold voltage of the driving transistor Tdr not being accurately compensated, causing the problem of uneven luminous brightness. In particular, when the display panel adopts the existing pixel driving circuit design, the scan time corresponding to each row is shorter when the display panel adopts high-frequency drive. Accordingly, the accuracy of extracting the threshold voltage of the driving transistor Tdr will be further reduced, resulting in the problem of uneven display on the display panel. Furthermore, since the voltage value corresponding to the data signal used for the low grayscale display screen is higher than the voltage value corresponding to the data signal used for the high grayscale display screen, for a display panel using the existing pixel driving circuit design and in which the driving transistor Tdr is a P-type transistor, when extracting the threshold voltage of the driving transistor Tdr, the data signal corresponding to the low grayscale display screen is transmitted to the control end of the driving transistor Tdr, which causes the conduction degree of the driving transistor Tdr to be lower than the conduction degree of the driving transistor Tdr caused by the data signal corresponding to the high grayscale display screen being transmitted to the control end of the driving transistor Tdr. Therefore, the accuracy of extracting the threshold voltage of the driving transistor Tdr corresponding to the low grayscale display screen will be lower than the accuracy of extracting the threshold voltage of the driving transistor Tdr corresponding to the high grayscale display screen, resulting in the problem of uneven low grayscale display screen being more obvious than the problem of uneven high grayscale display screen.

[0035] The high frequency may be that the display panel uses a frequency greater than or equal to 120 Hz for display.

[0036] In the present application, when the pixel driving circuit is applied to a display panel, since the first voltage terminal VDD simultaneously provides the first voltage to multiple sub-pixels included in the display panel, regardless of whether it is a high grayscale display screen or a low grayscale display screen, the voltage transmitted to the control terminal of the driving transistor Tdr included in the multiple sub-pixels is also the first voltage. Therefore, when the threshold voltage of the driving transistor Tdr is extracted, the conduction degree of the driving transistor Tdr corresponding to the low grayscale display screen is the same as the conduction degree corresponding to the high grayscale display screen. When extracting the threshold voltage of the driving transistor Tdr, in addition to being electrically connected to the control terminal of the driving transistor Tdr via the first compensation transistor Tc1 and the second compensation transistor Tc2, the first voltage terminal VDD is also electrically connected to the control terminal of the driving transistor Tdr via the first capacitor C1. Therefore, the driving transistor Tdr can be fully turned on in a timely manner under the action of the first voltage, so that the charging time of the first capacitor C1 is prolonged, thereby allowing the potential of the first node N1 to be charged to a more ideal potential, thereby improving the accuracy of the extracted threshold voltage of the driving transistor Tdr.

[0037] Optionally, when the pixel driving circuit is applied to a display panel, since the first voltage terminal VDD simultaneously provides the first voltage to multiple sub-pixels included in the display panel, the extraction of the threshold voltage of the driving transistor Tdr can be achieved without being limited to the scanning time of one row, so that the charging time of the first capacitor C1 is further prolonged, so as to further improve the accuracy of the extracted threshold voltage of the driving transistor Tdr.

[0038] 2A to 2C , the data writing module is electrically connected to the first node N1 and the data line DL. The data writing module couples the data signal transmitted by the data line DL to the first node N1 according to the data writing control signal Scan2 .

[0039] Optionally, the data writing module includes a data transistor Tda and a second capacitor C2.

[0040] The control end of the data transistor Tda is electrically connected to the third gate control line SL3, and the input end of the data transistor Tda is electrically connected to the data line DL; the second capacitor C2 is connected in series between the output end of the data transistor Tda and the first node N1, and the data transistor Tda transmits the data signal to the output end of the data transistor Tda according to the data write control signal Scan2 transmitted by the third gate control line SL3, so as to couple the data signal to the first node N1 through the second capacitor C2.

[0041] Optionally, the data transistor Tda includes a silicon transistor, an oxide transistor, etc. Optionally, the data transistor Tda includes a P-type transistor or an N-type transistor.

[0042] Since in the existing pixel driving circuit, the driving transistor Tdr is connected in a diode-type manner when the data signal is written, the data signal writing speed is slow. In the present application, the data signal can be directly coupled to the first node N1 through the data transistor Tda and the second capacitor C2, and the charging speed of the second capacitor C2 is faster. Therefore, the data signal writing speed of the present application is faster. Therefore, the voltage value corresponding to the data signal used in the present application can also be set to be smaller than the voltage value corresponding to the data signal used in the existing pixel driving circuit, which can meet the use requirements. Therefore, the present application can improve the problem of excessive dark state voltage of the display panel using the pixel driving circuit. In addition, since the data signal writing speed of the present application is faster, the extraction of the threshold voltage of the driving transistor Tdr and the writing of the data signal are divided into two stages, which will not have a significant impact on the duration of the display control timing.

[0043] Optionally, please continue to refer to Figures 2A to 2C. The pixel driving circuit also includes a first reset module, which is electrically connected to the first node N1 and the output end of the data transistor Tda. The first reset module resets the first node N1 and the output end of the data transistor Tda through a first reset signal.

[0044] Optionally, the first reset module includes a first reset transistor Ti1 and a second reset transistor Ti2.

[0045] A control terminal of the first reset transistor Ti1 is electrically connected to a fourth gate control line SL4, an input terminal of the first reset transistor Ti1 is electrically connected to a first reset line VL1 that transmits the first reset signal, and an output terminal of the first reset transistor Ti1 is electrically connected to the first node N1. The first reset transistor Ti1 transmits the first reset signal to the first node N1 in response to a second gate control signal Scan12 transmitted by the fourth gate control line SL4, thereby resetting the potential of the first node N1.

[0046] The control terminal of the second reset transistor Ti2 is electrically connected to the fourth gate control line SL4, the input terminal of the second reset transistor Ti2 is electrically connected to the first node N1, and the output terminal of the second reset transistor Ti2 is electrically connected to the output terminal of the data transistor Tda. The second reset transistor Ti2 transmits the first reset signal to the output terminal of the data transistor Tda in response to the second gate control signal Scan12, thereby resetting the second capacitor C2 while resetting the potential of the first node N1.

[0047] Optionally, in a display panel using the pixel driving circuit, the fourth gate control line SL4 and the second gate control line SL2 can be electrically connected to gate driving circuits of different levels in the same gate driving unit to reduce the number of gate driving units used in the display panel and reduce the border width of the display panel.

[0048] Optionally, the first reset transistor Ti1 and the second reset transistor Ti2 include silicon transistors, oxide transistors, etc.

[0049] Optionally, referring to FIG. 2C , the first reset transistor Ti1 and the second reset transistor Ti2 comprise oxide transistors to reduce leakage current from the first node N1 to the first reset line VL1 when the driving transistor Tdr drives the light-emitting device Le to emit light, thereby maintaining the light emission stability of the light-emitting device Le. Optionally, the second compensation transistor Tc2 is an oxide transistor.

[0050] Optionally, please continue to refer to Figures 2A to 2C. To prevent the light-emitting device Le from emitting light by mistake, the pixel driving circuit further includes a switch control module, which controls the timing of the light-emitting device Le to emit light in accordance with the light-emitting control signal EM in cooperation with the first compensation transistor Tc1.

[0051] Optionally, the switch control module includes a switching transistor Ts, the control end of the switching transistor Ts is electrically connected to the light-emitting control line EML, the input end of the switching transistor Ts is electrically connected to the third node N3, and the output end of the switching transistor Ts is electrically connected to the light-emitting device Le. The switching transistor Ts cooperates with the first compensation transistor Tc1 to control the light-emitting moment of the light-emitting device Le according to the light-emitting control signal EM transmitted by the light-emitting control line EML.

[0052] Optionally, please continue to refer to Figures 2A to 2C. In order to further improve the display difference, the pixel driving circuit also includes a second reset module, which transmits a second reset signal to the anode of the light-emitting device Le according to the reset control signal SN transmitted by the reset control line SNL to reset the anode potential of the light-emitting device Le.

[0053] Optionally, the second reset module includes a third reset transistor Ti3, the control end of the third reset transistor Ti3 is electrically connected to the reset control line SNL, the input end of the third reset transistor Ti3 is electrically connected to the second reset line VL2, and the output end of the third reset transistor Ti3 is electrically connected to the light-emitting device Le.

[0054] Optionally, the reset control signal SN transmitted by the reset control line SNL may be the same as the signal transmitted by the second gate control line SL2 (i.e., the control end of the third reset transistor Ti3 may be electrically connected to the second gate control line SL2, as shown in FIG2A ), so as to achieve resetting of the anode of the light-emitting device Le while extracting the threshold voltage of the driving transistor Tdr.

[0055] Optionally, please continue to refer to Figures 2B to 2C. To further improve the display difference, the pixel driving circuit also includes a third reset module, which transmits a third reset signal to the second node N2 according to the reset control signal SN transmitted by the reset control line SNL to reset the potential of the second node N2.

[0056] Optionally, the third reset module includes a fourth reset transistor Ti4, the control end of the fourth reset transistor Ti4 is electrically connected to the reset control line SNL, the input end of the fourth reset transistor Ti4 is electrically connected to the third reset line VL3, and the output end of the fourth reset transistor Ti4 is electrically connected to the second node N2.

[0057] Figures 3A to 3C are timing diagrams of corresponding pixel driving circuits provided in embodiments of the present application. Figure 3A is a timing diagram corresponding to the pixel driving circuit shown in Figure 2A , Figure 3B is a timing diagram corresponding to the pixel driving circuit shown in Figure 2B , and Figure 3C is a timing diagram corresponding to the pixel driving circuit shown in Figure 2C .

[0058] Taking the pixel driving circuits in Figures 2A and 2B as P-type transistors, the pixel driving circuit in Figure 2C as N-type transistors, the first reset transistor Ti1, the second reset transistor Ti2, and the second compensation transistor Tc2 as N-type transistors, and the remaining transistors as P-type transistors as an example, the working principles of the pixel driving circuits shown in Figures 2A to 2C are explained.

[0059] Phase 1 t1: the composite control signal Mc transmitted by the first gate control line SL1 is in an invalid level state (i.e., the composite control signal Mc in Figures 3A to 3C is a high level), the first gate control signal Scan11 transmitted by the second gate control line SL2 is in an invalid level state (i.e., the first gate control signal Scan11 in Figures 3A to 3B is a high level, and the first gate control signal Scan11 in Figure 3C is a low level), the data write control signal Scan2 transmitted by the third gate control line SL3 is in an invalid level state (i.e., the data write control signal Scan2 in Figures 3A to 3C is a high level), the second gate control signal Scan12 transmitted by the fourth gate control line SL4 is in an invalid level state (i.e., the second gate control signal Scan12 in Figures 3A to 3B is a high level, and the second gate control signal Scan12 in Figure 3C is a low level), and the light-emitting control signal EM transmitted by the light-emitting control line EML is in an invalid level state (i.e., the light-emitting control signal EM in Figures 3A to 3C is a high level). The reset control signal SN transmitted by the reset control line SNL is in an invalid level state (ie, the reset control signal SN in FIG. 3B to FIG. 3C is at a high level).

[0060] The first compensation transistor Tc1 is turned off according to the composite control signal Mc, the second compensation transistor Tc2 is turned off according to the first gate control signal Scan11, the data transistor Tda is turned off according to the data write control signal Scan2, the first reset transistor Ti1 and the second reset transistor Ti2 are turned off according to the second gate control signal Scan12, the switch transistor Ts is turned off according to the light-emitting control signal EM, and the light-emitting device Le stops emitting light. In the pixel driving circuit shown in Figure 2A, the third reset transistor Ti3 is turned off according to the first gate control signal Scan11; in the pixel driving circuits shown in Figures 2B and 2C, the third reset transistor Ti3 and the fourth reset transistor Ti4 are turned off according to the reset control signal SN.

[0061] Second stage t2: the composite control signal Mc transmitted by the first gate control line SL1 is in an invalid level state (i.e., the composite control signal Mc in Figures 3A to 3C is a high level), the first gate control signal Scan11 transmitted by the second gate control line SL2 is in an invalid level state (i.e., the first gate control signal Scan11 in Figures 3A to 3B is a high level, and the first gate control signal Scan11 in Figure 3C is a low level), the data write control signal Scan2 transmitted by the third gate control line SL3 is in an invalid level state (i.e., the data write control signal Scan2 in Figures 3A to 3C is a high level), the second gate control signal Scan12 transmitted by the fourth gate control line SL4 is in an invalid level state (i.e., the second gate control signal Scan12 in Figures 3A to 3B is a high level, and the second gate control signal Scan12 in Figure 3C is a low level), and the light-emitting control signal EM transmitted by the light-emitting control line EML is in an invalid level state (i.e., the light-emitting control signal EM in Figures 3A to 3C is a high level). The reset control signal SN transmitted by the reset control line SNL is in an active level state (ie, the reset control signal SN in FIG. 3B to FIG. 3C is at a low level).

[0062] The first compensation transistor Tc1 is turned off in response to the composite control signal Mc, the second compensation transistor Tc2 is turned off in response to the first gate control signal Scan11, the data transistor Tda is turned off in response to the data write control signal Scan2, the first reset transistor Ti1 and the second reset transistor Ti2 are turned off in response to the second gate control signal Scan12, and the switch transistor Ts is turned off in response to the light-emitting control signal EM. In the pixel driving circuits shown in Figures 2B and 2C, the third reset transistor Ti3 and the fourth reset transistor Ti4 are turned on in response to the reset control signal SN. The second reset signal resets the anode of the light-emitting device Le, and the third reset signal resets the first node N1. In the pixel driving circuit shown in Figure 2A, since the fourth reset transistor Ti4 is not provided, the control terminal of the third reset transistor Ti3 is electrically connected to the second gate control line SL2. Therefore, the pixel driving circuit shown in Figure 2A does not need to perform the second stage t2.

[0063] In the third stage t3, the composite control signal Mc transmitted by the first gate control line SL1 is in an invalid level state (i.e., the composite control signal Mc in Figures 3A to 3C is a high level), the first gate control signal Scan11 transmitted by the second gate control line SL2 is in an invalid level state (i.e., the first gate control signal Scan11 in Figures 3A to 3B is a high level, and the first gate control signal Scan11 in Figure 3C is a low level), the data write control signal Scan2 transmitted by the third gate control line SL3 is in an invalid level state (i.e., the data write control signal Scan2 in Figures 3A to 3C is a high level), the second gate control signal Scan12 transmitted by the fourth gate control line SL4 is in an valid level state (i.e., the second gate control signal Scan12 in Figures 3A to 3B is a low level, and the second gate control signal Scan12 in Figure 3C is a high level), and the light-emitting control signal EM transmitted by the light-emitting control line EML is in an invalid level state (i.e., the light-emitting control signal EM in Figures 3A to 3C is a high level). The reset control signal SN transmitted by the reset control line SNL is in an invalid level state (ie, the reset control signal SN in FIG. 3B to FIG. 3C is at a high level).

[0064] The first compensation transistor Tc1 is turned off in response to the composite control signal Mc, the second compensation transistor Tc2 is turned off in response to the first gate control signal Scan11, and the data transistor Tda is turned off in response to the data write control signal Scan2. The first reset transistor Ti1 and the second reset transistor Ti2 are turned on in response to the second gate control signal Scan12. The first reset signal resets the first node N1, and the first reset signal resets the second capacitor C2. The switching transistor Ts is turned off in response to the emission control signal EM. In the pixel driving circuit shown in FIG2A, the third reset transistor Ti3 is turned off in response to the first gate control signal Scan11. In the pixel driving circuits shown in FIG2B and FIG2C, the third reset transistor Ti3 and the fourth reset transistor Ti4 are turned off in response to the reset control signal SN.

[0065] Fourth stage t4: the composite control signal Mc transmitted by the first gate control line SL1 is in a valid level state (i.e., the composite control signal Mc in Figures 3A to 3C is a low level), the first gate control signal Scan11 transmitted by the second gate control line SL2 is in a valid level state (i.e., the first gate control signal Scan11 in Figures 3A to 3B is a low level, and the first gate control signal Scan11 in Figure 3C is a high level), the data write control signal Scan2 transmitted by the third gate control line SL3 is in an invalid level state (i.e., the data write control signal Scan2 in Figures 3A to 3C is a high level), the second gate control signal Scan12 transmitted by the fourth gate control line SL4 is in an invalid level state (i.e., the second gate control signal Scan12 in Figures 3A to 3B is a high level, and the second gate control signal Scan12 in Figure 3C is a low level), and the light-emitting control signal EM transmitted by the light-emitting control line EML is in an invalid level state (i.e., the light-emitting control signal EM in Figures 3A to 3C is a high level). The reset control signal SN transmitted by the reset control line SNL is in an invalid level state (ie, the reset control signal SN in FIG. 3B to FIG. 3C is at a high level).

[0066] The first compensation transistor Tc1 is turned on in response to the composite control signal Mc, and the second compensation transistor Tc2 is turned on in response to the first gate control signal Scan11. The first voltage is transmitted to the first node N1 via the first compensation transistor Tc1 and the second compensation transistor Tc2 until the potential of the first node N1 reaches the sum of the first voltage and the threshold voltage of the driving transistor Tdr. The first capacitor C1 then stores the threshold voltage of the driving transistor Tdr. The data transistor Tda is turned off in response to the data write control signal Scan2, the first reset transistor Ti1 and the second reset transistor Ti2 are turned off in response to the second gate control signal Scan12, and the switching transistor Ts is turned off in response to the emission control signal EM. In the pixel driving circuit shown in FIG2A , the third reset transistor Ti3 is turned on in response to the first gate control signal Scan11 to reset the anode potential of the light-emitting device Le via the second reset signal. Among them, in the pixel driving circuit shown in Figures 2B to 2C, the third reset transistor Ti3 and the fourth reset transistor Ti4 are turned on in the second stage t2, so that the potential of the second node N2 in the second stage t2 is reset, which is beneficial to improving the accuracy of extracting the threshold voltage of the driving transistor Tdr in the fourth stage t4.

[0067] Fifth stage t5: the composite control signal Mc transmitted by the first gate control line SL1 is in an invalid level state (i.e., the composite control signal Mc in Figures 3A to 3C is a high level), the first gate control signal Scan11 transmitted by the second gate control line SL2 is in an invalid level state (i.e., the first gate control signal Scan11 in Figures 3A to 3B is a high level, and the first gate control signal Scan11 in Figure 3C is a low level), the data write control signal Scan2 transmitted by the third gate control line SL3 is in an effective level state (i.e., the data write control signal Scan2 in Figures 3A to 3C is a low level), the second gate control signal Scan12 transmitted by the fourth gate control line SL4 is in an invalid level state (i.e., the second gate control signal Scan12 in Figures 3A to 3B is a high level, and the second gate control signal Scan12 in Figure 3C is a low level), and the light-emitting control signal EM transmitted by the light-emitting control line EML is in an invalid level state (i.e., the light-emitting control signal EM in Figures 3A to 3C is a high level). The reset control signal SN transmitted by the reset control line SNL is in an invalid level state (ie, the reset control signal SN in FIG. 3B to FIG. 3C is at a high level).

[0068] The first compensation transistor Tc1 is turned off in response to the composite control signal Mc, and the second compensation transistor Tc2 is turned off in response to the first gate control signal Scan11. The data transistor Tda is turned on in response to the data write control signal Scan2, and the data signal is coupled to the first node N1 via the data transistor Tda and the second capacitor C2. The first reset transistor Ti1 and the second reset transistor Ti2 are turned off in response to the second gate control signal Scan12, and the switching transistor Ts is turned off in response to the emission control signal EM. In the pixel driving circuit shown in FIG2A, the third reset transistor Ti3 is turned off in response to the first gate control signal Scan11; in the pixel driving circuits shown in FIG2B and FIG2C, the third reset transistor Ti3 and the fourth reset transistor Ti4 are turned off in response to the reset control signal SN.

[0069] The sixth stage t6: the composite control signal Mc transmitted by the first gate control line SL1 is in an invalid level state (i.e., the composite control signal Mc in Figures 3A to 3C is a high level), the first gate control signal Scan11 transmitted by the second gate control line SL2 is in an invalid level state (i.e., the first gate control signal Scan11 in Figures 3A to 3B is a high level, and the first gate control signal Scan11 in Figure 3C is a low level), the data write control signal Scan2 transmitted by the third gate control line SL3 is in an invalid level state (i.e., the data write control signal Scan2 in Figures 3A to 3C is a high level), the second gate control signal Scan12 transmitted by the fourth gate control line SL4 is in an invalid level state (i.e., the second gate control signal Scan12 in Figures 3A to 3B is a high level, and the second gate control signal Scan12 in Figure 3C is a low level), and the light-emitting control signal EM transmitted by the light-emitting control line EML is in an invalid level state (i.e., the light-emitting control signal EM in Figures 3A to 3C is a high level). The reset control signal SN transmitted by the reset control line SNL is in an active level state (ie, the reset control signal SN in FIG. 3B to FIG. 3C is at a low level).

[0070] The first compensation transistor Tc1 is turned off according to the composite control signal Mc, the second compensation transistor Tc2 is turned off according to the first gate control signal Scan11, the data transistor Tda is turned off according to the data write control signal Scan2, the first reset transistor Ti1 and the second reset transistor Ti2 are turned off according to the second gate control signal Scan12, and the switch transistor Ts is turned off according to the light-emitting control signal EM. In the pixel driving circuits shown in Figures 2B and 2C, the third reset transistor Ti3 and the fourth reset transistor Ti4 are turned on according to the reset control signal SN. The second reset signal resets the anode of the light-emitting device Le, and the third reset signal resets the first node N1. Similar to the second stage t2, the pixel driving circuit shown in Figure 2A may not perform the sixth stage t6.

[0071] Seventh stage t7: the composite control signal Mc transmitted by the first gate control line SL1 is in a valid level state (i.e., the composite control signal Mc in Figures 3A to 3C is a low level), the first gate control signal Scan11 transmitted by the second gate control line SL2 is in an invalid level state (i.e., the first gate control signal Scan11 in Figures 3A to 3B is a high level, and the first gate control signal Scan11 in Figure 3C is a low level), the data write control signal Scan2 transmitted by the third gate control line SL3 is in an invalid level state (i.e., the data write control signal Scan2 in Figures 3A to 3C is a high level), the second gate control signal Scan12 transmitted by the fourth gate control line SL4 is in an invalid level state (i.e., the second gate control signal Scan12 in Figures 3A to 3B is a high level, and the second gate control signal Scan12 in Figure 3C is a low level), and the light-emitting control signal EM transmitted by the light-emitting control line EML is in a valid level state (i.e., the light-emitting control signal EM in Figures 3A to 3C is a low level). The reset control signal SN transmitted by the reset control line SNL is in an invalid level state (ie, the reset control signal SN in FIG. 3B to FIG. 3C is at a high level).

[0072] The first compensation transistor Tc1 is turned on according to the composite control signal Mc, the switching transistor Ts is turned on according to the light-emitting control signal EM, and the driving current generated by the driving transistor Tdr drives the light-emitting device Le to emit light. The second compensation transistor Tc2 is turned off according to the first gate control signal Scan11, the data transistor Tda is turned off according to the data write control signal Scan2, and the first reset transistor Ti1 and the second reset transistor Ti2 are turned off according to the second gate control signal Scan12. In the pixel driving circuit shown in FIG2A, the third reset transistor Ti3 is turned off according to the first gate control signal Scan11; in the pixel driving circuits shown in FIG2B and FIG2C, the third reset transistor Ti3 and the fourth reset transistor Ti4 are turned off according to the reset control signal SN.

[0073] FIG4 is a schematic structural diagram of a display panel provided in an embodiment of the present application. An embodiment of the present application further provides a display panel, wherein the display panel includes a plurality of sub-pixels Pi, and each of the sub-pixels Pi includes any of the above-mentioned pixel driving circuits.

[0074] Optionally, the display panel includes a plurality of gate driving units, and the plurality of gate driving units are electrically connected to the plurality of sub-pixels Pi to control the plurality of sub-pixels Pi to realize a light-emitting function.

[0075] Optionally, each gate driving unit includes a plurality of cascaded gate driving circuits, and the plurality of cascaded gate driving circuits sequentially output a plurality of control signals to control at least one transistor of a plurality of the sub-pixels Pi.

[0076] Optionally, the plurality of gate driving units include a first gate driving unit, the first gate driving unit includes a plurality of cascaded first gate driving circuits 401, and each first gate driving circuit 401 is electrically connected to the control end of the first compensation transistor Tc1 of the plurality of sub-pixels Pi in two adjacent rows through two first gate control lines SL1.

[0077] Optionally, the plurality of gate driving units include a second gate driving unit, the second gate driving unit includes a plurality of cascaded second gate driving circuits 402, and each second gate driving circuit 402 is electrically connected to the control end of the second compensation transistor Tc2 of the plurality of sub-pixels Pi located in a row through a second gate control line SL2.

[0078] Optionally, each second gate driving circuit 402 is electrically connected to the control terminals of the first reset transistor Ti1 and the second reset transistor Ti2 of a plurality of the sub-pixels Pi located in a row through the fourth gate control line SL4 .

[0079] Optionally, the plurality of gate driving units include a third gate driving unit, and the third gate driving unit includes a plurality of cascaded third gate driving circuits 403, and each third gate driving circuit 403 is electrically connected to the control end of the data transistor Tda of the plurality of sub-pixels Pi located in a row through the third gate control line SL3.

[0080] Optionally, the plurality of gate driving units include a fourth gate driving unit, and the fourth gate driving unit includes a plurality of cascaded fourth gate driving circuits 404, each fourth gate driving circuit 404 being electrically connected to the control end of the switching transistor Ts of the plurality of sub-pixels Pi in two adjacent rows through the two light-emitting control lines EML.

[0081] Optionally, the fourth gate driving circuit 404 and the first gate driving circuit 401 have the same circuit topology.

[0082] Optionally, the plurality of gate driving units include a fifth gate driving unit, and the fifth gate driving unit includes a plurality of cascaded fifth gate driving circuits 405, each fifth gate driving circuit 405 being electrically connected to the control ends of the third reset transistor Ti3 and the fourth reset transistor Ti4 of the plurality of sub-pixels Pi in two adjacent rows through the two reset control lines SNL.

[0083] Optionally, the display panel includes a display area and a first non-display area and a second non-display area located on opposite sides of the display area, a plurality of the sub-pixels Pi are located in the display area, and a plurality of the gate driving units are located in the first non-display area and the second non-display area.

[0084] Optionally, the first gate driving unit is located on a side of the fourth gate driving unit away from the display area, the third gate driving unit is located on a side of the second gate driving unit close to the display area, the fourth gate driving unit is located on a side of the second gate driving unit away from the display area, and the fifth gate driving unit is located between the fourth driving unit and the second gate driving unit.

[0085] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for technical personnel in this field, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A pixel driving circuit, wherein: include: A light emitting device, electrically connected between the first voltage terminal and the second voltage terminal; a driving transistor, wherein a control terminal of the driving transistor is electrically connected to the first node, an input terminal of the driving transistor is electrically connected to the first voltage terminal via a second node, and an output terminal of the driving transistor is electrically connected to the light emitting device via a third node; a threshold voltage extraction module, electrically connected to the driving transistor and the first voltage terminal, wherein the threshold voltage extraction module extracts the threshold voltage of the driving transistor through the first voltage transmitted by the first voltage terminal; as well as The data writing module is electrically connected to the first node and the data line, and the data writing module couples the data signal transmitted by the data line to the first node according to a data writing control signal.

2. The pixel driving circuit according to claim 1, wherein: The threshold voltage extraction module comprises: a first compensation transistor, wherein a control terminal of the first compensation transistor is electrically connected to the first gate control line, an input terminal of the first compensation transistor is electrically connected to the first voltage terminal, and an output terminal of the first compensation transistor is electrically connected to the second node; a second compensation transistor, wherein a control terminal of the second compensation transistor is electrically connected to a second gate control line, an input terminal of the second compensation transistor is electrically connected to the third node, and an output terminal of the second compensation transistor is electrically connected to the first node; and The first capacitor is connected in series between the first voltage terminal and the first node.

3. The pixel driving circuit according to claim 1, wherein: The data writing module comprises: a data transistor, wherein a control terminal of the data transistor is electrically connected to a third gate control line, and an input terminal of the data transistor is electrically connected to the data line; and A second capacitor is connected in series between the output end of the data transistor and the first node.

4. The pixel driving circuit according to claim 3, wherein: Also includes: The first reset module is electrically connected to the first node and the output end of the data transistor, and the first reset module resets the first node and the output end of the data transistor through a first reset signal.

5. The pixel driving circuit according to claim 4, wherein: The first reset module includes: a first reset transistor, wherein a control terminal of the first reset transistor is electrically connected to a fourth gate control line, an input terminal of the first reset transistor is electrically connected to a first reset line transmitting the first reset signal, and an output terminal of the first reset transistor is electrically connected to the first node; and A second reset transistor, wherein a control terminal of the second reset transistor is electrically connected to the fourth gate control line, an input terminal of the second reset transistor is electrically connected to the first node, and an output terminal of the second reset transistor is electrically connected to an output terminal of the data transistor.

6. The pixel driving circuit according to claim 5, wherein: The first reset transistor and the second reset transistor include oxide transistors.

7. The pixel driving circuit according to claim 1, wherein: Also includes: The switch control module comprises a switch transistor, wherein the control end of the switch transistor is electrically connected to the light-emitting control line, the input end of the switch transistor is electrically connected to the third node, and the output end of the switch transistor is electrically connected to the light-emitting device.

8. The pixel driving circuit according to claim 1, wherein: Also includes: The second reset module includes a third reset transistor, a control end of the third reset transistor is electrically connected to the reset control line, an input end of the third reset transistor is electrically connected to the second reset line, and an output end of the third reset transistor is electrically connected to the light emitting device.

9. The pixel driving circuit according to claim 8, wherein: Also includes: The third reset module includes a fourth reset transistor, wherein the control end of the fourth reset transistor is electrically connected to the reset control line, the input end of the fourth reset transistor is electrically connected to the third reset line, and the output end of the fourth reset transistor is electrically connected to the second node.

10. A display panel, wherein: The invention comprises a plurality of sub-pixels, each of which comprises a pixel driving circuit, wherein the pixel driving circuit comprises: A light emitting device, electrically connected between the first voltage terminal and the second voltage terminal; a driving transistor, wherein a control terminal of the driving transistor is electrically connected to the first node, an input terminal of the driving transistor is electrically connected to the first voltage terminal via a second node, and an output terminal of the driving transistor is electrically connected to the light emitting device via a third node; a threshold voltage extraction module, electrically connected to the driving transistor and the first voltage terminal, the threshold voltage extraction module extracting the threshold voltage of the driving transistor through the first voltage transmitted by the first voltage terminal; and The data writing module is electrically connected to the first node and the data line, and the data writing module couples the data signal transmitted by the data line to the first node according to a data writing control signal.

11. The display panel according to claim 10, wherein: The threshold voltage extraction module comprises: a first compensation transistor, wherein a control terminal of the first compensation transistor is electrically connected to the first gate control line, an input terminal of the first compensation transistor is electrically connected to the first voltage terminal, and an output terminal of the first compensation transistor is electrically connected to the second node; a second compensation transistor, wherein a control terminal of the second compensation transistor is electrically connected to a second gate control line, an input terminal of the second compensation transistor is electrically connected to the third node, and an output terminal of the second compensation transistor is electrically connected to the first node; and The first capacitor is connected in series between the first voltage terminal and the first node.

12. The display panel according to claim 10, wherein: The data writing module comprises: a data transistor, wherein a control terminal of the data transistor is electrically connected to a third gate control line, and an input terminal of the data transistor is electrically connected to the data line; and A second capacitor is connected in series between the output end of the data transistor and the first node.

13. The display panel according to claim 11, wherein: The pixel driving circuit comprises: a first reset transistor, wherein a control terminal of the first reset transistor is electrically connected to a fourth gate control line, an input terminal of the first reset transistor is electrically connected to a first reset line transmitting the first reset signal, and an output terminal of the first reset transistor is electrically connected to the first node; a second reset transistor, wherein a control terminal of the second reset transistor is electrically connected to the fourth gate control line, an input terminal of the second reset transistor is electrically connected to the first node, and an output terminal of the second reset transistor is electrically connected to an output terminal of the data transistor; and A third reset transistor, wherein a control terminal of the third reset transistor is electrically connected to the second gate control line, an input terminal of the third reset transistor is electrically connected to the second reset line, and an output terminal of the third reset transistor is electrically connected to the light emitting device.

14. The display panel according to claim 11, wherein: The pixel driving circuit comprises: A fourth reset transistor, wherein a control terminal of the fourth reset transistor is electrically connected to a reset control line, an input terminal of the fourth reset transistor is electrically connected to a third reset line, and an output terminal of the fourth reset transistor is electrically connected to the second node.

15. The display panel according to claim 11, wherein: The pixel driving circuit comprises: A switch transistor, wherein the control end of the switch transistor is electrically connected to the light emitting control line, the input end of the switch transistor is electrically connected to the third node, and the output end of the switch transistor is electrically connected to the light emitting device.

16. The display panel according to claim 11, wherein: Also includes: a first gate driving unit, comprising a plurality of cascaded first gate driving circuits, each of the first gate driving circuits being electrically connected to control terminals of the first compensation transistors of a plurality of the sub-pixels in two adjacent rows through two first gate control lines; and The second gate driving unit includes a plurality of cascaded second gate driving circuits, each of which is electrically connected to a control end of the second compensation transistors of a plurality of the sub-pixels in a row through a second gate control line.

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