Display device

Abstract

[Problem] To provide a display device that makes it possible to suppress a decrease in brightness. [Solution] This display device comprises: a plurality of pixels; a plurality of data signal lines that are connected to a plurality of pixels arranged in a first direction and supply an electric charge corresponding to data to a driving circuit; a plurality of scanning control lines that are connected to a plurality of pixels arranged in a second direction crossing the first direction and transmit a scanning signal when the electric charge is accumulated in the driving circuit; a light emission control line that is connected to the plurality of pixels and transmits a light emission signal when the electric charge is passed to a light emission element; a data signal control circuit that transmits data to the plurality of pixels via the plurality of data signal lines; and the driving circuit that drives the scanning control lines and the light emission control line. The driving circuit transmits the scanning signal to the plurality of scanning control lines in a first frame among a plurality of frames divided by a timing signal indicating a timing at which the plurality of pixels are driven, and thereafter transmits the light emission signal to the light emission control line from at least the first frame to a second frame following the first frame.

Description

display device

[0001] The present disclosure relates to a display device.

[0002] A display device displays an image by repeating a scanning operation in which image data is written to pixels and a light-emitting operation in which the pixels emit light based on the written image data. One scanning operation and one light-emitting operation constitute one frame. It is desirable to increase the ratio (duty) of light-emitting operations in one frame.

[0003] JP 2016-191940 A International Patent Application Publication No. 13 / 021418 International Patent Application Publication No. 13 / 073466 A

[0004] However, in the case of a surface-emitting display device, after image data is written to all pixels in one frame, all pixels are made to emit light, which causes a problem of a low duty and a decrease in brightness.

[0005] Therefore, the present disclosure provides a display device that can suppress a decrease in brightness.

[0006] a plurality of scanning control lines connected to the plurality of pixel circuits arranged in a second direction intersecting the first direction and transmitting scanning signals when charges are to be accumulated in the drive circuit; a plurality of emission control lines connected to the plurality of pixel circuits and transmitting emission signals when charges are to be flowed to the light-emitting elements; a data signal control circuit that transmits data to the plurality of pixel circuits via the plurality of data signal lines; and a drive circuit that drives the scanning control lines and the emission control lines, wherein the drive circuit transmits scanning signals to the plurality of scanning control lines in a first frame of a plurality of frames separated by a timing signal that indicates the timing to drive the plurality of pixel circuits, and then transmits the emission signals to the emission control lines from at least the first frame through a second frame that follows the first frame.

[0007] The drive circuit deactivates the light emission signal before starting to transmit the scanning signal to the plurality of scanning control lines in a third frame following the second frame among the plurality of frames.

[0008] The drive circuit performs a write operation for transmitting scanning signals to a plurality of scanning control lines and supplying charges according to data to the drive circuit via a plurality of data signal lines, and a light emission operation for transmitting light emission signals to a light emission control line to cause the pixel circuits to emit light, for each of a plurality of frames.

[0009] The ratio of the period of the light emitting operation to the total operation period of the writing operation and the light emitting operation is greater than 50%.

[0010] The drive circuit performs a write operation in which scanning signals are transmitted to a plurality of scanning control lines and charges corresponding to data are supplied to the drive circuit via a plurality of data signal lines, and an emission operation in which emission signals are transmitted to an emission control line to cause the pixel circuit to emit light, every three frames.

[0011] In a fourth frame following the third frame among the plurality of frames, the drive circuit inactivates the light emission signal before starting to transmit the scan signal to the plurality of scan control lines.

[0012] The period of light emitting operation is a period exceeding two of the three frames.

[0013] The plurality of light emission control lines are divided into a plurality of groups, and the drive circuit transmits a light emission signal to the light emission control lines for each group.

[0014] The drive circuit continuously transmits scanning signals to a plurality of scanning control lines corresponding to a plurality of groups.

[0015] The drive circuit transmits scanning signals to the plurality of scanning control lines in the first frame, and then activates the light-emitting signal a plurality of times.

[0016] The drive circuit transmits the scan signals to the plurality of scan control lines in the first frame, and then activates the light-emitting signal a plurality of times while increasing the activation period of the light-emitting signal.

[0017] The display device includes a first display unit that has a plurality of data signal lines, a plurality of scanning control lines, a light-emitting control line, a data signal control circuit, and a drive circuit and corresponds to one eye, and a second display unit that has a plurality of data signal lines, a plurality of scanning control lines, a light-emitting control line, a data signal control circuit, and a drive circuit and corresponds to the other eye, and the first display unit and the second display unit alternately perform an operation of transmitting scanning signals to the plurality of scanning control lines and an operation of transmitting light-emitting signals to the light-emitting control lines.

[0018] 1 is a block diagram showing an example of the configuration of a display device according to a first embodiment. FIG. 2 is a circuit diagram showing an example of the configuration of a pixel circuit. FIG. 3 is a block diagram showing an example of the internal configuration of a drive circuit. FIG. 4 is a timing chart showing an example of the operation of a display device according to a second embodiment. FIG. 5 is a block diagram showing an example of the configuration of a display device according to a third embodiment. FIG. 6 is a timing chart showing an example of the operation of a display device according to a third embodiment. FIG. 7 is a timing chart showing an example of the operation of a display device according to a fourth embodiment. FIG. 8 is a conceptual diagram showing an example of the operation of a display device according to a fifth embodiment.

[0019] Hereinafter, specific embodiments to which the present technology is applied will be described in detail with reference to the drawings. The drawings are schematic or conceptual, and the proportions of each part are not necessarily the same as those in reality. In the specification and drawings, elements similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0020] First Embodiment Fig. 1 is a block diagram showing an example of the configuration of a display device according to a first embodiment. The display device 100 is an EL (Electro-Luminescence) display including a timing controller 1, a drive circuit 2, a data input interface 3, a data signal control circuit 5, and (m x n) pixel circuits 10. The EL display may be, for example, a current-driven display device such as an organic EL display. Hereinafter, m and n are integers of 2 or more, i is an integer of 1 to n, j is an integer of 1 to m, and k is an integer of 1 to n.

[0021] The display device 100 is provided with n scanning control lines LWS1 to LWSn and m data signal lines S1 to Sm. The scanning control lines LWS1 to LWSn are arranged parallel to one another and extend in the same direction (second direction). The data signal lines S1 to Sm extend in a direction (first direction) that intersects (e.g., orthogonal to) the scanning control lines LWS1 to LWSn and are arranged parallel to one another. Pixel circuits 10 are arranged near each intersection of the scanning control lines LWS1 to LWSn and the data signal lines S1 to Sm. In this manner, (m×n) pixel circuits 10 are arranged two-dimensionally in a matrix. A scanning control line LWSi (i = 1 to n) is commonly connected to m pixel circuits 10 in the ith row arranged in the second direction. A data signal line Sj is commonly connected to n pixel circuits 10 in the jth column arranged in the first direction. The data signal line Sj supplies charges corresponding to a data signal to n pixel circuits 10 in the j-th column. The display device 100 is also provided with light-emission control lines LDS1 to LDSn and reset control lines LAZ1 to LAZn. The light-emission control lines LDS1 to LDSn and the reset control lines LAZ1 to LAZn extend in the second direction and are each connected in common to (m×n) pixel circuits 10. A power supply line and a reference potential line (e.g., a ground line), not shown, are connected to the pixel circuits 10, and a power supply voltage and a reference potential (e.g., a ground potential) are supplied to the pixel circuits 10.

[0022] The data input interface 3 transmits a data signal DA and synchronization signals XVD and XHD to the timing controller 1 based on data input from the outside.

[0023] The timing controller 1 transmits control signals WSST and SHT_EN to the drive circuit 2 based on synchronization signals XVD and XHD. The synchronization signal XVD is a timing signal that notifies the timing controller 1 of the start of an image frame. The synchronization signal XHD is a timing signal that notifies the timing controller 1 of the start of each line of the image. The control signal WSST is a timing signal that causes the drive circuit 2 to operate for each image frame. The control signal SHT_EN is a signal that causes the pixel circuits 10 to emit light. The timing controller 1 also transmits a data signal DA to the data signal control circuit 5. The timing controller 1 outputs other control signals, clock signals, etc. to the drive circuit 2 and the data signal control circuit 5.

[0024] The drive circuit 2 is connected to the scanning control lines LWS1 to LWSn, the light-emission control lines LDS1 to LDSn, and the reset control lines LAZ1 to LAZn, and drives the scanning control lines LWS1 to LWSn, the light-emission control lines LDS1 to LDSn, and the reset control lines LAZ1 to LAZn. The drive circuit 2 is, for example, a shift register circuit, and is configured by the flip-flops FF, logic circuits LC, and level shifters LS shown in FIG. 3.

[0025] The drive circuit 2 outputs a write signal WS to a scanning control line LWSi selected from the scanning control lines LWS1 to LWSn based on the control signal WSST. The selected scanning control line LWSi transmits the write signal WS to the m pixel circuits 10 connected to that scanning control line LWSi. This allows the drive circuit 2 to accumulate electric charge in the drive circuits of the m pixel circuits 10. In other words, the drive circuit 2 can write data signals from the data signal lines S1 to Sm to the m pixel circuits 10 connected to the scanning control line LWSi.

[0026] Furthermore, the drive circuit 2 outputs a light-emitting signal DS to the light-emitting control lines LDS1 to LDSn based on the control signals WSST and SHT_EN. The light-emitting control lines LDS1 to LDSn can transmit the light-emitting signal DS to the (m×n) pixel circuits 10 almost simultaneously. This allows the drive circuit 2 to supply a drive current to the light-emitting elements of the (m×n) pixel circuits 10, causing these light-emitting elements to emit light almost simultaneously and collectively. In other words, the display device 100 according to the present disclosure is a surface-emitting display device. The drive circuit 2 can also selectively supply a drive current to the m pixel circuits 10 connected to a selected light-emitting control line LDSi.

[0027] Furthermore, the drive circuit 2 outputs a reset signal AZ to the reset control lines LAZ1 to LAZn based on the control signal WSST. The reset control lines LAZ1 to LAZn can transmit the reset signal AZ to the (m×n) pixel circuits 10. This allows the drive circuit 2 to collectively reset the (m×n) pixel circuits 10 almost simultaneously. The drive circuit 2 can also selectively output the reset signal AZ to the m pixel circuits 10 connected to a selected reset control line LAZi.

[0028] The data signal control circuit 5 temporarily latches the data signal DA received from the timing controller 1 and outputs the data signal DA to the data signal lines S1 to Sm, thereby enabling the data signal control circuit 5 to transmit and write data to the m pixel circuits 10 connected to the selected scanning control line LWSi via the data signal lines S1 to Sm.

[0029] 2 is a circuit diagram showing an example configuration of the pixel circuit 10. The pixel circuit 10 includes transistors MP12 to MP15, capacitors C11 and C12, and a light-emitting element EL. The transistors MP12 to MP15 may all be P-type metal oxide semiconductor field effect transistors (MOSFETs). The pixel circuit 10 is connected to a scanning control line LWSi, a data signal line Sj, a light-emitting control line LDSi, and a reset control line LAZi. The pixel circuit 10 is also connected to a power supply line for a high-level power supply voltage VCCP and a power supply line for a low-level power supply voltage VSS.

[0030] The gate of transistor MP12 is connected to the scan control line LWSi, its source is connected to the data signal line Sj, and its drain is connected to the gate of transistor MP14 and capacitor C12. One end of capacitor C11 is connected to the power supply line of power supply voltage VCCP, and the other end is connected to capacitor C12, the drain of transistor MP13, and the source of transistor MP14. One end of capacitor C12 is connected to the other end of capacitor C11, the drain of transistor MP13, and the source of transistor MP14, and the other end is connected to the drain of transistor MP12 and gate of transistor MP14. The gate of transistor MP13 is connected to the light emission control line LDSi, its source is connected to the power supply line of power supply voltage VCCP, and its drain is connected to the source of transistor MP14, the other end of capacitor C11, and one end of capacitor C12. The gate of transistor MP14 is connected to the drain of transistor MP12 and the other end of capacitor C12, the source is connected to the drain of transistor MP13, the other end of capacitor C11, and one end of capacitor C12, and the drain is connected to the anode of light-emitting element EL and the source of transistor MP15. The gate of transistor MP15 is connected to reset control line LAZi, the source is connected to the drain of transistor MP14 and the anode of light-emitting element EL, and the drain is connected to the power supply line for power supply voltage VSS. The anode of light-emitting element EL is connected to the drain of transistor MP4 and the source of transistor MP5, and the cathode is connected to the power supply line for a predetermined cathode voltage Vcath.

[0031] With this configuration, in the pixel circuit 10, when the transistor MP12 is turned on (conductive), the voltage across the capacitor C12 is set based on the pixel signal supplied from the data signal line Sj. The transistor MP13 is turned on (conductive) or off (non-conductive) based on the signal on the light-emission control line LDSi. While the transistor MP13 is on, the transistor MP14 passes a current corresponding to the voltage difference across the capacitor C12 through the light-emitting element EL. The light-emitting element EL emits light based on the current supplied from the transistor MP14. In this way, the pixel circuit 10 emits light at a brightness corresponding to the pixel signal on the data signal line Sj. The transistor MP15 is turned on or off based on the signal on the reset control line LAZi. While the transistor MP15 is on, the anode voltage of the light-emitting element EL is initialized by being set to the power supply voltage VSS.

[0032] The transistors MP12 to MP15 are examples of a write control transistor, a light emission control transistor, a drive transistor, and a reset transistor, respectively. The light emitting element EL may be, for example, a photodiode.

[0033] 3 is a block diagram showing an example of the internal configuration of the drive circuit 2. The drive circuit 2 includes a plurality of flip-flops FF, a plurality of logic circuits LC, and a plurality of level shifters LS. The flip-flops FF, logic circuits LC, and level shifters LS are provided corresponding to the respective rows of the scanning control lines LWS1 to LWSn.

[0034] The flip-flop FF receives the control signal WSST and the clock CK, and outputs the control signal WSST to the logic circuit LC of each row in the scanning order of the frame at the timing of the clock CK.

[0035] The logic circuit LC receives a control signal WSST from the flip-flop FF and a control signal SHT_EN from the timing controller 1. The logic circuit LC generates a write signal WS, a light-emitting signal DS, and a reset signal AZ based on the control signal WSST and the control signal SHT_EN.

[0036] The level shifter LS adjusts the voltage levels of the write signal WS, light emission signal DS, and reset signal AZ generated by the logic circuit LC. The level shifter LS transmits the write signal WS, light emission signal DS, and reset signal AZ to the scan control line LWSi, light emission control line LDSi, and reset control line LAZi, respectively, via buffers.

[0037] FIG. 4 is a timing diagram showing an example of the operation of the display device according to the first embodiment. Frames FR1 to FR4 represent periods separated by a synchronization signal XVD indicating the timing for driving the pixel circuits 10. One or more frames (FR1 to FR4) are operating periods including a write period during which the scanning control lines LWS1 to LWSn are sequentially selected and data signals are written from the data signal lines S1 to Sm to the (m×n) pixel circuits 10, an emission period during which the (m×n) pixel circuits 10 are collectively illuminated, and a reset period during which the (m×n) pixel circuits 10 are reset. The display device 100 displays an image by repeating one or more frames. The number of frames is not particularly limited.

[0038] Typically, each frame is an operation cycle including a write period, a light emitting period, and a reset period, but in the present disclosure, the light emitting period is executed over multiple frames.

[0039] At time t1, the synchronization signal XVD is activated to a low level in a pulsed manner, thereby starting frame F1.

[0040] After the synchronization signal XVD rises to a high level, at time t2 the drive circuit 2 activates the control signal WSST to a high level in a pulsed manner, thereby starting the write operation of the data signal.

[0041] In the write operation, first, the drive circuit 2 selectively drives the scanning control line LWS1 of the first row. At t3, the drive circuit 2 activates the reset signal AZ1 to a low level, turning on the transistor MP15 (shown in FIG. 2) of each pixel circuit 10. This connects the drains of the transistors MP14 and the anodes of the light-emitting elements EL of the m pixel circuits 10 connected to the scanning control line LWS1 to the signal line of the low-level power supply voltage VSS, thereby resetting the pixel circuits 10.

[0042] At t4, the drive circuit 2 activates the light-emitting signal DSi to a low level to turn on the transistor MP13 of each pixel circuit 10. This connects the sources of the transistors MP14 of the m pixel circuits 10 connected to the scanning control line LWS1 to the power supply voltage VCCP.

[0043] At t5, the drive circuit 2 activates the write signal WS to a low level, turning on the transistors MP12 of the m pixel circuits 10 connected to the selected scanning control line LWS1. The m pixel circuits 10 in the selected row are connected to data signal lines S1 to Sm, respectively, and receive data signals from the data signal lines S1 to Sm. This causes the data signals to be written to the gates of the transistors MP14 and capacitors C12 of each pixel circuit 10 in the selected row. Once the data has been written to the m pixel circuits 10 in the selected row, the write signal WS, light-emitting signal DS, and reset signal AZ are deactivated to a high level.

[0044] Next, the drive circuit 2 selects the scanning control line LWS2 in the second row. The drive circuit 2 executes the same write operation as that performed at t3 to t5 on the m pixel circuits 10 connected to the scanning control line LWS2. At this time, the drive circuit 2 activates the reset control line LAZ2 and the light-emitting control line LDS2 to a low level. This causes the data signal from the data signal control circuit 5 to be written to the gates of the transistors MP14 and the capacitors C12 of the m pixel circuits 10 connected to the scanning control line LWS2. The gate voltage of the transistor MP14 after the write operation is held by the capacitor C12.

[0045] Thereafter, the drive circuit 2 sequentially selects the scanning control lines LWS3 to LWSn in the third to nth rows and executes the same write operation as that at t3 to t5, thereby writing data signals from the data signal control circuit 5 to all of the (m×n) pixel circuits 10. Note that the order of selection of the scanning control lines LWS1 to LWSn (the order of i) may be arbitrary.

[0046] Next, at t6, when the control signal SHT_EN is activated to a high level, the drive circuit 2 simultaneously activates the light-emitting signals DS of all rows of light-emitting control lines LDS1 to LDSn to a low level. This turns on the transistors MP13 of all (m×n) pixel circuits 10. In each pixel circuit 10, the transistor MP14 passes a current corresponding to its gate voltage to the light-emitting element EL. This causes the light-emitting element EL to emit light with an intensity corresponding to the data signal. All (m×n) pixel circuits 10 emit light collectively at approximately the same time.

[0047] Here, activation of the light-emitting signal DS begins after the data signal is written to the pixel circuit 10 and before the end of frame FR1. Therefore, the pixel circuit 10 emits light in response to the data signal written in frame FR1 from the middle of frame FR1 (t6), when the control signal SHT_EN and the light-emitting signal DS are activated. Furthermore, the (m×n) pixel circuits 10 maintain light emission from the middle of frame FR1 through frame FR2, which follows frame FR1. Therefore, at t7, the synchronization signal XVD falls to a low level in a pulsed manner, ending frame FR1 and starting frame FR2. However, at this time, the control signal SHT_EN and the light-emitting signal DS remain activated throughout frame FR2, and the (m×n) pixel circuits 10 maintain light emission.

[0048] Next, at t8, the synchronization signal XVD falls to a low level in a pulsed manner, thereby ending frame FR2 and starting frame FR3.

[0049] Next, at t9, the data input interface 3 raises the synchronization signal XVD in a pulsed manner.

[0050] Immediately after t9 and immediately before t10, in response to the falling edge of the synchronization signal XVD, the timing controller 1 inactivates the control signal SHT_EN to a low level, and the drive circuit 2 simultaneously inactivates the light-emitting signals DS of the light-emitting control lines LDS1 to LDSn of all rows to a high level. This causes the light-emitting operations of all (m×n) pixel circuits 10 to stop almost simultaneously. The light-emitting operations of the pixel circuits 10 must be terminated before the start of the next data signal writing operation (or reset operation).

[0051] At t10, the timing controller 1 activates the control signal WSST in a pulsed manner to a high level, thereby starting the write operation of the next data signal. The drive circuit 2 sequentially selects the scanning control lines LWS1 to LWSn in the first to nth rows, and executes the same write operation as at t3 to t5. As a result, the next data signal is written to all (m×n) pixel circuits 10.

[0052] Next, similarly to t6 to t10, pixel circuit 10 starts the light emitting operation midway through frame FR3 in which control signal SHT_EN and light emitting signal DS are activated, and continues emitting light throughout frame FR4. Thereafter, pixel circuit 10 finishes the light emitting operation before the writing operation of the next data signal starts in response to the falling edge of synchronization signal XVD.

[0053] In this manner, the display device 100 according to the present disclosure repeats the reset operation, the write operation, and the light-emitting operation in a two-frame cycle. This allows the drive circuit 2 to use a portion of one of the two frames for the write operation and the remaining period exceeding one frame for the light-emitting period. In other words, the ratio of the light-emitting period to the total operating period (duty) is greater than 50%. As a result, the display device 100 can suppress a decrease in brightness. Furthermore, by improving the duty, deterioration of the light-emitting element EL can be suppressed.

[0054] 5 is a timing chart showing an example of the operation of a display device according to a second embodiment. In the second embodiment, a reset operation, a write operation, and a light-emitting operation are repeated in a three-frame cycle, and two or more of the three frames are used as the light-emitting period. The configuration of the display device 100 according to the second embodiment may be the same as that of the first embodiment.

[0055] For example, after frames FR1 and FR2 of the first embodiment are executed, the (m×n) pixel circuits 10 continue to emit light throughout frame FR3. At t8, the synchronization signal XVD falls to a low level in a pulsed manner, ending frame FR2 and starting frame FR3. However, at this time, the control signals SHT_EN and light-emitting signals DS in the light-emission control lines LDS1 to LDSn of all rows are activated throughout frame FR3, and the (m×n) pixel circuits 10 continue to emit light.

[0056] At t10, just before the falling edge of the synchronization signal XVD, the control signal SHT_EN is inactivated to a low level, and the light-emitting signal DS is inactivated to a high level. This causes the light-emitting operations of all (m×n) pixel circuits 10 to stop collectively and almost simultaneously. The light-emitting signals DS in the light-emitting control lines LDS1 to LDSn of all rows must be inactivated before the writing operation (or reset operation) of the next data signal is started in frame FR4.

[0057] At time t11 immediately after time t10, the data input interface 3 causes the synchronization signal XVD to fall in a pulse-like manner.

[0058] Thereafter, the operations from t2 to t11 are repeated.

[0059] In this way, the display device 100 according to the second embodiment repeats the reset operation, the write operation, and the light-emitting operation in a three-frame cycle. This allows more than two of the three frames to be used as the light-emitting period. That is, the duty becomes greater than 66%. As a result, the display device 100 can suppress a decrease in brightness.

[0060] In the second embodiment, the light emitting operation is stopped at t10, immediately before frame FR4. However, in the second embodiment, as in the first embodiment, the light emitting operation may be maintained until immediately before the start of the writing operation of frame FR4 (t2). This allows for further improvement of the duty.

[0061] Furthermore, the display device 100 may repeat the reset operation, the write operation, and the light emitting operation in a cycle of four or more frames, which can further improve the duty.

[0062] Third Embodiment FIG. 6 is a block diagram showing an example of the configuration of a display device according to a third embodiment. A display device 100 according to the third embodiment divides the scanning control lines LWS1 to LWSn into a plurality of groups and performs a light-emitting operation for each group. Accordingly, a control signal SHT_EN and a light-emitting signal DS are provided for each group corresponding to the plurality of groups of the scanning control lines LWS1 to LWSn. For example, when the scanning control lines LWS1 to LWSn are divided into two groups, the control signal SHT_EN is divided into two control signals SHT_EN_1 and SHT_EN_2. The light-emitting signal DS is divided into two light-emitting signals DS1 and DS2. Two control lines are also provided for transmitting the control signals SHT_EN_1 and SHT_EN_2. The light-emitting control lines LDS1 to LDSn that transmit the light-emitting signals DS1 and DS2 are also divided into two groups (LDS1 to LDSk, LDSk+1 to LDSn). Other configurations of the third embodiment may be similar to the corresponding configurations of the first embodiment. The number of groups of the scanning control lines LWS1 to LWSn may be three or more. Accordingly, the light-emitting control lines LDS1 to LDSn are also divided into three or more groups. The control signal SHT_EN and its control line, and the light-emitting signal DS and its control line (light-emitting control lines LDS1 to LDSn) may be provided in accordance with the number of groups of the scanning control lines LWS1 to LWSn.

[0063] 7 is a timing diagram showing an example of the operation of the display device according to the third embodiment. In the third embodiment, the drive circuit 2 sequentially selects some of the scanning control lines LWS1 to LWSk among the n rows of scanning control lines LWS1 to LWSn, and sequentially writes data signals to the pixel circuits 10 connected to the selected scanning control lines. The drive circuit 2 then causes the scanning control lines LWS1 to LWSk to perform light-emitting operations simultaneously and collectively (t6_1 to t10_1). That is, the drive circuit 2 simultaneously drives the light-emitting control lines LDS1 to LDSk corresponding to the scanning control lines LWS1 to LWSk, causing the pixel circuits 10 connected to the scanning control lines LWS1 to LWSk to emit light.

[0064] After the write operation of the scanning control lines LWS1 to LWSk, the drive circuit 2 sequentially selects the other scanning control lines LWSk+1 to LWSn among the n rows of scanning control lines LWS1 to LWSn, and sequentially writes data signals to the pixel circuits 10 connected to the selected scanning control lines. Thereafter, the drive circuit 2 causes the scanning control lines LWSk+1 to LWSn to perform light-emitting operations simultaneously and collectively (t6_2 to t10_2). That is, the drive circuit 2 simultaneously drives the light-emitting control lines LDSk+1 to LDSn corresponding to the scanning control lines LWSk+1 to LWSn, causing the pixel circuits 10 connected to the scanning control lines LWSk+1 to LWSn to emit light.

[0065] As described above, in the third embodiment, the scanning control lines LWS1 to LWSn are divided into a plurality of groups, and light emission is performed for each group. The cycle of the light emission operation of the scanning control lines LWS1 to LWSn of all rows may be a two-frame cycle, as in the first embodiment, or may be a three-frame cycle, as in the second embodiment. In the example of FIG. 7, the cycle of the light emission operation of the scanning control lines LWS1 to LWSn of all rows is a two-frame cycle.

[0066] For example, in frame FR1 of the first embodiment, after performing operations corresponding to t1 and t2, the drive circuit 2 sequentially selects the scanning control lines LWS1 to LWSk of group GP1 and performs the same write operations as those at t3 to t5, thereby writing data signals from the data signal control circuit 5 to the pixel circuits 10 connected to the scanning control lines LWS1 to LWSk.

[0067] Next, at t6_1, when the control signal SHT_EN_1 is activated to a high level, the drive circuit 2 activates the light-emitting signal DS1 for the scanning control lines LWS1 to LWSk to a low level. The light-emitting signal DS1 is a signal transmitted to the light-emitting control lines LDS1 to LDSk belonging to group GP1. As a result, the pixel circuits 10 connected to the scanning control lines LWS1 to LWSk emit light collectively almost simultaneously.

[0068] The activation of the light emitting signal DS1 for the scanning control lines LWS1 to LWSk starts before the end of frame FR1 and is maintained throughout frame FR2. Therefore, the pixel circuit 10 starts the light emitting operation midway through frame FR1 and maintains the light emission throughout frame FR2.

[0069] At t10_1, the control signal SHT_EN_1 is deactivated to a low level, and the light-emitting signal DS1 is deactivated to a high level, which causes the light-emitting operations of the pixel circuits 10 connected to the scanning control lines LWS1 to LWSk to stop almost simultaneously.

[0070] On the other hand, after the write operation for the scanning control lines LWS1 to LWSk is completed, the drive circuit 2 continues to sequentially select the scanning control lines LWSk+1 to LWSn of the group GP2 and executes the same write operation as at t3 to t5. As a result, data signals from the data signal control circuit 5 are written to the pixel circuits 10 connected to the scanning control lines LWSk+1 to LWSn. That is, the write operation is executed consecutively for the scanning control lines LWS1 to LWSn corresponding to the groups GP1 and GP2.

[0071] Next, at t6_2, when the control signal SHT_EN_2 is activated to a high level, the drive circuit 2 activates the light-emitting signal DS2 for the scanning control lines LWSk+1 to LWSn to a low level. The light-emitting signal DS2 is a signal transmitted to the light-emitting control lines LDSk+1 to LDSn belonging to group GP2. As a result, the pixel circuits 10 connected to the scanning control lines LWSk+1 to LWSn emit light collectively almost simultaneously.

[0072] Activation of the light emitting signal DS2 for the scanning control lines LWSk+1 to LWSn starts after the end of frame FR1, and light emission is maintained until the start of the write operation of the next data signal in frame FR3 (t10_2).

[0073] At t10_2, the control signal SHT_EN_2 is inactivated to a low level, and the light-emitting signal DS2 is inactivated to a high level, which causes the light-emitting operations of the pixel circuits 10 connected to the scanning control lines LWSk+1 to LWSn to stop almost simultaneously.

[0074] After that, t2 to t10_2 are repeated.

[0075] In this way, the display device 100 according to the third embodiment divides the scanning control lines LWS1 to LWSn into a plurality of groups and performs a light emitting operation for each group. This allows the group GP1 to perform a light emitting operation while one group GP2 is performing a write operation. Furthermore, the light emitting operation of one group GP2 may overlap with the light emitting operation of the other group GP1. This increases the duty, and the display device 100 can suppress a decrease in brightness.

[0076] The display device 100 repeats the reset operation, the write operation, and the light-emitting operation in a two-frame cycle. However, the display device 100 may repeat the reset operation, the write operation, and the light-emitting operation in a three-frame or more cycle. In this case, the duty can be further improved.

[0077] Fourth Embodiment FIG. 8 is a timing chart showing an example of the operation of a display device according to a fourth embodiment. In the fourth embodiment, the drive circuit 2 divides the light-emitting operation of data written to all (m×n) pixel circuits 10 in one frame into multiple parts and executes the operation. That is, after the write operation to the (m×n) pixel circuits 10, the drive circuit 2 activates the control signal SHT_EN to a high level and activates the light-emitting signal DS multiple times. Note that, in the fourth embodiment, the drive circuit 2 executes the reset operation, write operation, and light-emitting operation in a two-frame cycle, but these operations may be executed in a cycle of three or more frames. The configuration of the display device 100 according to the fourth embodiment may be the same as that of the first embodiment.

[0078] For example, the drive circuit 2 sequentially selects the scanning control lines LWS3 to LWSn and executes the same write operation as at t3 to t5, thereby writing data signals from the data signal control circuit 5 to all of the (m×n) pixel circuits 10. Note that the order in which the scanning control lines LWS1 to LWSn are selected may be arbitrary.

[0079] Next, from t6_1 to t10_1, the timing controller 1 activates the control signal SHT_EN to high level, and the drive circuit 2 activates the light-emitting signal DS to low level. As a result, all of the (m×n) pixel circuits 10 emit light almost simultaneously. If the longest light-emitting period (t6_8 to t10_8) is 100%, the period from t6_1 to t10_1 is 20% of the longest light-emitting period.

[0080] Next, after deactivating the light-emitting signal DS, the drive circuit 2 activates the light-emitting signal DS to a low level from t6_2 to t10_2. This causes all of the (m×n) pixel circuits 10 to emit light almost simultaneously. The period from t6_2 to t10_2 is 40% of the longest light-emitting period.

[0081] Next, after deactivating the light-emitting signal DS, the drive circuit 2 activates the light-emitting signal DS to a low level from t6_3 to t10_3. This causes all of the (m×n) pixel circuits 10 to emit light almost simultaneously. The period from t6_3 to t10_3 is 50% of the longest light-emitting period.

[0082] Thereafter, from t6_4 to t10_4, t6_4 to t10_4, . . . t6_8 to t10_8, the ratio of each light emitting period to the longest light emitting period is increased to 60%, 70%, 80%, 90%, and 100%.

[0083] At t10, the timing controller 1 deactivates the control signal SHT_EN to low level, thereby ending the light emitting operation. Thereafter, the display device 100 repeats the reset operation, the write operation, and the light emitting operation from t2 to t10.

[0084] During light emission, the light emission intensity (brightness) of the pixel circuit 10 changes when the charge from the capacitor C12 in FIG. 2 is discharged. The charge from the capacitor C12 decreases over time. Therefore, the light emission intensity of the pixel circuit 10 during the period from t6_1 to t10_1 in FIG. 8 is stronger than the light emission intensity of the pixel circuit 10 during the period from t6_8 to t10_8. The light emission intensity of the pixel circuit 10 decreases in the order of t6_1 to t10_1, t6_2 to t10_2, ..., t6_8 to t10_8.

[0085] On the other hand, in the fourth embodiment, the light-emitting time of the pixel circuit 10 increases in the order of t6_1 to t10_1, t6_2 to t10_2, ..., t6_8 to t10_8. In this way, by compensating for the decrease in light-emitting intensity of the pixel circuit 10 with the light-emitting time, it is possible to stabilize the brightness of the image. In addition, it is possible to suppress flicker and improve the image quality of moving images.

[0086] Other operations of the fourth embodiment may be the same as those of the first embodiment, and therefore the fourth embodiment can achieve the same effects as those of the first embodiment.

[0087] Fifth Embodiment Fig. 9 is a conceptual diagram showing an example of the operation of a display device according to a fifth embodiment. A display device 100 according to the fifth embodiment includes a plurality of display units 100R and 100L corresponding to the right and left eyes, respectively, of the two eyes. Each of the display units 100R and 100L alternately performs a writing operation and a light-emitting operation. In frames FR1 and FR3 in which the display unit 100R is performing a writing operation, the display unit 100L is performing a light-emitting operation. In frames FR2 and FR4 in which the display unit 100L is performing a writing operation, the display unit 100R is performing a light-emitting operation.

[0088] The display units 100R and 100L may each have the configuration of any of the first to fourth embodiments. The display units 100R and 100L may each execute any of the first to fourth embodiments. When operating in a three-frame cycle, the operation of the display units 100R and 100L may be shifted by one frame period or by 1.5 frame periods.

[0089] The present technology can be configured as follows.

[0090] a plurality of scanning control lines connected to the plurality of pixel circuits arranged in a second direction intersecting the first direction and transmitting scanning signals when the charges are to be accumulated in the drive circuit; a plurality of light-emitting control lines connected to the plurality of pixel circuits and transmitting light-emitting signals when the charges are to be flowed to the light-emitting elements; a data signal control circuit that transmits data to the plurality of pixel circuits via the plurality of data signal lines; and a drive circuit that drives the scanning control lines and the light-emitting control lines, wherein the drive circuit transmits the scanning signals to the plurality of scanning control lines in a first frame of a plurality of frames separated by a timing signal that indicates timing for driving the plurality of pixel circuits, and then transmits the light-emitting signals to the light-emitting control lines from the first frame through at least a second frame that follows the first frame.

[0091] (2) The display device according to (1), wherein the drive circuit inactivates the light-emitting signal before starting to transmit the scanning signal to the plurality of scanning control lines in a third frame following the second frame among the plurality of frames.

[0092] (3) The display device according to (1) or (2), wherein the drive circuit performs a write operation for transmitting the scanning signals to the plurality of scanning control lines and supplying charges according to data to the drive circuit via the plurality of data signal lines, and a light emission operation for transmitting the light emission signals to the light emission control lines to cause the pixel circuits to emit light, for each of the plurality of frames.

[0093] (4) The display device according to (3), wherein a ratio of the period of the light emitting operation to the total operation period of the writing operation and the light emitting operation is greater than 50%.

[0094] (5) The display device according to (3), wherein the drive circuit performs a write operation for transmitting the scanning signals to the plurality of scanning control lines and supplying charges according to data to the drive circuit via the plurality of data signal lines, and a light emission operation for transmitting the light emission signals to the light emission control lines to cause the pixel circuits to emit light, for every three of the frames.

[0095] (6) The display device according to (5), wherein the drive circuit inactivates the light-emitting signal before starting to transmit the scanning signal to the plurality of scanning control lines in a fourth frame following the third frame among the plurality of frames.

[0096] (7) The display device according to (5) or (6), wherein the period of the light emitting operation is a period exceeding two frames out of the three frames.

[0097] (8) The display device according to any one of (1) to (7), wherein the plurality of light-emission control lines are divided into a plurality of groups, and the drive circuit transmits the light-emission signal to the light-emission control lines for each group.

[0098] (9) The display device according to (8), wherein the drive circuit continuously transmits the scanning signals to the plurality of scanning control lines corresponding to the plurality of groups.

[0099] (10) The display device according to any one of (1) to (9), wherein the drive circuit activates the light-emitting signal multiple times after transmitting the scanning signals to the plurality of scanning control lines in the first frame.

[0100] (11) The display device according to (10), wherein after transmitting the scanning signals to the plurality of scanning control lines in the first frame, the drive circuit activates the light-emitting signal a plurality of times while increasing an activation period of the light-emitting signal.

[0101] (12) The display device according to any one of (1) to (11), comprising: a first display unit corresponding to one eye and including the plurality of data signal lines, the plurality of scanning control lines, the light-emission control lines, the data signal control circuit, and the drive circuit; and a second display unit corresponding to the other eye and including the plurality of data signal lines, the plurality of scanning control lines, the light-emission control lines, the data signal control circuit, and the drive circuit, wherein the first display unit and the second display unit alternately perform an operation of transmitting the scanning signals to the plurality of scanning control lines and an operation of transmitting the light-emission signals to the light-emission control lines.

[0102] The present disclosure is not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the present disclosure. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be obtained.

[0103] REFERENCE SIGNS LIST 100 Display device 1 Timing controller 2 Drive circuit 3 Data input interface 5 Data signal line drive circuit 10 Pixel circuit LWS1 to LWSn Scanning control lines LDS1 to LDSn Light emitting control lines LAZ1 to LAZn Reset control lines S1 to Sm Data signal lines

Claims

a plurality of pixel circuits including a light-emitting element and a drive circuit for supplying a drive current to the light-emitting element; a plurality of data signal lines connected to the plurality of pixel circuits arranged in a first direction and supplying a charge according to data to the drive circuit; a plurality of scanning control lines connected to the plurality of pixel circuits arranged in a second direction intersecting the first direction and transmitting a scanning signal when the charge is to be accumulated in the drive circuit; a plurality of light-emitting control lines connected to the plurality of pixel circuits and transmitting a light-emitting signal when the charge is to be flowed to the light-emitting element; a data signal control circuit for transmitting data to the plurality of pixel circuits via the plurality of data signal lines; and a drive circuit for driving the scanning control lines and the light-emitting control lines, wherein the drive circuit transmits the scanning signal to the plurality of scanning control lines in a first frame of a plurality of frames separated by a timing signal indicating the timing to drive the plurality of pixel circuits, and then transmits the light-emitting signal to the light-emitting control lines from the first frame to a second frame following the first frame.

2. The display device according to claim 1, wherein the driving circuit inactivates the emission signal before starting to transmit the scanning signal to the plurality of scanning control lines in a third frame following the second frame among the plurality of frames.

3. The display device according to claim 1, wherein the drive circuit performs a write operation for transmitting the scanning signal to the plurality of scanning control lines and supplying charges corresponding to data to the drive circuit via the plurality of data control lines, and a light emission operation for transmitting the light emission signal to the light emission control line to cause the pixel circuit to emit light, for each of the plurality of frames.

4. The display device according to claim 3, wherein a ratio of a period of said light emitting operation to a total operation period of said writing operation and said light emitting operation is greater than 50%.

5. The display device according to claim 3, wherein the drive circuit performs a write operation for transmitting the scanning signals to the plurality of scanning control lines and supplying charges corresponding to data to the drive circuit via the plurality of data signal lines, and a light emission operation for transmitting the light emission signals to the light emission control lines to cause the pixel circuits to emit light, for every three of the frames.

6. The display device according to claim 5, wherein the driving circuit inactivates the emission signal before starting to transmit the scanning signal to the plurality of scanning control lines in a fourth frame following the third frame among the plurality of frames.

7. The display device according to claim 5, wherein the period of the light emitting operation is a period exceeding two of the three frames.

8. The display device according to claim 1, wherein the plurality of light emission control lines are divided into a plurality of groups, and the drive circuit transmits the light emission signal to the light emission control lines for each of the groups.

9. The display device according to claim 8, wherein the drive circuit transmits the scanning signals successively to the plurality of scanning control lines corresponding to the plurality of groups.

10. The display device according to claim 1, wherein the drive circuit activates the light emission signal a plurality of times after transmitting the scanning signals to the plurality of scanning control lines in the first frame.

11. The display device according to claim 10, wherein after transmitting the scanning signals to the plurality of scanning control lines in the first frame, the drive circuit activates the light-emitting signal a plurality of times while increasing the activation period of the light-emitting signal.

12. A display device as described in claim 1, comprising: a first display unit corresponding to one eye, the first display unit comprising the plurality of data signal lines, the plurality of scanning control lines, the light-emitting control line, the data signal control circuit, and the drive circuit; and a second display unit corresponding to the other eye, the first display unit and the second display unit alternately perform an operation of transmitting the scanning signals to the plurality of scanning control lines and an operation of transmitting the light-emitting signals to the light-emitting control lines.

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