Display substrate and manufacturing method therefor, and display apparatus

Abstract

A display substrate and a manufacturing method therefor, and a display apparatus. The display substrate comprises sub-pixels; each sub-pixel comprises a pixel circuit; the pixel circuit comprises a light-emitting device and a driving transistor, and the driving transistor is configured to control, on the basis of a data signal, the magnitude of a driving current flowing through the light-emitting device; the pixel circuit also comprises a control transistor, and a first electrode of the control transistor is electrically connected to a gate of the driving transistor; the material of an active layer of the driving transistor is a first semiconductor material, the material of an active layer of the control transistor is a second semiconductor material, and the first semiconductor material is different from the second semiconductor material; an electrode where the active layer of the control transistor is located is directly electrically connected to the gate of the driving transistor and the first electrode of the control transistor.

Description

Display substrate, manufacturing method thereof, and display device

[0001] This application claims priority to Chinese Patent Application No. 202310956228.7, filed on July 31, 2023, the disclosure of which is incorporated herein in its entirety as part of the present application. TECHNICAL FIELD

[0002] The present disclosure relates to a display substrate, a manufacturing method thereof, and a display device. BACKGROUND

[0003] LTPO display substrate integrates oxide transistor (Oxide TFT) and low-temperature polysilicon transistor (LTPS TFT), has the advantage of low-frequency driving, can reduce the power consumption of display products, and has been more and more applied in organic light-emitting diode (OLED) display substrate, such as flexible active matrix organic light-emitting diode (AMOLED) display substrate mobile display products. However, since the LTPO display substrate integrates the LTPS TFT and the Oxide TFT, the few hydrogen process of the Oxide TFT is easily affected by the more hydrogen and high temperature process of the LTPS TFT, so that the device stability of the Oxide TFT is poor; and since the LTPO display substrate integrates the LTPS TFT and the Oxide TFT, the signal line layout of the pixel area is very complex, which will affect the aperture ratio and the transmittance of the LTPO display substrate, so that the design difficulty is increased.

[0004] SUMMARY

[0005] The present disclosure relates to a display substrate, a manufacturing method thereof, and a display device. For example, the present disclosure relates to a display substrate, a manufacturing method thereof, and a display device.

[0006] For example, the present disclosure relates to a display substrate, a manufacturing method thereof, and a display device. For example, the present disclosure relates to a display substrate, a manufacturing method thereof, and a display device.

[0007] For example, at least one embodiment of the present disclosure provides a display substrate, the display substrate comprising a substrate, a driving transistor disposed on a main surface of the substrate, and an active layer of the driving transistor located on a side of an active layer of the control transistor close to the substrate.

[0008] For example, at least one embodiment of the present disclosure provides a display substrate, the pixel circuit comprising a first reset transistor configured to write a first reset signal to a gate of the driving transistor under control of a first reset control signal, and the control transistor comprising the first reset transistor, an electrode in which an active layer of the first reset transistor is located directly electrically connecting the gate of the driving transistor and a first electrode of the first reset transistor.

[0009] For example, at least one embodiment of the present disclosure provides a display substrate, the electrode in which the active layer of the first reset transistor is located comprising the active layer of the first reset transistor and the first electrode of the first reset transistor, a material of the first electrode of the first reset transistor being a material of the second semiconductor material after being conductorized, the active layer of the first reset transistor and the first electrode of the first reset transistor being disposed in a same layer and constituting an integrated structure, the gate of the driving transistor and the electrode in which the active layer of the first reset transistor is located being disposed in different layers, the first electrode of the first reset transistor being in contact with the gate of the driving transistor through a first via hole exposing the gate of the driving transistor to directly electrically connect the gate of the driving transistor and the first electrode of the first reset transistor.

[0010] For example, at least one embodiment of the present disclosure provides a display substrate, the electrode in which the active layer of the first reset transistor is located further comprising a second electrode of the first reset transistor, a material of the second electrode of the first reset transistor being a material of the second semiconductor material after being conductorized, and the pixel circuit further comprising a first reset signal line disposed in a different layer from the second electrode of the first reset transistor, the second electrode of the first reset transistor being in contact with the first reset signal line through a second via hole exposing the first reset signal line to directly electrically connect the first reset signal line.

[0011] For example, at least one embodiment of the present disclosure provides a display substrate, the pixel circuit further comprising a compensation transistor configured to compensate a signal applied to the gate of the driving transistor in response to a compensation scan signal and the data signal, and the control transistor further comprising the compensation transistor, an electrode in which an active layer of the compensation transistor is located directly electrically connecting the gate of the driving transistor and a first electrode of the compensation transistor.

[0012] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the electrode where the active layer of the compensation transistor is located further comprises the first electrode of the compensation transistor, the material of the active layer of the compensation transistor and the first electrode of the compensation transistor is the material after the second semiconductor material is conductorized, the active layer of the compensation transistor and the first electrode of the compensation transistor are arranged in the same layer and constitute an integrated structure; the gate of the driving transistor is arranged in a layer different from the electrode where the active layer of the compensation transistor is located, and the first electrode of the compensation transistor is in contact with the gate of the driving transistor through a third via hole exposing the gate of the driving transistor to directly electrically connect the gate of the driving transistor and the first electrode of the compensation transistor.

[0013] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the electrode where the active layer of the compensation transistor is located further comprises the first electrode of the compensation transistor, the material of the active layer of the compensation transistor and the first electrode of the compensation transistor is the material after the second semiconductor material is conductorized, the active layer of the compensation transistor and the first electrode of the compensation transistor are arranged in the same layer and constitute an integrated structure; the gate of the driving transistor is arranged in a layer different from the electrode where the active layer of the compensation transistor is located, and the first electrode of the compensation transistor is in contact with the gate of the driving transistor through a third via hole exposing the gate of the driving transistor to directly electrically connect the gate of the driving transistor and the first electrode of the compensation transistor.

[0014] For example, at least one of the embodiments of the present disclosure provides a display substrate, wherein the pixel circuit further comprises a first light emitting control transistor configured to cause the driving current to be applied to the light emitting device under the control of a first light emitting control signal; a material of an active layer of the first light emitting control transistor is the first semiconductor material, and the active layer of the first light emitting control transistor is disposed in a layer different from that of the active layer of the control transistor; an electrode in which the active layer of the compensation transistor is disposed further comprises a connecting portion, a material of the connecting portion is a material of the second semiconductor material after being made conductive, the connecting portion is disposed in a layer integrated with the active layer of the compensation transistor, and the connecting portion is used as a first electrode of the first light emitting control transistor and a second electrode of the compensation transistor.

[0015] For example, at least one of the embodiments of the present disclosure provides a display substrate, wherein the active layer of the first light emitting control transistor and the active layer of the driving transistor are disposed in the same layer, and / or the gate of the driving transistor and the gate of the first light emitting control transistor are disposed in the same layer.

[0016] For example, at least one of the embodiments of the present disclosure provides a display substrate, wherein the pixel circuit further comprises a first light emitting control transistor configured to cause the driving current to be applied to the light emitting device under the control of a first light emitting control signal; a material of an active layer of the first light emitting control transistor is the first semiconductor material, and the active layer of the first light emitting control transistor is disposed in a layer different from that of the active layer of the control transistor; an electrode in which the active layer of the control transistor is disposed is disposed in a layer different from that of the second electrode of the first light emitting control transistor, the electrode in which the active layer of the control transistor is disposed is in contact with the active layer of the first light emitting control transistor through a fourth via hole exposing the active layer of the first light emitting control transistor, and the second electrode of the first light emitting control transistor is in contact with the active layer of the first light emitting control transistor through a fifth via hole exposing the active layer of the first light emitting control transistor.

[0017] For example, at least one of the embodiments of the present disclosure provides a display substrate, wherein the display substrate comprises a substrate, the driving transistor is disposed on a main surface of the substrate, and the second electrode of the first light emitting control transistor is located on a side of the electrode in which the active layer of the control transistor is disposed, which is away from the substrate.

[0018] For example, at least one of the embodiments of the present disclosure provides a display substrate, wherein the control transistor comprises a first reset transistor, an electrode where an active layer of the first reset transistor is located further comprises a second electrode of the first reset transistor, a material of the second electrode of the first reset transistor is a material after the second semiconductor material is made conductive, the pixel circuit further comprises a first reset signal line arranged in a layer different from the second electrode of the first reset transistor, and the first reset signal line is arranged in a layer different from the second electrode of the first reset transistor in the case that the second electrode of the first reset transistor is electrically connected to the first reset signal line through a second via hole exposing the first reset signal line.

[0019] For example, at least one of the embodiments of the present disclosure provides a display substrate, wherein the first reset signal line and the gate electrode of the driving transistor are located between the gate electrode of the driving transistor and an electrode where an active layer of the control transistor is located; and the first reset signal line is arranged in a layer different from or the same as the gate electrode of the driving transistor.

[0020] For example, at least one of the embodiments of the present disclosure provides a display substrate, wherein the control transistor is a single-gate transistor, a gate electrode of the control transistor is located on a side of an active layer of the control transistor away from an active layer of the driving transistor; or the control transistor is a double-gate transistor, a first gate electrode of the control transistor is located on a side of an active layer of the control transistor away from an active layer of the driving transistor, a second gate electrode of the control transistor is located between the active layer of the control transistor and the active layer of the driving transistor, and the second gate electrode of the control transistor is arranged in a layer different from or the same as the first reset signal line.

[0021] For example, at least one of the embodiments of the present disclosure provides a display substrate, wherein the second gate electrode of the control transistor and the gate electrode of the driving transistor are arranged in a transverse direction; and in the case that the control transistor is a double-gate transistor, a line width of the second gate electrode of the control transistor in the transverse direction is greater than a line width of the first gate electrode of the control transistor in the transverse direction.

[0022] For example, at least one of the embodiments of the present disclosure provides a display substrate, wherein the display substrate comprises a substrate, the driving transistor is arranged on a main surface of the substrate, and the first reset signal line and the gate electrode of the control transistor do not overlap in a direction perpendicular to the main surface of the substrate.

[0023] For example, at least one of the embodiments of the present disclosure provides a display substrate, the pixel circuit further comprising a first light emitting control transistor configured to cause the driving current to be applied to the light emitting device under control of a first light emitting control signal; a material of an active layer of the first light emitting control transistor is the first semiconductor material, and the active layer of the first light emitting control transistor is disposed in a layer different from that of the active layer of the control transistor; an electrode in which the active layer of the compensation transistor is disposed further comprises a second electrode of the compensation transistor, a material of the second electrode of the compensation transistor is a material after the second semiconductor material is made conductive, the second electrode of the compensation transistor is disposed in a layer same as that of the active layer of the compensation transistor and forms an integrated structure; the pixel circuit comprises a first connection structure, the first connection structure, the second electrode of the compensation transistor and the electrode in which the active layer of the control transistor is disposed are all disposed in layers different from each other; the first connection structure is electrically connected to the second electrode of the compensation transistor through a sixth via hole, and is electrically connected to the active layer of the first light emitting control transistor through a seventh via hole.

[0024] For example, at least one of the embodiments of the present disclosure provides a display substrate, the display substrate comprising a substrate, the driving transistor being disposed on a main surface of the substrate; the fifth via hole penetrates the second electrode of the compensation transistor, the first connection structure comprises an inner hole portion in the sixth via hole, a side surface of the inner hole portion is in contact with the second electrode of the compensation transistor, and a surface in which the side surface of the inner hole portion is located intersects with a surface in which the main surface of the substrate is located; or, the fifth via hole exposes an upper surface of the second electrode of the compensation transistor, the upper surface of the second electrode of the compensation transistor is away from the main surface of the substrate, and the first connection structure comprises an inner hole portion in the sixth via hole, a bottom surface of the inner hole portion is in contact with the upper surface of the second electrode of the compensation transistor.

[0025] For example, at least one of the embodiments of the present disclosure provides a display substrate, wherein the pixel circuit further comprises a first light emitting control transistor configured to cause the driving current to be applied to the light emitting device under control of a first light emitting control signal; a material of an active layer of the first light emitting control transistor is the first semiconductor material, and the active layer of the first light emitting control transistor is disposed in a layer different from that of the active layer of the control transistor; an electrode in which the active layer of the compensation transistor is disposed further comprises a second electrode of the compensation transistor, a material of the second electrode of the compensation transistor is a material obtained by conducting the second semiconductor material, the connection portion is disposed in a layer integrated with the active layer of the compensation transistor; the pixel circuit further comprises a second connection structure and a third connection structure, the second electrode of the compensation transistor, the second connection structure, the third connection structure and the active layer of the first light emitting control transistor are disposed in layers different from each other; the second electrode of the compensation transistor is electrically connected to the second connection structure through an eighth via, the third connection structure is electrically connected to the second connection structure through a ninth via, and the third connection structure is electrically connected to the active layer of the first light emitting control transistor through a tenth via.

[0026] For example, at least one of the embodiments of the present disclosure provides a display substrate, wherein the first semiconductor material is a silicon semiconductor material, and the second semiconductor material is a transparent metal oxide semiconductor material.

[0027] For example, at least one of the embodiments of the present disclosure provides a display substrate, wherein the transparent metal oxide semiconductor material comprises indium gallium zinc oxide (IGZO).

[0028] At least one of the embodiments of the present disclosure further provides a display device comprising any one of the display substrates provided by the embodiments of the present disclosure.

[0029] At least one of the embodiments of the present disclosure further comprises a manufacturing method of a display substrate, the manufacturing method comprising: forming a sub-pixel, comprising forming a pixel circuit, wherein the forming the pixel circuit comprises forming a light emitting device and a driving transistor, the driving transistor being configured to control a size of a driving current flowing through the light emitting device according to a data signal; the forming the pixel circuit further comprises: forming a control transistor, wherein a first electrode of the control transistor is electrically connected to a gate electrode of the driving transistor; a material of an active layer of the driving transistor is a first semiconductor material, a material of an active layer of the control transistor is a second semiconductor material, the first semiconductor material being different from the second semiconductor material; an electrode in which the active layer of the control transistor is disposed directly electrically connects the gate electrode of the driving transistor and the first electrode of the control transistor.

[0030] For example, at least one embodiment of the present disclosure provides a manufacturing method of a display substrate, comprising: forming a first type of via hole, wherein the first type of via hole exposes at least an active layer composed of the first semiconductor material; forming a first conductive structure to be electrically connected with a surface of the active layer composed of the first semiconductor material exposed by the first type of via hole through the first type of via hole; performing a high-temperature annealing process on the display substrate after forming the first type of via hole; and performing a low-resistance contact treatment on the surface of the active layer composed of the first semiconductor material exposed by the first type of via hole.

[0031] For example, at least one embodiment of the present disclosure provides a manufacturing method of a display substrate, comprising: forming a second semiconductor layer by a one-time patterning process using the second semiconductor material; conducting a part of the second semiconductor layer to form a second conductive structure, wherein the second conductive structure serves as an electrode of an active layer of a control transistor and comprises a conductive part and a non-conductive part, the conductive part and the non-conductive part form an integrated structure; the non-conductive part constitutes the active layer of the control transistor, the conductive part is directly electrically connected with a gate of the driving transistor and a first electrode of the control transistor, and the material of the conductive part is a material of the second semiconductor material after being conducted; and forming a second type of via hole, the conductive part of the second conductive structure is directly electrically connected with the gate of the driving transistor and the first electrode of the control transistor through the second type of via hole.

[0032] For example, at least one embodiment of the present disclosure provides a manufacturing method of a display substrate, wherein the high-temperature annealing process is performed on the display substrate after forming the second type of via hole and before forming the second conductive structure. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings of the embodiments. Obviously, the drawings described in the following description only relate to some embodiments of the present application, and are not a limitation on the present application.

[0034] FIG. 1 is a plan view of a display substrate according to at least one embodiment of the present disclosure;

[0035] FIG. 2 is a schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0036] FIG. 3 is a partial cross-sectional view of a pixel circuit of a display substrate according to at least one embodiment of the present disclosure;

[0037] FIG. 4 is a partial cross-sectional view of a pixel circuit;

[0038] FIG. 5 is a partial plan view of a pixel circuit;

[0039] FIG. 6 is a schematic cross-sectional view of a partial pixel circuit of another display substrate according to at least one embodiment of the present disclosure;

[0040] FIG. 7 is a schematic cross-sectional view of a partial pixel circuit of yet another display substrate according to at least one embodiment of the present disclosure;

[0041] FIG. 8 is a schematic cross-sectional view of a partial pixel circuit of still another display substrate according to at least one embodiment of the present disclosure;

[0042] FIG. 9 is a schematic cross-sectional view of a partial pixel circuit of another display substrate according to at least one embodiment of the present disclosure;

[0043] FIG. 10 is a schematic cross-sectional view of a partial pixel circuit of another display substrate according to at least one embodiment of the present disclosure;

[0044] FIG. 11 is a schematic cross-sectional view of a partial pixel circuit of another display substrate according to at least one embodiment of the present disclosure;

[0045] FIG. 12 is a schematic cross-sectional view of a partial pixel circuit of another display substrate according to at least one embodiment of the present disclosure;

[0046] FIG. 13 is a schematic view of a display device according to an embodiment of the present disclosure;

[0047] FIGS. 14A-14D are schematic views of a manufacturing method of a display substrate according to an embodiment of the present disclosure;

[0048] FIGS. 15A-15D are schematic views of a manufacturing method of a display substrate according to an embodiment of the present disclosure;

[0049] FIGS. 16A-16D are schematic views of a manufacturing method of a display substrate according to an embodiment of the present disclosure;

[0050] FIGS. 17A-17D are schematic views of a manufacturing method of a display substrate according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] In order to make the objects, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be described clearly and completely below with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the described embodiments of the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present application.

[0052] Unless otherwise defined, technical terms or scientific terms used herein shall have the same meaning to those of a person skilled in the art. The terms "first", "second", and similar terms used herein do not denote any order, quantity, or importance, but are used to distinguish different components. The terms "include", "comprise", and similar terms used herein mean that the elements or objects before the term encompass the elements or objects listed after the term and equivalents thereof, and do not exclude other elements or objects. The terms "inner", "outer", "upper", "lower", and the like are used only to indicate relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0053] The terms in the present disclosure are explained as follows:

[0054] (1) The meaning of the integrated structure: the description that the structure A and the structure B constitute an integrated structure means that the structure A and the structure B have no joint between each other and are a structure of uniform texture, for example, formed by the same patterning process. The letters A and B are used to refer to the corresponding structures described herein.

[0055] (2) The meaning of the same layer arrangement: the relationship between a plurality of structures formed by the same material after the same patterning process. Here, the "same layer arrangement" does not always mean that the thicknesses of the plurality of structures are the same or the heights of the plurality of structures in the cross-sectional view are the same.

[0056] (3) The meaning of the same patterning process: a mask plate is used for a film layer to be patterned by one-time exposure process.

[0057] The drawings in the present disclosure are not strictly drawn according to the actual proportions, and the number of sub-pixels in the substrate is not limited to the number shown in the drawings. The specific size and number of each structure can be determined according to actual needs. The drawings described in the present disclosure are only structural schematic diagrams.

[0058] At least one embodiment of the present disclosure provides a display substrate, which comprises a sub-pixel, the sub-pixel comprises a pixel circuit, the pixel circuit comprises a light emitting device and a driving transistor, the driving transistor is configured to control the size of the driving current flowing through the light emitting device according to a data signal; the pixel circuit further comprises a control transistor, the first electrode of the control transistor is electrically connected with the gate electrode of the driving transistor; the material of the active layer of the driving transistor is a first semiconductor material, the material of the active layer of the control transistor is a second semiconductor material, the first semiconductor material is different from the second semiconductor material; the electrode where the active layer of the control transistor is located is directly electrically connected with the gate electrode of the driving transistor and the first electrode of the control transistor.

[0059] The display device includes any one of the display substrates provided in the embodiments of the present disclosure.

[0060] The display substrate manufacturing method includes forming a sub-pixel, including forming a pixel circuit, wherein the forming of the pixel circuit includes forming a light-emitting device and a driving transistor, the driving transistor is configured to control the size of the driving current flowing through the light-emitting device according to a data signal; the forming of the pixel circuit further includes forming a control transistor, wherein the first electrode of the control transistor is electrically connected with the gate electrode of the driving transistor; the material of the active layer of the driving transistor is a first semiconductor material, the material of the active layer of the control transistor is a second semiconductor material, the first semiconductor material is different from the second semiconductor material; the electrode where the active layer of the control transistor is located is directly electrically connected with the gate electrode of the driving transistor and the first electrode of the control transistor.

[0061] FIG. 1 is a schematic plan view of a display substrate provided in at least one embodiment of the present disclosure. As shown in FIG. 1, for example, the display substrate 10 includes a plurality of pixels 100 arranged in an array, at least part of the plurality of pixels 100 includes a plurality of sub-pixels, at least part of the plurality of sub-pixels includes a light-emitting device and a pixel circuit for driving the light-emitting device to emit light. For example, the pixel circuit can include a 2T1C (i.e., two transistors and one capacitor) pixel circuit, a 4T2C, a 5T1C, a 7T1C, or an nTmC (n, m are positive integers) pixel circuit. For example, in different embodiments, the pixel circuit can also include a compensation sub-circuit, which includes an internal compensation sub-circuit or an external compensation sub-circuit, and the compensation sub-circuit can include transistors, capacitors, etc. For example, the pixel circuit can further include a reset circuit, a light-emitting control sub-circuit, a detection circuit, etc. as needed.

[0062] For example, as shown in FIG. 1, the plurality of pixels 100 are located in a display area. For example, in the display substrate 10 provided in some embodiments, part of the plurality of pixels 100 are dummy pixels 101, which do not participate in display work, and each dummy pixel 101 includes a plurality of dummy sub-pixels without including sub-pixels for display driving.

[0063] For example, the display substrate 10 is an organic light-emitting diode (OLED) display substrate, and the light-emitting device is an OLED. The display substrate 10 can also include a plurality of scan lines and a plurality of data lines for providing scan signals (e.g., gate lines, control signals, as shown in FIG. 5) and data signals to the plurality of sub-pixels, thereby driving the plurality of sub-pixels. As needed, the display substrate 10 can further include a power supply line, a detection line, etc.

[0064] The pixel circuit of the display substrate 10 provided by the embodiments of the present disclosure includes a light emitting device and a driving transistor, the driving transistor is configured to control the size of the driving current flowing through the light emitting device according to a data signal; the pixel circuit further includes a control transistor, a first electrode of the control transistor is electrically connected with a gate electrode of the driving transistor; the material of the active layer of the driving transistor is a first semiconductor material, the material of the active layer of the control transistor is a second semiconductor material, the first semiconductor material is different from the second semiconductor material; the electrode where the active layer of the control transistor is located is directly electrically connected with the gate electrode of the driving transistor and the first electrode of the control transistor, that is, the electrode where the active layer of the control transistor is located serves as a connection line electrically connecting the gate electrode of the driving transistor and the first electrode of the control transistor.

[0065] It should be noted that the "the electrode where the active layer of the control transistor is located is directly electrically connected with the gate electrode of the driving transistor and the first electrode of the control transistor" means that the electrode where the active layer of the control transistor is located is directly in contact with the gate electrode of the driving transistor and the first electrode of the control transistor, so as to electrically connect the gate electrode of the driving transistor and the first electrode of the control transistor, instead of indirectly electrically connecting the gate electrode of the driving transistor and the first electrode of the control transistor via other conductive structures (for example, conductive structures located in other layers).

[0066] Exemplarily, FIG. 2 is a schematic diagram of a pixel circuit provided by at least one embodiment of the present disclosure, and here, a 7T1C pixel circuit shown in FIG. 2 is taken as an example to introduce the structure of a sub-pixel of a display substrate.

[0067] Referring to FIG. 2, the pixel circuit includes a light emitting device EL and a driving transistor T3, the driving transistor T3 is configured to control the size of the driving current flowing through the light emitting device EL according to a data signal Vd. For example, the pixel circuit includes a first reset transistor T1, the first reset transistor T1 is configured to write a first reset signal Vinit1 to the gate electrode T3g of the driving transistor T3 under the control of a first reset control signal Rst1. For example, the first reset signal Vinit1 and a second reset signal Vinit2 are the same signal, come from the same reset signal line connected with the same reset signal terminal, so that one reset signal line can be saved. Of course, the first reset signal Vinit1 and the second reset signal Vinit2 can also be two independent signals.

[0068] Figure 3 is a cross-sectional schematic view of a partial pixel circuit of a display substrate according to at least one embodiment of the present disclosure. In combination with Figure 2 and Figure 3, for example, the control transistor includes a first reset transistor T1, and an electrode ET in which the active layer T1a of the first reset transistor T1 is located is directly electrically connected to the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1. The electrode ET in which the active layer T1a of the first reset transistor T1 is located is an integrated structure, and includes the active layer T1a of the first reset transistor T1 and other parts, i.e., the active layer T1a of the first reset transistor T1 and the other parts constitute the electrode ET of the integrated structure. In this case, the material of the active layer T3a of the driving transistor T3 is a first semiconductor material, and the material of the active layer T1a of the first reset transistor T1 is a second semiconductor material. The electrode ET in which the active layer T1a of the first reset transistor T1 is located further includes a conductive portion, the conductive portion constitutes an integrated structure with the active layer T1a of the first reset transistor T1, and the conductive portion includes the first electrode T1s of the first reset transistor T1, for example, the first electrode T1s of the first reset transistor T1 is adjacent to the active layer T1a of the first reset transistor T1 and constitutes an integrated structure, and the conductive portion is in contact with the gate T3g of the driving transistor T3, thereby realizing that the first electrode T1s of the first reset transistor T1 is electrically connected to the active layer T1a of the first reset transistor T1 and is electrically connected to the gate T3g of the driving transistor T3. For example, the material of the conductive portion is the material of the second semiconductor material after being made conductive.

[0069] FIG. 4 is a schematic cross-sectional view of a partial pixel circuit (FIG. 4 does not represent the prior art, FIG. 4 is a design made by the inventor based on the structure of the pixel circuit of the display substrate provided in the embodiments of the present application, but the connection design of the control transistor and other transistors is different from that in the embodiments of the present application). The circuit diagram of the pixel circuit shown in FIG. 4 can be the same as that shown in FIG. 2, however, in the pixel circuit shown in FIG. 4, the first reset transistor T1 includes double gates T10g1 and T10g2, an active layer T10a, a first electrode and a second electrode, the active layer T10a of the first reset transistor T1 is electrically connected with the gate T30g of the driving transistor T3 through a first connection structure S1, the first connection structure S1 serves as the first electrode of the first reset transistor T1; the first connection structure S1 and the active layer T10a of the first reset transistor T1 and the gate T30g of the driving transistor T3 are all located in different layers, for example, the first connection structure S1 is located on the side away from the substrate 010 of both the active layer T10a of the first reset transistor T1 and the gate T30g of the driving transistor, and the first connection structure S1 is electrically connected with the active layer T10a of the first reset transistor T1 and the gate T30g of the driving transistor T3 through two kinds of vias respectively. For example, the first connection structure S1 is often arranged in the same layer as the data line providing the data signal. In FIG. 4, the first connection structure S1 also electrically connects the gate T30g of the driving transistor T3 and the active layer T20a of the compensation transistor T2, and is reused as the first electrode of the compensation transistor T2. The compensation transistor T2 includes double gates T20g1 and T20g2. In FIG. 4, the second electrode of the first reset transistor T1 is electrically connected with the active layer T10a of the first reset transistor T1 and the first reset signal line LVinitial0 through two kinds of vias respectively through a second connection structure S2. The second connection structure S2 is arranged in the same layer as the first connection structure S1 or in a different layer, however, the second connection structure S2 and the first connection structure S1 are both provided with an insulating layer between the active layer T10a of the first reset transistor T1, between the first reset signal line LVinitial0, and between the active layer T20a of the compensation transistor T2, and are conductive structures provided outside the layers where the active layer T10a of the first reset transistor T1, the first reset signal line LVinitial0 and the active layer T20a of the compensation transistor T2 are respectively located, to realize the electrical connection between the above three or the electrical connection between the above three and other structures through these conductive structures.

[0070] In the display substrate provided by the embodiment of the present disclosure, the electrode ET where the active layer T1a of the first reset transistor T1 with the conductorized part is located is directly electrically connected with the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1. Thus, compared with the structure of the pixel circuit shown in FIG. 4, the display substrate provided by the embodiment of the present disclosure can at least achieve the following technical effects. On the one hand, in the display substrate provided by the embodiment of the present disclosure, the electrode ET where the active layer T1a of the first reset transistor T1 is located is reused as a connection electrode to realize the electrical connection between the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1, and a special connection electrode does not need to be additionally arranged on other layers (for example, the conductive layer SD1 on the side of the active layer T1a of the first reset transistor T1 away from the substrate BS) to realize the electrical connection between the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1 through at least two vias by using the connection electrode, so that the structure of the pixel circuit is greatly simplified. On the other hand, in the display substrate provided by the embodiment of the present disclosure, other signal lines such as a data line for providing a data signal Vd or a connection electrode for electrical connection between other elements of the pixel circuit can be arranged on other layers (for example, the conductive layer SD1), and a connection electrode does not need to be arranged to connect the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1, so that the number of conductive structures arranged on the other layers is reduced, the number of connection vias is reduced, the process of manufacturing the vias is simplified, the design difficulty is reduced, the yield of the display panel is improved, and the density of the conductive structures arranged on the other layers (for example, the conductive layer SD1) is reduced, the parasitic capacitance caused by the over-density of the conductive structures is reduced, and the display quality is improved.

[0071] For example, the first semiconductor material is a silicon semiconductor material, and the second semiconductor material is a transparent metal oxide semiconductor material. For example, the transparent metal oxide semiconductor material includes indium gallium zinc oxide (IGZO). In this case, the display substrate 10 is an LTPO display substrate integrating oxide transistors (Oxide TFTs) and low-temperature polysilicon transistors (LTPS TFTs), has the advantage of low-frequency driving, and can reduce the power consumption of the display product. Of course, the first semiconductor material and the second semiconductor material are not limited to the types listed above, and the specific types of the first semiconductor material and the second semiconductor material are not limited in the embodiment of the present disclosure.

[0072] In combination with FIGS. 2 and 3, for example, the electrode ET where the active layer T1a of the first reset transistor T1 is located includes the first electrode T1s of the first reset transistor T1 and is electrically connected with the gate T3g of the driving transistor T3 through the first via V1.

[0073] In combination with FIG. 2 and FIG. 3, the electrode ET where the active layer T1a of the first reset transistor T1 is located includes the active layer T1a of the first reset transistor T1 and the first electrode T1s of the first reset transistor T1, and the conductorized part of the electrode ET where the active layer T1a of the first reset transistor T1 is located includes the first electrode T1s of the first reset transistor T1; for example, the material of the first electrode T1s of the first reset transistor T1 is the material of the second semiconductor material after being conductorized, the active layer T1a of the first reset transistor T1 and the first electrode T1s of the first reset transistor T1 are arranged in the same layer and constitute an integrated structure, that is, the material of the conductorized part of the electrode ET where the active layer T1a of the first reset transistor T1 is located is the material of the second semiconductor material after being conductorized, the first electrode T1s of the first reset transistor T1 belongs to the conductorized part of the electrode ET where the active layer T1a of the first reset transistor T1 is located, and the active layer T1a of the first reset transistor T1 is the part that is not conductorized. For example, the gate T3g of the driving transistor T3 is arranged in a layer different from the electrode ET where the active layer T1a of the first reset transistor T1 is located, and the first electrode T1s of the first reset transistor T1 contacts the gate T3g of the driving transistor T3 through the first via V1 to expose the gate T3g of the driving transistor T3, so as to directly electrically connect the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1. In this way, for example, the conductorized part of the electrode ET where the active layer T1a of the first reset transistor T1 is located only needs to be electrically connected with the gate T3g of the driving transistor T3 through the first via V1, and the active layer T1a of the first reset transistor T1 and the active layer T1a of the first reset transistor T1 constitute an integrated structure, so as to electrically connect the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1, without the need to additionally arrange a connection structure in other layers through at least two vias to be electrically connected with the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1, respectively, so as to fully utilize the electrode EL where the material of the active layer T1a of the first reset transistor T1 is located, simplify the structure of the sub-pixel, reduce the connection wiring, and thus also increase the light transmittance; and further reduce the number of conductive structures arranged in the other layers, which is conducive to reducing the design difficulty, reducing the density of the conductive structures arranged in the other layers, and reducing the parasitic capacitance caused by the over-density of the conductive structures.

[0074] For example, referring to FIGS. 2 and 3, the electrode ET in which the active layer T1a of the first reset transistor T1 is located also includes the second electrode T1d of the first reset transistor T1, the material of the second electrode T1d of the first reset transistor T1 is also the material of the second semiconductor material after being conductorized, and the second electrode T1d of the first reset transistor T1 also belongs to the conductorized part of the electrode ET in which the active layer T1a of the first reset transistor T1 is located; the pixel circuit further includes a first reset signal line LVini1 which is arranged in a layer different from the second electrode T1d of the first reset transistor T1, and the second electrode T1d of the first reset transistor T1 is in contact with the first reset signal line LVini1 through the second via V2 which exposes the first reset signal line LVini1 to directly electrically connect the first reset signal line LVini1. In this way, the second electrode T1d (the material of the second semiconductor material after being conductorized) of the first reset transistor T1 only needs to be electrically connected with the first reset signal line LVini1 through the second via V2. It is not necessary to additionally arrange a connection junction (for example, the second connection structure S2 in FIG. 4) in other layers to be electrically connected with the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1 through at least two vias, which makes full use of the electrode EL in which the material of the active layer T1a of the first reset transistor T1 is located, simplifies the structure of the sub-pixel, reduces the connection wiring, and thus also increases the light transmittance; and further reduces the number of conductive structures arranged in the other layers, and reduces the number of connection vias, so as to simplify the process of manufacturing the vias, which is conducive to reducing the design difficulty and improving the yield of the display panel, and at the same time, reduces the density of the conductive structures arranged in the other layers, and reduces the parasitic capacitance caused by the over-density of the conductive structures.

[0075] For example, referring to FIG. 3, the active layer T3a of the driving transistor T3 is arranged in a layer different from the active layer T1a of the first reset transistor T1, and the gate T3g of the driving transistor T3 is located between the active layer T3a of the driving transistor T3 and the electrode ET in which the active layer T1a of the first reset transistor T1 is located, that is, the gate T3g of the driving transistor T3 is located on the side of the active layer T3a of the driving transistor T3 close to the electrode ET in which the active layer T1a of the first reset transistor T1 is located, so as to facilitate the contact between the gate T3g of the driving transistor T3 and the conductorized part of the electrode ET in which the active layer T1a of the first reset transistor T1 is located during the manufacturing process of the display substrate, while not affecting the function of the driving transistor T3.

[0076] For example, referring to FIG. 3, the display substrate includes a substrate BS, and a driving transistor T3 is disposed on a main surface of the substrate BS; an active layer T3a of the driving transistor T3 is located on a side of an active layer Tla of the first reset transistor Tl close to the substrate BS. That is, the active layer of the oxide transistor (Oxide TFT) is on the top, and the active layer of the low-temperature polysilicon transistor (LTPS TFT) is on the bottom, where the direction "bottom" is closer to the substrate BS than the direction "top", so that in the manufacturing process of the display substrate, the active layer of the low-temperature polysilicon transistor (LTPS TFT) is formed first, and then the active layer of the oxide transistor (Oxide TFT) is formed, so as to avoid the process of manufacturing the active layer of the low-temperature polysilicon transistor (LTPS TFT) after the active layer (for example, IGZO) of the oxide transistor (Oxide TFT) is formed, which affects the performance of the oxide transistor (Oxide TFT).

[0077] For example, referring to FIG. 2 and FIG. 4, the pixel circuit further comprises a compensation transistor T2 configured to compensate the signal applied to the gate T3g of the driving transistor T3 in response to a compensation scan signal and the data signal Vd. For example, the control transistor further comprises the compensation transistor T2, and the electrode ET where the active layer T2a of the compensation transistor T2 is located is directly electrically connected with the gate T3g of the driving transistor T3 and the first pole T2s of the compensation transistor T2. The electrode ET where the active layer T2a of the compensation transistor T2 is located is an integrated structure, and comprises the active layer T2a of the compensation transistor T2 and other parts constituting the integrated structure. In this case, the material of the active layer T3a of the driving transistor T3 is the first semiconductor material, and the material of the active layer T2a of the compensation transistor T2 is the second semiconductor material. For example, the electrode ET where the active layer T2a of the compensation transistor T2 is located further comprises a conductorized part constituting an integrated structure with the active layer T2a of the compensation transistor T2, and the conductorized part is respectively in contact with the first pole T2s of the compensation transistor T2 and the gate T3g of the driving transistor T3 to achieve electrical connection with the two. For example, the material of the conductorized part is the material of the second semiconductor material after being conductorized. In this way, the electrode ET where the active layer T2a of the compensation transistor T2 with the conductorized part is located is directly electrically connected with the gate T3g of the driving transistor T3 and the first pole T1s of the first reset transistor T1, on the one hand, the electrode ET where the active layer T1a of the first reset transistor T1 is located can be multiplexed as a connection electrode to achieve electrical connection between the gate T3g of the driving transistor T3 and the first pole T2s of the compensation transistor T2, without the need to additionally provide a dedicated connection electrode in other layers (for example, a conductive layer on the side of the active layer T2a of the compensation transistor T2 away from the substrate BS) to electrically connect the gate T3g of the driving transistor T3 and the first pole T2s of the compensation transistor T2 through at least two vias, thereby simplifying the structure of the pixel circuit; on the other hand, other signal lines such as data lines providing data signals Vd or connection electrodes for electrical connection between other elements of the pixel circuit can be provided in the other layers, without the need to additionally provide a connection electrode to connect the gate T3g of the driving transistor T3 and the first pole T1s of the first reset transistor T1, thereby reducing the number of conductive structures provided in the other layers, facilitating the reduction of design difficulty, reducing the density of conductive structures provided in the other layers, reducing the parasitic capacitance caused by the over-density of conductive structures, and improving the display quality.

[0078] For example, referring to FIG. 3, the electrode ET in which the active layer T2a of the compensation transistor T2 is located includes the active layer T2a of the compensation transistor T2 and the first electrode T2s of the compensation transistor T2, the materials of the active layer T2a of the compensation transistor T2 and the first electrode T2s of the compensation transistor T2 are both materials of the second semiconductor material after being conductorized, both belong to the conductorized part of the electrode ET in which the active layer T2a of the compensation transistor T2 is located, the active layer T2a of the compensation transistor T2 and the first electrode T2s of the compensation transistor T2 are arranged in the same layer and constitute an integrated structure; the gate T3g of the driving transistor T3 is arranged in a layer different from the electrode in which the active layer T2a of the compensation transistor T2 is located, and the first electrode T2s of the compensation transistor T2 contacts the gate T3g of the driving transistor T3 through the third via V3 to directly electrically connect the gate T3g of the driving transistor T3 and the first electrode T2s of the compensation transistor T2.

[0079] For example, in the embodiment shown in FIG. 3, the electrode ET in which the active layer T2a of the compensation transistor T2 is located is arranged in the same layer and constitutes an integrated structure with the electrode ET in which the active layer T1a of the first reset transistor T1 is located, that is, the electrode ET in which the active layer T2a of the compensation transistor T2 is located is the same electrode as the electrode ET in which the active layer T1a of the first reset transistor T1 is located, the first electrode T1s of the first reset transistor T1 and the first electrode T2s of the compensation transistor T2 are integrated, and the first via V1 and the third via V3 are the same via. The electrode ET in which the active layer T2a of the compensation transistor T2 is located further includes the first electrode T2s of the compensation transistor T2, the material of the active layer T2a of the compensation transistor T2 is the second semiconductor material, the material of the first electrode T2s of the compensation transistor T2 is the material of the second semiconductor material after being conductorized, and the first electrode T1s of the first reset transistor T1, the first electrode T2s of the compensation transistor T2, and the active layer T2a of the compensation transistor T2 are sequentially connected, arranged in the same layer, and constitute an integrated structure.

[0080] For example, as shown in FIG. 3, the first electrode T1s of the first reset transistor T1 is adjacent to and integrally formed with the first electrode T2s of the compensation transistor T2 to constitute a conductive connection part CS, that is, the conductorized part of the electrode ET in which the active layer of the control transistor is located includes the conductive connection part CS, and the conductive connection part CS is electrically connected with the gate T3g of the driving transistor T3 through the third via V3.

[0081] In the embodiment shown in FIG. 3, the same electrode ET including the active layer of the control transistor and the conductorized portion is used to realize the electrical connection of the gate T3g of the driving transistor T3 and the first pole T1s of the first reset transistor T1, the electrical connection of the gate T3g of the driving transistor T3 and the first pole T2s of the compensation transistor T2, and the electrical connection of the second pole T1d of the first reset transistor T1 and the first reset signal line LVini1, the active layer including the control transistor is fully utilized, the number and density of the conductive structures for connecting the respective transistors, capacitors and other elements of the sub-pixel provided in other layers (for example, the conductive layer on the side of the active layer T1a of the first reset transistor T1 away from or close to the substrate BS) are greatly reduced, thereby greatly reducing the design difficulty, and also reducing the parasitic capacitance caused by the excessive density of the conductive structures in the other layers, and improving the display quality of the display substrate.

[0082] Of course, in other embodiments, the gate T3g of the driving transistor T3 can be electrically connected with the first pole T1s of the first reset transistor T1, but not with the first pole T2s of the compensation transistor T2; or the gate T3g of the driving transistor T3 is electrically connected with the first pole T2s of the compensation transistor T2, but not with the first pole T1s of the first reset transistor T1. The above-mentioned several ways can achieve the above technical effects of the display substrate provided by the present application to different degrees, and solve the corresponding technical problems.

[0083] Referring to FIG. 2, the pixel circuit further includes a first light-emitting control transistor T6 configured to cause a driving current to be applied to the light-emitting device EL under the control of a first light-emitting control signal EM1. Referring to FIG. 3, the material of the active layer T6a of the first light-emitting control transistor T6 is the first semiconductor material (silicon semiconductor material) described above, and the active layer T6a of the first light-emitting control transistor T6 is disposed in a layer different from the active layer of the control transistor (the active layer T1a of the first reset transistor T1 and / or the compensation transistor T2); the electrode in which the active layer T2a of the compensation transistor T2 is located further includes a connection portion C1, the material of the connection portion C1 is the material of the second semiconductor material after being conductorized, and the connection portion C1 is disposed in the same layer as the active layer T2a of the compensation transistor T2 and forms an integrated structure; the connection portion C1 contacts the active layer T6a of the first light-emitting control transistor T6 through the fourth via V4 exposing the active layer T6a of the first light-emitting control transistor T6 to electrically connect with the active layer T6a of the first light-emitting control transistor T6, thereby the connection portion C1 serving as the first pole T6s of the first light-emitting control transistor T6 and the second pole T2d of the compensation transistor T2.

[0084] For example, referring to FIG. 3, the active layer T6a of the first light emitting control transistor T6 and the active layer T3a of the driving transistor T3 are arranged in the same layer, and / or the gate T3g of the driving transistor T3 and the gate T6g of the first light emitting control transistor T6 are arranged in the same layer, so as to form the active layer T6a of the first light emitting control transistor T6 and the active layer T3a of the driving transistor T3 by the same patterning process on the same semiconductor layer (the first semiconductor material), and form the gate T3g of the driving transistor T3 and the gate T6g of the first light emitting control transistor T6 by the same patterning process on the same conductive layer.

[0085] For example, referring to FIG. 3, the active layer T6a of the first light emitting control transistor T6 is made of the first semiconductor material, and the active layer T6a of the first light emitting control transistor T6 is arranged in a layer different from the active layer of the control transistor (the active layer T1a of the first reset transistor T1 and / or the active layer of the compensation transistor T2); the electrode ET in which the active layer of the control transistor is arranged is arranged in a layer different from the second electrode T6d of the first light emitting control transistor T6, the electrode ET in which the active layer of the control transistor is arranged is in contact with the active layer T6a of the first light emitting control transistor T6 through the fourth via V4 exposing the active layer T6a of the first light emitting control transistor T6, and the second electrode T6d of the first light emitting control transistor T6 is in contact with the active layer T6a of the first light emitting control transistor T6 through the fifth via V5 exposing the active layer T6a of the first light emitting control transistor T6. For example, the second electrode T6d of the first light emitting control transistor T6 is located in the conductive layer SD1, so as to reduce the wiring of the conductive layer SD1, avoid the need to make a detour in the conductive layer SD1 to avoid structures in the same layer, reduce the design difficulty of the conductive layer SD1, and avoid parasitic capacitance.

[0086] For example, referring to FIG. 3, the second electrode T6d of the first light emitting control transistor T6 is located on the side of the electrode ET in which the active layer of the control transistor is arranged away from the substrate BS, i.e., the conductive layer SD1 is located on the side of the electrode ET in which the active layer of the control transistor is arranged away from the substrate BS, so as to avoid the second electrode T6d of the first light emitting control transistor T6 being located between the electrode ET in which the active layer of the control transistor is arranged and the gate T6g of the first light emitting control transistor T6, thereby avoiding interference with the arrangement of the electrode ET in which the active layer of the control transistor is arranged and the gate T6g of the first light emitting control transistor T6, reducing the layout difficulty, reducing the difficulty of the manufacturing process, optimizing the above-mentioned performance of the pixel circuit, reducing the difficulty of the manufacturing process, and being very important for ensuring the yield of the product.

[0087] For example, the data line providing the above-mentioned data signal Vd is also located in the conductive layer SD1, i.e., is arranged in the same layer as the second electrode T6d of the first light-emitting control transistor T6. In the embodiments of the present disclosure, at least the connection electrode for electrically connecting the active layer of the first reset transistor T1 and the gate of the driving transistor T3, the connection electrode for electrically connecting the active layer of the first reset transistor T1 and the gate of the driving transistor T3, and the connection electrode for electrically connecting the active layer of the first reset transistor and the first reset signal line are not present in the conductive layer SD1, thereby greatly reducing the number of electric lines or conductive structures in the conductive layer SD1, reducing the density of the electric lines or conductive structures arranged in the conductive layer SD1, reducing the parasitic capacitance caused by the excessive density of the conductive structures, and improving the display quality.

[0088] For example, in the embodiment shown in FIG. 3, the first reset signal line LVini1 is arranged in a layer different from the second electrode T6d of the first light emitting control transistor T6, so as to avoid that the first reset signal line LVini1 is arranged in the conductive layer SD1 and needs to avoid other conductive structures and has a winding design, i.e., winding around other structures to avoid intersection with other conductive structures. For example, FIG. 5 is a schematic view of a planar structure of a pixel circuit, and the circuit diagram of the pixel circuit can be, for example, the equivalent circuit shown in FIG. 2. The schematic view of the planar structure of the pixel circuit in the rectangular dashed box in FIG. 5 is a sub-pixel unit. Referring to FIG. 5, the first scan line LGa1 provides the first scan signal Ga1 (data scan signal) in FIG. 2, the second scan line LGa2 provides the second scan signal Ga2 (compensation scan signal) in FIG. 2, the light emitting control scan line LEM provides the first light emitting control signal EM1 and the second light emitting control signal EM2 in FIG. 2, the first reset scan line LRst1 provides the first reset scan signal Rst1 in FIG. 2, and the second reset scan line LRst2 provides the second reset scan signal Rst2 in FIG. 2. The first reset signal line LV1 is arranged in the same layer as the first connection electrode S1 (i.e., the first connection electrode S1 in FIG. 4) that implements the first node N1 in FIG. 2. In order to avoid the first connection electrode S1, the first reset signal line LV1 includes a winding design, i.e., winding up and then extending to the right, including a winding part R. The above scheme shown in FIG. 5, on the one hand, increases the parasitic capacitance between the conductive layer SD1 and other conductive layers, and on the other hand, the first reset signal line LV1 needs to pass directly above the channel region of the first reset transistor T1 (near the position indicated by T1 in FIG. 5) due to wiring difficulties, which affects the switching characteristics of the first reset transistor T1. However, in the display substrate provided by the embodiments of the present application, the electrode ET (the conductorized part of the electrode ET where the active layer of the control transistor is located) directly electrically connects the gate T3g of the driving transistor T3 and the first electrode of the control transistor, and there is no need to additionally arrange a conductorized part in the conductive layer SD1 for electrically connecting the gate T3g of the driving transistor T3 and the electrode ET where the active layer of the control transistor is located, thereby reducing the number and density of conductive structures in the conductive layer SD1 and improving the technical problem that the density of conductive structures in the conductive layer SD1 is too large, which causes winding and then causes the parasitic capacitance to be too large and affects the switching characteristics of the first reset transistor T1. Further, since the first reset signal line LVini1 is arranged in a layer different from the second electrode T6d of the first light emitting control transistor T6, the above technical problem can be further improved.

[0089] For example, referring to FIG. 3, the first reset signal line LVini1 and the gate T3g of the driving transistor T3 are both located between the active layer T3a of the driving transistor T3 and the electrode ET where the active layer of the control transistor (the active layer T1a of the first reset transistor T1 and / or the active layer T2a of the compensation transistor T2) is located. For example, referring to FIG. 3, the first reset signal line LVini1 is located in a layer different from the gate T3g of the driving transistor T3, so as to avoid the density of conductive structures in the conductive layers where the two are located being too high, especially for a display substrate with high PPI, the space for each sub-pixel is more limited, so that the structure of the pixel circuit can meet the requirements of a display substrate with higher PPI. For example, the gate T3g of the driving transistor T3 is located in the first conductive layer Gate1, and the first reset signal line LVini1 is located in the second conductive layer Gate2, and the second conductive layer Gate2 is located on the side of the first conductive layer Gate1 away from the substrate BS, so that in the direction perpendicular to the main surface of the substrate BS, the second conductive layer Gate2 is closer to the electrode ET where the active layer T1a of the first reset transistor T1 is located, so that the active layer T1a of the first reset transistor T1 is in contact with the first reset signal line LVini1 located in the second conductive layer Gate2 through the second via V2 to be electrically connected.

[0090] Alternatively, in other embodiments, the first reset signal line LVini1 and the gate T3g of the driving transistor T3 can also be located in the same layer.

[0091] For example, in the embodiment shown in FIG. 3, the control transistor is a double-gate transistor, for example, the first reset transistor T1 and the compensation transistor T2 are both double-gate transistors, the first reset transistor T1 includes a first gate T1g1 and a second gate T1g2, and the compensation transistor T2 includes a first gate T2g1 and a second gate T2g2. Of course, at least one of the first reset transistor T1 and the compensation transistor T2 is a double-gate transistor, the first gate of the control transistor (the first gate T1g1 of the first reset transistor T1 and / or the first gate T2g1 of the compensation transistor T2) is located on the side of the active layer of the control transistor away from the active layer T3a of the driving transistor T3, for example, in the third conductive layer Gate3; the second gate of the control transistor (the first gate T1g1 of the first reset transistor T1 and / or the second gate T2g2 of the compensation transistor T2) is located between the active layer of the control transistor (the active layer T1a of the first reset transistor T1 and / or the active layer T2a of the compensation transistor T2) and the active layer T3a of the driving transistor T3, and the second gate of the control transistor (the first gate T1g1 of the first reset transistor T1 and / or the second gate T2g2 of the compensation transistor T2) is located in the same layer as the first reset signal line LVini1, for example, both are located in the second conductive layer Gate2.

[0092] Alternatively, in other embodiments, the second gate of the control transistor and the first reset signal line LVini1 can be arranged in different layers.

[0093] For example, referring to FIG. 3, the second gate T1g2 of the first reset transistor T1 and / or the second gate T2g2 of the compensation transistor T2 and the gate T3g of the driving transistor T3 are arranged in a lateral direction, which is parallel to the main surface of the substrate BS, i.e., the second gates of the control transistors and the gate T3g of the driving transistor T3 are arranged in the lateral direction; in the case that the control transistor is a double-gate transistor, the line width of the second gate of the control transistor in the lateral direction is greater than the line width of the first gate of the control transistor in the lateral direction. For example, the line width of the second gate T1g2 of the first reset transistor T1 in the lateral direction is greater than the line width of the first gate T1g1 of the first reset transistor T1 in the lateral direction, and the line width of the second gate T2g2 of the compensation transistor T2 in the lateral direction is greater than the line width of the first gate T2g1 of the compensation transistor T2 in the lateral direction.

[0094] For example, referring to FIG. 3, the first reset signal line LVini1 and the gate of the control transistor do not overlap in a direction perpendicular to the main surface of the substrate BS to prevent parasitic capacitance caused by the overlap of the two in the direction perpendicular to the main surface of the substrate BS.

[0095] For example, referring to FIG. 3, the display substrate further includes a first flexible layer PI1, a second flexible layer PI2, a first barrier layer Barrier1, a second flexible layer PI2, a second barrier layer Barrier2-1, a bottom shielding electrode BSM, a third barrier layer Barrier2-2, a first buffer layer Buffer1, a first gate insulating layer GI1, a second gate insulating layer GI2, a first interlayer insulating layer ILD1, a second buffer layer Buffer2, a third gate insulating layer GI3, and a second interlayer insulating layer ILD2 arranged on the substrate BS. Each insulating layer directly insulates each conductive layer, and each buffer layer can isolate impurities from a film layer formed on the corresponding buffer layer. The materials of the first flexible layer PI1 and the second flexible layer PI2 are, for example, polyimide (PI) so that the display substrate is a flexible substrate. In a substrate including polyimide (PI), there are movable fixed charges. When the gate voltage of the driving transistor T3 changes, the movable charges move up and down with the change of the electric field formed by the gate voltage of the driving transistor T3, forming a built-in electric field that changes with the gate voltage of the driving transistor T3, which further affects the characteristics of the driving transistor T3 and the display quality of the display substrate. After a fixed voltage is applied to the bottom shielding electrode BSM, the influence of the fixed charges in the polyimide (PI) on the characteristics of the driving transistor T3 can be shielded, thereby improving the display quality. For example, the bottom shielding electrode BSM is connected to the first voltage signal VDD.

[0096] FIG. 6 is a schematic view of a cross section of a part of a pixel circuit of another display substrate according to an embodiment of the present disclosure. The technical solution of FIG. 6 is different from the technical solution of FIG. 3 in the following aspects.

[0097] Referring to FIG. 6, the electrode ET in which the active layer T2a of the compensation transistor T2 is located further includes the second electrode T2d of the compensation transistor T2, the material of the second electrode T2d of the compensation transistor T2 is the material of the second semiconductor material after being made conductive, and the second electrode T2d of the compensation transistor T2 is arranged in the same layer as the active layer T2a of the compensation transistor T2 and forms an integrated structure; the pixel circuit includes a first connection structure CS1, the first connection structure CS1, the second electrode T2d of the compensation transistor T2, and the electrode ET in which the active layer of the control transistor is located are all arranged in different layers from each other; for example, the first connection structure CS1 is arranged in the same layer as the second electrode T6d of the first light-emitting control transistor T6, for example, both are located in the conductive layer SD1. The first connection structure CS1 is electrically connected to the second electrode T2d of the compensation transistor T2 through the sixth via hole V6 and is electrically connected to the active layer T6a of the first light-emitting control transistor T6 through the seventh via hole V7. In the embodiment shown in FIG. 6, the electrode ET in which the active layer of the control transistor is located is directly electrically connected to the gate T3g of the driving transistor T3 and the first electrode of the control transistor, which can greatly simplify the structure of the pixel circuit, and without the need to additionally arrange a connection electrode in other layers to connect the gate T3g of the driving transistor T3 and the first electrode of the control transistor, thereby reducing the number of conductive structures arranged in the other layers, and in the embodiment shown in FIG. 6, the first connection structure CS1 is in contact with the second electrode T2d of the compensation transistor T2 and the active layer T6a of the first light-emitting control transistor T6 through the sixth via hole V6 and the seventh via hole V7, respectively, to electrically connect the two, the material of the first connection structure CS1 can be a common conductive material, for example, a metal conductive material, for example, aluminum, copper, chromium, and the like, and an alloy thereof, and the problem of a large contact resistance caused by the direct contact between the conductive part of the electrode ET composed of the conductive IGZO and the P-Si can also be avoided, thereby making the display uniformity of the pixel array of the display substrate good and improving the display effect.

[0098] Referring to FIG. 6, for example, the sixth via hole V6 penetrates the second electrode T2d of the compensation transistor T2 in a direction perpendicular to the main surface of the substrate BS, and the first connection structure CS1 includes an in-hole portion PIV located in the hole, the side surface of the in-hole portion PIV is in contact with the second electrode T2d of the compensation transistor T2 to electrically connect the second electrode T2d of the compensation transistor T2, and the face in which the side surface of the in-hole portion PIV is located intersects with the face in which the main surface of the substrate BS is located, that is, the face of the in-hole portion PIV in contact with the hole wall of the hole penetrating the second electrode T2d of the compensation transistor T2. The first connection structure CS1 is electrically connected to the second electrode T2d of the compensation transistor T2 in a side lap manner in FIG. 6.

[0099] The other features and corresponding technical effects of the embodiment shown in FIG. 6 are the same as those in FIG. 3, and reference can be made to the previous description.

[0100] FIG. 7 is a schematic cross-sectional view of a partial pixel circuit of a display substrate according to at least one embodiment of the present disclosure. The technical solution of FIG. 7 is different from the technical solution of FIG. 6 in the following aspects.

[0101] Referring to FIG. 7, the sixth via V6 exposes the upper surface of the second electrode T2d of the compensation transistor T2, the upper surface of the second electrode T2d of the compensation transistor T2 is away from the main surface of the substrate BS, and the first connection structure CS1 includes an in-hole portion PIV located in the hole of the sixth via V6, the bottom surface (the surface facing the substrate BS) of the in-hole portion PIV is in contact with the upper surface of the second electrode T2d of the compensation transistor T2 to be electrically connected with the second electrode T2d of the compensation transistor T2. The first connection structure CS1 is electrically connected with the second electrode T2d of the compensation transistor T2 in a bottom lap joint manner in FIG. 7.

[0102] On the basis of the technical effects achieved by the embodiment of FIG. 3, the display substrate shown in FIG. 7 can also avoid the problem of large contact resistance caused by the direct contact and electrical connection between the conductive part of the electrode ET composed of the conductive IGZO and the P-Si, thereby making the display uniformity of the pixel array of the display substrate good and improving the display effect.

[0103] The other features and corresponding technical effects of the embodiment shown in FIG. 7 are the same as those in FIG. 6 or FIG. 3, and reference can be made to the previous description.

[0104] FIG. 8 is a schematic cross-sectional view of a partial pixel circuit of a display substrate according to at least one embodiment of the present disclosure. The technical solution of FIG. 8 is different from the technical solution of FIG. 6 in the following aspects.

[0105] Referring to FIG. 8, the material of the active layer T6a of the first light-emitting control transistor T6 is the first semiconductor material, and the active layer T6a of the first light-emitting control transistor T6 is arranged in a layer different from the active layer of the control transistor; the electrode ET in which the active layer T2a of the compensation transistor T2 is located further includes the second electrode T2d of the compensation transistor T2, the material of the second electrode T2d of the compensation transistor T2 is the material of the second semiconductor material after being made conductive, that is, the conductive part of the electrode ET includes the second electrode T2d of the compensation transistor T2; the second electrode T2d of the compensation transistor T2 is arranged in the same layer as the active layer T2a of the compensation transistor T2 and forms an integrated structure; the pixel circuit includes a second connection structure CS2 and a third connection structure CS3, the second electrode T2d of the compensation transistor T2, the second connection structure CS2, the third connection structure CS3, and the active layer T6a of the first light-emitting control transistor T6 are all arranged in different layers from each other. The second electrode T2d of the compensation transistor T2 is electrically connected to the second connection structure CS2 through an eighth via V8, the third connection structure CS3 is electrically connected to the second connection structure CS2 through a ninth via V9, and the third connection structure CS3 is electrically connected to the active layer T6a of the first light-emitting control transistor T6 through a tenth via V10, so that the third connection structure CS3 serves as the first electrode T6s of the first light-emitting control transistor T6. On the basis of the technical effects achieved by the embodiment in FIG. 3, the display substrate shown in FIG. 8 can also avoid the problem of a large contact resistance caused by the direct contact and electrical connection between the conductive part of the electrode ET composed of conductive IGZO and P-Si, thereby making the display uniformity of the pixel array of the display substrate good and improving the display effect.

[0106] For example, referring to FIG. 8, the second connection structure CS2 is arranged in the same layer as the gate T6g of the first light-emitting control transistor T6, and is located in the first conductive layer Gate1; for example, the third connection structure CS3 is arranged in the same layer as the second electrode T6d of the first light-emitting control transistor T6, that is, is located in the conductive layer SD1.

[0107] The other features and corresponding technical effects of the embodiment shown in FIG. 8 are the same as those in FIG. 6 or FIG. 3, and can be referred to the previous description.

[0108] For example, in some embodiments of the present disclosure, the control transistor can be a single-gate transistor, and the gate of the control transistor is located on the side of the active layer of the control transistor away from the active layer of the drive transistor. Here, the control transistor can still include at least one of the first reset transistor T1 and the compensation transistor T2.

[0109] For example, FIG. 9 is a schematic view of a cross section of a pixel circuit of another display substrate provided by at least one embodiment of the present disclosure. The technical solution of FIG. 9 is different from the technical solution of FIG. 3 in the following aspects. Referring to FIG. 9, for example, at least one of the first reset transistor T1 and the compensation transistor T2 is a single-gate transistor, and FIG. 9 shows a case where both the first reset transistor T1 and the compensation transistor T2 are single-gate transistors. The first reset transistor T1 has a gate T1g, and the compensation transistor T2 has a gate T2g. For example, the gate T1g of the first reset transistor T1 is located on a side of the active layer T1a of the first reset transistor T1 away from the substrate BS, and the gate T2g of the compensation transistor T2 is located on a side of the active layer T2a of the compensation transistor T2 away from the substrate BS. For example, the gate T1g of the first reset transistor T1 and the gate T2g of the compensation transistor T2 are both disposed in a layer different from the first reset signal line Lvinil and the gate T3g of the driving transistor T3, so as to avoid too high density of conductive structures in the same layer, which may cause too much parasitic capacitance or increase the difficulty of manufacturing. Especially in the case of high resolution (high PPI) display substrate, the space of each sub-pixel is more limited, and the problem has a greater impact on the display effect. For example, referring to FIG. 9, the gate T1g and the gate T2g are located in the third conductive layer Gate3, the first reset signal line Lvinil is located in the second conductive layer Gate2, and the gate T3g of the driving transistor T3 is located in the first conductive layer Gate1. This is a preferred way when considering the convenience of manufacturing and preventing too high density of conductive structures in the same layer, but the conductive layer in which the gate T1g, the gate T2g, and the gate T3g are located is not limited to this way.

[0110] For example, the manufacturing method of the pixel circuit provided by at least one embodiment of the present disclosure includes: forming a first type of via hole, the first type of via hole at least exposing an active layer composed of a first semiconductor material (for example, P-Si), and forming a first conductive structure to electrically connect the surface of the active layer exposed by the first type of via hole through the first type of via hole. After forming the first type of via hole, in order to improve the characteristics of the LTPS TFT device, a high-temperature annealing process needs to be performed on the display substrate; for example, the manufacturing method of the pixel circuit includes: performing a contact resistance reduction process on the surface of the active layer composed of the first semiconductor material exposed by the first type of via hole, so as to reduce the contact resistance of the exposed surface, for example, to enable ohmic contact between the surface and the conductive structure in contact with the surface through the first type of via hole; for example, the surface of the active layer composed of the first semiconductor material exposed by the first type of via hole can be etched to remove the oxide layer of the exposed surface, so as to reduce the contact resistance of the exposed surface. For example, the first type of via hole includes a fifth via hole V5 that exposes the active layer T6a of the first light-emitting control transistor T6.

[0111] For example, the manufacturing method of the pixel circuit provided in the embodiments of the present application further includes: forming a second conductive structure, wherein the second conductive structure is an electrode where the active layer of the control transistor is located, the second conductive structure includes the active layer of the control transistor and a conductorized part integrated with the active layer of the control transistor, the active layer of the control transistor is composed of a second semiconductor material (for example, IGZO), and the conductorized part is a material after the second semiconductor material is conductorized; and forming a second type of via, wherein the conductorized part of the second conductive structure is electrically connected to a structure exposed by the second type of via through the second type of via, for example, the conductorized part of the second conductive structure is directly electrically connected to the gate of the driving transistor and the first electrode of the control transistor through the second type of via. For example, the process of the above-mentioned contact resistance reduction treatment can be performed after the second type of via is formed and before the second conductive structure is formed, so that the contact resistance reduction treatment does not affect the performance of the control transistor, the stability of the characteristics of the control transistor is maintained, therefore, the control transistor can achieve ideal performance by using a single gate, thereby simplifying the structure.

[0112] Referring to FIG. 9, compared with the structure shown in FIG. 3, for the first reset transistor T1, the first gate T1g1 with a smaller lateral length is retained, and the second gate T1g2 with a larger lateral length is removed; similarly, for the compensation transistor T2, the first gate T2g1 with a smaller lateral length is retained, and the second gate T2g2 with a larger lateral length is removed. In this way, the length of the gate of the control transistor (the first reset transistor T1 and / or the compensation transistor T2) in the lateral direction is reduced, for example, in the embodiment shown in FIG. 9, the control transistor adopts a single-gate structure, the length of the first gate T1g1 of the first reset transistor T1 and / or the length of the first gate T2g1 of the compensation transistor T2 in the lateral direction is smaller than the length of the gate of other transistors of the pixel circuit in the lateral direction, for example, smaller than the length of the gate of the driving transistor T3 in the lateral direction, or smaller than the length of the gate of the first light-emitting control transistor T6 in the lateral direction, or smaller than the length of the gate of the data transistor T4 in the lateral direction, etc. Since the material of the gate is usually an opaque conductive material such as a metal material, the above-mentioned length reduction of the gate of the single-gate control transistor can improve the aperture ratio of the display substrate; in addition, for the corresponding control transistor, taking the first reset transistor T1 as an example, the length of the channel region of the first reset transistor T1 in the direction from the first terminal T1s of the first reset transistor T1 to the second terminal T1d of the first reset transistor T1 is L, i.e., the length in the lateral direction in FIG. 9 is L, and the width of the channel region in the direction perpendicular to the lateral direction is W, so that, under the condition that W is unchanged, L is reduced, which increases the aspect ratio W / L of the first reset transistor T1, i.e., the aspect ratio of the first reset transistor T1 is increased, which is beneficial to reducing the heat generation of the first reset transistor T1 and improving the service life of the first reset transistor T1. Similarly, the same is true for the compensation transistor T2 with a single gate with a smaller length.

[0113] The other features of the embodiment shown in FIG. 9 and the corresponding technical effects are the same as those in FIG. 3, and reference can be made to the previous description.

[0114] FIG. 10 is a partial cross-sectional schematic view of a pixel circuit of another display substrate provided by at least one embodiment of the present disclosure. The technical solution of FIG. 10 is different from the technical solution of FIG. 6 in the following aspects. Referring to FIG. 10, for example, at least one of the first reset transistor T1 and the compensation transistor T2 is a single-gate transistor, and FIG. 10 shows the case where both the first reset transistor T1 and the compensation transistor T2 are single-gate transistors, the first reset transistor T1 has a gate T1g, and the compensation transistor T2 has a gate T2g.

[0115] The other features of the first reset transistor T1 shown in FIG. 10 and the compensation transistor T2 with the gate T2g and the corresponding technical effects are the same as those in FIG. 9, and reference can be made to the description of FIG. 9, which will not be repeated here.

[0116] The other unmentioned features and corresponding technical effects of the embodiment shown in FIG. 10 are the same as those in FIG. 6, and reference can be made to the previous description.

[0117] FIG. 11 is a schematic view of a cross section of a pixel circuit of another display substrate provided by at least one embodiment of the present disclosure. The technical solution of FIG. 11 is different from the technical solution of FIG. 7 in that, for example, at least one of the first reset transistor T1 and the compensation transistor T2 is a single-gate transistor. FIG. 11 shows a case where both the first reset transistor T1 and the compensation transistor T2 are single-gate transistors. The first reset transistor T1 has a gate T1g, and the compensation transistor T2 has a gate T2g.

[0118] The other unmentioned features and corresponding technical effects of the first reset transistor T1 having the gate T1g and the compensation transistor T2 having the gate T2g shown in FIG. 11 are the same as those in FIG. 9, and reference can be made to the description of FIG. 9, which will not be repeated here.

[0119] The other unmentioned features and corresponding technical effects of the embodiment shown in FIG. 11 are the same as those in FIG. 7, and reference can be made to the previous description.

[0120] FIG. 12 is a schematic view of a cross section of a pixel circuit of another display substrate provided by at least one embodiment of the present disclosure. The technical solution of FIG. 12 is different from the technical solution of FIG. 8 in that, for example, at least one of the first reset transistor T1 and the compensation transistor T2 is a single-gate transistor. FIG. 12 shows a case where both the first reset transistor T1 and the compensation transistor T2 are single-gate transistors. The first reset transistor T1 has a gate T1g, and the compensation transistor T2 has a gate T2g.

[0121] The other unmentioned features and corresponding technical effects of the first reset transistor T1 having the gate T1g and the compensation transistor T2 having the gate T2g shown in FIG. 12 are the same as those in FIG. 9, and reference can be made to the description of FIG. 9, which will not be repeated here.

[0122] The other unmentioned features and corresponding technical effects of the embodiment shown in FIG. 12 are the same as those in FIG. 8, and reference can be made to the previous description.

[0123] FIG. 13 is a schematic view of a display device provided by an embodiment of the present disclosure. Referring to FIG. 13, at least one embodiment of the present disclosure further provides a display device 100, which includes any one of the display substrates 10 provided by the embodiments of the present disclosure. The display device may, for example, be a display panel, a display, an OLED panel, an OLED television, electronic paper, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, or any product or component having a display function. Of course, the display device provided by the embodiments of the present disclosure is not limited to the types listed above.

[0124] Correspondingly, the display panel and the display device provided by the embodiments of the present disclosure have the technical effects of the pixel circuit and the display substrate provided by the embodiments of the present disclosure.

[0125] The display substrate manufacturing method provided by at least one of the embodiments of the present disclosure includes: forming a sub-pixel, including forming a pixel circuit, wherein the forming of the pixel circuit includes forming a light-emitting device and a driving transistor, the driving transistor is configured to control the size of a driving current flowing through the light-emitting device according to a data signal; the forming of the pixel circuit further includes: forming a control transistor, wherein the first electrode of the control transistor is electrically connected with the gate electrode of the driving transistor; the material of the active layer of the driving transistor is a first semiconductor material, the material of the active layer of the control transistor is a second semiconductor material, the first semiconductor material is different from the second semiconductor material; the electrode where the active layer of the control transistor is located is directly electrically connected with the gate electrode of the driving transistor and the first electrode of the control transistor.

[0126] For example, the display substrate manufacturing method includes: forming a second semiconductor layer by one-time patterning process by using the second semiconductor material; partially conducting the second semiconductor layer to form a second conductive structure, wherein the second conductive structure is the electrode where the active layer of the control transistor is located, and includes a conductive part and a non-conductive part, the conductive part and the non-conductive part constitute an integrated structure; the non-conductive part constitutes the active layer of the control transistor, the conductive part is directly electrically connected with the gate electrode of the driving transistor and the first electrode of the control transistor, the material of the conductive part is the material of the second semiconductor material after being conducted; and forming a second type of via, the conductive part of the second conductive structure is directly electrically connected with the gate electrode of the driving transistor and the first electrode of the control transistor through the second type of via.

[0127] Here, "directly electrically connected" means that at least part of the conductive part is directly in contact with the gate electrode of the driving transistor and the first electrode of the control transistor to be electrically connected with them, instead of the conductive part needing to be indirectly connected with the gate electrode of the driving transistor and the first electrode of the control transistor through other non-integrated conductive structures or even conductive structures arranged in different layers.

[0128] For example, the conductive part of the electrode where the active layer of the control transistor is located includes the first electrode of the control transistor, the first electrode of the control transistor is arranged in the same layer as the active layer of the control transistor and constitutes an integrated structure.

[0129] Therefore, the manufacturing method of the display substrate provided by the embodiments of the present disclosure can form the second semiconductor layer through one patterning process, reduce the number of electrodes and the number of vias for transfer, simplify the manufacturing process and design difficulty of the display substrate, greatly reduce the density of the same layer conductive structure, reduce the wiring difficulty of the same layer conductive structure or the wire, and play an important role in improving the yield of the display substrate.

[0130] [According to Rule 91 correction 11.10.2025] In a common manufacturing method of a display substrate, for example, in the manufacturing process of the display substrate shown in FIG. 4, after forming the first type of via, for example, taking the via V01 including the surface of the active layer T60a composed of the first semiconductor material exposed by the first light-emitting control transistor T6 as an example, the surface of the active layer T60a exposed by the via V01 is etched to remove the oxide film on the surface to reduce the contact resistance; then, the process of forming the via V02 including the surface of the active layer T10a / T20a composed of the second semiconductor material is performed, and then the first connection structure S1, the second connection structure S2 and the third connection structure S3 are formed to electrically connect the first reset transistor T1, the compensation transistor T2 and the first light-emitting control transistor T6 through the via V01 and the via V02 by using the first connection structure S1, the second connection structure S2 and the third connection structure S3. In this manufacturing method, from the surface of the active layer T60a exposed by the via V01 being etched to the formation of the first connection structure S1, the second connection structure S2 and the third connection structure S3 (for example, commonly formed by deposition or sputtering), a certain time interval is required, and during this interval, on the one hand, the surface of the active layer T60a exposed by the via V01 will form an oxide layer again, which will affect the ohmic contact between the active layer T60a and the third connection structure S3; on the other hand, the presence of foreign matter such as impurity particles at part of the via V01 will affect the electrical connection between the active layer T60a and the third connection structure S3, and thus affect the yield of the display substrate.

[0131] For example, the pixel circuit manufacturing method provided by at least one of the embodiments of the present application includes: forming a first type of via hole, the first type of via hole exposing at least an active layer composed of a first semiconductor material (for example, P-Si), and forming a first conductive structure to be electrically connected to the surface of the active layer composed of the first semiconductor material exposed by the first type of via hole through the first type of via hole. After forming the first type of via hole, in order to improve the characteristics of the LTPS TFT device, a high-temperature annealing process needs to be performed on the display substrate; for example, the pixel circuit manufacturing method includes: performing a contact resistance reduction process on the surface of the active layer composed of the first semiconductor material exposed by the first type of via hole, so as to reduce the contact resistance of the exposed surface, for example, to enable ohmic contact between the surface and the conductive structure in contact with the surface through the first type of via hole; for example, the surface of the active layer composed of the first semiconductor material exposed by the first type of via hole can be etched to remove the oxide layer of the exposed surface, so as to reduce the contact resistance of the exposed surface. For example, the first type of via hole includes a fifth via hole V5 exposing an active layer T6a of a first light-emitting control transistor T6.

[0132] For example, the pixel circuit manufacturing method provided by the embodiments of the present application further includes: forming a second type of via hole, and forming a second conductive structure in the second type of via hole; the electrode where the second conductive structure is located includes the active layer of the control transistor, the active layer of the control transistor is composed of a second semiconductor material (for example, IGZO), and the electrode where the second conductive structure is located further includes a conductorized part forming an integrated structure with the active layer of the control transistor, the conductorized part being a material after the second semiconductor material is conductorized. For example, the part of the second conductive structure located in the second type of via hole is in contact with the structure exposed by the second type of via hole through the second type of via hole to be electrically connected. For example, the contact resistance reduction process can be performed after forming the second type of via hole and before forming the second conductive structure, so that the contact resistance reduction process does not affect the performance of the control transistor, and therefore, the control transistor can achieve ideal performance by using a single gate, thereby simplifying the structure.

[0133] For example, FIGS. 14A-14D are schematic diagrams of a display substrate manufacturing method provided by an embodiment of the present application, for example, FIGS. 14A-14D show the manufacturing method of the display substrate shown in FIG. 3.

[0134] Referring to FIG. 14A, a substrate BS is provided, on which a first flexible layer PI1, a first barrier layer Barrier1, a second flexible layer PI2, a second barrier layer Barrier2-1, a BSM, a third barrier layer Barrier2-2, a first buffer layer Buffer1, an active layer including but not limited to an active layer T3a of a driving transistor T3 and an active layer T6a of a first light-emitting control transistor T6 composed of a first semiconductor material, a first gate insulating layer GI1, a first metal layer Gate1, a second gate insulating layer GI2, a second metal layer Gate2, a first interlayer insulating layer ILD1, and a second buffer layer Buffer2 are formed; then, the above-mentioned second type of via is formed by one patterning process, where the second type of via includes a first via V1, a second via V2 (which is also a third via V3 in this embodiment) and a fourth via V4, for example, in a single pixel circuit, there are three second type of vias formed. Of course, the number of second type of vias is not limited to this case.

[0135] Next, referring to FIG. 14B, a second semiconductor layer (not shown in the figure) is formed using the above-mentioned second semiconductor material, for example, the second semiconductor layer is formed using a deposition method, and a connection electrode pattern is formed by performing a patterning process on the second semiconductor layer, then, a part of the connection electrode pattern is subjected to a conductorization process to form a second conductive structure, a part of the second conductive structure is located in the first via V1, the second via V2 and the fourth via V4, the second conductive structure is an electrode ET in which the active layer of the control transistor is located, the second conductive structure includes the active layer T1a of the first reset transistor T1, the active layer T2a of the compensation transistor T2, and a conductorized part that constitutes an integrated structure with the active layer T1a of the first reset transistor T1 and the active layer T2a of the compensation transistor T2, so that the active layer T1a of the first reset transistor T1 and the active layer T2a of the compensation transistor T2 are both composed of the second semiconductor material (for example, IGZO), and the conductorized part is a material after the second semiconductor material is conductorized. For example, the conductorized part includes, for example, the part of the second conductive structure located in the second type of via is in contact with the structure exposed by the second type of via through the second type of via to be electrically connected. Thus, the second conductive structure is formed, which is the electrode ET in which the active layer T1a of the first reset transistor T1 shown in FIG. 3 is located, and the specific connection relationship of the second conductive structure can be seen from the description of FIG. 3.

[0136] Then, as shown in FIG. 14C, a third gate insulating layer GI3, a third conductive layer Gate3 and a second interlayer insulating layer ILD2 are sequentially formed, and the above-mentioned first type of via is formed by one patterning process, for example, the first type of via includes a fifth via V5.

[0137] Then, after forming the first type of via hole (for example, the fifth via hole V5), a high-temperature annealing process is performed on the display substrate to improve the characteristics of the LTPS TFT device (for example, the first light-emitting control transistor T6). Then, the surface of the active layer T6a of the first light-emitting control transistor T6 composed of the first semiconductor material exposed by the fifth via hole V5 is subjected to a low-resistance contact treatment to reduce the contact resistance of the exposed surface, so that the surface realizes ohmic contact with the second electrode T6d of the first light-emitting control transistor T6 formed subsequently through the fifth via hole V5; for example, the surface of the active layer T6a exposed by the fifth via hole V5 can be subjected to etching treatment to remove the oxide layer of the surface of the active layer T6a exposed by the fifth via hole V5, thereby reducing the contact resistance of the exposed surface.

[0138] Then, as shown in FIG. 14D, a conductive layer SD1 is formed, for example, by using a deposition method and a one-time patterning process to form the conductive layer SD1, and the conductive layer SD1 includes the second electrode T6d of the first light-emitting control transistor T6. The second electrode T6d of the first light-emitting control transistor T6 is electrically connected to the active layer T6a of the first light-emitting control transistor T6 through the fifth via hole V5.

[0139] Therefore, in the method for manufacturing a display substrate provided in at least one embodiment of the present disclosure, after removing the oxide layer of the surface of the active layer T6a exposed by the fifth via hole V5, the conductive layer SD1 can be immediately manufactured without an interval process of forming the second type of via hole. In this way, on the one hand, the ohmic contact between the active layer composed of the first semiconductor material and the conductive layer SD1 can be effectively improved; on the other hand, the formation of foreign matter such as impurity particles in the fifth via hole V5 can be effectively prevented, thereby preventing the influence of the foreign matter such as impurity particles on the electrical connection between the active layer composed of the first semiconductor material and the conductive layer SD1, and further improving the yield of the display substrate.

[0140] For example, in another method for manufacturing a display substrate shown in FIG. 3, a high-temperature annealing process can also be performed on the display substrate after forming the second type of via hole and before forming the second conductive structure (i.e., the electrode ET where the active layer of the control transistor is located) to prevent the high-temperature annealing process from affecting the performance of the second conductive structure composed of the second semiconductor material, thereby not affecting the performance of the control transistor.

[0141] FIGS. 15A-15D are schematic diagrams of a method for manufacturing a display substrate provided in an embodiment of the present disclosure, for example, FIGS. 15A-15D show a method for manufacturing the display substrate shown in FIG. 6.

[0142] Referring to FIG. 15A, the difference between the step shown in FIG. 14A is that the second type of via hole is formed by one patterning process, and the second type of via hole includes the first via hole V1 and the second via hole V2 (which is also the third via hole V3 in this embodiment), and the fourth via hole V4 in FIG. 14A is not formed.

[0143] Next, referring to FIG. 15B, a second semiconductor layer (not shown in the figure) is formed using the second semiconductor material, for example, the second semiconductor layer is formed by a deposition method, and a patterning process is performed on the second semiconductor layer to form a connection electrode pattern, and then a part of the connection electrode pattern is subjected to a conductorization process to form a second conductive structure. The second conductive structure is the electrode ET in which the active layer T1a of the first reset transistor T1 shown in FIG. 6 is located, and the specific structure and connection relationship of the second conductive structure can be seen from the description of FIG. 6. Then, a third gate insulating layer GI3, a third conductive layer Gate3 and a second interlayer insulating layer ILD2 are sequentially formed, and the first type of via hole is formed by one patterning process, for example, the first type of via hole includes the fifth via hole V5 and the seventh via hole V7, and the fifth via hole V5 and the seventh via hole V7 expose the surface of the active layer T1a of the first reset transistor T1 composed of the first semiconductor material; here, the first type of via hole also includes the sixth via hole V6 that exposes the conductorized part of the second conductive structure (i.e., the integrated electrode ET), and the sixth via hole V6 exposes the end of the electrode ET that is close to the first light-emitting control transistor T6 in the lateral direction, and the end of the electrode ET that is close to the first light-emitting control transistor T6 in the lateral direction is multiplexed as the second electrode T2d of the compensation transistor T2.

[0144] Next, referring to FIG. 15C, a high-temperature annealing process is performed on the display substrate to improve the characteristics of the LTPS TFT device (for example, the first light-emitting control transistor T6). Then, the surface of the active layer T6a of the first light-emitting control transistor T6 composed of the first semiconductor material exposed by the fifth via hole V5 and the seventh via hole V7 is subjected to a contact resistance reduction process; for example, the surface of the active layer T6a exposed by the fifth via hole V5 and the seventh via hole V7 can be subjected to an etching process to remove the oxide layer on the surface of the active layer T6a exposed by the fifth via hole V5 and the seventh via hole V7, thereby reducing the contact resistance of the exposed surface. After the etching process, the end of the electrode ET exposed by the sixth via hole V6 in FIG. 15B that is close to the first light-emitting control transistor T6 in the lateral direction is etched through, that is, the second electrode T2d of the compensation transistor T2 is etched through, so that the sixth via hole V6 penetrates the second electrode T2d of the compensation transistor T2 in the direction perpendicular to the main surface of the substrate BS.

[0145] Then, referring to FIG. 15D, a conductive layer SD1 is formed, for example, by using a deposition method and a one-time patterning process, and the conductive layer SD1 includes the second electrode T6d of the first light-emitting control transistor T6 and the first connection structure CS1. The second electrode T6d of the first light-emitting control transistor T6 is electrically connected to the active layer T6a of the first light-emitting control transistor T6 through the fifth via V5; the first connection structure CS1 is electrically connected to the second electrode T2d of the compensation transistor T2 through the sixth via V6 and is electrically connected to the active layer T6a of the first light-emitting control transistor T6 through the seventh via V7.

[0146] Thus, the display substrate shown in FIG. 6 is formed. FIG. 6 uses a side lap joint manner to electrically connect the first connection structure CS1 to the second electrode T2d of the compensation transistor T2. In the method for manufacturing the display substrate provided in at least one embodiment of the present disclosure, after the oxide layer on the surface of the active layer T6a exposed by the fifth via V5 and the seventh via V7 is removed, the conductive layer SD1 can be immediately manufactured without an interval process for forming the second type of via. In this way, the technical effects of effectively improving the ohmic contact between the active layer made of the first semiconductor material and the conductive layer SD1 and effectively preventing the formation of impurity particles and other foreign matters in the fifth via V5 can also be achieved.

[0147] FIGS. 16A-16D are schematic diagrams of a method for manufacturing a display substrate provided in an embodiment of the present disclosure, for example, showing the method for manufacturing the display substrate shown in FIG. 7.

[0148] Referring to FIG. 16A, the same steps as those shown in FIG. 15A are performed.

[0149] Then, referring to FIG. 16B, a second semiconductor layer (not shown) is formed by using the second semiconductor material described above, for example, by using a deposition method, and a one-time patterning process is performed on the second semiconductor layer to form a connection electrode pattern, and then, a part of the connection electrode pattern is subjected to a conductorization process to form a second conductive structure. The second conductive structure is the electrode ET in which the active layer T1a of the first reset transistor T1 shown in FIG. 6 is located, and the specific structure and connection relationship of the second conductive structure can be found in the description of FIG. 6. Then, a third gate insulating layer GI3, a third conductive layer Gate3, and a second interlayer insulating layer ILD2 are sequentially formed, and the first type of via is formed by a one-time patterning process. Different from the steps shown in FIG. 15B, the first type of via here does not include the sixth via V6 that exposes the conductorized part of the second conductive structure (i.e., the integrated electrode ET), but includes the fifth via V5 and the seventh via V7. The fifth via V5 and the seventh via V7 expose the surface of the active layer T1a of the first reset transistor T1 made of the first semiconductor material.

[0150] Next, referring to FIG. 16C, a high-temperature annealing process is performed on the display substrate to improve the characteristics of the LTPS TFT device (e.g., the first light-emitting control transistor T6). Then, a surface of the active layer T6a of the first light-emitting control transistor T6, which is composed of the first semiconductor material, exposed by the fifth via V5 and the seventh via V7 is subjected to a low-resistance contact treatment; for example, the surface of the active layer T6a exposed by the fifth via V5 and the seventh via V7 can be subjected to an etching treatment to remove the oxide layer of the surface of the active layer T6a exposed by the fifth via V5 and the seventh via V7, thereby reducing the contact resistance of the exposed surface. After the etching treatment, the sixth via V6 is formed by a one-time patterning process, the sixth via V6 exposing the upper surface of the end portion of the electrode ET, which is laterally close to the first light-emitting control transistor T6, which is multiplexed as the second electrode T2d of the compensation transistor T2.

[0151] Next, referring to FIG. 16D, the conductive layer SD1 is formed, for example, by using a deposition method and a one-time patterning process, the conductive layer SD1 including the second electrode T6d of the first light-emitting control transistor T6 and the first connection structure CS1. The second electrode T6d of the first light-emitting control transistor T6 is electrically connected to the active layer T6a of the first light-emitting control transistor T6 through the fifth via V5; the first connection structure CS1 is electrically connected to the second electrode T2d of the compensation transistor T2 through the sixth via V6 and to the active layer T6a of the first light-emitting control transistor T6 through the seventh via V7.

[0152] Thus, the display substrate shown in FIG. 7 is formed. FIG. 7 uses a bottom lap joint to electrically connect the first connection structure CS1 to the second electrode T2d of the compensation transistor T2. In the method for manufacturing the display substrate provided in at least one embodiment of the present disclosure, after removing the oxide layer of the surface of the active layer T6a exposed by the fifth via V5 and the seventh via V7, the conductive layer SD1 can be immediately manufactured without an interval process for forming the second type of via. In this way, the technical effects of effectively improving the ohmic contact between the active layer composed of the first semiconductor material and the conductive layer SD1 and effectively preventing the formation of impurity particles and other foreign matter in the fifth via V5 and the seventh via V7 can also be achieved.

[0153] FIGS. 17A-17D are schematic diagrams of a method for manufacturing a display substrate provided in an embodiment of the present disclosure, for example, FIGS. 17A-17D show a method for manufacturing the display substrate shown in FIG. 8.

[0154] Referring to FIG. 17A, different from the step shown in FIG. 15A, the first metal layer Gate 1 further comprises a second connection structure CS2. The above-mentioned second type of via is formed by the same patterning process, and here the second type of via comprises the first via V1, the second via V2 (which is also the third via V3 in this embodiment), and the eighth via V8 exposing the second connection structure CS2.

[0155] Next, referring to FIG. 17B, a second semiconductor layer (not shown in the figure) is formed using the above-mentioned second semiconductor material, for example, the second semiconductor layer is formed using a deposition method, and a patterning process is performed on the second semiconductor layer to form a connection electrode pattern, and then a part of the connection electrode pattern is subjected to a conductorization treatment to form a second conductive structure. The second conductive structure is also the electrode ET in which the active layer T1a of the first reset transistor T1 shown in FIG. 8 is located, and the specific structure and connection relationship of the second conductive structure can be seen from the description of FIG. 8.

[0156] Then, referring to FIG. 17C, a third gate insulating layer GI3, a third conductive layer Gate3 and a second interlayer insulating layer ILD2 are sequentially formed, and the above-mentioned first type of via is formed by a patterning process. Different from the step shown in FIG. 15B, here the first type of via does not comprise the sixth via V6 exposing the conductorized part of the second conductive structure (i.e. the integrated electrode ET), but comprises the fifth via V5 and the tenth via V10 respectively exposing the source region and the drain region of the active layer T6a of the first light emitting control transistor T6, and the ninth via V9 exposing the second connection structure CS2.

[0157] Next, a high-temperature annealing process is performed on the display substrate to improve the characteristics of the LTPS TFT device (for example, the first light emitting control transistor T6). Then, the surface of the active layer T6a composed of the first semiconductor material of the first light emitting control transistor T6 exposed by the fifth via V5 and the seventh via V7 is subjected to a contact resistance reduction treatment; for example, the surface of the active layer T6a exposed by the fifth via V5 and the tenth via V10 can be subjected to an etching treatment to remove the oxide layer of the surface of the active layer T6a exposed by the fifth via V5 and the seventh via V7, thereby reducing the contact resistance of the exposed surface.

[0158] Then, referring to FIG. 17D, a conductive layer SD1 is formed, for example, by using a deposition method and a one-time patterning process, and the conductive layer SD1 includes the first connection structure CS1, the second connection structure CS2, and the third connection structure CS3. The second electrode T6d of the first light-emitting control transistor T6 is electrically connected to the active layer T6a of the first light-emitting control transistor T6 through the fifth via V5. The second electrode T2d of the compensation transistor T2 is electrically connected to the second connection structure CS2 through the eighth via V8, the third connection structure CS3 is electrically connected to the second connection structure CS2 through the ninth via V9, and the third connection structure CS3 is electrically connected to the active layer T6a of the first light-emitting control transistor T6 through the tenth via V10, so that the third connection structure CS3 serves as the first electrode T6s of the first light-emitting control transistor T6.

[0159] Thus, the display substrate shown in FIG. 8 is formed. In the method for manufacturing the display substrate provided in at least one of the embodiments of the present disclosure, after the oxide layer on the surface of the active layer T6a exposed by the fifth via V5 and the tenth via V10 is removed, the conductive layer SD1 can be manufactured immediately without an interval process of forming the second type of via. In this way, the technical effects of effectively improving the ohmic contact between the active layer made of the first semiconductor material and the conductive layer SD1 and effectively preventing the formation of impurity particles and other foreign matters in the fifth via V5 and the tenth via V10 can also be achieved.

[0160] For the method for manufacturing the display substrate shown in FIGS. 9 to 12, in the method for manufacturing the display substrate shown in FIGS. 3, 6, 7, and 8, respectively, in the process of forming the second metal layer Gate2 by the patterning process, the patterning pattern is changed to not form the second gate T1g2 of the first reset transistor T1 and the second gate T2g2 of the compensation transistor T2. The other method steps can be referred to the method for manufacturing the display substrate shown in FIGS. 3, 6, 7, and 8, respectively. The technical effects of the method for manufacturing the display substrate shown in FIGS. 3, 6, 7, and 8 can also be achieved, and the removal of the second gate simplifies the design of the mask plate and the process.

[0161] The following points need to be explained:

[0162] (1) The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0163] (2) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0164] The above only describes exemplary embodiments of the present application, and is not intended to limit the protection scope of the present application, which is determined by the appended claims.

Claims

1. A display substrate, comprising a sub-pixel, wherein, The sub-pixel comprises a pixel circuit, the pixel circuit comprising a light emitting device and a driving transistor configured to control a size of a driving current flowing through the light emitting device according to a data signal; The pixel circuit further comprises a control transistor, a first electrode of the control transistor being electrically connected with a gate electrode of the driving transistor; The material of an active layer of the driving transistor is a first semiconductor material, and the material of an active layer of the control transistor is a second semiconductor material, the first semiconductor material being different from the second semiconductor material; An electrode where the active layer of the control transistor is located directly electrically connects the gate electrode of the driving transistor and the first electrode of the control transistor. 2.The display substrate of claim 1, wherein, The active layer of the driving transistor is located in a layer different from the active layer of the control transistor, and the gate electrode of the driving transistor is located between the active layer of the driving transistor and the electrode where the active layer of the control transistor is located. 3.The display substrate of claim 2, wherein, The display substrate comprises a substrate, and the driving transistor is disposed on a main surface of the substrate; The active layer of the driving transistor is located on a side of the active layer of the control transistor close to the substrate. 4.The display substrate of claim 1, wherein, The pixel circuit comprises a first reset transistor configured to write a first reset signal to the gate electrode of the driving transistor under control of a first reset control signal; The control transistor comprises the first reset transistor, and an electrode where the active layer of the first reset transistor is located directly electrically connects the gate electrode of the driving transistor and a first electrode of the first reset transistor. 5.The display substrate of claim 4, wherein, The electrode where the active layer of the first reset transistor is located comprises the active layer of the first reset transistor and a first electrode of the first reset transistor, the material of the first electrode of the first reset transistor being a material obtained by conducting the second semiconductor material, and the active layer of the first reset transistor and the first electrode of the first reset transistor are located in the same layer and form an integrated structure; The gate electrode of the driving transistor is located in a layer different from the electrode where the active layer of the first reset transistor is located, and the first electrode of the first reset transistor is in contact with the gate electrode of the driving transistor through a first via hole exposing the gate electrode of the driving transistor to directly electrically connect the gate electrode of the driving transistor and the first electrode of the first reset transistor. 6.The display substrate of claim 5, wherein, The electrode where the active layer of the first reset transistor is located further comprises a second electrode of the first reset transistor, and the material of the second electrode of the first reset transistor is a material obtained by conducting the second semiconductor material; The pixel circuit further comprises a first reset signal line located in a layer different from the second electrode of the first reset transistor, and the second electrode of the first reset transistor is in contact with the first reset signal line through a second via hole exposing the first reset signal line to directly electrically connect the first reset signal line. 7.The display substrate according to any one of claims 1-6, wherein, The pixel circuit further comprises a compensation transistor configured to compensate a signal applied to the gate electrode of the driving transistor in response to a compensation scan signal and the data signal; The active layer of the compensation transistor is located in an electrode, and the electrode is directly electrically connected with the gate of the driving transistor and the first electrode of the compensation transistor. 8.The display substrate of claim 7, wherein, The active layer of the compensation transistor is located in an electrode, and the electrode includes the active layer of the compensation transistor and the first electrode of the compensation transistor, and the material of the first electrode of the compensation transistor is the material of the second semiconductor material after being conductorized, and the active layer of the compensation transistor and the first electrode of the compensation transistor are located in the same layer and form an integrated structure. The gate of the driving transistor is located in a different layer from the electrode in which the active layer of the compensation transistor is located, and the first electrode of the compensation transistor is in contact with the gate of the driving transistor through a third via hole exposing the gate of the driving transistor to directly electrically connect the gate of the driving transistor and the first electrode of the compensation transistor. 9.The display substrate of claim 8, wherein, In the case where the control transistor includes a first reset transistor, the electrode in which the active layer of the first reset transistor is located includes the active layer of the first reset transistor and the first electrode of the first reset transistor, the material of the first electrode of the first reset transistor is the material of the second semiconductor material after being conductorized, the active layer of the first reset transistor and the first electrode of the first reset transistor are located in the same layer and form an integrated structure, the gate of the driving transistor is located in a different layer from the electrode in which the active layer of the first reset transistor is located, and the first electrode of the first reset transistor is in contact with the gate of the driving transistor through a first via hole exposing the gate of the driving transistor to directly electrically connect the gate of the driving transistor and the first electrode of the first reset transistor, The electrode in which the active layer of the compensation transistor is located is located in the same layer as the electrode in which the active layer of the first reset transistor is located and forms an integrated structure, the first electrode of the first reset transistor and the first electrode of the compensation transistor are integrated, and the first via hole and the second via hole are the same via hole. The material of the active layer of the compensation transistor is the second semiconductor material, the material of the first electrode of the compensation transistor is the material of the second semiconductor material after being conductorized, and the first electrode of the first reset transistor, the first electrode of the compensation transistor and the active layer of the compensation transistor are sequentially connected, located in the same layer and form an integrated structure. 10.The display substrate of claim 7, wherein, The pixel circuit further includes a first light-emitting control transistor configured to cause the driving current to be applied to the light-emitting device under the control of a first light-emitting control signal; The material of the active layer of the first light-emitting control transistor is the first semiconductor material, and the active layer of the first light-emitting control transistor is located in a different layer from the active layer of the control transistor; The electrode in which the active layer of the compensation transistor is located further includes a connecting portion, the material of the connecting portion is the material of the second semiconductor material after being conductorized, and the connecting portion is located in the same layer as the active layer of the compensation transistor and forms an integrated structure. The connection portion is in contact with the active layer of the first light emitting control transistor through a fourth via hole exposing the active layer of the first light emitting control transistor to electrically connect the active layer of the first light emitting control transistor, and the connection portion serves as a first electrode of the first light emitting control transistor and a second electrode of the compensation transistor. 11.The display substrate of claim 10, wherein, The active layer of the first light emitting control transistor and the active layer of the driving transistor are arranged in the same layer, and / or, The gate electrode of the driving transistor is arranged in the same layer as the gate electrode of the first light emitting control transistor.

12. The display substrate according to any one of claims 1-6, wherein, The pixel circuit further comprises a first light emitting control transistor configured to cause the driving current to be applied to the light emitting device under the control of a first light emitting control signal; The material of the active layer of the first light emitting control transistor is the first semiconductor material, and the active layer of the first light emitting control transistor is arranged in a different layer from the active layer of the control transistor; The electrode in which the active layer of the control transistor is arranged is arranged in a different layer from the second electrode of the first light emitting control transistor, the electrode in which the active layer of the control transistor is arranged is in contact with the active layer of the first light emitting control transistor through a fourth via hole exposing the active layer of the first light emitting control transistor, and the second electrode of the first light emitting control transistor is in contact with the active layer of the first light emitting control transistor through a fifth via hole exposing the active layer of the first light emitting control transistor. 13.The display substrate of claim 12, wherein, The display substrate comprises a substrate, and the driving transistor is arranged on a main surface of the substrate; The second electrode of the first light emitting control transistor is located on a side of the electrode in which the active layer of the control transistor is arranged away from the substrate. 14.The display substrate of claim 12, wherein, In the case that the control transistor comprises a first reset transistor, the electrode in which the active layer of the first reset transistor is arranged further comprises a second electrode of the first reset transistor, the material of the second electrode of the first reset transistor is a material obtained by conducting the second semiconductor material, the pixel circuit further comprises a first reset signal line arranged in a different layer from the second electrode of the first reset transistor, and the second electrode of the first reset transistor is electrically connected to the first reset signal line by exposing a second via hole of the first reset signal line. The first reset signal line is arranged in a different layer from the second electrode of the first light emitting control transistor. 15.The display substrate of claim 14, wherein, The first reset signal line and the gate electrode of the driving transistor are both located between the gate electrode of the driving transistor and the electrode in which the active layer of the control transistor is arranged. The first reset signal line is arranged in a different layer or in the same layer as the gate electrode of the driving transistor. 16.The display substrate of claim 15, wherein, The control transistor is a single-gate transistor, and the gate electrode of the control transistor is located on a side of the active layer of the control transistor away from the active layer of the driving transistor; or The control transistor is a double-gate transistor, a first gate electrode of the control transistor is located on a side of the active layer of the control transistor away from the active layer of the driving transistor, and a second gate electrode of the control transistor is located between the active layer of the control transistor and the active layer of the driving transistor The second gate of the control transistor is arranged in the same layer as the first reset signal line or in a different layer. 17.The display substrate of claim 15, wherein, The second gate of the control transistor and the gate of the drive transistor are arranged in a lateral direction; In a case where the control transistor is a double-gate transistor, a line width of the second gate of the control transistor in the lateral direction is greater than a line width of the first gate of the control transistor in the lateral direction. 18.The display substrate of claim 14, wherein, The display substrate includes a substrate, and the drive transistor is disposed on a main surface of the substrate; The first reset signal line and the gate of the control transistor do not overlap in a direction perpendicular to the main surface of the substrate.

19. The display substrate of claim 7, wherein, The pixel circuit further includes a first light emitting control transistor configured to cause the drive current to be applied to the light emitting device under control of a first light emitting control signal; A material of an active layer of the first light emitting control transistor is the first semiconductor material, and the active layer of the first light emitting control transistor is arranged in a different layer than the active layer of the control transistor; An electrode in which the active layer of the compensation transistor is arranged further includes a second electrode of the compensation transistor, a material of the second electrode of the compensation transistor is a material of the second semiconductor material after being made conductive, and the second electrode of the compensation transistor is arranged in the same layer as the active layer of the compensation transistor and forms an integrated structure; The pixel circuit includes a first connection structure, the first connection structure, the second electrode of the compensation transistor, and the electrode in which the active layer of the control transistor are arranged in different layers from each other; The first connection structure is electrically connected to the second electrode of the compensation transistor through a sixth via hole and is electrically connected to the active layer of the first light emitting control transistor through a seventh via hole. 20.The display substrate of claim 19, wherein, The display substrate includes a substrate, and the drive transistor is disposed on a main surface of the substrate; The fifth via hole penetrates the second electrode of the compensation transistor, the first connection structure includes an inner hole portion in the sixth via hole, a side surface of the inner hole portion is in contact with the second electrode of the compensation transistor, and a surface in which the side surface of the inner hole portion is located intersects with a surface in which the main surface of the substrate is located. Alternatively, The fifth via hole exposes an upper surface of the second electrode of the compensation transistor, the upper surface of the second electrode of the compensation transistor is away from the main surface of the substrate, and the first connection structure includes an inner hole portion in the sixth via hole, a bottom surface of the inner hole portion is in contact with the upper surface of the second electrode of the compensation transistor. The pixel circuit further includes a first light emitting control transistor configured to cause the drive current to be applied to the light emitting device under control of a first light emitting control signal; 21. The display substrate of claim 7, wherein, A material of an active layer of the first light emitting control transistor is the first semiconductor material, and the active layer of the first light emitting control transistor is arranged in a different layer than the active layer of the control transistor; ​ The electrode where the active layer of the compensation transistor is located further comprises a second electrode of the compensation transistor, a material of the second electrode of the compensation transistor is a material after the second semiconductor material is conductorized, the connection part is arranged in the same layer as the active layer of the compensation transistor and constitutes an integrated structure; The pixel circuit further comprises a second connection structure and a third connection structure, the second electrode of the compensation transistor, the second connection structure, the third connection structure and the active layer of the first light-emitting control transistor are arranged in different layers from each other; The second electrode of the compensation transistor is electrically connected with the second connection structure through an eighth via hole, the third connection structure is electrically connected with the second connection structure through a ninth via hole, and the third connection structure is electrically connected with the active layer of the first light-emitting control transistor through a tenth via hole.

22. The display substrate according to any one of claims 1-6, wherein, The first semiconductor material is a silicon semiconductor material, and the second semiconductor material is a transparent metal oxide semiconductor material.

23. The display substrate of claim 22, wherein, The transparent metal oxide semiconductor material comprises indium gallium zinc oxide (IGZO).

24. A display device comprising the display substrate according to any one of claims 1-23.

25. A manufacturing method of a display substrate, comprising: forming a sub-pixel, comprising forming a pixel circuit, wherein the forming a pixel circuit comprises forming a light-emitting device and a driving transistor, the driving transistor being configured to control a size of a driving current flowing through the light-emitting device according to a data signal; the forming a pixel circuit further comprises forming a control transistor, wherein a first electrode of the control transistor is electrically connected with a gate electrode of the driving transistor; a material of an active layer of the driving transistor is a first semiconductor material, a material of an active layer of the control transistor is a second semiconductor material, the first semiconductor material is different from the second semiconductor material; an electrode where the active layer of the control transistor is located directly electrically connects the gate electrode of the driving transistor and the first electrode of the control transistor.

26. The manufacturing method of the display substrate according to claim 25, comprising: forming a first type of via hole, wherein the first type of via hole exposes at least an active layer composed of the first semiconductor material; forming a first conductive structure to be electrically connected with a surface of the active layer composed of the first semiconductor material exposed by the first type of via hole through the first type of via hole; after forming the first type of via hole, performing a high-temperature annealing process on the display substrate; and performing a low-resistance contact treatment on the surface of the active layer composed of the first semiconductor material exposed by the first type of via hole.

27. The manufacturing method of the display substrate according to claim 26, comprising: forming a second semiconductor layer by one-time patterning using the second semiconductor material; ​ part of the second semiconductor layer is made conductive to form a second conductive structure, wherein the second conductive structure is an electrode where the active layer of the control transistor is located, and comprises a conductive part and a non-conductive part, the conductive part and the non-conductive part constitute an integrated structure; the non-conductive part constitutes the active layer of the control transistor, the conductive part is directly electrically connected with the gate of the driving transistor and the first electrode of the control transistor, and the material of the conductive part is the material of the second semiconductor material after being made conductive; and a second type of via hole is formed, and the conductive part of the second conductive structure is directly electrically connected with the gate of the driving transistor and the first electrode of the control transistor through the second type of via hole.

28. The manufacturing method of the display substrate according to claim 27, wherein, after the second type of via hole is formed and before the second conductive structure is formed, the high-temperature annealing process is performed on the display substrate.

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