Display panel and display device

Abstract

The present application relates to the technical field of display, and discloses a display panel and a display device. The display panel comprises: a substrate, a plurality of pixel circuits, a plurality of light-emitting devices, a plurality of data signal lines, and a plurality of redundant signal lines. The redundant signal lines each may comprise: a first lead portion connected to one data signal line. Here, the first lead portion may be part of a fan-out lead electrically connected to said data signal line. Because the redundant signal lines are distributed in a display area, part of each fan-out lead configured to be electrically connected to the corresponding data signal line can be distributed in the display area, such that when the part of the fan-out lead other than the first lead portion is distributed in a non-display area, the space occupied by the fan-out leads in the non-display is reduced, thereby effectively reducing the width of the area where the fan-out leads are arranged in the non-display area. In this way, the screen-to-body ratio of a display device having the display panel integrated thereon can be effectively improved, such that the display effect of the display device is good.

Description

Display panel and display device

[0001] This application claims priority to Chinese patent application No. 202310974470.7, filed on August 3, 2023, entitled “Display Panel and Display Device,” the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] Currently, in order to provide users with a better visual experience, display screens (also called display panels) in display devices are developing towards larger screens and full screens.

[0004] A display device typically includes a display panel and a driver chip. The display panel has a display area and a non-display area, and may include: multiple sub-pixels and multiple data signal lines located in the display area, and multiple fan-out leads located in the non-display area; each data signal line may be electrically connected to a column of sub-pixels, and each data signal line may be electrically connected to the driver chip via a fan-out lead. In this way, the driver chip can send a drive signal to the data signal line via the fan-out lead, so that the display panel can display the picture.

[0005] However, in the above-mentioned display panel, the fan-out leads occupy a large space, resulting in a large width of the area where the fan-out leads are set in the non-display area, which in turn leads to a low screen-to-body ratio of the display device, affecting the display effect of the display device.

[0006] Summary of the Invention

[0007] The present invention provides a display panel and a display device. The display device can solve the problem of low screen-to-body ratio in conventional display devices. The technical solution is as follows:

[0008] In one aspect, a display panel is provided, the display panel having a display area, the display panel comprising:

[0009] substrate;

[0010] A plurality of pixel circuits arranged in an array on one side of the substrate, the plurality of pixel circuits comprising: a plurality of first pixel circuits and a plurality of dummy pixel circuits;

[0011] a plurality of light-emitting devices located on a side of the plurality of pixel circuits facing away from the substrate, the plurality of light-emitting devices being electrically connected to the plurality of first pixel circuits in a one-to-one correspondence;

[0012] and, a plurality of data signal lines and a plurality of redundant signal lines located in the display area, wherein the extending direction of the data signal lines is the same as the extending direction of the redundant signal lines;

[0013] Among them, one of the data signal lines is connected to a column of the first pixel circuits; one of the redundant signal lines is located in the area where a column of the virtual pixel circuits is located; at least some of the multiple redundant signal lines are first redundant signal lines, and one of the first redundant signal lines includes a first lead portion connected to one of the data signal lines.

[0014] Optionally, the display panel further comprises: a plurality of auxiliary signal lines located in the display area, wherein an extension direction of the auxiliary signal lines intersects with an extension direction of the redundant signal lines;

[0015] Among them, one of the auxiliary signal lines is located in the area where a row of pixel circuits is located; at least some of the multiple auxiliary signal lines are first auxiliary signal lines, and one of the first auxiliary signal lines includes: a second lead portion, one end of the second lead portion is electrically connected to one of the data signal lines, and the other end is electrically connected to one end of the first lead portion.

[0016] Optionally, one of the first redundant signal lines further includes: a redundant line body disconnected from the first lead portion; and one of the first auxiliary signal lines further includes: an auxiliary line body disconnected from the second lead portion;

[0017] The redundant line body and the auxiliary line body are electrically connected at the intersection.

[0018] Optionally, a portion of the plurality of redundant signal lines is the first redundant signal line, another portion of the redundant signal lines is a second redundant signal line, the first lead portion is not provided in the second redundant signal line, and the second redundant signal line is electrically connected to the auxiliary line body at an intersection;

[0019] And / or, a part of the multiple auxiliary signal lines are the first auxiliary signal lines, and another part of the auxiliary signal lines are second auxiliary signal lines, the second lead portion is not provided in the second auxiliary signal line, and the second auxiliary signal line is electrically connected to the redundant line body at the intersection.

[0020] Optionally, when the display panel includes both the second redundant signal line and the second auxiliary signal line, the second redundant signal line and the second auxiliary signal line are electrically connected at an intersection.

[0021] Optionally, the display panel further includes: a first power signal line; the second redundant signal line is electrically connected to the first power signal line, and / or the second auxiliary signal line is electrically connected to the first power signal line.

[0022] Optionally, the light emitting device comprises: an anode, a light emitting layer and a cathode layer that are stacked, and the anode is closer to the substrate than the cathode layer;

[0023] The first pixel circuit is electrically connected to the anode of the corresponding light-emitting device, and the cathode layer is electrically connected to the first power signal line.

[0024] Optionally, the display panel further has a non-display area located outside the display area;

[0025] The display panel further includes: a plurality of connecting leads located in the non-display area and electrically connected to the plurality of data signal lines in a one-to-one correspondence, wherein a portion of the plurality of connecting leads is electrically connected to the corresponding data signal lines via the first lead portion and the second lead portion, and another portion of the plurality of connecting leads is directly electrically connected to the corresponding data signal lines;

[0026] Wherein, the plurality of connecting leads are used for binding and connecting with the driving component.

[0027] Optionally, the redundant signal line and the data signal line are provided in the same layer and made of the same material, and the redundant signal line and the auxiliary signal line are provided in different layers.

[0028] Optionally, the display panel further comprises: a gate driving circuit; the light emitting device comprises: an anode, a light emitting layer and a cathode layer that are stacked, the anode being closer to the substrate than the cathode layer;

[0029] The orthographic projection of the gate driving circuit on the substrate and the orthographic projection of the anode on the substrate have an overlapping area.

[0030] Optionally, the display area includes: a first display partition, a second display partition and a third display partition, and the second display partition is located between the first display partition and the third display partition;

[0031] The plurality of pixel circuits are all located in the first display subarea and the second display area, and are all located outside the third display subarea; at least part of the GOA circuit is located in the third display subarea;

[0032] Among them, the pixel circuits located in the first display partition include the first pixel circuit and the virtual pixel circuit; the pixel circuits located in the second display partition among the multiple pixel circuits are all the first pixel circuits, and a part of the first pixel circuits located in the second display area is electrically connected to the light-emitting device located in the second display area, and another part of the first pixel circuits located in the second display area is electrically connected to the light-emitting device located in the third display area.

[0033] Optionally, within the first display partition, multiple columns of the first pixel circuits and the multiple columns of the virtual pixel circuits are distributed alternately.

[0034] Optionally, N columns of the first pixel circuits are distributed between two adjacent columns of the virtual pixel circuits, where N is an integer greater than or equal to 2 and less than or equal to 6.

[0035] Optionally, the distribution density of the light-emitting devices distributed in the first display partition is equal to the distribution density of the light-emitting devices distributed in the second display partition.

[0036] Optionally, the multiple columns of the first pixel circuits located in the second display subarea are electrically connected to the anodes of the multiple columns of the light-emitting devices located in the second display subarea and the third display subarea respectively.

[0037] Optionally, the display panel further includes: a plurality of transparent connecting lines located in the second display area and the third display area;

[0038] Wherein, the anodes of at least some of the light-emitting devices located in the second display subarea and the third display subarea are electrically connected to the corresponding first pixel circuits through the transparent connecting lines.

[0039] Optionally, the display panel further includes: a plurality of auxiliary signal lines, wherein some of the auxiliary signal lines are located in the second display partition and the third display partition;

[0040] The transparent connecting line includes: a first transparent wiring portion and a second transparent wiring portion connected to each other, wherein the extending direction of the first transparent wiring portion is the same as the extending direction of the auxiliary signal line, and the extending direction of the second transparent wiring portion intersects with the extending direction of the auxiliary signal line;

[0041] The orthographic projection of the first transparent wiring portion on the substrate does not overlap with the orthographic projection of the auxiliary signal line on the substrate, and the orthographic projection of the second transparent wiring portion in at least part of the transparent connecting line on the substrate overlaps with the orthographic projection of the auxiliary signal line on the substrate.

[0042] Optionally, the area where the orthographic projection of at least one of the transparent connecting lines on the substrate overlaps with the orthographic projection of at least one of the auxiliary signal lines on the substrate accounts for less than or equal to 30% of the total area of ​​the orthographic projection of at least one of the transparent connecting lines on the substrate.

[0043] Optionally, orthographic projections of anodes of at least some of the light-emitting devices located in the second display subarea and the third display subarea on the substrate overlap with orthographic projections of at least two of the transparent signal lines on the substrate.

[0044] On the other hand, a display device is provided, characterized in that it includes: a power supply component, and a display panel electrically connected to the power supply component, and the display panel is the display panel mentioned above.

[0045] The beneficial effects of the technical solutions provided in the embodiments of the present application include at least:

[0046] A display panel includes: a substrate, multiple pixel circuits, multiple light-emitting devices, multiple data signal lines, and multiple redundant signal lines. A redundant signal line may include: a first lead portion connected to a data signal line. Here, the first lead portion can serve as a portion of a fan-out lead electrically connected to the data signal line. Since the redundant signal line is distributed within the display area, the portion of the fan-out lead used to electrically connect to the data signal line (i.e., the first lead portion) can be distributed within the display area, so that when the portion of the fan-out lead other than the first lead portion is distributed within the non-display area, the occupied space in the non-display area is reduced, thereby effectively reducing the width of the area in the non-display area where the fan-out lead is provided. In this way, the screen-to-body ratio of a display device integrated with such a display panel can be effectively improved, resulting in a better display effect of the display device. In addition, multiple data signal lines and multiple redundant signal lines can be located in the same conductive pattern, and this conductive pattern containing the data signal lines and the redundant signal lines can be evenly distributed within the display area. To this end, when a part of the first redundant signal line in the area where a column of virtual pixel circuits is located is used as the part of the fan-out lead located in the display area, it can be ensured that the various conductive layer patterns in the display panel are evenly distributed in the display area while ensuring that the part of the fan-out lead can be distributed in the display area, which can effectively reduce the probability of color deviation in the display panel and make the display effect of the display panel better. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0048] FIG1 is a top view of a display panel provided in an embodiment of the present application;

[0049] FIG2 is a partial enlarged view of the display panel at position A1 shown in FIG1 ;

[0050] FIG3 is a schematic diagram of the film layer structure of the display panel at position BB′ shown in FIG2 ;

[0051] FIG4 is a schematic diagram showing the connection between a plurality of light-emitting devices and a plurality of first pixel circuits provided in an embodiment of the present application;

[0052] FIG5 is a partial top view of another display panel provided in an embodiment of the present application;

[0053] FIG6 is a schematic diagram of the film structure of the display panel at CC' shown in FIG5;

[0054] FIG7 is a top view of another display panel provided in an embodiment of the present application;

[0055] FIG8 is a schematic diagram showing the distribution of redundant signal lines and auxiliary signal lines provided in an embodiment of the present application;

[0056] FIG9 is a schematic diagram of the film structure of the display panel at position DD′ shown in FIG8 ;

[0057] FIG10 is a schematic diagram of a film structure in a display area of ​​a display panel provided in an embodiment of the present application;

[0058] FIG11 is a partial top view of a display panel provided in an embodiment of the present application;

[0059] FIG12 is a top view of a display panel provided in another embodiment of the present application;

[0060] FIG13 is a top view of another display panel provided in another embodiment of the present application;

[0061] FIG14 is a partial enlarged view of the display panel at position A2 shown in FIG12 ;

[0062] FIG15 is another schematic diagram of the connection between multiple light-emitting devices and multiple first pixel circuits provided by an embodiment of the present application;

[0063] FIG16 is a schematic diagram of the electrical connection between the light emitting device and the first pixel circuit in A3 of the display panel shown in FIG12 ;

[0064] FIG17 is a schematic diagram showing the connection between an anode and a first pixel circuit of a light-emitting device provided in an embodiment of the present application;

[0065] FIG18 is a schematic diagram showing the distribution of transparent connecting lines and auxiliary signal lines provided in an embodiment of the present application;

[0066] FIG19 is a schematic diagram of the relative positional relationship between an anode and a transparent signal line of a light-emitting device provided in an embodiment of the present application;

[0067] FIG. 20 is a schematic diagram of the film layer structure of the display panel shown in FIG. 19 at EE′. DETAILED DESCRIPTION

[0068] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0069] Please refer to Figures 1, 2, and 3. Figure 1 is a top view of a display panel provided in an embodiment of the present application. Figure 2 is a partial enlarged view of the display panel shown in Figure 1 at position A1. Figure 3 is a schematic diagram of the film layer structure of the display panel shown in Figure 2 at position BB'. Display panel 000 may have a display area 00a and a non-display area 00b located outside the display area 00a. Display panel 000 may include: a substrate 100, a plurality of pixel circuits 200, a plurality of light-emitting devices 300, a plurality of data signal lines D10, and a plurality of redundant signal lines D20.

[0070] The multiple pixel circuits 200 in the display panel 000 can be arranged in an array on one side of the substrate 100, and the multiple pixel circuits 200 can all be located in the display area 00a. Among them, the multiple pixel circuits 200 may include: multiple first pixel circuits 201 and multiple virtual pixel circuits 202. Here, the multiple first pixel circuits 201 can be arranged in multiple columns, and the multiple virtual pixel circuits 202 can also be arranged in multiple columns, and the multiple columns of virtual pixel circuits 202 can be interspersed in the multiple columns of first pixel circuits 201. And the number of columns of first pixel circuits 201 is more than the number of columns of virtual pixel circuits 202. To this end, at least two columns of first pixel circuits 201 can be distributed between two adjacent columns of virtual pixel circuits 202. It should be noted that Figure 2 is for the purpose of easily seeing the distribution relationship of the multiple pixel circuits 200 in the display panel 000. Therefore, the light-emitting device 300 in the display panel 000 is not shown in Figure 2. Moreover, in FIG. 2 , each block P1 represents a first pixel circuit 201 , and each block P2 represents a virtual pixel circuit 202 .

[0071] The multiple light-emitting devices 300 in the display panel 000 can be located on the side of the multiple pixel circuits 200 away from the substrate 100, and the multiple light-emitting devices 300 can all be located in the display area 00a. Here, in order to more clearly see the connection relationship between the multiple light-emitting devices 300 and the multiple first pixel circuits 201, please refer to Figure 4. Figure 4 is a schematic diagram of the connection between multiple light-emitting devices and multiple first pixel circuits provided in an embodiment of the present application. The multiple light-emitting devices 300 can be electrically connected to the multiple first pixel circuits 201 in a one-to-one correspondence. Each first pixel circuit 201 is used to drive the corresponding light-emitting device 300 to emit light, so that the display surface 00a of the display panel 000 can present a corresponding display screen. It should be noted that the virtual pixel circuit 202 needs to be insulated from the light-emitting device 300, that is, there is no electrical connection between the virtual pixel circuit 202 and the light-emitting device 300.

[0072] The plurality of data signal lines D10 and the plurality of redundant signal lines D20 in the display panel 000 may both be located in the display area 00a. Here, the extending direction of the data signal lines D10 may be the same as the extending direction of the redundant signal lines D20.

[0073] The plurality of data signal lines D1 may correspond one-to-one to the plurality of columns of first pixel circuits 201, each data signal line D10 may be located within the region where the corresponding column of first pixel circuits 201 is located, and each data signal line D10 may be electrically connected to each first pixel circuit 201 in the corresponding column of first pixel circuits 201. Furthermore, the data signal line D10 may be insulated from the dummy pixel circuits 202, that is, there is no electrical connection between the data signal line D10 and the dummy pixel circuits 202.

[0074] The plurality of redundant signal lines D20 may correspond one-to-one to the plurality of columns of dummy pixel circuits 202. Each redundant signal line D20 may be located within the region where a corresponding column of dummy pixel circuits 202 is located, and each redundant signal line D20 needs to be insulated from each dummy pixel circuit in the corresponding column of dummy pixel circuits 202. In other words, there is no electrical connection between the redundant signal line D20 and the dummy pixel circuits 202.

[0075] It should be noted that the multiple first pixel circuits 201 and the multiple dummy pixel circuits 202 in the display panel 000 are formed simultaneously using the same process. During the formation of the multiple first pixel circuits 201, a data signal line D10 electrically connected to a column of first pixel circuits 201 is also formed. Therefore, during the formation of the multiple dummy pixel circuits 202, a redundant signal line D20 is also formed within the region where the column of dummy pixel circuits 202 is located. However, it is necessary to ensure that the redundant signal line D20 is insulated from the individual dummy pixel circuits in the column of dummy pixel circuits 202.

[0076] In the present application, at least some of the multiple redundant signal lines D20 within the display panel 000 may be first redundant signal lines D201. Here, a first redundant signal line D201 may include a first lead portion D21 connected to a data signal line D10. Here, the first lead portion D21 may serve as a portion of a fan-out lead electrically connected to the data signal line D10. Because the redundant signal line D20 is distributed within the display area 00a, the portion of the fan-out lead electrically connected to the data signal line D10 (i.e., the first lead portion D21) may be distributed within the display area 00a. This reduces the space occupied by the fan-out lead, excluding the first lead portion D21, within the non-display area 00b, effectively reducing the width of the area within the non-display area 00b where the fan-out lead is located. This effectively improves the screen-to-body ratio of a display device incorporating such a display panel 000, resulting in a better display quality.

[0077] It should be noted that in related art, additional signal leads electrically connected to data signal lines can be inserted between two adjacent columns of sub-pixels. These signal leads can serve as the portion of the fan-out leads located within the display area. However, some areas of such display panels require signal leads while others do not. This results in the conductive pattern used to form these signal leads being unevenly distributed within the display area, which in turn can lead to display issues such as color shift.

[0078] In the embodiment of the present application, the data signal lines D10 and the redundant signal lines D20 within the display panel 000 are arranged in the same layer and made of the same material. That is, the data signal lines D10 and the redundant signal lines D20 are formed through the same patterning process. In other words, the data signal lines D10 and the redundant signal lines D20 within the display panel 000 can be located within the same conductive pattern. Because the multiple columns of dummy pixel circuits 202 are interspersed within the multiple columns of first pixel circuits 201, the multiple redundant signal lines D20 within the display panel 000 are also interspersed within the multiple data signal lines D10. To this end, the conductive pattern including the data signal line D10 and the redundant signal line D20 can be evenly distributed within the display area 00a. When a portion of the first redundant signal line D201 within the region where a column of virtual pixel circuits 202 is located is used as the portion of the fan-out lead located within the display area 00a, the conductive layer patterns within the display panel 000 can be evenly distributed within the display area 00a, while ensuring that the portion of the fan-out lead can be distributed within the display area 00a. This effectively reduces the probability of color shift in the display panel 000, resulting in a better display quality for the display panel 000.

[0079] In summary, the display panel provided by the embodiment of the present application includes: a substrate, a plurality of pixel circuits, a plurality of light-emitting devices, a plurality of data signal lines and a plurality of redundant signal lines. A redundant signal line may include: a first lead portion connected to a data signal line. Here, the first lead portion can be used as a part of a fan-out lead electrically connected to this data signal line. Since the redundant signal line is distributed in the display area, the part of the fan-out lead used to be electrically connected to the data signal line (that is, the first lead portion) can be distributed in the display area, so that when the part of the fan-out lead other than the first lead portion is distributed in the non-display area, the occupied space in the non-display area is reduced, thereby effectively reducing the width of the area where the fan-out lead is set in the non-display area. In this way, the screen-to-body ratio of the display device integrating such a display panel can be effectively improved, so that the display effect of the display device is better. In addition, multiple data signal lines and multiple redundant signal lines can be located in the same conductive pattern, and this conductive pattern containing the data signal lines and the redundant signal lines can be evenly distributed in the display area. To this end, when a part of the first redundant signal line in the area where a column of virtual pixel circuits is located is used as the part of the fan-out lead located in the display area, it can be ensured that the various conductive layer patterns in the display panel are evenly distributed in the display area while ensuring that the part of the fan-out lead can be distributed in the display area, which can effectively reduce the probability of color deviation in the display panel and make the display effect of the display panel better.

[0080] In an embodiment of the present application, as shown in FIG5 , which is a partial top view of another display panel provided in an embodiment of the present application, the display panel 000 may further include: a plurality of gate lines G10. Here, the extending direction of the gate lines G10 may intersect with the extending direction of the data signal lines D10. For example, the extending direction of the gate lines G10 may be perpendicular to the extending direction of the data signal lines D10.

[0081] The plurality of pixel circuits 200 within the display panel 000 may be arranged in an array of multiple rows, and the multiple rows of pixel circuits 200 may correspond one-to-one to the plurality of gate lines G10. Each gate line G10 may be located within a region where a corresponding row of pixel circuits 200 is located, and each gate line G10 may be electrically connected to each first pixel circuit 201 within a corresponding row of pixel circuits 200. Furthermore, the gate line G10 may be insulated from the dummy pixel circuit 202, that is, there is no electrical connection between the gate line G10 and the dummy pixel circuit 202.

[0082] Optionally, as shown in FIG5 , the display panel 000 may further include a plurality of auxiliary signal lines G20 located within the display area 00a. Here, the auxiliary signal lines G20 may extend in a direction that intersects with the redundant signal lines D20. For example, the auxiliary signal lines G20 may extend in a direction perpendicular to the redundant signal lines D20.

[0083] In the present application, the extension direction of the auxiliary signal line G20 can be the same as the extension direction of the gate line G10. It should be noted that, due to the high density of the gate lines G10 in the display panel 000, even if the extension direction of the auxiliary signal line G20 is the same as that of the gate line G10, it is necessary to ensure that the auxiliary signal line G20 and the gate line G10 are distributed in different layers. That is, the conductive pattern where the auxiliary signal line G20 is located is different from the conductive pattern where the gate line G10 is located, and an insulating layer is distributed between the conductive pattern where the auxiliary signal line G20 is located and the conductive pattern where the gate line G10 is located.

[0084] Here, the auxiliary signal line G20 and the redundant signal line D20 are also distributed in different layers. That is, the conductive pattern where the auxiliary signal line G20 is located is different from the conductive pattern where the redundant signal line D20 is located, and an insulating layer is disposed between the conductive pattern where the auxiliary signal line G20 is located and the conductive pattern where the redundant signal line D20 is located. This ensures that no short circuit occurs between the auxiliary signal line G20 and the data signal line D10, and also ensures that no short circuit occurs between the gate line G10 and the data signal line D10.

[0085] Among them, multiple auxiliary signal lines G20 in the display panel 000 can correspond one-to-one to multiple rows of pixel circuits 200, each auxiliary signal line G20 can be located in the area where the corresponding row of pixel circuits 200 is located, and each auxiliary signal line G20 can be insulated from each pixel circuit in the corresponding row of pixel circuits 200, that is, there is no electrical connection between the auxiliary signal line G20 and the pixel circuit 200.

[0086] In the present application, at least some of the multiple auxiliary signal lines G20 are first auxiliary signal lines G201. Here, an auxiliary signal line G20 may include a second lead portion G21, and one end of the second lead portion G21 may be electrically connected to the data signal line D10, and the other end may be electrically connected to one end of the first lead portion D21. In this case, the portion of the fan-out lead connected to the data signal line D10 located within the display area 00a may include a second lead portion G21 and a first lead portion D21. After the multiple fan-out leads within the display panel are bound and connected to the driver chip, the drive signal can sequentially transmit the data signal to the data signal line D10 through the portion of the fan-out lead located within the non-display area 00b, the first lead portion D21, and the second lead portion G21.

[0087] Here, since an auxiliary signal line G20 is distributed within each row of pixel circuits 200, the conductive pattern including multiple auxiliary signal lines G20 can be evenly distributed within the display area 00a. Furthermore, the conductive pattern including multiple redundant signal lines D20 is also evenly distributed within the display area 00a. Therefore, when a portion of the auxiliary signal lines G20 and a portion of the redundant signal lines D20 are used as the portion of the fan-out leads located within the display area 00a, the conductive layer patterns within the display panel 000 can be evenly distributed within the display area 00a while ensuring that the portion of the fan-out leads can be distributed within the display area 00a. This can further reduce the probability of color shift in the display panel 000.

[0088] In the embodiment of the present application, as shown in FIG6 , FIG6 is a schematic diagram of the film layer structure at the CC' position of the display panel shown in FIG5 . Because an insulating layer 001 exists between the conductive pattern where the data signal line D10 is located and the conductive pattern where the auxiliary signal line G20 is located, it is necessary to provide a first via hole V1 and a second via hole V2 in the display panel 000 for penetrating the insulating layer 001 so that one end of the second lead portion G21 in the first auxiliary signal line G201 can be overlapped with the data signal line D10 through the first via hole V1, and the other end of the second lead portion G21 in the first auxiliary signal line G201 can be overlapped with one end of the first lead portion G21 in the first redundant signal line D201 through the second via hole V2.

[0089] It should be noted that the portion of the redundant signal lines D20 other than the first lead portion D21 is not loaded with a drive signal, resulting in it being suspended. When the portion of the redundant signal lines D20 other than the first lead portion D21 is suspended, it may interfere with the gate scan signal loaded on the gate line G10 intersecting it. Similarly, the portion of the auxiliary signal lines G20 other than the second lead portion G21 is not loaded with a drive signal, resulting in it also being suspended. When the portion of the auxiliary signal lines G20 other than the second lead portion G21 is suspended, it may interfere with the data signal recorded on the data signal line D10 intersecting it.

[0090] To this end, the embodiment of the present application requires further processing of the portions of the multiple redundant signal lines D20 except the first lead portion D21, and the portions of the multiple auxiliary signal lines G20 except the second lead portion G21, to ensure that these signal lines do not interfere with the signals loaded on other signal lines.

[0091] For example, as shown in FIG7 , which is a top view of another display panel provided in an embodiment of the present application, the display panel 000 may further include: a first power signal line 400 located in the non-display area 00b. Here, the first power signal line 400 may be a low-level power signal line (i.e., a VSS power signal line), and the first power signal line 400 may be a ring-shaped power signal line.

[0092] Here, portions of the plurality of redundant signal lines D20 excluding the first lead portion D21 may be electrically connected to the first power signal line 400, and / or portions of the plurality of auxiliary signal lines G20 excluding the second lead portion G21 may be electrically connected to the first power signal line 400. It should be noted that FIG. 7 is a schematic illustration of an example in which portions of the plurality of redundant signal lines D20 excluding the first lead portion D21 and portions of the plurality of auxiliary signal lines G20 excluding the second lead portion G21 are both electrically connected to the first power signal line 400.

[0093] Since the first power signal line 400 carries a fixed-potential VSS signal, when the portions of the redundant signal lines D20 other than the first lead portion D21 are electrically connected to the first power signal line 400, the portions of the redundant signal lines D20 other than the first lead portion D21 can also be loaded with the fixed-potential VSS signal. When the portions of the auxiliary signal lines G20 other than the second lead portion G21 are electrically connected to the first power signal line 400, the portions of the auxiliary signal lines G20 other than the second lead portion G21 can also be loaded with the fixed-potential VSS signal. This ensures that the portions of the redundant signal lines D20 other than the first lead portion D21 and the portions of the auxiliary signal lines G20 other than the second lead portion G21 are no longer suspended, preventing the portions of the redundant signal lines D20 other than the first lead portion D21 from interfering with the gate line G10, and preventing the portions of the auxiliary signal lines G20 other than the second lead portion G21 from interfering with the data line D1.

[0094] Optionally, the portions of the multiple redundant signal lines D20 within the display panel 000, excluding the first lead portion D21, may be electrically connected to the portions of the multiple auxiliary signal lines G20, excluding the second lead portion G21. In this way, as long as one of the portions of the multiple redundant signal lines D20 excluding the first lead portion D21 and the portions of the multiple auxiliary signal lines G20 excluding the second lead portion G21 is connected to the first power signal line 400, it is possible to ensure that the first power signal line 400 can provide a VSS signal to the portions of the multiple redundant signal lines D20 excluding the first lead portion D21. This also ensures that the first power signal line 400 can provide a VSS signal to the portions of the multiple auxiliary signal lines G20 excluding the second lead portion G21.

[0095] For example, as shown in FIG8 , which is a schematic diagram of the distribution of redundant signal lines and auxiliary signal lines provided in an embodiment of the present application, a first redundant signal line D201, in addition to including a first lead portion D21, may also include a redundant line body D22 disconnected from the first lead portion D21. For example, a first partition U1 is provided between the first lead portion D21 and the redundant line body D22 in the first redundant signal line D201, and the first lead portion D21 and the redundant line body D22 are insulated by the first partition U1. A first auxiliary signal line G201, in addition to including a second lead portion G21, may also include an auxiliary line body G22 disconnected from the second lead portion G21. For example, a second partition U2 is provided between the second lead portion G21 and the auxiliary line body G22 in the first auxiliary signal line G201, and the second lead portion G21 and the auxiliary line body G22 are insulated by the second partition U2.

[0096] In which, the redundant line body D22 in the first redundant signal line D201 can be electrically connected to the auxiliary line body G22 in the first auxiliary signal line G201 at the intersection, so that the part of the first redundant signal line D201 except the first lead part D21 can be electrically connected to the part of the first auxiliary signal line G201 except the second lead part G21.

[0097] It should be noted that, in the display panel 000 , not every redundant signal line D20 needs to be provided with the first lead portion D21 , and not every auxiliary signal line G1 needs to be provided with the second lead portion G21 .

[0098] To this end, some of the multiple redundant signal lines D20 within the display panel 000 may be first redundant signal lines D201, while others may be second redundant signal lines D202. The first redundant signal lines D201 may include both first lead portions D21 and redundant signal line bodies D22, while the second redundant signal lines D201 lack first lead portions D21 and are single, uninterrupted signal lines. The second redundant signal lines D202 may be electrically connected to the auxiliary signal line bodies G22 within the first auxiliary signal lines G201 at their intersections.

[0099] And / or, among the multiple auxiliary signal lines G20 within the display panel 000, some of the auxiliary signal lines G20 may be first auxiliary signal lines G201, while others may be second auxiliary signal lines G202. Here, the first auxiliary signal line G201 may include both the second lead portion G21 and the auxiliary line body G22, while the second auxiliary signal line G202 does not include the second lead portion G21. The second auxiliary signal line G202 is a single signal line without any internal partitions. The second auxiliary signal line G202 may be electrically connected to the redundant line body D22 of the first redundant signal line D201 at the intersection.

[0100] In an embodiment of the present application, when the display panel 000 includes both the second redundant signal line D202 and the second auxiliary signal line G202 , the second redundant signal line D202 and the second auxiliary signal line G202 may be electrically connected at the intersection.

[0101] In this case, the portions of the plurality of redundant signal lines D20, excluding the first lead portion D21, and the portions of the plurality of auxiliary signal lines G20, excluding the second lead portion G21, within the display panel 000 are electrically connected at their intersections. Furthermore, the portions of the plurality of redundant signal lines D20, excluding the first lead portion D21, and the portions of the plurality of auxiliary signal lines G20, excluding the second lead portion G21, can form a grid-like conductive layer within the display panel 000.

[0102] For example, please refer to Figure 9, which is a schematic diagram of the film layer structure at the D-D' position of the display panel shown in Figure 8. Because an insulating layer 001 exists between the conductive pattern where the redundant signal line D20 is located and the conductive pattern where the auxiliary signal line G20 is located, it is necessary to provide a third via V3 in the display panel 000 to penetrate the insulating layer 001 so that the portions of the multiple redundant signal lines D20 other than the first lead portion D21 and the portions of the multiple auxiliary signal lines G20 other than the second lead portion G21 can overlap at the intersection through the third via V3.

[0103] In the present application, the end of the second redundant signal line D202 in the display panel 000 can be electrically connected to the first power signal line 400, and / or the end of the second auxiliary signal line G202 can be electrically connected to the first power signal line 400. Of course, the end of the redundant line body D22 in the first redundant signal line D201 can also be electrically connected to the first power signal line 400, and / or the end of the auxiliary line body G22 in the first auxiliary signal line G201 can also be electrically connected to the first power signal line 400. In this way, the grid-like conductive layer in the display panel 000, which is composed of the portions of the multiple redundant signal lines D20 excluding the first lead portion D21 and the portions of the multiple auxiliary signal lines G20 excluding the second lead portion G21, can be connected to the first power signal line 400.

[0104] In an embodiment of the present application, as shown in Figure 10, which is a schematic diagram of the film layer structure within the display area of ​​a display panel provided in an embodiment of the present application, the light-emitting device 300 in the display panel 000 may include: an anode 301, a light-emitting layer 302, and a cathode layer 303 arranged in a stacked manner. Here, the anode 301 of the light-emitting device 300 is closer to the substrate 100 than the cathode layer 303.

[0105] Optionally, the display panel 000 may further include a pixel definition layer 500. The conductive pattern where the anode 301 is located is closer to the substrate 100 than the pixel definition layer 500. The cathode layer 303 may be located on the side of the pixel definition layer 500 facing away from the substrate 100. The light-emitting layer 302 may be located between the anode 301 and the cathode layer 303. Here, the pixel definition layer 500 may have pixel openings 501 corresponding to a plurality of light-emitting devices 300. The orthographic projection of each pixel opening 501 on the substrate 100 may be located within the orthographic projection of the anode 301 in the corresponding light-emitting device 300 on the substrate 100. It should be noted that both the light-emitting layer 302 and the cathode layer 303 are integral film structures. Therefore, in the display panel 000, the portion of the anode 301 located within the corresponding pixel opening 501, the portion of the light-emitting layer 302 located within the pixel opening 501, and the portion of the cathode layer 303 located within the pixel opening 501 constitute a single light-emitting device 300. For example, the light emitting device 300 may be an organic light emitting diode (OLED) device.

[0106] In the present application, each first pixel circuit 201 in the display panel 000 may be electrically connected to the anode 301 in the corresponding light emitting device 300 , and the cathode layer 303 in the light emitting device 300 may be electrically connected to the first power signal 400 .

[0107] Here, since the cathode layer 303 in the display panel 000 is a film structure provided as a whole layer, when the cathode layer 303 is electrically connected to the first power signal line 400, the first power signal line 400 can provide a VSS signal to each light-emitting device 300. Furthermore, since the cathode layer 303 is generally thin, its resistance is generally relatively high. Furthermore, when a grid-shaped conductive layer is formed by the portions of the plurality of redundant signal lines D20 excluding the first lead portion D21 and the plurality of auxiliary signal lines G20 excluding the second lead portion G21, and is electrically connected to the cathode layer 303, the grid-shaped conductive layer can serve as an auxiliary electrode for the cathode layer 303. Therefore, the grid-shaped conductive layer can reduce the resistance of the cathode layer 303, ensuring that the VSS signal at each position on the cathode layer 303 is consistent, thereby ensuring good uniformity when the VSS signal is applied to the cathode layer 303.

[0108] Optionally, the display panel 000 may further include a second power signal line (not shown), at least a portion of which may be located within the display area 00a, and the second power signal line may be electrically connected to each active driving circuit 201 within the display area 00a. Here, the second power signal line may be a high-level signal line (i.e., a VDD power signal line), through which a VDD signal may be applied to each active driving circuit 201, thereby enabling the active driving circuit 201 to drive the corresponding light-emitting device 300 to emit light.

[0109] In an embodiment of the present application, as shown in FIG11 , FIG11 is a partial top view of a display panel provided in an embodiment of the present application. The display panel 000 may further include: a plurality of connecting leads F corresponding one-to-one with the plurality of data signal lines D10. The plurality of connecting leads F may be located within the non-display area 00b of the display panel 000. A portion of the plurality of connecting leads F may be electrically connected to the corresponding data signal line D10 via the first lead portion D21 and the second lead portion G21. When a connecting lead F needs to be electrically connected to the corresponding data signal line D10 via the first lead portion D21 and the second lead portion G21, the connecting lead F, the first lead portion D21, and the second lead portion D22 may constitute a fan-out lead corresponding to the data signal line D10. This ensures that a portion of the fan-out leads are located within the display area 00a, effectively reducing the space occupied by the fan-out leads within the non-display area 00b. Another portion of the plurality of connecting leads F may be directly electrically connected to the corresponding data signal line D10. When a connecting lead F is directly electrically connected to the data signal line D10, the connecting lead F is a fan-out lead corresponding to the data signal line D10.

[0110] In the present application, a plurality of connecting leads F located within the non-display area 00b are used to bind and connect to the driving component. For example, the driving component can be bound at position B1 within the non-display area 00b, so that the driving component can provide data signals to the corresponding data signal lines D10 through these connecting leads F.

[0111] For example, to connect multiple data signal lines D10 in display panel 000 to the driver chip, it is typically necessary to connect multiple data signal lines D1 to the driver chip by converging from the sides toward the center. Furthermore, because the data signal lines D10 located on both sides of the driver chip's binding position B1 are farther away from the driver chip, the data signal lines D10 located in the center are closer to the driver chip. Therefore, the data signal lines D10 located on both sides need to connect to the corresponding connecting leads F via the second lead portion G21 and the first lead portion D21, while the data signal lines D10 located in the center can connect directly to the corresponding connecting leads F.

[0112] Here, for the data signal lines D10 located on both sides, the driving component can sequentially apply data signals to these data signal lines D10 through the corresponding connecting leads F, the first lead portion D21, and the second lead portion G21. For the data signal lines D10 located in the center, the driving component can directly apply data signals to these data signal lines D10 through the corresponding connecting leads F.

[0113] In an embodiment of the present application, as shown in Figure 12, Figure 12 is a top view of a display panel provided by another embodiment of the present application. Display panel 000 may also include: gate drive (English: Gate Driver On Array, abbreviated as: GOA) circuit 600, at least part of the GOA circuit 600 can be located in the display area 00a of display panel 000. Here, the number of GOA circuit 600 is generally two, and two GOA circuits 600 can be distributed on both sides of display panel 000, and the two ends of each gate line G10 in display panel 000 can be electrically connected to these two GOA circuits 600, and gate scan signals can be provided to each gate line G10 by GOA circuit 600. In the present application, since at least part of the GOA circuit 600 in display panel 000 is located in display 00a, the width of the non-display area 00b of display panel 000 can be further reduced. In this way, the screen ratio of the display device integrating this display panel can be further improved.

[0114] For example, please refer to Figure 13, which is a top view of another display panel provided by another embodiment of the present application. The orthographic projection of the gate drive circuit 600 in the display panel 000 on the substrate 100 can overlap with the orthographic projection of the anode 301 in the light-emitting device 300 on the substrate 100. To this end, some of the light-emitting devices 300 in the display panel 000 can be distributed on the side of the gate drive circuit 600 facing away from the substrate 100, so that the area of ​​the display panel 600 where the gate drive circuit 600 is located can also display the image normally.

[0115] In the present application, the display area 00a of the display panel 000 may include: a first display partition 00a1, a second display partition 00a2, and a third display partition 00a3. The second display partition 00a2 may be located between the first display partition 00a1 and the third display partition 00a3, and light-emitting devices 300 may be distributed in the first display partition 00a1, the second display partition 00a2, and the third display partition 00a3. Therefore, the light-emitting devices 300 in these three display partitions can ensure that the three display partitions can display corresponding images.

[0116] Here, the plurality of pixel circuits 200 in the display panel 000 may be located in the first display partition 00a1 and the second display partition 00a2, and these pixel circuits 200 are all located outside the third display partition 00a3. At least a portion of the GOA circuit 600 in the display panel 000 may be located in the third display partition 00a3. It should be noted that, since the pixel circuit 200 and the GOA circuit 600 may generally include transistors, and the transistors in the pixel circuit 200 and the crystals in the GOA circuit 600 are generally formed at the same time, in the present application, the pixel circuit 200 is disposed outside the third display partition 00a3, and at least a portion of the GOA circuit 600 is disposed in the third display partition 00a3. This ensures that there is no mutual interference between the setting position of the GOA circuit 600 and the setting position of the pixel circuit 200, while ensuring that the GOA circuit 600 is disposed in the display area 00a.

[0117] In the present application, the pixel circuits 200 located in the first display subarea 00a1 may include: first pixel circuits 201 and dummy pixel circuits 202. Among the pixel circuits 200, the pixel circuits located in the second display subarea 00a2 may all be first pixel circuits 201. Part of the first pixel circuits 201 located in the second display subarea 00a2 may be electrically connected to the light-emitting device 300 located in the second display subarea 00a2, and another part of the first pixel circuits 201 located in the second display subarea 00a2 may be electrically connected to the light-emitting device 300 located in the third display subarea 00a3.

[0118] It should be noted that, within the first display partition 00a, multiple columns of first pixel circuits 201 and multiple columns of virtual pixel circuits 202 are staggered. The number of columns of first pixel circuits 201 is greater than the number of columns of virtual pixel circuits 202. For this reason, at least two columns of first pixel circuits 201 can be distributed between two adjacent columns of virtual pixel circuits 202. In this case, compared with the display panel in the related art in which multiple pixel circuits are electrically connected to multiple light-emitting devices in a one-to-one correspondence, the multiple pixel circuits 200 in the display panel 000 in the embodiment of the present application are equivalent to compressing the multiple pixel circuits in the display panel in the related art in the row direction. For this reason, the pixel circuits 200 in the embodiment of the present application will be greater than the number of light-emitting devices 300, and in the display panel 000 in the embodiment of the present application, the width of the pixel circuits 200 in the row direction is much smaller than the width of the light-emitting device 300.

[0119] For example, as shown in Figure 14, Figure 14 is a partial enlarged view of the display panel shown in Figure 12 at A2. In the first display partition 00a of the display panel 000, the ratio of the number of columns of multiple columns of first pixel circuits 201 to the number of columns of multiple columns of virtual pixel circuits 202 is N:1. That is, N columns of virtual pixel circuits 202 can be distributed between two adjacent columns of virtual pixel circuits 202. Here, N can be an integer greater than or equal to 2 and less than or equal to 6. In this way, please refer to Figure 15, which is another schematic diagram of the connection between multiple light-emitting devices and multiple first pixel circuits provided in an embodiment of the present application. When N is equal to 4, in the first display partition 00a, four columns of first pixel circuits 201 and one column of virtual pixel circuits 202 can be distributed in the area where four columns of adjacent light-emitting devices 300 are located, and these four columns of first pixel circuits 201 are electrically connected to the four columns of adjacent light-emitting devices 300 in a one-to-one correspondence. It should be noted that the four adjacent columns of light-emitting devices 300 can be: one column of red light-emitting devices, one column of blue light-emitting devices, and two columns of green light-emitting devices. Thus, the light-emitting devices within the display panel 000 are arranged in an RGBB pattern. In the row direction of the plurality of light-emitting devices 300, one red light-emitting device R, one blue light-emitting device B, and two green light-emitting devices G arranged adjacent to each other can form a pixel.

[0120] In the embodiment of the present application, the light-emitting devices 300 distributed in the first display subarea 00a1, the light-emitting devices 300 distributed in the second display subarea 00a2, and the light-emitting devices 300 distributed in the third display subarea 00a3 are distributed at equal densities. This ensures that the display effect of the first display subarea 00a1 is substantially consistent with that of the second display subarea 00a2, and substantially consistent with that of the third display subarea 00a3, thereby effectively improving the overall display effect of the display panel.

[0121] It should be noted that since there are two GOA circuits 600 in the display panel 000, the number of third display subareas 00a3 in the display area 00a also needs to be two, so that the two GOA circuits are respectively arranged between the two third display subareas 00a3. Furthermore, since the second display subarea 00a2 needs to be arranged between the third display subarea 00a3 and the first display subarea 00a1, the number of second display subareas 00a2 in the display area 00a also needs to be two. In this case, the first display subarea 00a1 in the display area 00a needs to be located between the two second display subareas 00a2, and the third display subarea 00a3 needs to be located on the side of the second display subarea 00a2 facing away from the first display subarea 00a1.

[0122] In the embodiment of the present application, the distribution density of the pixel circuits 200 distributed in the first display partition 00a1 is equal to the distribution density of the pixel circuits 200 distributed in the second display partition 00a2.

[0123] In this case, please refer to Figure 16, which is a schematic diagram of the electrical connections between the light-emitting devices and the first pixel circuits in A3 of the display panel shown in Figure 12. Because the pixel circuits 200 in the second display subarea 00a2 are all first pixel circuits 201, and the width of the pixel circuits 200 in the row direction is much smaller than the width of the light-emitting devices 300, the number of columns of first pixel circuits 201 in the second display subarea 00a2 is greater than the number of columns of light-emitting devices 300. In this way, a portion of the first pixel circuits 201 in the second display subarea 00a2 can be electrically connected one-to-one with the multiple light-emitting devices 300 in the second display subarea 00a2. However, a redundant portion of the first pixel circuits 201 in the second display subarea 00a2 does not need to be electrically connected to the multiple light-emitting devices 300 in the second display subarea 00a2. Instead, these first pixel circuits 201 can be electrically connected one-to-one with the multiple light-emitting devices 300 in the third display subarea 00a3.

[0124] For example, the number of columns of first pixel circuits 201 within the second display partition 00a2 is the same as the number of columns of light-emitting devices 300 within the second display partition 00a2 and the third display partition 00a3. That is, the sum of the number of columns of light-emitting devices 300 within the second display partition 00a2 and the third display partition 00a3 is equal to the number of columns of first pixel circuits 201 within the second display partition 00a2. In this way, multiple columns of first pixel circuits 201 within the second display partition 00a2 can be electrically connected to multiple columns of light-emitting devices 300 within the second display partition 00a2 and the third display partition 00a3 in a one-to-one correspondence. In other words, multiple columns of first pixel circuits 201 within the second display partition 00a2 can be electrically connected to the anodes 301 of multiple columns of light-emitting devices 300 within the second display partition 00a2 and the third display partition 00a3, respectively. In this way, while ensuring that the first pixel circuit 201 is not provided in the third display subarea 00a3, the anode 301 in the light-emitting device 300 in the third display subarea 00a3 is connected to the first pixel circuit 201 in the second display subarea 00a, so that the GOA circuit 600 can be provided in the third display subarea 00a3. In this way, the GOA circuit 600 can be hidden in the third display subarea 00a3 in the display area 00a.

[0125] In an embodiment of the present application, as shown in FIG17 , which is a schematic diagram illustrating the connection between an anode of a light-emitting device and a first pixel circuit according to an embodiment of the present application, the display panel 000 may further include: a plurality of transparent connecting lines L located within the second display subarea 00a2 and the third display subarea 00a3. Here, the anodes 301 of at least some of the light-emitting devices 300 located within the second display subarea 00a2 and the third display subarea 00a3 may be electrically connected to the corresponding first pixel circuits 201 via the transparent connecting lines L. In this way, since the transparent connecting line L has a high transmittance to light and a low reflectivity to light, when the anode 301 of the light-emitting device 300 distributed in the second display partition 00a2 and the third display partition 00a3 is connected to the corresponding first pixel circuit 201 through the transparent connecting line L, it can be ensured that the light-emitting devices 300 distributed in the second display partition 00a2 and the third display partition 00a3 can be normally connected to the corresponding first pixel circuit 201, and the reflectivity of the second display partition 00a2 and the third display partition 00a3 to ambient light is basically consistent with the reflectivity of the first display partition 00a1 to ambient light, so that the reliability of the display panel 000 is higher.

[0126] In an embodiment of the present application, as shown in FIG18 , FIG18 is a schematic diagram of the distribution of a transparent connecting line and auxiliary signal routing provided by an embodiment of the present application. The transparent connecting line L may include: a first transparent routing portion L1 and a second transparent routing portion L2 connected to each other. The extending direction of the first transparent routing portion L1 in the transparent connecting line L is the same as the extending direction of the auxiliary signal line G20, and the extending direction of the second transparent routing portion L2 intersects the extending direction of the auxiliary signal line G20.

[0127] In the present application, the orthographic projection of the first transparent routing portion L1 of each transparent connecting line L within the display panel 000 on the substrate 100 may not overlap with the orthographic projection of the auxiliary signal line G20 on the substrate 100, and the orthographic projection of the second transparent routing portion L2 of at least some of the transparent connecting lines L within the display panel 000 on the substrate 100 overlaps. In this case, the area of ​​the orthographic projection of the transparent connecting line L within the display panel 000 on the substrate 100 that overlaps with the orthographic projection of the auxiliary signal line G20 on the substrate 100 can be ensured to be small, thereby reducing the parasitic capacitance generated between the transparent connecting line L and the auxiliary signal line G20. For example, the area of ​​the orthographic projection of at least one transparent connecting line L on the substrate 100 that overlaps with the orthographic projection of at least one auxiliary signal line G20 on the substrate 100 accounts for less than or equal to 30% of the total area of ​​the orthographic projection of the at least one transparent connecting line L on the substrate 100. In this way, it can be ensured that when the first pixel circuit 201 transmits a signal to the anode 301 of the corresponding light-emitting device 300 through the transparent connecting line L, the transparent connecting line L is less interfered by the auxiliary signal line G20, thereby ensuring that the light emitted by the light-emitting devices 300 in the second display partition 00a2 and the third display partition 00a3 has a better effect.

[0128] Optionally, please refer to Figure 19, which is a schematic diagram of the relative positional relationship between the anode and transparent signal line of a light-emitting device provided in an embodiment of the present application. The orthographic projections of the anodes 301 of at least some of the light-emitting devices 300 located in the second display partition 00a2 and the third display partition 00a3 on the substrate 100 overlap with the orthographic projections of at least two of the transparent signal lines on the substrate. Here, there may be no electrical connection between the anodes 301 and the transparent signal lines L whose orthographic projections on the substrate 100 overlap. That is, the transparent signal lines L need to pass through other light-emitting devices 300 before being electrically connected to the anodes 301 in the corresponding light-emitting devices 300.

[0129] In this case, referring to FIG. 20 , which is a schematic diagram of the film structure of the display panel at line EE′ shown in FIG. 19 , at least two transparent signal lines L are located below the anode 301 in the light-emitting device 300 (i.e., on the side close to the substrate 100). This ensures a high degree of flatness of the anode 301, thereby improving the effect of light emitted by the light-emitting device 300.

[0130] In an embodiment of the present application, as shown in FIG20 , a first flat layer 701 is present between the conductive layer where the transparent signal line L is located and the conductive layer where the anode 301 is located within the display panel 000. The conductive layer where the data signal line D10 is located within the display panel 000 can be located on the side of the first flat layer 701 facing the substrate 100, and the data signal line D10 within the display panel 000 can be provided on the same layer and made of the same material as the VDD power supply signal line. Here, a second flat layer 702 is present between the conductive layer where the data signal line D10 is located and the conductive layer where the transparent signal line L is located. The auxiliary signal line G20 within the display panel 000 can be located on the side of the second flat layer 702 facing the substrate 100, and a third flat layer 703 is present between the conductive layer where the second auxiliary signal line G20 is located and the conductive layer where the data signal line D10 is located.

[0131] It should be noted that each pixel circuit 200 and GOA circuit 600 in the present application can be distributed on the side of the third flat layer 703 facing the substrate 100. To this end, it is necessary to open a connection through hole in the first flat layer 701, the second flat layer 702 and the third flat layer 703 so that the first pixel circuit 201 can be electrically connected to the anode 301 in the corresponding light-emitting device 300 through the connection through hole. In addition, the flat layer between the dummy pixel circuit 202 and the light-emitting device 300 in the display panel 000 is not provided with a connection through hole, so that the dummy pixel circuit 202 and the light-emitting device 300 can be insulated by the flat layer. Similarly, the flat layer between the GOA circuit 600 and the light-emitting device 300 in the display panel 000 is not provided with a connection via, so that the GOA circuit 600 and the light-emitting device 300 can be insulated by the flat layer.

[0132] In the embodiment of the present application, the display panel 000 may further include an encapsulation layer. The encapsulation layer may be located on a side of the plurality of light-emitting devices 300 facing away from the substrate 100. The encapsulation layer isolates the light-emitting devices 300 from moisture and oxygen in the external environment, preventing moisture and oxygen from corroding the light-emitting layer 302 of the light-emitting devices 300, thereby ensuring a longer service life for the light-emitting devices 300.

[0133] In summary, the display panel provided by the embodiment of the present application includes: a substrate, a plurality of pixel circuits, a plurality of light-emitting devices, a plurality of data signal lines and a plurality of redundant signal lines. A redundant signal line may include: a first lead portion connected to a data signal line. Here, the first lead portion can be used as a part of a fan-out lead electrically connected to this data signal line. Since the redundant signal line is distributed in the display area, the part of the fan-out lead used to be electrically connected to the data signal line (that is, the first lead portion) can be distributed in the display area, so that when the part of the fan-out lead other than the first lead portion is distributed in the non-display area, the occupied space in the non-display area is reduced, thereby effectively reducing the width of the area where the fan-out lead is set in the non-display area. In this way, the screen-to-body ratio of the display device integrating such a display panel can be effectively improved, so that the display effect of the display device is better. In addition, multiple data signal lines and multiple redundant signal lines can be located in the same conductive pattern, and this conductive pattern containing the data signal lines and the redundant signal lines can be evenly distributed in the display area. To this end, when a part of the first redundant signal line in the area where a column of virtual pixel circuits is located is used as the part of the fan-out lead located in the display area, it can be ensured that the various conductive layer patterns in the display panel are evenly distributed in the display area while ensuring that the part of the fan-out lead can be distributed in the display area, which can effectively reduce the probability of color deviation in the display panel and make the display effect of the display panel better.

[0134] Embodiments of the present application also provide a display device. This display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. This display device can include a power supply component and a display panel. The display panel can be the display panel described in the above embodiments.

[0135] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it may be the only layer between the two layers or elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0136] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "plurality" refers to two or more than two, unless expressly limited otherwise.

[0137] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: The display panel has a display area, and the display panel includes: substrate; A plurality of pixel circuits arranged in an array on one side of the substrate, the plurality of pixel circuits comprising: a plurality of first pixel circuits and a plurality of virtual pixel circuits; a plurality of light-emitting devices located on a side of the plurality of pixel circuits away from the substrate, the plurality of light-emitting devices being electrically connected to the plurality of first pixel circuits in a one-to-one correspondence; and, a plurality of data signal lines and a plurality of redundant signal lines located in the display area, wherein an extension direction of the data signal lines is the same as an extension direction of the redundant signal lines; Among them, one of the data signal lines is connected to a column of the first pixel circuits; one of the redundant signal lines is located in the area where a column of the virtual pixel circuits is located; at least some of the multiple redundant signal lines are first redundant signal lines, and one of the first redundant signal lines includes a first lead portion connected to one of the data signal lines.

2. The display panel according to claim 1, characterized in that: The display panel further comprises: a plurality of auxiliary signal lines located in the display area, wherein an extension direction of the auxiliary signal lines intersects an extension direction of the redundant signal lines; Among them, one of the auxiliary signal lines is located in the area where a row of pixel circuits is located; at least some of the multiple auxiliary signal lines are first auxiliary signal lines, and one of the first auxiliary signal lines includes: a second lead portion, one end of the second lead portion is electrically connected to one of the data signal lines, and the other end is electrically connected to one end of the first lead portion.

3. The display panel according to claim 2, characterized in that: One of the first redundant signal lines further includes: a redundant line body disconnected from the first lead portion; one of the first auxiliary signal lines further includes: an auxiliary line body disconnected from the second lead portion; Wherein, the redundant line body and the auxiliary line body are electrically connected at the intersection.

4. The display panel according to claim 3, characterized in that: A portion of the plurality of redundant signal lines is the first redundant signal line, another portion of the redundant signal lines is a second redundant signal line, the first lead portion is not provided in the second redundant signal line, and the second redundant signal line is electrically connected to the auxiliary line body at a crossing; And / or, a part of the multiple auxiliary signal lines are the first auxiliary signal lines, and another part of the auxiliary signal lines are second auxiliary signal lines, the second lead part is not set in the second auxiliary signal line, and the second auxiliary signal line is electrically connected to the redundant line body at the intersection.

5. The display panel according to claim 4, characterized in that: In a case where the display panel includes both the second redundant signal line and the second auxiliary signal line, the second redundant signal line is electrically connected to the second auxiliary signal line at a crossing point.

6. The display panel according to claim 4, characterized in that: The display panel further includes: a first power signal line; the second redundant signal line is electrically connected to the first power signal line, and / or the second auxiliary signal line is electrically connected to the first power signal line.

7. The display panel according to claim 6, characterized in that: The light emitting device comprises: an anode, a light emitting layer and a cathode layer which are stacked, wherein the anode is closer to the substrate than the cathode layer; The first pixel circuit is electrically connected to the anode of the corresponding light-emitting device, and the cathode layer is electrically connected to the first power signal line.

8. The display panel according to any one of claims 2 to 7, characterized in that: The display panel also has a non-display area located outside the display area; The display panel further comprises: a plurality of connection leads located in the non-display area and electrically connected to the plurality of data signal lines in a one-to-one correspondence, a portion of the plurality of connection leads being electrically connected to the corresponding data signal lines through the first lead portion and the second lead portion, and another portion of the plurality of connection leads being electrically connected directly to the corresponding data signal lines; Wherein, the plurality of connecting leads are used for binding and connecting with the driving component.

9. The display panel according to any one of claims 2 to 7, characterized in that: The redundant signal line and the data signal line are arranged in the same layer and made of the same material, and the redundant signal line and the auxiliary signal line are arranged in different layers.

10. The display panel according to any one of claims 1 to 7, characterized in that: The display panel further comprises: a gate driving circuit; the light emitting device comprises: an anode, a light emitting layer and a cathode layer which are stacked, the anode being closer to the substrate than the cathode layer; There is an overlapping area between the orthographic projection of the gate driving circuit on the substrate and the orthographic projection of the anode on the substrate.

11. The display panel according to claim 10, characterized in that: The display area includes: a first display partition, a second display partition and a third display partition, wherein the second display partition is located between the first display partition and the third display partition; The plurality of pixel circuits are all located in the first display subarea and the second display area, and are all located outside the third display subarea; at least part of the GOA circuit is located in the third display subarea; Among them, the pixel circuits located in the first display partition include the first pixel circuit and the virtual pixel circuit; the pixel circuits located in the second display partition among the multiple pixel circuits are all the first pixel circuits, and a part of the first pixel circuits located in the second display area is electrically connected to the light-emitting device located in the second display area, and another part of the first pixel circuits located in the second display area is electrically connected to the light-emitting device located in the third display area.

12. The display panel according to claim 11, characterized in that: In the first display partition, a plurality of columns of the first pixel circuits and a plurality of columns of the virtual pixel circuits are arranged alternately.

13. The display panel according to claim 12, characterized in that: N columns of the first pixel circuits are distributed between two adjacent columns of the virtual pixel circuits, where N is an integer greater than or equal to 2 and less than or equal to 6.

14. The display panel according to claim 11, characterized in that: The distribution density of the light emitting devices distributed in the first display partition is equal to the distribution density of the light emitting devices distributed in the second display partition.

15. The display panel according to claim 11, characterized in that: The plurality of columns of the first pixel circuits in the second display subarea are electrically connected to the anodes of the plurality of columns of the light emitting devices in the second display subarea and the third display subarea respectively.

16. The display panel according to claim 15, characterized in that: The display panel further includes: a plurality of transparent connection lines located in the second display area and the third display area; Wherein, the anodes of at least some of the light-emitting devices located in the second display subarea and the third display subarea are electrically connected to the corresponding first pixel circuits through the transparent connecting lines.

17. The display panel according to claim 16, characterized in that: The display panel further comprises: a plurality of auxiliary signal lines, some of the auxiliary signal lines being located in the second display subarea and the third display subarea; The transparent connecting line comprises: a first transparent wiring portion and a second transparent wiring portion connected to each other, wherein the extension direction of the first transparent wiring portion is the same as the extension direction of the auxiliary signal line, and the extension direction of the second transparent wiring portion intersects with the extension direction of the auxiliary signal line; Among them, the orthographic projection of the first transparent wiring portion on the substrate does not overlap with the orthographic projection of the auxiliary signal line on the substrate, and the orthographic projection of the second transparent wiring portion in at least part of the transparent connecting line on the substrate overlaps with the orthographic projection of the auxiliary signal line on the substrate.

18. The display panel according to claim 17, characterized in that: The area where the orthographic projection of at least one of the transparent connecting lines on the substrate overlaps with the orthographic projection of at least one of the auxiliary signal lines on the substrate accounts for less than or equal to 30% of the total area of ​​the orthographic projection of at least one of the transparent connecting lines on the substrate.

19. The display panel according to claim 16, characterized in that: The orthographic projections of anodes of at least some of the light-emitting devices located in the second display subarea and the third display subarea on the substrate overlap with the orthographic projections of at least two of the transparent signal lines on the substrate.

20. A display device, characterized in that: include: A power supply component, and a display panel electrically connected to the power supply component, wherein the display panel is the display panel according to any one of claims 1 to 19.

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