Communication method based on LDPC code, and communication apparatus

Abstract

A communication method based on an LDPC code, and a communication apparatus. By means of row grouping and column grouping, an LDPC base matrix can be divided into a plurality of units having the same size, and the plurality of units comprise three types of units, i.e., a first unit, a second unit and a third unit, wherein the column weight of each column of the first unit is 1, the column weight of at least one column of the second unit is 1 and the column weight of the remaining columns is 0, and the column weight of each column of the third unit is 0. None of the column weights of columns of the first unit, the second unit and the third unit is greater than 1. Therefore, a receiving-end device can perform multi-QC block parallel decoding on a codeword sequence corresponding to each unit, without the occurrence of it being impossible to perform decoding, thereby facilitating an improvement in the decoding performance.

Description

A communication method and communication device based on LDPC code Technical Field

[0001] The present application relates to the field of coding, and more particularly, to a communication method and a communication device based on LDPC codes. Background Art

[0002] In the field of channel coding, low-density parity check (LDPC) code is one of the most mature and widely used channel coding schemes.

[0003] Currently, chips are designed to support decoding of codewords with the maximum boost value, taking into account chip area and resource availability. For example, new radio (NR) supports boost values ​​ranging from 2 to 384, and chips are designed for a maximum boost value of 384. However, in actual decoding, the boost value used may be less than the maximum boost value. In this case, multiple quasi-cyclic (QC) blocks can be used for parallel decoding. However, the randomness of the edge relationships of current LDPC codes can cause parallel decoding of multiple QC blocks to fail, affecting decoding performance.

[0004] Summary of the Invention

[0005] The present application provides a communication method and a communication device based on LDPC codes, which help to improve decoding performance.

[0006] In a first aspect, a communication method based on LDPC codes is provided. The method can be executed by a transmitting device or a module or unit (e.g., a chip) within the transmitting device. For ease of description, the transmitting device is used in the following description. The transmitting device can be a terminal device or a network device.

[0007] The method comprises: obtaining an information bit sequence; performing LDPC encoding on the information bit sequence according to an LDPC base matrix to obtain a first LDPC codeword sequence, wherein the q×(i-1)+1th row to the q×ith row of the first part of the LDPC base matrix include M i Unit 1, F i Unit 2 and G i a third unit, the first part is a matrix region consisting of the 1st column to the xth column of the LDPC base matrix, the first unit is a matrix of q rows and k columns and the column weight of each column is 1, the second unit is a matrix of q rows and k columns, and the column weight of at least one column of the second unit is 1 and the column weight of the remaining columns is 0, the third unit is a matrix of q rows and k columns and the column weight of each column is 0, i and q are positive integers, x and k are integers greater than or equal to 2, Mi is a positive integer, F i and G i is a non-negative integer; based on the first LDPC codeword sequence, a second LDPC codeword sequence is output.

[0008] In the above method, the column weights of the first, second, and third units are all no greater than 1. Therefore, the receiving device can perform parallel decoding of multiple QC blocks for the codeword sequence corresponding to each unit, for example, decoding two QC blocks in parallel. This prevents decoding failures, thus improving decoding performance. Furthermore, only the second unit wastes some hardware resources, thereby improving hardware utilization.

[0009] In combination with the first aspect, in some implementations, outputting a second LDPC codeword sequence based on the first LDPC codeword sequence includes: performing a first interleaving between a portion of the first LDPC codeword sequence corresponding to the information column of the LDPC base matrix and a portion of the first LDPC codeword sequence corresponding to the core check column of the LDPC base matrix to obtain the second LDPC codeword sequence, the first interleaving being performed with a granularity of columns having a lifting value, the number of second units included in the base matrix corresponding to the second LDPC codeword sequence being less than the number of second units included in the base matrix corresponding to the first LDPC codeword sequence; and outputting the second LDPC codeword sequence.

[0010] The first interleaving is performed at the granularity of the number of columns of the lifting value, that is, the first interleaving is performed between QC blocks at the granularity of QC blocks. The interleaving between QC blocks at the granularity of QC blocks can also be referred to as QC block-level interleaving.

[0011] In the above method, the portion of the first LDPC codeword sequence corresponding to the information columns of the LDPC base matrix and the portion of the first LDPC codeword sequence corresponding to the core parity check columns of the LDPC base matrix are interleaved at the granularity of QC blocks, which can reduce the number of second units. Since only using second units would waste some hardware resources, this method can further reduce hardware resource waste. Furthermore, since the interleaving granularity is QC blocks, the complexity is very low.

[0012] In combination with the first aspect or any implementation thereof, in other implementations, when i1 is less than i2, Greater than When i=i1, F i The value of When i=i2, F i The value of .

[0013] Based on the above method, the utilization rate of hardware resources can be improved as much as possible while ensuring the performance of each bit rate is not damaged.

[0014] In combination with the first aspect or any implementation thereof, in other implementations, the value interval of i includes multiple continuous subintervals, and the same subinterval corresponds to the same F i , and F i Decrease by subinterval.

[0015] Based on the above method, on the basis of ensuring high decoding efficiency, the edge density of each code rate corresponding to the LDPC base matrix can meet the edge density evolution requirements, thereby ensuring a better decoding threshold.

[0016] In combination with the first aspect or any implementation thereof, in other implementations, when i is less than a first value, F i Greater than 0; when i is greater than or equal to the first value, F i is 0.

[0017] Based on the above method, as the code rate decreases, the LDPC base matrix can have greater orthogonality and greater design freedom without compromising performance. Based on this, F can be used after the code rate is lower than a certain threshold. i To improve the utilization of hardware resources.

[0018] In combination with the first aspect or any implementation thereof, in other implementations, when i is less than the second value, F i is 2; when i is greater than or equal to the second value and less than the third value, F i is 1; when i is greater than or equal to the third value, F i is 0.

[0019] Based on the above method, for the LDPC base matrix that supports multiple code rate intervals, as the code rate changes, the maximum hardware utilization that can be achieved by the LDPC base matrix with an optimal decoding threshold will also change. Overall, as the code rate decreases, there is more room for optimization. i The values ​​of the segment are 2, 1, and 0, which help to achieve the highest utilization of hardware resources.

[0020] In combination with the first aspect or any implementation thereof, in other implementations, the M i The first unit, the F i The second unit and the G i The third units are included in the non-punctured information columns in the 1st column to the xth column of the LDPC base matrix; or, the M i The first unit, the F i The second unit and the G iThe third unit is included in the information columns from the 1st column to the xth column of the LDPC base matrix; or, the M i The first unit, the F i The second unit and the G i The third units are included in non-punctured columns from the 1st column to the xth column of the LDPC base matrix.

[0021] M i Unit 1, F i Unit 2 and G i The third element consists of the non-punctured information columns from columns 1 to x of the LDPC base matrix. This can be understood as restricting only the non-punctured information columns of the LDPC base matrix. Because the punctured information columns are highly correlated with the decoding threshold, the design of the punctured information columns generally prioritizes ensuring the decoding threshold. This design, focusing solely on the non-punctured information columns of the LDPC base matrix, can improve hardware resource utilization while ensuring the decoding threshold.

[0022] M i Unit 1, F i Unit 2 and G i The third unit contains the information columns from columns 1 to x of the LDPC base matrix, which can be understood as restricting all information columns of the LDPC base matrix. The combined design of punctured and non-punctured information columns provides more combinations and helps improve hardware resource utilization.

[0023] M i Unit 1, F i Unit 2 and G i The third unit is included in the non-punctured columns from columns 1 to x of the LDPC base matrix, which can be understood as a restriction on the non-punctured information columns and non-punctured core parity check columns of the LDPC base matrix. Jointly designing the non-punctured information columns and non-punctured core parity check columns of the LDPC base matrix can provide more combinations. Although the core parity check columns have a coding structure that does not strictly achieve very high hardware utilization, they can be combined with other information columns to help form a grouping structure with higher hardware resource utilization.

[0024] In combination with the first aspect or any implementation thereof, in some other implementations, q=1.

[0025] In the above method, q = 1, meaning the first, second, and third units comprise a single row. This makes the present solution applicable to regions of the LDPC base matrix with a high edge density. Furthermore, the first, second, and third units comprised by the LDPC base matrix are of equal size, and the first unit is both row- and column-regular. In this case, the LDPC base matrix has a well-regulated structure, simplifying the hardware decoding architecture.

[0026] In combination with the first aspect or any implementation thereof, in some other implementations, the sum of the offset values ​​of the non-zero elements of the first unit is an integer multiple of the lifting value.

[0027] In LDPC codes, a cycle is composed of interconnected vertices that both start and end at a vertex within this group and only pass through each node once. A node's short cycle is the shortest path among the cycles starting from that node. For example, if a node has cycles of lengths 4, 6, and 8, the short cycle for that variable node is 4. The longer the short cycle of a node, the lower the correlation between the information transmitted from that node and the node itself, and the better the decoding performance. The above method helps to achieve a LDPC base matrix without short cycles of relatively short lengths, such as 4-short cycles and 6-short cycles, which can ensure that the information transmission correlation of the LDPC code is relatively low, thereby improving decoding performance.

[0028] In combination with the first aspect or any implementation thereof, in other implementations, when the bit rate is greater than the first bit rate threshold, F i is 0.

[0029] Based on the above method, as the code rate decreases, the LDPC base matrix can have greater orthogonality and greater design freedom without compromising performance. Based on this, F can be used after the code rate is lower than a certain threshold. i To improve the utilization of hardware resources.

[0030] In combination with the first aspect or any implementation thereof, in some other implementations, the first bit rate threshold is any one of the following bit rates: 0.926, or

[0031] The first code rate threshold may be the highest code rate defined in the Modulation and Coding Scheme (MCS) table, such as The first code rate threshold can also be the code rate of the existing base matrix, such as BG1 or In this way, the range of the LDPC base matrix application grouping structure can be adapted to the existing code rate, such as when the code rate is lower than The grouping structure of the embodiment of the present application is applied within the scope of.

[0032] In combination with the first aspect or any implementation thereof, in some other implementations, the columns of the third subpart of the first part include multiple groups, the symmetric difference of the non-zero elements of any two columns in each of the groups is 0 or 1, each of the groups includes at most one second unit, and the third subpart is a matrix area consisting of the 1st row to the uth row and the 1st column to the xth column of the first part, where u is an integer greater than or equal to 1.

[0033] Based on the above method, the utilization rate of hardware resources can be improved while ensuring the optimal decoding threshold.

[0034] In combination with the first aspect or any implementation manner thereof, in some other implementation manners, the LDPC base matrix includes a punctured column; and the group including the punctured column includes the second unit.

[0035] The above method helps to ensure successful decoding of the punctured columns.

[0036] In combination with the first aspect or any implementation thereof, in some other implementations, the LDPC base matrix includes a punctured column; i At most one second unit among the second units includes the perforation column.

[0037] Based on the above method, when the LDPC base matrix has punctured columns, the utilization rate of hardware resources can be improved while ensuring the optimal decoding threshold.

[0038] In combination with the first aspect or any implementation thereof, in some other implementations, the columns of the second sub-part of the first part include multiple groups, the symmetric difference of the non-zero elements of any two columns in each of the groups is 0 or 1, each of the groups includes at most one second unit, and the second sub-part is a matrix area consisting of the 1st row to the uth row and the 1st column to the yth column of the first part, where u is an integer greater than or equal to 1, and y is less than x.

[0039] Based on the above method, the utilization rate of hardware resources can be improved while ensuring the optimal decoding threshold.

[0040] In combination with the first aspect or any implementation manner thereof, in some other implementation manners, a matrix region corresponding to a non-punctured information column of the LDPC base matrix does not include the second unit.

[0041] Based on the above method, the number of second units can be reduced to a small number, which helps to improve the utilization of hardware resources.

[0042] In combination with the first aspect or any implementation thereof, in some other implementations, the first part includes a first sub-part, which is a matrix area consisting of the 1st row to the uth row and the y+1th column to the xth column of the first part, where u is an integer greater than or equal to 1, u-1=xy-1, and y is less than x; the diagonal elements of the first sub-part are all non-zero elements, and the first sub-part includes N blocks, which are square matrices; the N blocks include all diagonal elements of the first sub-part, and the diagonal elements of each block in the N blocks overlap with the diagonal elements of the first sub-part, and the blocks do not overlap; some or all of the N blocks include multiple rows, and the non-zero elements of at least two rows in the multiple rows have a true inclusion relationship.

[0043] Based on the above method, when the core check region has a coding structure, the utilization rate of hardware resources can be improved while ensuring the optimal decoding threshold.

[0044] In combination with the first aspect or any implementation thereof, in some other implementations, the N blocks are composed of N1 first blocks and one second block, the size of the first block is k×k, the size of the second block is k′×k′, N1 is a positive integer, N2 is a non-negative integer, and k′ is less than k.

[0045] In combination with the first aspect or any implementation thereof, in some other implementations, all elements in the first subpart except the N blocks are zero elements.

[0046] Based on the above method, the number of non-zero elements in the first sub-part can be minimized and the hardware complexity can be minimized.

[0047] In combination with the first aspect or any implementation manner thereof, in some other implementation manners, the first portion includes a first subportion, where the first subportion is a matrix region consisting of rows 1 to u and columns y+1 to x of the first portion, where u is an integer greater than or equal to 1, u-1=xy-1, and y is less than x;

[0048] When u-1=xy-1=3, the positions of the zero and non-zero elements of the first sub-part are as shown in any of the following matrices:

[0049] and / or,

[0050] When u-1=xy-1=4, the positions of the zero and non-zero elements of the first sub-part are as shown in any of the following matrices:

[0051] or and / or,

[0052] When u-1=xy-1=5, the positions of the zero and non-zero elements of the first sub-part are as shown in any of the following matrices:

[0053] or

[0054] In each of the above matrices, "1" represents a non-zero element and "0" represents a non-zero element.

[0055] In combination with the first aspect or any implementation thereof, in some other implementations, q=k.

[0056] In combination with the first aspect or any implementation manner thereof, in some other implementation manners, the row weight of each row of the first unit is 1.

[0057] Based on the above method, the first unit, the second unit, and the third unit included in the LDPC base matrix have the same size, and the first unit is row-regular and column-regular. In this case, the LDPC base matrix has a relatively regular structure, and the hardware decoding architecture can be simplified.

[0058] In combination with the first aspect or any implementation thereof, in some other implementations, each of the first units is based on a sequence θ (θ1, θ2, ..., θ a ,…,θ k ), where the ath element θ a Indicates the ath row and the θth row of the first unit a The elements of the column are non-zero elements, and a is an integer greater than 0 and less than or equal to k.

[0059] In the above method, each first unit can be obtained based on a replacement method, and the implementation is simple.

[0060] In combination with the first aspect or any implementation thereof, in other implementations, θ a =a+b(mod k), or, θ a =k+1-a+b(mod k), where b is a constant.

[0061] The above method helps to achieve the absence of short cycles of relatively short length, such as 4 short cycles and 6 short cycles, in the LDPC base matrix, which can ensure that the information transmission correlation of the LDPC code is relatively low, thereby improving the decoding performance.

[0062] In combination with the first aspect or any implementation thereof, in some other implementations, the offset values ​​of the non-zero elements of the first unit are the same; or, the remainders of any two non-zero elements of the first unit relative to the boost value are the same; or, the sum of the offset values ​​of the non-zero elements of the first unit is an integer multiple of the boost value.

[0063] The above method helps to achieve the absence of short cycles of relatively short length, such as 4 short cycles and 6 short cycles, in the LDPC base matrix, which can ensure that the information transmission correlation of the LDPC code is relatively low, thereby improving the decoding performance.

[0064] In combination with the first aspect or any implementation thereof, in other implementations, each of the first units includes K segments, the K segments are divided according to columns, the intersection of any two segments in the K segments is empty, and the union of the K segments is the first unit, K is greater than or equal to 2; the cth segment in the K segments is based on a length of |K c |The sequence θ c The permutation of θ is obtained, where θ c The ath element in Indicates the ath row, the cth row of the cth segment The elements of the column are non-zero elements, |K c | is the number of columns in the cth segment, c is an integer greater than 0 and less than or equal to K, and a is an integer greater than 0 and less than or equal to K c An integer.

[0065] The above method provides a base graph structure that is easy to design hardware quasi-cyclic low density parity check (QC-LDPC) rotation networks.

[0066] In combination with the first aspect or any implementation thereof, in other implementations, or, Among them, b c is the constant corresponding to the c-th segment.

[0067] The above method provides an offset value design scheme corresponding to the segmented permutation mode of the first unit of the LDPC base matrix, and jointly supports QC-LDPC.

[0068] In combination with the first aspect or any implementation thereof, in some other implementations, each of the first units includes K segments, the K segments are divided according to columns, the intersection of any two segments in the K segments is empty, and the union of the K segments is the first unit, K is greater than or equal to 2; the offset values ​​of the non-zero elements of the segments are the same; or, the remainders of any two non-zero elements of the segments relative to the boost value are the same; or, the sum of the offset values ​​of the non-zero elements of the segments is an integer multiple of the boost value.

[0069] The above method helps to avoid short cycles of relatively short length, such as 4 short cycles and 6 short cycles, in the LDPC base matrix, thereby improving the decoding performance of the LDPC code and reducing the error floor.

[0070] In combination with the first aspect or any implementation thereof, in some other implementations, when q=k=2, the positions of the zero elements and non-zero elements of the first unit are as shown in any one of the following matrices: or In the matrix, "1" represents a non-zero element and "0" represents a non-zero element.

[0071] In combination with the first aspect or any implementation thereof, in some other implementations, when q=k=3, the positions of the zero elements and non-zero elements of the first unit are as shown in any one of the following matrices:

[0072] or

[0073] In the matrix, "1" represents a non-zero element and "0" represents a non-zero element.

[0074] In combination with the first aspect or any implementation thereof, in some other implementations, when q=k=4, the positions of the zero elements and non-zero elements of the first unit are as shown in any one of the following matrices:

[0075] or

[0076] In each of the above matrices, "1" represents a non-zero element and "0" represents a non-zero element.

[0077] In combination with the first aspect or any implementation thereof, in some other implementations, the LDPC base matrix is ​​obtained based on an indicator matrix, an element of the indicator matrix corresponds to one of the first unit, the second unit or the third unit, and the value of the element in the indicator matrix is ​​used to indicate the position of the zero element and / or non-zero element in the first unit, the second unit or the third unit corresponding to the element.

[0078] In other words, the LDPC base matrix can be represented by a smaller indicator matrix, which helps reduce the storage content of the device.

[0079] In combination with the first aspect or any implementation thereof, in some other implementations, the row numbers of the rows of the matrix area including the first unit, the second unit, and the third unit are greater than the row numbers of the rows in the matrix area corresponding to the first code rate, and the first code rate is greater than the code rate threshold.

[0080] Because the core matrix of the LDPC base matrix has a high edge density, the applicable grouping structures are generally limited to q = 1. That is, if the first region contains the core matrix, the grouping structures applicable to the first region are generally limited to q = 1. As the row number increases, the edge density of the LDPC base matrix decreases. Therefore, if the grouping structure is only applied within the range where the row number is greater than the row number threshold (such as the extended region), a wider variety of grouping structures can be compatible without being limited to the grouping structure of q = 1, thus providing greater design flexibility.

[0081] In combination with the first aspect or any implementation thereof, in other implementations, F i Related to at least one of the following information: the code rate corresponding to the q×(i-1)+1th row to the q×ith row, the row weight of the q×(i-1)+1th row to the q×ith row, or the position of the zero elements and / or non-zero elements of the q×(i-1)+1th row to the q×ith row of the punctured column of the LDPC basis matrix.

[0082] In combination with the first aspect or any implementation manner thereof, in some other implementation manners, the row weight from the q×(i-1)+1th row to the q×ith row includes at least one of the following information: when the LDPC base matrix includes a punctured column, the row weight from the q×(i-1)+1th row to the q×ith row including the punctured column; when the LDPC base matrix includes a punctured column, the row weight from the q×(i-1)+1th row to the q×ith row not including the punctured column; or, when the LDPC base matrix does not include a punctured column, the row weight from the q×(i-1)+1th row to the q×ith row.

[0083] In a second aspect, a communication method based on LDPC codes is provided. The method can be executed by a receiving device or a module or unit in the receiving device (e.g., a chip). For ease of description, the following description uses the receiving device. The receiving device can be a terminal device or a network device.

[0084] The method includes: receiving a second LDPC codeword sequence; decoding the second LDPC codeword sequence according to an LDPC base matrix, wherein the q×(i-1)+1th row to the q×ith row of the first part of the LDPC base matrix include M i Unit 1, F i Unit 2 and G ia third unit, the first part is a matrix region consisting of the 1st column to the xth column of the LDPC base matrix, the first unit is a matrix of q rows and k columns and the column weight of each column is 1, the second unit is a matrix of q rows and k columns, and the column weight of at least one column of the second unit is 1 and the column weight of the remaining columns is 0, the third unit is a matrix of q rows and k columns and the column weight of each column is 0, i and q are positive integers, x and k are integers greater than or equal to 2, M i is a positive integer, F i and G i A non-negative integer.

[0085] In the above method, the column weights of the first, second, and third units are all no greater than 1. Therefore, the receiving device can perform parallel decoding of multiple QC blocks for the codeword sequence corresponding to each unit, for example, decoding two QC blocks in parallel. This prevents decoding failures, thus improving decoding performance. Furthermore, only the second unit wastes some hardware resources, thereby improving hardware utilization.

[0086] In combination with the second aspect, in some implementations, the decoding of the second LDPC codeword sequence according to the LDPC base matrix includes: performing a first column transformation between the information column and the core check column of the LDPC base matrix, the first column transformation being performed with a granularity of columns having a lifting value, the number of second units included in the LDPC base matrix after the first column transformation being less than the number of second units included in the LDPC base matrix that has not undergone the first column transformation; and decoding the second LDPC codeword sequence according to the LDPC base matrix after the first column transformation.

[0087] The first column transformation is performed at the granularity of the columns corresponding to the number of columns with the same value being lifted. This means that the first column transformation is a column transformation between QC blocks at the granularity of a QC block. This column transformation between QC blocks at the granularity of a QC block can also be referred to as a QC block-level column transformation. This method further reduces hardware resource waste. Furthermore, since the first column transformation is performed at the QC block granularity, its complexity is very low.

[0088] In combination with the second aspect or any implementation thereof, in other implementations, the decoding of the second LDPC codeword sequence according to the LDPC base matrix includes: performing a first deinterleaving on the second LDPC codeword sequence, the first deinterleaving performing deinterleaving with a granularity of columns of the lifting value number to obtain a first LDPC codeword sequence; and decoding the first LDPC codeword sequence according to the LDPC base matrix. The first deinterleaving performs deinterleaving with a granularity of columns of the lifting value number, that is, the first deinterleaving is deinterleaving between QC blocks with a granularity of QC blocks. The deinterleaving between QC blocks with a granularity of QC blocks can also be referred to as QC block-level deinterleaving.

[0089] In combination with the second aspect or any implementation thereof, in some other implementations, decoding the second LDPC codeword sequence according to the LDPC base matrix includes: using the same storage unit and computing unit to parallel decode the elements in the second LDPC codeword sequence corresponding to the first unit, the second unit or the third unit, and the storage unit and the computing unit are the storage unit and the computing unit of a QC block.

[0090] In the above method, the same storage unit and computing unit can be used to decode multiple elements in the first unit, the second unit or the third unit in parallel. There is no need to process one element before processing another element. Therefore, the delay of processing multiple elements is consistent with the delay of processing one element alone, which helps to improve decoding performance.

[0091] The terms or features in the second aspect or its implementation methods that are the same as those in the first aspect or its implementation methods can refer to the first aspect or its implementation methods, and their technical effects can refer to the technical effects in the first aspect or its implementation methods, and will not be repeated in the second aspect.

[0092] In a third aspect, a communication device is provided, configured to execute the method provided by any of the above aspects or implementations thereof. Specifically, the device may include units and / or modules, such as a processing unit and / or a transceiver unit, configured to execute the method provided by any of the above aspects or implementations thereof.

[0093] In one implementation, the apparatus is a transmitting device or a receiving device. When the apparatus is a transmitting device or a receiving device, the transceiver unit may be a transceiver, an input / output interface, or a communication interface; and the processing unit may be at least one processor. Optionally, the transceiver is a transceiver circuit. Optionally, the input / output interface is an input / output circuit.

[0094] In another implementation, the apparatus is a chip, chip system, or circuit used in a transmitting device or a receiving device. When the apparatus is a chip, chip system, or circuit used in a transmitting device or a receiving device, the transceiver unit may be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit; and the processing unit may be at least one processor, processing circuit, or logic circuit.

[0095] In a fourth aspect, a communication device is provided, comprising: a memory for storing programs; and at least one processor for executing computer programs or instructions stored in the memory to perform the method provided by any one of the above aspects or its implementation.

[0096] In one implementation, the apparatus is a transmitting end device or a receiving end device.

[0097] In another implementation, the apparatus is a chip, a chip system, or a circuit used in a transmitting device or a receiving device.

[0098] In a fifth aspect, a communication device is provided, comprising: at least one processor and a communication interface, wherein the at least one processor is configured to retrieve a computer program or instruction stored in a memory through the communication interface to execute the method provided by any of the above aspects or implementations thereof. The communication interface may be implemented in hardware or software.

[0099] In one implementation, the device further includes the memory.

[0100] In a sixth aspect, a processor is provided for executing the methods provided in the above aspects.

[0101] For the operations such as sending and acquiring / receiving involved in the processor, unless otherwise specified, or if they do not conflict with their actual functions or internal logic in the relevant descriptions, they can be understood as operations such as processor output, reception, and input, or as sending and receiving operations performed by the radio frequency circuit and antenna. This application does not limit this.

[0102] In a seventh aspect, a computer-readable storage medium is provided, which stores a program code for execution by a device, wherein the program code includes a method for executing any one of the above aspects or its implementation.

[0103] In an eighth aspect, a computer program product comprising instructions is provided, which, when run on a computer, enables the computer to execute the method provided by any one of the above aspects or its implementation.

[0104] In a ninth aspect, a chip is provided, comprising a processor and a communication interface, wherein the processor reads instructions stored in a memory through the communication interface and executes the method provided by any one of the above aspects or implementations thereof. The communication interface may be implemented in hardware or software.

[0105] Optionally, as an implementation method, the chip also includes a memory, in which a computer program or instruction is stored, and the processor is used to execute the computer program or instruction stored in the memory. When the computer program or instruction is executed, the processor is used to execute the method provided by any of the above aspects or its implementation methods.

[0106] When the method provided in this application is executed by a chip, this application does not limit the number of chips that implement the method. For example, the method can be executed by one chip or by two or more chips. Furthermore, when the number of chips implementing the method of this application is two or more, the chip manufacturers are not limited and can be the same manufacturer or different manufacturers.

[0107] In a tenth aspect, a communication system is provided, comprising at least one of the transmitting device or the receiving device described above.

[0108] In an eleventh aspect, a computer program is provided, which, when executed on a computer, enables the method provided by any one of the above aspects or its implementation to be executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0109] FIG1 is a schematic diagram of a network architecture to which embodiments of the present application can be applied.

[0110] FIG2 is a schematic diagram of an LDPC check matrix H.

[0111] FIG3 is a Tanner graph of an LDPC check matrix H.

[0112] FIG4 is a schematic diagram of the structure of a check matrix.

[0113] FIG. 5 shows an example of a non-column-regularized grouping structure and a column-regularized grouping structure.

[0114] FIG. 6 shows an example of a non-row-regular grouping structure and a row-regular grouping structure.

[0115] FIG7 is a schematic diagram of a matrix using the grouping structure 1 with k=2.

[0116] FIG8 is a schematic diagram of a matrix using the grouping structure 2 with k=2.

[0117] FIG9 is a schematic diagram of the information transmission process.

[0118] FIG10 is a schematic flowchart of a communication method 1000 based on LDPC codes provided in this application.

[0119] FIG11 is a schematic diagram of the hardware decoding architecture corresponding to grouping structure 1 and grouping structure 2.

[0120] FIG12 is a schematic diagram of the coding chain provided by this application.

[0121] FIG13 is a schematic diagram of interleaving of QC blocks between information columns and core check columns.

[0122] FIG. 14 is an example of grouping of core columns.

[0123] FIG15 is a schematic diagram showing how to divide part B into blocks.

[0124] FIG16 is a graph showing the change in the number of non-column regularized grouping structures at different code rates.

[0125] FIG17 is a simulation result of the equivalent number of decoding QC blocks for LDPC codes at different code rates.

[0126] FIG18 shows the simulation results of the signal-noise ratio (SNR) of LDPC codes at different code rates.

[0127] FIG19 is a first simulation result of the signal-to-noise ratio of LDPC codes with different code lengths and different code rates.

[0128] FIG20 is a second simulation result of the signal-to-noise ratio of LDPC codes with different code lengths and different code rates.

[0129] FIG21 is the third simulation result of the signal-to-noise ratio of LDPC codes with different code lengths and different code rates.

[0130] FIG22 is a schematic structural diagram of a device provided in an embodiment of the present application.

[0131] FIG23 is another schematic structural diagram of the device provided in an embodiment of the present application.

[0132] FIG24 is a schematic diagram of a chip system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0133] To facilitate understanding of the embodiments of the present application, the following explanations are made before introducing the embodiments of the present application.

[0134] "For indicating" or "indicating" can include direct indication and indirect indication, or "for indicating" or "indicating" can be explicitly and / or implicitly indicated. The various numerical numbers such as first, second, etc. are only used for the convenience of description and are not used to limit the scope of the embodiments of the present application, such as distinguishing different messages, different information, etc. "Pre-definition" can be implemented by pre-saving corresponding codes, tables or other methods that can be used to indicate relevant information in the device. This application does not limit its specific implementation method. The "protocol" involved may refer to a standard protocol in the communication field, for example, it may include the Long Term Evolution (LTE) protocol, the NR protocol and related protocols used in future communication systems. This application does not limit this. Words such as "exemplary", "for example", "exemplarily", "as (another) example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as an "example" in this application should not be construed as being preferred or advantageous over other embodiments or design schemes. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized. "At least one" means one or more, and "a plurality" means two or more. "At most one" and "at most one" refer to one or zero. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can mean: a, or b, or c, or a and b, or a and c, or b and c, or a, b and c. Where a, b and c can be single or multiple, respectively. Descriptions of network element A sending a message, information, or data to network element B, or network element B receiving a message, information, or data from network element A, are intended to clarify the network element to which the message, information, or data is sent, and do not limit whether the messages, information, or data are sent directly or indirectly through other network elements. Phrases such as "when," "under the circumstances," "if," and "if" all imply that the device will take appropriate action under certain objective circumstances. They do not specify a time limit, do not require the device to perform a judgment action, and do not imply any other limitations.

[0135] In addition, the network architecture and business scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field can know that with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0136] A communication system to which the embodiments of the present application can be applied is described below.

[0137] The embodiments of the present application can be applied to various communication systems, including but not limited to: fifth generation (5G) system or NR system, LTE system, long term evolution-advanced (LTE-A) system, LTE frequency division duplex (FDD) system, LTE time division duplex (TDD) system, etc. It can also be applied to future communication systems, such as the sixth generation mobile communication system. In addition, it can also be applied to device to device (D2D) communication, vehicle-to-everything (V2X) communication, machine to machine (M2M) communication, machine type communication (MTC), and Internet of Things (IoT) communication system or other communication system. In addition, it can also be extended to similar wireless communication systems, such as wireless fidelity (Wi-Fi), global interoperability for microwave access (WIMAX), and third generation partnership project (3GPP) related communication systems, etc., without limitation.

[0138] A communication system applicable to embodiments of the present application may include one or more transmitting devices and one or more receiving devices. Optionally, one of the transmitting device and the receiving device may be a terminal device, and the other may be a network device. Optionally, both the transmitting device and the receiving device may be terminal devices. Optionally, both the transmitting device and the receiving device may be network devices.

[0139] Exemplarily, FIG1 shows a schematic diagram of a network architecture to which an embodiment of the present application may be applied.

[0140] As shown in Figure 1, the embodiments of the present application can be applied to both uplink data transmission and downlink data transmission. Figure 1 only takes uplink data transmission or downlink data transmission between a network device and two terminal devices (such as terminal device 1 and terminal device 2) as an example. In uplink data transmission, the transmitting device in this article is a terminal device, and the receiving device is a network device; conversely, in downlink data transmission, the transmitting device is a network device, and the receiving device is a terminal device. In addition, the applicability of the embodiments of the present application in other communication scenarios is not limited. For example, it can also be applied to sidelink communications.

[0141] The terminal device of the present application may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, drone, wireless communication device, user agent or user device, etc. The terminal device in the embodiments of the present application can refer to a device that provides voice and / or data connectivity to a user, and can be used to connect people, objects and machines, such as a handheld device with wireless connection function, a vehicle-mounted device, etc. The terminal device in the embodiments of the present application can be a mobile phone, a tablet computer, a laptop computer, a PDA, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, etc.

[0142] The network device of the present application may be a device with wireless transceiver functions, and the network device may be a device that provides wireless communication function services, usually located on the network side, including but not limited to the next-generation base station (gNodeB, gNB) in the 5G system, the base station in the sixth-generation mobile communication system, the base station in the future mobile communication system, or the access node in the wireless fidelity (WiFi) system, the evolved node B (eNB) in the long-term evolution (LTE) system, the radio network controller (RNC), the node B (NB), the base station controller (BSC), the home base station (for example, home evolved NodeB, or home Node B, HNB), the base band unit (BBU), the transmission reception point (TRP), the transmitting point (TP), the base transceiver station (BTS), the satellite, the drone, etc. In a network structure, the network device may include a centralized unit (CU) node, or a distributed unit (DU) node, or a RAN device including a CU node and a DU node, or a RAN device including a control plane CU node and a user plane CU node, and a DU node, or the network device may also be a wireless controller, relay station, vehicle-mounted device, and wearable device in a cloud radio access network (CRAN) scenario. In addition, the base station may be a macro base station, a micro base station, a relay node, a donor node, or a combination thereof. The base station may also refer to a communication module, a modem, or a chip for being set in the aforementioned device or apparatus. The base station may also be a mobile switching center and a device that performs the base station function in D2D, V2X, and M2M communications, a network-side device in a 6G network, or a device that performs the base station function in future communication systems. The base station can support networks with the same or different access technologies without limitation.

[0143] Unless otherwise specified, the device used to implement the function of a terminal device or network device in this application may refer to the terminal device or network device itself, or may refer to a device that can support the terminal device or network device to implement the function, such as a chip system or chip, specifically, a system on a chip (SoC) or a modem. The device can be installed in the terminal device or network device. In the embodiments of the present application, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0144] It should also be noted that some embodiments herein use the 5G system as an example to describe specific solution details. It is understood that when this solution is applied to other communication systems, such as the LTE system or future communication systems, the messages, channels, or information in the solution can be replaced with messages, channels, or information in other communication systems that can implement corresponding functions, and this application does not limit this.

[0145] To facilitate understanding of the embodiments of the present application, several concepts or terms involved in the embodiments of the present application are briefly explained. The concepts or terms introduced below are explained based on the concepts or terms specified in the reference protocol, but this does not mean that the embodiments of the present application can only be applied to existing systems. The concepts or terms involved in the embodiments of the present application can be applied to future systems. The specific names of the concepts or terms (for example, concepts or terms involving functional descriptions) can be adjusted as future systems develop.

[0146] 1. LDPC Code

[0147] LDPC codes are linear block codes whose parity check matrices are sparse. The number of zero elements in an LDPC parity check matrix far outnumbers the number of nonzero elements. In other words, the row and column weights of the parity check matrix are very small compared to the LDPC code length. An LDPC code with an information bit sequence length equal to w and a code length equal to v can be uniquely identified by its parity check matrix.

[0148] In 1981, Tanner represented LDPC codewords using a graph, now called a Tanner graph. There is a one-to-one correspondence between a Tanner graph and a parity check matrix. A Tanner graph consists of two types of vertices: one type represents codeword bits, called variable nodes, and the other type is a check node, representing a check constraint. Each check node represents a check constraint. This is explained below using Figures 2 and 3.

[0149] FIG2 is a schematic diagram of an LDPC check matrix H.

[0150] In Figure 2, {V i} represents the variable node (VN) set, {C i} represents the set of check nodes (CN). Each row of the check matrix H represents a check equation, each check equation corresponds to a check node, and each column represents a codeword bit, each codeword bit corresponds to a variable node. In Figure 2, there are eight variable nodes and four check nodes. If a codeword bit is included in the corresponding check equation, a line is connected between the variable node and the check node involved, resulting in a Tanner graph.

[0151] FIG3 is a Tanner graph of an LDPC check matrix H.

[0152] As shown in Figure 3, the Tanner graph represents the LDPC parity check matrix. For example, for a parity check matrix H with g rows and v columns, the Tanner graph contains two types of nodes: v variable nodes and g check nodes. The v variable nodes correspond to the v columns of the parity check matrix H, and the g check nodes correspond to the g rows of the parity check matrix H. A cycle in a Tanner graph consists of interconnected vertices. The cycle has one vertex in this group as both its starting and ending point, and passes through each node only once. The length of a cycle is defined as the number of edges it contains, while the girth of the graph, also known as its size, is defined as the minimum cycle length in the graph. In Figure 3, the girth is 4, as indicated by the black lines. The variable nodes in the Tanner graph correspond to each column of the parity check matrix H, which in turn corresponds to each codeword bit of the LDPC codeword. The check nodes in the Tanner graph correspond to each row of the parity check matrix H, which in turn corresponds to each parity bit of the LDPC codeword. The connections between the two types of nodes correspond to the values ​​of the elements in the H matrix. If there is a connection between the i-th check node and the j-th variable node, the element (i, j) in the H matrix is ​​1. If there is no connection, the corresponding element is 0. The connection between a variable node and a check node can also be called an edge. A connection between a check node and a variable node can also be described as having a connection or edge between the check node and the variable node. The edge relationship between a check node and a variable node can include either the presence of an edge or the absence of an edge.

[0153] In addition, in the Tanner graph, a cycle refers to a closed loop consisting of variable nodes, check nodes, and edges connected end to end.

[0154] As mentioned above, LDPC is a linear block code. It divides the information sequence to be encoded into groups of w bits. The encoder then performs a linear operation on these w information bits to obtain g parity bits. These w information bits and g parity bits are then combined to form a codeword of length v = w + g. The mapping from w information bits to a codeword of length v bits is typically represented by a corresponding parity check matrix H. Based on the parity check matrix H, a codeword sequence is generated to complete the encoding process. After the codeword sequence is transmitted over the channel, the receiving device decodes the received signal and determines the original information bits.

[0155] 2. QC-LDPC code

[0156] QC-LDPC code is a type of structured LDPC code. Due to the unique structure of its check matrix, it can be encoded using a simple feedback shift register, reducing the coding complexity of the LDPC code. When the code length is long, the check matrix H of the LDPC code will be very large, so H is usually represented in blocks: the complete check matrix H is regarded as consisting of multiple Z c ×Z c Specifically, the complete check matrix H can be generated by a base matrix H b Indicates that H b Each element in corresponds to a Z c ×Z c Each submatrix can be represented by the number of cyclic shift bits, thus greatly reducing the storage space required for the complete check matrix H. b The elements in can also be called quasi-cyclic (QC) blocks.

[0157] Based on the basis matrix H b And the improvement value Z c (lifting size), the basis matrix H b Expanded to a complete check matrix for encoding or decoding. c It may also be called expansion factor, lifting factor, expansion value, expansion coefficient, or lifting size, etc.

[0158] For example, the basis matrix H of the QC-LDPC code b As shown below:

[0159] It can be seen that the basis matrix H b The size of the matrix is ​​4 rows and 24 columns, and the basis matrix H b Each element in represents a Z c square matrix of order, element represents the cyclic permutation matrix, i represents the cyclic shift value, and i is an integer. In addition, the basis matrix H b The "-1" in represents an all-zero matrix, and "0" represents an identity matrix.

[0160] For example, As shown below:

[0161] Optionally, the basis matrix H b In addition to "-1", the zero elements in can also be expressed in other forms, such as using "-" or null values ​​to represent an all-zero matrix. The base matrix of the LDPC code can also be called the LDPC base matrix.

[0162] 3. Non-zero elements and zero elements

[0163] In the check matrix, a zero element indicates that there is no connection between the variable node and the check node, and a non-zero element indicates that there is a connection between the variable node and the check node.

[0164] In the LDPC basis matrix, the zero element represents Z c An all-zero square matrix of order, with non-zero elements representing Z c The identity matrix of order or based on Z c The circulant permutation matrix of the identity matrix of order , where the values ​​of the non-zero elements represent the circulant shift values ​​or offset values ​​relative to the identity matrix.

[0165] This application does not limit the specific representation of zero elements and non-zero elements. For example, in the check matrix H shown in Figure 2, "0" is used to represent zero elements and "1" is used to represent non-zero elements. For another example, as described above, the base matrix H b In the , "-1" is used to represent zero elements, and "non-negative values" are used to represent non-zero elements.

[0166] For ease of description, the LDPC base matrix below uses "0" to represent a zero element and "1" to represent a non-zero element.

[0167] 4. Column weight and row weight

[0168] For a column of a matrix, the column weight can refer to the number of non-zero elements contained in the column. For a row of a matrix, the row weight can refer to the number of non-zero elements contained in the row. For example, as shown in Figure 2, the column weight of the first column of the check matrix H is 2, and the row weight of the first row is 4. For another example, as described above, the base matrix H b The first column has a column weight of 4 and the first row has a row weight of 20.

[0169] 5. Structure of the check matrix

[0170] FIG4 is a schematic diagram of the structure of a check matrix.

[0171] As shown in Figure 4(a), the check matrix may include a high rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high rate region may include part A and part B as shown in Figure 4(b), where part A corresponds to information bits (or information bits, systematic bits, etc.), and part B is a square matrix corresponding to core check bits (or core check bits). The all-zero region may correspond to part C of Figure 4(b), which is an all-zero matrix. The incremental redundancy region may correspond to part D of Figure 4(b). The raptor-like region may correspond to part E of Figure 4(b), which may be a unit matrix corresponding to the check bits of the low rate extension.

[0172] The parity check matrix of the LDPC code shown in Figure 4 employs a "raptor-like" structure, allowing it to be gradually extended to lower code rates using a high-rate core matrix. In practice, as shown in Figure 4(a), the first X rows and Y columns of the parity check matrix can be truncated. As the code rate decreases, X and Y gradually increase, and the area of ​​the matrix used also gradually expands.

[0173] It should be noted that the check matrix can be represented by the LDPC base matrix, so the structure of the LDPC base matrix is ​​similar to that of the check matrix, which will not be described in detail here.

[0174] 6. Core Matrix, Core Row, Core Column, Core Section, and Expansion Area

[0175] Core row: This is the row corresponding to the core parity bit. In other words, the core row is the row corresponding to the high bit rate area.

[0176] Core columns: This includes all information columns and all core check columns. In other words, core columns are the columns corresponding to the high bitrate area, or the columns corresponding to part A + part B.

[0177] Kernel Matrix: This is the portion of the LDPC parity check matrix or LDPC base matrix consisting of all core rows and all core columns. In other words, the core matrix is ​​the high-rate region of the LDPC parity check matrix or LDPC base matrix, or the portion consisting of Part A and Part B.

[0178] The core portion is composed of all rows and core columns of the LDPC parity check matrix or LDPC base matrix. In other words, the core portion is the area consisting of the high-rate region and the Laptrinhel-like region, or the area consisting of parts A, B, and D, or the area corresponding to non-Laptrinhel-like nodes.

[0179] Extension area: may also be called extension matrix or extension part, which may correspond to the incremental redundancy area or D part mentioned above.

[0180] 7. Punch column

[0181] A punctured column in an LDPC code may refer to a column that is not transmitted. A punctured column may be an information column or a check column. In this application, an information column to be punctured is referred to as a punctured information column, and a check column to be punctured is referred to as a punctured check column.

[0182] In addition, columns in an LDPC code that are not punctured can also be referred to as non-punctured columns. Similarly, non-punctured columns can be either information columns or parity columns. In this application, non-punctured information columns are referred to as non-punctured information columns, and non-punctured parity columns are referred to as non-punctured parity columns.

[0183] 8. Column Grouping

[0184] Column grouping: refers to grouping the columns of a matrix according to more than one column as a basic unit. For example, let the core column set be C, and the core column set C is divided into t subsets C1~C t . Where C1∪…∪C t = C and the intersection of any two subsets in t subsets is empty, that is,

[0185] Uniform column grouping: means that each subset of t subsets contains the same number of columns. Taking uniform k-column grouping as an example, for any subset C in t subsets i Yes | C i |=k.

[0186] Non-uniform column grouping: refers to the existence of at least two subsets among the t subsets, and the number of columns included in these two subsets is different.

[0187] 9. Row Grouping

[0188] Row grouping: refers to grouping the rows of a matrix into units with a row count greater than or equal to 1. For example, let the row set of the matrix be R, and the row set R is divided into s subsets R1~R s . Where R1∪…∪R s = R and the intersection of any two subsets in the s subsets is empty, that is,

[0189] Uniform row grouping: means that each subset of s subsets contains the same number of rows. Taking uniform q-row grouping as an example, for any subset R in s subsets i , with |R i |=q.

[0190] Non-uniform row grouping: refers to the existence of at least two subsets among the s subsets, and the number of rows included in these two subsets is different.

[0191] 10. Group structure and basic group structure

[0192] Grouping structure: It can also be called grouping unit or row and column partition set. j , row set R i Satisfies the condition: For any column c∈C j , we have |e(c,R i )|∈{0,1}, then it is called R i Contains lines and C j The structure of the included columns is a grouping structure, where e(c,R i ) represents the column c and row set R i The edge set of the included rows, |e(c,R i )| represents the column c and row set R i The number of edges between the included rows. The column weight of each column in the grouping structure is less than or equal to 1.

[0193] Basic grouping structure: If any If established, then it is called R i Contains lines and C j The structure of the included columns is a basic grouping structure.

[0194] In this application, uniform k-column grouping and q-row grouping are taken as examples for explanation. In this case, the scale of the grouping structure is consistent, and the number of edges included in the grouping structure is less than or equal to k.

[0195] 11. Column regular grouping structure

[0196] For the column set C j and row set R i , if it satisfies any c1,c2∈C j There is |e(c1,R i )|=|e(c2,R i )|∈{0,1}, then C j and R i is the column regular grouping structure, |e(c1,R i )| represents the column c1 and row set R iThe number of edges of the included rows, |e(c2,R i )| represents the column c2 and row set R i The number of edges between the included rows. In other words, the column weights of each column in the column-regular grouping structure are the same, either all 0 or all 1.

[0197] If for all j=1,2,…,t and i=1,2,…,q, we have C j and R i is a column-regular grouping structure, then the grouping structure of the matrix is ​​said to be column-regular.

[0198] Figure 5 shows an example of a non-column-regularized grouping structure and a column-regularized grouping structure. In the grouping structure shown in Figure 5(a), the column weight of the first column is 1, the column weight of the second column is 0, and the column weight of the third column is 1. The column weights of the columns included in the grouping mechanism are different, so this grouping structure is a non-column-regularized grouping structure. In the grouping structure shown in Figure 5(b), the column weight of each column is 1, so this grouping structure is a column-regularized grouping structure.

[0199] 12. Row regular grouping structure

[0200] For the column set C j and row set R i , if it satisfies any r1,r2∈R i , there is |e(r1,C j )|=|e(r2,C j )|, then C j and R i is the row-regular grouping structure, |e(r1,C j )| represents the row r1 and column set C j The number of edges of the included rows, |e(r2,C j )| represents the row r2 and column set C j The number of edges in the included rows. In other words, the row weight of each row in the row-regular grouping structure is the same, either 0 or a value greater than or equal to 1.

[0201] If for all j=1,2,…,t and i=1,2,…,q, we have C j and R i is a row-regular grouping structure, then the grouping structure of the matrix is ​​said to be row-regular.

[0202] Figure 6 shows an example of a non-row-regularized grouping structure and a row-regularized grouping structure. In the grouping structure shown in Figure 6(a), the column weight of the first row is 2, and the column weight of the second column is 1. The rows included in the grouping mechanism have different weights, so this grouping structure is a non-row-regularized grouping structure. In the grouping structure shown in Figure 6(b), the column weight of each row is 1, so this grouping structure is a non-row-regularized grouping structure. In the grouping structure shown in Figure 6(c), only one row is included, so this grouping structure is a row-regularized grouping structure.

[0203] 13. Row- and column-regular grouping structure

[0204] If the grouping structure is row-regular and column-regular, the column weight of each column of the grouping structure is 0 or 1. Correspondingly, the row weight of each row of the grouping structure is 0 or k / q, and q is divisible by k.

[0205] Two row-regular and column-regular grouping structures are given below.

[0206] 1) Grouping structure 1: q = k, with regular rows and regular columns

[0207] The grouping structure 1 is a square matrix. The column weight of each column of the grouping structure 1 is 1, and the row weight of each row is also 1.

[0208] A possible implementation is: q=k=2, 3, 4.

[0209] Figure 7 is a schematic diagram of a matrix using grouping structure 1 with k = 2. As shown in Figure 7, the 8×26 matrix is ​​divided into 4×13 2×2 grouping structures, each of which is row-regular and column-regular.

[0210] 2) Grouping structure 2: q = 1, row-regular and column-regular grouping structure

[0211] The grouping structure 2 includes only one row, and each column of the grouping structure 2 has a column weight of 1 and a row weight of k.

[0212] A possible implementation is k=2, 3, or 4.

[0213] Figure 8 is a schematic diagram of a matrix using grouping structure 2 with k=2. As shown in Figure 8, the 8×26 matrix is ​​divided into 8×13 1×2 grouping structures, each of which is row-regular and column-regular. The edges within each grouping structure are exactly the same, that is, for any row r, |N(r)∩C i |∈{0, k} holds. The row weight of the matrix is ​​k×U, where U is the number of grouping structures with column weight 1 included in each row.

[0214] Usually the core matrix of the LDPC base matrix can only support grouping structure 2.

[0215] 14. Information transmission process

[0216] Figure 9 is a schematic diagram of the information transmission process. As shown in Figure 9, information is sent by the source, undergoes source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, source recovery and other processing, and arrives at the destination, completing the transmission of information from the source to the destination. Among them, the processing shown in the upper layer of Figure 9 (including source coding, channel coding and modulation, etc.) is performed at the transmitting end device, and the processing shown in the lower layer (including demodulation, channel decoding, source recovery, etc.) is performed at the receiving end device. The embodiments of the present application mainly relate to source coding, channel coding, channel decoding and source recovery shown in Figure 9.

[0217] Currently, due to considerations of chip area and resource availability, the mainstream decoding architecture uses QC block parallel decoding. Chips are designed to support decoding of codewords with the maximum boost value. For example, NR supports a boost value range of 2-384, and the chip is designed for a maximum boost value of 384. However, in actual decoding, the boost value used may be less than the maximum boost value. In this case, chip hardware resources (such as storage or computing resources) become idle, resulting in hardware resource waste. Alternatively, when current hardware resources are greater than twice the boost value used, or in high-throughput scenarios, multiple QC block parallel decoding can be used. However, the edge relationships of current LDPC codes are highly random. Even if using multiple QC block parallel decoding (for example, decoding two QC blocks in parallel) doubles the decoding parallelism and hardware resource usage, the actual throughput cannot be doubled.

[0218] To address the above problems, the present application provides a communication method and a communication device based on LDPC codes, which can improve decoding performance.

[0219] The method embodiments of the present application are described below with reference to the accompanying drawings.

[0220] FIG10 is a schematic flowchart of a communication method 1000 based on LDPC codes provided in this application.

[0221] Method 1000 can be performed by a transmitting device and a receiving device. Unless otherwise specified, "transmitting device" or "receiving device" can refer to the transmitting device or receiving device itself, or can refer to a device that supports the transmitting device or receiving device to implement the function. For convenience of description, the following description uniformly uses the transmitting device and receiving device. The transmitting device can be a terminal device or a network device, and the receiving device can be a terminal device or a network device.

[0222] Method 1000 may include at least part of the following.

[0223] Step 1001: A transmitting device obtains an information bit sequence.

[0224] That is, if the transmitting device needs to communicate with the receiving device, that is, the transmitting device needs to send a signal to the receiving device, the transmitting device needs to first obtain the information bit sequence corresponding to the signal to be sent to the receiving device.

[0225] The transmitting end device obtaining the information bit sequence may refer to: the transmitting end device performing source coding on source symbols to generate the information bit sequence. The transmitting end device obtaining the information bit sequence may also refer to: the transmitting end device receiving the information bit sequence from other communication devices.

[0226] Step 1002: The transmitting end device performs LDPC encoding on the information bit sequence according to the LDPC base matrix to obtain a first LDPC codeword sequence.

[0227] The first part of the LDPC matrix includes the q×(i-1)+1th row to the q×ith row. i Unit 1, F i Unit 2 and G i The first part is the matrix area composed of the 1st column to the xth column of the LDPC matrix, M i is a positive integer, F i and G i is a non-negative integer, and x is an integer greater than or equal to 2. The "unit" here may be the grouping structure mentioned in the term explanation section. For ease of understanding, the unit, the first unit, the second unit, and the third unit are hereinafter referred to as the grouping structure, the first grouping structure, the second grouping structure, and the third grouping structure, respectively.

[0228] The first grouping structure, the second grouping structure, and the third grouping structure are all matrices with q rows and k columns, and the column weight of each column of the q-row, k-column matrix is ​​not greater than 1. Specifically, the column weight of each column of the first grouping structure is 1, that is, the first grouping structure is a column-regular grouping structure with a column weight of 1; the column weight of at least one column of the second grouping structure is 1, and the column weights of the remaining columns are 0. Since the column weights of the columns in the second grouping structure are not the same, the second grouping structure is a non-column-regular grouping structure; the column weight of each column of the third grouping structure is 0, that is, the third grouping structure is a column-regular grouping structure with a column weight of 0, that is, the third grouping structure is a matrix with q rows and k columns composed of all 0s.

[0229] In the embodiment of the present application, as the value of i is different, M i 、F i and G i The values ​​of may be the same or different, without limitation. In one possible implementation, Fi is less than or equal to the threshold V i A non-negative integer, V i is a non-negative integer. i is less than or equal to the threshold V i The non-negative integer of can be understood as that the number of non-column regular grouping structures included in the q×(i-1)+1th row to the q×ith row of the first part of the LDPC basis matrix is ​​less than a certain number.

[0230] In addition, as the value of i changes, M i 、F i and G i The sum of may be the same or different, without limitation. One possible implementation is, M i 、F i and G i The sum is always M. In other words, each q rows of the first part of the LDPC base matrix include M group structures of size q×k, or in other words, each q rows of the first part of the LDPC base matrix is ​​divided into M group structures of size q×k.

[0231] When F i When it is not 0, the q×(i-1)+1th row to the q×ith row include non-column regular grouping structures. In other words, the grouping structures included in the q×(i-1)+1th row to the q×ith row have both column regular grouping structures and non-column regular grouping structures. i2 When it is 0, the q×(i-1)+1th row to the q×ith row do not include non-column regular grouping structures. In other words, the grouping structures included in the q×(i-1)+1th row to the q×ith row are all column regular grouping structures.

[0232] It should be noted that the structure and characteristics of the LDPC base matrix mentioned in the embodiments of the present application may be that the LDPC base matrix itself has these structures and characteristics, or that the LDPC base matrix has these characteristics after row transformation and / or column change. There is no limitation. For the sake of convenience of description, the embodiments of the present application are described using the LDPC base matrix as an example.

[0233] The structure and characteristics of the LDPC base matrix of the embodiment of the present application will be described in more detail below.

[0234] In step 1003 , the transmitting device sends a second LDPC codeword sequence to the receiving device based on the first LDPC codeword sequence. In other words, the receiving device receives the second LDPC codeword sequence from the transmitting device.

[0235] Step 1004: The receiving end device decodes the second LDPC codeword sequence according to the LDPC base matrix.

[0236] It should be noted that, since the second LDPC codeword sequence may introduce channel noise signals during transmission, the second LDPC codeword sequence output or sent by the transmitting device may be different from the second LDPC codeword sequence received by the receiving device.

[0237] The LDPC base matrices used by the receiving device and the transmitting device can be the same or different, without limitation. For example, both the transmitting device and the receiving device use an LDPC base matrix with a grouped structure. For another example, the transmitting device uses an LDPC base matrix with a grouped structure after row transformation and / or column transformation to encode the information bit sequence, and the receiving device uses the LDPC base matrix that itself has a grouped structure to decode the received second LDPC codeword sequence. The characteristics of the LDPC base matrix used by the receiving device can be referred to in step 1003 and will not be described in detail.

[0238] Since the column weights of the columns of the first grouping structure, the second grouping structure, and the third grouping structure are all no greater than 1, the receiving device can perform parallel decoding of multiple QC blocks on the portion of the second LDPC codeword sequence corresponding to the grouping structure. In other words, the receiving device can perform parallel decoding on the codeword sequence corresponding to each grouping structure.

[0239] In one possible implementation, the receiving device uses the same storage unit and computing unit to perform parallel decoding of multiple QC blocks on the elements in the second LDPC codeword sequence corresponding to the first grouping structure, the second grouping structure, or the third grouping structure, where the storage unit and computing unit refer to the storage unit and computing unit of a QC block.

[0240] Taking the minimum-sum (MS) decoding algorithm as an example, the hardware decoding architectures corresponding to grouping structures 1 and 2 when k = 2 are respectively shown to illustrate that both grouping structures can perform parallel decoding under a decoding architecture with k QC blocks in parallel. Grouping structures 1 and 2 can be referred to in the descriptions of Figures 7 and 8 above.

[0241] FIG11 is a schematic diagram of the hardware decoding architecture corresponding to grouping structure 1 and grouping structure 2.

[0242] Figure 11(a) is a schematic diagram of the hardware decoding architecture corresponding to grouping structure 1. As shown in Figure 11(a), variable nodes are stored according to subsets grouped by columns, meaning that two variable nodes within a subset are stored in the same storage unit (or memory area); check nodes are stored according to subsets grouped by rows, meaning that two check nodes within a subset are stored in the same storage unit. The two variable nodes are read into the computational unit simultaneously, where the computation is performed simultaneously and the corresponding values ​​of the two variable nodes are temporarily stored (such as the addition unit, subtraction unit, and min unit in Figure 11). Thus, using grouping structure 1, two variable nodes can be processed simultaneously, with the operation time slots of the two variable nodes being completely consistent. There is no need to wait until one variable node is processed before processing the other. Therefore, the latency of processing two variable nodes is consistent with the latency of processing a single variable node.

[0243] FIG11( b ) is a schematic diagram of the hardware decoding architecture corresponding to grouping structure 2 . Unlike grouping structure 1 , this decoding architecture processes one check node at a time.

[0244] As can be seen from the hardware decoding architecture, using the same size for grouping structures is more conducive to hardware implementation. If the grouping structures use different sizes, the hardware decoding architecture needs to be designed according to the largest grouping structure, including support for the number of variable nodes, the number of check nodes, and parallelism. In this case, for grouping structures smaller than the maximum size, hardware waste will occur. If the grouping structures use the same size, such as q×k, the hardware decoding architecture can be designed according to the q×k scale. The hardware decoding architecture designed according to the q×k scale supports decoding of q rows and k columns, and its decoding parallelism is also fixed (at most k). The grouping structures included in the LDPC base matrix use the same size, which can also be described as uniform.

[0245] If the grouping structure included in the LDPC base matrix is ​​uniform and column-regular, the parallelism of the decoding is always k, and hardware resources (such as parallelism resources) are not wasted. For example, the first grouping structure among the M grouping structures mentioned above has a decoding parallelism of k, which does not waste hardware resources.

[0246] If the grouping structure included in the LDPC base matrix is ​​uniform and non-column-regular, some hardware resources will be wasted. The wasted resources correspond to the number of columns with column weight 0 in the non-column-regular grouping structure. For example, in the second grouping structure among the M grouping structures described above, the parallelism of decoding is the number of columns with column weight 1 in the second grouping structure. The columns with column weight 0 will cause hardware resource waste, so the second grouping structure will waste some hardware resources.

[0247] If the grouping structure included in the LDPC base matrix is ​​uniform, row-regular, and column-regular, then the grouping structure included in the LDPC base matrix has a regular structure, such as grouping structure 1 and grouping structure 2. In this case, the hardware decoding architecture can be further simplified, and there will be no waste of parallel resources, computing resources, etc.

[0248] Of course, the LDPC base matrix of the embodiment of the present application can also adopt a non-uniform grouping structure. The use of a non-uniform grouping structure helps to match the edge density of the LDPC base matrix and maintain the parallelism of computing resources, but it will increase the complexity of the design of the hardware decoding architecture.

[0249] From the above content, it can be seen that the first grouping structure and the third grouping structure will not cause waste of hardware resources, but the second grouping structure will cause waste of some hardware resources.

[0250] In method 1000, the column weights of the columns in the first, second, and third grouping structures are all no greater than 1. Therefore, the receiving device can decode the codeword sequences corresponding to each grouping structure in parallel, preventing decoding failures and improving decoding performance. Furthermore, only the second grouping structure wastes some hardware resources, thereby improving hardware utilization.

[0251] In addition, when the number of the second grouping structures from the q×(i-1)+1th row to the q×ith row of the first part of the LDPC base matrix is ​​limited to be less than or equal to the threshold value V i When , it can be achieved that the number of second grouping structures included in the q×(i-1)+1th row to the q×ith row of the first part of the LDPC base matrix is ​​less than a certain number, that is, the number of non-column regular grouping structures included in the LDPC base matrix can be limited, thereby further improving the utilization of hardware resources.

[0252] The embodiments of the present application do not limit the implementation manner in which the transmitting device sends the second LDPC codeword sequence based on the first LDPC codeword sequence.

[0253] In one possible implementation, the first LDPC codeword sequence is identical to the second LDPC codeword sequence, that is, the transmitting device sends the LDPC codeword sequence obtained in step 1002 to the receiving device.

[0254] In another possible implementation, the transmitting device performs a first interleaving between the portion of the information column corresponding to the LDPC base matrix in the first LDPC codeword sequence and the portion of the core check column corresponding to the LDPC base matrix in the first LDPC codeword sequence to obtain a second LDPC codeword sequence; the transmitting device sends the second LDPC codeword sequence to the receiving device. The first interleaving is performed with the columns of the lifting value as the granularity, and the number of second grouping structures included in the base matrix corresponding to the second LDPC codeword sequence is less than the number of second grouping structures included in the base matrix corresponding to the first LDPC codeword sequence. The first interleaving is performed with the columns of the lifting value as the granularity, that is, the first interleaving is the interleaving between QC blocks with the QC block as the granularity. The interleaving between QC blocks with the QC block as the granularity can also be referred to as QC block-level interleaving.

[0255] With respect to the above implementation, the receiving device decodes the second LDPC codeword sequence according to the LDPC base matrix, which may include: the receiving device performs a first column transformation on the information column and the core check column of the LDPC base matrix, and uses the LDPC base matrix after the first column transformation to decode the second LDPC codeword sequence, wherein the first column transformation is performed with a granularity of columns equal to the number of lifting values, the number of second grouping structures included in the LDPC base matrix after the first column transformation is less than the number of second grouping structures included in the LDPC base matrix that has not undergone the first column transformation, and the first column transformation performed by the receiving device corresponds to the first interleaving performed by the transmitting device. In other words, the receiving device does not deinterleave the second LDPC codeword sequence, but instead performs a column transformation on the LDPC base matrix corresponding to the interleaving between QC blocks performed by the transmitting device, and uses the column-transformed LDPC base matrix to decode the second LDPC codeword sequence. The first column transformation is performed with a granularity of columns equal to the number of lifting values, that is, the first column transformation is a column transformation between QC blocks performed with a granularity of QC blocks.

[0256] The receiving device decodes the second LDPC codeword sequence according to the LDPC base matrix, and can also include: the receiving device performs a first deinterleaving on the second LDPC codeword sequence to obtain a first LDPC codeword sequence, and decodes the first LDPC codeword sequence according to the LDPC base matrix, wherein the number of second grouping structures included in the base matrix corresponding to the first LDPC codeword sequence is less than the number of second grouping structures included in the base matrix corresponding to the second LDPC codeword sequence, and the first deinterleaving performed by the receiving device corresponds to the interleaving between QC blocks performed by the transmitting device. The first deinterleaving is performed with the column granularity of the number of lifting values, that is, the first deinterleaving is the deinterleaving between QC blocks performed with the QC block as the granularity.

[0257] It should be noted that the embodiments of the present application do not limit the application scenarios of the interleaving between the above-mentioned QC blocks. For example, the interleaving between the above-mentioned QC blocks can be applied in certain specific scenarios, such as in high-throughput scenarios where the code rate is usually high and the code length is usually not long (below 2048), and part or all of the core matrix of the LDPC base matrix can be used for encoding and decoding. Therefore, the interleaving between the above-mentioned QC blocks can be applied.

[0258] When the transmitting device performs the above-mentioned interleaving between QC blocks, the transmitting device can optionally send indication information to the receiving device to instruct the receiving device to perform column transformation between corresponding QC blocks on the LDPC base matrix or to perform deinterleaving between corresponding QC blocks on the second LDPC codeword sequence.

[0259] The interleaving between QC blocks performed by the transmitting device is described in detail below.

[0260] Since the number of information columns of the LDPC base matrix may not be divisible by the column grouping scale k, and the core check column of the LDPC base matrix needs to have an easily encoded matrix structure, the LDPC base matrix will inevitably have many non-column regular grouping structures, resulting in a waste of hardware resources. In an embodiment of the present application, the interleaving content between the above-mentioned QC blocks is the core column, and the purpose is to interleave the information column and the core check column in the core column. By interleaving the information column and the core check column between the QC blocks, the number of second grouping structures (or non-column regular grouping structures) can be reduced, thereby further reducing the waste of hardware resources. Moreover, since the granularity of the interleaving is the QC block, the complexity is very low.

[0261] To achieve the interleaving between the above-mentioned QC blocks, the encoding chain of the transmitting device may have a QC block-level interleaver, which is different from the interleaver used for quadrature amplitude modulation (QAM) or fading. The embodiments of the present application do not limit the position of the QC block-level interleaver in the encoding chain. For example, as shown in Figure 12, the QC block-level interleaver may be before the sending circular buffer. For another example, the QC block-level interleaver may be after the sending circular buffer and before reading from the sending circular buffer for transmission.

[0262] A possible implementation method is that the principle of interleaving between the above-mentioned QC blocks is: the codeword sequence corresponding to the information column of the LDPC base matrix and the codeword sequence corresponding to the core check column of the LDPC base matrix are interleaved between the QC blocks with the QC block as the granularity, so that the symmetric difference of the rows included in any two columns in the subset of each column group of the LDPC base matrix corresponding to the interleaved codeword sequence is less than or equal to 1. The rows included in a column may refer to the rows having an edge connected to the column. The symmetric difference of the rows included in the two columns can also be replaced by the symmetric difference of the positions of the non-zero elements of the two columns or the symmetric difference of the non-zero elements of the two columns. The symmetric difference of the rows included in the two columns can be understood as the number of rows obtained by subtracting the intersection of the rows included in the two columns from the union of the rows included in the two columns.

[0263] FIG13 is a schematic diagram of interleaving the information column and the core check column between QC blocks.

[0264] Figure 13 uses grouping structure 2 with k = 2 as an example. The bold black boxes in the figure represent non-column-regular grouping structures. As shown in Figure 13, before interleaving, the rows included in columns 7 and 8 are {1, 2, 3} and {1, 3, 4}, respectively; the rows included in columns 17 and 18 are {1, 2, 4} and {2, 3, 4}, respectively; and the rows included in columns 25 and 26 are {2, 3} and {3, 4}, respectively. The symmetric difference of each row is 2, and the matrix includes 8 non-column-regular grouping structures. After interleaving, the maximum symmetric difference between the rows included in the two columns in each subset of the column grouping is 1, and the matrix includes 4 non-column-regular grouping structures.

[0265] It should be noted that the interleaving between the QC blocks described above can be implemented in conjunction with the LDPC base matrix in step 1002 as described above, or can be implemented separately as an independent embodiment. When the interleaving between the QC blocks is implemented separately, the LDPC base matrix used for encoding in this application may not have the grouping structure described in step 1002, but after interleaving between the QC blocks, it can have the grouping structure described in step 1002. The base matrix corresponding to the LDPC codeword sequence after interleaving between the QC blocks can have the same grouping structure as the LDPC base matrix in step 1002.

[0266] The structure and characteristics of the LDPC base matrix of the embodiment of the present application are described in detail below.

[0267] As described above, the first part of the LDPC base matrix of the embodiment of the present application has a grouping structure. It should be noted that the embodiment of the present application does not limit the area in the LDPC base matrix where the grouping structure is applied.

[0268] In one possible implementation, the grouping structure is applied to the entire core portion of the LDPC base matrix. For a description of the core portion, see the Glossary section. If the first region is the core portion of the LDPC base matrix, then columns 1 through x of the LDPC base matrix are all core columns of the LDPC base matrix. In other words, the first region is a matrix region consisting of all rows and all core columns of the LDPC base matrix.

[0269] In this case, the LDPC base matrix with a grouping structure can be represented by a smaller indicator matrix J. In other words, the LDPC base matrix can be obtained according to the indicator matrix J, where an element of the indicator matrix J corresponds to one of the first grouping structure, the second grouping structure or the third grouping structure, and the value of the element in the indicator matrix J is used to indicate the position of the zero element and / or non-zero element in the first grouping structure, the second grouping structure or the third grouping structure corresponding to the element.

[0270] If the LDPC base matrix is ​​divided into s×t group structures, the LDPC base matrix can be represented by an indicator matrix J with s rows and t columns, where s is the number of subsets of row groupings and t is the number of subsets of column groupings.

[0271] Exemplarily, if the i-th row and j-th column of the indicator matrix J is 0, it means that the position of the LDPC base matrix is ​​a grouping structure of size q×k, and the grouping structure is a zero matrix; if the i-th row and j-th column of the indicator matrix J is 1, it means that the position of the LDPC base matrix is ​​a grouping structure of size q×k, and the number of edges contained in the grouping structure is not 0, or the grouping structure is a basic grouping structure.

[0272] In one embodiment, the storage of the LDPC base matrix can be to store an indicator matrix J, and at the same time indicate the edge relationship of the grouping structure corresponding to the position where the indicator matrix J takes a value of 1, or the position of the zero element and / or non-zero element in the grouping structure. Exemplarily, based on the type of basic grouping structure, a numerical value can be stored at each position where the indicator matrix J takes a value of 1, and the numerical value is used to indicate the type of basic grouping structure at that position. Taking the matrix shown in Figure 7 as an example, the matrix includes two types of basic grouping structures. The type of the first grouping structure of the matrix shown in Figure 7 is the first type, and the type of the second grouping structure is the second type. If 0 is used to represent the zero matrix, the numerical value 1 is used to represent the first type of basic grouping structure, and 2 is used to represent the second type of basic grouping structure, then the matrix shown in Figure 7 can be represented by the following indicator matrix J:

[0273] In another manner, the storage of the LDPC base matrix may also be to store the LDPC base matrix without using the indicator matrix J to represent that the LDPC base matrix has a clear grouping structure.

[0274] In another possible implementation, the grouping structure may be applied to a certain range of the core part of the LDPC base matrix.

[0275] As an example, the grouping structure may be applied within the range of the n1th column to the n2th column and the m1th row to the m2th row of the LDPC base matrix.

[0276] As another example, the grouping structure can be applied within a range where the number of rows of the LDPC base matrix is ​​greater than a row number threshold, that is, the row numbers of the rows of the matrix region including the first grouping structure, the second grouping structure, and the third grouping structure in the LDPC base matrix are all greater than the row number threshold. Since the edge density of the core matrix is ​​very large, the grouping structure that can be applied generally needs to be limited to q=1, that is, if the matrix region including the first grouping structure, the second grouping structure, and the third grouping structure contains the core matrix, the grouping structure that can be applied generally needs to be limited to q=1. As the row number increases, the edge density of the LDPC base matrix decreases. Therefore, if the grouping structure is only applied within a range where the row number is greater than the row number threshold (such as an extended area), it can be compatible with more types of grouping structures without being limited to the grouping structure of q=1, thus having more flexible design freedom.

[0277] As another example, the grouping structure can be applied within a range where the number of rows in the LDPC base matrix is ​​greater than a first row number threshold and less than a second row number threshold. That is, the row numbers of the rows in the first region of the LDPC base matrix are all greater than the first row number threshold and less than the second row number threshold. This design also offers greater design flexibility.

[0278] As another example, the grouping structure can be applied within a range where the code rate is greater than the second code rate threshold, that is, the row numbers of the rows of the matrix region in the LDPC base matrix including the first grouping structure, the second grouping structure, and the third grouping structure are all greater than the row numbers of the rows in the matrix region corresponding to the first code rate, where the first code rate is greater than the second code rate threshold.

[0279] In the embodiment of the present application, the number F of the second grouping structures (i.e., non-column regular grouping structures) included in the q×(i-1)+1th row to the q×ith row of the first region of the LDPC base matrix is i There is no restriction on the settings.

[0280] A possible implementation, F i Related to at least one of the following information: the code rate corresponding to the q×(i-1)+1th row to the q×ith row, the row weight of the q×(i-1)+1th row to the q×ith row, or the edge relationship between the q×(i-1)+1th row to the q×ith row of the punctured column of the LDPC basis matrix.

[0281] For example, from a holistic perspective, Fi will decrease as the bit rate decreases. In one approach, F i It can be segmented down with the bit rate. For example, when the bit rate is greater than or equal to the first bit rate threshold, F i Greater than 0, when the bit rate is greater than the first bit rate threshold F i is 0.

[0282] For example, from a holistic perspective, F i will decrease as the row weight decreases. In one approach, for example, F i It can be decreased in stages according to the row weight. For example, when the row weight is less than or equal to the row weight threshold, F i Greater than 0, when the row weight is greater than the row weight threshold F i is 0.

[0283] For example, F i It can decrease with the bit rate, piecewise, and is inversely proportional to the number of non-zero elements except the punctured columns.

[0284] For example, F i It can decrease in sections with the bit rate and is proportional to the number of zero elements except the punctured columns.

[0285] Among them, the row weights from the q×(i-1)+1th row to the q×ith row include at least one of the following information: when the LDPC base matrix includes a punctured column, the row weights from the q×(i-1)+1th row to the q×ith row including the punctured column; when the LDPC base matrix includes a punctured column, the row weights from the q×(i-1)+1th row to the q×ith row not including the punctured column; or, when the LDPC base matrix does not include a punctured column, the row weights from the q×(i-1)+1th row to the q×ith row.

[0286] Among them, taking the LDPC base matrix including punctured columns 1 and 2, q=1 as an example, the edge relationship from the q×(i-1)+1th row to the q×ith row of the punctured column of the LDPC base matrix is ​​explained. The edge relationship can be: the row has edges with both punctured columns 1 and 2, the row has an edge with punctured column 1 and has no edge with punctured column 2, the row has no edge with punctured column 1 and has an edge with punctured column 2, and the row has no edge with both punctured columns 1 and 2.

[0287] Another possible implementation method is that in the embodiment of the present application, as i increases, F i Can gradually become smaller. For example, when i1 is smaller than i2, Greater than When i=i1, F i The value of When i=i2, F i The value of .

[0288] As an example, as i increases F i Decreasing can mean that the value interval of i includes multiple continuous subintervals, and the same subinterval corresponds to the same F i , and F i In other words, the number of non-column regular grouping structures is segmented as i changes, and the number of non-column regular grouping structures decreases segment by segment. Optionally, each segment corresponds to the same number of non-column regular grouping structures. If multiple consecutive subintervals are numbered, then F i According to the sub-interval decrease, it can be understood that the sub-interval number is from small to large F i Decreasing.

[0289] For example, when i is less than the first value (i.e., subinterval 1), F i Greater than 0; when i is greater than or equal to the first value (i.e., subinterval 2), F i In other words, it can be designed that the number of non-column regular grouping structures is 0 after i exceeds the first value.

[0290] For another example, when i is less than the second value (i.e., subinterval 1), F i is 2; when i is greater than or equal to the second value and less than the third value (i.e., subinterval 2), F i is 1; when i is greater than or equal to the third value (i.e., subinterval 3), F i is 0.

[0291] In the embodiment of the present application, q=1 can be set (corresponding to the grouping structure 2 above), or q=k can be set (corresponding to the grouping structure 1 above). The LDPC base matrix designs in these two cases are described below.

[0292] Case 1: q=1, that is, the grouping structure includes one row.

[0293] In this case, there are many ways to design the LDPC base matrix, which are not limited.

[0294] In a first possible implementation, the first part includes a third subpart, where the third subpart is a matrix region consisting of rows 1 to u and columns 1 to x of the first part, where u is an integer greater than or equal to 1. Exemplarily, the third subpart is a core matrix of the LDPC base matrix, where columns of the core matrix can belong to multiple groups, where the symmetric difference between rows included in any two columns in each group is 0 or 1, and each group includes at most one second grouping structure (i.e., a non-column-regular grouping structure).

[0295] The grouping mentioned here can refer to the grouping obtained by classifying the core columns according to the "included rows". Since the core matrix has a small number of rows, the core columns can be classified by the rows included in the columns. The rows included in a column can refer to the rows that have edges connected to the column. For example, let the row set corresponding to the core matrix be γ = {r1, r2, ..., r X}, the set of rows contained in each core column is δ, The core columns are classified according to the δ of each core column to obtain a plurality of groups, wherein the symmetric difference of the rows included in any two columns in each group is less than or equal to 1. Optionally, the δ of the rows in each group satisfies |δ|=X or |δ|=X-1, where |δ| represents the number of rows in the row set δ and X is the number of rows included in the core matrix.

[0296] Figure 14 shows an example of grouping core columns. Taking k = 2 as an example, after column transformation, the 26 core columns can be grouped into groups 1 through 5. Group 1 includes columns 1 and 2, group 2 includes columns 1 through 7 and the 24th column, group 3 includes columns 12 through 17 and the 23rd column, group 4 includes columns 8 through 12 and the 26th column, and group 5 includes columns 18 through 22 and the 25th column. Groups 1, 2, 4, and 5 all include a non-column-regular grouping structure, while group 3 does not.

[0297] The method of classifying core columns according to “included rows” can be applied to an LDPC base matrix including punctured columns or to an LDPC base matrix not including punctured columns, without limitation.

[0298] When the LDPC base matrix includes a punctured column, the core matrix must include a non-column-regular grouping structure. In one possible implementation, the grouping containing the punctured column must include a non-column-regular grouping structure. Optionally, at most one second grouping structure among the F2 second grouping structures included in the q×(i-1)+1th row to the q×ith row of the first part of the LDPC base matrix includes a punctured column. When the LDPC base matrix can be represented by an indicator matrix J, at most one second grouping structure among the F2 second grouping structures included in the q×(i-1)+1th row to the q×ith row of the first part of the LDPC base matrix includes a punctured column, which can also be described as each row of the indicator matrix J corresponding to at most one non-column-regular grouping structure containing a punctured column. The matrix area corresponding to the non-punctured information column of the LDPC base matrix does not include a second grouping structure.

[0299] In addition, when the core matrix includes a non-column-regular grouping structure, the matrix range to which the grouping structure can be applied is the entire core matrix, that is, the non-column-regular grouping structure is compatible with the matrix region consisting of core check columns and core rows.

[0300] When the LDPC base matrix does not include a punctured column, the core matrix may include a non-column-regular grouping structure or may not include a non-column-regular grouping structure, without limitation.

[0301] In a second possible implementation, the first part includes a second subpart and a first subpart. The second subpart is a matrix region consisting of the 1st row to the uth row and the 1st column to the yth column of the first part, and the first subpart is a matrix region consisting of the 1st row to the uth row and the y+1th column to the xth column of the first part, where u is an integer greater than or equal to 1, u-1=xy-1, and y is less than x. Exemplarily, the second subpart is a matrix region consisting of all core rows of the LDPC base matrix and all information columns of the LDPC base matrix, i.e., part A, and the first subpart is a matrix region consisting of all core rows of the LDPC base matrix and all core check columns of the LDPC base matrix, i.e., part B.

[0302] The columns of the second sub-portion belong to multiple groups, and the symmetric difference between the rows included in any two columns in each group is 0 or 1. Each group includes at most one non-column-regular grouping structure, or the second sub-portion does not include any non-column-regular grouping structure, wherein the matrix region corresponding to the non-punctured information column does not include the second grouping structure. The method for obtaining multiple groups can be referred to the first possible implementation method and will not be further described.

[0303] The diagonal elements of the first sub-part are all non-zero elements, and the first sub-part includes N blocks, and the N blocks include all diagonal elements of the first sub-part. Each block in the N blocks is a square matrix, and the diagonal elements of each block overlap with the diagonal elements of the first sub-part, and the blocks do not overlap. Some or all of the N blocks include multiple rows, and the non-zero elements of at least two rows in the multiple rows included in the blocks have a true inclusion relationship. The two rows having a true inclusion relationship can be understood as the columns included in one of the two rows are truly included in the columns included in the other column in the two rows. The columns included in a row can refer to the columns that have edges with the row. For example, row #1 includes column #1, column #2 and column #3, and row #2 includes column #2 and column #3, then row #2 is truly included in row #1.

[0304] In a possible implementation, the N blocks consist of N1 first blocks and one second block, wherein the size of the first block is k×k, the size of the second block is k'×k', N1 is a positive integer, N2 is a non-negative integer, and k' is less than k.

[0305] In one possible implementation, the elements in the first sub-portion other than the N blocks may include non-zero elements or may all be zero elements. When the elements in the first sub-portion other than the N blocks are all zero elements, the non-zero elements in the first sub-portion are minimized, which helps reduce hardware complexity.

[0306] The design of the first sub - part (i.e., Part B) will be described in detail below.

[0307] The B part of the LDPC base matrix is the core check area and is a square matrix. Let the B part be a square matrix of X×X, where X is the number of core rows, that is, u - 1 = x - y - 1 = X. The design principle of the B part of the matrix is: it is easy to encode by solving equations and the base matrix is full - rank. Since X may not divide the scale k of the column grouping, the column grouping may be a non - uniform column grouping. If the column grouping of the B part is a non - uniform column grouping, then at most one subset of the column groupings corresponding to the B part includes a number of columns less than k, that is, the column groupings of the B part are C1, C2, …, Cr, where |C i | = k for i < r, |C r | = k', k' ≤ k.

[0308] First, partition the B part. For i, j < r, the range of the block (i, j) is the matrix area formed by the (i - 1)*k + 1 to i*k rows and the (j - 1)*k + 1 to j*k columns; for i = r, j < r, the range of the block (i, j) is the matrix area formed by the (r - 1)*k + 1 to X rows and the (j - 1)*k + 1 to j*k columns; for i < r, j = r, the range of the block (i, j) is the matrix area formed by the (i - 1)*k + 1 to i*k rows and the (r - 1)*k + 1 to X columns; for i = r, j = r, the range of the block (i, j) is the matrix area formed by the (r - 1)*k + 1 to X rows and the (r - 1)*k + 1 to X columns.

[0309] Then, classify the partitioned blocks to obtain two types of blocks. The first type is the blocks with i = j, and the second type is all the remaining blocks. The N blocks in the above - mentioned third matrix refer to the first - type blocks.

[0310] Among them, the first - type blocks contain all the diagonal elements of the B part. The grouping structure included in the first - type blocks must be a non - all - zero grouping structure (or basic grouping structure). If the LDPC base matrix is represented by the indicator matrix J, then the positions in the indicator matrix J corresponding to the first - type blocks must be non - zero elements. Exemplarily, let the rows included in the block L in the first - type blocks be divided into R1, R2, …, R f , then there is for x = 1, …, f. If the grouping structure 2 is adopted, then |R x | = q = 1, and the block L contains k grouping structures (for i < r, the block L includes k rows) or k' grouping structures (for i = r, the block L includes k' rows).

[0311] The grouping structure included in the second type of blocks can be an all-zero grouping structure or a non-all-zero grouping structure. If the LDPC base matrix is ​​represented by an indicator matrix J, the position in the indicator matrix J corresponding to the second type of blocks may contain a zero element. In one possible implementation, the grouping structure included in the second type of blocks is entirely an all-zero grouping structure, that is, there are no edges within the area of ​​the second type of blocks, and all edges are within the first type of blocks. In this case, the number of non-zero elements in part B is minimized, and the hardware complexity is minimized.

[0312] FIG15 is a schematic diagram showing how to divide part B into blocks.

[0313] The bold black frame in Figure 15 represents a block. Blocks that include both black and gray blocks are classified as first-class blocks, while blocks that include white blocks are classified as second-class blocks. Black blocks have edges, gray blocks may have edges, and white blocks do not.

[0314] Figure 15(a) is a schematic diagram of the blocks included in part B when k = 2 and X = 3. In this case, the first type of blocks in part B includes one 2×2 block and one 1×1 block, and the second type of blocks includes one 1×2 block and one 2×1 block. Figure 15(b) is a schematic diagram of the blocks included in part B when k = 2 and X = 4. In this case, the first type of blocks in part B includes two 2×2 blocks, and the second type of blocks includes two 2×2 blocks. Figure 15(c) is a schematic diagram of the blocks included in part B when k = 2 and X = 5. In this case, the first type of blocks in part B includes two 2×2 blocks and one 1×1 block, and the second type of blocks includes two 2×2 blocks, two 2×1 blocks, and two 1×2 blocks. Figure 15(d) is a schematic diagram of the blocks included in part B when k = 2 and X = 6. In this case, the first type of blocks in part B includes three 2×2 blocks, and the second type of blocks includes six 2×2 blocks. Figure 15(e) is a schematic diagram of the blocks included in part B when k = 3 and X = 6. In this case, the first type of blocks in part B includes two 3×3 blocks, and the second type of blocks includes two 3×3 blocks.

[0315] After the position of the above-mentioned blocks is determined, the position of the non-all-zero grouping structure has been determined. The following describes more detailed features of the non-all-zero grouping structure.

[0316] Since the first type of block contains all the diagonal elements of part B, there must be a non-column regular grouping structure among the k or k' non-zero grouping structures (when q = 1) included in each first type of block, and the non-zero elements (or edges) of at least two rows in the multiple rows included in the block have a true inclusion relationship. For example, let the row corresponding to the non-column regular grouping structure be R1. If there is a column regular grouping structure, let the row corresponding to the column regular grouping structure be R2, then e(R1,C i ) is truly contained in e(R2,C i ); even if there is no column-regular grouping structure, the above true inclusion relation is guaranteed to exist. The advantage of not requiring a column-regular grouping structure in the blocks is that the degree distribution is more flexible and the design space is larger.

[0317] In one possible implementation, each block with i=j=1,…,r-1 has both column-regularized and non-column-regularized grouping structures. Depending on the size of the blocks, the block with i=j=r may have only non-column-regularized grouping structures, only column-regularized grouping structures, or both. If the number of rows in the block with i=j=r is greater than 1, then the non-zero elements (or edges) in at least two of the multiple rows of the block have a true inclusion relationship.

[0318] The advantage of the above implementation of Part B is that it is easy to encode, and the core check equation can be accumulated to solve the equation to achieve the encoding effect. In addition, the structure of Part B will not be a double diagonal structure. The encoding process of Part B based on the embodiment of the present application can be performed based on the block structure, that is, each block i=j is performed sequentially or in parallel, i=j=1,2,…,r.

[0319] Several examples of Part B are given below.

[0320] When u-1=xy-1=X=3, k=2, the positions of the zero and non-zero elements in part B are as shown in any of the following matrices:

[0321] or

[0322] When u-1=xy-1=X=3, k=3, the positions of the zero and non-zero elements of part B are shown in the following matrix:

[0323] When u-1=xy-1=X=4, k=2, the positions of the zero and non-zero elements in part B are as shown in any of the following matrices:

[0324] or

[0325] When u-1=xy-1=X=4, k=3, the positions of the zero and non-zero elements in part B are as shown in any of the following matrices:

[0326] or

[0327] When u-1=xy-1=X=5, k=2, the positions of the zero and non-zero elements of part B can be shown in the following matrix:

[0328] When u-1=xy-1=X=5, k=3, the positions of the zero and non-zero elements of part B can be shown in the following matrix:

[0329] When u-1=xy-1=X=5 and k=4, the positions of the zero and non-zero elements of part B can be shown in the following matrix:

[0330] When u-1=xy-1=X=5, k=5, the positions of the zero and non-zero elements of part B can be shown in the following matrix:

[0331] When u-1=xy-1=X=6, k=2, the positions of the zero and non-zero elements of part B can be shown in the following matrix:

[0332] When u-1=xy-1=X=6, k=3, the positions of the zero and non-zero elements of part B can be shown in the following matrix:

[0333] It should be noted that the examples in Part B above are only for ease of understanding and are not intended to be limiting.

[0334] The above describes the design of the core matrix of the LDPC base matrix in Case 1. In some possible implementations, the first part further includes a fourth sub-part, which can be an extended matrix of the LDPC base matrix. The design of the extended matrix is ​​described below.

[0335] The number of non-column-regular grouping structures included in the extended matrix is ​​less than the number of non-column-regular grouping structures included in the core matrix, and the number of non-column-regular grouping structures gradually decreases as the bit rate decreases.

[0336] FIG16 is a graph showing the change in the number of non-column regularized grouping structures at different code rates.

[0337] As the row number i of the indicator matrix J increases, the code rate will gradually decrease. As i increases, the row weight of the indicator matrix J shows an overall downward trend, and the number of non-column-regular grouping structures also shows a downward trend. Among them, the number of non-column-regular grouping structures (i.e., the second grouping structure) corresponding to each i can refer to the number of non-column-regular grouping structures included in the q×(i-1)+1th row to the q×ith row of the non-punctured information column in the 1st to the xth column of the LDPC base matrix, or the number of non-column-regular grouping structures included in the q×(i-1)+1th row to the q×ith row of the information column in the 1st to the xth column of the LDPC base matrix, or the number of non-column-regular grouping structures included in the q×(i-1)+1th row to the q×ith row of the non-punctured column in the 1st to the xth column of the LDPC base matrix.

[0338] The number of non-column regular grouping structures in the extended region changes with the row number i of the indicator matrix J as shown in the previous F i The relationship with i will not be elaborated here.

[0339] In a possible implementation, the sum of the offset values ​​of the non-zero elements of the first grouping structure in case 1 is an integer multiple of the lifting value.

[0340] In a possible implementation, in case 1, when the code rate is greater than the first code rate threshold, F i 0. For example, the first code rate threshold is any one of the following code rates: 0.926, or

[0341] Case 2: q=k, that is, the grouping structure is a square matrix, and the number of rows and columns included is greater than or equal to 2.

[0342] In case 2, if the grouping structure is both column-regular and row-regular (each row of the grouping structure has weight 1 and each column has weight 1), i.e., the first grouping structure, each grouping structure can be considered to be generated through "lifting," and the lifting method is not limited to quasi-cyclic lifting. Two methods for constructing grouping structures in case 2 are given below.

[0343] Method 1: The above “boost” can be obtained by a sequence of length k θ (θ1, θ2, …, θ a ,…,θ k ), in other words, each column-regular and row-regular grouping structure can be represented by a sequence of length k θ (θ1, θ2, ..., θ a ,…,θ k ) is obtained by permutation. Among them, the a-th element θ a Indicates the a-th row and the θ-th row of the grouping structure aThe column has an edge (or the element at this position is a non-zero element), and a is an integer greater than 0 and less than or equal to k.

[0344] The embodiments of this application do not limit a The construction method.

[0345] One possible implementation, θ a =a+b(mod k), or, θ a =k+1-a+b(mod k), where b is a constant.

[0346] The embodiments of the present application do not limit the manner of setting the offset values ​​of the non-zero elements in the first grouping structure.

[0347] In one possible implementation, the offset values ​​of all non-zero elements of the first grouping structure are the same.

[0348] In another possible implementation, any two non-zero elements of the first grouping structure have the same remainder with respect to the promoted value.

[0349] In another possible implementation, the sum of the offset values ​​of all non-zero elements of the first grouping structure is an integer multiple of the lifting value.

[0350] The substitution in method 1 is θ(θ1,θ2,…,θ a ,…,θ k )The whole is cyclically replaced.

[0351] Method 2: Each column-regular and row-regular grouping structure can include K segments, and the K segments are divided according to columns. The intersection of any two segments in the K segments is empty, and the union of the K segments is the grouping structure, K is greater than or equal to 2; the cth segment in the K segments is based on the length |K c |The sequence θ c The permutation of θ is obtained, where θ c The ath element in Indicates the ath row and the cth row of the cth segment. The elements of the column are non-zero elements, |K c | is the number of columns in the cth segment, c is an integer greater than 0 and less than or equal to K, a is an integer greater than 0 and less than or equal to K c An integer.

[0352] The embodiments of this application do not limit The construction method.

[0353] One possible implementation is or, Among them, b c is the constant corresponding to the cth segment.

[0354] The embodiments of the present application do not limit the manner of setting the offset values ​​of the non-zero elements in each segment.

[0355] In one possible implementation, the offset values ​​of all non-zero elements in the c-th segment are the same.

[0356] In another possible implementation, any two non-zero elements of the c-th segment have the same remainder with respect to the promoted value.

[0357] In another possible implementation, the sum of the offset values ​​of all non-zero elements in the c-th segment is an integer multiple of the lifting value.

[0358] The permutation in mode 2 is a permutation in which each segment is a cycle but the whole may not be a cycle.

[0359] Several examples of the first grouping structure are given below.

[0360] When q=k=2, the positions of the zero and non-zero elements of the first grouping structure are as shown in any of the following matrices:

[0361] or

[0362] When q=k=3, the positions of the zero and non-zero elements of the first grouping structure are as shown in any of the following matrices:

[0363] or

[0364] When q=k=4, the positions of the zero and non-zero elements of the first grouping structure are as shown in any of the following matrices:

[0365] or

[0366] It should be noted that the above examples of the first grouping structure are only for ease of understanding and are not intended to be limiting.

[0367] Several examples of the second grouping structure are given below.

[0368] When q=k=2, the positions of the zero and non-zero elements of the second grouping structure are as shown in any of the following matrices:

[0369] or

[0370] When q=k=3, the positions of the zero and non-zero elements of the first grouping structure are shown in any of the following matrices:

[0371] or

[0372] When q=k=4, the positions of the zero and non-zero elements of the second grouping structure are as shown in any of the following matrices:

[0373] or

[0374] It should be noted that the above examples of the second grouping structure are only for ease of understanding and are not intended to be limiting.

[0375] The performance of the LDPC code of the embodiment of the present application is described below in conjunction with simulation results.

[0376] FIG17 is a simulation result of the equivalent number of decoding QC blocks for LDPC codes at different code rates.

[0377] The number of equivalent decoding QC blocks can reflect decoding performance in terms of complexity and latency. Figure 17 shows the simulation results of the equivalent number of decoding QC blocks at different code rates for an NR LDPC code using base graph 1 (BG1) and an LDPC code using grouping structure 2 (i.e., the LDPC code of this application), when the number of QC blocks in parallel decoding is 1 and 2 (i.e., the degree of parallelism is 1 and 2).

[0378] As shown in Figure 17, when the number of QC blocks for parallel decoding is 1, the equivalent number of QC blocks for decoding at all code rates for the NR LDPC code using BG1 and the LDPC code using grouping structure 2 is essentially the same (slightly lower at low code rates). In other words, when the degree of parallelism is 1, the introduction of column grouping structure 2 does not increase decoding complexity or cause latency loss. When the number of QC blocks for parallel decoding is 1, the equivalent number of QC blocks for decoding at all code rates for the LDPC code using grouping structure 2 decreases compared to the NR LDPC code using BG1. In other words, when the degree of parallelism is 2, the introduction of column grouping structure 2 can reduce decoding complexity and decoding latency.

[0379] FIG18 is a simulation result of the SNR of LDPC codes at different code rates.

[0380] The signal-to-noise ratio (SNR) can reflect the ultimate performance of decoding. Figure 18 shows the simulation results of the SNR of NR LDPC codes using BG1 and LDPC codes using grouping structure 2 at different code rates.

[0381] As shown in Figure 18, the signal-to-noise ratios of the NR LDPC code using BG1 and the LDPC code using grouping structure 2 are basically the same at all code rates. In other words, the introduction of column grouping structure 2 does not affect the decoding performance.

[0382] FIG19 is a first simulation result of the signal-to-noise ratio of LDPC codes with different code lengths and different code rates.

[0383] Figure 19 shows the simulation results of the signal-to-noise ratio (SNR) of the NR LDPC code and the LDPC code using grouping structure 2 at different code lengths (i.e., information lengths), different code rates, and 20 rounds of aligned decoding iterations. In Figure 19, the solid line represents the simulation results of the NR LDPC code, and the dashed line represents the simulation results of the LDPC code using grouping structure 2. As shown in Figure 19, at code rates of 5 / 6, 2 / 3, 1 / 2, and 1 / 3, the SNR of the NR LDPC code and the LDPC code using grouping structure 2 are essentially the same at various code lengths. In other words, the introduction of column grouping structure 2 does not compromise decoding performance.

[0384] FIG20 is a second simulation result of the signal-to-noise ratio of LDPC codes with different code lengths and different code rates.

[0385] Figure 20 shows the simulation results of the signal-to-noise ratio (SNR) of NR LDPC codes and LDPC codes using grouping structure 2 at different code lengths, code rates, and a uniform decoding delay (or complexity) of 20 NR iterations. In Figure 20, the solid line represents the simulation results for NR LDPC codes, and the dashed line represents the simulation results for LDPC codes using grouping structure 2. As shown in Figure 20, compared with NR LDPC codes, the performance gain of uniform decoding delay for LDPC codes using grouping structure 2 is approximately 0.1xdB at all code rates except high code rates.

[0386] FIG21 is the third simulation result of the signal-to-noise ratio of LDPC codes with different code lengths and different code rates.

[0387] Figure 21 shows the simulation results of the signal-to-noise ratio (SNR) of NR LDPC codes and LDPC codes using grouping structure 2 at different code lengths, code rates, and a uniform decoding delay (or complexity) of 4 NR iterations. In Figure 21, the solid line represents the simulation results for NR LDPC codes, and the dotted line represents the simulation results for LDPC codes using grouping structure 2. As shown in Figure 21, compared with NR LDPC codes, the performance gain of uniform decoding delay for LDPC codes using grouping structure 2 is approximately 0.3xdB at all code rates except high code rates.

[0388] It should be noted that the above embodiments all apply a grouping structure of one scale to the LDPC base matrix. In fact, the LDPC base matrix can apply grouping structures of various scales. For example, the grouping structure 2 described above can be applied to the core matrix of the LDPC base matrix, and the grouping structure 1 described above can be applied to the extended area of ​​the LDPC base matrix, without limitation.

[0389] The above describes in detail the method embodiment provided by the present application in combination with Figures 1 to 21. The following will describe the device embodiment of the present application in combination with Figures 22 to 24.

[0390] It is understood that, in order to implement the functions in the above embodiments, the apparatuses in Figures 22 to 24 include hardware structures and / or software modules corresponding to the functions. Those skilled in the art should readily appreciate that, in conjunction with the various exemplary units and method steps described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software.

[0391] Figures 22 and 23 are schematic diagrams of possible apparatuses provided in embodiments of the present application. These apparatuses can be used to implement the functions of the transmitting device or the receiving device in the above method embodiments, thereby also achieving the beneficial effects of the above method embodiments.

[0392] As shown in FIG. 22 , the device 10 includes a transceiver unit 11 and a processing unit 12 .

[0393] When apparatus 10 is used to implement the functions of the transmitting device in FIG. 10 , transceiver unit 11 is used to execute the transmitting and receiving steps of the transmitting device, such as step 1003, and processing unit 12 is used to execute the processing steps of the transmitting device, such as steps 1001 and 1002. When apparatus 10 is used to implement the functions of the receiving device in FIG. 10 , transceiver unit 11 is used to execute the transmitting and receiving steps of the receiving device, such as step 1003, and processing unit 12 is used to execute the processing steps of the receiving device, such as step 1004.

[0394] For a more detailed description of the transceiver unit 11 and the processing unit 12 , please refer to the relevant description in the above method embodiment, which will not be described again here.

[0395] As shown in FIG23 , the apparatus 20 includes a processor 21. The processor 21 is coupled to a memory 23, which is used to store instructions. When the apparatus 20 is used to implement the method described above, the processor 21 is used to execute the instructions in the memory 23 to implement the functions of the processing unit 12 described above.

[0396] Optionally, the device 20 further includes a memory 23 .

[0397] Optionally, the apparatus 20 further includes an interface circuit 22. The processor 21 and the interface circuit 22 are coupled to each other. It will be appreciated that the interface circuit 22 may be a transceiver or an input / output interface. When the apparatus 20 is used to implement the method described above, the processor 21 is configured to execute instructions to implement the functions of the processing unit 12, and the interface circuit 22 is configured to implement the functions of the transceiver unit 11.

[0398] Exemplarily, when apparatus 20 is a chip applied to a transmitting device or a receiving device, the chip implements the functions of the transmitting device or the receiving device in the above-described method embodiments. The chip receives information from other modules (such as a radio frequency module or an antenna) in the transmitting device or the receiving device, where the information is sent to the transmitting device or the receiving device by other devices; or the chip sends information to other modules (such as a radio frequency module or an antenna) in the transmitting device or the receiving device, where the information is sent to other devices by the transmitting device or the receiving device.

[0399] 24 is a schematic diagram of a chip system 30 provided in an embodiment of the present application. The chip system 30 (or also referred to as a processing system) includes a logic circuit 31 and an input / output interface 32.

[0400] The logic circuit 31 may be a processing circuit in the chip system 30. The logic circuit 31 may be coupled to a storage unit and call instructions in the storage unit so that the chip system 30 can implement the methods and functions of the various embodiments of the present application. The input / output interface 32 may be an input / output circuit in the chip system 30, outputting information processed by the chip system 30 or inputting data or signaling information to be processed into the chip system 30 for processing.

[0401] As a solution, the chip system 30 is used to implement the operations performed by the transmitting end device or the receiving end device in each of the above method embodiments.

[0402] For example, the logic circuit 31 is used to implement the processing-related operations performed by the sending device or the receiving device in the above method embodiment; the input / output interface 32 is used to implement the sending and / or receiving-related operations performed by the sending device or the receiving device in the above method embodiment.

[0403] The present application also provides a communication device, comprising a processor coupled to a memory, the memory being configured to store computer programs or instructions and / or data, the processor being configured to execute the computer programs or instructions stored in the memory, or to read data stored in the memory, to perform the methods described in the above method embodiments. Optionally, there are one or more processors. Optionally, the communication device includes a memory. Optionally, there are one or more memories. Optionally, the memory is integrated with the processor or provided separately.

[0404] The present application also provides a chip, including a processor, which is coupled to a memory, the memory is used to store computer programs or instructions, and the processor is used to execute the computer programs or instructions stored in the memory to implement the methods performed by the sending device or the receiving device in the above-mentioned method embodiments.

[0405] The present application also provides a computer-readable storage medium storing computer instructions for implementing the methods executed by a transmitting device or a receiving device in the above-mentioned method embodiments.

[0406] The present application also provides a computer program product comprising instructions, which, when executed by a computer, implement the methods performed by a transmitting device or a receiving device in the above-mentioned method embodiments.

[0407] The present application also provides a communication system, which includes at least one of the transmitting end device or the receiving end device in the above embodiments.

[0408] The explanation of the relevant contents and beneficial effects of any of the above-mentioned devices can be referred to the corresponding method embodiments provided above, which will not be repeated here.

[0409] It is understood that the processor in the embodiments of the present application may be a central processing unit (CPU), or may be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor.

[0410] The method steps in the embodiments of the present application can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, and the software modules can be stored in random access memory, flash memory, read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, hard disks, mobile hard disks, compact disc read-only memory (CD-ROM) or any other form of storage medium well known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and storage medium can be located in an ASIC. In addition, the ASIC can be located in a transmitting device or a receiving device. Of course, the processor and storage medium can also be present in a transmitting device or a receiving device as discrete components.

[0411] In the above embodiments, all or part of the embodiments may be implemented using software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are performed in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user device, or other programmable device. The computer program or instructions may be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions may be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; an optical medium, such as a digital video disk; or a semiconductor medium, such as a solid-state drive.

[0412] In the various embodiments of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced by each other. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

[0413] Unless otherwise indicated, all technical and scientific terms used in the embodiments of the present application have the same meaning as those generally understood by those skilled in the art of the technical field of the application. The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the application. It should be understood that the above are for illustration, and the examples above are only for helping those skilled in the art to understand the embodiments of the present application, rather than limiting the application embodiments to the specific numerical values ​​or specific scenarios illustrated. Those skilled in the art can obviously carry out various equivalent modifications or changes based on the examples given above, and such modifications and changes also fall within the scope of the embodiments of the present application.

Claims

1. A communication method based on low-density parity check (LDPC) codes, characterized in that: The method comprises: Obtaining an information bit sequence; The information bit sequence is LDPC-encoded according to the LDPC base matrix to obtain a first LDPC codeword sequence, wherein the q×(i-1)+1th row to the q×ith row of the first part of the LDPC base matrix include M i Unit 1, F i Unit 2 and G i a third unit, the first part is a matrix region composed of the 1st column to the xth column of the LDPC base matrix, the first unit is a matrix of q rows and k columns and the column weight of each column is 1, the second unit is a matrix of q rows and k columns, and the column weight of at least one column of the second unit is 1 and the column weight of the remaining columns is 0, the third unit is a matrix of q rows and k columns and the column weight of each column is 0, i and q are positive integers, x and k are integers greater than or equal to 2, M i is a positive integer, F i and G i is a non-negative integer; Based on the first LDPC codeword sequence, a second LDPC codeword sequence is output.

2. The method according to claim 1, characterized in that The step of outputting a second LDPC codeword sequence based on the first LDPC codeword sequence comprises: Performing a first interleaving on a portion of the first LDPC codeword sequence corresponding to the information column of the LDPC base matrix and a portion of the first LDPC codeword sequence corresponding to the core check column of the LDPC base matrix to obtain a second LDPC codeword sequence, wherein the first interleaving is performed with columns of the number of lifting values ​​as a granularity, and the number of the second units included in the base matrix corresponding to the second LDPC codeword sequence is less than the number of the second units included in the base matrix corresponding to the first LDPC codeword sequence; The second LDPC codeword sequence is output.

3. A communication method based on low-density parity check LDPC code, characterized in that: The method comprises: Receiving a second LDPC codeword sequence; The second LDPC codeword sequence is decoded according to an LDPC base matrix, wherein the q×(i-1)+1th row to the q×ith row of the first part of the LDPC base matrix include M i Unit 1, F i Unit 2 and G i a third unit, the first part is a matrix region composed of the 1st column to the xth column of the LDPC base matrix, the first unit is a matrix of q rows and k columns and the column weight of each column is 1, the second unit is a matrix of q rows and k columns, and the column weight of at least one column of the second unit is 1 and the column weight of the remaining columns is 0, the third unit is a matrix of q rows and k columns and the column weight of each column is 0, i and q are positive integers, x and k are integers greater than or equal to 2, M i is a positive integer, F i and G i A non-negative integer.

4. The method according to claim 3, characterized in that The decoding the second LDPC codeword sequence according to the LDPC base matrix includes: Performing a first column transformation on the information column and the core check column of the LDPC base matrix, wherein the first column transformation is performed with the columns of the number of lifting values ​​as the granularity, and the number of the second units included in the LDPC base matrix after the first column transformation is less than the number of the second units included in the LDPC base matrix not subjected to the first column transformation; The second LDPC codeword sequence is decoded according to the LDPC base matrix after the first column transformation.

5. The method according to any one of claims 1 to 4, characterized in that When i1 is less than i2, Greater than When i=i1, F i The value of When i=i2, F i The value of .

6. The method according to claims 1 to 4, characterized in that The value range of i includes multiple continuous sub-intervals, and the same sub-interval corresponds to the same F i , and F i Decrease by sub-interval.

7. The method according to claim 6, characterized in that When i is less than the first value, F i Greater than 0; When i is greater than or equal to the first value, F i is 0.

8. The method according to claim 6, characterized in that When i is less than the second value, the threshold V i is 2; When i is greater than or equal to the second value and less than the third value, the threshold V i is 1; When i is greater than or equal to the third value, the threshold V i is 0.

9. The method according to any one of claims 1 to 8, characterized in that The M i The first unit, the F i The second unit and the G i The third unit is included in the non-punctured information columns in the 1st column to the xth column of the LDPC base matrix; or, The M i The first unit, the F i The second unit and the G i The third unit includes information columns in columns 1 to x of the LDPC base matrix; or, The M i The first unit, the F i The second unit and the G i The third units are included in non-punctured columns from the 1st column to the xth column of the LDPC base matrix.

10. The method according to any one of claims 1 to 9, characterized in that q＝1。 11. The method according to claim 10, characterized in that The sum of the offset values ​​of the non-zero elements of the first unit is an integer multiple of the boost value.

12. The method according to claim 10 or 11, characterized in that: When the bit rate is greater than the first bit rate threshold, F i is 0.

13. The method according to claim 12, characterized in that The first bit rate threshold is any one of the following bit rates: 0.926, or 14. The method according to any one of claims 1 to 13, characterized in that The LDPC base matrix includes punctured columns; The F i At most one second unit among the second units includes the perforation column.

15. The method according to any one of claims 1 to 14, characterized in that A matrix region corresponding to the non-punctured information column of the LDPC base matrix does not include the second unit.

16. The method according to any one of claims 1 to 15, characterized in that The first part includes a first sub-part, and the first sub-part is a matrix area consisting of the 1st row to the uth row and the y+1th column to the xth column of the first part, where u is an integer greater than or equal to 1, u-1=xy-1, and y is less than x; The diagonal elements of the first sub-part are all non-zero elements, the first sub-part includes N blocks, and the blocks are square matrices; the N blocks include all diagonal elements of the first sub-part, the diagonal elements of each block in the N blocks overlap with the diagonal elements of the first sub-part, and the blocks do not overlap; some or all of the N blocks include multiple rows, and the non-zero elements of at least two rows in the multiple rows have a true inclusion relationship.

17. The method according to claim 16, characterized in that The N blocks consist of N1 first blocks and one second block, the size of the first block is k×k, the size of the second block is k′×k′, N1 is a positive integer, N2 is a non-negative integer, and k′ is less than k.

18. The method according to claim 16 or 17, characterized in that All elements in the first subpart except the N blocks are zero elements.

19. The method according to any one of claims 1 to 18, characterized in that The first part includes a first sub-part, and the first sub-part is a matrix area consisting of the 1st row to the uth row and the y+1th column to the xth column of the first part, where u is an integer greater than or equal to 1, u-1=xy-1, and y is less than x; When u-1=xy-1=3, the positions of the zero and non-zero elements of the first sub-part are shown in the following matrix: and / or, When u-1=xy-1=4, the positions of the zero and non-zero elements of the first sub-part are shown in any of the following matrices: or and / or, When u-1=xy-1=5, the positions of the zero and non-zero elements of the first sub-part are shown in any of the following matrices: or Among them, "1" in the above matrices represents a non-zero element, and "0" represents a non-zero element.

20. The method according to any one of claims 1 to 9, characterized in that q=k.

21. The method according to claim 20, characterized in that The row weight of each row of the first unit is 1.

22. The method according to claim 21, characterized in that Each of the first units is based on a sequence θ (θ1, θ2, ..., θ a ,…,θ k ), where the a-th element θ a represents the ath row and the θth row of the first unit a The elements of the column are non-zero elements, and a is an integer greater than 0 and less than or equal to k.

23. The method according to claim 22, characterized in that θ a =a+b(mod k), or, θ a =k+1-a+b(mod k), where b is a constant.

24. The method according to any one of claims 21 to 23, characterized in that The offset values ​​of the non-zero elements of the first unit are the same; or, Any two non-zero elements of the first unit have the same remainder with respect to the lifted value; or, The sum of the offset values ​​of the non-zero elements of the first unit is an integer multiple of the boost value.

25. The method according to any one of claims 21 to 24, characterized in that When q=k=2, the positions of the zero and non-zero elements of the first unit are shown in any of the following matrices: or and / or, When q=k=3, the positions of the zero and non-zero elements of the first unit are shown in any of the following matrices: or and / or, When q=k=4, the positions of the zero and non-zero elements of the first unit are shown in any of the following matrices: or Among them, "1" in the above matrices represents a non-zero element, and "0" represents a non-zero element.

26. The method according to any one of claims 1 to 25, characterized in that The LDPC base matrix is ​​obtained according to an indicator matrix, an element of the indicator matrix corresponds to one of the first unit, the second unit or the third unit, and the value of the element in the indicator matrix is ​​used to indicate the position of the zero element and / or non-zero element in the first unit, the second unit or the third unit corresponding to the element.

27. The method according to any one of claims 1 to 25, characterized in that The row numbers of the rows of the matrix region including the first unit, the second unit and the third unit are greater than the row numbers of the rows in the matrix region corresponding to a first coding rate, and the first coding rate is greater than a coding rate threshold.

28. The method according to any one of claims 1 to 27, characterized in that F i Related to at least one of the following: The code rate corresponding to the q×(i-1)+1th row to the q×ith row, the row weight of the q×(i-1)+1th row to the q×ith row, or the position of the zero elements and / or non-zero elements of the q×(i-1)+1th row to the q×ith row of the punctured column of the LDPC base matrix.

29. A communication device, characterized in that: The method comprises a module or a unit for executing the method as claimed in any one of claims 1 to 28.

30. A communication device, characterized in that: It includes a processor and an interface circuit, wherein the interface circuit is used to receive signals from other communication devices outside the communication device and transmit them to the processor or send signals from the processor to other communication devices outside the communication device, and the processor is used to implement the method as described in any one of claims 1 to 28 through a logic circuit or executing code instructions.

31. The communication device according to claim 30, characterized in that: The communication device is a chip or a chip system.

32. A computer-readable storage medium, characterized in that: The storage medium stores a computer program or an instruction, and when the computer program or the instruction is executed by the communication device, the method according to any one of claims 1 to 28 is implemented.

33. A computer program product, characterized in that The invention comprises a computer program which, when being executed, implements the method according to any one of claims 1 to 28.

34. A communication system, characterized in that: include: A sending end device for executing the method as claimed in any one of claims 1, 2, 5 to 28; A receiving device for executing the method as claimed in any one of claims 3 to 28.

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