Signal processing method, apparatus, and system

Abstract

The present application relates to the technical field of communications, and discloses a signal processing method, apparatus, and system. In the method, a signal to be transmitted is encoded to obtain a plurality of code blocks, wherein the plurality of code blocks comprise a first data signal and / or a first control signal, and further comprise a management signal. Thus, the plurality of code blocks comprise relatively rich signal types. In addition, in the method, the plurality of code blocks are transmitted by means of one serial channel. The number of pins of the serial channel can be small. Furthermore, in the method, a serial channel based on an MII can be used, so that the method can be applied to an MII scenario.

Description

Signal processing method, device and system

[0001] This application claims priority to Chinese patent application number 202311162937.4, filed on September 6, 2023, entitled “Signal Processing Method, Device and System”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to a signal processing method, device and system. Background Art

[0003] In the field of communication technology, a signal transmitting end may process a signal and transmit the obtained processing result to a signal receiving end. The signal receiving end may restore the signal based on the received processing result.

[0004] Summary of the Invention

[0005] The present application proposes a signal processing method, device and system for processing signals.

[0006] In a first aspect, a signal processing method is provided, comprising: encoding a signal to be transmitted to obtain multiple code blocks, wherein the multiple code blocks include a first data signal and / or a first control signal, and the multiple code blocks also include a management signal; and transmitting the multiple code blocks via a serial channel. The serial channel may be referred to as a first serial channel. In this method, because the multiple code blocks include the management signal as well as the first data signal and / or the first control signal, the multiple code blocks can include content of a wide variety of signal types. When transmitting the multiple code blocks via a serial channel, only a few pins are required to implement the serial channel, thereby enabling transmission of the first data signal, the first control signal, and the management signal over the serial channel.

[0007] In one possible implementation, a first code block among the multiple code blocks includes a first portion and a second portion, where the first portion includes a first data signal and / or a first control signal, and the second portion includes a management signal. In other words, the same first code block can carry management signals, first data signals, and / or first control signals, providing a wide variety of flexible signal types.

[0008] In one possible implementation, there are multiple first code blocks, and the management signal appears periodically in each of the multiple first code blocks. This allows the location of the management signal in the first code block to be quickly determined based on the regularity of the management signal appearing periodically in the multiple first code blocks, resulting in more efficient acquisition of the management signal from the first code block.

[0009] In one possible implementation, the multiple code blocks include a management code block, which includes a management signal. In other words, in addition to carrying the management signal via the first code block, the management signal can also be carried via the management code block, providing greater flexibility in how the management signal is carried. Furthermore, when the management code block includes a multi-bit management signal, transmitting the management signal via the management code block improves transmission efficiency.

[0010] In one possible implementation, a serial channel is used to connect the media access control (MAC) layer and the physical layer (PHY). In this case, the serial channel can be referred to as a serial channel implemented based on a media independent interface (MII), and thus the method can be applied to MII scenarios.

[0011] In a possible implementation, the serial channel is implemented by one pin or a group of pins, so that the number of pins used to implement the serial channel can be relatively small.

[0012] In a possible implementation, the serial channel is implemented based on MII.

[0013] In a possible implementation, the signal to be transmitted is related to an Ethernet frame, so the method can be applied to Ethernet scenarios.

[0014] In a possible implementation, the signal to be transmitted being related to the Ethernet frame includes at least one of the following: the signal to be transmitted is generated based on the Ethernet frame, or the signal to be transmitted is used to manage transmission of the Ethernet frame.

[0015] In one possible implementation, the management signal includes a first management data input / output (MDIO) signal corresponding to a read operation. The method further includes receiving a second MDIO signal, the second MDIO signal being used to provide feedback regarding the read operation. Thus, the method can implement management signal interaction by transmitting the first and second MDIO signals.

[0016] In one possible implementation, the second serial channel for receiving the second MDIO signal is different from the first serial channel for transmitting the multiple code blocks. In this case, whether the transmitted MDIO signal is the first or second MDIO signal can be determined based on the serial channel, thereby preventing a read operation from being mistaken for feedback to a read operation, or vice versa.

[0017] In a possible implementation, the method is applied to a PHY functional module, and the plurality of code blocks further include a physical layer channel state indication. Thus, the method can realize the transmission of the physical layer channel state indication.

[0018] In a second aspect, a signal processing method is provided, comprising: receiving multiple code blocks via a serial channel, the multiple code blocks including a first data signal and / or a first control signal, and the multiple code blocks also including a management signal; and obtaining the management signal, as well as the first data signal and / or the first control signal, from the multiple code blocks. The serial channel may be referred to as a first serial channel. In this method, because the multiple code blocks include the management signal, the first data signal, and / or the first control signal, the multiple code blocks can include content of a wide variety of signal types. When transmitting multiple code blocks via a serial channel, only a few pins are required to implement the serial channel, and the first data signal, the first control signal, and the management signal can then be transmitted over the serial channel.

[0019] In one possible implementation, a first code block among multiple code blocks includes a first portion and a second portion, the first portion including a first data signal and / or a first control signal, and the second portion including a management signal. Acquiring the management signal and the first data signal and / or the first control signal from the multiple code blocks includes: acquiring the first data signal and / or the first control signal from the first portion of the first code block; and acquiring the management signal from the second portion of the first code block. In this method, the same first code block can carry both the management signal and the first data signal and / or the first control signal. The types of signals carried by the first code block are relatively diverse and flexible, enabling the acquisition of multiple signals based on the first code block.

[0020] In one possible implementation, there are multiple first code blocks, and the second portion appears periodically in the multiple first code blocks. Acquiring the management signal from the second portion of the first code block includes: acquiring the periodically appearing second portion from the multiple first code blocks; and acquiring the management signal from the second portion. In this method, based on the periodic appearance of the second portion in the multiple first code blocks, the location of the management signal in the first code block can be determined relatively quickly, thereby increasing the efficiency of acquiring the management signal from the first code block.

[0021] In one possible implementation, the multiple code blocks include a management code block, and the management code block includes a management signal; obtaining the management signal from the multiple code blocks includes: obtaining the management signal from the management code block. That is, in addition to carrying the management signal via the first code block, the management signal can also be carried via the management code block, providing a more flexible method for carrying the management signal. Furthermore, when the management code block includes a multi-bit management signal, transmitting the management signal via the management code block improves management signal transmission efficiency.

[0022] In one possible implementation, a serial channel is used to connect the MAC layer and the PHY. In this case, the serial channel can be called a serial channel implemented based on MII, and thus the method can be applied to MII scenarios.

[0023] In a possible implementation, the serial channel is implemented by one pin or a group of pins, so that the number of pins used to implement the serial channel can be relatively small.

[0024] In a possible implementation, the serial channel is implemented based on MII.

[0025] In one possible implementation, the management signal includes a first MDIO signal corresponding to a read operation. The method further includes transmitting a second MDIO signal for providing feedback on the read operation. Thus, the method can implement management signal interaction by transmitting the first and second MDIO signals.

[0026] In one possible implementation, the second serial channel for transmitting the second MDIO signal is different from the first serial channel for receiving the plurality of code blocks. In this case, whether the transmitted MDIO signal is the first or second MDIO signal can be determined based on the serial channel, thereby preventing a read operation from being mistaken for feedback to a read operation, or vice versa.

[0027] In one possible implementation, the method is applied to a MAC functional module, the multiple code blocks further include a physical layer channel state indication, and the method further includes: obtaining the physical layer channel state indication from the multiple code blocks. Thus, the method can implement transmission of the physical layer channel state indication.

[0028] In a third aspect, a signal processing device is provided, which includes: a transceiver module for performing operations related to reception and / or transmission in the first aspect and any corresponding possible implementation thereof; and a processing module for performing other operations other than the operations related to reception and / or transmission in the first aspect and any corresponding possible implementation thereof.

[0029] In a fourth aspect, a signal processing device is provided, which includes: a transceiver module for performing operations related to receiving and / or sending in the second aspect and any corresponding possible implementation thereof; and a processing module for performing other operations other than the operations related to receiving and / or sending in the second aspect and any corresponding possible implementation thereof.

[0030] In a fifth aspect, a signal processing device is provided, which includes: an encoding module for encoding a signal to be transmitted to obtain multiple code blocks, the multiple code blocks including a first data signal and / or a first control signal, and the multiple code blocks also including a management signal; a sending module for sending multiple code blocks through a serial channel.

[0031] In a possible implementation, a first code block among the multiple code blocks includes a first part and a second part, the first part includes a first data signal and / or a first control signal, and the second part includes a management signal.

[0032] In a possible implementation, there are multiple first code blocks, and the second part appears periodically in the multiple first code blocks.

[0033] In a possible implementation, the multiple code blocks include a management code block, and the management code block includes a management signal.

[0034] In a possible implementation, a serial channel is used to connect the MAC layer and the PHY.

[0035] In a possible implementation, the serial channel is implemented by one pin or a group of pins.

[0036] In a possible implementation, the serial channel is implemented based on MII.

[0037] In a possible implementation, the signal to be transmitted is related to an Ethernet frame.

[0038] In a possible implementation, the signal to be transmitted being related to the Ethernet frame includes at least one of the following: the signal to be transmitted is generated based on the Ethernet frame, or the signal to be transmitted is used to manage transmission of the Ethernet frame.

[0039] In a possible implementation, the management signal includes a first MDIO signal corresponding to a read operation; the apparatus further includes: a receiving module configured to receive a second MDIO signal, where the second MDIO signal is used to provide feedback on the read operation.

[0040] In a possible implementation, the second serial channel for receiving the second MDIO signal is different from the first serial channel for sending the multiple code blocks.

[0041] In a possible implementation manner, if the device is applied to a PHY functional module, the multiple code blocks further include a physical layer channel status indication.

[0042] In a sixth aspect, a signal processing device is provided, which includes: a receiving module for receiving multiple code blocks through a serial channel, the multiple code blocks including a first data signal and / or a first control signal, and the multiple code blocks also including a management signal; an acquisition module for acquiring the management signal, as well as the first data signal and / or the first control signal from the multiple code blocks.

[0043] In one possible implementation, a first code block among multiple code blocks includes a first part and a second part, the first part includes a first data signal and / or a first control signal, and the second part includes a management signal; an acquisition module is used to obtain the first data signal and / or the first control signal from the first part of the first code block, and obtain the management signal from the second part of the first code block.

[0044] In a possible implementation, there are multiple first code blocks, and the second part appears periodically in the multiple first code blocks; the acquisition module is used to obtain the periodically appearing second part from the multiple first code blocks, and obtain the management signal from the second part.

[0045] In a possible implementation, the multiple code blocks include a management code block, and the management code block includes a management signal; the acquisition module is configured to acquire the management signal from the management code block.

[0046] In a possible implementation, a serial channel is used to connect the MAC layer and the PHY.

[0047] In a possible implementation, the serial channel is implemented by one pin or a group of pins.

[0048] In a possible implementation, the serial channel is implemented based on MII.

[0049] In a possible implementation, the management signal includes a first MDIO signal corresponding to a read operation; the apparatus further includes: a sending module, configured to send a second MDIO signal, where the second MDIO signal is used to provide feedback on the read operation.

[0050] In a possible implementation, the second serial channel for sending the second MDIO signal is different from the first serial channel for receiving the multiple code blocks.

[0051] In a possible implementation, if the device is applied to a MAC functional module, the multiple code blocks further include a physical layer channel state indication; and the acquisition module is further configured to acquire the physical layer channel state indication from the multiple code blocks.

[0052] In a seventh aspect, a communication device is provided, comprising: a MAC layer circuit, the MAC layer circuit being configured to execute any one of the signal processing methods in the first aspect and / or the second aspect.

[0053] In an eighth aspect, a communication device is provided, comprising: a PHY circuit, the PHY circuit being configured to execute any one of the signal processing methods in the first aspect and / or the second aspect.

[0054] Any signal processing device or communication device in the fourth to eighth aspects above may be a chip or a communication device.

[0055] In a ninth aspect, a chip is provided, comprising: a MAC layer circuit, the MAC layer circuit being configured to execute any one of the signal processing methods in the first aspect and / or the second aspect.

[0056] In a tenth aspect, another chip is provided, which includes: a PHY circuit, and the PHY circuit is used to execute any signal processing method in the first aspect and / or the second aspect.

[0057] In an eleventh aspect, a communication system is provided, comprising a MAC layer circuit and a PHY circuit. The MAC layer circuit is configured to perform the signal processing method of the first aspect, and the PHY circuit is configured to perform the signal processing method of the second aspect; alternatively, the PHY circuit is configured to perform the signal processing method of the first aspect, and the MAC layer circuit is configured to perform the signal processing method of the second aspect. This communication system can be implemented using a chip or a communication device.

[0058] It should be understood that the beneficial effects achieved by the technical solutions of the third to eleventh aspects of this application and the corresponding possible implementation methods can be referred to the technical effects of the technical solutions of the first to second aspects and their corresponding possible implementation methods, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] FIG1 is a pin diagram of an MII in related art;

[0060] FIG2 is a pin diagram of an RMII in the related art;

[0061] FIG3 is a schematic diagram of a host, SPI and MACPHY chip in a related art;

[0062] FIG4 is a schematic diagram of SGMII compatible with a 100 Mbps transmission rate in a related art;

[0063] FIG5 is a schematic diagram of a signal transmitted by an MII interface in a related art;

[0064] FIG6 is a schematic diagram of a transmission management signal in a related art;

[0065] FIG7 is a schematic diagram of an implementation environment provided by an embodiment of the present application;

[0066] FIG8 is a flowchart of a signal processing method provided in an embodiment of the present application;

[0067] FIG9 is a schematic diagram of a format of a management frame provided in an embodiment of the present application;

[0068] FIG10 is a schematic diagram of the format of another management frame provided in an embodiment of the present application;

[0069] FIG11 is a schematic diagram of a plurality of first code blocks provided in an embodiment of the present application;

[0070] FIG12 is a schematic diagram of another plurality of first code blocks provided in an embodiment of the present application;

[0071] FIG13 is a schematic diagram of another embodiment of the present application providing a plurality of first code blocks;

[0072] FIG14 is a schematic diagram of another embodiment of the present application providing a plurality of first code blocks;

[0073] FIG15 is a schematic diagram of another embodiment of the present application providing a plurality of first code blocks;

[0074] FIG16 is a schematic diagram of a management code block provided in an embodiment of the present application;

[0075] FIG17 is a schematic diagram of a code block provided in an embodiment of the present application;

[0076] FIG18 is a schematic diagram of a second code block provided in an embodiment of the present application;

[0077] FIG19 is a schematic diagram of a third code block provided in an embodiment of the present application;

[0078] FIG20 is a schematic diagram of a first code block provided in an embodiment of the present application;

[0079] FIG21 is a schematic diagram of an Ethernet frame transmission according to an embodiment of the present application;

[0080] FIG22 is a schematic diagram of a misidentification provided by an embodiment of the present application;

[0081] FIG23 is a schematic diagram of a process for transmitting multiple code blocks provided in an embodiment of the present application;

[0082] FIG24 is a schematic diagram of a process for transmitting a first code block provided in an embodiment of the present application;

[0083] FIG25 is a schematic diagram of another process of transmitting a first code block provided in an embodiment of the present application;

[0084] FIG26 is a schematic diagram of a process of transmitting a management code block according to an embodiment of the present application;

[0085] FIG27 is a schematic diagram of another code block provided in an embodiment of the present application;

[0086] FIG28 is a schematic diagram of a process for transmitting an H.sig code block provided in an embodiment of the present application;

[0087] FIG29 is a schematic diagram of another process of transmitting an H.sig code block provided in an embodiment of the present application;

[0088] FIG30 is a schematic diagram of another process of transmitting an H.sig code block provided in an embodiment of the present application;

[0089] FIG31 is a schematic diagram of another first code block provided in an embodiment of the present application;

[0090] FIG32 is a schematic diagram of another process of transmitting multiple first code blocks provided in an embodiment of the present application;

[0091] FIG33 is a schematic diagram of a newly added code table provided in an embodiment of the present application;

[0092] FIG34 is a schematic diagram of a physical layer signal indicator code provided in an embodiment of the present application;

[0093] FIG35 is a flowchart of another signal processing method provided in an embodiment of the present application;

[0094] FIG36 is a schematic diagram of a process of inputting multiple code blocks into an RS according to an embodiment of the present application;

[0095] FIG37 is a schematic diagram of a synchronization process of a management channel provided in an embodiment of the present application;

[0096] FIG38 is a schematic diagram of a data channel synchronization process provided by an embodiment of the present application;

[0097] FIG39 is a schematic structural diagram of a signal processing device provided in an embodiment of the present application;

[0098] FIG40 is a schematic structural diagram of another signal processing device provided in an embodiment of the present application;

[0099] FIG41 is a schematic diagram of the structure of a computer system provided in an embodiment of the present application;

[0100] Figure 42 is a structural diagram of another computer system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0101] The terms used in the embodiments of the present application are only used to explain the embodiments of the present application and are not intended to limit the present application. The embodiments of the present application are described below in conjunction with the accompanying drawings.

[0102] In the field of communications technology, a signal transmitter can process a signal to be transmitted, obtain a processing result, and transmit the processing result to a signal receiver. The signal transmitter can encode the signal, and the processing result includes multiple code blocks obtained by encoding. The signal receiver can decode the multiple code blocks to recover the signal. Related art techniques encode only data signals or control signals to obtain multiple code blocks. Because the encoded multiple code blocks contain a limited number of signal types, the multiple code blocks only carry information about the data signal or control signal, and the types of information carried by the multiple code blocks are limited.

[0103] Furthermore, in the field of communications technology, signals can be transmitted between the media access control (MAC) chip and the physical layer (PHY) chip via a media independent interface (MII). For example, in scenarios such as the Industrial Internet of Things (IIoT), the IOT terminal includes a PHY chip and a microcontroller (MCU), and the MCU includes a MAC chip. Signals are transmitted between the PHY and MAC chips via the MII. For another example, in a switch scenario, the switch includes a PHY and MAC chip, and signals are transmitted between the PHY and MAC chips via the MII.

[0104] In related art, the MII is a parallel interface that includes pins for transmitting data signals, control signals, and management signals. Figure 1 is a schematic diagram of the MII pinout in related art. As shown in Figure 1, the MII is used to implement signal transmission between the MAC chip and the PHY chip. The MII includes 18 pins, and the signals transmitted by these 18 pins are as follows: 1 pin is used to transmit the transmit enable signal (TX_EN), 1 pin is used to transmit the transmit data error prompt signal (TX_ER), 4 pins are used to transmit the transmit data signal (TXD), and these 4 pins are represented as TXD<3:0> in Figure 1, 1 pin is used to transmit the transmit data reference clock (TX_CLK), 1 pin is used to transmit the receive data error prompt signal (RX_ER), 1 pin is used to transmit the receive data valid signal (RX_DV), 4 pins are used to transmit the receive data signal (RXD), and these 4 pins used to transmit RXD in Figure 1 are represented as RXD<3:0>, 1 pin is used to transmit the receive data reference clock (RX_CLK), 1 pin is used to transmit the collision detection (COL) signal, and 1 pin is used to transmit the carrier detection (CARRIER) signal. sense, CRS) signal, 1 pin is used to transmit the management data clock (MDC), and 1 pin is used to transmit the management data input and output (MDIO) signal.

[0105] However, in scenarios such as the Industrial Internet of Things, since the chip packaging cost increases with the increase in the number of chip pins, the number of chip pins needs to be controlled. When the number of pins that a chip can provide is relatively limited, the number of MII pins needs to be reduced so that the MCU can allocate more pins to provide other functions. In the scenario of using a switch, the MAC chip can be included in the switching chip. Since the switching chip usually needs to connect to more Ethernet chips to support more Ethernet interfaces, it is necessary to reduce the number of MII pins of the MAC chip so that the switching chip can support more Ethernet interfaces.

[0106] In a related technology, a reduced media independent interface (RMII) is derived based on the MII, and signals are transmitted between the MAC chip and the PHY chip through the RMII. Figure 2 is a pin diagram of the RMII in the related technology. As shown in Figure 2, the RMII is used to implement signal transmission between the MAC chip and the PHY chip. The RMII includes 9 pins, and the signals transmitted by these 9 pins are as follows: 1 pin is used to transmit TX_EN, 2 pins are used to transmit TXD, and these 2 pins are represented as TXD<1:0> in Figure 2, 1 pin is used to transmit RX_ER, 2 pins are used to transmit RXD, and these 2 pins are represented as RXD<1:0> in Figure 2, 1 pin is used to transmit the carrier sense data valid (CRS_DV) signal, 1 pin is used to transmit the MDC, and 1 pin is used to transmit the MDIO signal. However, the number of RMII pins is still relatively large.

[0107] In another related art, the MAC chip and the PHY chip are integrated into a media access control physical layer (MACPHY) chip. The MCU may include a MACPHY chip, and the MACPHY chip is connected to the host via a serial peripheral interface (SPI). Figure 3 is a schematic diagram of a host, SPI, and MACPHY chip in a related art. As shown in Figure 3, a serial clock signal (SCK), a master output slave input (MOSI), n chip selects (CS), a master input slave output (MISO), and n interrupt requests (IRQ) are transmitted between the host and the MACPHY chip, where n is a positive integer, and n CSs are represented by CSn shown in Figure 3, and n IRQs are represented by IRQn shown in Figure 3. The MACPHY chip can also transmit signals to other chips. For example, as shown in Figure 3, the MACPHY chip is connected to a signal line 1 and a signal line 2, and signal lines 1 and 2 can be used to transmit differential signals to other chips. However, the SPI in the related art is not suitable for a transmission rate of 100 megabits per second (Mbps), resulting in a relatively limited scope of application.

[0108] In another related art, signal transmission between a MAC chip and a PHY chip is achieved via a serial gigabit media independent interface (SGMII). The SGMII has an 8-bit bit width and supports a transmission rate of 1000 megabits per second (Mbps). The SGMII is backward compatible with transmission rates of 10 Mbps and 100 Mbps. To achieve compatibility with a 10 Mbps transmission rate via the SGMII, data is replicated 100 times and then transmitted. To achieve compatibility with a 100 Mbps transmission rate via the SGMII, data is replicated 100 times and then transmitted. Figure 4 is a schematic diagram of SGMII compatibility with a 100 Mbps transmission rate in a related art. As shown in Figure 4, data to be transmitted at a 100 Mbps transmission rate includes d0, d1, and d2. For each data item to be transmitted at a 100 Mbps transmission rate, each data item is replicated 10 times. The replicated data can then be transmitted via the SGMII, achieving SGMII compatibility with a 100 Mbps transmission rate. However, copying data multiple times to accommodate lower transmission rates results in higher transmission costs and power consumption.

[0109] Furthermore, since the data width of SGMII is 8 bits, while the data width of MII is 4 bits, if SGMII is used instead of MII, the difference in data width will lead to data width mismatch. For example, Figure 5 is a schematic diagram of signals transmitted by an MII interface in the related art. As shown in Figure 5, RX_DV indicates that the 4-bit data 0101, D1, D2, / F / , and D4 to D7 are valid data, RX_ER indicates that / F / is error data, and D1, D2, D4 to D7 are all non-error data. Among them, D1, D2, / F / , and D4 to D7 are all 4 bits. For the error data / F / transmitted by MII, if SGMII is used instead of MII, the data transmitted by SGMII to replace the error data / F / will meet the SGMII data width requirement of 8 bits by squeezing out D2 or D4. In other words, the 8-bit data width of SGMII cannot match the 4-bit data width of MII.

[0110] In another related technology, management signals are transmitted through independent channels. For example, FIG6 is a schematic diagram of a related technology for transmitting management signals. The switching chip of the switch includes a MAC chip, and, as shown in FIG6 , the switching chip is connected to multiple PHY chips, and the switching chip is also connected to a complex programmable logic device (CPLD) or an MCU. The switching chip establishes channels for transmitting management signals with N PHY chips through the CPLD or MCU, where N is a positive integer. That is, the switching chip transmits management signals with the N PHY chips through the CPLD or MCU, and the management signals include MDIO signals. However, the method of establishing channels for transmitting management signals through the CPLD or MCU results in a high equipment cost for transmitting management signals and a large development workload.

[0111] An embodiment of the present application provides a signal processing method for encoding and decoding a signal to be transmitted to realize signal processing. The method can be applied to a scenario in which a signal is transmitted via MII, that is, the above-mentioned signal to be transmitted is a signal transmitted by MII. The method can also be applied to scenarios other than MII. Figure 7 is a schematic diagram of an implementation environment provided by an embodiment of the present application. The method can be applied to the implementation environment shown in Figure 7, wherein the implementation environment shown in Figure 7 takes the MII scenario as an example. The method can also be applied to other implementation environments. For example, the implementation environment in which the method is applied includes chip 1 and chip 2, chip 1 and chip 2 are connected, and the method can be applied to chip 1 or chip 2.

[0112] Referring to FIG. 7 , an implementation environment includes a switch 701 and an IoT terminal 702. The switch 701 includes a MAC function module 7011 and a PHY function module 7012. Signals are transmitted between the MAC function module 7011 and each PHY function module 7012 via the MII. The IoT terminal 702 includes a MAC function module 70211 and a PHY function module 7022. Signals are transmitted between the MAC function module 70211 and the PHY function module 7022 via the MII. Signals can be transmitted between the PHY function modules 7012 and 7022. In some embodiments, the IoT terminal 702 includes an MCU 7021 and a PHY function module 7022. The MCU 7021 includes a MAC function module 70211. In some embodiments, one or more of the MAC function module 7011, the PHY function module 7012, the MAC function module 70211, and the PHY function module 7022 can be located in a separate chip, in a separate die, or in one or more cores of a multi-core chip. The signal processing method provided in the embodiment of the present application can be applied to signal transmission between the MAC function module 7011 and the PHY function module 7012, and can also be applied to signal transmission between the MAC function module 70211 and the PHY function module 7022. The number of switches 701, the number of MAC function modules 7011, the number of PHY function modules 7012, the number of IoT terminals 702, the number of MCUs 7021, the number of MAC function modules 70211, and the number of PHY function modules 7022 shown in FIG7 are only examples and are not limited in this embodiment of the present application. For example, the above-mentioned switches 701 and IoT terminals 702 can be single pair Ethernet (SPE) devices or advanced physical layer (APL) devices.

[0113] The signal processing method provided in the embodiment of the present application can be shown in Figure 8. Next, the method will be described in conjunction with the implementation environment shown in Figure 7. The method can be applied to the MAC functional module or the PHY functional module shown in Figure 7. As shown in Figure 8, the method includes but is not limited to S801 and S802.

[0114] S801 , encode a signal to be transmitted to obtain multiple code blocks, where the multiple code blocks include a first data signal and / or a first control signal, and the multiple code blocks also include a management signal.

[0115] In one possible implementation, the signal to be transmitted includes at least one of a first data signal and / or a first control signal, and the signal to be transmitted also includes a management signal. The signal type included in the multiple code blocks is determined based on the signal type included in the signal to be transmitted. Thus, when the signal to be transmitted includes the first data signal, the multiple code blocks include the first data signal; when the signal to be transmitted includes the first control signal, the multiple code blocks include the first control signal; when the signal to be transmitted includes the management signal, the multiple code blocks include the management signal. In an embodiment of the present application, the first data signal may be a signal for transmitting data, the first control signal may be a signal for controlling the transmission of data, and the management signal may be a signal other than the first data signal and the first control signal.

[0116] Taking the example of a signal to be transmitted including a signal transmitted via MII, the management signal includes an MDIO signal. For example, the method is applied to a MAC functional module, and the MAC functional module includes a management entity (STA). In this case, the management signal includes an MDIO signal driven by the STA. For another example, the method is applied to a PHY functional module. In this case, the management signal includes an MDIO signal driven by the PHY functional module. The manner in which STA drives the MDIO signal can refer to the manner in which STA drives the MDIO signal in the Institute of Electrical and Electronics Engineers (IEEE) 802.3 standard, and the manner in which the PHY functional module drives the MDIO signal can refer to the manner in which the PHY functional module drives the MDIO signal in the IEEE 802.3 standard, which will not be further described here.

[0117] In one possible implementation, the MDIO signal is associated with a management frame, for example, the various bits of the MDIO signal are used to form a management frame. The management frame includes an operation (OP) field, and the operation type indicated by the operation field includes any one of a write operation, a read operation, or a read feedback operation. For example, when the method is applied to a MAC function module, the operation type indicated by the operation field is a write operation or a read operation; when the method is applied to a PHY function module, the operation type indicated by the operation field is a read feedback operation. The management frame may also include other fields in addition to the operation field. Figure 9 is a format diagram of a management frame provided in an embodiment of the present application. As shown in Figure 9, the management frame includes a start field, an operation (OP) field, a physical layer address (PHY AD) field, a register address (REG AD) field, a reserved (RSV) field, and a register data field. The Start field indicates the start of management frame transmission, the Physical Layer Address field indicates the address of the PHY functional module where the register to be operated is located, the Register Address field indicates the address of the register, the Register Data field indicates the data to be operated on, and the Reserved field can be a preset value. As shown in Figure 9, the Start field is 2 bits long, the Operation field is 2 bits long, the Physical Layer Address field is 5 bits long, the Register Address field is 5 bits long, the Reserved field is 2 bits long, and the Register Data field is 16 bits long.

[0118] Figure 10 is a schematic diagram of the format of another management frame provided by an embodiment of the present application. Referring to Figure 10 , when the method is applied to a MAC functional module and data needs to be written to a register of a PHY functional module, the operation type indicated by the operation field is a write operation, and the value of the operation field can be 01; the physical layer address field is used to indicate the address of the PHY functional module, the register address field is used to indicate the address of the register, and the value of the reserved field is a first preset value, which xx in Figure 10 can represent; and the register data field is used to indicate the data to be written to the register.

[0119] When this method is applied to a MAC functional module and needs to read the value of a register of a PHY functional module, the operation type indicated by the operation field is a read operation, and the value of the operation field can be 10; the physical layer address field is used to indicate the address of the PHY functional module, the register address field is used to indicate the address of the register, and the value of the reserved field is a first preset value; since the first processor is not used to write data to the register, the value of the register data field can be a second preset value, and xxxxx in Figure 10 can represent the second preset value.

[0120] When this method is applied to a PHY functional module and data from a register of the PHY functional module needs to be fed back to the MAC functional module, the operation type indicated by the operation field is a read feedback operation, and the value of the operation field can be 10; the physical layer address field is used to indicate the address of the PHY functional module, the register address field is used to indicate the address of the register, the value of the reserved field is a first preset value, and the value of the register data field is used to indicate the data read from the register. For example, since the read operation and the read feedback operation target the same register, as shown in FIG10 , the read operation and the read feedback operation have the same value for the physical layer address field and the same value for the register address field.

[0121] The values ​​of the above-mentioned operation field, the value of the reserved field, and the value of the register data field when the operation type is a read operation are only for illustration. Those skilled in the art can set them based on experience or actual needs. The embodiments of the present application do not limit this. In one possible implementation, whether the method is applied to the MAC functional module or the PHY functional module, the management signal is obtained based on the management frame and the idle state. The idle state can be before or after the management frame. For example, referring to Figure 9, in addition to the management frame, there are idle states before and after the management frame. The management frame and the idle state are used to obtain the management signal.

[0122] Still taking the signal to be transmitted including the signal transmitted through MII as an example for explanation, when the method is applied to the MAC functional module, the first data signal and the first control signal can be represented as a whole by TX_EN, TX_ER and TXD shown in Figure 1. That is, by the validity and invalidity of TX_EN and the validity and invalidity of TX_ER, it is indicated that the signal transmitted by TXD is a data signal or a control signal. Wherein, the data signal includes but is not limited to the data (data) included in the Ethernet frame, and the control signal includes but is not limited to the preamble (preamble), low power idle (low power idle, LPI) and end-of-frame delimiter (end-of-frame delimiter, EFD) when the Ethernet frame is transmitted. When the method is applied to the PHY functional module, the first data signal and the first control signal can be represented as a whole by RX_DV, RX_ER and RXD shown in Figure 1. That is, by the validity and invalidity of RX_DV and the validity and invalidity of RX_ER, it is indicated that the signal transmitted by RXD is a data signal or a control signal.

[0123] In one possible implementation, the signal to be transmitted is related to an Ethernet frame. That is, the method can be applied in an Ethernet scenario. Exemplarily, the signal to be transmitted includes a first data signal and / or a first control signal, and the first data signal and / or the first control signal are generated based on the Ethernet frame to be transmitted. The signal to be transmitted also includes a management signal, and the management signal can be used to manage the transmission of the Ethernet frame. Exemplarily, when the method is applied to the MAC function module, the MAC function module converts the Ethernet frame to be transmitted into a parallel signal transmitted via the MII, and obtains the signal to be transmitted based on the parallel signal transmitted by the MII. The parallel signal transmitted via the MII refers to a signal transmitted via multiple pins of the MII shown in Figure 1. Exemplarily, part or all of the data signal transmitted by the MII is used as the first data signal, and part or all of the control signal transmitted by the MII is used as the first control signal.

[0124] Alternatively, both the first data signal and the first control signal can be generated based on an Ethernet frame. For example, when the method is applied to a MAC function module, the MAC function module obtains an Ethernet frame and generates the first data signal based on the Ethernet frame. For another example, when the method is applied to a MAC function module, the MAC function module obtains an Ethernet frame and generates a first sub-signal of the first control signal based on the Ethernet frame. In some embodiments, the first processor may also generate a second sub-signal of the first control signal. The first sub-signal may be a signal derived from the content of the Ethernet frame, for example, a control signal for MII transmission derived from the Ethernet frame; the second sub-signal may be an error signal used to transmit error information. For example, an error signal may be generated when it is necessary to interrupt the transmission of an Ethernet frame. For another example, an error signal may be generated when it is necessary to continue occupying the channel after the Ethernet frame transmission is complete. The embodiments of the present application do not limit the format of the error signal. That is, if the signal to be transmitted includes the first data signal, the first data signal is derived from the Ethernet frame; if the signal to be transmitted includes the first control signal, the first control signal includes at least one of the first sub-signal derived from the Ethernet frame or the second sub-signal generated.

[0125] In one possible implementation, when the Ethernet frame carries data, the signal to be transmitted includes a first data signal generated based on the carried data; when the Ethernet frame does not carry data, the signal to be transmitted does not include the first data signal. Exemplarily, the first sub-signal of the first control signal is obtained based on other parts of the Ethernet frame except the start of the Ethernet frame, or based on other parts of the Ethernet frame except the start of the Ethernet frame and the end of the Ethernet frame. In an embodiment of the present application, the Ethernet frame can also be used to obtain a second control signal, or to obtain a second control signal and a third control signal. For example, the second control signal is generated based on the Ethernet frame start of the Ethernet frame, or the second control signal is generated based on the Ethernet frame start of the Ethernet frame, and the third control signal is generated based on the Ethernet frame end of the Ethernet frame. When the second control signal is obtained, the signal to be transmitted may include the second control signal. When the second control signal and the third control signal are obtained, the signal to be transmitted may include the second control signal and the third control signal.

[0126] Once the signal to be transmitted is acquired, the signal to be transmitted can be encoded to obtain multiple code blocks. In one possible implementation, the first code block among the multiple code blocks includes a first part and a second part, the first part including the first data signal and / or the first control signal, and the second part including the management signal. For example, the first part is obtained by encoding the first data bit group of the first data signal and / or the first control bit group of the first control signal, and the second part is obtained based on the management signal. In an embodiment of the present application, the first data bit group of the first data signal may include some or all bits of the first data signal, and the first control bit group of the first control signal may include some or all bits of the first control signal. The first part may include at least one code block, and the second part may include at least one code block or at least one unencoded bit. The at least one code block included in the second part is obtained by encoding bits of the management signal. This embodiment of the present application does not limit the number of bits that can be encoded into a code block. In an embodiment of the present application, the bit position obtained based on the first data signal may be referred to as a data channel, the bit position obtained based on the first control signal may be referred to as a control channel, and the bit position obtained based on the management signal may be referred to as a management channel.

[0127] In one possible implementation, the code blocks included in the first part are obtained based on any one of 4B / 5B encoding, 8B / 9B encoding, 8B / 10B encoding, 64B / 65B encoding, 64B / 66B encoding, and 80B / 81B encoding. In some embodiments, if the second part includes at least one bit that has not been encoded, the at least one bit included in the second part may be a transformed bit or an untransformed bit. The embodiment of the present application does not limit the transformation method. For example, the transformation method includes sequential transformation, and the second part includes multiple bits that have been sequentially transformed. If the second part includes at least one code block obtained by encoding, the code blocks included in the second part are obtained based on any one of 4B / 5B encoding, 8B / 9B encoding, 8B / 10B encoding, 64B / 65B encoding, 64B / 66B encoding, or 80B / 81B encoding. In some embodiments, when the first part and the second part of the first code block both include encoded code blocks, the encoding method of the code blocks in the first part and the encoding method of the code blocks in the second part can be the same as or different, so that the encoding method of the code blocks in the first part and the encoding method of the code blocks in the second part are more flexible.

[0128] Exemplarily, when there are multiple first code blocks, the management signal appears periodically in the multiple first code blocks. Figure 11 is a schematic diagram of multiple first code blocks provided in an embodiment of the present application. Referring to Figure 11, each first code block includes a first part and a second part, and the first part and the second part appear alternately in the multiple first code blocks, so that the management signal appears periodically in the multiple first code blocks.

[0129] In one possible implementation, the encoding result of the first portion is used to indicate that the first portion is obtained by encoding the first data bit group of the first data signal, or by encoding the first control bit group of the first control signal, or by encoding the first data bit group of the first data signal and the first control bit group of the first control signal. For example, the first portion includes at least one code block obtained based on 4B / 5B encoding, and for any one of the at least one code block, the overall encoding status of the any one code block is used to indicate that the code block is obtained by encoding the first data bit group of the first data signal, or by encoding the first control bit group of the first control signal.

[0130] For another example, the first portion includes at least one code block obtained based on 8B / 10B encoding. For any one of the at least one code block, the overall encoding status of the code block is used to indicate whether the code block is obtained by encoding the first data bit group of the first data signal, or by encoding the first control bit group of the first control signal, or by encoding the first data bit group of the first data signal and the first control bit group of the first control signal. Regardless of whether the code blocks in the first portion are obtained through 4B / 5B encoding or 8B / 10B encoding, the method for indicating the source of the bits of the code block as a whole can be found in the relevant content of the IEEE 802.3 standard regarding indicating the source of the bits of the code block as a whole obtained through 4B / 5B encoding and 8B / 10B encoding, and will not be further described here.

[0131] In another possible implementation, part of the content in the first part is used to indicate the source of the bits of the first part. For example, the first part includes a type identification field, which is used to indicate that the first part is obtained by encoding the first data bit group of the first data signal, or by encoding the first control bit group of the first control signal, or by encoding the first data bit group of the first data signal and the first control bit group of the first control signal. In this embodiment of the present application, the signal type used to obtain the first part can be referred to as the source of the bits of the first part.

[0132] Exemplarily, the first part includes at least one code block, and each code block includes a type identification field, and the type identification field is used to indicate the type of any code block. The type of a code block corresponds to a bit source, so that for any code block, the type identification field of any code block can indicate the bit source of any code block. For code blocks obtained by different encoding methods, the type identification field of the code block can refer to the field used to identify the type in the code block obtained by the encoding method in the IEEE 802.3 standard. For example, when any code block is obtained based on any encoding method of 8B / 9B encoding, 64B / 65B encoding, or 80B / 81B encoding, the type identification field is the bit position of the highest bit of the code block. For another example, when any code block is obtained based on 64B / 66B encoding, the type identification field includes the first two bit positions of the code block.

[0133] In some embodiments, the type identification field indicates that the first portion is obtained by encoding the first data bit group of the first data signal, and the remaining portion of the first portion excluding the type identification field can be referred to as a data field. In some embodiments, the type identification field indicates that the first portion is obtained by encoding the first control bit group of the first control signal, or by encoding the first data bit group of the first data signal and the first control bit group of the first control signal, and the remaining portion of the first portion excluding the type identification field can be referred to as a control field.

[0134] Figure 12 is a schematic diagram of another plurality of first code blocks provided in an embodiment of the present application. As shown in Figure 12, for any first code block, the first portion of the first code block is obtained based on at least one of the first data bit group of the first data signal or the first control bit group of the first control signal, and the second portion of the first code block includes bits of the management signal. In the first code block shown in Figure 12, the first portion of the first code block is obtained based on 8B / 9B encoding, and the first portion includes 9 bits, the most significant bit position of these 9 bits is used as a type identification field. The second portion of the first code block includes 1 bit.

[0135] Figure 13 is a schematic diagram of another embodiment of multiple first code blocks provided by the present application. As shown in Figure 13, for any first code block, the first portion of any first code block is obtained based on at least one of the first data bit group of the first data signal or the first control bit group of the first control signal, and the second portion of any first code block includes bits of the management signal. In the first code block shown in Figure 13, the first portion of the first code block is obtained based on 64B / 65B encoding, and the first portion includes 65 bits. The most significant bit position of these 65 bits is used as a type identification field. The second portion of the first code block includes 1 bit.

[0136] The embodiment of the present application does not limit the manner in which the type identification field indicates the source of the bits of the first part. For example, if the type identification field includes 1 bit, the value of this bit is the first value, and the first part is obtained by encoding the first data bit group of the first data signal, that is, the first part includes the type identification field and the data field, and the content of the data field is obtained by encoding the first data bit group of the first data signal. If the value of this bit is the second value, the first part is obtained by encoding the first control bit group of the first control signal, or by encoding the first data bit group of the first data signal or the first control bit group of the first control signal. That is, the first part includes the type identification field and the control field. The content of the control field is obtained by encoding the first control bit group of the first control signal, or by encoding the first data bit group of the first data signal and the first control bit group of the first control signal. Exemplarily, the first value is 0 and the second value is 1.

[0137] In one possible implementation, the control field includes a first subfield and a second subfield. The content of the first subfield is obtained by encoding the first data bit group of the first data signal, and the content of the second subfield is obtained by encoding the first control bit group of the first control signal. Alternatively, the content of the first subfield and the content of the second subfield are both obtained by encoding the first control bit group of the first control signal, and the first bit used to obtain the content of the first subfield is different from the first bit used to obtain the content of the second subfield.

[0138] Figure 14 is a schematic diagram of another embodiment of the present application for multiple first code blocks. As shown in Figure 14, the type identification field of the first part of a first code block includes 1 bit, and the value of this bit is 0, indicating that the rest of the first part except the type identification field is a data field, and the data field includes 8 bits. The second part of this first code block includes a 1-bit management signal. The type identification field of the first part of another first code block includes 1 bit, and the value of this bit is 1, indicating that the rest of the first part except the type identification field is a control field, and the control field includes 8 bits. The control field includes a first subfield and a second subfield, and the first subfield and the second subfield each include 4 bits. The content of the second subfield can be indicated by the content of the first subfield. For example, the first subfield is a first control code, in which case the second subfield is an extended control code corresponding to the first control code; or the first subfield is a second control code, in which case the second subfield carries half a byte of data. When the second subfield is an extended control code, the content of the second subfield is obtained by encoding the first control bit group of the first control signal; when the second subfield carries half-byte data, the content of the second subfield is obtained by encoding the first data bit group of the first data signal.

[0139] The lengths of the first subfield and the second subfield shown in FIG14 are for example only. The lengths of the first subfield and the second subfield may also be other cases, for example, the first subfield includes 2 bits and the second subfield includes 6 bits. The second portion of the first code block shown in FIG14 includes 1 bit of a management signal. The second portions of both first code blocks are used to carry the management signal.

[0140] In one possible implementation, at least one of the first data bit group of the first data signal or the first control bit group of the first control signal is encoded to obtain a first portion of each first code block, and a second portion of each first code block is inserted between the plurality of first portions to obtain each first code block. The second portion includes, but is not limited to, at least one code block obtained based on the management signal or at least one bit of the unencoded management signal.

[0141] Figure 15 is a schematic diagram of another type of multiple first code blocks provided by an embodiment of the present application. As shown in Figure 15, at least one of the first data bit group of the first data signal or the first control bit group of the first control signal is encoded to obtain a coding sequence, and the first part of each first code block is obtained based on the coding sequence, and then the second part of each first code block is inserted to obtain each first code block. In an embodiment of the present application, a coding symbol can be a code block. Inserting the second part may cause an interruption in the coding sequence. After obtaining multiple first code blocks, the multiple code blocks used to identify the boundaries of the coding sequence may be located in the first part of the same first code block or in the first part of multiple first code blocks. Thus, when it is necessary to identify the boundaries of the coding sequence subsequently, the boundaries of the coding sequence can be identified based on the first part of the same first code block, or based on the first parts of multiple first code blocks.

[0142] In one possible implementation, the first portion of the first code block also carries an unencoded second data bit group of the first data signal and / or an unencoded second control bit group of the first control signal. For example, the first portion of the first code block carries at least one code block obtained by encoding the first data bit group of the first data signal and also carries an unencoded second data bit group. Alternatively, the first portion of the first code block carries at least one code block obtained by encoding the first control bit group of the first control signal and also carries an unencoded second control bit group. Alternatively, the first portion of the first code block carries at least one code block obtained by encoding the first control bit group of the first control signal and also carries an unencoded second data bit group. The second data bit group may include some or all bits of the first data signal excluding the first data bit group, and the second control bit group may include some or all bits of the first control signal excluding the first control bit group. The bits in the first data signal that serve as the first data bit group and the bits that serve as the second data bit group can be determined based on experience or actual needs. The bits in the first control signal that serve as the first control bit group and the bits that serve as the second control bit group can also be determined based on experience or actual needs, and are not limited in the present embodiments. Since the first part may include only the encoded code blocks, or include the encoded code blocks and unencoded bits, the manner in which the first part carries the first data signal or the first control signal is more flexible.

[0143] In some embodiments, the plurality of code blocks further include a management code block, and the management code block includes a management signal. That is, the management signal and the first data signal and / or the first control signal are carried in different code blocks. Exemplarily, the management code block includes a third control code and a management signal, and the third control code is used to indicate that the code block is a management code block. Figure 16 is a schematic diagram of a management code block provided in an embodiment of the present application. As shown in Figure 16, the third control code is 00011, and the bit position for carrying the management signal is represented by "O". The management code block may also be referred to as a PHY operation administration and maintenance (OAM) code block. The bit position for carrying the management signal may also be set at other bit positions based on experience or demand.

[0144] In some embodiments, the method is applied to a PHY functional module, and multiple code blocks also include a physical layer channel status indication, which includes but is not limited to part or all of COL and CRS. Figure 17 is a schematic diagram of a code block provided in an embodiment of the present application. As shown in Figure 17, the code block includes a fourth control code and a physical layer channel status indication, wherein the fourth control code is 00100, the physical layer channel status indication includes COL and CRS, and the code block also includes an error indication (error, ERR). The code block can also be used to carry management signals. For example, the bit position where "O" is located shown in Figure 17 is used to carry management signals. In other words, the physical layer signal status indication and management signals can be encoded into the same code block. The bit position for carrying management signals, ERR, COL and CRS can also be set at other bit positions based on experience or needs.

[0145] In some embodiments, the signal to be transmitted includes other signals other than the management signal, the first data signal, and the first control signal. When other signals are included, the other signals are encoded to obtain at least one code block. For example, if the signal to be transmitted includes a second control signal, the second control signal is encoded to obtain a second code block, wherein the second control signal is obtained based on the Ethernet frame start of the Ethernet frame. Thus, the multiple code blocks for encoding the signal to be transmitted include the second code block. Figure 18 is a schematic diagram of a second code block provided in an embodiment of the present application. As shown in Figure 18, the second code block includes the / J / code and / K / code obtained by 4B / 5B encoding in the IEEE 802.3 standard. The second code block can be used to indicate the start of stream delimiter (SSD).

[0146] If the signal to be transmitted includes a third control signal, the third control signal is encoded to obtain a third code block, wherein the third control signal is obtained based on the Ethernet frame end of the Ethernet frame. Thus, the multiple code blocks obtained by encoding the signal to be transmitted include the third code block. Figure 19 is a schematic diagram of a third code block provided in an embodiment of the present application. As shown in Figure 19, the third code block includes the / T / code and / R / code obtained by 4B / 5B encoding in the IEEE 802.3 standard, and the third code block can be used to indicate the end of stream delimiter (ESD). Since the multiple code blocks also include the second code block and the third code block, the types of the multiple code blocks are relatively rich, and the method for encoding the signal to be transmitted is relatively flexible.

[0147] Next, the obtained multiple code blocks are described by taking the first part of the first code block obtained based on 4B / 5B encoding as an example.

[0148] The 4B / 5B encoding method specified in the IEEE 802.3 standard encodes bits based on a half-byte width, and the encoded symbols obtained are used to represent data codes and control codes. The coding efficiency of 4B / 5B encoding is 4 / 5*100%=80%. Figure 20 is a schematic diagram of a first code block provided in an embodiment of the present application. Referring to Figure 20, the first code block includes a first part and a second part, wherein the first part includes a code block obtained based on 4B / 5B encoding and 4 unencoded bits, and the second part includes 1 bit. The bits used to obtain the code block can be the first data bit group of the first data signal or the first control bit group of the first control signal. In the case where the code block is obtained based on the first data bit group, the unencoded bits can be obtained based on the second data bit group. In the case where the code block is obtained based on the first control bit group, the unencoded bits can be obtained based on the second data bit group or the second control bit group.

[0149] Exemplarily, the code blocks included in the first part are obtained using the 4B / 5B encoding method specified in the IEEE 802.3 standard. The encoded code blocks can be data codes or control codes. In the first part, the specific type of the unencoded 4 bits can be indicated by the type of the code block in the first part. For example, if the code block is a data code, the unencoded 4 bits are the second data bit group of the first data signal. If the code block is a control code, the unencoded 4 bits are the second control bit group of the first control signal or the second data bit group of the first data signal. If the code block is a control code, the specific type of signal the second bit of the second part includes can be determined based on the type of the control code of the code block.

[0150] In some embodiments, the bits used to obtain the first portion can be indicated by TX_EN and TX_ER transmitted by the MII. For example, in Figure 20, TX_EN and TX_ER can indicate that the bits of the first half byte are the first data bit group of the first data signal or the first control bit group of the first control signal, and can also indicate that the bits of the second half byte are the second data bit group of the first data signal or the second control bit group of the first control signal. The bits of the first half byte are used to obtain the code blocks in the first portion, and the bits of the second half byte are used to obtain the uncoded bits in the first portion.

[0151] The bits of the management signal are used to obtain the second part of the first code block. As shown in Figure 20, the second part includes one bit of the management signal, which is marked as "0". As shown in Figure 20, the second part can be located between the code block included in the first part and the uncoded bits. The second part can also be located between the uncoded bits or before or after the first part. This embodiment of the application is not limited to this. The second part can also include four bits of the second half byte. These four bits can be the second data bit group of the first data signal or the second control bit group of the first control signal.

[0152] In one possible implementation, the 4 uncoded bits are the unchanged second data bit group or the second control bit group, or are the changed second data bit group or the second control bit group. The embodiment of the present application does not limit the manner in which the second data bit group and the second control bit group are changed. For example, the order of the bits in the second data bit group or the second control bit group is changed. In conjunction with the first code block shown in Figure 20, if the first part is obtained based on 8 bits of the first data signal, or based on 8 bits of the first control signal, or based on 4 bits of the first data signal and 4 bits of the first control signal, the coding efficiency of the first code block is 8 / 10*100%=80%.

[0153] In an embodiment of the present application, continuous / J / codes and / K / codes are used for stream synchronization and to indicate SSD. When continuous / J / codes and / K / codes are identified, it is determined that the Ethernet frame transmission starts. Continuous / T / codes and / R / codes are used to indicate ESD. Thus, when continuous / T / codes and / R / codes are identified, it is determined that the Ethernet frame transmission ends. Figure 21 is a transmission schematic diagram of an Ethernet frame provided by an embodiment of the present application. As shown in Figure 21, the Ethernet frame is represented by TX_EN, TX_ER, and TXD transmitted by the MII. The Ethernet frame includes the Ethernet frame start, the Ethernet frame end, and the portion of the Ethernet frame other than the Ethernet frame start and the Ethernet frame end. The signal representing the Ethernet frame start of the Ethernet frame is encoded to obtain a second code block, the second code block includes the / J / code and the / K / code, the signal representing the Ethernet frame end of the Ethernet frame is encoded to obtain a third code block, the third code block includes the / T / code and the / R / code, and the signal representing the portion of the Ethernet frame other than the Ethernet frame start and the Ethernet frame end is encoded to obtain multiple first code blocks. Exemplarily, if the number of bits included in the Ethernet frame is not an integer multiple of a byte, the first part of the last first code block in the multiple first code blocks is encoded based on the first control bit group of the first control signal, and as shown in Figure 21, the first part of the first code block also includes the second data bit group of the first data signal.

[0154] In one possible implementation, using consecutive / J / and / K / codes to represent SSD can prevent the content of the first code block from being identified as a / J / or / K / code. Consecutive / J / and / K / codes can also be represented as a / J / K / code. Using consecutive / T / and / R / codes to represent ESD can prevent the content of the first code block from being identified as an / R / code. Consecutive / T / and / R / codes can also be represented as a / T / R / code.

[0155] Figure 22 is a schematic diagram of a misidentification method provided by an embodiment of the present application. As shown in Figure 22, if the / J / code and / K / code are not used continuously, the content of the first code block may be identified as the / J / code and / K / code, causing the first code block to be considered the second code block. The content of the previous first code block may be identified as the / J / code, and the content of the next first code block may be identified as the / K / code, causing the content belonging to the two first code blocks to be considered as one second code block. If the / T / code and / R / code are not used continuously, the content of the first code block may be identified as the / T / code and / R / code, causing the first code block to be identified as the third code block. All three of the above situations will lead to misidentification of the first code block, that is, bits of the management signal are mistaken for bits of the first control signal. Therefore, in the embodiment of the present application, the / J / code and / K / code need to be used continuously, and the / T / code and / R / code need to be used continuously to prevent the first code block from being misidentified as the second or third code block. In this case, a code block including consecutive / J / codes and / K / codes is the second code block, and a code block including consecutive / T / codes and / R / codes is the third code block.

[0156] Exemplarily, the second code block includes 1100010001, where 11000 represents the / J / code and 10001 represents the / K / code, and the second code block is used to represent SSD. The third code block includes 0110100111, where 01101 represents the / T / code and 00111 represents the / R / code, and the third code block is used to represent ESD. The contents of the first code block may be shown in Table 1 below, wherein the first code block includes a first sub-block and a second sub-block, the first sub-block including the 5 bits encoded in the first part, and the second sub-block including the 4 unencoded bits in the second part and the first part. The value of the position represented by O can be 1, and the value of the position represented by x can be 0 or 1.

[0157] Table 1

[0158] In some embodiments, if the last five bits of the R code are the portion of Oxxxx other than Ox1xx, the first code block is a control-type code block and indicates a reset extend. If the last five bits of the H code are O ERR 1 CRS COL, the first code block is a control-type code block and indicates a physical layer channel state indication. In this case, the first code block may be referred to as an H.sig code. If the last five bits of the S code are O1110, the first code block is a control-type code block and indicates PHY-level collision avoidance (PLCA) BEACON (a signal type). If the last five bits of the S code are O1101, the first code block is a control-type code block and indicates PLCA COMMIT (a signal type). If the last five bits of the S code are the portion of Oxxxx other than O1110 and O1101, the first code block is a control-type code block and indicates a set extend. In cases other than those shown in Table 1, the first code block is a control type code block and is reserved. Exemplarily, the reserved first code block is used to expand new Ethernet functions, which is not limited in this embodiment of the present application.

[0159] S802: Send multiple code blocks through a serial channel.

[0160] This serial channel may be referred to as a first serial channel. In one possible implementation, the serial channel is used to connect the MAC layer and the PHY. For example, the serial channel is used to connect the reconciliation sublayer (RS) and the physical coding sublayer (PCS). In another example, the serial channel is used to connect the RS and the physical layer signaling sublayer (PLS). Exemplarily, the serial channel is used to implement data transmission between the MAC sublayer and the PHY, or to implement data transmission between the STA and the PHY. This serial channel may also be referred to as a serial channel implemented based on the MII. Exemplarily, the serial channel is implemented by a pin or a group of pins. Thus, if the serial channel is implemented by a single pin, the pin is used to transmit multiple code blocks. If the serial channel is implemented by multiple pins, differential signals transmitted via multiple pins can be first obtained based on the multiple code blocks, and then the differential signals can be transmitted via the multiple pins to implement the transmission of multiple code blocks via a single serial channel. Thus, by using a single serial channel to transmit multiple code blocks, fewer pins are required to implement the serial channel, and the transmission of data signals, control signals, and management signals can be implemented based on the serial channel.

[0161] FIG23 is a schematic diagram of a process for transmitting multiple code blocks according to an embodiment of the present application. This method can be applied to a MAC functional module or a PHY functional module. If the method is applied to a MAC functional module, the method can transmit multiple code blocks to the PHY functional module via a serial channel. This transmission process can correspond to the TX serial transmission shown in FIG23. If the method is applied to a PHY functional module, the method can transmit multiple code blocks to the MAC functional module via a serial channel. This transmission process can correspond to the RX serial transmission shown in FIG23.

[0162] In an embodiment of the present application, when transmitting multiple code blocks via a serial channel, the obtained multiple code blocks can be directly transmitted, or the multiple code blocks can be processed first and then transmitted. The processing performed on the multiple code blocks includes at least one of encoding or scrambling, and the encoding includes non-return-to-zero-invert (NRZI) encoding or non-return-to-zero (NRZ) encoding.

[0163] Figure 24 is a schematic diagram of a process for transmitting a first code block provided by an embodiment of the present application. As shown in Figure 24, the signal to be transmitted includes a management signal, a first data signal, and a first control signal transmitted in parallel by MII. The signal to be transmitted is encoded to obtain a first code block. Among them, the first part of the first code block is obtained by encoding at least one of the four first bits of the first data signal or the four first bits of the first control signal, the first part also includes the four second bits of the first data signal or the four second bits of the first control signal, the second part includes one bit of the management signal, and the first code block includes 10 bits. After obtaining the first code block, the first code block is transmitted serially via MII. Moreover, as shown in Figure 24, when transmitting the first code block, multiple bits of the first code block can be transmitted in order from high to low bit position. In some embodiments, multiple bits of the first code block can also be transmitted in order from low to high bit position.

[0164] Figure 25 is a schematic diagram of another process for transmitting a first code block provided by an embodiment of the present application. As shown in Figure 25, the bit positions corresponding to the first parts of multiple first code blocks serve as data and control channels, and the bit positions corresponding to the second parts of multiple first code blocks serve as management channels. As shown in Figure 25, the bits of management signals included in the multiple second parts can be used to form MDIO signals. Figure 26 is a schematic diagram of a process for transmitting a management code block provided by an embodiment of the present application. As shown in Figure 26, when there is no need to transmit a data signal, that is, when the data channel is idle, a management code block is encoded, and the management code block can include multiple bits of the management signal. Referring to Figure 26, each management code block includes four bits of the management signal, and the four bits of the management signal are represented by "0". In this case, the transmission efficiency of the management signal is higher than that of the second part of the first code block including only one bit of the management signal.

[0165] FIG27 is a schematic diagram of another code block provided by an embodiment of the present application. For example, when a code block includes a physical layer status indication, the code block may be as shown in FIG27 , and the code block may be referred to as an H.sig code block, wherein x shown in FIG27 may be 0 or 1. FIG28 is a schematic diagram of a process for transmitting an H.sig code block provided by an embodiment of the present application. As shown in FIG28 , when the method is applied to a PHY function module and multiple code blocks are transmitted to a MAC function module, if the MAC function module is in a transmitting mode, that is, the MAC function module transmits a code block to the PHY function module, the PHY function module may transmit the H.sig code block to the MAC function module via the receiving channel of the MAC function module. The transmitting channel of the MAC function module may be a channel established by the MAC function module based on the MII for transmitting code blocks to the PHY function module, and the receiving channel of the MAC function module may be a channel established by the MAC function module based on the MII for receiving code blocks transmitted by the PHY function module.

[0166] If this method is applied to the PHY functional module and multiple code blocks are transmitted to the MAC functional module, if the MAC functional module is in receiving mode, that is, the MAC functional module receives the code blocks sent by the PHY functional module, the PHY functional module can transmit the H.sig code blocks to the MAC functional module through the receiving channel of the MAC functional module.

[0167] Figure 29 is a schematic diagram of another process for transmitting an H.sig code block provided by an embodiment of the present application. As shown in Figure 29, the MAC function module receives data through a receiving channel, and the data is obtained based on an Ethernet frame. For example, the data obtained based on the Ethernet frame includes / data / shown in Figure 29. As shown in Figure 29, the PHY function module also transmits the / J / K / code for indicating SSD and the / T / R / code for indicating ESD to the MAC function module. When there is no abnormality in the data, the MAC function module can obtain a physical layer status indication based on the received Ethernet frame. The MAC function module can also receive an H.sig code block sent by the PHY function module through a receiving channel. The H.sig code block includes a physical layer status indication. The physical layer status indication included in the H.sig code block can indicate virtual CRS occupancy.

[0168] When this method is applied to the PHY functional module and transmits code blocks to the MAC functional module, if the MAC functional module is in receive mode and the data sent by the PHY functional module to the MAC functional module is abnormal, the H.sig code block can be used to replace the abnormal data for transmission. Figure 30 is another schematic diagram of the process of transmitting an H.sig code block provided by an embodiment of the present application. As shown in Figure 30, the MAC functional module receives data through a receive channel, and the data is obtained based on an Ethernet frame. For example, the data obtained based on the Ethernet frame includes / data / shown in Figure 30. As shown in Figure 30, the PHY functional module also transmits the / J / K / code used to indicate SSD to the MAC functional module. The MAC functional module also receives an H.sig code block through the receive channel. The H.sig code block includes a physical layer status indication, and the H.sig code block is obtained by replacing the abnormal data. As shown in Figure 30, the PHY functional module can also transmit an idle code block to the MAC functional module. The idle code block is the first code block indicating idleness. For example, in Figures 28 to 30 above, the process of the PHY functional module transmitting the H.sig code block is implemented in a half-duplex scenario.

[0169] The above description is made by taking the example of obtaining the first part of the first code block based on 4B / 5Bb encoding. Next, the description is made by taking the example of obtaining the first part of the first code block based on 64B / 65B encoding.

[0170] Figure 31 is a schematic diagram of another first code block provided in an embodiment of the present application. Referring to Figure 31, since the bit width of the TXD of the MII is 4 bits, it is necessary to obtain the first part of the first code block based on the bit encoding of the TXD of 16 cycles, and the second part of the first code block includes one bit of the management signal. Figure 32 is a schematic diagram of another process for transmitting multiple first code blocks provided in an embodiment of the present application. As shown in Figure 32, management signals can be transmitted by transmitting the second parts of multiple first code blocks, and the management signals include MDIO signals.

[0171] For example, in the 64B / 65B encoding of the IEEE 802.3 standard, the frame start position of an Ethernet frame is indicated by the / S / code, and the / S / code can only be located at the first and fifth bytes of a 64-bit block. In the method provided in the embodiment of the present application, when transmitting an Ethernet frame via the MII, if 64B / 65B encoding is used to obtain the first part of the first code block, the frame start position needs to be able to be located at any byte within the 64 bits of the first part. Therefore, it is necessary to add a code table that can indicate that the / S / code is located at any byte to the encoding table of the IEEE 802.3 standard. Since the 64B / 65B encoding table of the IEEE 802.3 standard already includes code tables for S0 and S4, the method provided in the embodiment of the present application can expand code tables indicating S1, S2, and S3 based on S0, and expand code tables indicating S5, S6, and S7 based on S4. FIG33 is a schematic diagram of a newly added code table provided in an embodiment of the present application. As shown in FIG33 , the type (type) indicating the S0 code is 0x78. By modifying the value of the second hexadecimal digit, i.e., 0x7i, where i is a variable value, the type value is set to 0x7i1, 0x7i2, 0x7i3, indicating S1, S2, and S3, respectively. The type indicating the S4 code is 0x33. By modifying the value of the second hexadecimal digit, i.e., 0x3i, where i is a variable value, the type value is set to 0x3i5, 0x3i6, 0x3i7, indicating S5, S6, and S7, respectively. Wherein, i1 to i7 all represent the value of i. For other unexplained parts in FIG33, please refer to the 64B / 65B coding table in the IEEE 802.3 standard, which will not be further described here.

[0172] Exemplarily, the bit width of the control code / C / in the 64B / 65B encoding of the IEEE 802.3 standard is 7 bits. The method provided in the embodiment of the present application can expand the first code block representing half-byte data, the first code block representing the physical layer channel state indication, etc. on the basis of the control code of the IEEE 802.3 standard. The first code block representing half-byte data can be called a half-byte representation code, and the first code block representing the physical layer channel state indication can be called a physical layer signal indicator code. Table 2 is a control code table of 64B / 65B encoding in the IEEE 802.3 standard. The half-byte representation code can be obtained based on the reserved code expansion in the control code table. As shown in Table 2, the reserved code includes reserved code 0 to reserved code 5. Taking the half-byte representation code obtained based on reserved code 5 as an example, the half-byte representation code can be 0x7h, where 0x7 represents the control code type, and the h part is 4 bits, representing the half-byte data. The physical layer signal indicator code can be derived by extending the error code 0x1E in Table 2. For example, the physical layer signal indicator code is 0x1u, where 0x1 represents the control code pattern and the u portion is 4 bits, indicating the physical layer channel status indication. The physical layer indication code can also be derived by extending the reserved codes in Table 2, which will not be further described here.

[0173] Table 2

[0174] FIG34 is a schematic diagram of a physical layer signal indicator code provided in an embodiment of the present application. Referring to FIG34 , the value of x can be 0 or 1. For example, referring to FIG34 , where a bit position of 0 indicates valid and 1 indicates invalid, if both COL and CRS are invalid and x is 1, the physical layer channel indicator code is the same as the original error code.

[0175] In one possible implementation, the management signal includes a first MDIO signal corresponding to a read operation, and the method further includes: receiving a second MDIO signal, the second MDIO signal being used to provide feedback on the read operation. Exemplarily, the serial channel for receiving the second MDIO signal is different from the serial channel for transmitting the multiple code blocks. That is, the first MDIO signal corresponding to the read operation and the second MDIO signal corresponding to the read feedback operation are transmitted via two serial channels. Exemplarily, the serial channel for transmitting the second MDIO signal is also used to connect the MAC layer and the PHY, and the serial channel can be implemented by one pin or a group of pins. The serial channel for receiving the second MDIO signal can be referred to as a second serial channel. The second MDIO signal can also be encoded into a code block, and then the second MDIO signal is transmitted by transmitting the code block. For example, the method is applied to a MAC functional module, and the MAC functional module receives a code block transmitted by the PHY functional module, and the code block includes the second MDIO signal. For another example, the method is applied to a PHY functional module, and the PHY functional module receives a code block transmitted by the MAC functional module, and the code block includes the second MDIO signal. The method of encoding to obtain the code block including the second MDIO signal is similar in principle to the method of encoding to obtain the code block including the first MDIO signal, and is not described in detail here.

[0176] The above describes the information processing method provided by the embodiments of the present application from the perspective of encoding. Next, the method will be described from the perspective of decoding. The method can be shown in Figure 35. This method can be applied to the MAC functional module or PHY functional module shown in Figure 7, and the MAC functional module and the PHY functional module can be located on the same or different chips. As shown in Figure 35, the method includes but is not limited to S3501 and S3502.

[0177] S3501 , receiving a plurality of code blocks through a serial channel, where the plurality of code blocks include a first data signal and / or a first control signal, and the plurality of code blocks also include a management signal.

[0178] In one possible implementation, a serial channel is used to connect the MAC layer and the PHY, and the serial channel can be referred to as a channel implemented based on the MII. Exemplarily, the serial channel is implemented by one pin or by a group of pins. Thus, if the serial channel is implemented by one pin, the pin is used to receive multiple code blocks. If the serial channel is implemented by multiple pins, differential signals obtained based on multiple code blocks can be received through multiple pins, and multiple code blocks can be obtained based on the differential signals. Thus, by using one serial channel to receive multiple code blocks, the serial channel can be implemented by setting fewer pins, and then the transmission of data signals, control signals, and management signals can be implemented based on the serial channel. For content related to the encoding of multiple code blocks, please refer to the content in the encoding method, which will not be repeated here.

[0179] S3502: Acquire a management signal, a first data signal, and / or a first control signal from multiple code blocks.

[0180] For example, referring again to FIG. 24 above, after receiving multiple first code blocks via the MII, the multiple first code blocks are decoded to obtain a signal to be transmitted, that is, a management signal, a first data signal, and / or a first control signal. Each first code block includes 10 bits. Exemplarily, if a first code block among the multiple code blocks includes a first portion and a second portion, the first portion includes the first data signal and / or the first control signal, and the second portion includes the management signal; obtaining the management signal and the first data signal and / or the first control signal from the multiple code blocks includes: obtaining the first data signal and / or the first control signal from the first portion of the first code block; and obtaining the management signal from the second portion of the first code block. For example, if the first portion includes at least one code block obtained by encoding a first data bit group of the first data signal and / or a first control bit group of the first control signal, the at least one first code block is decoded according to the encoding method of the at least one code block to obtain the first data bit group of the first data signal and / or the first control bit group of the first control signal. If the first part further includes the second data bit group of the first data signal and / or the second control bit group of the first control signal, the second data bit group of the first data signal and / or the second control bit group of the first control signal are obtained from the first part. The bits of the management signal are obtained from the second part of the first code block.

[0181] Exemplarily, if there are multiple first code blocks, the second portion appears periodically in the multiple first code blocks; obtaining the management signal from the second portion of the first code block includes: obtaining the periodically appearing second portion from the multiple first code blocks; and obtaining the management signal from the second portion. Exemplarily, the multiple code blocks include a management code block, and the management code block includes a management signal; obtaining the management signal from the multiple code blocks includes: obtaining the management signal from the management code block. For example, the management signal is obtained from the management code block in a manner based on the management signal. Taking the management code block shown in Figure 16 as an example, the bit of the management signal is obtained from the position indicated by "O" in the management code block.

[0182] In one possible implementation, the method is applied to a MAC functional module, wherein the multiple code blocks also include a physical layer channel state indicator. Thus, the method further includes: obtaining the physical layer channel state indicator from the multiple code blocks. For example, the physical layer channel state indicator is obtained from the code block by obtaining a code block including the physical layer channel state indicator based on the physical layer channel state indicator. Taking the code block shown in FIG. 17 as an example, the physical layer channel state indicator is obtained from the locations indicated by "COL" and "CRS."

[0183] In one possible implementation, the management signal includes a first MDIO signal corresponding to a read operation. The method further includes sending a second MDIO signal, the second MDIO signal being used to provide feedback regarding the read operation. Exemplarily, the serial channel for sending the second MDIO signal is different from the serial channel for receiving the multiple code blocks. The method for sending the second MDIO signal is similar in principle to the method for sending the first MDIO signal. For details regarding the first MDIO signal in S801 and S802, please refer to the details here.

[0184] Exemplarily, if the multiple code blocks further include a second code block, a second control signal is obtained based on the second code block, and the second control signal is used to obtain an Ethernet frame start of the Ethernet frame. Exemplarily, if the multiple code blocks further include a third code block, a third control signal is obtained based on the third code block, and the third control signal is used to obtain an Ethernet frame end of the Ethernet frame.

[0185] In some embodiments, if the method is applied to a PHY functional module, obtaining a management signal, a first data signal, and / or a first control signal from a plurality of code blocks includes: inputting the plurality of code blocks into a coordination sublayer (RS), and executing in the RS the acquisition of the management signal, the first data signal, and / or the first control signal from the plurality of code blocks. By executing in the RS the acquisition of the management signal, the first data signal, and / or the first control signal from the plurality of code blocks, the method can directly convert the management signal, the first data signal, and / or the first control signal into a signal that can be processed by a PLS in the RS, without first converting the management signal, the first data signal, and / or the first control signal into a parallel signal for MII transmission in the IEEE 802.3 standard, and then converting the parallel signal into a signal for PLS processing, thereby achieving a higher efficiency in obtaining the signal processed by the PLS.

[0186] Figure 36 is a schematic diagram of a process for inputting multiple code blocks into an RS according to an embodiment of the present application. As shown in Figure 36, multiple code blocks received through a serial channel enter the RS, and the RS executes the acquisition of management signals, first data signals and / or first control signals from multiple code blocks. The RS also converts the management signal, the first data signal and / or the first control signal into a signal processed by PLS. For example, the signal processed by PLS includes the PLS service primitives shown in Figure 36. Multiple code blocks include code blocks of control type and code blocks of data type, and the type of the code block is determined according to the content of the code block obtained by encoding. The code block of control type can be called a control code block, and the code block represented by C shown in Figure 36 can be a control code block; the code block of data type can be called a data code block, and the code block represented by D shown in Figure 36 can be a data code block.

[0187] As shown in Figure 36, the RS can separate the control code block and the data code block, and perform operations on the separated data code block and the control code block. The performed operations are shown in C1 and C2 in Figure 36. The embodiment of the present application does not limit the type of operation. PLS service primitives include but are not limited to PLS control request (PLS control request), PLS data request (PLS data request), PLS signal indication (PLS signal indication), PLS carrier indication (PLS carrier indication), PLS data indication (PLS data indication) and PLS control indication (PLS control indication) shown in Figure 36.

[0188] In one possible implementation, after receiving multiple code blocks, it is necessary to identify the boundaries of the multiple code blocks and synchronize them. Synchronizing the multiple code blocks includes, but is not limited to, synchronizing the management channel and the data channel. Synchronizing the management channel ensures the interaction of management signals, while synchronizing the data channel ensures the interaction of data signals and control signals.

[0189] FIG37 is a schematic diagram of a management channel synchronization process provided by an embodiment of the present application. Referring to FIG37 , when the first portion of a first code block is derived based on the first control bit group and the second control bit group of a first control signal, the first portion of the first code block includes an / I / code and a second control bit group. The / I / code is also known as an idle code, and the / I / code is uniquely identifiable. When the management signal does not include an MDIO signal, the value of the management signal bit is 1. When the management signal includes an MDIO signal and transmission of the MDIO signal begins, multiple bits of the management signal will transition from "101," which can indicate a start field. Thus, by identifying the start field, management channel synchronization can be achieved. For other details of the management signal shown in FIG37 , please refer to the relevant descriptions of FIG9 and FIG10 above and will not be repeated here. Furthermore, a0 to a4 shown in FIG37 are only used to illustrate the values ​​of the physical layer address field, and r0 to r4 are only used to illustrate the values ​​of the register address field and are not used to limit the values ​​of these two fields.

[0190] In one possible implementation, data channel synchronization is achieved by identifying the SSD of the Ethernet frame. That is, by identifying consecutive / J / codes and / K / codes, it can be determined that the Ethernet frame starts to be transmitted, thereby achieving data channel synchronization. Figure 38 is a schematic diagram of the process of data channel synchronization provided by an embodiment of the present application. As shown in Figure 38, a first code block is first identified. The first code block is a control type code block and indicates idle. For example, the first code block shown in Figure 38 is 11111x1111, and the x shown in Figure 38 can represent 0 or 1. Then a second code block is identified. The second code block includes a / J / code and a / K / code. Therefore, after identifying the second code block, it can be determined that the Ethernet frame starts to be transmitted, thereby achieving data channel synchronization. In one possible implementation, when achieving data channel synchronization, since the position of the management channel bit in the first code block is fixed, when achieving data channel synchronization, the position of the management channel bit can be directly located, so that by identifying the start field of the management signal, the management channel synchronization can be achieved.

[0191] In the signal processing method provided in the embodiments of the present application, because the multiple code blocks include management signals, first data signals, and / or first control signals, the multiple code blocks can include a wide range of signal types. When the multiple code blocks are transmitted via a single serial channel, only a relatively small number of pins are required to implement the serial channel, thereby enabling transmission of data signals, control signals, and management signals over the serial channel.

[0192] The present application also provides a signal processing device. Figure 39 is a schematic diagram of the structure of a signal processing device provided in an embodiment of the present application. The device is applied to a MAC functional module or a PHY functional module. Based on the multiple modules shown in Figure 39, the device can perform all or part of the operations in the signal processing method shown in Figure 7. It should be understood that the device may include more additional modules than the modules shown or omit some of the modules shown, and the present application does not limit this. As shown in Figure 39, the device includes an encoding module 3901 and a transmitting module 3902.

[0193] The encoding module 3901 is configured to encode a signal to be transmitted to obtain multiple code blocks, where the multiple code blocks include a first data signal and / or a first control signal, and also include a management signal. The transmitting module 3902 is configured to transmit the multiple code blocks via a serial channel. This serial channel may be referred to as a first serial channel.

[0194] In some embodiments, a first code block among the plurality of code blocks includes a first portion and a second portion, the first portion includes a first data signal and / or a first control signal, and the second portion includes a management signal.

[0195] In some embodiments, there are multiple first code blocks, and the management signal appears periodically in the multiple first code blocks.

[0196] In some embodiments, the plurality of code blocks includes a management code block, and the management code block includes a management signal.

[0197] In some embodiments, a serial channel is used to connect the MAC layer and the PHY.

[0198] In some embodiments, the serial channel is implemented by one pin or by a group of pins.

[0199] In some embodiments, the serial channel is implemented based on MII.

[0200] In some embodiments, the signal to be transmitted is associated with an Ethernet frame.

[0201] In some embodiments, the signal to be transmitted being related to the Ethernet frame includes at least one of the following: the signal to be transmitted is generated based on the Ethernet frame, or the signal to be transmitted is used to manage transmission of the Ethernet frame.

[0202] In some embodiments, the management signal includes a first MDIO signal corresponding to a read operation; the apparatus further includes: a receiving module configured to receive a second MDIO signal, where the second MDIO signal is used to provide feedback on the read operation.

[0203] In some embodiments, the serial channel for receiving the second MDIO signal is different from the serial channel for sending the plurality of code blocks, wherein the serial channel for receiving the second MDIO signal may be referred to as the second serial channel.

[0204] In some embodiments, if the apparatus is applied to a PHY functional module, the plurality of code blocks further include a physical layer channel status indicator.

[0205] In the apparatus provided in the embodiments of the present application, because the multiple code blocks include management signals, first data signals, and / or first control signals, the multiple code blocks can include a wide range of signal types. When the multiple code blocks are transmitted via a single serial channel, only a relatively small number of pins are required to implement the serial channel, thereby enabling transmission of data signals, control signals, and management signals over the serial channel.

[0206] The present application also provides another signal processing device. Figure 40 is a schematic diagram of the structure of another signal processing device provided by an embodiment of the present application. This device is applied to a MAC functional module or a PHY functional module. Based on the multiple modules shown in Figure 40, the device can perform all or part of the operations in the signal processing method shown in Figure 35. It should be understood that the device may include more additional modules than those shown or omit some of the modules shown, and this embodiment of the present application is not limited to this. As shown in Figure 40, the device includes a receiving module 4001 and an acquisition module 4002.

[0207] A receiving module 4001 is configured to receive multiple code blocks via a serial channel, wherein the multiple code blocks include a first data signal and / or a first control signal, and the multiple code blocks also include a management signal. An acquiring module 4002 is configured to acquire the management signal, the first data signal, and / or the first control signal from the multiple code blocks. The serial channel may be referred to as a first serial channel.

[0208] In some embodiments, the first code block among multiple code blocks includes a first part and a second part, the first part includes a first data signal and / or a first control signal, and the second part includes a management signal; the acquisition module 4002 is used to obtain the first data signal and / or the first control signal from the first part of the first code block; and obtain the management signal from the second part of the first code block.

[0209] In some embodiments, there are multiple first code blocks, and the second part appears periodically in the multiple first code blocks; the acquisition module 4002 is used to acquire the periodically appearing second part from the multiple first code blocks; and acquire the management signal from the second part.

[0210] In some embodiments, the multiple code blocks include a management code block, and the management code block includes a management signal; the acquisition module 4002 is used to acquire the management signal from the management code block.

[0211] In some embodiments, a serial channel is used to connect the MAC layer and the PHY.

[0212] In some embodiments, the serial channel is implemented by one pin or by a group of pins.

[0213] In some embodiments, the serial channel is implemented based on MII.

[0214] In some embodiments, the management signal includes a first MDIO signal corresponding to a read operation; the apparatus further includes: a sending module configured to send a second MDIO signal, where the second MDIO signal is used to provide feedback on the read operation.

[0215] In some embodiments, the serial channel for sending the second MDIO signal is different from the serial channel for receiving the plurality of code blocks, wherein the serial channel for receiving the second MDIO signal may be referred to as the second serial channel.

[0216] In some embodiments, if the device is applied to a MAC functional module, the multiple code blocks further include a physical layer channel state indication; and the acquisition module 4002 is further configured to acquire the physical layer channel state indication from the multiple code blocks.

[0217] In the apparatus provided in the embodiments of the present application, because the multiple code blocks include management signals, first data signals, and / or first control signals, the multiple code blocks can include a wide range of signal types. When the multiple code blocks are transmitted via a single serial channel, only a relatively small number of pins are required to implement the serial channel, thereby enabling transmission of data signals, control signals, and management signals over the serial channel.

[0218] It should be understood that the devices provided in Figures 39 and 40 above are only exemplified by the division of the above functional modules when implementing their functions. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the devices and method embodiments provided in the above embodiments belong to the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0219] Referring to FIG. 41 , FIG. 41 is a schematic diagram illustrating the structure of a computer system according to an embodiment of the present application. For example, as shown in FIG. 41 , the computer system is computer system 2000. Computer system 2000 may be a network device, a routing device, or a switching device. Computer system 2000 shown in FIG. 41 is configured to perform the operations described in the signal processing method shown in FIG. 8 or FIG. 35 . Computer system 2000 is, for example, a server, and may be implemented using a general bus architecture.

[0220] As shown in FIG. 41 , the computer system 2000 includes at least one processor 2001 , a memory 2003 , and at least one communication interface 2004 .

[0221] The processor 2001 is a central processing unit (CPU), a digital signal processor (DSP), a network processor (NP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor or one or more integrated circuits for implementing the method provided in the embodiments of the present application. For example, the processor 2001 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination of the above three. The processor 2001 can be a combination of various logic blocks, modules and circuits that implement or execute the contents disclosed in conjunction with the embodiments of the present application, or it can be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and the like.

[0222] Optionally, computer system 2000 also includes a bus. The bus is used to transmit information between the components of computer system 2000. The bus may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, for example. Buses can be classified as address buses, data buses, control buses, and the like. For ease of illustration, FIG41 shows only one thick line, but this does not imply that there is only one bus or only one type of bus.

[0223] The memory 2003 is, for example, a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, an optical disc storage (including a compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 2003 is, for example, independent and connected to the processor 2001 via a bus. The memory 2003 can also be integrated with the processor 2001.

[0224] The communication interface 2004 uses any transceiver-like device to communicate with other devices or communication networks. The communication network can be Ethernet, a radio access network (RAN), or a wireless local area network (WLAN). The communication interface 2004 can include a wired communication interface or a wireless communication interface. Specifically, the communication interface 2004 can be an Ethernet interface, a fast Ethernet (FE) interface, a gigabit Ethernet (GE) interface, an asynchronous transfer mode (ATM) interface, a WLAN interface, a cellular network communication interface, or a combination thereof. The Ethernet interface can be an optical interface, an electrical interface, or a combination thereof. In the embodiment of the present application, the communication interface 2004 can be used for the computer system 2000 to communicate with other devices.

[0225] In a specific implementation, as an embodiment, the processor 2001 may include one or more CPUs, such as CPU0 and CPU1 shown in FIG41 . Each of these processors may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. The processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0226] In a specific implementation, as an embodiment, the computer system 2000 may include multiple processors, such as processor 2001 and processor 2005 shown in FIG41 . Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). A processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0227] In a specific implementation, as an embodiment, the computer system 2000 may further include an output device and an input device. The output device communicates with the processor 2001 and can display information in a variety of ways. For example, the output device can be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. The input device communicates with the processor 2001 and can receive user input in a variety of ways. For example, the input device can be a mouse, a keyboard, a touch screen device, or a sensor device.

[0228] In some embodiments, the memory 2003 is used to store program code 2010, and the processor 2001 can execute the program code 2010 stored in the memory 2003. The program code 2010 may include one or more software modules. Alternatively, the processor 2001 itself can also store program code or instructions.

[0229] In a specific embodiment, the computer system 2000 of the embodiment of the present application may include the MAC functional module and / or PHY functional module in the above-mentioned various method embodiments, and the MAC functional module and / or PHY functional module may be implemented by the processor 2001 in the computer system 2000.

[0230] The computer system 2000 may also correspond to the apparatus shown in FIG. 39 and FIG. 40 , and each functional module in the apparatus shown in FIG. 39 or FIG. 40 may be implemented by a circuit in the processor 2000 .

[0231] 8 and 35 are implemented by hardware integrated logic circuits in the processor of the computer system 2000. The steps of the method disclosed in the embodiments of the present application can be directly implemented by the hardware processor.

[0232] FIG42 is a schematic diagram of the structure of another computer system provided in an embodiment of the present application. The computer system is used to perform the operations in the signal processing methods shown in FIG8 and FIG35 above. Exemplarily, the computer system is a server, and servers may vary significantly due to different configurations or performance. The computer system may include one or more processors 4201, which are used to implement the MAC functional module and / or PHY functional module in the method embodiment. As shown in FIG42, the computer system may also include one or more memories 4202, wherein the one or more memories 4202 store at least one computer program, and the at least one computer program is loaded and executed by the one or more processors 4201. Exemplarily, processor 4201 is a CPU. Of course, the computer system may also have components such as a wired or wireless network interface, a keyboard, and input / output interfaces for input and output. The computer system may also include other components for implementing device functions, which are not described in detail here.

[0233] An embodiment of the present application also provides a communication device, which includes: a transceiver module for performing operations related to reception and / or transmission in the signal processing method shown in Figure 8; a processing module for performing other operations in the signal processing method shown in Figure 8 except for operations related to reception and / or transmission. An embodiment of the present application also provides another communication device, which includes: a transceiver module for performing operations related to reception and / or transmission in the signal processing method shown in Figure 35; a processing module for performing other operations in the signal processing method shown in Figure 35 except for operations related to reception and / or transmission. An embodiment of the present application provides another communication device, which includes: a MAC layer circuit, the MAC layer circuit is used to perform the signal processing method shown in Figure 8 and / or Figure 35. An embodiment of the present application provides another communication device, which includes: a PHY circuit, the PHY circuit is used to perform the signal processing method shown in Figure 8 and / or Figure 35.

[0234] The various signal processing devices and various communication devices mentioned above may all be chips or communication devices.

[0235] An embodiment of the present application provides a chip including: a MAC layer circuit, the MAC layer circuit being configured to execute the signal processing method shown in FIG8 and / or FIG35. An embodiment of the present application also provides another chip including: a PHY circuit, the PHY circuit being configured to execute the signal processing method shown in FIG8 and / or FIG35.

[0236] An embodiment of the present application further provides a communication system, comprising a MAC layer circuit and a PHY circuit; the MAC layer circuit is configured to execute the signal processing method shown in FIG8 , and the PHY circuit is configured to execute the signal processing method shown in FIG35 ; alternatively, the PHY circuit is configured to execute the signal processing method shown in FIG8 , and the MAC layer circuit is configured to execute the signal processing method shown in FIG35 . This communication system may be implemented in a chip or a communication device.

[0237] It should be understood that the processor may be a CPU, or other general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc. It is worth noting that the processor may be a processor supporting the Advanced Reduced Instruction Set Machine (ARM) architecture.

[0238] Furthermore, in an optional embodiment, if one or more of the aforementioned computer system, communication device, chip, or communication system further includes memory, the memory may include read-only memory and random access memory, and provide instructions and data to the processor. The memory may also include non-volatile random access memory. For example, the memory may also store device type information.

[0239] The memory may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a ROM, a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a RAM, which is used as an external cache. By way of example but not limitation, many forms of RAM are available. For example, static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0240] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When software is used for implementation, it can be implemented in whole or in part in the form of a computer program or computer program product. The computer program or computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function according to the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center to another website, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a digital versatile disc (DVD)), or a semiconductor medium (eg, a solid state disk (SSD)).

[0241] To clearly illustrate the interchangeability of hardware and software, the above description has generally described the steps and components of each embodiment according to their functions. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0242] The computer program code for realizing the method for the embodiment of the application can be written in one or more programming languages. These computer program codes can be provided to the processor of the storage device of general-purpose computer, special-purpose computer or other programmable annotation content, so that the program code, when being executed by the storage device of computer or other programmable annotation content, causes the function / operation specified in the flow chart and / or block diagram to be implemented. The program code can be executed completely on the computer, partially on the computer, as an independent software package, partially on the computer and partially on a remote computer or completely on a remote computer or server.

[0243] In the context of the embodiments of the present application, computer program code or related data may be carried by any suitable carrier to enable a device, apparatus, or processor to perform the various processes and operations described above. Examples of carriers include signals, computer-readable media, and the like. Examples of signals may include electrical, optical, radio, acoustic, or other forms of propagated signals, such as carrier waves, infrared signals, and the like.

[0244] Those skilled in the art will clearly understand that, for the sake of convenience and brevity of description, the specific working processes of the above-described systems, devices, and modules can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0245] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the modules is merely a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, or can be electrical, mechanical or other forms of connection.

[0246] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0247] In addition, the functional modules in the various embodiments of the present application may be integrated into a processing module, or each module may exist physically separately, or two or more modules may be integrated into a single module. The above-mentioned integrated modules may be implemented in the form of hardware or software functional modules.

[0248] In this application, the terms "first", "second", etc. are used to distinguish between identical or similar items with substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is there a limit on quantity and execution order. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the various examples, a first graphic may be referred to as a second graphic, and similarly, a second graphic may be referred to as a first graphic.

[0249] It should also be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0250] In this application, the term "at least one" means one or more, and the term "plurality" means two or more. For example, a plurality of range locks means two or more range locks. The terms "system" and "network" are often used interchangeably herein.

[0251] It should be understood that the terminology used in the description of the various examples herein is for the purpose of describing particular examples only and is not intended to be limiting. As used in the description of the various examples and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0252] It will also be understood that the term “comprise” (also known as “includes,” “including,” “comprises,” and / or “comprising”) when used in this specification specifies the presence of stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0253] It should also be understood that, depending on the context, the phrase “if it is determined that…” or “if [stated condition or event] is detected” may be interpreted to mean “upon determining…” or “in response to determining…” or “upon detecting [stated condition or event]” or “in response to detecting [stated condition or event]”.

[0254] It should be understood that determining B based on A does not mean determining B based solely on A. B can also be determined based on A and / or other information.

[0255] It should also be understood that references throughout this specification to "one embodiment," "an embodiment," or "one possible implementation" mean that specific features, structures, or characteristics associated with that embodiment or implementation are included in at least one embodiment of the present application. Therefore, the appearance of "in one embodiment," "in an embodiment," or "one possible implementation" throughout this specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0256] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the principles of the present application should be included in the scope of protection of the present application.

Claims

1. A signal processing method, characterized in that: The method comprises: Encoding the signal to be transmitted to obtain a plurality of code blocks, wherein the plurality of code blocks include a first data signal and / or a first control signal, and the plurality of code blocks also include a management signal; The plurality of code blocks are transmitted through a serial channel.

2. The method according to claim 1, characterized in that: A first code block among the plurality of code blocks includes a first part and a second part, the first part includes the first data signal and / or the first control signal, and the second part includes the management signal.

3. The method according to claim 2, characterized in that There are multiple first code blocks, and the management signal appears periodically in the multiple first code blocks.

4. The method according to any one of claims 1 to 3, characterized in that: The plurality of code blocks include a management code block, and the management code block includes the management signal.

5. The method according to any one of claims 1 to 4, characterized in that: The serial channel is used to connect the media access control MAC layer and the physical layer PHY.

6. The method according to any one of claims 1 to 5, characterized in that: The serial channel is implemented by one pin or by a group of pins.

7. The method according to any one of claims 1 to 6, characterized in that: The serial channel is implemented based on a medium independent interface MII.

8. The method according to any one of claims 1 to 7, characterized in that: The signal to be transmitted is related to an Ethernet frame.

9. The method according to claim 8, characterized in that The signal to be transmitted being related to the Ethernet frame includes at least one of the following: the signal to be transmitted is generated based on the Ethernet frame, or the signal to be transmitted is used to manage the transmission of the Ethernet frame.

10. The method according to any one of claims 1 to 9, characterized in that: The management signal includes a first management data input and output MDIO signal corresponding to the read operation; the method further includes: A second MDIO signal is received, where the second MDIO signal is used to provide feedback on the read operation.

11. The method according to claim 10, characterized in that The second serial channel for receiving the second MDIO signal is different from the first serial channel for sending the plurality of code blocks.

12. The method according to any one of claims 1 to 11, characterized in that: The method is applied to a physical layer PHY function module, and the multiple code blocks also include a physical layer channel status indication.

13. A signal processing method, characterized in that: The method comprises: receiving a plurality of code blocks through a serial channel, the plurality of code blocks including a first data signal and / or a first control signal, the plurality of code blocks also including a management signal; The management signal, and the first data signal and / or the first control signal are obtained from the multiple code blocks.

14. The method according to claim 13, characterized in that A first code block among the plurality of code blocks comprises a first part and a second part, the first part comprises the first data signal and / or the first control signal, and the second part comprises the management signal; The acquiring the management signal, the first data signal and / or the first control signal from the multiple code blocks includes: Acquire the first data signal and / or the first control signal from a first part of the first code block; The management signal is obtained from a second portion of the first code block.

15. The method according to claim 14, characterized in that The number of the first code blocks is multiple, and the second part appears periodically in the multiple first code blocks; and obtaining the management signal from the second part of the first code block includes: Acquire a periodically occurring second portion from the plurality of first code blocks; The management signal is obtained from the second portion.

16. The method according to any one of claims 13 to 15, characterized in that: The plurality of code blocks include a management code block, and the management code block includes the management signal; The acquiring the management signal from the multiple code blocks comprises: The management signal is obtained from the management code block.

17. The method according to any one of claims 13 to 16, characterized in that: The serial channel is used to connect the media access control MAC layer and the physical layer PHY.

18. The method according to any one of claims 13 to 17, characterized in that: The serial channel is implemented by one pin or by a group of pins.

19. The method according to any one of claims 13 to 18, characterized in that: The serial channel is implemented based on a medium independent interface MII.

20. The method according to any one of claims 13 to 19, characterized in that: The management signal includes a first management data input and output MDIO signal corresponding to the read operation; the method further includes: A second MDIO signal is sent, where the second MDIO signal is used to provide feedback on the read operation.

21. The method according to claim 20, characterized in that The second serial channel for sending the second MDIO signal is different from the first serial channel for receiving the plurality of code blocks.

22. The method according to any one of claims 13 to 21, characterized in that: The method is applied to a media access control (MAC) function module, wherein the multiple code blocks further include a physical layer channel state indication; the method further includes: The physical layer channel state indication is obtained from the multiple code blocks.

23. A signal processing device, characterized in that: The signal processing device comprises: An encoding module, configured to encode a signal to be transmitted to obtain a plurality of code blocks, wherein the plurality of code blocks include a first data signal and / or a first control signal, and the plurality of code blocks also include a management signal; The sending module is used to send the multiple code blocks through a serial channel.

24. The device according to claim 23, characterized in that A first code block among the plurality of code blocks includes a first part and a second part, the first part includes the first data signal and / or the first control signal, and the second part includes the management signal.

25. The device according to claim 24, characterized in that There are multiple first code blocks, and the management signal appears periodically in the multiple first code blocks.

26. The device according to any one of claims 23 to 25, characterized in that The plurality of code blocks include a management code block, and the management code block includes the management signal.

27. The device according to any one of claims 23 to 26, characterized in that The serial channel is used to connect the media access control MAC layer and the physical layer PHY.

28. The device according to any one of claims 23 to 27, characterized in that The serial channel is implemented by one pin or by a group of pins.

29. The device according to any one of claims 23 to 28, characterized in that The serial channel is implemented based on a medium independent interface MII.

30. The device according to any one of claims 23 to 29, characterized in that The signal to be transmitted is related to an Ethernet frame.

31. The device according to claim 30, characterized in that The signal to be transmitted is related to the Ethernet frame and includes at least one of the following: the signal to be transmitted is generated based on the Ethernet frame, or the system to be transmitted is used to manage the transmission of the Ethernet frame.

32. The device according to any one of claims 23 to 31, characterized in that The management signal includes a first management data input and output MDIO signal corresponding to a read operation; the device also includes: The receiving module is used to receive a second MDIO signal, where the second MDIO signal is used to provide feedback on the read operation.

33. The device according to claim 32, characterized in that The second serial channel for receiving the second MDIO signal is different from the first serial channel for sending the plurality of code blocks.

34. The device according to any one of claims 23 to 33, characterized in that If the device is applied to a physical layer PHY function module, the multiple code blocks also include a physical layer channel status indication.

35. A signal processing device, characterized in that: The signal processing device comprises: A receiving module, configured to receive a plurality of code blocks through a serial channel, wherein the plurality of code blocks include a first data signal and / or a first control signal, and the plurality of code blocks also include a management signal; An acquisition module is used to acquire the management signal, the first data signal and / or the first control signal from the multiple code blocks.

36. The device according to claim 35, characterized in that A first code block among the plurality of code blocks comprises a first part and a second part, the first part comprises the first data signal and / or the first control signal, and the second part comprises the management signal; The acquisition module is used to acquire the first data signal and / or the first control signal from the first part of the first code block, and acquire the management signal from the second part of the first code block.

37. The device according to claim 36, characterized in that There are multiple first code blocks, and the second part appears periodically in the multiple first code blocks; the acquisition module is used to acquire the periodically appearing second part from the multiple first code blocks, and acquire the management signal from the second part.

38. The device according to any one of claims 35 to 37, characterized in that The multiple code blocks include a management code block, and the management code block includes the management signal; the acquisition module is used to acquire the management signal from the management code block.

39. The device according to any one of claims 35 to 38, characterized in that The serial channel is used to connect the media access control MAC layer and the physical layer PHY.

40. The device according to any one of claims 35 to 39, characterized in that The serial channel is implemented by one pin or by a group of pins.

41. The device according to any one of claims 35 to 40, characterized in that The serial channel is implemented based on a medium independent interface MII.

42. The device according to any one of claims 35 to 41, characterized in that The management signal includes a first management data input and output MDIO signal corresponding to a read operation; the device also includes: The sending module is used to send a second MDIO signal, where the second MDIO signal is used to provide feedback on the read operation.

43. The device according to claim 42, characterized in that The second serial channel for sending the second MDIO signal is different from the first serial channel for receiving the plurality of code blocks.

44. The device according to any one of claims 35 to 43, characterized in that If the device is applied to a media access control MAC functional module, the multiple code blocks also include a physical layer channel status indication; the acquisition module is further used to acquire the physical layer channel status indication from the multiple code blocks.

45. A communication device, characterized in that: The device comprises: a media access control MAC layer circuit, wherein the MAC layer circuit is used to execute the signal processing method as described in any one of claims 1-11 and 13-22.

46. ​​A communication device, characterized in that: The device comprises: a physical layer PHY circuit, and the PHY circuit is used to execute the signal processing method according to any one of claims 1-21.

47. A chip, characterized in that: The chip comprises: a media access control MAC layer circuit, and the MAC layer circuit is used to execute the signal processing method as described in any one of claims 1-11 and 13-22.

48. A chip, characterized in that: The chip comprises: a physical layer PHY circuit, and the PHY circuit is used to execute the signal processing method as described in any one of claims 1-21.

49. A signal processing system, characterized in that: The signal processing system includes a media access control MAC layer circuit and a physical layer PHY circuit; the MAC layer circuit is used to execute the signal processing method as described in any one of claims 1-11, and the PHY circuit is used to execute the signal processing method as described in any one of claims 13-21; or, the PHY circuit is used to execute the signal processing method as described in any one of claims 1-12, and the MAC layer circuit is used to execute the signal processing method as described in any one of claims 13-22.

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