Interrupt processing control device, interrupt processing control method, and interrupt processing control program

Abstract

An interrupt processing control device (1) comprises: a data collection unit (110) that collects advance data from a compute (2) for each of a first interrupt setting, in which the compute (2) sets one CPU core to perform interrupt processing when a packet is received, and a second interrupt setting, in which the compute (2) sets a prescribed number of CPU cores to perform interrupt processing in a distributable manner; a control scope determination unit (130) that uses the relationship between performance information and metrics for the first and second interrupt settings to determine a designated threshold value that meets performance requirements; and an interrupt core setting unit (140) that uses the designated threshold value to schedule the CPU core(s) to perform interrupt processing when a packet is received.

Description

Interrupt processing control device, interrupt processing control method, and interrupt processing control program

[0001] The present invention relates to an interrupt processing control device, an interrupt processing control method, and an interrupt processing control program for controlling interrupt processing to a CPU.

[0002] Among the services provided by large-scale distributed systems, network services are subject to strict requirements for latency, throughput, etc. For this reason, HW (hardware) with high processing performance is used, but there is a trade-off between HW processing performance and power consumption (i.e., increasing processing performance increases power consumption, while reducing power consumption decreases processing performance), and power consumption in systems with strict performance requirements is seen as a problematic factor that puts pressure on operating costs.

[0003] Meanwhile, technologies related to packet processing include Receive Side Scaling (RSS) (Non-Patent Document 1) and Irqbalance (Non-Patent Document 2). A hardware interrupt occurs to process packets arriving at a Network Interface Card (NIC). High traffic volumes increase interrupt processing, placing a strain on the CPU. Therefore, RSS relieves the bottleneck of interrupt processing by distributing the load on received packet processing across multiple cores (CPU cores).

[0004] Irqbalance is a software-enabled technology that distributes the load on the CPU caused by interrupt processing. When Irqbalance is enabled on hardware equipped with an RSS-compatible NIC, the interrupt processing of packets received by the NIC is distributed to multiple cores. Irqbalance also has a power-saving function that assigns interrupt processing to specific CPU cores during low load periods, putting the remaining CPUs into power-save mode.

[0005] The Linux Kernel Archives ("Linux" is a registered trademark), "Scaling in the Linux Networking Stack," [online], [Retrieved August 22, 2023], Internet <URL: https: / / www.kernel.org / doc / Documentation / networking / scaling.txt> nhorman, "Irqbalance," [online], [Retrieved August 22, 2023], Internet <https: / / irqbalance.github.io / irqbalance / >

[0006] In hardware equipped with an RSS-compatible NIC, when Irqbalance is enabled, Irqbalance periodically monitors the interrupt load on CPU cores and changes the assignment of interrupt processing to balance the load. However, if a core running an App (application) thread is selected as the assignment destination, the overhead of context switching will affect the performance of the App ("Problem 1").

[0007] Furthermore, because Irqbalance uses statistical data on (software / hardware) interrupt rates as a control index, depending on the hardware and app conditions, it may not be able to maximize power reduction while guaranteeing performance ("Problem 2"). In other words, if there is room in the app's performance requirements, the number of cores operating in energy-saving mode can be increased by consolidating interrupt-target cores. However, because performance requirements vary from user to user, the degree of achievement of requirements varies depending on the app when performance is measured at a given interrupt rate. In the example shown in Figure 10, if different users set performance requirements as "Performance Requirement 1" and "Performance Requirement 2," at a certain interrupt rate "R," "Performance Requirement 1" will be met but "Performance Requirement 2" will not. Therefore, because conventional Irqbalance does not take performance requirements into account, it is not possible to maximize power reduction while guaranteeing performance.

[0008] The present invention was made in consideration of these points, and its objective is to reduce the overhead caused by context switching when processing an interrupt to a CPU core, while simultaneously ensuring the performance of the app and maximizing power reduction.

[0009] The interrupt processing control device of the present invention is an interrupt processing control device that controls interrupt processing to a CPU core of a compute equipped with an application that provides a service via external communication, and is characterized by comprising: a data collection unit that collects preliminary data including performance information of the application and power consumption of the compute when a predetermined range of load is applied to the application, for each of a first interrupt setting indicating a state in which the compute sets one CPU core to perform interrupt processing when a packet is received, and a second interrupt setting indicating a state in which the compute sets a predetermined number of CPU cores to perform interrupt processing when a packet is received that can be distributed; a control range determination unit that selects, from the preliminary data, information that serves as a control parameter related to power consumption corresponding to the performance requirements required of the application as metrics, and determines predetermined thresholds for the first interrupt setting and the second interrupt setting that satisfy the performance requirements using the relationship between the performance information and the metrics; and an interrupt core setting unit that scales the CPU core that performs interrupt processing when a packet is received in the compute between the first interrupt setting and the second interrupt setting using the current value of the metrics obtained from the compute and the predetermined threshold.

[0010] According to the present invention, it is possible to reduce the overhead caused by context switching during interrupt processing for a CPU core, and to simultaneously guarantee the performance of an app and maximize power reduction.

[0011] 1 is a diagram showing the overall configuration of an interrupt processing control system including an interrupt processing control device according to an embodiment of the present invention; FIG. 2 is a diagram for explaining calculation of a threshold that defines a control range that satisfies performance requirements; FIG. 3 is a diagram showing an example of the data configuration of control range information according to an embodiment of the present invention; FIG. 4 is a diagram for explaining another example of calculation of a threshold that defines a control range that satisfies performance requirements; FIG. 5 is a flowchart showing the flow of control range determination processing executed in a pre-data collection phase by an interrupt processing control device according to an embodiment of the present invention; FIG. 6 is a flowchart showing the flow of interrupt processing control executed in an operation phase by an interrupt processing control device according to an embodiment of the present invention; FIG. 7 is a diagram showing an example of interrupt processing control using time-series data of metrics; FIG. 8 is a diagram showing an example of interrupt processing control using time-series data of metrics; FIG. 9 is a hardware configuration diagram showing an example of a computer that realizes the functions of an interrupt processing control device according to an embodiment of the present invention;

[0012] Next, an embodiment of the present invention (hereinafter referred to as "the present embodiment") will be described.

[0013] The interrupt processing control device of this embodiment allocates cores only to interrupt processing by networks and web apps where external communications occur frequently, and by collecting data in advance and determining a control range that satisfies the performance requirements of the app, it controls within a range that does not affect the performance of the app, thereby dynamically scaling cores to ensure both performance guarantees and maximize power reduction (details will be provided later).

[0014] 1 is a diagram showing the overall configuration of an interrupt processing control system 1000 including an interrupt processing control device 1 according to this embodiment. As shown in Fig. 1, the interrupt processing control device 1 is communicatively connected to each compute (physical server) 2, which is the subject of control of allocation of CPU cores accompanying interrupt processing via communication.

[0015] Each compute 2 has an application (App) 200 (e.g., a web service application) implemented on its hardware (HW). The application (App) 200 may be implemented in a virtual machine (VM) or a container. Each compute 2 also includes data collection software 21 and an intelligent platform management interface (IPMI) 22.

[0016] The data collection software 21 is software that collects performance data of the compute 2 and acquires app performance values ​​and HW operation status data. App performance values ​​include, for example, response time and throughput. HW operation status data is an index that serves as a reference for the load on the compute 2, and includes performance data obtainable from each compute 2, such as CPU usage, the number of instructions executed, cache misses, and the number of received packets, as well as performance values ​​obtained from the logs of apps running on the compute 2. Hereinafter, app performance values ​​and HW operation status data will be referred to as "performance information." This data collection software 21 can use existing data collection software such as Perf and dstat, or self-developed software, and collects performance information at predetermined time intervals (for example, as frequently as every second).

[0017] The IPMI 22 is a standard interface for monitoring and managing the state of HW (hardware) and includes a power consumption measurement unit. The IPMI 22 implements an application (App) 200 to measure the power consumption of the Compute 2 when a load is applied. Note that this power consumption measurement unit is not limited to the IPMI 22. If the Compute 2 includes a power meter, the power consumption may be measured using the power meter.

[0018] The Compute 2 transmits performance information and power consumption information (hereinafter referred to as "metrics") obtained when a load is applied to the implemented application (App) 200 to the interrupt processing control device 1. The Compute 2 then acquires CPU core setting information from the interrupt processing control device 1 and sets the CPU core optimally according to the metric information described below.

[0019] Compute 2 has a function to set the HW to a power-saving mode by enabling C-State, etc. In other words, if a specific CPU core (for example, one core) is set to interrupt when a packet is received, the remaining CPU cores can be set to a power-saving mode to reduce power consumption.

[0020] <Interrupt Processing Control Device> Next, the interrupt processing control device 1 according to this embodiment will be described. The interrupt processing control device 1 controls the interrupt processing of a CPU core through a preliminary data collection phase and an operation phase. In the preliminary data collection phase, the interrupt processing control device 1 applies a load to the App to be used and collects performance information (App performance values, HW operation status data, etc.) and power consumption of the CPU and server from the Compute 2. In this case, the interrupt processing control device 1 collects data for two setting patterns: one setting in which a specific core is set to interrupt when a packet is received (a state in which distributed processing is not performed, referred to as "Setting A" (first interrupt setting)), and one setting in which M specific cores are set to interrupt when a packet is received (M is a predetermined number that can be distributed (e.g., the maximum value), and a state in which distributed processing is performed, referred to as "Setting B" (second interrupt setting)). The interrupt processing control device 1 then uses one of the acquired data as a metric (e.g., CPU power consumption) and calculates predetermined thresholds (thresholds "a" and "b" described below) that define a control range that satisfies the performance requirements when scaling between the states of setting A and setting B. Note that the data that is the subject of analysis in interrupt processing control and information that serves as a control parameter related to power consumption corresponding to the performance requirements is referred to as "metrics." Furthermore, in the operation phase, if the metric (e.g., CPU power consumption) exceeds threshold "a" (first threshold), the interrupt processing control device 1 sets M specific cores (e.g., the maximum value) as the cores that will interrupt when a packet is received. If the metric is below threshold "b" (second threshold), the interrupt processing control device 1 controls to set one specific core as the core that will interrupt when a packet is received.

[0021] The interrupt processing control device 1 limits interrupt processing to communication-based interrupts and dynamically changes the settings of the interrupting core within a range that does not affect the performance of the target app, thereby guaranteeing performance and maximizing power reduction. As shown in Figure 1, the interrupt processing control device 1 includes a control unit 10, an input / output unit 11, and a storage unit 12.

[0022] The input / output unit 11 inputs and outputs information between each compute 2, etc. This input / output unit 11 is composed of a communication interface that transmits and receives information via a communication line, and an input / output interface that inputs and outputs information between an input device such as a keyboard and an output device such as a monitor, which are not shown.

[0023] The storage unit 12 is configured by a hard disk, a flash memory, a RAM (Random Access Memory), etc. The storage unit 12 stores a data store 100 and control range information 101.

[0024] The data store 100 stores performance information (app performance values, HW operation status data, etc.) and power consumption that are collected from the compute 2 by a data collection unit 110 (described later). In addition, as control range information 101, information on thresholds (threshold "a" and threshold "b") that define a control range that satisfies performance requirements when scaling between the states of setting A and setting B, determined by a control range determination unit 130 (described later), is stored.

[0025] The control unit 10 is responsible for all the processes executed by the interrupt processing control device 1 , and includes a data collection unit 110 , a load application unit 120 , a control range determination unit 130 , and an interrupt core setting unit 140 .

[0026] During the preliminary data collection phase and the operation phase, the data collection unit 110 collects preliminary data, including performance information (app performance values, HW operation status data, etc.) and power consumption, from each compute 2 for a predetermined period of time and stores the collected data in the data store 100. The data collection unit 110 acquires, for example, response time and throughput as app performance values, and acquires, for example, CPU usage, the number of executed instructions, cache misses, and the number of received packets as HW operation status data. The data collected by the data collection unit 110 includes data to be analyzed for calculating thresholds in the control range determination unit 130 and the interrupt core setting unit 140 (described below). For example, if the data specified by the performance requirement is response time, the data collection unit 110 acquires data on the response time. In addition, metrics (e.g., CPU power consumption) that serve as control parameters corresponding to the performance requirements are selected in advance, and the data collection unit 110 acquires data including information on the metrics.

[0027] In the preliminary data collection phase, the load application unit 120 applies a load within a predetermined range to the application (App) 200 used in Compute 2. The load application unit 120 gradually increases the amount of load assumed for the application (App) 200.

[0028] At this time, Compute 2 is made to execute processing in two patterns: "Setting A" (first interrupt setting), which sets one specific core to be interrupted when a packet is received, and "Setting B" (second interrupt setting), which sets M specific cores to be interrupted when a packet is received (M is a predetermined number that can be distributed (for example, a maximum value)). Note that the predetermined number that can be distributed, "M," may be set to the maximum number of CPU cores that maximizes the effect of load distribution, or the number of cores c (1<c<M) may be used as the predetermined number in consideration of increased power consumption, etc.

[0029] Regarding the cores assigned to a NIC, in Linux, for example, you can set the core to be assigned to the NIC for interrupt processing by writing to the / proc / irq / [IRQ_NUMBER] / smp_affinity file and specifying the core to be assigned to the target [IRQ_NUMBER] (IRQ number (interrupt request number)). For example, if the NIC's IRQ numbers are 135 to 142 (eight numbers), in setting A, the same arbitrary core is set in all eight files / proc / irq / [135-142] / smp_affinity. On the other hand, in setting B, different arbitrary cores are set in all eight files / proc / irq / [135-142] / smp_affinity. However, on servers with two or more sockets, a core is selected from the CPU of the socket to which the target NIC is connected.

[0030] The function of the load application unit 120 can be performed by an existing load test tool. Alternatively, the interrupt processing control device 1 may not include the load application unit 120, and an external device may apply a load to each compute 2.

[0031] The control range determination unit 130 calculates, as control range information 101, predetermined thresholds (threshold "a" and threshold "b") that define a control range that satisfies the performance requirements when scaling between the states of setting A and setting B. Specifically, the control range determination unit 130 determines the relationship between performance information (response time) and metrics (e.g., CPU power consumption) for each of setting A and setting B, as shown in FIG. 2 , based on the information collected by the data collection unit 110 and stored in the data store 100. The control range determination unit 130 then determines the metric value corresponding to the value (Xα) obtained by multiplying performance requirement X by a predetermined percentage α (0 < α ≦ 1), and determines this as threshold a (first threshold) for setting A and threshold b (second threshold) for setting B. Note that the predetermined percentage α is set so that the performance requirements are satisfied with an appropriate margin when scaling between the states of setting A and setting B. The control range determination unit 130 stores information about the threshold value a and the threshold value b in the storage unit 12 (FIG. 1) as control range information 101 as shown in Fig. 3. Note that Fig. 3 shows an example in which the threshold value a for setting A is set to "80 W" and the threshold value b for setting B is set to "95 W."

[0032] To calculate the control range information 101 ( FIG. 3 ), the control range determination unit 130 may determine thresholds based on the load amount set during the load test, as a method other than the method shown in FIG. 2 that determines thresholds from the correspondence between performance data and metrics. For example, as shown in the graph indicated by reference numeral 41 in FIG. 4 , the load amount Y is calculated when the performance requirement (response time) is exceeded on the graph for setting A, which does not distribute processing. Then, as shown in the graph indicated by reference numeral 42, the metric values ​​at the load amount (Yβ) obtained by multiplying the load amount Y by a predetermined ratio β (0<β≦1) may be calculated for settings A and B, and the thresholds a and b may be determined. The predetermined ratio β is set to ensure that the performance requirements are met with an appropriate margin when scaling between settings A and B. In this way, the control range determination unit 130 can calculate, as the control range information 101, thresholds (threshold “a” and threshold “b”) that define the control range that satisfies the performance requirements when scaling between settings A and B.

[0033] Returning to FIG. 1 , during the operation phase, the interrupt core setting unit 140 scales the CPU cores that interrupt when a packet is received, using thresholds (thresholds a and b) indicated in the control range information 101, based on data (metrics) collected by the data collection unit 110 from Compute 2 and stored in the data store 100. Specifically, when the core allocation for Compute 2 is Setting A (set to one specific core), if the value of the metric exceeds Threshold A, the interrupt core setting unit 140 changes the setting to Setting B (set to M cores (a predetermined number that can be distributed)). On the other hand, when the core allocation for Compute 2 is Setting B (set to M cores), if the value of the metric is below Threshold B, the interrupt core setting unit 140 changes the setting to Setting A (set to one specific core). The interrupt core setting process performed by the interrupt core setting unit 140 will be described in detail later with reference to FIG. 6 .

[0034] <Processing Flow> Next, a description will be given of the processing executed by the interrupt processing control system 1000 including the interrupt processing control device 1. Fig. 5 shows the processing in the preliminary data collection phase, and Fig. 6 shows the processing in the operation phase.

[0035] 5 is a flowchart showing the flow of the control range determination process executed in the preliminary data collection phase by the interrupt processing control device 1. First, the load application unit 120 of the interrupt processing control device 1 applies a load within a predetermined range to the application (App) 200 used in the Compute 2 using the two patterns of setting A and setting B described above. As a result, the data collection unit 110 collects data (preliminary data) on performance information (App performance values, HW operation status data, etc.) and power consumption (CPU power consumption) from the Compute 2 (step S1).

[0036] Specifically, the load application unit 120 executes processing in two patterns: setting A (first interrupt setting) in which one specific core is set as the core that will be interrupted when a packet is received, and setting B (second interrupt setting) in which M specific cores (a predetermined number that can be distributed (e.g., the maximum value)) are set as the cores that will be interrupted when a packet is received. The load application unit 120 gradually increases the amount of load assumed in the application (App) 200.

[0037] The data collection software 21 of the Compute 2 collects performance information (App performance values, HW operation status data, etc.) during processing by the application (App) 200 at predetermined time intervals (for example, as frequently as every second) and transmits the information to the interrupt processing control device 1. Similarly, the IPMI 22 measures power consumption (CPU power consumption) during processing by the application (App) 200 and transmits the information to the interrupt processing control device 1. The data collection unit 110 stores the performance information (App performance values, HW operation status data, etc.) and power consumption information (preliminary data) collected from the Compute 2 in the data store 100 of the storage unit 12.

[0038] Next, the control range determination unit 130 calculates, based on the prior data stored in the data store 100, thresholds (threshold "a" and threshold "b") that define the control range that satisfies the performance requirements when scaling between the states of setting A and setting B for each of the above-mentioned settings A and B, as control range information 101 (Figure 3) (step S2).

[0039] Specifically, the control range determination unit 130 determines the relationship between performance information (response time) and metrics (e.g., CPU power consumption) as shown in FIG. 2 based on the prior data collected by the data collection unit 110 and stored in the data store 100. The control range determination unit 130 then determines the metric value corresponding to the value (Xα) obtained by multiplying performance requirement X by a predetermined rate α (0 < α ≦ 1), and determines this as threshold a (first threshold) for setting A and threshold b (second threshold) for setting B. The control range determination unit 130 stores the determined thresholds (threshold a, threshold b) in the storage unit 12 as control range information 101. Note that the control range determination unit 130 may also determine the thresholds (threshold a, threshold b) based on the load amount set during the load test, as shown in FIG. 4.

[0040] In this way, the interrupt processing control device 1 can determine threshold value a, which is an index for determining whether to increase (scale up) the number of CPU cores that process interrupts for an application (App) 200 used in the Compute 2 when the number of cores that process interrupts upon packet reception is set to one specific core (setting A). Furthermore, the interrupt processing control device 1 can determine threshold value b, which is an index for determining whether to decrease (scale down) the number of CPU cores that process interrupts for an application (App) 200 used in the Compute 2 when the number of cores that process interrupts upon packet reception is set to M specific cores (e.g., the maximum value) (setting B). By determining the control range information 101 for these threshold values ​​(threshold value a, threshold value b), the interrupt processing control device 1 can appropriately scale the number of cores that process interrupts in response to fluctuations in metrics.

[0041] 6 is a flowchart showing the flow of interrupt processing control executed in the operation phase by the interrupt processing control device 1. The interrupt processing control device 1 collects metrics from the Compute 2 in the data collection unit 110, and executes scaling of the CPU core that processes the interrupt based on the thresholds (threshold a, threshold b) calculated as the control range information 101.

[0042] First, the interrupt core setting unit 140 of the interrupt processing control device 1 sets, as an initial setting, setting A, which sets one specific core to be interrupted when a packet is received, to the Compute 2 (step S10). Next, the interrupt core setting unit 140 repeats the processes from steps S11 to S23.

[0043] In step S12, the data collection unit 110 of the interrupt processing control device 1 collects information on metrics (e.g., CPU power consumption) from the Compute 2. The data collection unit 110 may also collect information on metrics when collecting information on performance (app performance values, HW operation status data, etc.), power consumption, etc. The metrics are collected at a predetermined time interval (e.g., at a high frequency such as every 1 second).

[0044] Next, the interrupt core setting unit 140 determines whether the current setting of the interrupt core is setting A or setting B (step S13). If the current setting is setting A, the process proceeds to step S14, and if it is setting B, the process proceeds to step S18.

[0045] In step S14, the interrupt core setting unit 140 determines whether the metrics (e.g., CPU power consumption) collected in step S12 exceed the threshold value a indicated in the control range information 101. If the metrics do not exceed the threshold value a (step S14 → No), the process proceeds to step S22. On the other hand, if the metrics exceed the threshold value a (step S14 → Yes), the process proceeds to the next step S15.

[0046] In step S15, the data collection unit 110 collects metrics for a predetermined time (e.g., 5 seconds). Then, during the measurement for that predetermined time (e.g., 5 seconds), it is determined whether all metric values ​​exceed threshold a (step S16). The reason for collecting metrics for the predetermined time (e.g., 5 seconds) is to suppress excessive control due to noise in frequently collected metric data or sudden increases or decreases in values. If all metric values ​​do not exceed threshold a (step S16 → No), that is, if there is even one value that does not exceed threshold a, proceed to step S22. On the other hand, if all metric values ​​exceed threshold a (step S16 → Yes), proceed to the next step S17.

[0047] In step S17, the interrupt core setting unit 140 changes setting A to setting B. That is, the number of cores that will be interrupted when a packet is received is set to M specific cores (M is a predetermined distributable number (e.g., a maximum value)). Then, the process proceeds to the next step, S22.

[0048] On the other hand, if the current setting is setting B in step S13, the interrupt core setting unit 140 determines whether the metrics (e.g., CPU power consumption) collected in step S12 are below threshold b indicated in the control range information 101 (step S18). If the metrics are not below threshold b (step S18 → No), the process proceeds to step S22. On the other hand, if the metrics are below threshold b (step S18 → Yes), the process proceeds to the next step S19.

[0049] In step S19, the data collection unit 110 collects metrics for a predetermined time (e.g., 5 seconds). Then, during the measurement for that predetermined time (e.g., 5 seconds), it is determined whether all metric values ​​are below threshold b (step S20). The reason for collecting metrics for the predetermined time (e.g., 5 seconds) is to suppress excessive control due to noise in frequently collected metric data or sudden increases or decreases in values. If all metric values ​​are not below threshold b (step S20 → No), that is, if there is at least one value that is not below threshold b, proceed to step S22. On the other hand, if all metric values ​​are below threshold b (step S20 → Yes), proceed to the next step S21.

[0050] In step S21, the interrupt core setting unit 140 changes setting B to setting A. That is, the interrupt core setting unit 150 sets one specific core as the core that will interrupt when a packet is received for Compute 2 that includes the application (App) 200 to be controlled. Then, the process proceeds to the next step, S22. Note that when setting A is changed, Compute 2 sets the other CPU cores, except for the specific CPU core that will interrupt when a packet is received, to power saving mode. This makes it possible to reduce power consumption.

[0051] In step S22, the interrupt core setting unit 140 determines whether the service of the application (App) 200 in Compute 2 has ended. If the service has not ended (step S22 → No), the process proceeds to step S23, returns to step S11, and repeats the process. On the other hand, if the service has ended (step S22 → Yes), the entire interrupt processing control process ends.

[0052] <Variation of this embodiment> In addition to the interrupt processing control as shown in FIG. 6, the interrupt processing control device 1 according to this embodiment may, after operation has started, if time series data of metrics has been collected and accumulated over a long period of time, perform time series prediction to grasp increases or decreases in metrics and make control decisions in advance, or may utilize the analysis results to assist in making control decisions.

[0053] For example, as shown in Figure 7, when time series data is obtained in which the metric values ​​change periodically over time, the interrupt core setting unit 140 of the interrupt processing control device 1 determines that there is a high possibility that the threshold will be exceeded based on the accumulated past data at the timing indicated by time t1, and scales up the core allocation for packet processing.

[0054] 8, if a downward trend is predicted from past data, the interrupt core setting unit 140 of the interrupt processing control device 1 scales down the core allocation for packet processing even when the metric value fluctuates around the threshold (symbol z in FIG. 8). By storing time-series data of the metric in the data store 100 in this way, the interrupt core setting unit 140 can grasp the trend of increase or decrease in the metric and use it for scaling the core allocation.

[0055] <Hardware Configuration> The interrupt processing control device 1 according to this embodiment is realized by, for example, a computer 900 configured as shown in Fig. 9. Fig. 9 is a hardware configuration diagram showing an example of the computer 900 that realizes the functions of the interrupt processing control device 1 according to this embodiment. The computer 900 has a CPU 901, a ROM (Read Only Memory) 902, a RAM 903, an HDD (Hard Disk Drive) 904, an input / output I / F (Interface) 905, a communication I / F 906, and a media I / F 907.

[0056] The CPU 901 operates based on a program (interrupt processing control program) stored in the ROM 902 or the HDD 904, and performs control by the control unit 10 (FIG. 1). The ROM 902 stores a boot program executed by the CPU 901 when the computer 900 is started up, programs related to the hardware of the computer 900, and the like.

[0057] The CPU 901 controls an input device 910 such as a mouse or keyboard, and an output device 911 such as a display or printer, via an input / output I / F 905. The CPU 901 acquires data from the input device 910 via the input / output I / F 905, and outputs generated data to the output device 911. Note that a GPU (Graphics Processing Unit) or the like may be used as a processor together with the CPU 901.

[0058] The HDD 904 stores programs executed by the CPU 901 and data used by the programs. The communication I / F 906 receives data from other devices via a communication network (e.g., NW (Network) 920) and outputs the data to the CPU 901, and also transmits data generated by the CPU 901 to other devices via the communication network.

[0059] The media I / F 907 reads a program (interrupt processing control program) or data stored in the recording medium 912 and outputs it to the CPU 901 via the RAM 903. The CPU 901 loads a program related to a target process from the recording medium 912 onto the RAM 903 via the media I / F 907, and executes the loaded program. The recording medium 912 is an optical recording medium such as a DVD (Digital Versatile Disc) or a PD (Phase Change Rewritable Disc), a magneto-optical recording medium such as an MO (Magneto Optical Disc), a magnetic recording medium, a semiconductor memory, or the like.

[0060] For example, when a computer 900 functions as the interrupt processing control device 1 of the present invention, a CPU 901 of the computer 900 executes a program loaded onto a RAM 903 to realize the functions of the interrupt processing control program. In addition, data stored in the RAM 903 is stored in an HDD 904. The CPU 901 reads and executes a program related to a target process from a recording medium 912. Alternatively, the CPU 901 may read a program related to a target process from another device via a communication network (NW 920).

[0061] <Effects> The effects of the interrupt processing control device etc. according to the present invention will be described below. The interrupt processing control device according to the present invention is an interrupt processing control device 1 that controls interrupt processing to a CPU core of a compute 2 that is equipped with an application 200 that provides a service via external communication, and includes a data processor that collects advance data including performance information of the application 200 and power consumption of the compute 2 when a load within a predetermined range is applied to the application 200 in each of a first interrupt setting indicating a state in which the compute 2 sets one CPU core to perform interrupt processing when a packet is received and a second interrupt setting indicating a state in which the compute 2 sets a predetermined number of CPU cores to perform interrupt processing when a packet is received that can be distributed. The system is characterized by comprising a data collection unit 110, a control range determination unit 130 that selects, from the advance data, information that will be a control parameter related to power consumption corresponding to the performance requirements required of the application 200 as metrics, and determines, for the first interrupt setting and the second interrupt setting, predetermined thresholds that satisfy the performance requirements using the relationship between the performance information and the metrics, and an interrupt core setting unit 140 that scales the CPU core that processes the interrupt when a packet is received in Compute 2 between the first interrupt setting and the second interrupt setting using the current metric value obtained from Compute 2 and the predetermined threshold.

[0062] In this way, the interrupt processing control device 1 can limit core allocation to communication-based interrupt processing only, thereby suppressing overhead caused by context switching. Furthermore, the interrupt processing control device 1 collects data in advance for the target application (App) 200, determines a range that does not affect performance using a predetermined threshold, and scales the CPU core that processes the interrupt when a packet is received. This allows the interrupt processing control device 1 to ensure both performance and maximize power reduction. Furthermore, the interrupt processing control device 1 requires only one parameter (metric) to be used for control decisions, and can achieve dynamic scaling of the CPU core with a simple control algorithm that does not require storing or processing large amounts of data.

[0063] In addition, in the interrupt processing control device 1, the control range determination unit 130 determines a first threshold value for a metric that satisfies the performance requirements from the relationship between the metrics and performance information based on the preliminary data obtained in the first interrupt setting, and determines a second threshold value for a metric that satisfies the performance requirements from the relationship between the metrics and performance information based on the preliminary data obtained in the second interrupt setting, and the interrupt core setting unit 140 scales the CPU core to change the first interrupt setting of Compute 2 to the second interrupt setting when the current metric value exceeds the first threshold value, and changes the second interrupt setting of Compute 2 to the first interrupt setting when the current metric value falls below the second threshold value.

[0064] In this way, the interrupt processing control device 1 can determine, based on the relationship between performance requirements and metrics, a threshold value a (first threshold value) that serves as an index for determining whether to increase (scale up) the number of CPU cores that process interrupts when a packet is received and a specific core is set to interrupt when the packet is received (setting A: first interrupt setting). Furthermore, the interrupt processing control device 1 can determine a threshold value b (second threshold value) that serves as an index for determining whether to decrease (scale down) the number of CPU cores that process interrupts when the packet is received and a specific number M (e.g., the maximum value) that can be distributed (setting B: second interrupt setting). The interrupt processing control device 1 can refer to the threshold values ​​a and b based on the current metric values ​​and perform dynamic scaling of CPU cores that meet the performance requirements of the application (App) 200.

[0065] Furthermore, in the interrupt processing control device 1, the control range determination unit 130 determines a first threshold value for a metric that satisfies the performance requirements from the relationship between the load amount and the metrics corresponding to performance information that satisfies the performance requirements based on the preliminary data obtained in the first interrupt setting, and determines a second threshold value from the load amount corresponding to the performance information that satisfies the performance requirements based on the preliminary data obtained in the first interrupt setting and the relationship between the load amount and the metrics based on the preliminary data obtained in the second interrupt setting, and the interrupt core setting unit 140 scales the CPU core to change the first interrupt setting of Compute to the second interrupt setting when the current metric value exceeds the first threshold value, and changes the second interrupt setting of Compute to the first interrupt setting when the current metric value falls below the second threshold value.

[0066] In this way, the interrupt processing control device 1 can determine a threshold value a (first threshold value) that serves as an index for determining whether to increase (scale up) the number of CPU cores that process interrupts when a packet is received, based on the relationship between the load amount and the metrics corresponding to the performance information that satisfies the performance requirements, when a specific core is set to process interrupts when a packet is received (setting A: first interrupt setting). Furthermore, the interrupt processing control device 1 can determine a threshold value b (second threshold value) that serves as an index for determining whether to decrease (scale down) the number of CPU cores that process interrupts when a packet is received, based on a predetermined number M (e.g., the maximum value) that can be distributed (setting B: second interrupt setting). The interrupt processing control device 1 can refer to the threshold values ​​a and b based on the current metric values ​​and perform dynamic scaling of CPU cores that meet the performance requirements of the application (App) 200.

[0067] Furthermore, in the interrupt processing control device 1, when the data collection unit 110 is collecting current metrics information from the compute 2 in a time series, the interrupt core setting unit 140 is characterized in that it performs scaling using a predetermined threshold value based on a time series prediction based on increases and decreases in the metric values.

[0068] In this way, by collecting metrics information in time series, the interrupt processing control device 1 can grasp trends in increases and decreases in metrics, perform time series predictions, and make scaling decisions in advance. Alternatively, the interrupt processing control device 1 can utilize analysis of time series data to assist in making scaling decisions.

[0069] The present invention is not limited to the above-described embodiments, and many modifications can be made by a person having ordinary skill in the art within the technical concept of the present invention.

[0070] REFERENCE SIGNS LIST 1 Interrupt processing control device 2 Compute (physical server) 10 Control unit 11 Input / output unit 12 Storage unit 21 Data collection software 22 IPMI 100 Data store 101 Control range information 110 Data collection unit 120 Load application unit 130 Control range determination unit 140 Interrupt core setting unit 200 Application (App) 1000 Interrupt processing control system

Claims

1. An interrupt processing control device that controls interrupt processing for a CPU core of a compute equipped with an application that provides a service via external communication, comprising: a data collection unit that collects advance data including performance information of the application and power consumption of the compute when a predetermined range of load is applied to the application, for each of a first interrupt setting indicating a state in which the compute sets one CPU core to perform interrupt processing when a packet is received, and a second interrupt setting indicating a state in which the compute sets a predetermined number of CPU cores to perform interrupt processing when a packet is received that can be distributed; a control range determination unit that selects, from the advance data, information that becomes a control parameter related to power consumption corresponding to performance requirements required for the application as metrics, and determines a predetermined threshold value for the first interrupt setting and the second interrupt setting that satisfies the performance requirements using the relationship between the performance information and the metrics; and an interrupt core setting unit that scales the CPU core that performs interrupt processing when a packet is received in the compute between the first interrupt setting and the second interrupt setting, using the current metric value obtained from the compute and the predetermined threshold value.

2. The interrupt processing control device of claim 1, characterized in that the control range determination unit determines a first threshold value for the metric that satisfies the performance requirements from the relationship between the performance information based on the preliminary data obtained in the first interrupt setting and the metric, and determines a second threshold value for the metric that satisfies the performance requirements from the relationship between the performance information based on the preliminary data obtained in the second interrupt setting, and the interrupt core setting unit performs the scaling of a CPU core to change the first interrupt setting of the compute to the second interrupt setting when the current value of the metric exceeds the first threshold value, and to change the second interrupt setting of the compute to the first interrupt setting when the current value of the metric falls below the second threshold value.

3. The interrupt processing control device of claim 1, wherein the control range determination unit determines a first threshold value for the metric that satisfies the performance requirement from the relationship between the metric and the load amount corresponding to the performance information that satisfies the performance requirement based on the preliminary data obtained in the first interrupt setting, and determines a second threshold value from the load amount corresponding to the performance information that satisfies the performance requirement based on the preliminary data obtained in the first interrupt setting and the relationship between the load amount and the metric based on the preliminary data obtained in the second interrupt setting; and the interrupt core setting unit performs the scaling of a CPU core to change the first interrupt setting of the compute to the second interrupt setting when the current value of the metric exceeds the first threshold value, and to change the second interrupt setting of the compute to the first interrupt setting when the current value of the metric falls below the second threshold value.

4. The interrupt processing control device of claim 1, characterized in that when the data collection unit collects current metric information from the compute in a time series, the interrupt core setting unit performs scaling using the specified threshold based on a time series prediction based on increases and decreases in the metric values.

5. An interrupt processing control method for an interrupt processing control device that controls interrupt processing for a CPU core of a compute equipped with an application that provides a service through external communication, comprising the steps of: collecting advance data including performance information of the application and power consumption of the compute when a predetermined range of load is applied to the application, for each of a first interrupt setting indicating a state in which the compute sets one CPU core to perform interrupt processing when a packet is received, and a second interrupt setting indicating a state in which the compute sets a predetermined distributable number of CPU cores to perform interrupt processing when a packet is received; selecting, from the advance data, information that is a control parameter related to power consumption corresponding to a performance requirement required for the application as a metric, and determining, for the first interrupt setting and the second interrupt setting, a predetermined threshold value that satisfies the performance requirement by using the relationship between the performance information and the metric; and scaling the CPU core that performs interrupt processing when a packet is received in the compute between the first interrupt setting and the second interrupt setting by using the current metric value obtained from the compute and the predetermined threshold value; 2. An interrupt processing control method comprising:

6. An interrupt processing control program for causing a computer to function as the interrupt processing control device according to any one of claims 1 to 4.

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