Processing circuit and information processing device

Abstract

At each cycle time, a fetch circuit (110) fetches an instruction at the cycle time as a reference instruction and fetches an instruction at the cycle time shifted back in time one or more cycles from the cycle time as a comparison instruction. At each cycle time, a comparison circuit (120) compares the fetched comparison instruction with the reference instruction fetched at a cycle time shifted back in time from the cycle time when the comparison instruction was fetched. At each cycle time, an arithmetic circuit (140) computes the compared reference instruction if the compared reference instruction matches the compared comparison instruction.

Description

Processing circuit and information processing device

[0001] The present disclosure relates to fault-tolerant processors.

[0002] Security bypass attacks using fault attacks are becoming a problem. The assumption that a program will run as written breaks down through the following mechanisms. Mechanism 1: A setup time violation caused by a power supply or clock glitch causes an instruction to be skipped. Mechanism 2: Photocurrent or eddy current causes data corruption (bit flip).

[0003] When a fault attack is made on a typical processor with a five-stage pipeline, errors such as memory access are likely to occur on the longest path (critical path) that takes the longest processing time. In particular, instruction fetch (IF) or memory access (MEM) is likely to be broken. The simplest fault mechanism is an instruction skip due to a fetch error.

[0004] Patent Document 1 discloses the following data processing device. The data processing device includes a first processing device, a second processing device, and a comparison device. The first processing device processes input data during a first processing period to generate first output data. The second processing device processes the input data during a second processing period to generate second output data. The comparison device compares the first output data with the second output data to determine whether a processing error has occurred.

[0005] Patent No. 4386766

[0006] The data processing device of Patent Document 1 shifts the processing period to make the processing redundant, and is unable to notice an instruction skip (NOP) caused by a fetch error before processing.

[0007] The present disclosure aims to make it possible to notice instruction skips due to fetch errors.

[0008] The processing circuit of the present disclosure comprises: a fetch circuit that, for each cycle time, fetches an instruction at the cycle time as a reference instruction and fetches an instruction at a cycle time that is one or more cycles earlier than the cycle time as a comparison instruction; a comparison circuit that, for each cycle time, compares the fetched comparison instruction with a reference instruction fetched at a cycle time that is earlier by the shift time than the cycle time at which the comparison instruction was fetched; and an operation circuit that, for each cycle time, operates on the compared reference instruction when the compared reference instruction matches the compared comparison instruction.

[0009] According to the present disclosure, it becomes possible to detect an instruction skip caused by a fetch error.

[0010] FIG. 1 is a configuration diagram of a processing circuit 100 according to a first embodiment. FIG. 2 is a configuration diagram of a fetch circuit 110 according to the first embodiment. FIG. 3 is a diagram showing an example of the configuration of the processing circuit 100 according to the first embodiment. FIG. 4 is a diagram showing an example of a timing chart according to the first embodiment. FIG. 5 is a configuration diagram of a conventional processor. FIG. 6 is a diagram showing a difference in operation between the processing circuit 100 according to the first embodiment and a conventional processor. FIG. 7 is a diagram showing an example of the processing circuit 100 according to the first embodiment. FIG. 8 is a diagram showing an example of the processing circuit 100 according to the first embodiment. FIG. 9 is a diagram showing an example of the processing circuit 100 according to the first embodiment.

[0011] In the embodiments and drawings, the same or corresponding elements are denoted by the same reference numerals. The description of elements denoted by the same reference numerals as those already described will be omitted or simplified as appropriate. Arrows in the drawings primarily indicate the flow of signals, data, or processes.

[0012] First Embodiment A processing circuit 100 will be described with reference to FIGS.

[0013] *** Description of Configuration *** The configuration of the processing circuit 100 will be described based on FIG. 1. The processing circuit 100 is hardware that realizes the execution of any processing. Examples of the processing circuit 100 are a processor and an FPGA. Examples of a processor are a CPU and a GPU. CPU is an abbreviation for Central Processing Unit. GPU is an abbreviation for Graphics Processing Unit. FPGA is an abbreviation for Field Programmable Gate Array.

[0014] The processing circuit 100 includes a fetch circuit 110, a comparison circuit 120, a decode circuit 130, an arithmetic circuit 140, and a bus control circuit 150. The processing circuit 100 is characterized by the fetch circuit 110 and the comparison circuit 120.

[0015] The fetch circuit 110 is a circuit that fetches, for each cycle time, an instruction at that cycle time as a reference instruction, and also fetches an instruction at a cycle time that is one or more cycles earlier than the cycle time as a comparison instruction. The cycle time corresponds to the time when a clock signal is generated. The offset time is a time equivalent to a predetermined number of cycles. The instruction at a cycle time is an instruction stored in a memory area specified by the program counter value (address) at the cycle time.

[0016] The comparison circuit 120 is a circuit that compares, for each cycle time, a fetched comparison instruction with a reference instruction fetched at a cycle time that is the shift time before the cycle time at which the comparison instruction was fetched. The comparison circuit 120 outputs an alert signal if the compared reference instruction does not match the compared comparison instruction.

[0017] The decode circuit 130 is a circuit that decodes the compared reference instruction when the compared reference instruction matches the compared comparison instruction.

[0018] The arithmetic circuit 140 is a circuit that performs an arithmetic operation on the compared reference instruction (decoded reference instruction) when the compared reference instruction matches the compared comparison instruction at each cycle time.

[0019] The bus control circuit 150 is a circuit that controls the bus of the processing circuit 100 .

[0020] In the first embodiment, the processing circuit 100 functions as follows: The fetch circuit 110 fetches, for each cycle time, two or more compare instructions corresponding to two or more different stagger times.

[0021] The comparison circuit 120 compares, for each cycle time, two or more fetched comparison instructions with a reference instruction fetched at a cycle time that is the shift time before the cycle time at which each of the two or more comparison instructions was fetched. The decode circuit 130 decodes the compared reference instruction for each cycle time if the compared reference instruction matches the two or more compared comparison instructions. The operation circuit 140 operates, for each cycle time, the compared reference instruction (decoded reference instruction) if the compared reference instruction matches the two or more compared comparison instructions.

[0022] The comparison circuit 120 selects an instruction to be operated by a majority vote between the compared reference instruction and the two or more compared instructions at each cycle time when the compared reference instruction does not match at least one of the two or more compared instructions. The decode circuit 130 decodes the instruction selected by the majority vote at each cycle time when the compared reference instruction does not match at least one of the two or more compared instructions. The operation circuit 140 operates the instruction selected by the majority vote (decoded instruction) at each cycle time when the compared reference instruction does not match at least one of the two or more compared instructions.

[0023] The comparison circuit 120 outputs an alert signal at each cycle time when the compared reference instruction does not match at least one of the two or more compared instructions. The output alert signal is input to the bus control circuit 150. When the alert signal is input, the bus control circuit 150 performs bus control for exception handling. For example, the bus control circuit 150 sets a program counter value for exception handling in the program counter.

[0024] 2, the configuration of the fetch circuit 110 will be described. The fetch circuit 110 includes a program counter group 111, an instruction memory 112, and a register group 113. The fetch circuit 110 is characterized by the program counter group 111 and the register group 113.

[0025] The program counter group 111 consists of two or more program counters. Each program counter stores a program counter value corresponding to each cycle time. One program counter in the program counter group 111 is called the main program counter. The main program counter stores the program counter value at each cycle time. The program counter value stored in the main program counter is called the main program counter value. The instruction stored in the memory area specified by the main program counter value is the reference instruction. Each program counter other than the main program counter is called a sub-program counter. The sub-program counter stores the main program counter value at a cycle time that is a shift time before the cycle time at each cycle time. The program counter value stored in the sub-program counter is called the sub-program counter value. The instruction stored in the memory area specified by the sub-program counter value is the comparison instruction.

[0026] The instruction memory 112 is a memory in which two or more instructions are stored in sequence.

[0027] The register group 113 is a plurality of registers. Each register stores one instruction for each cycle time. The register group 113 includes one or more registers for each program counter. The one or more registers for the main program counter store one or more reference instructions corresponding to one or more cycle times. The one or more registers for the sub-program counter store one or more comparison instructions corresponding to one or more cycle times.

[0028] 3 shows an example of the configuration of the fetch circuit 110. The program counter group 111 is made up of three program counters (PC). The register group 113 is made up of six registers (FR). The register group 113 includes the program counter PC ｔ Three registers (FR1 ｔ ~FR3 ｔ The register group 113 includes a program counter PC ｔ－１ Two registers (FR1 ｔ－１ , FR2 ｔ－１ The register group 113 includes a program counter PC ｔ－２ One register (FR1 ｔ－２ )

[0029] The decode circuit 130 includes an instruction decoder 131 and a register 132 (DR).

[0030] 3, "IF" means Instruction Fetch, "ID" means Instruction Decode, and "EX" means Execution.

[0031] ***Description of Operation*** The procedure of operation of the processing circuit 100 corresponds to a fault-tolerant processing method.

[0032] The fault tolerance processing method will be described with reference to FIG. ｔ is the main program counter, and the program counter (PC ｔ－１ , PC ｔ－２ ) is the sub-program counter. ｔ－１ The shift time is set to the time equivalent to one cycle. ｔ－２ The shift time is set to a time equivalent to two cycles.

[0033] At each cycle time t, the processing circuit 100 operates as follows: ｔ－２ is the program counter PC ｔ－１ The program counter value V stored inｔ－２ The program counter value V ｔ－２ is the program counter PC two cycles ago ｔ The program counter value of register FR1 ｔ－２ is the program counter value V ｔ－２ This register stores the instruction for the memory area specified by FR1. ｔ－２ The instruction stored in the instruction I1 is compared with the instruction I1. ｔ－２ The comparison instruction I1 ｔ－２ is the register FR1 at cycle time t. ｔ－２ This is the instruction fetched in

[0034] Register FR2 ｔ－１ is the register FR1 ｔ－１ Stores the instruction stored in register FR2. ｔ－１ The instruction stored in the instruction I2 is compared with the instruction I1. ｔ－１ The comparison instruction I2 is called ｔ－１ is the value of register FR1 one cycle before cycle time t. ｔ－１ The program counter PC is the instruction fetched in ｔ－１ is the program counter PC ｔ The program counter value V stored in ｔ－１ The program counter value V ｔ－１ is the program counter PC one cycle ago ｔ The program counter value of register FR1 ｔ－１ is the program counter value V ｔ－１ The instruction for the memory area specified by is stored.

[0035] Register FR3 ｔ is the register FR2 ｔ Stores the instruction stored in register FR3. ｔ The command stored in the standard command I3 ｔ It is called Standard Instruction I3. ｔ is set in register FR1 two cycles before cycle time t. ｔ This is the instruction fetched into register FR2. ｔ is the register FR1 ｔThe bus control circuit 150 stores the instruction stored in the program counter value V at cycle time t. ｔ Program counter PC ｔ Set the program counter PC ｔ is the program counter value V ｔ Stores the value in register FR1. ｔ is the program counter value V ｔ The instruction for the memory area specified by is stored.

[0036] The comparator circuit 120 includes register FR3 ｔ The standard instruction I3 stored in ｔ to register FR2 ｔ－１ The comparison instruction I2 stored in ｔ－１ and register FR1 ｔ－２ The comparison instruction I1 stored in ｔ－２ Compare with:

[0037] Standard command I3 ｔ and comparison instruction I2 ｔ－１ and comparison instruction I1 ｔ－２ If all of the reference instructions I3 and I4 match, the processing circuit 100 operates as follows: ｔ The standard instruction I3 output from the comparison circuit 120 ｔ is input to the instruction decoder 131. The instruction decoder 131 receives the standard instruction I3 ｔ The register 132 stores the decoded standard instruction I3 ｔ The arithmetic circuit 140 stores the standard instruction I3 stored in the register 132. ｔ The calculation result is input to the bus control circuit 150, for example.

[0038] Standard command I3 ｔ and comparison instruction I2 ｔ－１ and comparison instruction I1 ｔ－２ If only two of the instructions match, the processing circuit 100 operates as follows: ｔ and comparison instruction I2 ｔ－１ and comparison instruction I1 ｔ－２The comparison circuit 120 selects an instruction by majority vote and outputs the selected instruction. The output instruction is called a selected instruction. The instruction decoder 131 decodes the selected instruction. The register 132 stores the decoded selected instruction. The arithmetic circuit 140 performs an operation on the selected instruction stored in the register 132 and outputs the operation result. The comparison circuit 120 also outputs an alert signal. The output alert signal is input to the bus control circuit 150. The bus control circuit 150 performs bus control for exception handling.

[0039] Standard command I3 ｔ and comparison instruction I2 ｔ－１ and comparison instruction I1 ｔ－２ If none of the above match, the processing circuit 100 operates as follows: The comparison circuit 120 outputs an alert signal. The output alert signal is input to the bus control circuit 150. The bus control circuit 150 performs bus control for exception handling.

[0040] A specific example of the operation of the processing circuit 100 will be described with reference to FIG. 4. At cycle time t2, the register FR1 ｔ－２ stores instruction A, and register FR2 ｔ－１ stores instruction A, and register FR3 ｔ stores instruction A. That is, register FR1 ｔ－２ and register FR2 ｔ－１ and register FR3 ｔ All of the instructions match instruction A. In this case, instruction A is decoded, stored in register DR, and then executed.

[0041] The fault attack causes an error in the fetch at cycle time t4, and the three registers in the first stage (FR1 ｔ , FR1 ｔ－１ , FR1 ｔ－２ Assume that three instructions stored in register FR1 are corrupted. At cycle time t4, ｔ－２ stores instruction C', and register FR2 ｔ－１ stores instruction C, and register FR3 ｔ stores instruction C. That is, register FR1 ｔ－２ The instruction C' is in register FR2ｔ－１ and register FR3 ｔ In this case, instruction C is selected by majority vote, decoded, stored in register DR, and operated on. An alert signal is also output. At cycle time t5, ｔ－２ stores instruction D, and register FR2 ｔ－１ stores instruction D', and register FR3 ｔ stores instruction D. That is, register FR2 ｔ－１ The instruction D' is written to the register FR1. ｔ－２ and register FR3 ｔ In this case, instruction D is selected by majority vote, decoded, stored in register DR, and operated on. An alert signal is also output. At cycle time t6, ｔ－２ stores instruction E, and register FR2 ｔ－１ stores instruction E, and register FR3 ｔ stores instruction E'. That is, register FR3 ｔ The instruction E' is in register FR1 ｔ－２ and register FR2 ｔ－１ In this case, instruction E is selected by majority vote, decoded, stored in register DR, and executed. An alert signal is also output.

[0042] ***Comparison with Prior Art*** The configuration of a conventional processor is shown in Figure 5. In the conventional processor, the fetch circuit (IF) comprises one program counter PC and one register FR.

[0043] On the other hand, the processing circuit 100 is configured as follows (see FIG. 3): The fetch circuit 110 has two or more program counters PC and a plurality of registers FR. The fetch circuit 110 has two or more systems of fetch units. In FIG. 3, the first system of fetch units has a program counter PC ｔ and instruction memory 112 and three registers (FR1 ｔ , FR2 ｔ , FR3 ｔThe second fetch unit is composed of a program counter PC ｔ－１ and instruction memory 112 and two registers (FR1 ｔ－１ , FR2 ｔ－１ The third system fetch unit is composed of a program counter PC ｔ－２ and instruction memory 112 and one register FR1 ｔ－２ The fetch circuit 110 has two or more stages of fetch units. In FIG. 3, the first stage fetch unit (IF1) has three registers (FR1 ｔ , FR1 ｔ－１ , FR1 ｔ－２ The second stage fetch (IF2) has two registers (FR2 ｔ , FR2 ｔ－１ The third stage register section (IF3) has one register FR3 ｔ The fetch circuit 110 further includes a comparison circuit 120.

[0044] The difference between the operation of a conventional processor and the operation of the processing circuit 100 will be described with reference to FIG. 6. The conventional processor decodes and performs an operation on an instruction fetched by a fetch circuit (IF) at each cycle time. The processing circuit 100 fetches two or more instructions in different orders at each cycle time using two or more systems of fetch units (IF1, IF2, IF3). The processing circuit 100 fetches two or more instructions at different cycle times (t ０ , t １ , t ２ ) and compares two or more instructions fetched by the processor, and decodes and operates on the instruction selected by majority vote.

[0045] ***Effects of First Embodiment*** The first embodiment discloses a processing circuit 100 that is fault-tolerant.

[0046] The processing circuit 100 can protect fetches by making the fetches redundant.

[0047] The processing circuit 100 does not simply make fetching redundant, but fetches two or more different instructions simultaneously. Therefore, it is difficult to target a single instruction in the processing circuit 100 and cause an instruction skip, and other instructions fetched at the same time are likely to be erroneous. The processing circuit 100 does not simply reuse fetch modules for time redundancy, but rather pipelines the fetch module. Therefore, in order to inject a fault into the processing circuit 100 once and corrupt an instruction without the processing circuit 100 noticing the fault, it is necessary to similarly corrupt other instructions fetched at the same time. However, it is generally difficult to inject faults continuously by skillfully controlling the timing and strength to corrupt other instructions in the same way. Even if other instructions can be corrupted in the same way, new instructions fetched at the same time as the other instructions will likely also be corrupted, allowing the processing circuit 100 to notice the fault. Ultimately, to prevent the processing circuit 100 from detecting a fault, it is necessary to continually inject faults to maintain instruction consistency in the pipelined fetch module. However, this is not realistic. Therefore, the processing circuit 100 can notice the fetch fault, i.e., the processing circuit 100 can defend the fetch.

[0048] Furthermore, the processing circuit 100 can detect faults targeting stages other than the fetch stage. If a fault is introduced targeting a stage other than the fetch stage, the fetch stage, which tends to be a critical path, will also be broken. Therefore, by monitoring the fetch stage, it is possible to detect faults in stages other than the fetch stage.

[0049] ***Example of First Embodiment*** Figure 7 shows an example of the configuration of the processing circuit 100. The fetch circuit 110 may have two systems and two stages of fetch units as shown in Figure 7. In this case, the register FR2 ｔ Instruction and register FR1 ｔ－１ If the instructions in register FR2 match, the instruction is executed. ｔ Instruction and register FR1 ｔ－１If the instructions do not match, neither instruction is computed and an alert signal is output.

[0050] 8 shows an example of the configuration of the processing circuit 100. The fetch circuit 110 may have four or more systems and four or more stages of fetch units. In FIG. 8, the fetch circuit 110 has four systems and four stages of fetch units. In this case, the register FR4 ｔ Instruction and register FR3 ｔ－１ Instruction and register FR2 ｔ－２ Instruction and register FR1 ｔ－３ If the instructions in register FR4 match, the instruction is executed. ｔ Instruction and register FR3 ｔ－１ Instruction and register FR2 ｔ－２ Instruction and register FR1 ｔ－３ If the instructions in register FR4 do not match, the instruction is selected by majority vote and the selected instruction is executed. Furthermore, an alert signal is output. ｔ Instruction and register FR3 ｔ－１ Instruction and register FR2 ｔ－２ Instruction and register FR1 ｔ－３ If all of the instructions are different, then none of the instructions are calculated and an alert signal is output.

[0051] When the fetch circuit 110 has four or more systems of fetch units, the processing circuit 100 may operate as follows. The fetch circuit 110 fetches a reference instruction at each cycle time and also fetches three or more comparison instructions corresponding to three or more different shift times. The comparison circuit 120 randomly selects three or more instructions from the three or more fetched comparison instructions and a reference instruction fetched at a cycle time that is one shift time before the cycle time at which each of the two or more comparison instructions was fetched. The comparison circuit 120 then compares the selected three or more instructions. The decode circuit 130 decodes the compared instructions at each cycle time if the compared three or more instructions match. The calculation circuit 140 calculates the compared instructions (decoded instructions) at each cycle time if the compared three or more instructions match. If the compared three or more instructions do not match at each cycle time, the comparison circuit 120 selects an instruction to be calculated by a majority vote of the compared three or more instructions. The decode circuit 130 decodes the instruction selected by majority vote if three or more compared instructions do not match at each cycle time. The calculation circuit 140 calculates the instruction selected by majority vote (decoded instruction) if three or more compared instructions do not match at each cycle time. The comparison circuit 120 outputs an alert signal if three or more compared instructions do not match at each cycle time.

[0052] When the fetch circuit 110 has three or more systems of fetch units, the processing circuit 100 may operate as follows. The fetch circuit 110 fetches a reference instruction at each cycle time and fetches two or more comparison instructions corresponding to two or more different shift times. The comparison circuit 120 randomly selects two instructions from the two or more fetched comparison instructions and a reference instruction fetched at a cycle time that is one shift time before the cycle time at which each of the two or more comparison instructions was fetched. The comparison circuit 120 then compares the two selected instructions. The decode circuit 130 decodes the compared instructions at each cycle time if the two compared instructions match. The calculation circuit 140 calculates the compared instructions (decoded instructions) at each cycle time if the two compared instructions match. The comparison circuit 120 outputs an alert signal at each cycle time if the two compared instructions do not match.

[0053] 9 shows an example of the configuration of the processing circuit 100. The shift time between the systems may be a time equivalent to two or more cycles, not just one cycle. In FIG. 9, the fetch circuit 110 has two systems of fetch units, and the shift time between the systems is a time equivalent to two cycles. In this case, the fetch circuit 110 stores the reference instruction for each cycle time in a register FR1. ｔ At the same time, the fetch circuit 110 fetches the compare instruction at the cycle time two cycles before the cycle time into the register FR1. ｔ－２ Fetch to.

[0054] Even when the shift time between the systems is a time equivalent to two or more cycles, the fetch circuit 110 may have three systems of fetch units, or four or more systems of fetch units.

[0055] 10 shows an example of the configuration of an information processing device 200 equipped with the processing circuit 100. The processing circuit 100 is mainly used by being equipped in the information processing device 200. The information processing device 200 is a computer equipped with hardware such as the processing circuit 100, a memory 201, and an input / output interface 202.

[0056] *** Supplementary Note on First Embodiment *** First embodiment is an example of a preferred embodiment and is not intended to limit the technical scope of the present disclosure. Each embodiment may be implemented in part or in combination with other embodiments.

[0057] 100 Processing circuit, 110 Fetch circuit, 111 Program counter group, 112 Instruction memory, 113 Register group, 120 Comparison circuit, 130 Decode circuit, 131 Instruction decoder, 132 Register, 140 Arithmetic circuit, 150 Bus control circuit, 200 Information processing device, 201 Memory, 202 Input / output interface.

Claims

1. A processing circuit comprising: a fetch circuit which, for each cycle time, fetches an instruction at the cycle time as a reference instruction and fetches an instruction at a cycle time that is one or more cycles earlier than the cycle time as a comparison instruction; a comparison circuit which, for each cycle time, compares the fetched comparison instruction with a reference instruction fetched at a cycle time that is earlier than the cycle time at which the comparison instruction was fetched by the shift time; and an operation circuit which, for each cycle time, operates on the compared reference instruction when the compared reference instruction matches the compared comparison instruction.

2. The processing circuit of claim 1, wherein the comparison circuit outputs an alert signal when the compared reference instruction does not match the compared comparison instruction.

3. The processing circuit of claim 1, wherein the fetch circuit fetches, for each cycle time, two or more comparison instructions corresponding to two or more mutually different shift times; the comparison circuit compares, for each cycle time, the two or more fetched comparison instructions with a reference instruction fetched at a cycle time that is one shift time earlier than the cycle time at which each of the two or more comparison instructions was fetched; and the calculation circuit calculates, for each cycle time, the compared reference instruction when it matches the two or more compared comparison instructions.

4. The processing circuit according to claim 3, wherein the arithmetic circuit calculates, for each cycle time, an instruction selected by majority vote between the compared reference instruction and the compared two or more compared instructions when the compared reference instruction does not match at least any of the compared two or more compared instructions.

5. The processing circuit according to claim 3 or 4, wherein the comparison circuit outputs an alert signal when the compared reference instruction does not match at least any of the compared two or more comparison instructions at each cycle time.

6. The processing circuit according to claim 1, wherein the fetch circuit fetches the reference instruction for each cycle time and also fetches two or more comparison instructions corresponding to two or more different shift times; the comparison circuit randomly selects two instructions for each cycle time from the two or more fetched comparison instructions and a reference instruction fetched at a cycle time that is one shift time earlier than the cycle time at which each of the two or more comparison instructions was fetched, and compares the two selected instructions; and the calculation circuit calculates the compared instruction for each cycle time if the two compared instructions match.

7. The processing circuit of claim 6, wherein the comparison circuit outputs an alert signal every cycle time if the two compared instructions do not match.

8. The processing circuit according to claim 1, wherein the fetch circuit fetches the reference instruction for each cycle time and also fetches three or more comparison instructions corresponding to three or more different shift times; the comparison circuit randomly selects three or more instructions for each cycle time from the three or more fetched comparison instructions and a reference instruction fetched at a cycle time that is one shift time earlier than the cycle time at which each of the two or more comparison instructions was fetched, and compares the selected three or more instructions; and the calculation circuit calculates the compared instruction for each cycle time if the three or more compared instructions match.

9. The processing circuit according to claim 8, wherein the arithmetic circuit calculates, for each cycle time, an instruction selected by majority vote of the compared three or more instructions when the compared three or more instructions do not match.

10. The processing circuit according to claim 8 or 9, wherein the comparison circuit outputs an alert signal if the three or more compared instructions do not match at each cycle time.

11. A processing circuit according to any one of claims 1 to 10, which is a processor or an FPGA.

12. An information processing device equipped with the processing circuit according to any one of claims 1 to 11.

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