Coder, coding method and chip

Abstract

The present application relates to the technical field of coding. Disclosed are a coder, a coding method and a chip. In a scenario of a large bandwidth and high degree-of-parallelism input, the technical defect whereby a feedback loop in the coder cannot converge in time series does not occur. The coder comprises: a feedforward module, which is configured to receive, at a degree-of-parallelism of n symbols per cycle, data to be coded, and performing calculation in a finite field on the basis of symbols in said data received at the current cycle, so as to obtain a single-cycle polynomial corresponding to a current cycle; and a feedback module, which is configured to receive the single-cycle polynomial which is output by the feedforward module and corresponds to the current cycle, and performing calculation in the finite field on the basis of the single-cycle polynomial corresponding to the current cycle and a first polynomial representing symbols received at a historical cycle, so as to obtain a second polynomial, wherein the second polynomial is used for determining a target polynomial representing said data, and the target polynomial is used for generating a check sequence for said data, so as to obtain a code word obtained after said data is coded by means of forward error correction coding.

Description

Encoder, encoding method and chip

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on September 11, 2023, with application number 202311177437.8 and application name “An Encoder, Encoding Method and Chip”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of coding technology, and in particular to an encoder, a coding method and a chip. Background Art

[0003] In Ethernet-based data communications, to ensure reliable data transmission, the data transmitter can use forward error correction (FEC) to encode the data being transmitted. FEC is an error control technology that can self-correct and recover data when errors occur during data transmission.

[0004] With the development of information technologies such as cloud computing, big data, artificial intelligence, and the Internet of Things, the scale of global data is experiencing explosive growth. To improve data transmission efficiency, when performing FEC encoding on the data to be transmitted, the encoder receives the symbols of the data to be encoded in parallel to perform FEC encoding on the data to be encoded.

[0005] However, when the degree of parallelism of the symbols in the data to be encoded input to the encoder is large, there is a technical risk that the feedback loop in the current encoder may not be able to converge in timing.

[0006] Summary of the Invention

[0007] The present application provides an encoder, an encoding method, and a chip. In the scenario of large bandwidth and high parallel input, the feedback circuit in the encoder will not produce the technical defect of non-convergence in timing.

[0008] To achieve the above objectives, this application provides the following technical solutions:

[0009] In a first aspect, the present application provides an encoder comprising: a feedforward module for receiving data to be encoded with a parallelism of n (n is a positive integer) symbols per beat, and, based on the symbols in the data to be encoded received in the current beat, calculating a single-beat polynomial corresponding to the current beat in a finite field. Here, the single-beat polynomial represents the symbols received by the feedforward module in one beat. A feedback module for receiving the single-beat polynomial corresponding to the current beat output by the feedforward module, and calculating a second polynomial in a finite field based on the single-beat polynomial corresponding to the current beat and a first polynomial representing the symbols received in the historical beats. The second polynomial represents the symbols received from the first beat to the current beat, and the second polynomial is used to determine a target polynomial representing the data to be encoded. The target polynomial is used to generate a check sequence for the data to be encoded, and the check sequence for the data to be encoded is used to check and correct errors in the data to be encoded. The codeword obtained after encoding the data to be encoded using a forward error correction coding method includes the data to be encoded and the check sequence for the data to be encoded. In addition, the aforementioned first beat is the first beat of the data to be encoded received by the feedforward module, and the historical beats are the beats located between the current beats during the process of the feedforward module receiving the data to be encoded.

[0010] When the encoder provided by the present application is encoded, the target polynomial representing the data to be encoded is calculated by the feedforward module and the feedback module in the encoder. In addition, when the encoder calculates the target polynomial representing the data to be encoded by the feedforward module and the feedback module, the feedforward circuit calculates the corresponding single-beat polynomial according to the symbol received per beat, and the feedback module performs at least one iterative calculation on the single-beat polynomial output of the feedforward module, thereby calculating the target polynomial representing the data to be encoded. It can be seen that the feedback module has nothing to do with the number of symbols (i.e., parallelism) of the data to be encoded input to the feedforward module per beat, or is understood as the decoupling of the parallelism of the feedback module and the data to be encoded input to the feedforward module. In this way, in a large bandwidth scenario, even if the parallelism of the data to be encoded input to the encoder is very large, the amount of calculation of the feedback module will not become longer due to the increase in the parallelism, so that the feedback module will not produce a technical problem that the timing cannot converge.

[0011] In one possible design, the data to be encoded includes K symbols, where K is a positive integer. When the length of the codeword obtained after encoding the data using a forward error correction encoding method is N, and N is an integer greater than K, the encoder includes NK polynomial evaluation modules, each of which includes the aforementioned feedforward module and feedback module. Furthermore, the NK polynomial evaluation modules are configured to calculate, in a finite field, NK target polynomials representing the data to be encoded using the feedforward module and feedback module within each polynomial evaluation module.

[0012] In another possible design, when the codeword length obtained after encoding the data to be encoded using a forward error correction encoding method is N+ΔN, the encoder includes N+ΔN-K polynomial evaluation modules, each of which includes the above-mentioned feedforward module and feedback module. Furthermore, the N+ΔN-K polynomial evaluation modules are used to calculate N+ΔN-K target polynomials representing the data to be encoded in a finite field using the feedforward module and feedback module in each polynomial evaluation module. The N+ΔN-K polynomial evaluation modules include the above-mentioned NK polynomial evaluation modules.

[0013] Among them, for the RS(N,K) code type with a codeword length of N and a payload length of K, the error correction capability is (NK) / 2. For the RS(N+ΔN,K) code type with a codeword length of N+ΔN and a payload length of K, the error correction capability is (N+ΔN-K) / 2. Therefore, through the above two possible design methods, the encoder provided by the present application can realize that when encoding RS code types with different error correction capabilities, the polynomial evaluation module in the encoder of the RS code type with higher error correction capability can reuse the polynomial evaluation module in the encoder of the RS code type with lower error correction capability. That is, through the encoder design provided by the present application, it is possible to realize that the encoder of the RS code type with higher error correction capability and the encoder of the RS code type with lower error correction capability share a common (i.e., multiplexed) polynomial evaluation module, thereby being able to achieve significant savings in circuit area and power consumption in actual module implementation. The error correction capability when the encoded codeword length is (N+ΔN) is (N+ΔN-K), and the error correction capability when the encoded codeword length is N is N-K.

[0014] In another possible design, the encoder further includes a constant coefficient multiplication-addition module configured to calculate a check sequence for the data to be encoded based on the constant coefficient matrix and the target polynomial. A merging module configured to merge the data to be encoded and the check sequence for the data to be encoded to obtain a codeword for the data to be encoded using a forward error correction encoding method.

[0015] In another possible design, when the codeword length obtained after the data to be encoded using the forward error correction coding method is N, the constant coefficient matrix is ​​a first constant coefficient matrix of (NK)×(NK). When the codeword length after the data to be encoded using the forward error correction coding method is N+ΔN, the constant coefficient matrix is ​​a second constant coefficient matrix of (N+ΔN-K)×(N+ΔN-K). The second coefficient matrix includes the constant first coefficient matrix.

[0016] Through the above-mentioned possible design mode, the constant coefficient matrix (second constant coefficient matrix) preset in the encoder with high error correction capability in the present application includes the constant coefficient matrix (second constant coefficient matrix) preset in the encoder with low error correction capability. In this way, the encoder with high error correction capability and the encoder with low error correction capability provided by the present application can share a module constructed based on the same coefficient matrix, so that the encoder provided by the embodiment of the present application can not only encode forward error correction patterns with different error correction capabilities, but also save the circuit area and power consumption of the encoder.

[0017] In another possible design, the encoder supports encoding of at least one forward error correction coding pattern, and each pattern in the at least one forward error correction coding pattern has a different error correction capability.

[0018] Through this possible design, the encoder provided in the embodiment of the present application is a fusion encoder that can support forward error correction coding with multiple error correction capability code types.

[0019] In another possible design, when the value of n is greater than a threshold, the feedforward module includes a register, wherein the register is used to control the feedforward module to complete the calculation of a single-beat polynomial in at least two clock cycles.

[0020] This possible design ensures that the feedforward module of the encoder provided by this application completes the calculation of a single-beat polynomial using at least two clocks. In other words, in a high-bandwidth scenario, even if the degree of parallelism of the encoded data input to the encoder is large, the encoder provided by this application can still complete forward error correction coding.

[0021] In another possible design, when the codeword length obtained after the above-mentioned data to be encoded is encoded in an error correction coding manner is N, and the root of the primitive polynomial of the finite field is α, the first constant coefficient matrix is ​​pre-calculated based on the following formula:

[0022] In another possible design, the feedback module is specifically used when the first polynomial is A1, indicating that the polynomial of the symbol received in the current beat is A 2a When the second polynomial A2 is calculated by the following formula: A2 = A1 × (α i ) n +A 2a ; Among them, α i is a root of a generator polynomial in a finite field, and i is an integer in [0, NK-1].

[0023] This possible design shows that the feedback module in the encoder provided by this application is independent of the parallelism of the input data to be encoded, that is, the two are decoupled. Therefore, the length of the feedback module is fixed and does not increase with the increase in the parallelism of the input data to be encoded. Therefore, in the scenario of large bandwidth and high input parallelism, the feedback module in the encoder of this application will not cause the problem of non-convergence of timing.

[0024] In a second aspect, the present application provides an encoding method, which is applied to an encoder, the encoder comprising a feedforward module and a feedback module. The method comprises: receiving data to be encoded via the feedforward module with a parallelism of n (n is a positive integer) symbols per beat; and calculating a single-beat polynomial corresponding to the current beat in a finite field based on the symbols in the data to be encoded received in the current beat. Here, the single-beat polynomial represents the symbols received by the feedforward module in one beat. The feedback module receives the single-beat polynomial corresponding to the current beat output by the feedforward module, and calculates a second polynomial in a finite field based on the single-beat polynomial corresponding to the current beat and a first polynomial representing symbols received in previous beats. The second polynomial represents the symbols received from the first beat to the current beat, and the second polynomial is used to determine a target polynomial representing the data to be encoded. The target polynomial is used to generate a check sequence for the data to be encoded, and the check sequence for the data to be encoded is used to perform error correction on the data to be encoded. The codeword obtained after encoding the data to be encoded using a forward error correction encoding method includes the data to be encoded and the check sequence for the data to be encoded. In addition, the aforementioned first beat is the first beat of the data to be encoded received by the feedforward module, and the historical beat is the beat between the current beats during the process of the feedforward module receiving the data to be encoded.

[0025] In another possible design, the data to be encoded includes K symbols, where K is a positive integer. When the length of the codeword obtained after encoding the data to be encoded using a forward error correction encoding method is N, and N is an integer greater than K, the encoder includes NK polynomial evaluation modules, each of which includes the above-mentioned feedforward module and feedback module. Furthermore, the NK polynomial evaluation modules are configured to calculate, in a finite field, NK target polynomials representing the data to be encoded using the feedforward module and feedback module within each polynomial evaluation module.

[0026] In another possible design, when the codeword length obtained after encoding the data to be encoded using a forward error correction encoding method is N+ΔN, the encoder includes N+ΔN-K polynomial evaluation modules, each of which includes a feedforward module and a feedback module. Furthermore, the N+ΔN-K polynomial evaluation modules are used to calculate N+ΔN-K target polynomials representing the data to be encoded in a finite field using the feedforward module and feedback module in each polynomial evaluation module. The N+ΔN-K polynomial evaluation modules include the aforementioned NK polynomial evaluation modules.

[0027] In another possible design, the method further includes: when it is determined that the current beat is the K / nth beat of the data to be encoded, determining the second polynomial as the target polynomial. Based on the constant coefficient matrix and the target polynomial, a check sequence of the data to be encoded is calculated. The data to be encoded and the check sequence of the data to be encoded are combined to obtain a codeword after the data to be encoded is encoded using a forward error correction coding method. The value of K / n is specifically the value of the quotient of K / n rounded upward. It should be understood that if the current beat is the K / nth beat of the encoder receiving the data to be encoded, it means that the payload of a codeword has been completed. Correspondingly, if the current beat is not the K / nth beat of the encoder receiving the data to be encoded, it means that the payload of a codeword has not yet been completed.

[0028] In another possible design, when the codeword length obtained after the data to be encoded using the forward error correction coding method is N, the constant coefficient matrix is ​​a first constant coefficient matrix of (NK)×(NK). When the codeword length after the data to be encoded using the forward error correction coding method is N+ΔN, the constant coefficient matrix is ​​a second constant coefficient matrix of (N+ΔN-K)×(N+ΔN-K). The second constant coefficient matrix includes the constant first coefficient matrix.

[0029] In another possible design, the encoder supports encoding of at least one forward error correction coding pattern, and each pattern in the at least one forward error correction coding pattern has a different error correction capability.

[0030] In another possible design, when the value of n is greater than a threshold, the method further includes: controlling the feedforward module to complete calculation of a single-beat polynomial through at least two clock cycles through a register inserted in the feedforward module.

[0031] It should be understood that the description of the beneficial effects of the second aspect and any possible design thereof can refer to the description of the beneficial effects of the first aspect and any possible design thereof, and no further details will be given.

[0032] In a third aspect, the present application provides an encoding device. In a possible design, the encoding device is used to execute any one of the methods provided in the second aspect above. The present application can divide the encoding device into functional modules according to any one of the methods provided in the second aspect above. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. Exemplarily, the present application can divide the malicious domain name determination device into a receiving unit and a computing unit, etc. according to the function. The description of the possible technical solutions and beneficial effects executed by each of the divided functional modules can refer to the technical solutions provided by the second aspect or its corresponding possible design, and will not be repeated here.

[0033] In a fourth aspect, the present application provides a chip comprising a coding circuit, which is used to execute any of the methods provided in the second aspect and any possible design thereof, so as to realize encoding of the coded data in a forward error correction coding manner.

[0034] In a fifth aspect, the present application provides a computer-readable storage medium comprising program instructions, which, when executed on a computer or processor, enables the computer or processor to execute any method provided by any possible implementation in the second aspect.

[0035] In a sixth aspect, the present application provides a computer program product, which, when run on an encoding device, enables any method provided by any possible implementation manner in the second aspect to be executed.

[0036] In this application, the names of the aforementioned encoders, encoding devices, encoding circuits, etc. do not limit the devices or functional modules themselves. In actual implementation, these devices or functional modules may appear with other names. As long as the functions of each device or functional module are similar to those of this application, they are within the scope of the claims of this application and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] FIG1 is a schematic diagram of a current encoding circuit;

[0038] FIG2 is a schematic diagram of another current encoding circuit;

[0039] FIG3 is a diagram of an application scenario provided by an embodiment of the present application;

[0040] FIG4 is a schematic diagram of an application of the FEC encoding technology provided in an Ethernet architecture according to an embodiment of the present application;

[0041] FIG5 is a schematic diagram of another application of the FEC encoding technology provided in an Ethernet architecture according to an embodiment of the present application;

[0042] FIG6 is a schematic diagram of the architecture of a coding system provided in an embodiment of the present application;

[0043] FIG7 is a schematic diagram of the structure of a general-purpose computer provided in an embodiment of the present application;

[0044] FIG8 is a schematic diagram of an encoder provided in an embodiment of the present application;

[0045] FIG9 is a schematic diagram of a circuit structure of a feedforward circuit provided in an embodiment of the present application;

[0046] FIG10 is a schematic structural diagram of a feedforward circuit and a feedback circuit provided in an embodiment of the present application;

[0047] FIG11 is a schematic structural diagram of an encoder provided in an embodiment of the present application;

[0048] FIG12 is another structural diagram of an encoder provided in an embodiment of the present application;

[0049] FIG13 is another structural diagram of an encoder provided in an embodiment of the present application;

[0050] FIG14 is a schematic diagram of a feedforward circuit provided in an embodiment of the present application;

[0051] FIG15 is a schematic diagram showing the relationship between sets of polynomials representing payloads under different codeword lengths provided in an embodiment of the present application;

[0052] FIG16 is another schematic diagram of an encoder provided in an embodiment of the present application;

[0053] FIG17 is a schematic diagram showing the relationship between constant coefficient sets under different codeword lengths provided by an embodiment of the present application;

[0054] FIG18 is another schematic diagram of the structure of an encoder provided in an embodiment of the present application;

[0055] FIG19 is a schematic diagram of the structure of an encoder supporting multi-code type fusion encoding provided by an embodiment of the present application;

[0056] FIG20 is a schematic diagram of a flow chart of an encoding method provided in an embodiment of the present application;

[0057] FIG21 is a schematic diagram of a constant coefficient matrix of the RS (544, 514, 15, 10) code pattern provided in an embodiment of the present application;

[0058] Figure 22 is a structural diagram of an encoding device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0059] In order to better understand the embodiments of the present application, some of the terms or technologies involved in the embodiments of the present application are explained below:

[0060] 1) Forward error correction (FEC)

[0061] FEC, also known as forward error correction coding technology, is an error control technology.

[0062] FEC is widely used in communication systems to ensure the accuracy of transmitted data. The basic idea behind FEC is to add a check sequence of a certain length to the data being transmitted at the transmitting end, thereby generating a codeword after FRC encoding of the data. The FRC-encoded codeword consists of the data being transmitted and the check sequence. After the FRC-encoded codeword is transmitted to the receiving end, if any errors in the data fall within the correctable range of the check sequence, the receiving end corrects the errors using the decoded check sequence. This reduces the bit error rate (BER) and improves the reliability of the communication system.

[0063] Common FEC coding types include but are not limited to the following: Reed Solomon code (RS code), Hamming code, linear error correction code (low-density parity-check code), etc.

[0064] Taking the RS code as an example, a specific implementation scheme in the RS code FEC technology is a linear block cyclic code. The RS code can correct both random errors and burst errors, and is usually also referred to as RS FEC.

[0065] Among them, cyclic codes include but are not limited to RS codes, cyclic redundancy check (CRC) codes, forward error correction codes (Bose-Chaudhuri-Hocquenghem codes, BCH), Fire codes, etc. The basic unit that constitutes the codeword of a cyclic code is called a symbol. Therefore, the basic unit of RS code encoding and decoding calculations is also a symbol. Generally, a symbol contains m bits, where m is an integer greater than or equal to 1. It should be understood that when m=1, the meaning of symbol and bit is the same. As an example, for BCH, CRC code, Fire code, etc., m is usually 1. For RS code, m is usually greater than 1. Therefore, the basic unit of a cyclic code can be a bit, such as BCH, CRC, etc., or a symbol, such as RS code.

[0066] Specifically, the length of the RS code word refers to the number of symbols contained in the RS code, usually represented by the letter N. The payload length in the RS code word refers to the number of symbols contained in the payload of an RS code word, usually represented by the letter K. Among them, the payload in the RS code word refers to the original data information protected by the RS code. For example, the payload in the RS code word can be message data to be transmitted in a communication network, etc., but is not limited to this. In addition, the redundant length of the RS code word refers to the number of symbols contained in the check sequence in an RS code word, usually represented by the letter R. Here, the symbols in the check sequence are also called redundant symbols. Obviously, R=NK.

[0067] For ease of description, when the codeword length of an RS code is N and the payload length is K, it can be denoted as an RS(N,K) code. For example, the RS code pattern of KR4 is denoted as RS(528,514), indicating that the RS codeword length is 528 and the payload length is 514. For another example, the RS code pattern of KP4 is denoted as RS(544,514), indicating that the RS codeword length is 544 and the codeword information length is 514.

[0068] The error correction capability of an RS code refers to the maximum number of symbols that can be successfully corrected by an RS code word and are allowed to have errors, and is usually represented by T. For RS codes, the error correction capability T = (NK) / 2 (i.e., half the number of redundant symbols in the RS code word). For example, for the RS code pattern of KR4, the error correction capability T = (528-514) / 2 = 7, which means that the maximum number of symbols that can be corrected by an RS code word in the RS code pattern of KR4 and are allowed to have errors is 7. For another example, for the RS code pattern of KP4, the error correction capability T = (544-514) / 2 = 15, which means that the maximum number of symbols that can be corrected by an RS code word in the RS code pattern of KP4 and are allowed to have errors is 15.

[0069] In addition, the coding overhead of the FEC code refers to the ratio of the redundancy length in the FEC codeword to the payload length. That is, the coding overhead of the FEC code is ((NK) / K, or denoted as R / K).

[0070] The following briefly describes the encoding principle of a cyclic code by taking a cyclic code with a codeword length of N and a payload length of K as an example.

[0071] The payload of length K can be expressed as a polynomial M(x), which satisfies the following formula (1):

[0072] Formula (1) M(x) = m K-1 ·x K-1 +m K-2 ·x K-2 +…+m1·x+m0

[0073] Here, m represents the value of each symbol in the payload, and x represents the position of each symbol in the payload.

[0074] The preset generating polynomial of the cyclic code in the finite field is denoted as g(x), and g(x) satisfies the following formula (2):

[0075] Formula (2) g(x) = g N-K ·x N-K +g N-K-1 ·x N-K-1 +…+g1·x+g0

[0076] Here, g represents the coefficient of the generator polynomial, and x represents the position of each symbol in the check sequence.

[0077] Based on the polynomials shown in formulas (1) and (2), the encoding process of a cyclic code can be implemented by dividing M(x) and g(x) to obtain the remainder p(x). Here, p(x) is the cyclic code codeword check sequence. Therefore, the codeword polynomial of a cyclic code satisfies the following formula (3):

[0078] Formula (3)x N-K M(x) = q(x) g(x) + p(x)

[0079] Here, q(x) is the quotient of dividing M(x) and g(x).

[0080] Furthermore, the codeword polynomial of the cyclic code can be recorded as C(x), and C(x) satisfies the following formula (4):

[0081] Formula (4) C(x) = x N-K M(x)+p(x)

[0082] Thus, according to formula (4), the check sequence p(x) in the cyclic code word can be calculated as shown in formula (5). Wherein, MOD is the remainder operation.

[0083] Formula (5) p(x) = (x N-K ·M(x))MODg(x)

[0084] Thus, the check sequence p(x) of the payload data is obtained, and the encoded codeword can be obtained by combining the payload and the check sequence.

[0085] It should be noted that the calculation of polynomials in the above coding principles is the calculation of polynomials in a finite field.

[0086] Among them, the finite field is also called the Galois field, which is a field containing only a finite number of elements and can be obtained by GF(2 m ) means that the 2 m Represents an element in a finite field, and m is a positive integer. The addition of polynomials in a finite field is to combine like terms and perform either or operations on the coefficients, such as x 4 +x 4 = 0. Subtraction in a finite field is equal to addition, and there are no negative numbers in a finite field. For example, x 4 –x 4 is equal to x 4 +x 4 , -x 3 It's x 3 .

[0087] Furthermore, the RS code pattern can also be expressed as RS(N,K,T,m), where N is the code length of the RS codeword, K is the payload length in the RS codeword, T is the error correction capability of the RS code, and m is used to indicate the finite field for the RS encoding calculation.

[0088] 2) Feedforward circuit and feedback circuit

[0089] In the embodiments of the present application, when, in the time domain, the signal output by the circuit at time t1 does not affect the signal output at time t2, the circuit is called a feedforward circuit. When, in the time domain, the signal output by the circuit at time t1 affects the signal output at time t2, the circuit is called a feedback circuit. Here, time t2 is a time after time t1. For example, time t1 is the time before time t2.

[0090] 3) Shoot

[0091] The "beat" described in the embodiment of the present application refers to the rhythm, and the "beat" and "rhythm" in the embodiment of the present application can be replaced with each other.

[0092] Typically, one clock cycle is defined as one tick.

[0093] 4) Parallelism

[0094] The degree of parallelism described in the embodiments of the present application refers to the number of symbols of the data to be encoded that are allowed to be input to the encoder / encoding circuit in parallel in one tick. For example, when the degree of parallelism of the data to be encoded is n, it means that n symbols of the data to be encoded are allowed to be input to the encoder / encoding circuit in parallel in one tick.

[0095] When the degree of parallelism of the data to be encoded is n, and the number of symbols included in the data to be encoded is K, it means that the K symbols of the data to be encoded can be input to the encoder / encoding circuit in K / n beats. The specific value of K / n is the quotient of K / n rounded up. For example, when K is 10 and n is 4, the value of K / n is: the quotient of 10 / 4 (i.e., 2.5) rounded up (i.e., 3).

[0096] In this case, in a scenario where the degree of parallelism of inputting the data to be encoded into the encoder / encoding circuit is n and the number of symbols included in the data to be encoded is K, assuming that K can divide n evenly, then in the first beat, the 1st to nth symbols of the K symbols are allowed to be input into the encoder / encoding circuit in parallel; in the second beat, the (n+1)th to 2nth symbols of the K symbols are allowed to be input into the encoder / encoding circuit in parallel;…; in the [K / n]th beat, the symbols allowed to be input into the encoder / encoding circuit in parallel are the (K-n+1)th to Kth symbols.

[0097] 5) Other terms

[0098] In the embodiments of the present application, the terms "first" and "second" do not indicate a sequential relationship, but are used to distinguish different objects. The first, second, etc. mentioned in the following documents are also used to distinguish different messages, etc., and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0099] It should also be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0100] Currently, when FEC encoding is used for transmitted data, since the cyclic code encoding process is essentially a polynomial division calculation, the encoding circuit can be implemented as shown in Figure 1. As shown in Figure 1, taking the cyclic RS(N,K) code as an example, circuit 10 can serially receive K payload symbols over K clock cycles. During the input of the K payload symbols, the selector points to "1." As the K payload symbols are input, the K payload symbols are sequentially output from the selector over K clock cycles while entering circuit 10 for calculations by the multiplier and adder within circuit 10. When the K payload symbols have been input over K clock cycles, the values ​​stored in the NK registers within circuit 10 become the symbols of the check sequence. At this point, the selector switches to 0, and circuit 10 sequentially outputs the symbols of the check sequence over NK clock cycles, resulting in a complete RS codeword (consisting of K payload symbols and NK check sequences).

[0101] However, the coding efficiency of serially inputting the data to be transmitted into the encoder is too low. Therefore, when actually implementing cyclic code encoding, a parallel input coding architecture is often adopted. In other words, multiple payload symbols are input to the encoding circuit at the same time to improve coding efficiency. As an example, common parallel bit widths include 40 bits, 80 bits, and 160 bits. Therefore, when the parallel bit width is 40 bits, four payload symbols with a length of 10 bits can be input to the encoding circuit at the same time. When the parallel bit width is 80 bits, eight payload symbols with a length of 10 bits can be input to the encoding circuit at the same time. When the parallel bit width is 160 bits, 16 payload symbols with a length of 10 bits can be input to the encoding circuit at the same time.

[0102] Existing cyclic codes (such as RS codes and BCH codes) typically use the circuit structure shown in Figure 1, that is, a linear feedback shift register (LFSR) circuit for encoding. Based on this circuit, a parallel encoding calculation circuit can be derived for large bandwidth scenarios. As an example, based on the circuit structure shown in Figure 1, it can be deduced that when 32 symbols are input into the encoding circuit in parallel, the data calculation in the encoding circuit satisfies the following formula (6):

[0103] Formula (6)

[0104] Where REGicurrent represents the current value of the i-th register, and REGinext represents the value of the i-th register in the next clock cycle. Dj represents the j-th data currently input, where i = 1, 2, 3, ..., 14 (i.e., the number of symbols in the check sequence); j = 1, 2, 3, ..., 32 (i.e., the degree of parallelism). G is a 14×14 constant coefficient matrix, which can be expressed as the following matrix (1). H' is a 14×18 constant coefficient matrix, which can be expressed as the following matrix (2).

[0105] Matrix (1)

[0106] Matrix (2)

[0107] Furthermore, for RS (528, 514) encoding, when the payload is input to the encoding circuit in parallel as 32 symbols, the encoding circuit can be as shown in Figure 2. As shown in Figure 2, for the 32 symbols (including D1-D32) input to the encoding circuit in one clock cycle, D1-D18 are input to circuit 201 shown in Figure 2 to perform operations on the payload and the constant coefficient matrix H'. D19-D32 are respectively added to the feedback value of the previous clock cycle and then input to circuit 202 to perform operations on the payload and the constant coefficient matrix G. Furthermore, the calculation results of the constant coefficient matrix H' of D1-D18 and the calculation results of the constant coefficient matrix G of D19-D32 are added through 31 adders (such as the 31 adders included in block 203 shown in Figure 2) to output the calculation results of D1-D32. The feedback value of the previous clock cycle refers to the result calculated based on D1-D32 in the previous clock cycle. That is, the result of the operation in one clock cycle is used as the feedback value of the next clock cycle to participate in the operation of the next clock cycle. The loop used to obtain the feedback value can be called a feedback loop.

[0108] It can be seen that for each clock cycle of the encoder's input payload, the result of the regular coefficient matrix operation must be cascaded through n-1 adders (i.e., the result of the previous adder serves as the input to the next adder). Here, n is the number of symbols in the parallel input payload, or the degree of parallelism. Therefore, the length of the encoder's feedback loop is strongly correlated with the degree of parallelism of the encoder's input payload symbols. That is, the greater the number of symbols in the encoder's parallel input payload, the more addition operations (n-1 addition operations) are performed in the encoder's feedback loop, and thus, the longer the encoder's feedback loop. Consequently, when the number of symbols in the parallel input payload is large, the encoding circuit shown in Figure 2 cannot complete n-1 addition operations within a single clock cycle, resulting in a technical risk of non-convergence of the encoder's feedback loop timing.

[0109] In addition, for various FEC code types, such as the two RS FEC code types defined in the 802.3 standard: RS (528, 514) and RS (544, 514), the coefficients of the generating polynomials of these two code types in the finite field are completely different, so it is difficult to share the circuit resources (adders and multipliers) for implementing the encoding of these two code types. Referring to Table 1, Table 1 shows the values ​​of the coefficients of the generating polynomials of the RS (528, 514) code type and the RS (544, 514) code type. As shown in Table 1, the 15 (i∈[0,15]) coefficients of the RS (528, 514) code type generating polynomial and the 31 (i∈[0,30]) coefficients of the RS (544, 514) code type generating polynomial are all different. Where i is an integer. It should be understood that the coefficients of the generating polynomial are the coefficients g in the above polynomial (2).

[0110] Table 1

[0111] Based on this, an embodiment of the present application provides an encoder, which, when encoding, calculates a target polynomial representing the data to be encoded through a feedforward module and a feedback module in the encoder. Among them, the feedforward path is used to receive the data to be encoded with a parallelism of n symbols per beat, and calculates a single-beat polynomial corresponding to the current beat in a finite field based on the symbols in the data to be encoded received by the current beat. The feedback module is used to calculate the target polynomial representing the data to be encoded based on the single-beat polynomial corresponding to the current beat received from the feedforward module and the first polynomial representing the symbols received by the historical beat. In this way, the purpose of decoupling the feedback module in the encoder from the parallelism of the data to be encoded input to the encoder is achieved. That is, even if the number of symbols of the data to be encoded input to the encoder per beat is large, the length of the feedback module will not become longer, so that the feedback module will not produce the technical problem of timing convergence failure.

[0112] The data to be encoded may be data to be transmitted in a communication network, or data to be stored in a storage system (such as a distributed storage system), without limitation. The single-shot polynomial is used to represent the symbols received by the feedforward module in one shot.

[0113] With reference to Figure 3, Figure 3 shows an application scenario diagram of an embodiment of the present application. As shown in Figure 3, the payload data to be encoded is input into the encoder provided in the embodiment of the present application with a parallelism of n symbols per beat. Or it can be understood that the payload data to be encoded is input into the encoder provided in the embodiment of the present application with a parallelism of n per beat. Thus, the encoder performs forward error correction encoding on the payload data to be encoded, and outputs the encoded codeword of the data to be encoded, which includes the payload and the check sequence, and the payload is the data to be encoded. Furthermore, the encoded codeword can be transmitted or stored. It should be understood that since the feedback module in the encoder provided in the embodiment of the present application does not generate the technical risk of timing convergence failure, the encoder provided in the embodiment of the present application supports forward error correction encoding of the payload data to be encoded with high parallelism in a large bandwidth scenario.

[0114] Optionally, the process of encoding data by the encoder provided in the embodiment of the present application is generally applied to the media access control (MAC) sublayer and the physical layer (PHY) layer in the Ethernet architecture.

[0115] In one example, referring to FIG4 , FIG4 shows a schematic diagram of an application of the FEC coding technology provided by an embodiment of the present application in an Ethernet architecture. As shown in FIG4 , FIG4 shows a hierarchical architecture of an Ethernet network. In the Ethernet architecture, the functional division includes a MAC sublayer, a physical coding sublayer (PCS) sublayer, a physical medium attachment (PMA) sublayer, and a physical medium dependent (PMD) sublayer. Among them, the PCS, PMA, and PMD constitute the PHY layer. The FEC coding technology is applied to the MAC sublayer and PHY layer of the Ethernet architecture shown in FIG4 . For example, CRC coding is generally applied to the MAC sublayer in the Ethernet architecture shown in FIG4 , and RS coding is generally applied to the PCS sublayer in the Ethernet architecture shown in FIG4 , which will not be described in detail.

[0116] In another example, referring to FIG5 , FIG5 shows another schematic diagram of an application of the FEC coding technology provided by an embodiment of the present application in an Ethernet architecture. As shown in FIG5 , a standard Ethernet architecture includes an application layer, a presentation layer, a session layer, a transport layer, a network layer, a data link layer, and a physical layer. The data link layer includes a MAC sublayer and a reconciliation sublayer. The reconciliation sublayer is a special sublayer (equivalent to the top layer of the physical layer) responsible for handling the translation or mapping requirements between MII signaling and the MAC sublayer. The physical layer includes a PCS sublayer, a PMA sublayer, and a PMD sublayer. The FEC coding technology provided by an embodiment of the present application is applied to the MAC sublayer of the physical layer and the data link layer. For example, the RS encoder provided by an embodiment of the present application can be deployed in the PCS sublayer of the physical layer shown in FIG5 .

[0117] Optionally, the physical implementation of the encoder includes, but is not limited to, chips, integrated circuits, or computing devices or computing equipment with computing processing capabilities. As an example, chips include, but are not limited to, complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs), programmable array logic (PALs), generic array logic (GALs), network cards, microcontroller units (MCUs), and the like. Integrated circuits include, but are not limited to, application-specific integrated circuits (ASICs). Computing devices include, but are not limited to, general-purpose computers, laptops, tablet computers, and the like.

[0118] The present application also provides an encoding system including a controller and an encoder according to an embodiment of the present application. The controller controls the parallel input of symbols of data to be encoded into the encoder. The encoder then performs forward error correction encoding on the received data to be encoded. The specific process is described below and is not further elaborated here.

[0119] As an example, refer to Figure 6, which shows a schematic diagram of an encoding system 60 provided in an embodiment of the present application. As shown in Figure 6, the encoding system 60 includes a controller 610 and an encoder 620. Among them, the controller 610 controls the input of the symbols of the data to be encoded to the encoder 620 with a parallelism of n symbols per beat, where n is a positive integer. The encoder 620 performs forward error correction encoding on the data to be encoded based on the received data to be encoded, and outputs the encoded data. The specific process can be referred to the description below and will not be repeated here.

[0120] Optionally, the controller and encoder in the above-mentioned encoding system can be integrated into one device (such as a serdes chip (serdes is the abbreviation of SERializer / DESerializer)), or integrated into different devices, without limitation. Among them, the device can be a chip, an integrated circuit, or a computing device or computing equipment with computing processing capabilities, etc., without limitation. Among them, the detailed description of "chip, integrated circuit, or computing device or computing equipment with computing processing capabilities" can be referred to the above description and will not be repeated.

[0121] In one example, taking the above-mentioned encoding system as implemented by a general-purpose computer, reference is made to FIG7 , which shows a schematic diagram of the structure of a general-purpose computer 70 provided in an embodiment of the present application. As shown in FIG7 , the general-purpose computer 70 includes a processor 710, a memory 720, an encoder 730, a network / communication interface 740, and a bus 750. The processor 710, the memory 720, the encoder 730, and the network / communication interface 740 are connected via a bus 750.

[0122] The processor 710 is the control center of the general-purpose computer 70 and can be a general-purpose central processing unit (CPU). The processor 710 may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, graphics processing units (GPU), neural processing units (NPU), tensor processing units (TPU) or artificial intelligence (artificial intelligent) chips, data processing units (DPU), etc.

[0123] As an example, processor 710 includes one or more CPUs, such as CPU 0 and CPU 1 shown in FIG. 7 .

[0124] In addition, the processor 710 is used to implement the controller function in the above encoding system to control the parallel input of the data to be encoded to the encoder.

[0125] The memory 720 is used to store program instructions or data to be accessed by the application process, and the processor 710 can execute the program instructions in the memory 720. As an example, the memory 720 can be used to store data to be encoded and data that has been encoded.

[0126] The memory 720 includes volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. Among them, the volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory may be random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronized dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). Non-volatile memory can be storage class memory (SCM), solid state drive (SSD), hard disk drive (HDD), etc. Storage class memory can be, for example, non-volatile memory (NVM), phase-change memory (PCM), persistent memory, etc.

[0127] In one possible implementation, the memory 720 exists independently of the processor 710. The memory 720 is connected to the processor 710 via a bus 750 and is used to store data, instructions, or program codes. For example, the processor 710 controls the parallel input of the data to be encoded stored in the memory 720 to the encoder, and writes the data encoded by the encoder into the memory 720.

[0128] In another possible implementation, the memory 720 and the processor 710 are integrated together.

[0129] The encoder 730 is an encoder in the above encoding system, which is used to perform forward error correction encoding on the received data to be encoded and output the encoded codeword. The detailed description of the encoder can be found in the following description and is not repeated here.

[0130] Network / communication interface 740 is used to connect general-purpose computer 70 to other devices (such as devices for receiving encoded data) via a communication network. The communication network can be Ethernet, a radio access network (RAN), a wireless local area network (WLAN), etc. Network / communication interface 740 includes a receiving unit for receiving data / messages and a transmitting unit for sending data / messages.

[0131] Bus 750 can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, a high-speed serial computer expansion bus (PCIe), a Compute Express Link (CXL), or an Extended Industry Standard Architecture (EISA) bus. This bus can be classified as an address bus, a data bus, a control bus, etc. For ease of illustration, FIG7 shows only one thick line, but this does not mean that there is only one bus or only one type of bus.

[0132] It should be noted that the structure shown in FIG7 does not constitute a limitation on the general-purpose computer 70. In addition to the components shown in FIG7, the general-purpose computer 70 includes more or fewer components than those shown in FIG7, or combines certain components, or arranges the components differently.

[0133] The following, in conjunction with the accompanying drawings, describes in detail the encoder provided in the embodiments of the present application, using RS(N, K) code as an example for FEC encoding. RS(N, K) indicates that the encoded codeword length is N and the payload length is K. Accordingly, the length of the check sequence in the encoded codeword is NK. Both N and K are integers, and N is greater than K.

[0134] It should be understood that according to the definition of RS(N,K) code, the codeword C(x) after RS ​​encoding satisfies the mathematical constraints of formula (4) above. Therefore, the root α of the generating polynomial in the finite field is iSubstituting into formula (4), we can get formula (7), where i∈[0,NK-1].

[0135] Formula (7) C(α i )=(α i ) N-K ·M(α i )+p(α i )=0,i=0,1,2,….,NK-1

[0136] It should also be understood that the polynomial operations described in the embodiments of the present application are all operations of polynomials in a finite field. Based on this, (α i ) N-K ·M(α i )+p(αi)=0, we can get formula (8):

[0137] Formula (8)p(α i )=(α i ) N-K ·M(α i )i=0,1,2,….,NK-1

[0138] As can be seen from the above, the polynomial p(x) used to obtain the check sequence is the remainder of the division between the polynomial M(x) representing the payload and the generator polynomial g(x). Therefore, based on the polynomials (1) and (2) described above, the polynomial p(x) satisfies the following formula (9).

[0139] Formula (9) p(x) = p0 + p1x + p2x 2 +…+p N-K-1 x N-K-1

[0140] Therefore, the root α of the generating polynomial in the finite field will be i Substituting formula (9) and combining it with formula (8), we can obtain the following formula (10): where i∈[0,NK-1].

[0141] Formula 10

[0142] Furthermore, (α 0 ) N-K Moving to the left side of formula (10) and converting the operation into a matrix operation, we can obtain the following formula (11):

[0143] Formula (11)

[0144] After matrix operation, formula (11) can be obtained as formula (12):

[0145] Formula (12)

[0146] Based on formula (12), we introduce the symbols Θ, Φ, and Ω, and when implementing RS(N,K) coding, we make Θ N,K Satisfy formula (13), so that Φ N,K Satisfy formula (14), and make Ω N,K Satisfying formula (15):

[0147] Formula (13)

[0148] Formula (14)

[0149] Formula (15)

[0150] It can be seen that in the RS(N,K) code type, Θ N,K Indicates (NK) 2 A set of constant coefficients, Φ N,K The set of polynomials representing the payload in the RS codeword, Ω N,K Represents the check sequence in the RS codeword. And, from formula (12), formula (13), formula (14) and formula (15), we can know that Θ N,K , Φ N,K and Ω N,K Satisfy Ω N,K =Θ N,K ×Φ N,K mathematical constraints.

[0151] Therefore, the process of calculating the check sequence in the RS codeword in the RS encoding process can be converted into calculating Θ N,K ×Φ N,K In the specific implementation, the corresponding modules need to implement Θ N,K and Φ N,K Among them, Φ N,K The specific implementation module includes (NK) calculations for the polynomial M(α i ) module (hereinafter referred to as the polynomial evaluation module), i∈[0,NK-1]. Θ N,K Then the calculation (NK) is realized 2 constant coefficient θ j，1 ,θ j，2 ,θ j，3 ,….,θ j，N-K , j=1,2,…,NK.

[0152] Among them, M(α i ) is a polynomial representing the payload in a finite field.i is the root of the generator polynomial in the finite field, so α i Substituting into formula (1), we can get M(α i ):

[0153] Formula (16)M(α i )=m K-1 ·(α i ) K-1 +m K-2 ·(α i ) K-2 +…+m1·(α i )+m0

[0154] Based on this, in the embodiment of the present application, the polynomial M(α i The module that performs the polynomial evaluation is called a polynomial evaluation module. The polynomial evaluation module includes the feedforward module and feedback module described above. Optionally, the feedforward module and the feedback module can be implemented using hardware circuits or a combination of software and hardware circuits, without limitation. As an example, the feedforward module can be implemented using a feedforward circuit, and the feedback module can be implemented using a feedback circuit.

[0155] For simplicity, the following description of the embodiments of the present application uses an example in which the feedforward module in the encoder is a feedforward circuit, and the feedback module in the encoder is a feedback circuit. In this case, the polynomial evaluation module includes both the feedforward circuit and the feedback circuit. Therefore, the polynomial evaluation module is referred to as the polynomial evaluation circuit below.

[0156] 8 , which shows a schematic diagram of an encoder provided by an embodiment of the present application, as shown in FIG8 , the encoder 80 includes a feedforward circuit 810 and a feedback circuit 820 .

[0157] Among them, the feedforward circuit 810 is used to receive the data to be encoded with a parallelism of n symbols per beat. In this way, the feedforward circuit 810 can receive the data to be encoded through K / n beats. Among them, the data to be encoded (i.e., the payload data in the encoded codeword) includes K symbols, n and K are both positive integers, and K is greater than or equal to n. The value of K / n is specifically the value of the quotient of K / n rounded up. Therefore, the K / nth beat of receiving the data to be encoded is the last beat of receiving K symbols in the data to be encoded.

[0158] It should be understood that when encoding the data to be encoded, which includes K symbols, begins, the controller in the encoding system controls the data to be encoded to be input into the feedforward circuit 810 of the encoder 81 at n symbols per beat. A detailed description of the controller can be found above and will not be repeated here. In response, the feedforward circuit 810 receives the data to be encoded at a parallelism of n symbols per beat, and receives the data to be encoded over K / n beats.

[0159] The feedforward circuit 810 is further configured to calculate a single-beat polynomial corresponding to the current beat in a finite field based on the symbols in the data to be encoded received in the current beat. Here, the single-beat polynomial represents the symbols received by the feedforward module in one beat.

[0160] Specifically, the feedforward circuit 810 includes n multipliers, and the n multipliers are used to receive n symbols of the data to be encoded that are input to the feedforward circuit 810 with a parallelism of n. Based on formula (16), it can be seen that the n multipliers are used to multiply the received n symbols by the coefficients (α i ) u Then, the multiplication results are summed through n-1 adders to obtain a polynomial representing the n symbols input to the feedforward circuit 810 in a single shot, which is denoted as a single shot polynomial. Here, u∈[0,n-1].

[0161] It should be understood that the operation implemented by the feedforward circuit 810 is an operation in a finite field. i is the root of the generator polynomial used by the feedforward circuit 810 when performing finite field operations, i∈[0,NK-1]. α is the root of the primitive polynomial in the finite field. The finite field is GF(2 10 ) as an example, the primitive polynomial in this finite field is x 10 +x 3 +1, α is the root of the primitive polynomial, so the value of α can be solved based on the primitive polynomial. i The value of can also be calculated.

[0162] Furthermore, based on the K symbols of the data to be encoded input to the feedforward circuit 810 over K / n beats, the feedforward circuit can output K / n single-beat polynomials over K / n beats. That is, the feedforward circuit 810 can calculate a polynomial representing the symbols received in each beat (i.e., a single-beat polynomial) in a finite field.

[0163] Referring to Figure 9, Figure 9 shows a schematic diagram of the circuit structure of a feedforward circuit provided by an embodiment of the present application. As shown in Figure 9, m represents a symbol in the data to be encoded.

[0164] As shown in FIG9 , in the first beat, the feedforward circuit 810 receives the 1st to nth symbols of the data to be encoded, which are m K-1 、mK-2 ,…,m K-n Among them, m K-1 Through the multiplier and the coefficient (α i ) n-1 Multiplication, m K-2 Through the multiplier and the coefficient (α i ) n-2 Multiply, ..., m K-n Through the multiplier and the coefficient (α i ) 0 Multiply them and sum the multiplication results of n multipliers through n-1 adders, so as to obtain a single-beat polynomial representing the n symbols of the first beat input, that is, to obtain a single-beat polynomial corresponding to the first beat, which is recorded as B 1a .

[0165] Similarly, in the second beat, the feedforward circuit 810 receives the n+1th to 2nth symbols of the data to be encoded, which are m K-n- 1.m K-n-2 ,…,m K-2n Among them, m K-n-1 Through the multiplier and the coefficient (α i ) n-1 Multiplication, m K-n-2 Through the multiplier and the coefficient (α i ) n-2 Multiply, ..., m K-2n Through the multiplier and the coefficient (α i ) 0 Multiply them and sum the multiplication results of n multipliers through n-1 adders, so as to obtain a single-beat polynomial representing the n symbols of the second beat input, that is, to obtain a single-beat polynomial corresponding to the second beat, which is recorded as B 2a .

[0166] Similarly, in the K / nth beat, the feedforward circuit 810 receives the [(K / n)-1]×n+1 to (K / n)×n symbols in the data to be encoded, which are m n-1 、m n-2 ,…,m K-(K / n)×n . m K-(K / n)×n That is m0. Among them, m n-1 Through the multiplier and the coefficient (α i ) n-1 Multiplication, m n-2 Through the multiplier and the coefficient (α i ) n-2 Multiply, ..., m0 by the multiplier and the coefficient (α i ) 0Multiply them and sum the multiplication results of n multipliers through n-1 adders, so as to obtain a single-beat polynomial representing the n symbols of the K / n-th beat input, that is, to obtain a single-beat polynomial corresponding to the K / n-th beat, which is recorded as B (K / n)a .

[0167] It should be understood that in the process of inputting data to be encoded with a length of K symbols at a parallelism of n, the K / nth beat is the last beat. When the number of symbols in the data to be encoded input to the feedforward circuit 810 (referred to as "last-beat payload symbols") is less than n at the K / nth beat, the last-beat payload symbol can be set to the lower-order symbol of the n symbols input at the K / nth beat, and the bits of the n symbols input at the K / nth beat except for the bits used to set the last-beat payload symbol are padded with 0s, thereby inputting n symbols including the last-beat payload symbol to the encoder.

[0168] Feedback circuit 820 is used to receive the single-beat polynomial corresponding to the current beat output by the feedforward circuit, and calculate a second polynomial in a finite field based on the single-beat polynomial corresponding to the current beat and the first polynomial representing the symbols received in the historical beats. The second polynomial represents the symbols received from the first beat to the current beat, and the second polynomial is used to determine the polynomial representing the data to be encoded. Here, the first beat refers to the first beat of the data to be encoded received by the feedforward circuit, and the historical beat is the beat between the current beats in the process of receiving the data to be encoded by the feedforward circuit. As an example, assuming that the current beat is the third beat in the process of receiving the data to be encoded, the historical beat includes the first and second beats of the data to be encoded. As another example, assuming that the current beat is the fifth beat in the process of receiving the data to be encoded, the historical beat includes the first, second, third, and fourth beats of the data to be encoded.

[0169] Specifically, the feedback circuit 820 includes an adder and a multiplier. The implementation principle of the feedback circuit 820 is as follows: when the first polynomial is represented by A1, the second polynomial is represented by A2, and the single-beat polynomial representing the symbol received in the current beat is represented by A 2a When , the feedback circuit 820 is used to calculate the second polynomial A2 using the following formula (17):

[0170] Formula (17) A2=A1×(α i ) n +A 2a

[0171] It should be understood that the operation implemented by the feedback circuit 820 is an operation in a finite field. i is the root of the generator polynomial used by the feedback circuit 820 when performing finite field operations, i∈[0,NK-1]. α is the root of the primitive polynomial in the finite field. The process of solving α can be referred to the above description and will not be repeated here.

[0172] It should be noted that if the current beat is the K / nth beat, and the number of payload symbols in the last beat mentioned above is less than the parallelism n, then when calculating the second polynomial in the K / nth beat, (α i ) n The value of n in is the number of payload symbols at the end of the beat. For example, if the parallelism n is 10 and the number of payload symbols input at the K / nth beat (i.e., the payload symbols at the end of the beat) of the data to be encoded is 2, then when calculating the second polynomial corresponding to the K / nth beat, (α i ) n The value of n in is 2.

[0173] It can be seen that although in terms of timing, the calculation result of the current clock cycle of the feedback circuit 820 participates in the operation in the next clock cycle, the length of the feedback circuit 820 has nothing to do with the parallelism of the feedforward circuit 810 receiving the data to be encoded. In this way, even in a large bandwidth scenario, the parallelism of the data to be encoded input to the encoder is very large, and it will not affect the length of the feedback circuit in the encoder. In other words, the encoder provided in the embodiment of the present application realizes the decoupling of the parallelism of the data to be encoded input to the encoder and the feedback circuit in the encoder, so that in a large bandwidth scenario, when the high parallelism inputs the data to be encoded to the encoder, there will be no technical problem that cannot converge in timing. This is because the addition and multiplication operations that need to be completed by the feedback circuit in the encoder provided in the embodiment of the present application can be completed completely within one clock cycle.

[0174] Furthermore, the feedforward circuit 810 receives the data to be encoded in K / n beats, thereby outputting K / n single-beat polynomials. The feedback circuit then iterates (K / n)-1 times based on each single-beat polynomial output by the feedforward circuit 810 to calculate a polynomial representing the data to be encoded, referred to as the target polynomial. Furthermore, the target polynomial is used to generate a check sequence for the data to be encoded. The check sequence for the data to be encoded is used to check and correct errors in the data to be encoded. The codeword obtained after encoding the data to be encoded using a forward error correction encoding method includes the data to be encoded and the check sequence for the data to be encoded.

[0175] In combination with FIG9 , refer to FIG10 , which shows a schematic structural diagram of a feedforward circuit and a feedback circuit provided in an embodiment of the present application.

[0176] As shown in FIG10 , in the first beat, the feedback circuit 820 receives the single beat polynomial B of n symbols output by the feedforward circuit 810 representing the first beat input. 1a The feedback circuit 820 inputs 0 to the multiplier 1003 through the selector 1002. Then, the multiplier 1003 multiplies 0 and the coefficient (α i ) nPerform multiplication and output the multiplication result, which is 0. The adder 1001 adds the result 0 output by the multiplier 1003 and the single-shot polynomial B output by the feedforward circuit 810. 1a Perform addition operation to obtain the polynomial of the symbol of the data to be encoded input to the feedforward circuit 810 through the previous beat, which is recorded as B 1b .

[0177] In the second beat, the feedback circuit 820 receives the single-beat polynomial B of n symbols output by the feedforward circuit 810 representing the second beat input. 2a The feedback circuit 820 inputs the polynomial B calculated by the feedback circuit 820 at the first beat to the multiplier 1003 through the selector 1002. 1b It should be understood that the polynomial B calculated by the feedback circuit 820 at the first beat is 1b , which is the result of the calculation obtained by the adder 1001 of the feedback circuit 820 at the first beat. 1b and coefficient (α i ) n Perform multiplication and output the multiplication result. The result is B. 1b ×(α i ) n The adder 1001 adds the result B output by the multiplier 1003. 1b ×(α i ) n The single-beat polynomial B calculated by the feedforward circuit 810 for the n symbols input in the second beat 2a Perform addition operation to obtain the polynomial B of the symbol of the data to be encoded input to the feedforward circuit 810 through the first 2 beats 1b ×(α i ) n +B 2a , denoted as B 2b .

[0178] Similarly, at the K / nth beat, the feedback circuit 820 receives the single-beat polynomial B representing the n symbols input at the K / nth beat output by the feedforward circuit 810. (K / n)a The feedback circuit 820 inputs the polynomial B calculated by the feedback circuit 820 at the [(K / n)-1]th beat into the multiplier 1003 through the selector 1002. ((K / n)-1)b It should be understood that the polynomial B calculated by the feedback circuit 820 at the [(K / n)-1]th beat is ((K / n)-1)b , which is the calculation result output by the adder 1001 of the feedback circuit 820 at the [(K / n)-1]th beat. The multiplier 1003 ((K / n)-1)b and coefficient (α i ) nPerform multiplication and output the multiplication result. The result is B. ((K / n)-1)b ×(α i ) n The adder 1001 adds the result B output by the multiplier 1003. ((K / n)-1)b ×(α i ) n The single-beat polynomial B calculated by the feedforward circuit 810 for the n symbols input at the K / nth beat is (K / n)a Perform addition operation to obtain the polynomial B of K symbols of the data to be encoded input to the feedforward circuit 810 through K / n beats ((K / n)-1)b ×(α i ) n +B (K / n)a , denoted as B (K / n)b At this time, B (K / n)b This is the target polynomial mentioned above, and the feedback circuit 820 outputs the target polynomial.

[0179] The feedforward circuit 810 and the feedback circuit 820 in the encoder 80 constitute a polynomial evaluation circuit in the encoder 80 .

[0180] It should be understood that a polynomial evaluation circuit includes a feedforward circuit 810 and a feedback circuit 820. Furthermore, the feedforward circuit 810 and the feedback circuit 820 in the same polynomial evaluation circuit perform operations in the same finite field and use the same roots of the generator polynomial when performing the finite field operations. Thus, a target polynomial for the data to be encoded, which is input to the encoder 80 in parallel, can be calculated in the finite field using a single polynomial evaluation circuit.

[0181] To calculate the above Φ N,K In some embodiments, when the value of (NK) is 1, the encoder 80 includes a polynomial evaluation circuit. The roots of the generating polynomials used by the feedforward circuit and the feedback circuit in the polynomial evaluation circuit when performing finite field operations are α 0 .

[0182] In other embodiments, when the value of (NK) is greater than 1, the encoder 80 includes (NK) polynomial evaluation circuits. Thus, the (NK) polynomial evaluation circuits are used to calculate (NK) target polynomials representing the data to be encoded in a finite field using the feedforward circuit and feedback circuit in each of the (NK) polynomial evaluation circuits. Referring to FIG11 , FIG11 shows another schematic diagram of the structure of an encoder provided in an embodiment of the present application.

[0183] As shown in FIG11 , the encoder 80 includes (NK) polynomial evaluation circuits, namely polynomial evaluation circuit 0, polynomial evaluation circuit 1, ..., polynomial evaluation circuit (NK-2), and polynomial evaluation circuit (NK-1). The roots of the generating polynomial used by the feedforward circuit and the feedback circuit in the polynomial evaluation circuit 0 when performing finite field operations are α 0 The root of the generating polynomial used by the feedforward circuit and the feedback circuit in the polynomial evaluation circuit 1 when performing finite field operations is α 1 ,…, the roots of the generating polynomials used by the feedforward circuit and feedback circuit in the polynomial evaluation circuit (NK-2) when performing finite field operations are α N-K-2 , and the roots of the generating polynomials used by the feedforward circuit and the feedback circuit in the polynomial evaluation circuit (NK-1) when performing finite field operations are α N-K-1 In this way, the data to be encoded received by the encoder 80 through K / n beats can be input into each polynomial generation circuit in the (NK) polynomial evaluation circuits respectively, so as to calculate and output the corresponding target polynomial.

[0184] For example, the encoder 80 receives the data to be encoded in K / n beats and sequentially inputs them into the polynomial evaluation circuit 0, so that the polynomial evaluation circuit 0 calculates the root of the generating polynomial as α according to the data to be encoded received in K / n beats. 0 The target polynomial M(α 0 ).

[0185] Similarly, the encoder 80 receives the data to be encoded via K / n beats and sequentially inputs the data to be encoded into the polynomial evaluation circuit 1. Thus, the polynomial evaluation circuit 1 calculates the root of the generating polynomial as α based on the data to be encoded received via K / n beats. 1 The target polynomial M(α 1 ).

[0186] Similarly, the encoder 80 receives the data to be encoded in K / n beats and sequentially inputs them into the polynomial evaluation circuit (NK-2). Thus, the polynomial evaluation circuit (NK-2) calculates the root of the generating polynomial as α based on the data to be encoded received in K / n beats. N-K-2 The target polynomial M(α N-K-2 ).

[0187] Similarly, the encoder 80 receives the data to be encoded via K / n beats and sequentially inputs the data to be encoded into the polynomial evaluation circuit (NK-1). Thus, the polynomial evaluation circuit (NK-1) calculates the root of the generating polynomial as α based on the data to be encoded received via K / n beats. N-K-1 The target polynomial M(α N-K-1 ).

[0188] The polynomial evaluation circuit calculates the root of the generating polynomial as α according to the data to be encoded received in K / n beats. i The target polynomial M(α i ) for detailed description, please refer to the above description and will not be repeated here.

[0189] Furthermore, after (NK) target polynomials are calculated by the (NK) polynomial evaluation circuits, in order to implement the calculation of the check sequence of the to-be-encoded data using the (NK) target polynomials, referring to FIG12 , FIG12 shows another schematic diagram of the structure of the encoder provided in an embodiment of the present application. As shown in FIG12 , the encoder 80 further includes a constant coefficient multiplication and addition module 1210 and a merging module 1220.

[0190] The constant coefficient multiplication and addition module 1210 is used to calculate a check sequence for the data to be encoded based on the constant coefficient matrix and the target polynomial representing the data to be encoded. Specifically, the constant coefficient multiplication and addition module 1210 is used to calculate a check sequence for the data to be encoded based on the constant coefficient matrix and (NK) target polynomials representing the data to be encoded.

[0191] Here, the constant coefficient matrix is ​​the matrix Θ described in formula (13) above N,K , denoted as the first constant coefficient matrix, representing the (NK) target polynomials of the data to be encoded, which is the Φ mentioned above N,K Therefore, the constant coefficient multiplication and addition module 1210 is based on Θ N,K and Φ N,K , and the mathematical constraints Ω mentioned above N,K =Θ N,K ×Φ N,K Ω can be calculated N,K ,Ω N,K This is the check sequence of the data to be encoded.

[0192] Specifically, as shown in FIG12, when the data to be encoded is input to the encoder 80 with a parallel degree n, the (NK) polynomial evaluation circuits described above are calculated and (NK) target polynomials [including M(α 0 )、M(α 1 ),…,M(α N-K-2 )、M(α N-K-1 )], the constant coefficient multiplication and addition module 1210 receives the (NK) target polynomials and calculates the check sequence of the data to be encoded according to the first constant coefficient matrix and the (NK) target polynomials.

[0193] For RS(N,K), the first coefficient matrix Θ N,Kis a matrix of size (NK) × (NK). Therefore, in the encoder that implements RS(N,K) encoding, a first constant coefficient matrix is ​​preset. Each coefficient in the first constant coefficient matrix is ​​predetermined by formula (13). Since α is the root of the primitive polynomial in the finite field, when determining each coefficient in the first constant coefficient matrix, the root α can be solved based on the primitive polynomial of the finite field, and each coefficient in the first constant coefficient matrix can be determined based on α, constant N, constant K and formula (13). Assuming that the finite field is GF(2 10 ) as an example, the primitive polynomial in this finite field is x 10 +x 3 +1, so that the root α of the primitive polynomial can be solved based on the primitive polynomial. Then, each coefficient in the first constant coefficient matrix is ​​determined according to the solved α, constant N, constant K and formula (13).

[0194] Furthermore, based on the matrix operation principle, the constant coefficient multiplication and addition module 1210 is based on the above mathematical constraint relationship Ω N,K =Θ N,K ×Φ N,K Calculate Ω N,K That is, the constant coefficient multiplication and addition module 1210 includes (NK) submodules, each of which is used to calculate the coefficients corresponding to each submodule and the (NK) target polynomials (i.e., Φ) representing the data to be encoded. N,K ), calculate the corresponding check value. (NK) submodules obtain corresponding (NK) check values, and the (NK) check values ​​constitute the check sequence of the data to be encoded.

[0195] In conjunction with Figures 11 and 12, refer to Figure 13, which shows another schematic diagram of the structure of the encoder provided by an embodiment of the present application. As shown in Figure 13, the constant coefficient multiplication and addition module 1210 includes (NK) submodules, namely submodule 0, submodule 1, ..., submodule (NK-2), and submodule (NK-1). Among them, the coefficient corresponding to submodule 0 is the matrix Θ shown in formula (13) N,K The first row of coefficients in , that is, θ 1,1 ~θ 1,N-K , the coefficient corresponding to submodule 1 is the matrix Θ shown in formula (13) N,K The coefficients of the second row in θ 2,1 ~θ 2,N-K ,…, the coefficients corresponding to the submodule (NK-2) are the matrix Θ shown in formula (13) N,K The coefficients of the (NK-1)th row in the N-K-1,1 ~θ N-K-1,N-K , and the coefficients corresponding to the submodule (NK-1) are the matrix Θ shown in formula (13) N,KThe coefficients of the (NK)th row in θ N-K,1 ~θ N-K,N-K .

[0196] Thus, when the data to be encoded, which is input to the encoder 80 with K / N beats and a parallel degree of n, is calculated by the (NK) polynomial evaluation circuits described above, and (NK) target polynomials [including M(α 0 )、M(α 1 ),…,M(α N-K-2 )、M(α N-K-1 )], the encoder 80 sends the (NK) target polynomials to each submodule in the constant coefficient multiplication and addition module 1210, so that each submodule is encoded according to the coefficient corresponding to each submodule and the (NK) target polynomials (i.e., Φ N,K ), calculate the corresponding check value p. Then, the (NK) submodules obtain the corresponding (NK) check values ​​p, which constitute the check sequence of the data to be encoded.

[0197] For example, the encoder 80 sends (NK) target polynomials to the submodule 0 in the constant coefficient multiplication and addition module 1210, and the submodule 0 calculates the coefficients θ 1,1 ~θ 1,N-K Perform multiplication and addition operations with (NK) target polynomials to obtain the check value p N-K-1 Among them, based on Ω N,K =Θ N,K ×Φ N,K The mathematical constraints, formula (13) and formula (14), the multiplication and addition operation is specifically [θ 1,1 ×M(α 0 )+θ 1,2 ×M(α 1 )+…+θ 1,N-K-1 ×M(α N-K-2 )+θ 1,N-K ×M(α N-K-1 )] operation.

[0198] Similarly, the encoder 80 sends the (NK) target polynomials to the submodule 1 in the constant coefficient multiplication and addition module 1210, and the submodule 1 performs the multiplication and addition of the coefficients θ 2,1 ~θ 2,N-K Perform multiplication and addition operations with (NK) target polynomials to obtain the check value p N-K-2 .

[0199] Similarly, the encoder 80 sends the (NK) target polynomials to the submodule (NK-2) in the constant coefficient multiplication and addition module 1210, and the submodule (NK-2) performs the coefficient θ N-K-1,1 ~θ N-K-1,N-KPerform multiplication and addition operations with NK target polynomials to obtain the check value p1.

[0200] Similarly, the encoder 80 sends the (NK) target polynomials to the submodule (NK-1) in the constant coefficient multiplication and addition module 1210, and the submodule (NK-1) performs the multiplication of the coefficients θ N-K,1 ~θ N-K,N-K Perform multiplication and addition operations with NK target polynomials to obtain the check value p0.

[0201] The merging module 1220 is configured to merge the data to be coded and the check sequence of the data to be coded, thereby obtaining a codeword of the data to be coded using a forward error correction coding method.

[0202] Specifically, the merging module 1220 receives the check sequence of the data to be coded calculated by the constant coefficient multiplication and addition module 1210, and receives the data to be coded, and merges the data to be coded and the check sequence of the data to be coded, thereby obtaining a codeword after the data to be coded is encoded by the forward error correction coding method. Then, the merging module 1220 outputs a codeword including a payload and a check sequence. The payload of the codeword is the data to be coded, and the check sequence of the codeword is the check sequence of the data to be coded output by the constant coefficient multiplication and addition module 1210.

[0203] In this way, based on the encoder described above in the embodiment of the present application, when the encoder performs forward error correction coding on the data to be encoded input to the encoder in parallel, the feedback circuit in the encoder is decoupled from the parallelism of the data to be encoded when it is input to the encoder. Thus, in a large bandwidth scenario, when the encoder provided by the embodiment of the present application is input with high parallelism to the data to be encoded, there will be no technical problem of being unable to converge in timing. This is because the addition and multiplication operations that need to be completed by the feedback circuit in the encoder provided by the embodiment of the present application can be completed completely within one clock cycle.

[0204] However, the feedforward circuit in encoder 80 is related to the parallelism of the data to be encoded when it is input to encoder 80. Therefore, when the parallelism n of the data to be encoded when it is input to encoder 80 is greater than a threshold, the feedforward circuit in encoder 80 cannot complete the calculation of the single-beat polynomial within one clock cycle (also known as one beat or one tick). The specific value of the threshold is not limited in this embodiment of the present application.

[0205] In this case, the feedforward circuit 810 of the encoder 80 described above further includes a register, which is used to control the feedforward circuit 810 to complete the calculation of the polynomial representing the n symbols of the single-shot input (i.e., the single-shot polynomial) using at least two clock cycles. In other words, the register is used to control the feedforward circuit 810 to complete the calculation of a single-shot polynomial using at least two clock cycles. It should be understood that inserting a register into the feedforward circuit 810 can extend the duration of the feedforward circuit 810 by one clock cycle to complete the calculation of a single-shot polynomial. Inserting two registers into the feedforward circuit 810 can extend the duration of the feedforward circuit 810 by two clock cycles to complete the calculation of a single-shot polynomial.

[0206] In a first possible implementation, when feedforward circuit 810 can complete the calculation of a single-shot polynomial using at least two clock cycles, feedforward circuit 810 includes at least one delay register and multiple subcircuits, each of which can complete the computation within one clock cycle. Furthermore, the number of subcircuits in feedforward circuit 810 is the number of delay registers in feedforward circuit 810 plus one. For example, when feedforward circuit 810 includes one delay register, feedforward circuit 810 includes two subcircuits. For another example, when feedforward circuit 810 includes two delay registers, feedforward circuit 810 includes three subcircuits. Thus, by including at least one delay register in feedforward circuit 810, feedforward circuit 810 can complete the calculation of a single-shot polynomial within at least two clock cycles through pipelining of at least two subcircuits. Furthermore, the last subcircuit in the pipeline of feedforward circuit 810 is connected to feedback circuit 820 to output the single-shot polynomial to the feedback circuit. It should be understood that the working principle of the sub-circuit is the same as the working principle of the feedforward circuit 810 described above, and will not be described in detail.

[0207] Below, taking the case where the feedforward circuit 810 includes 1 register and the value of the parallelism n of the data to be encoded input to the encoder 80 is 4 as an example, the implementation process of the above-mentioned first possible implementation method is described. In conjunction with Figure 10, with reference to Figure 14, Figure 14 shows another schematic diagram of the feedforward circuit provided in an embodiment of the present application. Among them, the feedforward circuit 1400 is a feedforward circuit in which a register 1401 is inserted into the feedforward circuit 810 and n has a value of 4. The feedforward circuit 1400 includes a subcircuit 1410 and a subcircuit 1420, and the subcircuit 1420 is the last subcircuit on the feedforward circuit 1400 pipeline, so the subcircuit 1420 is connected to the feedback circuit.

[0208] Assume that the data to be encoded includes 12 symbols, and the 12 symbols are: m 11 、m 10, m9, m8, m7, m6, m5, m4, m3, m2, m1 and m0, then as shown in Figure 14, the data to be encoded needs to be input into the feedforward circuit 1400 of the encoder through (K / n)+1 beats (that is, (12 / 4)+1=4 beats).

[0209] In the first beat, the four symbols received by the feedforward circuit 1400 are m 11 、m 10 , 0, 0. Wherein, sub-circuit 1410 receives m 11 、m 10 , thereby calculating the result 1a, and sending the result 1a to sub-circuit 1420. Sub-circuit 1420 receives 0, 0, and the calculated result is actually 0 (or sub-circuit 1420 does not receive any symbols in the first beat). It should be noted that sub-circuit 1420 connected to the feedback circuit in the feedforward circuit 1400 does not output a result in the first beat.

[0210] In the second beat, the four symbols received by the feedforward circuit 1400 are m7, m6, m9, and m8. Among them, the sub-circuit 1410 receives m7 and m6, and calculates the result 2a, and sends the result 2a to the sub-circuit 1420. The sub-circuit 1420 receives m9 and m8 and calculates the result 1b. Then the sub-circuit 1420 sums the result 1b calculated in the second beat and the result 1a sent to the sub-circuit 1420 by the sub-circuit 1410 in the first beat, so as to obtain the result 1 in the second beat, and outputs the result 1 to the feedback circuit. It can be seen that the result 1 represents m 11 、m 10 , m9, m8, and the result 1 is the result calculated by the feedforward circuit 1400 over two clock cycles (beat 1 and beat 2). In other words, in beat 2, the sub-circuit 1420 in the feedforward circuit 1400 outputs a value representing m to the feedback circuit. 11 、m 10 , m9, and m8 are single-shot polynomials (i.e., result 1).

[0211] Similarly, in the third beat, the four symbols received by feedforward circuit 1400 are m3, m2, m5, and m4. Subcircuit 1410 receives m3 and m2, calculates result 3a, and sends result 3a to subcircuit 1420. Subcircuit 1420 receives m5 and m4 and calculates result 2b. Subcircuit 1420 then sums result 2b calculated in the third beat with result 2a sent to subcircuit 1420 by subcircuit 1410 in the second beat, thereby obtaining result 2 in the third beat, and outputs result 2 to the feedback circuit. It can be seen that result 2 is a single-beat polynomial representing m7, m6, m5, and m4, and is calculated by feedforward circuit 1400 over two clock cycles (beats 2 and 3). In other words, in the third beat, the sub-circuit 1420 in the feedforward circuit 1400 outputs a single-beat polynomial (ie, result 2) representing m7, m6, m5, and m4 to the feedback circuit.

[0212] Similarly, in the fourth beat, feedforward circuit 1400 receives four symbols: 0, 0, m1, and m0. Subcircuit 1410 receives 0 and 0, resulting in a calculated result of 0, which it then sends to subcircuit 1420. Subcircuit 1420 receives m1 and m0 and calculates result 3b. Subcircuit 1420 then sums result 3b calculated in the fourth beat with result 3a sent to it by subcircuit 1410 in the third beat, resulting in result 3 in the third beat. This result is then output to the feedback circuit. It can be seen that result 3 is a single-beat polynomial representing m3, m2, m1, and m0, and is calculated by feedforward circuit 1400 over two clock cycles (the third and fourth beats). In other words, in the fourth beat, subcircuit 1420 in feedforward circuit 1400 outputs a single-beat polynomial representing m3, m2, m1, and m0 (i.e., result 3) to the feedback circuit.

[0213] At this point, after 4 beats, all 12 characters in the data to be encoded are input into the feedforward circuit 1400, and the output represents m in the 2nd beat, 3rd beat and 4th beat respectively. 11 、m 10 , m9, and m8, single-beat polynomials representing m7, m6, m5, and m4, and single-beat polynomials representing m3, m2, m1, and m0. In this embodiment of the present application, the method of inputting the to-be-encoded data into the feedforward circuit 1400 shown in FIG. 14 is referred to as a half-beat input method. This method allows the calculation of a polynomial representing n symbols with a parallelism of n to be completed in two clock cycles (two beats).

[0214] By the above-mentioned implementation method, it is possible to ensure that the feedforward circuit 810 of the encoder 80 completes the calculation of the single-beat polynomial by at least two clocks. That is to say, in a large bandwidth scenario, even if the parallelism input to the encoder 80 is large, the encoder 80 provided in the embodiment of the present application can also complete forward error correction coding. Compared with the current coding circuit as shown in Figure 2, when the feedback loop cannot complete data calculation within a clock cycle, due to the constraint of the feedback loop in the time domain, the coding circuit shown in Figure 2 cannot insert a register into the feedback loop to extend the operating time of the feedback loop, so that the current technology has a technical defect that the time domain cannot converge in the scenario of large bandwidth high parallel input, and the encoder provided in the embodiment of the present application does not have this technical defect.

[0215] In other embodiments, the RS(N+ΔN,K) code pattern is described. RS(N+ΔN,K) indicates that the encoded codeword length is N+ΔN and the payload length is K. Accordingly, the length of the check sequence in the encoded codeword is N+ΔN-K. N, ΔN, and K are all integers, and N is greater than K.

[0216] Based on the above introduction to the RS(N,K) code type, when implementing RS(N+ΔN,K) encoding, Θ N+ΔN,K Satisfy formula (18), so that Φ N+ΔN,K Satisfy formula (19), and make Ω N+ΔN,K Satisfies formula (20). Where, Θ N+ΔN,K To convert Θ shown in the above formula (13) N,K Replace N in (N+ΔN) to obtain Φ N+ΔN,K To convert the Φ shown in the above formula (14) N,K Replace N in (N+ΔN) to get, and Ω N+ΔN,K To convert the Ω shown in the above formula (15) N,K Replace N in (N+ΔN) to obtain.

[0217] Formula (18)

[0218] Formula (19)

[0219] Formula (20)

[0220] It can be seen that in the RS(N+ΔN,K) code type, Θ N+ΔN,K represents (N+ΔN-K) 2 A set of constant coefficients, Φ N+ΔN,K The set of polynomials representing the payload in the RS codeword, Ω N+ΔN,K represents the check sequence in the RS codeword. And, ΘN+ΔN,K , Φ N+ΔN,K and Ω N+ΔN,K Satisfy Ω N+ΔN,K =Θ N+ΔN,K ×Φ N+ΔN,K mathematical constraints.

[0221] Thus, for the RS(N+ΔN,K) code type, that is, when the codeword length obtained after the data to be encoded is encoded in a forward error correction encoding method is N+ΔN, and the payload length is K, the encoder used to implement RS(N+ΔN,K) encoding includes (N+ΔN-K) polynomial evaluation circuits, and each of the (N+ΔN-K) polynomial evaluation circuits includes the feedforward circuit and feedback circuit described above. Thus, the (N+ΔN-K) polynomial evaluation circuits are used to calculate (N+ΔN-K) target polynomials representing the data to be encoded in a finite field through the feedforward circuit and feedback circuit in each polynomial evaluation circuit, that is, to obtain Φ N+ΔN,K The detailed description of the structure and working principle of the feedforward circuit, feedback circuit, and polynomial evaluation circuit can be found in the above description and will not be repeated here.

[0222] From formula (14) and formula (19), we can know that Φ N+ΔN,K Including Φ N,K , specifically refer to FIG15, FIG15 is a diagram showing the relationship between a set of polynomials representing payloads under different codeword lengths provided by an embodiment of the present application. As shown in FIG15, Φ N,K is Φ N+ΔN,K Part of Φ N+ΔN,K Including Φ N,K .

[0223] Given that Φ N+ΔN,K Including Φ N,K The (N+ΔN-K) polynomial evaluation circuits in the encoder for implementing RS(N+ΔN,K) encoding include the (NK) polynomial evaluation circuits in the encoder for implementing RS(N,K) encoding. In other words, the (N+ΔN-K) polynomial evaluation circuits in the encoder for implementing RS(N+ΔN,K) encoding can reuse the (NK) polynomial evaluation circuits in the encoder for implementing RS(N,K) encoding.

[0224] Referring to Figure 16, Figure 16 shows a schematic diagram of the structure of the encoder 1600 provided in an embodiment of the present application. The encoder 1600 is an encoder that implements RS (N + ΔN, K) encoding. As shown in Figure 16, in addition to the (NK) polynomial evaluation circuits in the encoder 80 described above, the encoder 1600 also includes ΔN polynomial evaluation circuits, namely: polynomial evaluation circuit (NK), ..., and polynomial evaluation circuit (N + ΔN-K-1). The encoder 1600 also includes a constant coefficient multiplication and addition module 1610 and a merging module 1620. The detailed description of the constant coefficient multiplication and addition module 1610 and the merging module 1620 can be referred to above and will not be repeated here.

[0225] The polynomial evaluation circuit (NK) is used to calculate the root of the generating polynomial α according to the data to be encoded received at K / n beats. N-K The target polynomial M(α N-K The polynomial evaluation circuit (N+ΔN-K-1) is used to calculate the root of the generating polynomial as α according to the data to be encoded received by K / n beats. N+ΔN-K-1 The target polynomial M(α N+ΔN-K-1 ).

[0226] It can be seen that the polynomial evaluation circuit for (N+ΔN-K) in the encoder 1600 for implementing the RS(N+ΔN,K) code pattern encoding includes the polynomial evaluation circuit for (NK) in the encoder 80 for implementing the RS(N,K) code pattern encoding. Since (N+ΔN-K) / 2 is the error correction capability of the RS(N+ΔN,K) code pattern, and (NK) / 2 is the error correction capability of RS(N,K), the error correction capability of the RS(N+ΔN,K) code pattern is higher than the error correction capability of RS(N,K). Therefore, the encoder provided by the embodiment of the present application can achieve that when encoding RS code patterns with different error correction capabilities, the polynomial evaluation circuit in the encoder of the RS code pattern with higher error correction capability can reuse the polynomial evaluation circuit in the encoder of the RS code pattern with lower error correction capability. That is, through the encoder design provided in the embodiment of the present application, it is possible to achieve that an encoder for an RS code type with a higher error correction capability and an encoder for an RS code type with a lower error correction capability share a common (i.e., multiplexed) polynomial evaluation circuit, thereby achieving significant savings in circuit area and circuit power consumption in actual circuit implementation.

[0227] In addition, for the RS(N+ΔN,K) code type, that is, when the codeword length obtained after the data to be encoded is encoded in the forward error correction coding mode is N+ΔN and the payload length is K, the constant coefficient matrix preset in the constant coefficient multiplication and addition module of the encoder for implementing the RS(N+ΔN,K) encoding is the above-mentioned matrix Θ N+ΔN,K , recorded as the second constant coefficient matrix. From formula (18), we can see that the second constant coefficient matrix ΘN+ΔN,K It is a matrix of size (N+ΔN-K)×(N+ΔN-K).

[0228] From formula (13) and formula (18), we can see that Θ N+ΔN,K Including Θ N,K , specifically refer to FIG17, FIG17 shows a schematic diagram of the relationship between a constant coefficient set under different codeword lengths provided by an embodiment of the present application. As shown in FIG17, Θ N,K is Θ N+ΔN,K Part of Θ N+ΔN,K Including Θ N,K .

[0229] Given Θ N+ΔN,K Including Θ N,K , a second constant coefficient matrix Θ preset in a constant coefficient multiplication and addition module in an encoder for implementing RS (N + ΔN, K) encoding N+ΔN,K , including a first constant coefficient matrix Θ preset in a constant coefficient multiplication and addition module in an encoder for implementing RS (N, K) encoding N,K That is, the second constant coefficient matrix Θ preset in the constant coefficient multiplication and addition module in the encoder for implementing RS (N + ΔN, K) encoding N+ΔN,K , the first constant coefficient matrix Θ preset in the constant coefficient multiplication and addition module in the encoder for implementing RS (N, K) coding can be reused N,K .

[0230] In conjunction with Figure 16, refer to Figure 18, which shows another structural diagram of the encoder 1600 provided in an embodiment of the present application. The encoder 1600 is an encoder that implements RS (N + ΔN, K) encoding. As shown in Figure 18, the constant coefficient multiplication and addition module 1610 in the encoder 1600 includes (N + ΔN-K) submodules, namely submodule 0, submodule 1, ..., submodule (NK-2), submodule (NK-1), submodule (NK), ..., and submodule (N + ΔN-K-1). Among them, the coefficient corresponding to submodule 0 is the matrix Θ shown in formula (18) N+ΔN,K The first row of coefficients in , that is, θ 1,1 ~θ 1,N-K ~θ 1,N+ΔN-K , the coefficient corresponding to submodule 1 is the matrix Θ shown in formula (18) N+ΔN,K The second row of coefficients in θ 2,1 ~θ 2,N-K ~θ 2,N+ΔN-K ,…, the coefficients corresponding to the submodule (NK-2) are the matrix Θ shown in formula (18) N+ΔN,K The coefficients of the (NK-1)th row in the N-K-1,1 ~θ N-K-1,N-K~θN-K-1,N+ΔN-K, the coefficient corresponding to the submodule (NK-1) is the matrix Θ shown in formula (18) N+ΔN,K The coefficients of the (NK)th row in θ N-K,1 ~θ N-K,N-K The coefficients corresponding to the submodule (NK) are the matrix Θ shown in formula (18) N+ΔN,K The (N+1-K)th row coefficient in θ N+1-K,1 ~θ N+1-K,N-K ~θ N+1- K,N+ΔN-K , ..., and the coefficients corresponding to the submodule (N+ΔN-K-1) are the matrix Θ shown in formula (18) N+ΔN,K The (N+ΔN-K)th row coefficient in θ N+ΔN-K,1 ~θN+ΔN-K,NK~θN+ΔN-K,N+ΔN-K.

[0231] Thus, when the data to be encoded, which is input to the encoder 1600 with K / N beats and a parallelism of n, is calculated by the (N+ΔN-K) polynomial evaluation circuits described above, and (N+ΔN-K) target polynomials [including M(α 0 )、M(α 1 ),…,M(α N-K-2 )、M(α N-K-1 )、M(α N-K ),…,M(α N+ΔN-K-1 )], the encoder 1600 sends the (N+ΔN-K) target polynomials to each submodule in the constant coefficient multiplication and addition module 1610, so that each submodule is encoded according to the coefficients corresponding to each submodule and the (N+ΔN-K) target polynomials (i.e., Θ N+ΔN,K ), calculate the corresponding check value p. Then, the (N+ΔN-K) submodules obtain the corresponding (N+ΔN-K) check values ​​p, which constitute the check sequence of the data to be encoded.

[0232] For example, the encoder 1600 sends (N+ΔN-K) target polynomials to the submodule 0 in the constant coefficient multiplication and addition module 1610, and the submodule 0 calculates the coefficients (θ 1,1 ~θ 1,N-K ~θ 1,N+ΔN-K ) and (N+ΔN-K) target polynomials to obtain the check value p N+ΔN-K-1 Among them, based on Ω N+ΔN,K =Θ N+ΔN,K ×Φ N+ΔN,K The mathematical constraints, formula (18) and formula (19), the multiplication and addition operation is specifically [θ 1,1 ×M(α 0)+θ 1,2 ×M(α 1 )+…+θ 1,N-K-1 ×M(α N-K-2 )+θ 1,N-K ×M(α N-K-1 )+θ 1,N+1-K ×M(α N-K )+θ 1,N+ΔN-K ×M(α N+ΔN–K-1 )] operation.

[0233] Similarly, the encoder 1600 sends (N+ΔN-K) target polynomials to the submodule 1 in the constant coefficient multiplication and addition module 1610, and the submodule 1 performs the multiplication and addition of coefficients (θ 2,1 ~θ 2,N-K ~θ 2,N+ΔN-K ) and (N+ΔN-K) target polynomials are multiplied and added to obtain the check value pN+ΔN-K-2.

[0234] Similarly, the encoder 1600 sends the (N+ΔN-K) target polynomials to the submodule (NK-2) in the constant coefficient multiplication and addition module 1610, and the submodule (NK-2) performs the multiplication and addition of the coefficients (θ N-K-1,1 ~θ N-K-1,N-K ~θN-K-1,N+ΔN-K) and (N+ΔN-K) target polynomials are multiplied and added to obtain the check value p ΔN+1 .

[0235] Similarly, the encoder 1600 sends the (N+ΔN-K) target polynomials to the submodule (NK-1) in the constant coefficient multiplication and addition module 1610, and the submodule (NK-1) performs the multiplication and addition of the coefficients (θ N-K,1 ~θ N-K,N-K ~θN-K,N+ΔN-K) and (N+ΔN-K) target polynomials are multiplied and added to obtain the check value p ΔN .

[0236] Similarly, the encoder 1600 sends (N+ΔN-K) target polynomials to the submodule (NK) in the constant coefficient multiplication and addition module 1610, and the submodule (NK) performs the multiplication and addition of the coefficients (θ N+1-K,1 ~θ N+1-K,N-K ~θN+1-K,N+ΔN-K) and (N+ΔN-K) target polynomials are multiplied and added to obtain the check value p ΔN-1 .

[0237] Similarly, the encoder 1600 sends the (N+ΔN-K) target polynomials to the submodule (N+ΔN-K-1) in the constant coefficient multiplication and addition module 1610, and the submodule (N+ΔN-K-1) multiplies the coefficients (θ N+ΔN-K,1~θN+ΔN-K,NK~θN+ΔN-K,N+ΔN-K) and (N+ΔN-K) target polynomials are multiplied and added to obtain the check value p0.

[0238] As can be seen from the description of FIG13 , the constant coefficient multiplication and addition module 1610 in the encoder for implementing the RS(N+ΔN,K) code pattern includes a specific implementation circuit of the constant coefficient multiplication and addition module 1210 in the encoder for implementing the RS(N,K) code pattern. For example, taking submodule 0 in the constant coefficient multiplication and addition module 1610 as an example, submodule 0 in the constant coefficient multiplication and addition module 1610 includes a specific implementation circuit of submodule 0 in the constant coefficient multiplication and addition module 1210 shown in FIG13 , and the implementation circuit is used to implement the constant coefficient multiplication and addition module 1210 with the coefficient (θ 1,1 ~θ 1,N-K ) is a circuit for performing multiplication and addition. For another example, taking the submodule (NK-1) in the constant coefficient multiplication and addition module 1610 as an example, the submodule (NK-1) in the constant coefficient multiplication and addition module 1610 includes a specific implementation circuit of the submodule (NK-1) in the constant coefficient multiplication and addition module 1210 shown in FIG13 , and the implementation circuit is used to implement the multiplication and addition with the coefficient (θ N-K,1 ~θ N-K,N-K ) circuit for performing multiplication and addition.

[0239] That is, the (N+ΔN-K) submodules in the constant coefficient multiplication and addition module in encoder 1600 each include (NK) submodules in the constant coefficient multiplication and addition module in encoder 80. Since the error correction capability [(N+ΔN-K) / 2] of encoder 1600 for implementing RS(N+ΔN,K) code pattern encoding is higher than the error correction capability [(NK) / 2] of encoder 80 for implementing RS(N,K) code pattern encoding, the constant coefficient multiplication and addition module 1610 in encoder 1600 with higher error correction capability can reuse the specific implementation circuit of the constant coefficient multiplication and addition module 1210 in encoder 80 with lower error correction capability. In other words, the encoder provided by the embodiments of the present application can achieve that when encoding RS code patterns with different error correction capabilities, the constant coefficient multiplication and addition module in the encoder for the RS code pattern with higher error correction capability can reuse the constant coefficient multiplication and addition module in the encoder for the RS code pattern with lower error correction capability. That is, through the encoder design provided in the embodiment of the present application, it is possible to achieve an encoder for an RS code type with higher error correction capability and an encoder for an RS code type with lower error correction capability sharing a common (i.e., multiplexed) constant coefficient multiplication and addition module implementation circuit, thereby achieving significant savings in circuit area and circuit power consumption in actual circuit implementation.

[0240] Furthermore, in conjunction with Figures 15 to 18, the encoder for realizing the RS(N+ΔN, K) code type with higher error correction capability provided by the embodiment of the present application can reuse the circuit of the polynomial evaluation circuit and the constant coefficient multiplication and addition module in the encoder for realizing the RS(N, K) code type with lower error correction capability. In this way, by realizing the encoder of the RS(N+ΔN, K) code type with higher error correction capability, the encoding of the RS(N, K) code type with lower error correction capability can be realized. That is, the encoder described in the embodiment of the present application can support the encoding of at least one forward error correction coding code type, and each code type in the at least one forward error correction coding code type has different error correction capabilities. Alternatively, it can be understood that the encoder provided in the embodiment of the present application is a fusion encoder that can support forward error correction coding of multiple error correction capability code types.

[0241] As an example, when the encoder provided in an embodiment of the present application is an encoder for implementing the RS(N+ΔN,K) code type, the encoder supports encoding of at least one forward error correction coding code type. Wherein, each code type in the at least one forward error correction coding code type has a different error correction capability, and the error correction capability of the codeword encoded by the at least one forward error correction coding code type is less than or equal to (N+ΔN-K) / 2, that is, the error correction capability of the codeword encoded by the at least one forward error correction coding code type is less than or equal to the error correction capability of the RS(N+ΔN,K) code type.

[0242] It should be understood that when the encoding of the RS(N,K) code type is realized by the encoder of the RS(N+ΔN,K) code type, it is only necessary to make Φ N+ΔN,K Φ in ΔN,K = 0, and multiply the constant coefficients by Θ in the module N+ΔN,K Replace with Θ N,K (Alternatively, reuse based on Θ N+ΔN,K The constant coefficient multiplication and addition module is used to realize the coefficient Θ N,K The circuit module for multiplication and addition). The encoding of RS(N,K) code type can be realized in the encoder of RS(N+ΔN,K) code type. Among them, Φ ΔN,K Including [M(α N-K ),…,M(α N+ΔN-K-1 )].

[0243] As an example, when we need to let Φ ΔN,K = 0, the encoder can input the coefficient 0 to the multiplier of each polynomial evaluation circuit in the ΔN polynomial evaluation circuits shown in FIG16 through the selector, thereby realizing Φ ΔN,K =0.

[0244] In order to deepen the understanding of the beneficial effects of the embodiments of the present application, the encoder provided in the embodiments of the present application is further introduced below by way of examples.

[0245] It can simultaneously support RS (N1, K1, T1, m) code type, RS (N2, K2, T2, m) code type, ..., and RS (N s , K s , T s , m) code type encoding encoder as an example, refer to Figure 19, Figure 19 shows a structural diagram of an encoder supporting multi-code type fusion encoding provided by an embodiment of the present application. Wherein, N is the codeword length after forward error correction encoding, K is the length of the payload in the codeword, m is used to indicate the finite field for RS encoding calculation, T is the error correction capability, and T = (NK) / 2, and then NK = 2T. And, set T1, T2, ..., T s Monotonically increasing in sequence, i.e. T1 <T2<…<T s , s is an integer.

[0246] As shown in FIG. 19 , the encoder 1900 includes s polynomial evaluation modules, namely a first polynomial evaluation module, a second polynomial evaluation module, . . . , and an sth polynomial evaluation module.

[0247] The first polynomial evaluation module includes (N1-K1) polynomial evaluation circuits, and is used to calculate (N1-K1) (i.e., 2T1) target polynomials according to the received data. That is to say The second polynomial evaluation module includes (2T2-2T1) polynomial evaluation circuits and is used to calculate (2T2-2T1) target polynomials based on the received data. And, the sth polynomial evaluation module includes (2T s -2T s-1 ) polynomial evaluation circuits, and used to calculate (2T s -2T s-1 ) target polynomials It is understandable that the detailed description of how to calculate the target polynomial by the polynomial evaluation circuit can be referred to the above description and will not be repeated here.

[0248] The encoder 1900 further includes s constant coefficient multiplication-addition modules, namely a first constant coefficient multiplication-addition module, a second constant coefficient multiplication-addition module, ..., and an sth constant coefficient multiplication-addition module.

[0249] Among them, the constant coefficient preset in the first multiplication coefficient multiplication and addition module is: Where j1 = 1, 2, ..., (N1-K1). It should be understood that when j1 = [1, 2, ..., (N1-K1)], the constant coefficient It is a coefficient matrix of (N1-K1)×(N1-K1). Furthermore, the first coefficient multiplication and addition module is used to calculate the corresponding check sequence according to the preset constant coefficients and the received (N1-K1) target polynomials. The constant coefficients preset in the second multiplication coefficient multiplication and addition module are: Where j2 = 1, 2, ..., (N2-K2). It should be understood that when j2 = [1, 2, ..., (N2-K2)], the constant coefficient It is a coefficient matrix of (N2-K2)×(N2-K2). Then, the second coefficient multiplication and addition module is used to calculate the corresponding check sequence according to the preset constant coefficients and the received (N2-K2) target polynomials. The constant coefficients preset in the sth multiplication and addition module are: Among them, j s =1,2,…,(N s -K s ). It should be understood that s =[1, 2, ..., (N s -K s )], constant coefficient is a (N s -K s )×(N s -K s ) coefficient matrix. Then, the sth coefficient multiplication and addition module is used to calculate the coefficient matrix according to the preset constant coefficient and the received (N s -K s ) target polynomials to obtain the corresponding check sequence

[0250] The encoder 1900 further includes a merging module 1910 , which is configured to merge the received check sequence and the corresponding data to be encoded, thereby obtaining an encoded codeword, and outputting the codeword.

[0251] Based on the above description, for the RS (N1, K1, T1, m) code type, assuming that data 1 includes K1 symbols, the encoder 1900 sends the data 1 that needs to be encoded with the RS (N1, K1, T1, m) code type to the first polynomial evaluation module in the encoder 1900 through K1 / n beats with a parallel degree n, thereby obtaining (N1-K1) (i.e., 2T1) target polynomials representing data 1. Next, the encoder 1900 converts the (N1-K1) target polynomials Send it to the first constant coefficient multiplication and addition module to realize the (N1-K1) target polynomials and coefficients The multiplication and addition operation is performed to obtain the check sequence of data 1 with a length of (N1-K1) in, Where i = 0, 1, 2, ..., (N1-K1). Then, the encoder 1900 checks the sequence The merge module 1910 will check the sequence Combined with data 1, the code word of data 1 after RS ​​(N1, K1, T1, m) encoding is obtained, and the code word is output.

[0252] For the RS (N2, K2, T2, m) code pattern, assuming that data 2 includes K2 symbols, the encoder 1900 sends data 2 to be encoded with the RS (N2, K2, T2, m) code pattern to the first polynomial evaluation module and the second polynomial evaluation module in K2 / n beats with a parallel degree n. In this way, the first polynomial evaluation module can calculate and output 2T1 target polynomials for data 2. And the second polynomial evaluation module can calculate and output the (2T2-2T1) target polynomials of data 2 Then, the encoder 1900 converts the 2T2 target polynomials Send it to the second constant coefficient multiplication and addition module to realize the 2T2 target polynomials and coefficients Multiplication and addition operation is performed to obtain the check sequence of data 2 The detailed process of the multiplication and addition operation can refer to the detailed explanation of the multiplication and addition operation in the first constant coefficient multiplication and addition module, which will not be repeated here. The merge module 1910 will check the sequence Combined with data 2, thereby obtaining the code word of data 2 after RS ​​(N2, K2, T2, m) encoding, and outputting the code word.

[0253] Similarly, for RS(N s , K s , T s , m) code type, assuming that data 3 includes K s symbols, the encoder 1900 with parallelism n will need to use RS(N s , K s , T s ,m) code-coded data 3, through K s / n beats are sent to the first polynomial evaluation module, the second polynomial evaluation module, ..., and the third polynomial evaluation module, thereby obtaining the 2T of data 3 s Target polynomial Then, the encoder 1900 performs the multiplication and addition of the sth constant coefficient on the 2T s target polynomial and coefficients Perform multiplication and addition operations to obtain the check sequence of data 3 Then, the encoder 1900 checks the sequence The merge module 1910 will check the sequence and data 3 are merged to obtain data 3 through RS(N s , K s , T s , m) the encoded codeword and output the codeword.

[0254] As described in the example of Figure 19, when encoding RS code types with different error correction capabilities, the embodiment of the present application has a multiplexed circuit structure (the first polynomial evaluation module and the second polynomial evaluation module as shown in Figure 19) in the encoder for implementing RS code types with different error correction capabilities. Therefore, the encoder provided by the embodiment of the present application can not only support the encoding of RS code types with different error correction capabilities, but also save the circuit area and circuit power consumption of the encoder.

[0255] The above describes the encoder provided in this application from the structural aspect. The following describes the encoding method performed by the encoder described above from the method perspective.

[0256] Referring to Figure 20, Figure 20 shows a schematic flow chart of an encoding method provided in an embodiment of the present application. The method is performed by the encoder described above (e.g., the encoder shown in Figures 8, 11, 13, 16, 18, or 19). As shown in Figure 20, the method includes the following steps:

[0257] S101 : Receive data to be encoded through a feedforward module with a parallelism of n symbols per beat.

[0258] Wherein, n is a positive integer.

[0259] Specifically, the detailed description of how the encoder receives the data to be encoded can be referred to the above description and will not be repeated here.

[0260] S102 : Obtain, by means of a feedforward module, a single-beat polynomial corresponding to the current beat by calculating in a finite field according to symbols in the data to be encoded received in the current beat.

[0261] The data to be encoded includes K symbols, K is a positive integer, and K is greater than or equal to n. Moreover, the polynomial representing the symbols received in each beat is the single-beat polynomial mentioned above.

[0262] Specifically, the encoder calculates the single-shot polynomial in the finite field through the feedforward module. For a detailed description of the calculation of the single-shot polynomial, please refer to the description of the calculation of the single-shot polynomial above, which will not be repeated here.

[0263] S103. Receive the single-beat polynomial corresponding to the current beat output by the feedforward module through the feedback module, and calculate a second polynomial in a finite field based on the single-beat polynomial corresponding to the current beat and the first polynomial representing the symbols received in the historical beats.

[0264] The second polynomial represents the symbols received from the first beat to the current beat, and is used to determine the target polynomial representing the data to be encoded. Here, the first beat is the first beat of the data to be encoded received by the feedforward module, and the historical beat is the beat between the current beats during the process of the feedforward module receiving the data to be encoded. It should be noted that the encoder's feedback module is decoupled from the input parallelism of the data to be encoded. A detailed description can be found above and will not be repeated here.

[0265] Among them, the target polynomial is used to generate a check sequence of the data to be encoded, and the check sequence of the data to be encoded is used to check and correct errors in the data to be encoded. The codeword obtained after the data to be encoded is encoded in a forward error correction coding method includes the data to be encoded and the check sequence of the data to be encoded.

[0266] Specifically, the encoder receives the single-beat polynomial corresponding to the current beat output by the feedforward module through the feedback module, and calculates and outputs the second polynomial in the finite field based on the single-beat polynomial corresponding to the current beat and the first polynomial representing the symbol received in the historical beat. For a detailed description, please refer to the detailed description of the feedback circuit above and will not be repeated here.

[0267] Furthermore, the encoder determines whether the current beat is the K / nth beat receiving the data to be encoded.

[0268] When the encoder determines that the current beat is the K / nth beat of receiving the data to be encoded, indicating that the payload of one codeword has been input, the encoder determines the second polynomial calculated by the feedback module as the target polynomial representing the data to be encoded, and the encoder executes S104.

[0269] When the encoder determines that the current beat is not the K / nth beat of the data to be encoded, it means that the payload of a codeword has not yet been input. In this case, the encoder repeatedly performs S102 to S103 until the K / nth beat of the data to be encoded is received.

[0270] S104: Calculate and obtain a check sequence of the data to be encoded according to the constant coefficient matrix and the target polynomial.

[0271] Among them, the encoder calculates a detailed description of the check sequence of the data to be encoded based on the constant coefficient matrix and the target polynomial. Please refer to the detailed description of the constant coefficient multiplication and addition module above and will not be repeated here.

[0272] S105 , combining the data to be encoded and the check sequence of the data to be encoded to obtain a codeword of the data to be encoded using a forward error correction encoding method.

[0273] Among them, the encoder merges the data to be encoded and the check sequence of the data to be encoded to obtain a detailed description of the codeword after the data to be encoded is encoded in a forward error correction encoding manner. Please refer to the detailed description of the merging module above and will not be repeated here.

[0274] In this way, the encoder provided in the embodiment of the present application can encode forward error correction code types with different error correction capabilities through the encoding method described in S101 to S105, and can also save the circuit area and circuit power consumption of the encoder.

[0275] To deepen the understanding of the encoder and encoding method described in the embodiments of the present application, further explanation is given below through specific examples.

[0276] Example 1: RS(528,514,7,10) pattern

[0277] Among them, the RS (528, 514, 7, 10) code type indicates that the RS codeword length is 528, the payload length in the codeword is 514, the check sequence length is (528-514) = 14 (that is, (NK) mentioned above), the error correction capability is 7, and the finite field of RS coding calculation is GF(2 10 ).

[0278] When the encoder provided by the present application performs the encoding method described above, and the encoder performs encoding using the RS (528, 514, 7, 10) code type, the constant coefficient matrix preset in the constant coefficient multiplication and addition module in the encoder is recorded as the following matrix (3):

[0279] Matrix (3)

[0280] In this case, the 14 polynomial evaluation modules in the encoder first calculate the 14 target polynomials of the data to be encoded: [M(α 13 ), M(α 12 ),…,M(α 0 )]. Then, the constant coefficient multiplication and addition module in the encoder [M(α 13 ), M(α 12 ),…,M(α 0 )] and the preset constant coefficient matrix (i.e. matrix (3)) are multiplied and added to obtain the check sequence [p13 , p 12 …, p0]. Among them, p 13 =∑θ (1，i+1) ×M(α i ), p 12 =∑θ (2，i+1) ×M(α i ),…,p0=∑θ (14，i+1) ×M(α i ), where i = 1, 2,…14.

[0281] Among them, [M(α 13 ), M(α 12 ),…,M(α 0 )] can be obtained from the following formula (21) and the finite field GF(2 10 ) in the primitive polynomial x 10 +x 3 The root α of +1 is calculated as:

[0282] Formula (21)

[0283] Each coefficient in the above matrix (3) can be expressed as follows according to the following formula (22) and the finite field GF(2 10 ) in the primitive polynomial x 10 +x 3 The root α of +1 is calculated. Wherein, formula (22) can be derived according to the above formula (13) and matrix (3), which will not be repeated here.

[0284] Formula 22

[0285] After pre-calculation, the coefficients in matrix (3) are specifically shown in the following matrix (4):

[0286] Matrix (4)

[0287] Then, the encoder calculates [M(α 13 ), M(α 12 ),…,M(α 0 )] and the coefficients shown in matrix (4), the check sequence [p 13 , p 12 …, p0]. After the encoder combines the data to be encoded and the check sequence, the codeword of the data to be encoded can be obtained by encoding the data using the RS (528, 514, 7, 10) code pattern.

[0288] Example 2 RS(544,514,15,10)

[0289] Among them, the RS (544, 514, 15, 10) code type indicates that the RS codeword length is 544, the payload length in the codeword is 514, the check sequence length is (544-514) = 30 (that is, (NK) mentioned above), the error correction capability is 15, and the finite field of RS coding calculation is GF(2 10 ).

[0290] When the encoder provided by the present application performs the encoding method described above, and the encoder performs encoding using the RS (544, 514, 15, 10) code pattern, the constant coefficient matrix preset in the constant coefficient multiplication and addition module in the encoder is recorded as the following matrix (5):

[0291] Matrix (5)

[0292] In this case, the 30 polynomial evaluation modules in the encoder first calculate the 30 target polynomials of the data to be encoded: [M(α 29 ),…,M(α 0 )]. Then, the constant coefficient multiplication and addition module in the encoder [M(α 29 ),…,M(α 0 )] and the preset constant coefficient matrix (i.e. matrix (5)) are multiplied and added to obtain the check sequence [p 29 , p 28 …, p0]. Among them, p 29 = ∑θ (1，i+1) ×M(α i ), p 28 =∑θ (2，i+1) ×M(α i ),…,p0=∑θ (30，i+1) ×M(α i ), where i = 1, 2,…30.

[0293] Among them, [M(α 29 ),…,M(α 0 )] can be obtained from the following formula (23) and the finite field GF(2 10 ) in the primitive polynomial x 10 +x 3 The root α of +1 is calculated as:

[0294] Formula (23)

[0295] From formula (21) and formula (23), we can know that when the encoder encodes with the RS (544, 514, 15, 10) code type, the encoder calculates [M (α 29 ),…,M(α 0)], you can reuse [M(α 13 ),…,M(α 0 )] corresponding to 14 polynomial evaluation circuits, thereby saving circuit area and circuit power consumption.

[0296] Each coefficient in the above matrix (5) can be expressed as follows according to the following formula (24) and the finite field GF(2 10 ) in the primitive polynomial x 10 +x 3 The root α of +1 is calculated. Wherein, formula (24) can be derived according to the above formula (13) and matrix (5), which will not be repeated here.

[0297] Formula 24

[0298] After calculation, with reference to FIG21, FIG21 shows the constant coefficient matrix of the RS(544,514,15,10) code type provided in an embodiment of the present application. Compared with the coefficients of the RS(528,514) code type and the RS(544,514) code type in the current encoding method shown in Table 1, the submatrix of the first 14 rows × the first 14 columns (shown as a black rectangular frame in FIG21) in the constant coefficient matrix of the RS(544,514,15,10) code type preset in the encoder provided in an embodiment of the present application shown in FIG21 is the constant coefficient matrix of the RS(528,514,7,10) code type preset in the encoder provided in an embodiment of the present application. Based on this, according to the same coefficient matrix, the encoder of the RS (544, 514, 15, 10) code type provided in the embodiment of the present application and the encoder of the RS (528, 514, 7, 10) code type can share the circuit constructed based on the aforementioned same coefficient matrix, so that the encoder provided in the embodiment of the present application can not only encode forward error correction code types with different error correction capabilities, but also save the circuit area and power consumption of the encoder.

[0299] Then, the encoder calculates [M(α 29 ),…,M(α 0 )] and the coefficients shown in Figure 21, the check sequence [p 29 , p 28 …, p0]. After the encoder combines the data to be encoded and the check sequence, the codeword of the data to be encoded can be obtained by encoding the data using the RS (544, 514, 15, 10) code pattern.

[0300] In summary, the encoder provided by the embodiment of the present application will not have the technical defect of non-convergence in timing in scenarios with large bandwidth and high parallelism input. Moreover, the encoder provided by the embodiment of the present application can not only encode forward error correction code types with different error correction capabilities, but also save the circuit area and power consumption of the encoder.

[0301] To implement the functions described in the above method, as shown in Figure 22, Figure 22 shows a schematic structural diagram of an encoding device 2200 provided in an embodiment of the present application. The encoding device 2200 is used to perform the above encoding method, for example, to perform the method shown in Figure 20. The encoding device 2200 can be the encoder including the feedforward module and the feedback module described above, or the encoding device 2200 is applied to the encoder including the feedforward module and the feedback module described above. The encoding device 2200 may include a receiving unit 2210 and a computing unit 2220.

[0302] The receiving unit 2210 is configured to receive the data to be encoded with a parallelism of n symbols per beat through the feedforward module, where n is a positive integer. The computing unit 2220 is configured to calculate a single-beat polynomial corresponding to the current beat in a finite field based on the symbols in the data to be encoded received in the current beat through the feedforward module. Here, the single-beat polynomial represents the symbols received by the feedforward module through one beat. The computing unit 2220 is further configured to receive the single-beat polynomial corresponding to the current beat output by the feedforward module through the feedback module, and calculate a second polynomial in a finite field based on the single-beat polynomial corresponding to the current beat and the first polynomial representing the symbols received in the historical beats. The second polynomial represents the symbols received from the first beat to the current beat, and the second polynomial is used to determine a target polynomial representing the data to be encoded. The target polynomial is used to generate a check sequence for the data to be encoded, and the check sequence for the data to be encoded is used to perform error correction on the data to be encoded. The codeword obtained after the data to be encoded is encoded in a forward error correction coding method includes the data to be encoded and the check sequence for the data to be encoded. In addition, the aforementioned first beat is the first beat of the data to be encoded received by the feedforward module, and the historical beat is the beat between the current beats in the process of the feedforward module receiving the data to be encoded.

[0303] As an example, in conjunction with FIG20 , the receiving unit 2210 may be used to execute S101 , and the computing unit 2220 may be used to execute S102 and S103 .

[0304] Optionally, the data to be encoded includes K symbols, where K is a positive integer. When the length of a codeword obtained after encoding the data to be encoded using a forward error correction encoding method is N, and N is an integer greater than K, the encoder includes NK polynomial evaluation modules, each of which includes a feedforward module and a feedback module. The NK polynomial evaluation modules are configured to calculate, in a finite field, NK target polynomials representing the data to be encoded using the feedforward module and the feedback module in each polynomial evaluation module.

[0305] Optionally, when the codeword length obtained after the above-mentioned data to be encoded using a forward error correction encoding method is N+ΔN, the above-mentioned encoder includes N+ΔN-K polynomial evaluation modules, each of which includes a feedforward module and a feedback module. The N+ΔN-K polynomial evaluation modules are used to calculate N+ΔN-K target polynomials representing the data to be encoded in a finite field through the feedforward module and feedback module in each polynomial evaluation module. In addition, the N+ΔN-K polynomial evaluation modules include the above-mentioned NK polynomial evaluation modules.

[0306] Optionally, the encoding device 2200 further includes a determining unit 2230 configured to determine the second polynomial as the target polynomial when determining that the current beat is the K / nth beat of the received data to be encoded. The calculating unit 2220 is further configured to calculate a check sequence for the data to be encoded based on the constant coefficient matrix and the target polynomial. The merging unit 2240 is configured to merge the data to be encoded and the check sequence for the data to be encoded to obtain a codeword after the data to be encoded is encoded using a forward error correction coding method.

[0307] As an example, in conjunction with FIG20 , the calculation unit 2220 may be used to execute S104 , and the merging unit 2240 may be used to execute S105 .

[0308] Optionally, when the codeword length obtained after the data to be encoded using the forward error correction coding method is N, the constant coefficient matrix is ​​a first constant coefficient matrix of (NK)×(NK). When the codeword length after the data to be encoded using the forward error correction coding method is N+ΔN, the constant coefficient matrix is ​​a second constant coefficient matrix of (N+ΔN-K)×(N+ΔN-K). The second constant coefficient matrix includes the constant first coefficient matrix.

[0309] Optionally, the encoder supports encoding of at least one forward error correction coding code type, and each code type in the at least one forward error correction coding code type has a different error correction capability.

[0310] Optionally, when the value of n is greater than a threshold, the encoding device 2200 further includes: a control unit 2250, configured to control the feedforward module to complete the calculation of a single-beat polynomial through at least two clock cycles via a register inserted in the feedforward module.

[0311] For a detailed description of the above optional methods, please refer to the aforementioned method embodiments, which will not be repeated here. In addition, the explanation of any encoding device 2200 provided above and the description of its beneficial effects can refer to the corresponding method and the embodiment of the encoder, which will not be repeated here.

[0312] As an example, in conjunction with FIG12 , the functions implemented by the receiving unit 2210 in the encoding device 2200 can be performed by the polynomial evaluation circuit in FIG12 . The functions implemented by the calculation unit 2220 can be performed by the polynomial evaluation circuit and the constant coefficient multiplication and addition module 1210 shown in FIG12 . The determination unit 2230 can be performed by the polynomial evaluation circuit shown in FIG12 . The merging unit 2240 can be performed by the merging module 1220 shown in FIG12 . In conjunction with FIG14 , the control unit 2250 can be performed by the registers inserted into the feedforward circuit 1400 in FIG14 .

[0313] It should be readily apparent to those skilled in the art that, in combination with the units and algorithmic steps of the various examples described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is performed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0314] It should be noted that the module division shown in FIG22 is schematic and represents only one logical functional division. In actual implementation, other divisions may be employed. For example, two or more functions may be integrated into a single processing module. Such integrated modules may be implemented in either hardware or software functional modules.

[0315] An embodiment of the present application further provides a chip, which includes a coding circuit, and the coding circuit is used to execute the coding method as described above to achieve encoding of the data to be encoded in a forward error correction coding manner.

[0316] The present application also provides a computer program product and a computer-readable storage medium for storing the computer program product. The computer program product may include one or more program instructions that, when executed by one or more processors, may provide the functions or portions of the functions described above with respect to FIG. 20 . Thus, for example, one or more features of S101 to S105 in FIG. 20 may be provided by one or more instructions in the computer program product.

[0317] In some examples, an encoding device, such as that described with respect to FIG. 20 , may be configured to provide various operations, functions, or actions in response to one or more program instructions stored in a computer-readable storage medium.

[0318] In the above embodiments, all or part of the embodiments can be implemented using software, hardware, firmware, or any combination thereof. When implemented using a software program, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the instructions are executed on a computer and executed by the computer, all or part of the processes or functions according to the embodiments of the present application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media. The available media can be magnetic media (e.g., floppy disk, hard disk, tape), optical media (e.g., DVD), or semiconductor media (e.g., solid state drive (SSD)).

[0319] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. An encoder, characterized in that: include: A feedforward module, configured to receive data to be encoded with a parallelism of n symbols per beat, and, based on symbols in the data to be encoded received in a current beat, calculate a single-beat polynomial corresponding to the current beat in a finite field, wherein the single-beat polynomial represents the symbols received by the feedforward module through one beat, and n is a positive integer; A feedback module is used to receive the single-beat polynomial corresponding to the current beat output by the feedforward module, and calculate a second polynomial in the finite field according to the single-beat polynomial corresponding to the current beat and the first polynomial representing the symbols received by the historical beats, wherein the second polynomial represents the symbols received from the first beat to the current beat, and the second polynomial is used to determine a target polynomial representing the data to be encoded; wherein the target polynomial is used to generate a check sequence for the data to be encoded, and the check sequence for the data to be encoded is used to check and correct the data to be encoded, and the codeword obtained after the data to be encoded is encoded in a forward error correction coding manner includes the data to be encoded and the check sequence for the data to be encoded; the first beat is the first beat of the data to be encoded received by the feedforward module, and the historical beat is the beat located between the current beats during the process of the feedforward module receiving the data to be encoded.

2. The encoder according to claim 1, characterized in that The data to be encoded includes K symbols, K is a positive integer; when the length of the codeword obtained after the data to be encoded in the forward error correction encoding mode is N, and N is an integer greater than K, the encoder includes NK polynomial evaluation modules, each polynomial evaluation module includes the feedforward module and the feedback module; The NK polynomial evaluation modules are used to calculate NK target polynomials representing the data to be encoded in the finite field through a feedforward module and a feedback module in each polynomial evaluation module.

3. The encoder according to claim 2, characterized in that When the length of the codeword obtained after the data to be encoded in the forward error correction encoding mode is N+ΔN, the encoder includes N+ΔN-K polynomial evaluation modules, each polynomial evaluation module includes the feedforward module and the feedback module; The N+ΔN-K polynomial evaluation modules are used to calculate N+ΔN-K target polynomials representing the data to be encoded in the finite field through the feedforward module and the feedback module in each polynomial evaluation module, and the N+ΔN-K polynomial evaluation modules include the NK polynomial evaluation modules.

4. The encoder according to any one of claims 1 to 3, characterized in that The encoder further comprises: A constant coefficient multiplication and addition module, used for calculating the check sequence of the data to be encoded according to the constant coefficient matrix and the target polynomial; The merging module is used to merge the data to be encoded and the check sequence of the data to be encoded to obtain a codeword after the data to be encoded is encoded in a forward error correction encoding manner.

5. The encoder according to claim 4, characterized in that When the length of the codeword obtained after the data to be encoded in the forward error correction encoding method is N, the constant coefficient matrix is ​​a first constant coefficient matrix of (NK)×(NK); When the codeword length of the data to be encoded after being encoded in a forward error correction coding manner is N+ΔN, the constant coefficient matrix is ​​a second constant coefficient matrix of (N+ΔN-K)×(N+ΔN-K), and the second constant coefficient matrix includes the first constant coefficient matrix.

6. The encoder according to any one of claims 1 to 5, characterized in that: The encoder supports encoding of at least one forward error correction encoding code type, each of the at least one forward error correction encoding code type having a different error correction capability.

7. The encoder according to any one of claims 1 to 6, characterized in that: When the value of n is greater than a threshold, the feedforward module includes a register; The register is used to control the feedforward module to complete the calculation of a single-beat polynomial through at least two clock cycles.

8. A coding method, characterized in that: The method is applied to an encoder, the encoder includes a feedforward module and a feedback module, and the method includes: Receiving the data to be encoded with a parallelism of n symbols per beat through the feedforward module, and calculating a single-beat polynomial corresponding to the current beat in a finite field according to the symbols in the data to be encoded received in the current beat, wherein the single-beat polynomial represents the symbols received by the feedforward module through one beat, and n is a positive integer; The feedback module receives the single-beat polynomial corresponding to the current beat output by the feedforward module, and A single-beat polynomial corresponding to the current beat and a first polynomial representing the symbols received in the historical beats are used to calculate a second polynomial in the finite field, the second polynomial represents the symbols received from the first beat to the current beat, and the second polynomial is used to determine a target polynomial representing the data to be encoded; wherein the target polynomial is used to generate a check sequence for the data to be encoded, the check sequence for the data to be encoded is used to check and correct the data to be encoded, and the codeword obtained after the data to be encoded is encoded in a forward error correction coding manner includes the data to be encoded and the check sequence for the data to be encoded; the first beat is the first beat of the feedforward module receiving the data to be encoded, and the historical beat is the beat located between the current beats in the process of the feedforward module receiving the data to be encoded.

9. The method according to claim 8, characterized in that The data to be encoded includes K symbols, K is a positive integer; when the codeword length obtained after the data to be encoded in a forward error correction encoding manner is N, and N is an integer greater than K, the encoder includes NK polynomial evaluation modules, each polynomial evaluation module includes the feedforward module and the feedback module; the NK polynomial evaluation modules are used to calculate NK target polynomials representing the data to be encoded in the finite field through the feedforward module and the feedback module in each polynomial evaluation module.

10. The method according to claim 9, characterized in that When the codeword length obtained after the data to be encoded in a forward error correction coding manner is N+ΔN, the encoder includes N+ΔN-K polynomial evaluation modules, each of which includes the feedforward module and the feedback module; the N+ΔN-K polynomial evaluation modules are used to calculate N+ΔN-K target polynomials representing the data to be encoded in the finite field through the feedforward module and the feedback module in each polynomial evaluation module, and the N+ΔN-K polynomial evaluation modules include the NK polynomial evaluation modules.

11. The method according to any one of claims 8 to 10, characterized in that The method further comprises: When it is determined that the current beat is the K / nth beat of receiving the data to be encoded, determining the second polynomial as the target polynomial; Calculate and obtain a check sequence of the data to be encoded according to the constant coefficient matrix and the target polynomial; The data to be encoded and the check sequence of the data to be encoded are combined to obtain a codeword of the data to be encoded in a forward error correction encoding manner.

12. The method according to claim 11, characterized in that When the length of the codeword obtained after the data to be encoded in the forward error correction encoding method is N, the constant coefficient matrix is ​​a first constant coefficient matrix of (NK)×(NK); When the codeword length of the data to be encoded after being encoded in a forward error correction coding manner is N+ΔN, the constant coefficient matrix is ​​a second constant coefficient matrix of (N+ΔN-K)×(N+ΔN-K), and the second constant coefficient matrix includes the first constant coefficient matrix.

13. The encoding method according to any one of claims 8 to 12, characterized in that: The encoder supports encoding of at least one forward error correction encoding code type, each of the at least one forward error correction encoding code type having a different error correction capability.

14. The method according to any one of claims 8 to 13, characterized in that When the value of n is greater than a threshold, the method further includes: By means of the register inserted in the feedforward module, the feedforward module is controlled to complete the calculation of a single-beat polynomial through at least two clock cycles.

15. A chip, characterized in that: The chip comprises a coding circuit, and the coding circuit is used to execute the method according to any one of claims 8 to 14, so as to realize encoding of the data to be encoded in a forward error correction coding manner.

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