Method and apparatus for executing plurality of computing tasks

Abstract

The present application relates to computer technology, and in particular to a method and apparatus for executing a plurality of computing tasks, and a non-transitory computer-readable storage medium for implementing the method. The method for executing a plurality of computing tasks according to one aspect of the present application comprises the following steps: using a processor to generate or accessing a memory to acquire a task scheduling graph (601), the method for generating the task scheduling graph comprising enabling the task scheduling graph to include a plurality of nodes, and edges connecting paired nodes to form a plurality of paths, wherein each path represents an optional execution sequence of a plurality of computing tasks, the nodes comprise a plurality of task nodes and one or more control nodes, each task node represents one of the plurality of computing tasks, and each control node is configured to describe a routing method of a node associated with the control node, so that one of the optional execution sequences is defined as an execution sequence of the plurality of computing tasks; and using the processor to execute the plurality of computing tasks according to the execution sequence defined by the task scheduling graph (602).

Description

Method and apparatus for performing multiple computing tasks Technical Field

[0001] The present application relates to computer technology, and more particularly to a method, an apparatus, and a non-transitory computer-readable storage medium for performing multiple computing tasks. Background Art

[0002] When training AI models, hundreds of computing tasks and thousands of nodes may be running simultaneously. Task schedulers are typically used to schedule and monitor training tasks. These schedulers enable users to launch and manage tasks through task control instructions. As model size increases, the computational workload becomes increasingly demanding. Therefore, achieving efficient task scheduling is a pressing issue.

[0003] Summary of the Invention

[0004] One object of the present application is to provide a method and apparatus for executing multiple computing tasks, which can achieve efficient scheduling of computing tasks.

[0005] According to one aspect of the present application, a method for executing multiple computing tasks is provided, the method comprising the following steps:

[0006] Generate a task scheduling graph using a processor or obtain the task scheduling graph by accessing a memory, wherein the task scheduling graph is generated in a manner including: causing the task scheduling graph to include a plurality of nodes and edges connecting pairs of nodes to form a plurality of paths, wherein each path represents an optional execution sequence of the plurality of computing tasks, the nodes including a plurality of task nodes and one or more control nodes, each task node representing one of the plurality of computing tasks, the control node being configured to describe a path through a node associated therewith, thereby defining one of the optional execution sequences as an execution sequence of the plurality of computing tasks; and

[0007] The processor executes the plurality of computing tasks according to an execution sequence defined by the task schedule graph.

[0008] Optionally, in the above method, the method of generating the task scheduling graph further includes: assigning directions to edges connecting pairs of nodes, wherein the directions indicate the execution order corresponding to the nodes connected by the edges.

[0009] Optionally, in the above method, the pathway includes one or more of the following: a conditional pathway, a cyclic pathway, and a conditional cyclic pathway.

[0010] Optionally, in the above method, the description of the conditional manner includes at least a branch judgment condition, a node pointed to by a branch whose judgment result is true, and a node pointed to by a branch whose judgment result is false.

[0011] Optionally, in the above method, the description of the loop mode includes at least the node where the loop body starts, the node where the loop body ends, the node pointed to after exiting the loop body, and the number of times the nodes in the loop body are executed in a loop.

[0012] Optionally, in the above method, the description of the conditional loop mode includes at least the node where the conditional loop body starts, the node where the conditional loop body ends, the conditional loop judgment condition, and the node to which the branch points when the judgment result is negative.

[0013] Optionally, in the above method, the step of executing the multiple computing tasks includes:

[0014] generating an execution sequence of the computing task based on the description of the control node and the direction indicated by the directed edge; and

[0015] The plurality of computing tasks are executed according to the process indicated by the execution sequence.

[0016] Optionally, in the above method, the task scheduling graph is stored in the form of a linked list, the nodes correspond to data elements of the linked list, and the execution order of the nodes is represented by the link order of the pointers in the linked list.

[0017] Optionally, in the above method, the task scheduling graph is stored in the form of an array, the nodes correspond to data elements of the array, and the execution order of the nodes is represented by the order of the data elements.

[0018] According to another aspect of the present application, there is provided an apparatus for performing multiple computing tasks, comprising:

[0019] at least one processor;

[0020] at least one memory;

[0021] a computer program stored in said memory,

[0022] By running the computer program on the processor, the following operations are performed:

[0023] Generating or obtaining a task scheduling graph by accessing the memory, wherein the task scheduling graph is generated in a manner comprising: causing the task scheduling graph to include a plurality of nodes and edges connecting pairs of nodes to form a plurality of paths, wherein each path represents an optional execution flow of the plurality of computing tasks, the nodes including a plurality of task nodes and one or more control nodes, each task node representing one of the plurality of computing tasks, the control node being configured to describe a path through its associated nodes, thereby defining one of the optional execution sequences as the execution flow of the plurality of computing tasks; and

[0024] The plurality of computing tasks are executed according to the execution process defined by the task scheduling graph.

[0025] According to another aspect of the present application, a non-transitory computer-readable storage medium is provided. The non-transitory computer-readable storage medium stores instructions, and the method described above is implemented by executing the instructions by a processor.

[0026] In some embodiments of the present application, using a task scheduling graph to define the execution sequence provides a good visualization effect and facilitates users to modify and maintain the execution process of computing tasks. In addition, by adding control nodes to the task scheduling graph to introduce various control logic such as conditions, loops, and conditional loops, it is possible to effectively address the completeness of the expression of task relationships in artificial intelligence computing models, improve the efficiency of task scheduling, and express and modify control logic in an efficient, concise, and intuitive manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and / or other aspects and advantages of the present application will become clearer and easier to understand through the following description of various aspects in conjunction with the accompanying drawings, in which the same or similar elements are represented by the same reference numerals.

[0028] FIG1 is a task scheduling diagram according to some embodiments of the present application, which includes control logic or node routing based on conditional judgment.

[0029] FIG2 is a task scheduling diagram according to some other embodiments of the present application, which includes control logic or node routing based on loop control.

[0030] FIG3 is a task scheduling diagram according to some other embodiments of the present application, which includes control logic or node routing based on conditional loop control.

[0031] 4A to 4D illustrate non-limiting examples of task scheduling diagrams for control logic having a complex structure.

[0032] FIG5 is a schematic block diagram of a computer system.

[0033] FIG6 is a flowchart of a method for executing multiple computing tasks according to some other embodiments of the present application.

[0034] FIG7 is a flowchart according to some other embodiments of the present application, which illustrates a process of executing a computing task according to an execution flow defined by a task scheduling graph. DETAILED DESCRIPTION

[0035] The present application is described more fully below with reference to the accompanying drawings, which illustrate exemplary embodiments of the present application. However, the present application may be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. The foregoing embodiments are provided to make the disclosure herein comprehensive and complete, so as to more fully convey the scope of protection of the present application to those skilled in the art.

[0036] In this specification, terms such as "comprise" and "include" indicate that in addition to the units and steps directly and clearly stated in the specification and claims, the technical solution of this application does not exclude the situation where it has other units and steps that are not directly or clearly stated.

[0037] Unless otherwise specified, terms such as "first" and "second" do not indicate the order of units in terms of time, space, size, etc., but are only used to distinguish between units.

[0038] According to one aspect of the present application, a task scheduling graph is used to define the execution sequence of multiple computing tasks, and the task scheduling graph has the following structure: it includes multiple nodes and edges that connect all or part of the nodes in pairs to form multiple paths, wherein the nodes include multiple task nodes and one or more control nodes. In the above task scheduling graph, each path represents one of the optional or possible execution sequences of multiple computing tasks (i.e., a sequence of computing tasks that are executed in sequence); each task node represents one of the computing tasks (in the following description, unless otherwise specified, the terms "task node" and "computing task" will be used interchangeably); the control node contains descriptive information to describe the path of the node associated with it (which can be a task node or other control node), thereby defining the (actual) execution sequence of multiple computing tasks.

[0039] Using a task scheduling graph to define an execution sequence has a good visualization effect and is convenient for users to modify and maintain (for example, by modifying the descriptive information of the control node).

[0040] In some embodiments, the direction of the edge (directed edge) can be used to represent at least one of the following execution orders: the execution order between a pair of task nodes or computing tasks, the execution order between a task node and a control node, and the execution order between a pair of control nodes.

[0041] In some embodiments, a control node can be a node that controls the execution process. Specifically, when a control node is connected to multiple nodes, the descriptive information it contains can define the control logic or path of these nodes, such as but not limited to conditional execution, loop execution, and conditional loop execution. By introducing descriptions of various control logics such as conditions, loops, and conditional loops in the control node, the completeness of the expression of task relationships in the artificial intelligence computing model can be effectively solved and the efficiency of task scheduling can be improved. In addition, it is also beneficial to express and modify the control logic in an efficient, concise and intuitive manner, especially when the control logic is very complex.

[0042] In some embodiments, the task scheduling graph having the above structure is suitable for storage in the form of a linked list or an array. For example, when the task scheduling graph is stored in the form of a linked list, the nodes can correspond to the data elements in the linked list, and the execution order of the nodes can be represented by the order of the pointer links in the linked list. For another example, when the task scheduling graph is stored in the form of an array, the nodes can correspond to the data elements of the array, and the execution order of the nodes can be represented by the order of the data elements.

[0043] The control logic will be further described below.

[0044] Figure 1 is a task scheduling diagram according to some embodiments of the present application, which includes control logic or node routing based on conditional judgment. In Figure 1, various nodes are represented by circles, wherein T0 to T3 represent task nodes, and IF represents a control node for implementing execution process control. Referring to Figure 1, based on the execution order indicated by the arrows, after completing the calculation task of task node T0, the execution process reaches the control node IF. At the control node IF, the execution process is determined based on the set branch judgment condition IF_DEF to determine whether the execution process will pass through task node T1 or task node T3. Specifically, at the control node IF, if the judgment result based on IF_DEF is true (TRUE), the execution process will be transferred to task node T1, and if the judgment result based on IF_DEF is false (FALSE), the execution process will be transferred to task node T3. Continuing to refer to Figure 1, based on the execution order indicated by the arrows, after completing the calculation task of task node T1, the execution process will be transferred to task node T2.

[0045] The control node IF can be described in various ways to describe the control logic shown in Figure 1. In one example, the description may include a branch judgment condition (IF_DEF in the example shown in Figure 1), the node to which the branch points if the judgment result is true (T1 in the example shown in Figure 1), and the node to which the branch points if the judgment result is false (T2 in the example shown in Figure 1). Optionally, the description may further include the type of the control node (for example, a control node that executes the conditional judgment logic in the example shown in Figure 1).

[0046] When the task scheduling graph is stored in a linked list or array format, the node pointed to by the branch with a true or false judgment result can be the first task address or array index of the branch. In addition, the control node IF can perform branch judgment in a direct or indirect manner. For example, in a direct manner, the control node IF compares the value (numerical value or logical value) with the reference value, while in an indirect manner, the address of the value is compared with the address of the reference value.

[0047] Fig. 2 is a task scheduling diagram according to some other embodiments of the present application, which includes control logic or node path mode based on loop control. In Fig. 2, various nodes are represented by circles, wherein T0~T4 represent task nodes, and LOOP represents a control node for implementing execution flow control. Referring to Fig. 2, based on the execution order indicated by the arrow, after completing the computing task of task node T0, execution flow arrives at control node LOOP. At control node LOOP, based on the set loop execution mode LOOP_DEF, the loop body LOOP_BODY consisting of task nodes T1~T3 is executed and after reaching the number of loops n, execution flow goes to node T4. Specifically, in loop body LOOP_BODY, task nodes T1~T3 are sequentially passed through (that is, corresponding computing tasks are executed in sequence) in the order shown by the arrows, and the start node, end node, node pointed to after exiting loop body LOOP_BODY and the number of times n that loop body LOOP_BODY is executed are defined at control node LOOP.

[0048] The control node LOOP can be used in various ways to describe the control logic shown in Figure 2. In one example, the description may include the start node of the loop body LOOP_BODY (node ​​T1 in the example shown in Figure 2), the end node (node ​​T3 in the example shown in Figure 2), the node pointed to after exiting the loop body LOOP_BODY (node ​​T4 in the example shown in Figure 2), and the number of times n that the loop body LOOP_BODY is looped. Optionally, the description may further include the type of the control node (for example, a control node used to implement loop control logic in the example shown in Figure 2).

[0049] It should be noted that the number of nodes included in the loop body can be multiple, but it can also be one, that is, the start node and the end node are the same node. In addition, the number of loops n can be directly included in the description of the control logic of the control node LOOP, or the storage address of the number of loops n can be included in the description of the control logic of the control node LOOP.

[0050] FIG3 is a task scheduling diagram according to some other embodiments of the present application, which includes control logic or node routing based on conditional loop control. In FIG3 , various nodes are represented by circles, wherein T0 to T4 represent task nodes, and WHILE represents a control node for implementing execution process control. Referring to FIG3 , based on the execution order indicated by the arrows, after completing the computing task of task node T0, the execution process reaches the control node WHILE. At the control node WHILE, the loop body LOOP_BODY composed of task nodes T1 to T3 is executed based on the set conditional loop execution mode WHILE_DEF, or the execution process is directly transferred to node T4. Specifically, at the control node WHILE, the execution flow is determined based on the set conditional loop execution judgment condition WHILE_DEF to determine whether the execution flow will transfer to the loop body LOOP_BODY or the task node T4; in the loop body LOOP_BODY, the task nodes T1 to T3 are passed in sequence according to the order shown by the arrows, and the start node, end node, conditional loop judgment condition and the node pointed to by the branch when the judgment result is negative of the loop body LOOP_BODY are defined at the control node WHILE.

[0051] The control node WHILE can be used in various ways to describe the control logic shown in Figure 3. In one example, the description may include the start node of the loop body LOOP_BODY (node ​​T1 in the example shown in Figure 3), the end node (node ​​T3 in the example shown in Figure 3), the node to which the branch points when the judgment result is no (node ​​T4 in the example shown in Figure 3), and the conditional loop judgment condition (WHILE_DEF in the example shown in Figure 3). Optionally, the description may further include the type of the control node (for example, a control node for implementing the conditional loop control logic in the example shown in Figure 3).

[0052] It should be noted that the number of nodes included in the loop body can be multiple, but can also be one. In addition, the control node WHILE can use the direct or indirect method described above to perform conditional loop judgment.

[0053] It should also be noted that although the nodes connected to the control nodes in Figures 1-3 are all task nodes, this is not limiting. In other examples, the nodes connected to the control nodes may also include control nodes, thereby forming a control logic with a complex structure. For example, the control logic shown in Figures 1-3 can be combined in a nested or cascaded manner to generate a task scheduling graph with a more complex control logic.

[0054] 4A to 4D illustrate non-limiting examples of task scheduling diagrams for control logic having a complex structure.

[0055] In FIG. 4A , the loop body LOOP1_BODY is embedded in the loop body LOOP0_BODY, wherein the control node LOOP0 is used to control the execution of the loop body LOOP0_BODY, and the control node LOOP1 is located in the loop body LOOP0_BODY and is used to control the execution of the loop body LOOP1_BODY.

[0056] In FIG4B , the loop body LOOP0_BODY and the loop body LOOP1_BODY are cascaded together via the task node T3 and the control node LOOP0. The loop body LOOP1_BODY is executed only after the execution of the loop body LOOP0_BODY and the task node T3 is completed.

[0057] In Figure 4C , the control logic based on conditional judgment is embedded in the loop body LOOP_BODY. Specifically, the control node LOOP is used to control the execution of the loop body LOOP_BODY. The loop body includes task nodes T1 to T5 and a control node IF, which are connected as shown. Task nodes T1 and T5 are the start and end nodes of the loop body, respectively. Furthermore, within the loop body LOOP_BODY, after the execution of task node T1 is completed, the control node IF is transferred to the control node. This control node is used to implement the control logic based on conditional judgment within the loop body LOOP_BODY. That is, if the judgment result made based on the branch condition is true, the execution flow will transfer to task node T2; otherwise, the execution flow will transfer to task node T3.

[0058] In Figure 4D , the control logic based on conditional judgment is cascaded with the loop body LOOP_BODY. Specifically, the control node LOOP is used to control the execution of the loop body LOOP_BODY, which contains task nodes T1 to T3, where task nodes T1 and T3 are the start and end nodes of the loop body, respectively. Further, referring to Figure 4D , the control node IF is connected to the end node T3 of the loop body LOOP_BODY. That is, when the execution process exits the loop body LOOP_BODY, it will jump to the control node IF, where the control logic based on conditional judgment will be completed. That is, if the judgment result made based on the branch condition is true, the execution process will jump to task node T4; otherwise, the execution process will jump to task node T6.

[0059] It should be noted that the task scheduling diagram described above in conjunction with the accompanying drawings is merely exemplary. In addition to the types mentioned above, control nodes may also have other types. Furthermore, in addition to the nested structure and cascade structure shown, the task scheduling diagram may also include other structures (such as parallel structures, etc.). In addition, the type and number of nested and cascaded control logic can also be flexibly set according to the needs of the actual application.

[0060] FIG5 is a schematic block diagram of a computer system that can be used to perform multiple computing tasks. As shown in FIG5 , the computer system 50 includes multiple computing devices 501 connected via a network 51 (e.g., the Internet or a local area network). Examples of computing devices include, but are not limited to, servers, PCs, workstations, and portable computers. The oval box in FIG5 shows the structure of each computing device 501. Referring to FIG5 , each computing device 501 includes at least one memory 501A (e.g., a non-volatile memory such as a flash memory, ROM, a hard disk drive, a magnetic disk, or an optical disk), at least one processor 501B, and a computer program 501C. Optionally, the computer system 50 can also be a stand-alone system.

[0061] Memory 501A stores a computer program 501C executable by processor 501B (e.g., for executing multiple computing tasks), and may also store a task scheduling diagram and the execution results of the computing tasks. Processor 501B is configured to execute computer program 501C stored in memory 501A and access memory 501A to obtain the task scheduling diagram. One or more steps included in the method described below with reference to FIG. 6 can be implemented by executing the computer program stored in one or more memories on one or more processors of one or more computing devices (e.g., by multiple processors collaboratively executing the computer program or by a single processor independently executing the computer program).

[0062] FIG6 is a flow chart of a method for executing multiple computing tasks according to some other embodiments of the present application. Exemplarily, the method described below is implemented by the computer system shown in FIG5 .

[0063] The method shown in FIG6 begins at step 601. In step 601, a task scheduling graph is obtained, for example, by generating the task scheduling graph using one or more processors 501B or by having one or more processors 501B access one or more memories 501A to invoke the task scheduling graph G. The task scheduling graph is assumed to include n task nodes T1-Tn, m control nodes C1-Cm, and k directed edges E1-Ek. The connections between these nodes and the types of control nodes can be determined according to the execution process of the computing tasks required by the actual application. The structure and generation method of the task scheduling graph have been described in detail above and will not be repeated here.

[0064] After completing step 601, the method shown in Figure 6 proceeds to step 602. In this step, one or more processors 501B are used to execute n computing tasks T1-Tn according to the execution flow defined by the task scheduling graph.

[0065] FIG7 is a flowchart according to some other embodiments of the present application, which illustrates a process of executing a computing task according to an execution flow defined by a task scheduling graph.

[0066] As shown in Figure 7, in step 701, one or more processors 501B are used to generate an execution sequence of the computing task (exemplarily denoted as {qi}, where i = 1,...n, qi is one of the computing tasks T1 to Tn) based on the description of the control logic of the control nodes C1 to Cm and the directions indicated by the k directed edges E1 to Ek.

[0067] After completing step 701, the method shown in Figure 7 proceeds to step 702. In this step, one or more processors 501B are used to execute computing tasks T1-Tn according to the process indicated by the execution sequence {qi}.

[0068] According to another aspect of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the program is executed by a processor, one or more steps included in the method described above with reference to Figures 6 and 7 can be implemented.

[0069] Those skilled in the art will appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described herein may be implemented as electronic hardware, computer software, or combinations of both.

[0070] To illustrate the interchangeability between hardware and software, various schematic components, blocks, modules, circuits, and steps are generally described above in terms of their functionality. Whether such functionality is implemented in hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in a varying manner for specific specific applications, but such implementation decisions should not be interpreted as causing a departure from the scope of this application.

[0071] Although only some specific embodiments of the present application have been described, it should be understood by those skilled in the art that the present application may be implemented in many other forms without departing from its spirit and scope. Therefore, the examples and embodiments shown are to be considered illustrative rather than restrictive, and the present application may encompass various modifications and substitutions without departing from the spirit and scope of the present application as defined in the appended claims.

[0072] The embodiments and examples set forth herein are provided to best illustrate embodiments according to the present technology and its specific applications, and thereby enable those skilled in the art to make and use the present application. However, those skilled in the art will appreciate that the above description and examples are provided for ease of illustration and example only. The descriptions set forth are not intended to be exhaustive of all aspects of the present application or to limit the present application to the precise forms disclosed.

Claims

1. A method for performing a plurality of computing tasks, comprising the following steps: The task scheduling graph is generated by a processor or obtained by accessing a memory, wherein the task scheduling graph is generated in the following manner: The task scheduling graph includes a plurality of nodes and edges connecting pairs of nodes to form a plurality of paths, wherein each path represents an optional execution sequence of the plurality of computing tasks, the nodes include a plurality of task nodes and one or more control nodes, each task node represents one of the plurality of computing tasks, and the control node is configured to describe a path through the nodes associated therewith, so that one of the optional execution sequences defines an execution sequence of the plurality of computing tasks; and The processor executes the plurality of computing tasks in accordance with an execution sequence defined by the task scheduling graph.

2. The method of claim 1, wherein: The method for generating the task scheduling graph further includes: assigning directions to the edges connecting the paired nodes, wherein the directions indicate the execution order corresponding to the nodes connected by the edges.

3. The method of claim 1, wherein: The pathway includes one or more of the following: a conditional pathway, a cyclic pathway, and a conditional cyclic pathway.

4. The method of claim 3, wherein: The description of the conditional method at least includes a branch judgment condition, a node pointed to by a branch whose judgment result is true, and a node pointed to by a branch whose judgment result is false.

5. The method of claim 3, wherein: The description of the loop mode at least includes the node where the loop body starts, the node where the loop body ends, the node pointed to after exiting the loop body, and the number of times the nodes in the loop body are executed cyclically.

6. The method of claim 3, wherein: The description of the conditional loop mode at least includes a node where the conditional loop body starts, a node where the conditional loop body ends, a conditional loop judgment condition, and a node to which a branch points when the judgment result is negative.

7. The method of claim 2, wherein: The steps of executing the plurality of computing tasks include: generating an execution sequence of the computing task based on the description of the control node and the direction indicated by the directed edge; and The plurality of computing tasks are executed according to the process indicated by the execution sequence.

8. The method of claim 7, wherein: The task scheduling graph is stored in the form of a linked list, the nodes correspond to data elements of the linked list, and the execution order of the nodes is represented by the link order of pointers in the linked list.

9. The method of claim 7, wherein: The task scheduling graph is stored in the form of an array, the nodes correspond to data elements of the array, and the execution order of the nodes is represented by the order of the data elements.

10. An apparatus for performing a plurality of computing tasks, comprising: at least one processor; at least one memory; a computer program stored in said memory, By running the computer program on the processor to perform the following operations: Generate or obtain a task scheduling graph by accessing the memory, wherein the task scheduling graph is generated in a manner including: causing the task scheduling graph to include a plurality of nodes and edges that connect pairs of nodes to form a plurality of paths, wherein each path represents an optional execution flow of the plurality of computing tasks, the nodes include a plurality of task nodes and one or more control nodes, each task node represents one of the plurality of computing tasks, and the control node is configured to describe a path of a node associated therewith, so that one of the optional execution sequences defines the execution flow of the plurality of computing tasks; and The plurality of computing tasks are executed according to the execution process defined by the task scheduling graph.

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