Data processing method and apparatus

Abstract

Embodiments of the present application relate to the technical field of data communications, and provide a data processing method and apparatus. A first physical layer (PHY) of a sending device receives first instruction information from a first media access control (MAC) layer of the sending device, the first instruction information being used for instructing the sending device to send a service flow to a receiving device; the first PHY acquires a first instruction code block on the basis of the first instruction information, the first instruction code block being used for instructing a second PHY of the receiving device to switch from a sleep state to a working state, and instructing a second serializer / deserializer SerDes corresponding to the second PHY to switch from a keep-alive state to a working state; and the first PHY sends the first instruction code block to the receiving device. By means of the method, the working state can be recovered more quickly while ensuring that the power consumption of the PHY of Ethernet is reduced, and user experience can be further improved.

Description

Data processing method and device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on September 14, 2023, with application number 202311196272.9 and application name “A Data Processing Method and Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The embodiments of the present application relate to the field of data communication technology, and in particular to a data processing method and device. Background Art

[0004] As demand for Ethernet capacity grows, services are placing increasing demands on Ethernet link speeds. Furthermore, Ethernet service bandwidth is also rapidly increasing. With increasing service bandwidth and increasing bit errors on physical links, the physical layer requires a more complex architecture to support these growing service demands. For example, cascaded forward error correction (FEC) increases physical layer power consumption.

[0005] In order to reduce the power consumption of the physical layer (PHY), related technologies have proposed saving power consumption of the physical layer by putting the serializer / deserializer (SerDes) into a dormant state. In the current processing mechanism, it takes a long time for the SerDes to switch from the dormant state to the working state. Specifically, the time required is more than tens of milliseconds (ms). This method not only requires caching business data transmitted for tens of milliseconds or more, but also requires a delay of tens of milliseconds for subsequent business data to be sent. This has a significant impact on the delay experience of Ethernet users, resulting in a poor user experience.

[0006] Summary of the Invention

[0007] The present application provides a data processing method and device to effectively shorten the time it takes for a SerDes to resume working status while saving power consumption at the Ethernet physical layer, reduce the cache of service data, and improve user experience.

[0008] In a first aspect, the present application provides a data processing method, which is applied to a sending device, the sending device including a first medium access control (MAC) layer and a first physical layer (PHY). The sending device may be a device in Ethernet or Hyper Ethernet, such as a switch, a router, etc., which is not specifically limited herein. The method is performed as follows:

[0009] The first PHY receives first indication information from the first MAC layer, where the first indication information is used to instruct the sending device to send a service flow to the receiving device; the first PHY obtains a first indication code block based on the first indication information, where the first indication code block is used to instruct the second PHY of the receiving device to switch from a sleep state to a working state, and to instruct the second SerDes corresponding to the second PHY to switch from a keep-alive state to a working state; the first PHY sends the first indication code block to the receiving device.

[0010] It should be noted that the first PHY obtains the first indication code block according to the first indication information, which can be understood as the first PHY generating the first indication code block according to the first indication information, or the first PHY selecting the indication code block as the first indication code block from the pre-generated indication code blocks according to the first indication information. This application does not specifically limit how to obtain the first indication code block. In addition, the dormant state in this application can be understood as a non-working state, a state of not processing business, and a state of not transmitting business flows; the working state can be understood as a state of transmitting business flows and processing business; and the keep-alive state can be understood as a standby state, which immediately returns to the working state upon receiving a business-related trigger message or instruction.

[0011] In the present application, after the PHY of the sending device receives the first indication information of the MAC layer, it determines that the transmission of the service flow needs to be resumed based on the first indication information, and then obtains the first indication code block based on the first indication information, and indicates the first indication code block to the receiving device, so that the receiving device switches the state of the PHY according to the first indication code block, and the PHY of the receiving device switches from the sleep state to the working state, and the corresponding SerDes switches from the keep-alive state to the working state. In this way, when the Ethernet device is not working, the PHY is in the sleep state, and the corresponding SerDes is in the keep-alive state, which can save power consumption of the physical layer. Once the service is restored, the Ethernet device can respond in time, the PHY switches from the sleep state to the working state, and the SerDes switches from the keep-alive state to the working state. The response when the service is restored is faster, and during the service recovery process, there is no need to cache a large amount of service data waiting for the Ethernet device to resume work, which can improve the user experience and further improve data processing efficiency.

[0012] In an optional manner, the first PHY switches the first PHY from a sleep state to a working state and switches the first SerDes corresponding to the first PHY from a keep-alive state to a working state according to the first indication information.

[0013] It should be noted that the first PHY can directly refer to the first indication information to adjust the working state of the first PHY and the working state of the first SerDes corresponding to the first PHY, and can also obtain the first indication code block based on the first indication information, and adjust the working state of the first PHY and the working state of the first SerDes corresponding to the first PHY according to the first indication code block. This application does not specifically limit this.

[0014] In the present application, when resuming work, the first PHY switches the first PHY from the sleep state to the working state according to the first indication information and switches the first SerDes corresponding to the first PHY from the keep-alive state to the working state, which can ensure rapid response to service recovery and improve user experience.

[0015] In an optional manner, the first PHY includes a first physical coding sublayer (PCS) and a first physical medium attachment (PMA), wherein the first PHY switches from a sleep state to an active state including the first PCS switches from a sleep state to an active state and the first PMA switches from a sleep state to an active state.

[0016] In the present application, the switching of the first PHY from the sleep state to the working state includes the switching of the first PCS from the sleep state to the working state and the switching of the first PMA from the sleep state to the working state, which can ensure rapid response to service recovery and improve user experience.

[0017] In an optional manner, the first PHY receives second indication information from the first MAC layer, and the second indication information is used to instruct the sending device to stop sending service flows to the receiving device; the first PHY obtains a second indication code block based on the second indication information, and the second indication code block is used to instruct the second PHY of the receiving device to switch from a working state to a sleep state, and to instruct the second SerDes corresponding to the second PHY to switch from a working state to a keep-alive state; the first PHY sends the second indication code block to the receiving device.

[0018] It should be noted that the first PHY obtains the second indication code block according to the second indication information, which can be understood as the first PHY generating the second indication code block according to the second indication information, or the first PHY selects an indication code block from the pre-generated indication code blocks as the second indication code block according to the second indication information. This application does not specifically limit how to obtain the second indication code block.

[0019] In this application, after the PHY of the transmitting device receives the second indication information of the MAC layer, it determines that the transmission of the service flow needs to be stopped based on the second indication information. Then, based on the second indication information, it obtains a second indication code block and indicates the second indication code block to the receiving device, so that the receiving device switches the PHY state according to the second indication code block. The PHY of the receiving device switches from the working state to the dormant state, and the corresponding SerDes switches from the working state to the keep-alive state. In this method, when the Ethernet device is not working, the PHY is in the dormant state and the corresponding SerDes is in the keep-alive state, which can save power consumption of the physical layer.

[0020] In an optional manner, the first PHY switches the first PHY from a working state to a sleep state and switches the first SerDes corresponding to the first PHY from a working state to a keep-alive state according to the second indication information.

[0021] It should be noted that the first PHY can directly refer to the second indication information to adjust the working state of the first PHY and the working state of the first SerDes corresponding to the first PHY, and can also obtain the second indication code block based on the second indication information, and adjust the working state of the first PHY and the working state of the first SerDes corresponding to the first PHY according to the second indication code block. This application does not specifically limit this.

[0022] In the present application, when the first PHY stops working, the first PHY is switched from the working state to the sleep state according to the second indication information, and the first SerDes corresponding to the first PHY is switched from the working state to the keep-alive state, which can ensure a quick response to service suspension and save power consumption.

[0023] In an optional manner, the first PHY includes a first PCS and a first PMA, wherein the switching of the first PHY from an active state to a sleep state includes the switching of the first PCS from an active state to a sleep state and the switching of the first PMA from an active state to a sleep state.

[0024] In the present application, the switching of the first PHY from the working state to the sleep state includes the switching of the first PCS from the working state to the sleep state and the switching of the first PMA from the working state to the sleep state, which can ensure a quick response to service stoppage and save power consumption.

[0025] In an optional manner, the first PCS switches the first PCS from a sleep state to a working state according to the first indication information, and obtains a first indication code block; the first PCS sends the first indication code block to the first PMA; the first PMA switches the first PMA from a sleep state to a working state according to the received first indication code block.

[0026] In an optional manner, the first PCS switches the first PCS from a sleep state to a working state according to the first indication information, and sends the first indication information to the first PMA; the first PMA switches the first PMA from a sleep state to a working state according to the received first indication information, and obtains a first indication code block.

[0027] In the present application, the first PCS switches the first PCS from the sleep state to the working state according to the first indication information. The first indication information can be directly transmitted to the first PMA, and the first indication code block can be obtained and the first indication code block can be transmitted to the first PMA to enable the first PMA to switch the state. Regardless of which method is used, it can be ensured that the first PCS and the first PMA are switched from the sleep state to the working state, which can ensure rapid business recovery and improve data processing efficiency.

[0028] In an optional manner, the first PCS switches the first PCS from the working state to the sleep state according to the second indication information, and obtains the second indication code block; the first PCS sends the second indication code block to the first PMA; the first PMA switches the first PMA from the working state to the sleep state according to the received second indication code block.

[0029] In an optional manner, the first PCS switches the first PCS from the working state to the sleep state according to the second indication information, and sends the second indication information to the first PMA; the first PMA switches the first PMA from the working state to the sleep state according to the received second indication information, and obtains the second indication code block.

[0030] In the present application, the first PCS switches the first PCS from the working state to the sleep state according to the second indication information. The second indication information can be directly transmitted to the first PMA. The second indication code block can also be obtained and the second indication code block can be transmitted to the first PMA to enable the first PMA to switch the state. Regardless of which method is used, it can be ensured that the first PCS and the first PMA are switched from the working state to the sleep state, which can ensure that the business is quickly stopped and improve data processing efficiency.

[0031] In an optional manner, the first PCS includes multiple first PCS channels, and the first PCS switches the multiple first PCS channels from a dormant state to a working state; or, the first PCS switches some of the multiple first PCS channels from a dormant state to a working state according to a first service flow rate threshold.

[0032] In this application, when the service is restored, part or all of the first PCS channels can be switched from the sleep state to the working state based on the actual service traffic demand. This method can further save the power consumption of the physical layer while ensuring the normal transmission of the service.

[0033] In an optional manner, the first PCS includes multiple first PCS channels, and the first PCS switches the multiple first PCS channels from a working state to a dormant state; or, the first PCS switches some of the multiple first PCS channels from a working state to a dormant state according to a second service flow rate threshold.

[0034] In this application, when the service is stopped, part or all of the first PCS channels can be switched from the working state to the sleep state based on the actual service traffic demand. This method can further save the power consumption of the physical layer while ensuring the normal transmission of the service.

[0035] In an optional manner, the first PCS includes multiple first PCS channels, and the first PCS sends the first indication code block via at least one first PCS channel among the multiple first PCS channels.

[0036] In the present application, when the service is restored, the multiple first PCS channels of the first PCS may all send the first indication code block, or may partially send the first indication code block, which is not specifically limited here, as long as it is ensured that the receiving device can receive the first indication code block.

[0037] In an optional manner, the first PCS includes multiple first PCS channels, and the first PCS sends the second indication code block via at least one first PCS channel among the multiple first PCS channels.

[0038] In the present application, when the service is paused, multiple first PCS channels of the first PCS may all send the second indication code block, or may partially send the second indication code block, which is not specifically limited here, as long as it is ensured that the receiving device can receive the second indication code block.

[0039] In an optional manner, the first PHY includes a first physical media dependent (PMD), and the first PHY switches the first PMD from a keep-alive state to a working state according to the first indication information; the first PHY switches the first SerDes corresponding to the first PMD from a keep-alive state to a working state.

[0040] In the present application, the first PMD is switched from the keep-alive state to the working state, and the first SerDes corresponding to the first PMD is switched from the keep-alive state to the working state, which can ensure rapid response to service recovery and improve user experience.

[0041] In an optional manner, the first PMD includes multiple first PMD channels, and the first PMD switches the multiple first PMD channels from a keep-alive state to a working state; or, the first PMD switches some of the multiple first PMD channels from a keep-alive state to a working state according to a first service flow rate threshold.

[0042] In this application, when the service is restored, part or all of the first PMD channels can be switched from the keep-alive state to the working state based on the actual service traffic demand. This method can further save the power consumption of the physical layer while ensuring normal transmission of the service.

[0043] In an optional manner, when the first SerDes is in a keep-alive state, the first PHY periodically sends a keep-alive code block to the receiving device via the first SerDes.

[0044] This approach ensures that when the service is restored, the first SerDes can respond to service needs in a timely manner and resume service transmission.

[0045] In an optional manner, the length of the first indicator code block is 10 bits, 64 bits, 66 bits, 128 bits or 130 bits.

[0046] In a second aspect, the present application provides a data processing method, which is applied to a receiving device, the receiving device including a second PHY. The receiving device may be a device in Ethernet or a device in Hyper-Ethernet, such as a switch, a router, etc., which is not specifically limited herein. The method is performed as follows:

[0047] The second PHY receives a first indication code block sent by the first PHY in the transmitting device, where the first indication code block is used to instruct the second PHY to switch from a sleep state to a working state, and to instruct the second SerDes corresponding to the second PHY to switch from a keep-alive state to a working state; the second PHY switches the second PHY from a sleep state to a working state and switches the second SerDes corresponding to the second PHY from a keep-alive state to a working state according to the first indication code block.

[0048] In the present application, a receiving device receives a first indication code block from a transmitting device, so that the receiving device switches the state of the PHY according to the first indication code block, and the PHY of the receiving device switches from a sleep state to a working state, and the corresponding SerDes switches from a keep-alive state to a working state. In this manner, when the Ethernet device is not working, the PHY is in a sleep state, and the corresponding SerDes is in a keep-alive state, which can save power consumption at the physical layer. Once the service is restored, the Ethernet device can respond in a timely manner, the PHY switches from a sleep state to a working state, and the SerDes switches from a keep-alive state to a working state. When the service is restored, the response is faster, and during the service recovery process, there is no need to cache a large amount of service data waiting for the Ethernet device to resume work, which can improve the user experience and further improve data processing efficiency.

[0049] In an optional manner, the second PHY includes a second PCS and a second PMA, wherein the second PHY switching from a sleep state to an active state includes the second PCS switching from a sleep state to an active state and the second PMA switching from a sleep state to an active state.

[0050] In the present application, the second PHY switches from a sleep state to an active state, including the second PCS switches from a sleep state to an active state and the first PMA switches from a sleep state to an active state, which can ensure rapid response to service recovery and improve user experience.

[0051] In an optional manner, the second PHY receives a second indication code block sent by the first PHY in the transmitting device, where the second indication code block is used to instruct the second PHY to switch from a working state to a sleep state, and to instruct the second SerDes corresponding to the second PHY to switch from a working state to a keep-alive state; the second PHY switches the second PHY from a working state to a sleep state and switches the second SerDes corresponding to the second PHY from a working state to a keep-alive state according to the second indication code block.

[0052] In this application, a receiving device receives a second indication code block from a transmitting device, so that the receiving device switches the PHY state according to the second indication code block. The PHY of the receiving device switches from an active state to a sleep state, and the corresponding SerDes switches from an active state to a keep-alive state. In this manner, when the Ethernet device is not operating, the PHY is in a sleep state and the corresponding SerDes is in a keep-alive state, which can save power consumption at the physical layer.

[0053] In an optional manner, the second PHY includes a second PCS and a second PMA, wherein the switching of the second PHY from an active state to a sleep state includes the switching of the second PCS from an active state to a sleep state and the switching of the second PMA from an active state to a sleep state.

[0054] In the present application, the second PHY switches from the working state to the sleep state, including the second PCS switches from the working state to the sleep state and the second PMA switches from the working state to the sleep state, which can ensure a quick response to service stop and save power consumption.

[0055] In an optional manner, the second PMA switches the second PMA from the sleep state to the working state according to the first indication code block; the second PMA sends the first indication information to the second PCS; the second PCS receives the first indication information and switches the second PCS from the sleep state to the working state.

[0056] In the present application, the second PMA switches the second PMA from the sleep state to the working state according to the first indication code block. The first indication code block can be directly transmitted to the second PCS, and the first indication information can be obtained and the first indication information can be transmitted to the second PCS to enable the second PCS to switch the state. Regardless of which method is used, it can be ensured that the second PCS and the second PMA are switched from the sleep state to the working state, which can ensure rapid business recovery and improve data processing efficiency.

[0057] In an optional manner, the second PMA switches the second PMA from the working state to the sleep state according to the second indication code block; the second PMA sends second indication information to the second PCS; the second PCS receives the second indication information and switches the second PCS from the working state to the sleep state.

[0058] In the present application, the second PMA switches the second PMA from a working state to a sleep state according to the second indication code block. The second indication code block can be directly transparently transmitted to the second PCS. The second indication information can also be obtained and the second indication information can be transmitted to the second PCS to enable the second PCS to switch the state. Regardless of which method is used, it can be ensured that the second PCS and the second PMA are switched from the sleep state to the working state, which can ensure that the business is quickly stopped and the data processing efficiency is improved.

[0059] In an optional manner, the second PCS includes multiple second PCS channels, and the second PCS switches the multiple second PCS channels from a dormant state to a working state; or, the second PCS switches some of the multiple second PCS channels from a dormant state to a working state according to a first service flow rate threshold.

[0060] In this application, when the service is restored, part or all of the second PCS channels can be switched from the sleep state to the working state based on the actual service traffic demand. This method can further save the power consumption of the physical layer while ensuring the normal transmission of the service.

[0061] In an optional manner, the second PCS includes multiple second PCS channels, and the second PCS switches the multiple second PCS channels from a working state to a dormant state; or, the second PCS switches some of the multiple second PCS channels from a working state to a dormant state according to a second service flow rate threshold.

[0062] In this application, when the service is stopped, part or all of the second PCS channels can be switched from the working state to the dormant state based on the actual service traffic demand. This method can further save the power consumption of the physical layer while ensuring the normal transmission of the service.

[0063] In an optional manner, the second PHY includes a second physical medium dependent PMD, and the second PHY switches the second PMD from a keep-alive state to a working state according to the first indication code block; the second PHY switches the second SerDes corresponding to the second PMD from a keep-alive state to a working state.

[0064] In this application, the second PMD is switched from the keep-alive state to the working state, and the second SerDes corresponding to the second PMD is switched from the keep-alive state to the working state, which can ensure rapid response to service recovery and improve user experience.

[0065] In an optional manner, the second PMD includes multiple second PMD channels, and the second PMD switches the multiple second PMD channels from a keep-alive state to a working state; or, the second PMD switches some of the multiple second PMD channels from a keep-alive state to a working state according to a first service flow rate threshold.

[0066] In this application, when the service is restored, part or all of the second PMD channels can be switched from the keep-alive state to the working state based on the actual service traffic demand. This method can further save the power consumption of the physical layer while ensuring normal transmission of the service.

[0067] In an optional manner, the second PCS includes multiple second PCS channels, and the second PCS receives the second indication information via at least one second PCS channel among the multiple second PCS channels.

[0068] In an optional manner, when the second SerDes is in a keep-alive state, the second PHY periodically receives a keep-alive code block via the second SerDes.

[0069] In an optional manner, the length of the first indicator code block is 10 bits, 64 bits, 66 bits, 128 bits or 130 bits.

[0070] In a third aspect, an embodiment of the present application provides a data processing method, which is applied to a sending device, the sending device including a first MAC layer and a first PHY. The sending device may be a device in Ethernet or a device in Hyper Ethernet, such as a switch, a router, etc., which is not specifically limited herein. The method is performed as follows:

[0071] The first PHY receives second indication information from the first MAC layer, where the second indication information is used to instruct the sending device to stop sending service flows to the receiving device; the first PHY obtains a second indication code block based on the second indication information, where the second indication code block is used to instruct the second PHY of the receiving device to switch from a working state to a sleep state, and to instruct the second SerDes corresponding to the second PHY to switch from a working state to a keep-alive state; the first PHY sends the second indication code block to the receiving device.

[0072] In an optional manner, the first PHY switches the first PHY from a working state to a sleep state and switches the first SerDes corresponding to the first PHY from a working state to a keep-alive state according to the second indication information.

[0073] In an optional manner, the first PHY includes a first PCS and a first PMA, and the first PHY obtains a second indication code block according to the second indication information, including:

[0074] The first PCS switches the first PCS from the working state to the sleep state according to the second indication information and obtains the second indication code block; the first PCS sends the second indication code block to the first PMA; the first PMA switches the first PMA from the working state to the sleep state according to the received second indication code block.

[0075] In an optional manner, the first PHY obtains the second indication code block according to the second indication information, including:

[0076] The first PCS switches the first PCS from the working state to the sleep state according to the second indication information, and sends the second indication information to the first PMA; the first PMA switches the first PMA from the working state to the sleep state according to the received second indication information, and obtains the second indication code block.

[0077] In an optional manner, the first PCS includes multiple first PCS channels, wherein the first PCS switches the first PCS from a working state to a dormant state according to the second indication information, including:

[0078] The first PCS switches the plurality of first PCS channels from an active state to a dormant state; or, the first PCS switches some of the plurality of first PCS channels from an active state to a dormant state according to a second service flow rate threshold.

[0079] In an optional manner, the first PCS includes multiple first PCS channels, and the first PCS sends a second indication code block to the first PMA, including:

[0080] The first PCS sends a second indication code block via at least one first PCS channel among the plurality of first PCS channels.

[0081] In an optional manner, when the first SerDes is in a keep-alive state, the first PHY periodically sends a keep-alive code block to the receiving device via the first SerDes.

[0082] In an optional manner, the length of the second indicator code block is 10 bits, 64 bits, 66 bits, 128 bits, or 130 bits.

[0083] In a fourth aspect, the present application provides a data processing method, which is applied to a receiving device, the receiving device including a second physical layer PHY. The receiving device may be a device in Ethernet or a device in Hyper Ethernet, such as a switch, a router, etc., which is not specifically limited herein. The method is performed as follows:

[0084] The second PHY receives a second indication code block sent by the first PHY in the transmitting device, where the second indication code block is used to instruct the second PHY to switch from a working state to a sleep state, and to instruct the second SerDes corresponding to the second PHY to switch from a working state to a keep-alive state; the second PHY switches the second PHY from a working state to a sleep state and switches the second SerDes corresponding to the second PHY from a working state to a keep-alive state according to the second indication code block.

[0085] In an optional manner, the second PHY includes a second PCS and a second PMA, wherein the second PHY switching from an active state to a sleep state includes the second PCS switching from an active state to a sleep state and the second PMA switching from an active state to a sleep state.

[0086] In an optional manner, the second PHY switches the second PHY from a working state to a sleep state according to the second indication code block, including:

[0087] The second PMA switches the second PMA from the working state to the sleep state according to the second indication code block; the second PMA sends second indication information to the second PCS; the second PCS receives the second indication information and switches the second PCS from the working state to the sleep state.

[0088] In an optional manner, the second PCS includes multiple second PCS channels, and the second PCS receives the second indication information, including:

[0089] The second PCS receives the second indication information via at least one second PCS channel among the plurality of second PCS channels.

[0090] In an optional manner, the second PCS includes multiple second PCS channels, wherein the second PCS receives the second indication information and switches the second PCS from a working state to a dormant state, including:

[0091] The second PCS switches the plurality of second PCS channels from an active state to a dormant state; or, the second PCS switches some of the plurality of second PCS channels from an active state to a dormant state according to a second service flow rate threshold.

[0092] In an optional manner, when the second SerDes is in a keep-alive state, the second PHY periodically receives a keep-alive code block via the second SerDes.

[0093] In an optional manner, the length of the second indicator code block is 10 bits, 64 bits, 66 bits, 128 bits or 130 bits.

[0094] In a fifth aspect, an embodiment of the present application provides a data processing device, which may be a sending device (such as the sending device in the first aspect, the sending device in the second aspect, the sending device in the third aspect, or the sending device in the fourth aspect) or a chip arranged inside the sending device, or a receiving device (such as the receiving device in the first aspect, the receiving device in the second aspect, the receiving device in the third aspect, or the receiving device in the fourth aspect) or a chip arranged inside the receiving device. The communication device has the function of implementing any of the above-mentioned first to fourth aspects. For example, the data processing device includes a module or unit or means corresponding to the steps involved in any of the above-mentioned first to fourth aspects. The function or unit or means may be implemented by software, or by hardware, or the corresponding software implementation may be executed by hardware.

[0095] In one possible design, the data processing device includes a processing unit and a transceiver unit, wherein the transceiver unit can be used to send and receive instruction code blocks or instruction information to achieve communication between the data processing device and other devices; the processing unit can be used to perform some internal operations of the data processing device. The transceiver unit can be called an input / output unit, a communication unit, etc., and the transceiver unit can be a transceiver; the processing unit can be a processor. When the data processing device is a module (such as a chip) in a communication device, the transceiver unit can be an input / output interface, an input / output circuit, or an input / output pin, etc., and can also be called an interface, a communication interface, or an interface circuit, etc.; the processing unit can be a processor, a processing circuit, or a logic circuit, etc.

[0096] In another possible design, the data processing device includes a processor and may also include a transceiver, the transceiver is used to send and receive signals, and the processor executes program instructions to complete the method in any possible design or implementation of the first to fourth aspects above. The data processing device may also include one or more memories, the memory is used to couple with the processor, and the memory can store the necessary computer programs or instructions for implementing the functions involved in any of the first to fourth aspects above. The processor can execute the computer program or instructions stored in the memory, and when the computer program or instructions are executed, the data processing device implements the method in any possible design or implementation of the first to fourth aspects above.

[0097] In another possible design, the data processing device includes a processor, which can be coupled to a memory. The memory can store the necessary computer programs or instructions for implementing the functions of any of the first to fourth aspects described above. The processor can execute the computer programs or instructions stored in the memory. When the computer programs or instructions are executed, the data processing device implements the method of any possible design or implementation of the first to fourth aspects described above.

[0098] In another possible design, the data processing device includes a processor and an interface circuit, wherein the processor is used to communicate with other devices through the interface circuit and execute the method in any possible design or implementation of the first to fourth aspects above.

[0099] It can be understood that in the fifth aspect above, the processor can be implemented by hardware or by software. When implemented by hardware, the processor can be a logic circuit, an integrated circuit, etc.; when implemented by software, the processor can be a general-purpose processor, which is implemented by reading the software code stored in the memory. In addition, the above processors can be one or more, and the memories can be one or more. The memory can be integrated with the processor, or the memory and the processor can be set separately. In the specific implementation process, the memory can be integrated with the processor on the same chip, or can be set on different chips respectively. The embodiment of the present application does not limit the type of memory and the setting method of the memory and the processor.

[0100] In a sixth aspect, an embodiment of the present application provides a data processing system, which includes the sending device and the receiving device in the above-mentioned first to fourth aspects.

[0101] In a seventh aspect, the present application provides a chip comprising a processor and further comprising a memory for implementing the method described in any one of the possible designs of aspects 1 to 4 above. The chip system may be composed of the chip alone or may include a chip and other discrete devices.

[0102] In an eighth aspect, the present application provides an integrated circuit, which includes an interface circuit and a control circuit, and the interface circuit is coupled to the control circuit; the interface circuit is used to receive first indication information from a first MAC layer through a first PHY, and the first indication information is used to instruct a sending device to send a service flow to a receiving device; the control circuit is used to obtain a first indication code block according to the first indication information through the first PHY, and the first indication code block is used to instruct the second PHY of the receiving device to switch from a sleep state to a working state, and to instruct the second serializer / deserializer SerDes corresponding to the second PHY to switch from a keep-alive state to a working state; the interface circuit is also used to send the first indication code block to the receiving device through the first PHY.

[0103] In a ninth aspect, the present application provides another integrated circuit, which includes an interface circuit and a control circuit, and the interface circuit is coupled to the control circuit; the interface circuit is used to receive a first indication code block sent by a first PHY in a sending device through a second PHY, and the first indication code block is used to instruct the second PHY to switch from a sleep state to a working state, and to instruct the second serializer / deserializer SerDes corresponding to the second PHY to switch from a keep-alive state to a working state; the control circuit is used to switch the second PHY from a sleep state to a working state and the second SerDes corresponding to the second PHY from a keep-alive state to a working state according to the first indication code block through the second PHY.

[0104] In the tenth aspect, the present application also provides a computer-readable storage medium, which stores computer-readable instructions. When the computer-readable instructions are run on a computer, the computer executes a method in any possible design as in the first to fourth aspects.

[0105] In an eleventh aspect, the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the methods of the various embodiments of the first to fourth aspects described above.

[0106] For the technical effects that can be achieved in the above-mentioned second to eleventh aspects, please refer to the description of the technical effects that can be achieved by the corresponding possible design schemes in the above-mentioned first aspect, and this application will not repeat them here. BRIEF DESCRIPTION OF THE DRAWINGS

[0107] Figure 1 shows a schematic diagram of interface composition and communication;

[0108] FIG2A shows a schematic diagram of an electrical chip interface composition and communication;

[0109] FIG2B shows a schematic diagram of a PCS logic function;

[0110] FIG2C shows a schematic diagram of another PCS logic function;

[0111] FIG2D shows a schematic diagram of a PMD logic function;

[0112] FIG2E shows a schematic diagram of implementing PHY through an electrical chip and an optical module chip;

[0113] FIG2F shows a schematic diagram of a channel for implementing 100GE PHY using an electrical chip and an optical module chip;

[0114] FIG3 shows a schematic diagram of a data processing flow;

[0115] FIG4 shows a schematic diagram of the structure of a SerDes and a PHY;

[0116] FIG5 shows a schematic diagram of transmission of a keep-alive code block;

[0117] FIG6 shows a schematic diagram of a data processing flow;

[0118] FIG7 shows a schematic diagram of a data processing flow;

[0119] FIG8 shows a schematic diagram of a data processing flow;

[0120] FIG9 shows a schematic structural diagram of a communication device provided in an embodiment of the present application;

[0121] FIG10 shows a schematic structural diagram of another data processing device;

[0122] FIG11 shows a schematic structural diagram of another data processing device. DETAILED DESCRIPTION

[0123] In this application, the media independent interface (MII) is referred to as MII at 10 Mb / s and 100 Mb / s, as GMII at 1000 Mb / s, and as XGMI at 10 Gb / s. The xMII in this application may include RMII (reduced MII), serial MII (serial MII, SMII), serial synchronous MII (serial sync MII, SSMII), source synchronous SMII (source synchronous SMII, S3MII), Gigabit MII (Gigabit MII, GMII), RGMII (Reduced GMII), serial GMII (serial GMII, SGMII), 10 bit interface (ten bit interface, TBI), RTBI (Reduced TBI), 10 Gigabit MII (10Gigabit MII, XGMII), 25 Gigabit MII (25Gigabit MII), 40 Gigabit MII, 50 Gigabit MII, 100 Gigabit MII (100Gb / s MII, CGMII), 200 Gigabit MII (200Gb / s MII, 200GMII), 400 Gigabit MII (400Gb / s MII, 400GMII), 800 Gigabit MII, 1.6 Terabit MII and other Ethernet interfaces.

[0124] The 200GbE / 400GbE speed standards implement a new generation of Ethernet speed standards based on 50G four-level pulse amplitude modulation (PAM4) technology for a single-channel electrical interface. Research into the next-generation Ethernet 800G / 1.6TE standard is underway. As single-channel electrical interface speeds increase to 100G PAM4 or 200G (using N-level pulse amplitude modulation (PAM-N), where N=4, 6, or 8), the next-generation speeds may support these electrical interface rates, potentially requiring compatibility with legacy 50G per-channel electrical interfaces. Optical interface speeds have the potential to evolve over multiple paths, including per-wavelength rates of 50Gbps / 100Gbps / 200Gbps / 400Gbps / 800Gbps, and so on.

[0125] Currently, various Ethernet interface logical layer solutions share certain common features, but also significant differences between interfaces at different rates. These differences make it difficult to share hardware resources between different rates, or to interconnect multiple low-rate Ethernet interfaces by binding them to a single high-rate interface module. For example, the 200GbE / 400GbE interface uses the logical layer architecture shown in Figure 1. In Figure 1, the device interface includes the medium access control (MAC) layer, the reconciliation sublayer (RS), the physical coding sublayer (PCS), cascaded forward error correction (FEC), the physical medium attachment (PMA), and the physical media dependent (PMD). The PCS, FEC, PMA, and PMD belong to the physical layer (PHY). Data from the transmitting device is processed and sent from the PMD to the receiving device's PMD. After processing by multiple submodules, data reaches the MAC layer. The PCS sublayer implements functions such as 64B / 66B encoding and decoding, transcoding, scrambling, alignment marker (AM) insertion, and FEC encoding and decoding. The PMA sublayer implements functions such as clock recovery, carrier detection, and PAM4 modulation / demodulation. The PMD sublayer performs parallel-to-serial / serial-to-parallel conversion on received data and modulates the digital signal for transmission. Within the PCS FEC sublayer, the introduction of new interleaved FEC (such as Reed-Solomon RS (544, 514) FEC) significantly deviates from the 100GbE solution at the logical layer, requiring significant redevelopment. For example, the logical layer defined by 400G-ZR utilizes the architecture shown in Figure 2A. Figure 2A shows a schematic diagram of the components of an electrical chip interface. Under this logical layer architecture, an optical module supporting 400G-ZR (80km) cannot support a 2x200GbE interface due to the fixed host-side interface being 400GAUI (attachment unit interface).

[0126] The data transmission scenarios of Figures 1 and 2A can be applicable to Ethernet, or unified bus (UB), infinite bandwidth (IB), peripheral component interconnect express (PCIE) in hyper Ethernet and other similar data communication systems, and are not specifically limited in this application. The sending device and the receiving device can be a switch and a router, etc., and are not specifically limited in this application. In addition, it should be noted that there is only one sending device and receiving device illustrated in Figure 1, but in actual applications, the data processing scenario may include multiple sending devices and receiving devices, and the sending device can also be used as a receiving device, and the receiving device can also be used as a sending device, which is not specifically limited in this application.

[0127] In order to more clearly illustrate the solution of the present application, the PHY is described in detail. The PHY includes PCS, PMA, and PMD. It should be noted that PCS, PMA, and PMD are sublayers of PHY. Among them, channels (lanes) are provided between the PCS and PMA, between the PMA of the electrical chip and the PMA of the optical module chip, between the PMD and the medium, and between the PMA and the PMD. For example, there is a logical lane between the PCS and the PMA, which can also be called a PCS lane; there may also be another logical lane between the PCS and the PMA, which can also be called an FEC lane; there may be a physical lane between the PMA of the electrical chip and the PMA of the optical module chip, which can also be called a PMA lane; in addition, there may also be a logical lane between the PMA layer and the PMD; there may be a physical lane between the PMD and the medium, which can also be called a PMD lane. Among them, logical lanes are also called virtual lanes. The number of channels can be configured according to actual needs, and the specific number is not limited. For example, the number of PCS lanes can be set to 8, 10, 12 or 16. This is only an example and does not specifically limit the number of logical channels.

[0128] Among them, PCS is usually connected to the MAC chip via MII. Specifically, PCS is connected to the RS in the MAC chip via MII. In PHY, the main function of PCS is to reduce overhead and has certain error detection and correction capabilities. For example, in the transmitting device, PCS includes a 64B / 66B encoding module, which converts the 72B code block into 66B, thereby reducing overhead. PCS can also include a 256B / 257B encoding module, which compresses every 4 66B code blocks into 1 257B code block, thereby further reducing overhead. PCS can also include a scrambling module, which is used to change the sequence content so that the number of 0s and 1s in the data sequence is balanced, and to ensure the frequency of 0 / 1 hopping to facilitate the operation of the phase-locked loop of the receiving device. Among them, a sufficiently long random number cycle period prevents malicious intrusion from causing the phase-locked loop to fail. The PCS also includes a distribution and interleaving module. After encoding, the module distributes the two RS codewords into PCS lanes, interleaving the codewords A and B on each lane to achieve interleaving. The PCS also includes an AM insertion module, which enables the receiving device to find RS codeword boundaries. Furthermore, the PCS includes FEC, which improves the PHY's error detection and correction capabilities.

[0129] The logical functions that the PCS can perform are shown in Figures 2B and 2C. Figure 2B illustrates the logical functions of 40GBASE-R and 100GBASE-R, while Figure 2C illustrates the logical functions of 200GBASE-R and 400GBASE-R. Figure 2C adds FEC to Figure 2B and makes some logical adjustments. 40GBASE-R, 100GBASE-R, 200GBASE-R, and 400GBASE-R represent PHY types. Taking 40GBASE-R as an example, "40G" represents the rate, "BASE" indicates baseband modulation, and "R" indicates the use of 64B / 66B encoding. Next, referring to Figure 2B, we will first explain the logical functions of the PCS. After the PCS of the transmitting device receives the data information from the MAC, it encodes it through the encoding module (encode) to obtain a coding block, scrambles the coding block through the scrambling module (scramble), distributes the scrambled coding block through the distribution module (Block Distribution), inserts the AM (alignment marker) into the scrambled coding block through the AM insertion module, and then transmits the data to the PMA through the logical channel. The data processing logic of the PMA and the layers after the PMA are not explained in detail here. The PCS of the receiving device receives the code block from the PMA, synchronizes the code blocks of each virtual channel through the block synchronization module (lane BLOCK SYNC), and then eliminates the SKEW between the PCS virtual channels through the SKEW elimination module (Alignment LOCK lane DESKEW). After eliminating the SKEW between the PCS virtual channels, the sorting module (Lane Reorder) sorts the data stream based on the PCS virtual channels so that the data stream can enter the correct PCS lane. The AM removal module (Alignment Removal) removes the AM in the code block, which is then descrambled by the descrambler module and decoded by the decoder module to obtain the data information. SKEW is a processing module used to eliminate skew between PCS lanes. Specifically, after completing the AM operation, the PCS lanes will be skewed. Therefore, the SKEW module is used to eliminate the skew to ensure alignment with the physical lanes in subsequent processing.

[0130] Next, refer to Figure 2C to describe the logical functions of the PCS. Because 200G BASE-R and 400G BASE-R are larger, the PCS of the transmitting device receives data information from the MAC and performs encoding and rate matching through the encoding and rate matching module to obtain a coded block. The encoding conversion module (256B / 257B transcode) converts the four 66-bit blocks in the coded block into a 257-bit block. The scrambling module then scrambles the coded block to obtain a scrambled coded block. The alignment insertion module inserts the AM into the scrambled coded block. The pre-FEC distribution module then splits the data into symbols before FEC encoding and distributes them. The FEC encoder module then performs FEC encoding. The distribution and interleaver module performs distribution and symbol interleaving. Finally, the data is transmitted to the PMA through logical lanes. The data processing logic of the PMA and the layers following the PMA is not described in detail here. The PCS of the receiving device receives the code blocks from the PMA, eliminates the SKEW between the PCS virtual lanes through the SKEW elimination module (Alignment Lock Lane Deskew), and then sorts and deinterleaves the data stream through the Lane Reorder and De-Interleaver module. The FEC decoding module then performs FEC decoding. The symbol deinterleaver module deinterleaves the FEC-decoded symbols, removes AM from the code blocks through the Alignment Removal module, and descrambles the code blocks through the Descrambler module. The Reverse Transcoder module converts the 257-bit blocks to 66-bit blocks. The Decoder and Rate Matching modules then perform encoding, decoding, and rate matching to obtain data information.

[0131] It should be noted that the 200GBASE-R and 400GBASE-R PCS provide all the services required for MII with a MAC layer rate of 200G and MII with a MAC layer rate of 400G (hereinafter referred to as 200GMI / 400GMII), including the following:

[0132] a) Encode (decode) 8 200GMI / 400GMII data bytes to (from) 66-bit blocks (64B / 66B).

[0133] b) Transcode from 66-bit blocks to 257-bit blocks, and then perform scrambling (descrambling) processing.

[0134] c) Reed-Solomon encoded (decoded) 257-bit blocks.

[0135] d) Transmitting the coded data to the PMA or transmitting the coded data to the PMA after interleaving.

[0136] e) Compensate for any rate differences due to insertion or deletion of alignment markers or due to any rate differences between 200GMII / 400GMII and PMA by inserting or deleting idle control characters.

[0137] f) Determine when a functional link is established and notify the management entity via management data input / output (MDIO) when the PHY is ready for use.

[0138] It should also be noted that the main functions of the PMA in the transmit and receive directions include the following:

[0139] a) Adapt PCS lane formatted signals to the appropriate number of abstract or physical lanes.

[0140] b) Provide clock and data recovery for each input lane.

[0141] c) Provide bit-level multiplexing.

[0142] d) Provide clock generation.

[0143] e) Provide signal drive.

[0144] f) Optionally provide local loopback to or from the PMA service interface.

[0145] g) Optionally provide remote loopback to the PMD service interface or remote loopback from the PMA service interface.

[0146] h) Optionally provide test pattern generation and detection.

[0147] i) SKEW mutation is allowed.

[0148] j) Perform PAM4 encoding and decoding for 200GBASE-R PMA with 4 physical lanes and 400GBASE-R PMA with 4 or 8 physical lanes.

[0149] The PMA is used for modulation and demodulation. Commonly used channel transmission modulation formats include non-return-to-zero (NRZ), PAM4, and 16-quadrature amplitude modulation (16-QAM). The PMA is also used for clock and data recovery (CDR) and signal driving. The CDR extracts the clock from the received signal and recovers the binary data, achieving analog-to-digital conversion. The signal driver provides power for the attachment unit interface (AUI) signal transmission, achieving digital-to-analog conversion.

[0150] Among them, PMD realizes the transmitter of electrical / optical signals and the connector with the transmission medium.

[0151] In addition, after the PMD service interface of the transmitting device receives the data from the PMA, it can perform operations such as Gray encoding and precoding as shown in FIG2D and then transmit the data to the receiving device.

[0152] It should be noted that FIG1 of the embodiment of the present application illustrates the implementation method of PHY using an electrical chip, wherein the PMD of the transmitting device in FIG1 is used to connect to the electrical transmission medium.

[0153] In actual application scenarios, PHY can also be implemented through the cooperation of an electrical chip (indicated by a dotted line in FIG2E ) and an optical module chip (indicated by a dotted line in FIG2E ), as shown in FIG2E .

[0154] For example, the PHY includes an electrical chip and an optical module chip. The electrical chip includes a PCS and a PMA. The PCS of the electrical chip connects to the RS of the MAC chip via the MII, and the PMA of the electrical chip connects to the PMA in the optical module chip via the AUI. In addition, the optical module chip also includes a PMD, which connects to the optical transmission medium via a medium-dependent interface (MDI).

[0155] For example, a PHY chip includes an electrical chip, a PMA module, and an optical module chip. The electrical chip includes a PCS and a PMA. The PCS of the electrical chip connects to the RS of the MAC chip via the MII. Furthermore, the PMA of the electrical chip connects to the PMA module via the AUI. The PMA module can be implemented as a separate chip. The PMA module connects to the PMA in the optical module chip via the AUI. Furthermore, the optical module chip also includes a PMD, which connects to the optical transmission medium via the MDI.

[0156] In the above architecture, for example, 100GE PHY is implemented using an electrical chip, a PMA module, and an optical module chip, as shown in Figure 2F. Typically, the PCS lanes included in the PCS are logical lanes, such as four 25G PCS lanes. Correspondingly, the PCS can also include four 25G FEC lanes (logical lanes). The PMA in the electrical chip includes four 25G PMA lanes (physical lanes), corresponding to four 25G PCS lanes. The PMA in the electrical chip includes four 25G PMA lanes connected to the PMA module. Correspondingly, the PMA module can include two 50G PMA lanes (physical lanes). The two 50G PMA lanes in the PMA module are used to connect to the PMA in the optical module chip. The PMA in the optical module chip includes one 100G PMA lane (logical lane), corresponding to two 50G PMA lanes. The one 100G PMA lane is used to connect to the PMD in the optical module chip. The PMD in the optical module chip includes one 100G PMD lane (physical lane), which corresponds to one 100G PMA lane. The PMD in the optical module chip includes one 100G PMD lane for connecting the media.

[0157] In the above architecture, AUI is the channel for chip interconnection. SerDes is usually used on both sides of AUI for serial-to-parallel conversion. Therefore, the serializer / deserializer (SerDes) implements some of the functions of the PMA in PHY. In addition, PMD is the connector of the transmission medium, and the functions of PMD are usually also implemented by SerDes. Therefore, SerDes is mainly used to implement the functions of PMA and PMD in PHY. In other words, SerDes implements some functions of the PHY protocol layer in a physical form.

[0158] It should be noted that SerDes is a serial-to-parallel signal conversion device that converts parallel signals into parallel-to-serial (serialization) and serial-to-parallel (deserialization) conversion of serial signals. SerDes is part of PHY. Traditional parallel buses are generally single-ended signal transmissions, which can be multi-point connections or point-to-point connections, with clocks and data separated. When the data rate is further increased, the bandwidth can be increased by increasing the bus width and increasing the clock rate, but the clock must be coordinated (strict setup and hold times need to be met between data and clock, there is crosstalk between signals, weak anti-common mode interference capability, electromagnetic interference (EMI) problems of the equipment, and too much printed circuit board (PCB) space is occupied, etc.), and its bus clock rate can only reach the 100M level. The high-speed serial data bus overcomes the shortcomings of the parallel bus and increases the data transmission rate by several levels. SerDes has the following advantages:

[0159] 1) Use serial signals to reduce the difficulty of single-board wiring, reduce the impact of crosstalk between signals, and reduce the difficulty of timing design;

[0160] 2) Eliminate the skew problem of parallel signal transmission and increase data transmission rate;

[0161] 3) No dedicated clock signal is required (the clock is directly recovered from the data). Data and clock are transmitted on one chip pin, which greatly saves pins, reduces packaging costs and saves board space. There is no separate clock, and the clock signal is extracted from the data.

[0162] 4) Using serial differential data bus output can improve the ability to resist common mode interference;

[0163] 5) Through pre-processing on the sending side and filtering on the receiving side, the signal quality is improved and the impact of the external environment on the signal is greatly reduced;

[0164] 6) Through SerDes, chips can be connected across multiple boards, which expands the scope of chip use and improves the scalability of the architecture.

[0165] In conjunction with the above, SerDes corresponds one-to-one to physical lanes. For example, if the PMA in an electrical chip includes four 25G PMA lanes, it means that it includes four SerDes in physical form. In the embodiment of the present application, the energy-saving control and state switching control implemented on the SerDes refers to the energy-saving control and state switching control implemented on at least one of the SerDes that implements the PMA function and the SerDes that implements the PMD function.

[0166] As the demand for Ethernet capacity expands, services are requiring higher and higher rates for Ethernet links, and the power consumption of PHY is increasing. Related technologies propose to turn off SerDes when there is no service transmission to save power consumption. However, when the service is restored, the SerDes recovery work takes a long time. During the SerDes recovery period, a large amount of service data will be cached, and there will be delays in the service data. This method will reduce the user's service experience, and a large amount of service cache may require a chip with a higher rate, which will also increase the cost of equipment. Based on this, there is an urgent need for a new data processing method that can reduce the cache of service data while saving PHY power consumption and improve the user experience. The data processing of this application mainly considers the situation of service suspension and service recovery during service flow transmission.

[0167] Refer to Figure 3, which is a flow chart of a data processing method provided in an embodiment of the present application. The method can be executed through data interaction between a sending device and a receiving device, wherein the sending device and the receiving device can be devices in Ethernet, or devices in Hyper Ethernet, which is not specifically limited in this application. The sending device and the receiving device can be routers, switches, etc. Only the data interaction between the sending device MAC layer (also known as the first MAC layer), PHY (also known as the first PHY) and the receiving device MAC layer (also known as the second MAC layer), PHY (also known as the second PHY) is described here, and the data interaction of other layers is not described in detail here. Figure 3 is applicable to the scenario of resuming business after business suspension, and is executed as follows:

[0168] Step 301: The first MAC layer sends first indication information to the first PHY, where the first indication information is used to instruct a sending device to send a service flow to a receiving device.

[0169] Before executing step 301, the sending device has obtained the service flow, and based on the service flow, triggered the first MAC layer of the sending device to send the first indication information to the first PHY, or the sending device receives an indication message sent by the upper-layer device, which is used to indicate service recovery, so that the first MAC layer of the sending device sends the first indication information to the first PHY. The specific method used to trigger the sending of the first indication information is not specifically limited in this application.

[0170] Specifically, the first indication information may be a data block in a service flow, or may be signaling (or notification message), etc. This is merely an example, and the present application does not specifically limit the form of the first indication information.

[0171] Referring to Figure 2A above, it can be seen that the MAC layer includes RS. The first MAC layer sending the first indication information to the first PHY can be understood as the RS of the MAC chip sending the first indication information to the PCS of the PHY electrical chip through the MII. This is only an example explanation and does not specifically limit the transmission path of the first indication information.

[0172] In step 302, the first PHY obtains a first indication code block according to the first indication information. The first indication code block is used to instruct the second PHY of the receiving device to switch from the sleep state to the working state, and to instruct the second SerDes corresponding to the second PHY to switch from the keep-alive state to the working state.

[0173] It should be noted that acquisition can be understood as generation, selection, selection, etc. For example, the first PHY generates a first indication code block according to the first indication information, or the first PHY selects (or selects) an indication code block as the first indication code block from the pre-generated indication code blocks according to the first indication information, etc. This application does not specifically limit this. When the first indication information is used to generate the first indication code block, the first indication information can be encoded to obtain the first indication code block. When the first indication information is used to select the first indication code block, the first PHY can pre-select the corresponding relationship between the stored indication information and the indication code block, and determine the first indication code block based on the acquired first indication information and the corresponding relationship. This is only an exemplary explanation.

[0174] The dormant state in this application can be understood as a non-working state, a state of not processing business, and a state of not transmitting business flow; the working state can be understood as a state of transmitting business flow and processing business; the keep-alive state can be understood as a standby state, and once a business-related trigger message or instruction is received, it immediately returns to the working state. The following descriptions related to the dormant state, working state, and keep-alive state can be understood with reference to this.

[0175] It should also be noted that the first PHY can switch the first PHY from a dormant state to an active state and switch the first SerDes corresponding to the first PHY from a keep-alive state to an active state according to the first indication information. The first PHY can directly adjust the working state of the first PHY and the working state of the first SerDes corresponding to the first PHY with reference to the first indication information, and can also obtain a first indication code block based on the first indication information, and adjust the working state of the first PHY and the working state of the first SerDes corresponding to the first PHY according to the first indication code block. This is not specifically limited in this application. When the first PHY resumes work, it switches the first PHY from a dormant state to an active state and switches the first SerDes corresponding to the first PHY from a keep-alive state to an active state according to the first indication information, which can ensure a rapid response to service recovery and improve user experience.

[0176] In addition, the first SerDes corresponding to the first PHY (or the second SerDes corresponding to the second PHY) can be provided together with the PHY in one chip, or can be provided separately from the PHY in a different chip, which is not specifically limited in this application. Referring to FIG1 above, it can be seen that PHY also includes PCS, PMA and PMD, etc. In addition, as mentioned above in the introduction of SerDes, SerDes is mainly used to implement the functions of PMA and PMD in PHY. The AUI of PMA can be implemented through SerDes, and the PMD connection medium can also be implemented through SerDes. SerDes needs to be switched to a working state. All SerDes can be switched in state, or some SerDes can be switched in state (such as switching the SerDes implemented by the AUI of PMA to a working state, without switching the SerDes implemented by the PMD connection medium). This application is not specifically limited here. In actual applications, the SerDes implemented by the AUI of PMA and the SerDes implemented by the PMD connection medium can be implemented by two different chips, or by the same chip. Refer to FIG2F. If the same chip is used for implementation, the SerDes implemented by the AUI of PMA and the SerDes implemented by the PMD connection medium belong to two different hardware units, which are not specifically limited here. The following can refer to this to understand the working state switching of SerDes, which will not be repeated elsewhere.

[0177] For illustration purposes, a first PHY includes a first PCS, a first PMA, and a first PMD, and a second PHY includes a second PCS, a second PMA, and a second PMD. As shown in FIG4 , the first SerDes is located in the first PMD, while the second SerDes is not located in the second PMD. In other words, the SerDes that implement the PMD function can be located in the PHY chip or not. The chips of the transmitting and receiving devices shown in FIG4 are electrical chips. The first SerDes can be located in the electrical chip PMD, while the second SerDes can be located independently of the electrical chip PMD. Regardless of the configuration, the SerDes are connected via an electrical interface. Furthermore, if the chips of the transmitting and receiving devices are optical module chips, the first SerDes can be located in the optical module chip PMD, while the second SerDes can be located independently of the optical module chip PMD. Regardless of the configuration, the SerDes are connected via an optical interface. If the SerDes is not configured in the PMD, the PHY switching from the sleep state to the working state includes the PCS switching from the sleep state to the working state, the PMA switching from the sleep state to the working state, and the PMD switching from the sleep state to the working state. If the SerDes is configured in the PMD, the PHY switching from the sleep state to the working state includes the PCS switching from the sleep state to the working state and the PMA switching from the sleep state to the working state. At this time, the PMD switches from the keep-alive state to the working state.

[0178] Furthermore, when the first PHY includes a first PCS, a first PMA, and a first PMD, when executing step 302, the first PCS may switch the first PCS from a dormant state to an active state based on the first indication information and obtain a first indication code block; the first PCS may send the first indication code block to the first PMA; and the first PMA may switch the first PMA from a dormant state to an active state based on the received first indication code block. Alternatively, the first PCS may switch the first PCS from a dormant state to an active state based on the first indication information and send the first indication information to the first PMA; the first PMA may switch the first PMA from a dormant state to an active state based on the received first indication information and obtain the first indication code block. Of course, in actual applications, the first PCS may switch the first PCS from a dormant state to an active state based on the first indication information and send the first indication information to the first PMA; the first PMA may switch the first PMA from a dormant state to an active state based on the received first indication information and send the first indication information to the first PMD; the first PMD may switch the first PMA from a dormant state (or a keep-alive state) to an active state based on the first indication information and obtain the first indication code block. Regardless of which method is adopted, it can be ensured that the first PHY is switched from the sleep state to the working state, which can ensure rapid service recovery and improve data processing efficiency.

[0179] In addition, when the first SerDes is set in the first PMD, the first PHY can switch the first PMD from the keep-alive state to the working state according to the first indication information, and switch the first SerDes corresponding to the first PMD from the keep-alive state to the working state.

[0180] It should also be noted that the first PCS and the first PMA of the first PHY transmit data through logical channels. The number of logical channels can be flexibly set according to business needs. For example, in the 100GE PHY, it includes 4 25G PCS lanes. The first PMD transmits data through a physical channel. The number of physical channels is limited and cannot be expanded arbitrarily. However, in actual business transmission, the logical channels and physical channels can correspond one to one, such as one logical channel corresponding to one physical channel. It can also be a many-to-one correspondence between logical channels and physical channels, such as four logical channels corresponding to one physical channel. Usually, when transmitting data, the sending device and the receiving device can predefine in advance which channels to use for data transmission. Of course, when switching the data transmission channel, the sending device can also send an indication signaling to the receiving device in advance to notify the switched data transmission channel before transmitting data. This application does not specifically limit this. Regarding logical channels, the PCS channel is taken as an example. The first PCS includes multiple PCS lanes. The first PCS switches multiple PCS lanes from a dormant state to a working state. For example, the first PCS is set with 16 PCS lanes, and all 16 PCS lanes can be switched from a dormant state to a working state; or, the first PCS switches some of the multiple first PCS channels from a dormant state to a working state according to a first service flow rate threshold. For example, if the service flow rate is W, the first service flow rate threshold is W1, and W is less than W1, then 10 PCS lanes can be switched from a dormant state to a working state. In addition, the first PCS can send the first indication code block via at least one first PCS lane among the multiple first PCS lanes (if all the above-mentioned PCS lanes are switched from the sleep state to the working state, all PCS lanes are used to send the first indication code block, such as using 16 PCS lanes to send the first indication code block; if some of the above-mentioned PCS lanes are switched from the sleep state to the working state, some of the PCS lanes are used to send the first indication code block, such as using 10 PCS lanes to send the first indication code block), as long as the first PMA is guaranteed to receive the first indication code block.

[0181] Regarding the physical channel, the PMD channel is taken as an example to illustrate. The first PMD includes multiple first PMD channels. The first PMD switches the multiple first PMD channels from the keep-alive state to the working state. For example, the first PMD sets 8 PMD lanes, and all 8 PMD lanes can be switched from the keep-alive state to the working state; or, the first PMD switches some of the multiple PMD lanes from the keep-alive state to the working state according to the first business flow rate threshold. For example, the business flow rate is W, the first business flow rate threshold is W1, W is less than W1, then 3 PMD lanes can be switched from the keep-alive state to the working state.

[0182] In addition, it should be noted that in actual application, multiple service flow rate thresholds can be set according to needs, and the number of virtual channels and logical channels used to transmit service data can be determined according to different service flow rate thresholds. For example, PCS lanes include 20 and PMD lanes include 16, and the service flow rate thresholds are W1, W2, and W3 (W1>W2>W3). When the service flow rate is less than W1, 10 PCS lanes of the first PCS and 3 PMD lanes of the first PMD are used to transmit service data; when the service flow rate is greater than W1 and less than W2, 12 PCS lanes of the first PCS and 4 PMD lanes of the first PMD are used to transmit service data; when the service flow rate is greater than W2 and less than W3, 15 PCS lanes of the first PCS and 6 PMD lanes of the first PMD are used to transmit service data. This is only an example and is not specifically limited. The following description of service flow rate thresholds can be understood with reference to the description here.

[0183] Step 303: The first PHY sends a first indication code block to the second PHY of the receiving device.

[0184] The length of the first indicator code block can be 10 bits, 64 bits, 66 bits, 128 bits, or 130 bits, such as 66-bit Blocks. The data structure of 66-bit Blocks is shown in Table 1 below, where Hd represents the head of the 66-bit Blocks, the default value is 0x1, and M0-M7 are the payload of the 66-bit Blocks.

[0185] Table 1

[0186] Step 304 : The second PHY switches the second PHY from the sleep state to the working state and switches the second SerDes corresponding to the second PHY from the keep-alive state to the working state according to the first indication code block.

[0187] In addition, when the second PHY includes a second PCS, a second PMA, and a second PMD, when executing step 304, the second PMA can switch the second PMA from a sleep state to a working state according to the first indication code block; the second PMA sends the first indication information to the second PCS (specifically, the second PMA can obtain the first indication information according to the first indication code block, such as determined according to the mapping relationship between the indication code block and the indication information, or directly generate the first indication information based on the first indication code block, which is not specifically limited here); the second PCS receives the first indication information and switches the second PCS from a sleep state to a working state. Alternatively, the second PMA can switch the second PMA from a sleep state to a working state according to the first indication code block; the second PMA sends the first indication code block to the second PCS; the second PCS receives the first indication code block, and switches the second PCS from a sleep state to a working state. Regardless of which method is used, it can be ensured that the second PHY is switched from a sleep state to a working state, which can ensure rapid service recovery and improve data processing efficiency.

[0188] In addition, when the second SerDes is set in the second PMD, the second PHY can switch the first PMD from the keep-alive state to the working state according to the first indication information or the first indication code block, and switch the second SerDes corresponding to the second PMD from the keep-alive state to the working state.

[0189] It should also be noted that the second PCS and second PMA of the second PHY transmit data through logical channels, and the number of such logical channels can be flexibly set according to business requirements. The second PMD transmits data through physical channels, and the number of such physical channels is limited and cannot be arbitrarily expanded. However, in actual business transmission, the logical channels and physical channels can correspond one-to-one, such as one logical channel corresponding to one physical channel. It can also be a many-to-one correspondence between logical channels and physical channels, such as four logical channels corresponding to one physical channel. Typically, during data transmission, the sending device and the receiving device can predefine in advance which channels are used to transmit data. Of course, when switching data transmission channels, the sending device can also send indication signaling to the receiving device in advance to notify the switched data transmission channel before transmitting data. This is not specifically limited in this application. Regarding logical channels, the PCS channel is used as an example for explanation. The second PCS includes multiple second PCS channels. The second PCS switches the multiple second PCS channels from a dormant state to a working state. For example, the second PCS is provided with 16 PCS lanes, and all 16 PCS lanes can be switched from a dormant state to a working state. Alternatively, the second PCS switches some of the multiple second PCS channels from a dormant state to a working state according to a first service flow rate threshold. For example, if the service flow rate is W, the first service flow rate threshold is W1, and W is less than W1, then 10 PCS lanes can be switched from a dormant state to a working state.

[0190] Regarding physical channels, the PMA channel is used as an example to illustrate that the second PMD includes multiple second PMD channels. The second PMD switches the multiple second PMD channels from a keep-alive state to an operating state. For example, if the second PMD is provided with eight PMD lanes, all eight PMD lanes can be switched from a keep-alive state to an operating state. Alternatively, the second PMD switches some of the multiple second PMD channels from a keep-alive state to an operating state based on a first service flow rate threshold. For example, if the service flow rate is W, the first service flow rate threshold is W1, and W is less than W1, then three PMD lanes can be switched from a keep-alive state to an operating state. Furthermore, it should be noted that, in actual applications, multiple service flow rate thresholds can be set as needed, and the number of logical channels and physical channels used to transmit service data can be determined based on different service flow rate thresholds. This can be understood with reference to the description of step 303 above, and will not be repeated here.

[0191] It should also be noted that when the first SerDes and the second SerDes are in a keep-alive state, the first PHY periodically sends a keep-alive code block to the receiving device via the first SerDes, and the second PHY periodically receives the keep-alive code block via the second SerDes. The keep-alive code block does not include service information and can be a pseudo-random code block. For example, a keep-alive code block is sent every 5 microseconds, and 10 keep-alive code blocks can be sent. The data transmission of the keep-alive code block can be understood with reference to Figure 5. In case 1, when the first SerDes is set in the first PMD, the keep-alive code block enters the first SerDes in the first PMD through the first PCS and the first PMA of the first PHY and is transmitted to the second SerDes. The keep-alive code block does not undergo data processing through the first PCS and the first PMA, that is, the encoding, interleaving and other processing operations in Figures 2A or 2B are not performed, and directly reaches the first SerDes for data processing. In case 2, when the first SerDes is not set in the first PMD, the keep-alive code block enters the first SerDes through the first PCS, the first PMA, and the first PMD of the first PHY and is transmitted to the second SerDes. The keep-alive code block does not undergo data processing through the first PCS, the first PMA, and the first PMD, that is, the encoding, interleaving, and other processing operations in the above-mentioned Figures 2A or 2B are not performed, and directly reaches the first SerDes for data processing.

[0192] In the present application, after the PHY of the sending device receives the first indication information of the MAC layer, it determines that the transmission of the service flow needs to be resumed based on the first indication information, and then obtains the first indication code block based on the first indication information, and indicates the first indication code block to the receiving device, so that the receiving device switches the state of the PHY according to the first indication code block, and the PHY of the receiving device switches from the sleep state to the working state, and the corresponding SerDes switches from the keep-alive state to the working state. In this way, when the Ethernet device is not working, the PHY is in the sleep state, and the corresponding SerDes is in the keep-alive state, which can save power consumption of the physical layer. Once the service is restored, the Ethernet device can respond in time, the PHY switches from the sleep state to the working state, and the SerDes switches from the keep-alive state to the working state. The response when the service is restored is faster, and during the service recovery process, there is no need to cache a large amount of service data waiting for the Ethernet device to resume work, which can improve the user experience and further improve data processing efficiency.

[0193] Refer to Figure 6 for a flow chart of a data processing method provided in an embodiment of the present application. The method can be executed through data interaction between a sending device and a receiving device, wherein the sending device and the receiving device can be devices in Ethernet, or devices in Hyper Ethernet, which is not specifically limited in this application. The sending device and the receiving device can be routers, switches, etc. Only the data interaction between the sending device MAC layer (also known as the first MAC layer), PHY (also known as the first PHY) and the receiving device MAC layer (also known as the second MAC layer), PHY (also known as the second PHY) is described here, and the data interaction of other layers is not expanded here. Figure 3 is applicable to the scenario of service suspension, and is executed as follows:

[0194] Step 601: The first MAC layer sends second indication information to the first PHY, where the second indication information is used to instruct the sending device to stop sending the service flow to the receiving device.

[0195] Before executing step 601, the sending device fails to obtain the service flow for a preset period of time, such as failing to obtain the service flow within 5 seconds. Based on this, the first MAC layer of the sending device is triggered to send the second indication information to the first PHY, or the sending device receives an indication message sent by the upper-layer device, which is used to indicate that the service is suspended, so that the first MAC layer of the sending device sends the second indication information to the first PHY. The specific method of triggering the sending of the second indication information is not specifically limited in this application.

[0196] Specifically, the second indication information may be signaling (or notification message), etc. This is only an example, and the present application does not specifically limit the form of the second indication information.

[0197] Referring to Figure 2A above, it can be seen that the MAC layer includes RS. The first MAC layer sending the second indication information to the first PHY can be understood as the RS of the MAC chip sending the second indication information to the PCS of the PHY electrical chip through the MII. This is only an example explanation and does not specifically limit the transmission path of the second indication information.

[0198] In step 602, the first PHY obtains a second indication code block according to the second indication information. The second indication code block is used to instruct the second PHY of the receiving device to switch from the working state to the sleep state, and to instruct the second SerDes corresponding to the second PHY to switch from the working state to the keep-alive state.

[0199] It should be noted that acquisition can be understood as generation, selection, selection, etc. For example, the first PHY generates a second indication code block according to the second indication information, or the first PHY selects (or selects) an indication code block as the second indication code block from the pre-generated indication code block according to the second indication information, etc. This application does not specifically limit this. When the second indication information is used to generate the second indication code block, the second indication information can be encoded to obtain the second indication code block. When the second indication information is used to select the second indication code block, the first PHY can pre-select the corresponding relationship between the stored indication information and the indication code block, and determine the second indication code block based on the acquired second indication information and the corresponding relationship. This is only an exemplary explanation.

[0200] It should also be noted that the first PHY can switch the second PHY from an operating state to a dormant state and the first SerDes corresponding to the first PHY from an operating state to a keep-alive state according to the second indication information. The first PHY can directly adjust the operating state of the first PHY and the operating state of the first SerDes corresponding to the first PHY with reference to the second indication information, and can also obtain a second indication code block based on the second indication information and adjust the operating state of the first PHY and the operating state of the first SerDes corresponding to the first PHY according to the second indication code block. This is not specifically limited in this application. When the first PHY suspends operation, the first PHY switches the first PHY from an operating state to a dormant state and the first SerDes corresponding to the first PHY from an operating state to a keep-alive state according to the second indication information, thereby ensuring a rapid response to service suspension.

[0201] In addition, the first SerDes corresponding to the first PHY (or the second SerDes corresponding to the second PHY) can be provided together with the PHY in one chip, or can be provided separately from the PHY in a different chip, which is not specifically limited in this application.

[0202] Referring to FIG. 1 above, it can be seen that the PHY also includes a PCS, a PMA, and a PMD. Here, the first PHY includes a first PCS, a first PMA, and a first PMD, and the second PHY includes a second PCS, a second PMA, and a second PMD as an example. If the SerDes is not set in the PMD, the switching of the PHY from the working state to the sleep state includes the switching of the PCS from the working state to the sleep state, the switching of the PMA from the working state to the sleep state, and the switching of the PMD from the working state to the sleep state. If the SerDes is set in the PMD, the switching of the PHY from the working state to the sleep state means that the PCS switches from the working state to the sleep state and the PMA switches from the working state to the sleep state. At this time, the PMD switches from the working state to the keep-alive state.

[0203] Furthermore, when the first PHY includes a first PCS, a first PMA, and a first PMD, when executing step 602, the first PCS may switch the first PCS from an active state to a sleep state based on the second indication information and obtain a second indication code block; the first PCS may send the second indication code block to the first PMA; and the first PMA may switch the first PMA from an active state to a sleep state based on the received second indication code block. Alternatively, the first PCS may switch the first PCS from an active state to a sleep state based on the second indication information and send the second indication information to the first PMA; the first PMA may switch the first PMA from an active state to a sleep state based on the received second indication information and obtain the second indication code block. Of course, in actual applications, the first PCS may switch the first PCS from an active state to a sleep state based on the second indication information and send the second indication information to the first PMA; the first PMA may switch the first PMA from an active state to a sleep state based on the received second indication information and send the second indication information to the first PMD; the first PMD may switch from an active state to a sleep state (or a keep-alive state) based on the second indication information and obtain the second indication code block. Regardless of which method is adopted, it can be ensured that the first PHY is switched from the working state to the dormant state, and the service can be quickly suspended.

[0204] In addition, when the first SerDes is set in the first PMD, the first PHY can switch the first PMD from the working state to the keep-alive state according to the second indication information, and switch the first SerDes corresponding to the first PMD from the working state to the keep-alive state.

[0205] It should also be noted that the first PCS and first PMA of the first PHY transmit data via logical channels. The number of logical channels can be flexibly set according to business needs. For example, a 100GE PHY includes two 50G PMA lanes. The first PMD transmits data via physical channels. The number of physical channels is limited and cannot be arbitrarily expanded. However, in actual business transmission, the logical channels and physical channels can correspond one-to-one, such as one logical channel corresponding to one physical channel. It can also be a many-to-one relationship, such as four logical channels corresponding to one physical channel. Typically, during data transmission, the sending device and the receiving device can predefine which channels to use for data transmission. Of course, when switching data transmission channels, the sending device can also send indication signaling to the receiving device in advance to notify the switched data transmission channel before transmitting data. This application does not specifically limit this. Regarding logical channels, the PCS channel is taken as an example. The first PCS includes multiple first PCS channels. The first PCS switches the multiple first PCS channels from the working state to the dormant state. For example, the first PCS is set with 16 PCS lanes, and all 16 PCS lanes can be switched from the working state to the dormant state; or, the first PCS switches some of the multiple first PCS channels from the working state to the dormant state according to the second service flow rate threshold. For example, the service flow rate is S, the second service flow rate threshold is S1, and S is less than S1, then 10 PCS lanes can be switched from the working state to the dormant state. In addition, the first PCS can send the second indication code block via at least one first PCS channel among the multiple first PCS channels (if all of the above-mentioned first PCS channels are switched from the working state to the sleep state, all of the first PCS channels are used to send the second indication code block, such as using 16 PCS lanes to send the second indication code block; if some of the above-mentioned PCS lanes are switched from the sleep state to the working state, some of the PCS lanes are used to send the second indication code block, such as using 10 PCS lanes to send the second indication code block), as long as it is ensured that the first PMA receives the second indication code block.

[0206] Regarding the physical channel, the PMD channel is taken as an example to illustrate. The first PMD includes multiple first PMD channels. The first PMD switches the multiple first PMD channels from the working state to the keep-alive state. For example, the first PMD sets 8 PMD lanes, and all 8 PMD lanes can be switched from the working state to the keep-alive state; or, the first PMD switches some of the multiple PMD lanes from the working state to the keep-alive state according to the second business flow rate threshold. For example, the business flow rate is S, the second business flow rate threshold is S1, S is less than S1, then 3 PMD lanes can be switched from the working state to the keep-alive state.

[0207] Step 603: The first PHY sends a second indication code block to the receiving device.

[0208] The length of the second indicator code block may be 10 bits, 64 bits, 66 bits, 128 bits or 130 bits, such as 66-bit Blocks, which may be understood with reference to Table 1 above and will not be described in detail here.

[0209] Step 604 : The second PHY switches the second PHY from an active state to a sleep state and switches the second SerDes corresponding to the second PHY from an active state to a keep-alive state according to the second indication code block.

[0210] In addition, when the second PHY includes a second PCS, a second PMA, and a second PMD, when executing step 604, the second PMA can switch the second PMA from a working state to a sleep state according to the second indication code block; the second PMA sends a second indication message to the second PCS (specifically, the second PMA can obtain the second indication information according to the second indication code block, such as determined according to the mapping relationship between the indication code block and the indication information, or directly generate the second indication information based on the second indication code block, which is not specifically limited here); the second PCS receives the second indication information and switches the second PCS from a working state to a sleep state. Alternatively, the second PMA can switch the second PMA from a working state to a sleep state according to the second indication code block; the second PMA sends a second indication code block to the second PCS; the second PCS receives the second indication code block, and switches the second PCS from a working state to a sleep state. Regardless of which method is used, it can be ensured that the second PHY is switched from a working state to a sleep state, and the service can be quickly suspended.

[0211] In addition, when the second SerDes is set in the second PMD, the second PHY can switch the first PMD from the working state to the keep-alive state according to the second indication information or the second indication code block, and switch the second SerDes corresponding to the second PMD from the working state to the keep-alive state.

[0212] It should also be noted that the second PCS and second PMA of the second PHY transmit data through logical channels, and the number of such logical channels can be flexibly set according to business requirements. The second PMD transmits data through physical channels, and the number of such physical channels is limited and cannot be arbitrarily expanded. However, in actual business transmission, the logical channels and physical channels can correspond one-to-one, such as one logical channel corresponding to one physical channel. It can also be a many-to-one correspondence between logical channels and physical channels, such as four logical channels corresponding to one physical channel. Typically, during data transmission, the sending device and the receiving device can predefine in advance which channels are used to transmit data. Of course, when switching data transmission channels, the sending device can also send indication signaling to the receiving device in advance to notify the switched data transmission channel before transmitting data. This is not specifically limited in this application. Regarding logical channels, using PCS channels as an example, the second PCS includes multiple second PCS lanes. The second PCS switches the multiple second PCS lanes from an active state to a dormant state. For example, if the second PCS has 16 PCS lanes, all 16 PCS lanes may be switched from an active state to a dormant state. Alternatively, the second PCS switches some of the multiple second PCS lanes from an active state to a dormant state based on a second service flow rate threshold. For example, if the service flow rate is S, the second service flow rate threshold is S1, and S is less than S1, then 10 PCS lanes may be switched from a dormant state to an active state. Furthermore, the second PCS receives second indication information via at least one of the multiple second PCS lanes. If all 16 PCS lanes are switched from an active state to a dormant state, the second indication information is received via all 16 PCS lanes. If 10 PCS lanes are switched from a dormant state to an active state, the second indication information is received via all 10 PCS lanes.

[0213] For physical channels, the channel of PMD is used as an example to illustrate. The second PMD includes multiple second PMD channels. The second PMD switches the multiple second PMD channels from a working state to a keep-alive state. For example, the second PMD sets 8 PMD lanes, and all 8 PMD lanes can be switched from a working state to a keep-alive state; or, the second PMD switches some of the second PMD channels in the multiple second PMD channels from a working state to a keep-alive state according to a second traffic flow rate threshold. For example, if the traffic flow rate is S, the second traffic flow rate threshold is S1, and S is less than S1, then 3 PMD lanes can be switched from a working state to a keep-alive state. In addition, it should be noted that, in actual application, multiple traffic flow rate thresholds can be set according to demand, and how many logical channels and physical channels are used to transmit traffic data can be determined according to different traffic flow rate thresholds. This can be understood with reference to the description of step 303 above and will not be repeated here.

[0214] In this application, after the PHY of the transmitting device receives the second indication information of the MAC layer, it determines that the transmission of the service flow needs to be stopped based on the second indication information. Then, based on the second indication information, it obtains a second indication code block and indicates the second indication code block to the receiving device, so that the receiving device switches the PHY state according to the second indication code block. The PHY of the receiving device switches from the working state to the dormant state, and the corresponding SerDes switches from the working state to the keep-alive state. In this method, when the Ethernet device is not working, the PHY is in the dormant state and the corresponding SerDes is in the keep-alive state, which can save power consumption of the physical layer.

[0215] To better illustrate the solution of this application, the following describes the data processing logic during service resumption and service suspension using two different scenarios: a low bit error rate (no FEC) and a high bit error rate (with FEC). Specific details are as follows:

[0216] Case 1: For scenarios where the Ethernet physical link has a low bit error rate (NO FEC) and the rate is less than or equal to 100G, such as the application of NRZ physical links such as 10G / 25G / 40G (4*10G) / 50G (2*25G) / 100G (4*25G)

[0217] Figure 7 shows a schematic diagram of the business processing flow from data stop to data recovery, taking 100GE PHY as an example. In the figure, the sending device (TX) and the receiving device (RX) are illustrated by setting SerDes in the PMD of the PHY as an example, wherein PKT indicates the time when business data is transmitted, and IDLE indicates the time when business data is not transmitted. The MAC layer of TX detects that there is no business message (that is, the cache is empty), and only transmits IDLE code stream (that is, empty business code stream), generates stop flow indication information (that is, the second indication information mentioned above), and transmits the stop flow indication information to the PCS (specifically, the MAC layer RS ​​transmits the stop flow indication information through the MII). The stop flow indication information can be a notification message, etc., which can be understood with reference to the second indication information mentioned above. The stop flow indication information can also be a low-power code stream or a normal power consumption code stream, which is not specifically limited in this application. The PCS generates a stop flow code block (that is, a second indication code block) according to the stop flow indication. The stop flow code block is illustrated by taking 66-bit blocks as an example. The time interval of the stop flow code block can be set according to business requirements. For example, if the stop flow operation needs to be performed quickly, the time interval can be set to 5 milliseconds. If the stop flow operation is not required too quickly, the time interval can be set to 10 milliseconds. This is only an example and is not specifically limited. The number of stop flow code blocks can be multiple to ensure that RX can receive it. The specific setting is not specifically limited in this application. The PCS can transmit the stop-flow code block to the PMA via the PCS lane (the logical channel is indicated by the dotted line in Figure 7, and two 50G PCS lanes are used as an example in Figure 7). The PMA transmits the stop-flow code block to the PMD via the PMA lane (four 25G PMA lanes are used as an example in Figure 7). The PMD transmits the stop-flow code block to the RX's PMD via the PMD lane (two 50G PMD lanes are used as an example in Figure 7, and the physical channel is indicated by a solid line). The RX's PMD transmits the stop-flow code block to the PMA via the PMA lane (four 25G PMA lanes are used as an example in Figure 7). The PMA uses a fuzzy matching method to identify. If the number of received stop-flow code blocks exceeds a predefined stop-flow threshold, it determines that the detected code block is a legitimate stop-flow indication. The PMA can convert the stop-flow code block into stop-flow indication information and transmit it to the PCS via the PCS lane (two 50G PCS lanes are used as an example in Figure 7). The PCS transmits it to the MAC layer via the MII.Afterwards, the PCS and PMA of TX and the PCS and PMA of RX are switched from the working state to the sleep state, the PMD of TX and the PMD of RX are switched from the working state to the keep-alive state, and the SerDes of PMD is also switched from the working state to the keep-alive state. In addition, the PMA of TX can generate a pseudo-random code block (i.e., a keep-alive code block, such as a pseudo-random code block, a scrambled IDLE code block) according to the stop flow indication code block, and transmit it between the SerDes of TX and the SerDes of RX to ensure that the SerDes is in the keep-alive state. Once the service is restored, the SerDes can respond in time to resume the transmission of the service.

[0218] In addition, once the service of the sending device is restored, the MAC layer of TX detects the service message, generates a flow indication information (that is, the first indication information mentioned above), and transmits the flow indication information to PCS. The flow indication information can be a notification message, etc., which can be understood with reference to the first indication information mentioned above. The flow indication information can be a low-power code stream, or a normal power code stream, which is not specifically limited in this application. PCS generates a flow code block (that is, a first indication code block) according to the flow indication. The flow code block is illustrated by taking 66-bit blocks as an example. The time interval of the flow code block can be set according to the service requirements. If it is necessary to quickly execute the stop flow and resume service flow operation, the time interval can be set to 5 milliseconds. If it is not necessary to recover too quickly, the time interval can be set to 10 milliseconds. The number of flow code blocks can be multiple to ensure that RX can receive it. The specific setting is not specifically limited in this application. The PCS transmits the transmission block to the PMA via the PCS lane. The PMA transmits the transmission block to the PMD via the PMA lane. The PMD transmits the transmission block to the RX PMD via the PMD lane. The RX PMD transmits the transmission block to the PMA via the PMA lane. The PMA uses fuzzy matching to identify the received transmission block. If the number of received transmission blocks exceeds a predefined threshold for resuming service flow, it determines that the detected block is a legitimate transmission indication. The PMA converts the transmission block into transmission indication information and transmits it to the PCS via the PCS lane. The PCS transmits it to the MAC layer via the PCS lane. The TX PCS and PMA, as well as the RX PCS and PMA, then switch from sleep to active mode. The TX PMD and RX PMD switch from keepalive mode to active mode. The PMD's SerDes also switches from keepalive mode to active mode.

[0219] Case 2: Ethernet physical link PAM4 (bit error rate becomes high and with FEC error correction code) and the rate is greater than or equal to 50G, such as 50G (1*50G) / 100G (2*50G) / 200G (4*50G / 2*100G) / 400G (8*50G / 4*100G) and other PAM4 physical link applications

[0220] FIG8 illustrates a schematic diagram of the service processing flow from data stop to data resumption, using a 200GE PHY as an example. The figure illustrates the transmitter (TX) and receiver (RX) using an example in which the PHY's PMD does not have a SerDes configured. PKT indicates when service data is being transmitted, and IDLE indicates when service data is not being transmitted. The MAC layer of the TX detects the absence of service packets and transmits only the IDLE stream (i.e., an empty service stream). It generates a stop flow indication (i.e., the second indication) and transmits it to the PCS (specifically, the MAC layer RS ​​transmits the stop flow indication via the MII). This stop flow indication can be a notification message, etc., which can be understood with reference to the second indication. This stop flow indication can be a low-power stream or a normal-power stream, which is not specifically limited in this application. The PCS generates a stop flow code block (i.e., the second indication code block) based on the stop flow indication. This stop flow code block is exemplified by a pattern of N*8-bit to 64-bit blocks (N is a natural number, such as N=1 to 8). The pattern can be composed of multiple interval patterns (8-bit to 64-bit). The size and interval of each pattern are definable, such as based on a symbol (10-bit) as the interval pattern, based on a 64-bit block as the interval pattern, or based on a codeword (2720 / 5280 / 5440-bit) as the boundary. Figure 8 shows B0 and B1, where B0 is separated by multiple B1s. The number of stop-flow code blocks can be multiple to ensure that RX can receive it. The specific setting is not specifically limited in this application. The PCS can transmit the stop-flow code block to the FEC layer through the PCS lane (4 50G PCS lanes are used as an example in Figure 8), the FEC layer transmits it to the PMA through the virtual channel, the PMA transmits the stop-flow code block to the PMD through the PMA lane (2 100G PMA lanes are used as an example in Figure 8), and the PMD transmits the stop-flow code block to the TX SerDes through the physical channel (4 50G PMD lanes are used as an example in Figure 8, and the physical channel is indicated by a solid line). Since the physical channel and the SerDes are one-to-one corresponding, the 4 physical channels correspond to 4 SerDes. The TX SerDes and the RX SerDes transmit the stop-flow code block, and then transmit it to the RX PMD. The RX PMD transmits the stop-flow code block through the PMA lane (2 100G PMA lanes are used as an example in Figure 8). The PMA uses fuzzy matching to identify the received stop-flow code blocks. If the number of received stop-flow code blocks exceeds a predefined stop-flow threshold, the detected code block is determined to be a legitimate stop-flow indication.PMA can convert the stop flow code block into stop flow indication information and transmit it to the FEC layer through PCS lane (4 50G PCS lanes are exemplarily described in Figure 8), and then pass through PCS, and PCS transmits it to the MAC layer through MII. After that, the PCS, PMA, PMD of TX and the PCS, PMA, PMD of RX are switched from the working state to the dormant state, and the SerDes of TX and the SerDes of RX are also switched from the working state to the keep-alive state. In addition, the PMA of TX can generate a pseudo-random code block (i.e., a keep-alive code block, such as a pseudo-random code block, a scrambled IDLE code block) based on the stop flow indication code block, and transmit it between the SerDes of TX and the SerDes of RX to ensure that the SerDes is in a keep-alive state. Once the service is restored, the SerDes can respond promptly to resume the transmission of the service.

[0221] In addition, once the service of the transmitting device is restored, the MAC layer of the TX detects the service message, generates a flow indication information (that is, the first indication information mentioned above), and transmits the flow indication information to the PCS. The flow indication information can be a notification message, etc., which can be understood with reference to the first indication information mentioned above. The flow indication information can be a low-power code stream or a normal power code stream, which is not specifically limited in this application. The PCS generates a flow code block (that is, a first indication code block) according to the flow indication. The flow code block takes a pattern of N*8-bit~64-bit blocks (N is a natural number, N=1~8, etc.) as an example. The pattern can be composed of multiple patterns with intervals (8-bit~64-bit). The size and interval of each pattern are definable, such as based on a symbol (10-bit) as an interval pattern, based on a 64-bit block as an interval pattern, or based on a codeword (2720 / 5280 / 5440-bit) as a boundary. Figure 8 is illustrated with B0 and B1, where B0 is separated by multiple B1s. The number of transmission code blocks can be multiple to ensure that RX can receive it. The specific setting is not specifically limited in this application. PCS can transmit the transmission code block to the FEC layer through the PCS lane, and then transmit it to the PMA. The PMA transmits the transmission code block to the PMD through the PMA lane (6 lanes are exemplarily described in Figure 8). The PMD transmits the transmission code block to the TX SerDes through the physical channel. The TX SerDes and the RX SerDes transmit the stop flow code block, and then transmit the RX PMD. The RX PMD transmits the transmission code block to the PMA through the PMA lane. The PMA uses a fuzzy matching method to identify. If the number of received transmission code blocks exceeds the predefined recovery service flow threshold, it is determined that the detected code block is a legal transmission indication. The PMA can convert the transmission code block into transmission indication information and transmit it to the FEC layer through the PCS lane, and then transmit it to the PCS. The PCS transmits it to the MAC layer through the MII. Afterwards, the PCS and PMA of TX and the PCS and PMA of RX are switched from the sleep state to the working state, the PMD of TX and the PMD of RX are switched from the keep-alive state to the working state, and the SerDes of PMD is also switched from the keep-alive state to the working state.

[0222] When the data processing method of the present application is used, the data recovery time is relatively fast for different scenarios, which can be understood by referring to the following Tables 2 to 4. Table 2 shows the scenario of NO FEC and NRZ (low bit error rate) link, corresponding to the use of a 2*66-bit block size for sending stop and resume flow indications, a sending interval of 0-bit, and the required traffic recovery time. The service traffic recovery time is usually at the nanosecond level, and the user experience is good. For example, the SerDes rate is 10.3125Gbps, the PHY rate is 10G, the working mode (that is, the interface data carrying capacity) is 1*10G, the code blocks for stop and start flow are both 66-bit blocks, the stop and start flow are both 2 times, the number of virtual channels is 1, the data size carried by each virtual channel is 1*66+1*66bit, the stop and start flow interval is 0bit (that is, there is no interval between stop and start flow, which is a "back-to-back" transmission mode), and the time required for service traffic recovery response is 12.8ns.

[0223] Table 2

[0224] Table 3 shows the traffic recovery time required for scenarios with FEC and NRZ (low bit error rate) links, using a 2*64-bit block size for sending stop and resume flow indications with a 0-bit interval. For example, if the SerDes rate is 25.78125 Gbps, the PHY rate is 50 Gbps, the operating mode (i.e., the interface data carrying capacity) is 2*25 Gbps, the block size for stopping and resuming flow is 2*64-bit blocks, flow stopping and resuming flow are both performed twice, there are two virtual channels, each carrying a data size of 1*64+1*64 bits, the stop and resume flow interval is 0 bits, and the service traffic recovery response time is 4.96 ns.

[0225] Table 3

[0226] Table 4 shows the required traffic recovery time for a scenario with FEC and a PAM4 link (low bit error rate). The corresponding block size for sending stop and resume flow indications is (2+2)*64-bit (to ensure reliability), and the sending interval is 2*64-bit (the block and interval sizes can be adjusted based on reliability requirements). For example, if the SerDes rate is 53.125 Gbps, the PHY rate is 200 Gbps, the operating mode (i.e., the interface data carrying capacity) is 8*25 Gbps, the block size for stop and resume flow is 32*64-bit blocks, the stop and resume flow is repeated twice, there are 8 virtual channels, the data size of each virtual channel is 2*64+2*64 bits, the stop and resume flow interval is 2*64 bits (i.e., the transmission time occupied by the 2*64-bit interval between stop and resume flow), the service traffic recovery response time is 14.46 ns.

[0227] Table 4

[0228] It should be noted that, if the solution of this application has traffic services occupying 50% of the average bandwidth, the total PHY logic power consumption can be saved by an estimated 35%. If the traffic services occupying 25% of the average bandwidth, the total PHY logic power consumption can be saved by an estimated 60%. If the traffic services occupying 10% of the average bandwidth, the total PHY logic power consumption can be saved by an estimated 75%.

[0229] The above mainly introduces the solution provided by the embodiment of the present application from the perspective of device interaction. It is understandable that, in order to implement the above functions, each device may include a hardware structure and / or software module that performs each function. Those skilled in the art should easily appreciate that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the embodiments of the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in a hardware or computer software driven hardware manner depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0230] In the embodiments of the present application, the functional units of the device can be divided according to the above method examples. For example, each functional unit can be divided according to each function, or two or more functions can be integrated into one unit. The above integrated unit can be implemented in the form of hardware or software functional units.

[0231] In the case of adopting an integrated unit, FIG9 shows a possible exemplary block diagram of the data processing device involved in the embodiments of the present application. As shown in FIG9 , the data processing device 900 may include: a processing unit 901 and a transceiver unit 902. The processing unit 901 is used to control and manage the actions of the data processing device 900. The transceiver unit 902 is used to support communication between the data processing device 900 and other devices. Optionally, the transceiver unit 902 may include a receiving unit and / or a sending unit, which are used to perform receiving and sending operations respectively. Optionally, the data processing device 900 may also include a storage unit for storing program code and / or data of the data processing device 900. The transceiver unit may be referred to as an input / output unit, a communication unit, etc., and the transceiver unit may be a transceiver; the processing unit may be a processor. When the image processing device is a module (such as a chip) in a communication device, the transceiver unit may be an input / output interface, an input / output circuit, or an input / output pin, etc., and may also be referred to as an interface, a communication interface, or an interface circuit, etc.; the processing unit may be a processor, a processing circuit, or a logic circuit, etc. Specifically, the data processing device may be the aforementioned sending device or receiving device, which is not specifically limited in this application.

[0232] In one embodiment, the data processing device is a sending device, which includes a first MAC layer and a first PHY. The sending device includes a transceiver unit 902 and a processing unit 901, wherein the transceiver unit 902 is used to receive first indication information from the first MAC layer through the first PHY, and the first indication information is used to instruct the sending device to send a service flow to the receiving device; the processing unit 901 is used to obtain a first indication code block according to the first indication information through the first PHY, and the first indication code block is used to instruct the second PHY of the receiving device to switch from a sleep state to a working state, and to instruct the second corresponding to the second PHY to switch from a keep-alive state to a working state; the transceiver unit 902 is also used to send the first indication code block to the receiving device through the first PHY.

[0233] In an optional manner, the processing unit 901 is further configured to switch the first PHY from a sleep state to a working state and switch a first SerDes corresponding to the first PHY from a keep-alive state to a working state according to the first indication information through the first PHY.

[0234] In an optional manner, the first PHY includes a first PCS and a first PMA, wherein the switching of the first PHY from a sleep state to an active state includes the switching of the first PCS from a sleep state to an active state and the switching of the first PMA from a sleep state to an active state.

[0235] In an optional manner, the transceiver unit 902 is also used to receive second indication information from the first MAC layer through the first PHY, and the second indication information is used to instruct the sending device to stop sending the service flow to the receiving device; the processing unit 901 is also used to obtain a second indication code block according to the second indication information through the first PHY, and the second indication code block is used to instruct the second PHY of the receiving device to switch from the working state to the sleep state, and to instruct the second SerDes corresponding to the second PHY to switch from the working state to the keep-alive state; the transceiver unit 902 is also used to send the second indication code block to the receiving device through the first PHY.

[0236] In an optional manner, the processing unit 901 is configured to, through the first PHY, switch the first PHY from a working state to a sleep state and switch a first SerDes corresponding to the first PHY from a working state to a keep-alive state according to the second indication information.

[0237] In an optional manner, the first PHY includes a first PCS and a first PMA, wherein the switching of the first PHY from an active state to a sleep state includes the switching of the first PCS from an active state to a sleep state and the switching of the first PMA from an active state to a sleep state.

[0238] In an optional manner, the processing unit 901 is specifically used to switch the first PCS from a sleep state to a working state according to the first indication information through the first PCS, and obtain a first indication code block; the transceiver unit 902 is specifically used to send the first indication code block to the first PMA through the first PCS; the processing unit 901 is specifically used to switch the first PMA from a sleep state to a working state according to the received first indication code block through the first PMA.

[0239] In an optional manner, the processing unit 901 is specifically used to switch the first PCS from a sleep state to a working state according to the first indication information through the first PCS, and send the first indication information to the first PMA; the processing unit 901 is specifically used to switch the first PMA from a sleep state to a working state according to the received first indication information through the first PMA, and obtain a first indication code block.

[0240] In an optional manner, the processing unit 901 is specifically used to switch the first PCS from a working state to a sleep state according to the second indication information through the first PCS, and obtain a second indication code block; the transceiver unit 902 is specifically used to send the second indication code block to the first PMA through the first PCS; the processing unit 901 is specifically used to switch the first PMA from a working state to a sleep state according to the received second indication code block through the first PMA.

[0241] In an optional manner, the processing unit 901 is specifically used to switch the first PCS from a working state to a sleep state according to the second indication information through the first PCS, and send the second indication information to the first PMA; the processing unit 901 is specifically used to switch the first PMA from a working state to a sleep state according to the received second indication information through the first PMA, and obtain a second indication code block.

[0242] In an optional manner, the first PCS includes multiple first PCS channels, and the processing unit 901 is specifically configured to switch the multiple first PCS channels from a sleep state to a working state through the first PCS; or, the first PCS switches some of the multiple first PCS channels from a sleep state to a working state according to a first service flow rate threshold.

[0243] In an optional manner, the first PCS includes multiple first PCS channels, and the processing unit 901 is specifically configured to switch the multiple first PCS channels from a working state to a dormant state through the first PCS; or, the first PCS switches some of the multiple first PCS channels from a working state to a dormant state according to a second service flow rate threshold.

[0244] In an optional manner, the first PCS includes multiple first PCS channels, and the transceiver unit 902 is specifically configured to send the first indication code block through the first PCS via at least one first PCS channel among the multiple first PCS channels.

[0245] In an optional manner, the first PCS includes multiple first PCS channels, and the transceiver unit 902 is specifically configured to send the second indication code block through the first PCS via at least one first PCS channel among the multiple first PCS channels.

[0246] In an optional manner, the first PHY includes a first PMD, and the processing unit 901 is specifically used to switch the first PMD from a keep-alive state to a working state according to the first indication information through the first PHY; the first PHY switches the first SerDes corresponding to the first PMD from a keep-alive state to a working state.

[0247] In an optional manner, the first PMD includes multiple first PMD channels, and the processing unit 901 is specifically used to switch the multiple first PMD channels from the keep-alive state to the working state through the first PMD; or, the first PMD switches some of the multiple first PMD channels from the keep-alive state to the working state according to the first business flow rate threshold.

[0248] In an optional manner, when the first SerDes is in a keep-alive state, the transceiver unit 902 is further configured to periodically send a keep-alive code block to a receiving device via the first PHY via the first SerDes.

[0249] In an optional manner, the length of the first indicator code block is 10 bits, 64 bits, 66 bits, 128 bits or 130 bits.

[0250] In another embodiment, the data processing device is a receiving device, the receiving device includes a second PHY, and the receiving device includes a transceiver unit 902 and a processing unit 901, wherein the transceiver unit 902 is used to receive a first indication code block sent by the first PHY in the sending device through the second PHY, and the first indication code block is used to instruct the second PHY to switch from a sleep state to a working state, and to instruct the second SerDes corresponding to the second PHY to switch from a keep-alive state to a working state; the processing unit 901 is used to switch the second PHY from a sleep state to a working state and switch the second SerDes corresponding to the second PHY from a keep-alive state to a working state according to the first indication code block through the second PHY.

[0251] In an optional manner, the second PHY includes a second PCS and a second PMA, wherein the second PHY switching from a sleep state to an active state includes the second PCS switching from a sleep state to an active state and the second PMA switching from a sleep state to an active state.

[0252] In an optional manner, the transceiver unit 902 is further used to receive a second indication code block sent by the first PHY in the transmitting device through the second PHY, where the second indication code block is used to indicate that the second PHY switches from a working state to a sleep state, and indicates that the second SerDes corresponding to the second PHY switches from a working state to a keep-alive state; the processing unit 901 is further used to switch the second PHY from a working state to a sleep state and switch the second SerDes corresponding to the second PHY from a working state to a keep-alive state according to the second indication code block through the second PHY.

[0253] In an optional manner, the second PHY includes a second PCS and a second PMA, wherein the switching of the second PHY from an active state to a sleep state includes the switching of the second PCS from an active state to a sleep state and the switching of the second PMA from an active state to a sleep state.

[0254] In an optional manner, the processing unit 901 is specifically used to switch the second PMA from a sleep state to a working state according to the first indication code block through the second PMA; the transceiver unit 902 is specifically used to send the first indication information to the second PCS through the second PMA; the transceiver unit 902 is specifically used to receive the first indication information through the second PCS and switch the second PCS from a sleep state to a working state.

[0255] In an optional manner, the processing unit 901 is specifically used to switch the second PMA from a working state to a sleep state according to a second indication code block through the second PMA; the transceiver unit 902 is specifically used to send second indication information to the second PCS through the second PMA; the transceiver unit 902 is specifically used to receive the second indication information through the second PCS and switch the second PCS from a working state to a sleep state.

[0256] In an optional manner, the second PCS includes multiple second PCS channels, and the processing unit 901 is specifically configured to switch the multiple second PCS channels from a dormant state to a working state through the second PCS; or, the second PCS switches some of the multiple second PCS channels from a dormant state to a working state according to a first service flow rate threshold.

[0257] In an optional manner, the second PCS includes multiple second PCS channels, and the processing unit 901 is specifically configured to switch the multiple second PCS channels from a working state to a dormant state through the second PCS; or, the second PCS switches some of the multiple second PCS channels from a working state to a dormant state according to a second service flow rate threshold.

[0258] In an optional manner, the second PHY includes a second PMD, and the processing unit 901 is specifically used to switch the second PMD from a keep-alive state to a working state according to the first indication code block through the second PHY; the second PHY switches the second SerDes corresponding to the second PMD from a keep-alive state to a working state.

[0259] In an optional manner, the second PMD includes multiple second PMD channels, and the processing unit 901 is specifically used to switch the multiple second PMD channels from the keep-alive state to the working state through the second PMD; or, the second PMD switches some of the multiple second PMD channels from the keep-alive state to the working state according to the first service flow rate threshold.

[0260] In an optional manner, the second PCS includes multiple second PCS channels, and the transceiver unit 902 is specifically configured to receive the second indication information through the second PCS via at least one second PCS channel among the multiple second PCS channels.

[0261] In an optional manner, when the second SerDes is in a keep-alive state, the transceiver unit 902 is specifically configured to periodically receive a keep-alive code block via the second SerDes through the second PHY.

[0262] In an optional manner, the length of the first indicator code block is 10 bits, 64 bits, 66 bits, 128 bits or 130 bits.

[0263] In another embodiment, the data processing device is a sending device, the sending device includes a first MAC layer and a first PHY, and the sending device includes a transceiver unit 902 and a processing unit 901, wherein the transceiver unit 902 is used to receive second indication information from the first MAC layer through the first PHY, and the second indication information is used to instruct the sending device to stop sending the service flow to the receiving device; the processing unit 901 is used to obtain a second indication code block according to the second indication information through the first PHY, and the second indication code block is used to instruct the second PHY of the receiving device to switch from the working state to the sleep state, and to instruct the second SerDes corresponding to the second PHY to switch from the working state to the keep-alive state; the transceiver unit 902 is also used to send the second indication code block to the receiving device through the first PHY.

[0264] In an optional manner, the processing unit 901 is configured to, through the first PHY, switch the first PHY from a working state to a sleep state and switch a first SerDes corresponding to the first PHY from a working state to a keep-alive state according to the second indication information.

[0265] In an optional manner, the first PHY includes a first PCS and a first PMA, and the processing unit 901 is specifically used to switch the first PCS from a working state to a sleep state according to the second indication information through the first PCS, and obtain a second indication code block; the transceiver unit 902 is specifically used to send the second indication code block to the first PMA through the first PCS; the processing unit 901 is specifically used to switch the first PMA from a working state to a sleep state according to the received second indication code block through the first PMA.

[0266] In an optional manner, the processing unit 901 is specifically used to switch the first PCS from a working state to a sleep state according to the second indication information through the first PCS, and send the second indication information to the first PMA; the processing unit 901 is specifically used to switch the first PMA from a working state to a sleep state according to the received second indication information through the first PMA, and obtain a second indication code block.

[0267] In an optional manner, the first PCS includes multiple first PCS channels, and the processing unit 901 is specifically configured to switch the multiple first PCS channels from a working state to a dormant state through the first PCS; or, the first PCS switches some of the multiple first PCS channels from a working state to a dormant state according to a second service flow rate threshold.

[0268] In an optional manner, the first PCS includes multiple first PCS channels, and the transceiver unit 902 is specifically configured to send the second indication code block through the first PCS via at least one first PCS channel among the multiple first PCS channels.

[0269] In an optional manner, when the first SerDes is in a keep-alive state, the transceiver unit 902 is specifically configured to periodically send a keep-alive code block to a receiving device via the first PHY via the first SerDes.

[0270] In an optional manner, the length of the second indicator code block is 10 bits, 64 bits, 66 bits, 128 bits, or 130 bits.

[0271] In another embodiment, the data processing device is a receiving device, the receiving device includes a second PHY, and the receiving device includes a transceiver unit 902 and a processing unit 901, wherein the transceiver unit 902 is used to receive a second indication code block sent by the first PHY in the sending device through the second PHY, and the second indication code block is used to indicate that the second PHY switches from a working state to a sleep state, and indicates that the second SerDes corresponding to the second PHY switches from a working state to a keep-alive state; the processing unit 901 is used to switch the second PHY from a working state to a sleep state and the second SerDes corresponding to the second PHY from a working state to a keep-alive state according to the second indication code block through the second PHY.

[0272] In an optional manner, the second PHY includes a second PCS and a second PMA, wherein the switching of the second PHY from an active state to a sleep state includes the switching of the second PCS from an active state to a sleep state and the switching of the second PMA from an active state to a sleep state.

[0273] In an optional manner, the processing unit 901 is specifically used to switch the second PMA from a working state to a sleep state according to a second indication code block through the second PMA; the transceiver unit 902 is specifically used to send second indication information to the second PCS through the second PMA; the transceiver unit 902 is specifically used to receive the second indication information through the second PCS and switch the second PCS from a working state to a sleep state.

[0274] In an optional manner, the second PCS includes multiple second PCS channels, and the transceiver unit 902 is specifically configured to receive the second indication information through the second PCS via at least one second PCS channel among the multiple second PCS channels.

[0275] In an optional manner, the second PCS includes multiple second PCS channels, and the transceiver unit 902 is specifically configured to switch the multiple second PCS channels from a working state to a dormant state through the second PCS; or, the second PCS switches some of the multiple second PCS channels from a working state to a dormant state according to a second service flow rate threshold.

[0276] In an optional manner, when the second SerDes is in a keep-alive state, the transceiver unit 902 is specifically configured to periodically receive a keep-alive code block via the second SerDes through the second PHY.

[0277] In an optional manner, the length of the second indicator code block is 10 bits, 64 bits, 66 bits, 128 bits or 130 bits.

[0278] The present application provides an integrated circuit (equivalent to a sending device), which includes an interface circuit and a control circuit, and the interface circuit is coupled to the control circuit; the interface circuit is used to receive first indication information from a first MAC layer through a first PHY, and the first indication information is used to instruct the sending device to send a service flow to a receiving device; the control circuit is used to obtain a first indication code block according to the first indication information through the first PHY, and the first indication code block is used to instruct the second PHY of the receiving device to switch from a sleep state to a working state, and to instruct the second serializer / deserializer SerDes corresponding to the second PHY to switch from a keep-alive state to a working state; the interface circuit is also used to send the first indication code block to the receiving device through the first PHY.

[0279] The present application provides another integrated circuit (equivalent to a receiving device), which includes an interface circuit and a control circuit, and the interface circuit is coupled to the control circuit; the interface circuit is used to receive a first indication code block sent by a first PHY in a transmitting device through a second PHY, and the first indication code block is used to instruct the second PHY to switch from a sleep state to a working state, and to instruct the second serializer / deserializer SerDes corresponding to the second PHY to switch from a keep-alive state to a working state; the control circuit is used to switch the second PHY from a sleep state to a working state and the second SerDes corresponding to the second PHY from a keep-alive state to a working state according to the first indication code block through the second PHY.

[0280] Referring to Figure 10 , Figure 10 shows a schematic diagram of the structure of a data processing device 2100 provided in this application. Data processing device 2100 may be the sending device or receiving device described in Figures 3 to 8 above. Device 2100 may be, for example, a switch or router, and may be implemented using a bus architecture.

[0281] As shown in FIG. 10 , the device 2100 includes a main control board 2110 and an interface board 2130 .

[0282] The main control board (2110), also known as the main processing unit (MPU) or route processor card, is used to control and manage the various components in device 2100, including routing calculations, device management, device maintenance, and protocol processing. It includes a central processing unit (CPU) 2111 and memory 2112.

[0283] Interface board 2130 is also known as a line processing unit (LPU), line card, or service board. It provides various service interfaces and implements data packet forwarding. Service interfaces include, but are not limited to, Ethernet interfaces and POS (Packet over SONET / SDH) interfaces. Ethernet interfaces, for example, are Flexible Ethernet Client (FlexE Client) interfaces. Interface board 2130 includes a central processing unit (CPU) 2131, a network processor (NPU) 2132, a forwarding table memory 2134, and a physical interface card (PIC) 2133.

[0284] The central processing unit 2131 on the interface board 2130 is used to control and manage the interface board 2130 and communicate with the central processing unit 2111 on the main control board 2110 .

[0285] The network processor 2132 is used to implement message forwarding processing. The network processor 2132 can be in the form of a forwarding chip. The forwarding chip can be a network processor (NP). In some embodiments, the forwarding chip can be implemented using an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA). Specifically, the network processor 2132 is used to forward received messages based on the forwarding table stored in the forwarding entry memory 2134. If the destination address of the message is the address of the device 2100, the message is sent to the CPU (such as the central processing unit 2131) for processing. If the destination address of the message is not the address of the device 2100, the next hop and outgoing interface corresponding to the destination address are searched in the forwarding table based on the destination address, and the message is forwarded to the outgoing interface corresponding to the destination address. The processing of uplink messages may include processing the message input interface and forwarding table lookup; the processing of downlink messages may include forwarding table lookup, etc. In some embodiments, the central processing unit may also perform the functions of the forwarding chip, such as implementing software forwarding based on a general-purpose CPU, thereby eliminating the need for a forwarding chip in the interface board.

[0286] Physical interface card 2133 implements the physical layer interconnection function. Raw traffic enters interface board 2130 from this card, and processed messages are sent from this physical interface card 2133. Physical interface card 2133, also known as a daughter card, can be installed on interface board 2130. It is responsible for converting optical and electrical signals into messages, performing a validity check on these messages, and forwarding them to network processor 2132 for processing. In some embodiments, central processing unit 2131 can also perform the functions of network processor 2132, such as implementing software forwarding based on a general-purpose CPU, thus eliminating the need for network processor 2132 in physical interface card 2133. This physical interface card 2133 can be used to implement the PHY in the transmitting or receiving device described in this application, and will not be further described here.

[0287] Optionally, the apparatus 2100 includes multiple interface boards. For example, the apparatus 2100 further includes an interface board 2140, which includes a central processing unit 2141, a network processor 2142, a forwarding table entry memory 2144, and a physical interface card 2143. The functions and implementations of the components in the interface board 2140 are the same as or similar to those of the interface board 2130 and are not described in detail herein. The interface board includes one or more interfaces described in the above embodiments.

[0288] Optionally, the device 2100 further includes a switch fabric board 2120. The switch fabric board 2120 may also be referred to as a switch fabric unit (SFU). If the device has multiple interface boards, the switch fabric board 2120 is used to exchange data between the interface boards. For example, the interface board 2130 and the interface board 2140 can communicate via the switch fabric board 2120.

[0289] The main control board 2110 is coupled to the interface board. For example, the main control board 2110, the interface board 2130, the interface board 2140, and the switching network board 2120 are connected to the system backplane via a system bus to achieve intercommunication. In one possible implementation, an inter-process communication (IPC) channel is established between the main control board 2110 and the interface boards 2130 and 2140, and communication is performed between the main control board 2110 and the interface boards 2130 and 2140 via the IPC channel.

[0290] Logically, device 2100 includes a control plane and a forwarding plane. The control plane includes a main control board 2110 and a central processing unit 2111. The forwarding plane includes various components that perform forwarding, such as a forwarding table entry memory 2134, a physical interface card 2133, and a network processor 2132. The control plane performs routing functions, generates forwarding tables, processes signaling and protocol messages, and configures and maintains device status. The control plane sends the generated forwarding tables to the forwarding plane. On the forwarding plane, the network processor 2132 forwards messages received by the physical interface card 2133 based on the forwarding tables sent by the control plane. The forwarding tables sent by the control plane can be stored in the forwarding table entry memory 2134. In some embodiments, the control plane and forwarding plane can be completely separate and not located on the same device.

[0291] It is worth noting that there may be one or more main control boards, which may include a primary main control board and a backup main control board. There may be one or more interface boards, and the more interface boards provided, the stronger the data processing capability of the device. The interface board may also have one or more physical interface cards. There may be no switching network board, one or more switching network boards, and when there are multiple switching network boards, they can jointly achieve load sharing and redundant backup. In a centralized forwarding architecture, the device may not require a switching network board, and the interface board is responsible for processing the service data of the entire system. In a distributed forwarding architecture, the device can have at least one switching network board, which enables data exchange between multiple interface boards, providing high-capacity data exchange and processing capabilities. Therefore, the data access and processing capabilities of devices with a distributed architecture are greater than those of devices with a centralized architecture. Alternatively, the device may consist of a single board, i.e., without a switching fabric board. The functions of the interface board and the main control board are integrated on this single board. In this case, the central processing unit (CPU) on the interface board and the CPU on the main control board can be combined into a single CPU on this single board to perform the combined functions of the two. This type of device has lower data exchange and processing capabilities (e.g., low-end switches or routers). The specific architecture to be used depends on the specific networking deployment scenario and is not limited here.

[0292] It should be understood that the processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor. It is worth noting that the processor may be a processor that supports the Advanced RISC Machine (ARM) architecture.

[0293] Furthermore, in an optional embodiment, the memory may include a read-only memory and a random access memory, and provide instructions and data to the processor. The memory may also include a non-volatile random access memory. For example, the memory may also store device type information.

[0294] The memory may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM), which is used as an external cache memory. By way of example and not limitation, many forms of RAM are available. For example, static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM) and direct rambus RAM (DR RAM).

[0295] Referring to Figure 11 , Figure 11 shows a schematic diagram of the structure of an apparatus 4000 provided in an exemplary embodiment of the present application. The apparatus 4000 shown in Figure 11 is used to perform operations associated with the interface functions shown in any of Figures 3 through 8 . The apparatus 4000 may be, for example, a switch, a router, a controller, or a server, a storage device, or a network device. The apparatus 4000 may be implemented using a bus architecture.

[0296] As shown in Figure 11, apparatus 4000 includes at least one processor 4001 and at least one communication interface 4004. In some embodiments, processor 4001 is coupled to memory 4003. The communication interface 4004 can be used to implement the PHY in the transmitting device or receiving device in this application, which will not be described in detail here.

[0297] The processor 4001 is, for example, a general-purpose central processing unit (CPU), a digital signal processor (DSP), a network processor (NP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits for implementing the solution of the present application. For example, the processor 4001 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or other programmable logic devices, a transistor logic device, a hardware component, or any combination thereof. The PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. It can implement or execute the various logic blocks, modules, and circuits described in conjunction with the disclosure of the embodiments of the present invention. The processor can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and the like.

[0298] Optionally, device 4000 further includes a bus. The bus is used to transmit information between the components of device 4000. The bus may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, for example. Buses can be classified as address buses, data buses, control buses, and the like. For ease of illustration, FIG11 shows only one thick line, but this does not imply that there is only one bus or only one type of bus.

[0299] The memory 4003 is, for example, a read-only memory (ROM) or other type of static storage device that can store static information and instructions, or a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 4003 is, for example, independent and connected to the processor 4001 via a bus. The memory 4003 can also be integrated with the processor 4001.

[0300] The communication interface 4004 uses any transceiver-type device for communicating with other devices or communication networks, and the communication network can be Ethernet, a radio access network (RAN), or a wireless local area network (WLAN). The communication interface 4004 can include a wired communication interface and a wireless communication interface. Specifically, the communication interface 4004 can be an Ethernet interface, a Fast Ethernet (FE) interface, a Gigabit Ethernet (GE) interface, an Asynchronous Transfer Mode (ATM) interface, a wireless local area network (WLAN) interface, a cellular network communication interface, or a combination thereof. The Ethernet interface can be an optical interface, an electrical interface, or a combination thereof. In the embodiment of the present application, the communication interface 4004 can be used for the device 4000 to communicate with other devices.

[0301] In a specific implementation, as an embodiment, the processor 4001 may include one or more CPUs, such as CPU0 and CPU1 shown in FIG11 . Each of these processors may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. The processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0302] In a specific implementation, as an embodiment, apparatus 4000 may include multiple processors, such as processor 4001 and processor 4005 shown in FIG11 . Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). A processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0303] In a specific implementation, as an embodiment, the apparatus 4000 may further include an output device and an input device. The output device communicates with the processor 4001 and may display information in a variety of ways. For example, the output device may be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. The input device communicates with the processor 4001 and may receive user input in a variety of ways. For example, the input device may be a mouse, a keyboard, a touch screen device, or a sensor device.

[0304] In some embodiments, the memory 4003 is used to store program code 4010 for executing the solution of the present application, and the processor 4001 can execute the program code 4010 stored in the memory 4003. That is, the device 4000 can implement the various functions of the interface shown in any of Figures 3-8 through the processor 4001 and the program code 4010 in the memory 4003. The program code 4010 may include one or more software modules. Optionally, the processor 4001 itself can also store program code or instructions for executing the solution of the present application.

[0305] In some embodiments, the communication interface 4004 is used to perform operations related to the interface functions shown in any of the above Figures 3-8.

[0306] Based on the above embodiments, embodiments of the present application further provide a computer-readable storage medium storing instructions that, when executed, implement the method performed by each device in any of the above method embodiments. For example, the method performed by the image encoding device and image decoding device in the embodiment shown in FIG4 is implemented. The computer-readable storage medium may include various media capable of storing program code, such as a USB flash drive, a mobile hard drive, a read-only memory, a random access memory, a magnetic disk, or an optical disk.

[0307] Based on the above embodiments, an embodiment of the present application provides a data processing system, which includes the sending device and receiving device mentioned in any of the above method embodiments, and can be used to execute the method executed by each device in any of the above method embodiments.

[0308] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0309] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0310] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0311] These computer program instructions can also be loaded onto a computer or other programmable image processing device so that a series of operating steps are executed on the computer or other programmable device to produce computer-implemented processing, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

Claims

1. A data processing method, applied to a sending device, wherein the sending device comprises a first media access control MAC layer and a first physical layer PHY, characterized in that: include: The first PHY receives first indication information from the first MAC layer, where the first indication information is used to instruct the sending device to send a service flow to the receiving device; The first PHY obtains a first indication code block according to the first indication information, where the first indication code block is used to instruct the second PHY of the receiving device to switch from a sleep state to a working state, and to instruct a second serializer / deserializer SerDes corresponding to the second PHY to switch from a keep-alive state to a working state; The first PHY sends the first indication code block to the receiving device.

2. The method according to claim 1, characterized in that Also includes: The first PHY switches the first PHY from a sleep state to a working state and switches a first SerDes corresponding to the first PHY from a keep-alive state to a working state according to the first indication information.

3. The method according to claim 2, characterized in that The first PHY includes a first physical coding sublayer PCS and a first physical medium attachment PMA, wherein the switching of the first PHY from a sleep state to an operating state includes the switching of the first PCS from a sleep state to an operating state and the switching of the first PMA from a sleep state to an operating state.

4. The method according to any one of claims 1 to 3, characterized in that: Also includes: The first PHY receives second indication information from the first MAC layer, where the second indication information is used to instruct the sending device to stop sending the service flow to the receiving device; The first PHY obtains a second indication code block according to the second indication information, where the second indication code block is used to instruct the second PHY of the receiving device to switch from a working state to a sleep state, and to instruct the second SerDes corresponding to the second PHY to switch from a working state to a keep-alive state; The first PHY sends the second indication code block to the receiving device.

5. The method according to claim 4, characterized in that Also includes: The first PHY switches the first PHY from a working state to a sleep state and switches the first SerDes corresponding to the first PHY from a working state to a keep-alive state according to the second indication information.

6. The method according to claim 5, characterized in that The first PHY includes a first PCS and a first PMA, wherein the switching of the first PHY from a working state to a sleeping state includes the switching of the first PCS from a working state to a sleeping state and the switching of the first PMA from a working state to a sleeping state.

7. The method according to claim 3, characterized in that The first PHY obtains a first indication code block according to the first indication information, including: The first PCS switches the first PCS from a sleep state to a working state according to the first indication information, and obtains the first indication code block; The first PCS sends the first indication code block to the first PMA; The first PMA switches the first PMA from a sleep state to a working state according to the received first indication code block.

8. The method according to claim 3, characterized in that The first PHY obtains a first indication code block according to the first indication information, including: The first PCS switches the first PCS from a sleep state to a working state according to the first indication information, and sends the first indication information to the first PMA; The first PMA switches the first PMA from a sleep state to a working state according to the received first indication information, and obtains the first indication code block.

9. The method according to claim 6, characterized in that The first PHY obtains a second indication code block according to the second indication information, including: The first PCS switches the first PCS from a working state to a dormant state according to the second indication information, and obtains the second indication code block; The first PCS sends the second indication code block to the first PMA; The first PMA switches the first PMA from a working state to a sleeping state according to the received second indication code block.

10. The method according to claim 6, characterized in that The first PHY obtains a second indication code block according to the second indication information, including: The first PCS switches the first PCS from a working state to a dormant state according to the second indication information, and sends the second indication information to the first PMA; The first PMA switches the first PMA from a working state to a sleeping state according to the received second indication information, and obtains the second indication code block.

11. The method according to claim 7 or 8, characterized in that: The first PCS includes a plurality of first PCS channels, wherein the first PCS switches the first PCS from a sleep state to a working state according to the first indication information, including: The first PCS switches the plurality of first PCS channels from a sleep state to a working state; or, The first PCS switches some of the first PCS channels among the plurality of first PCS channels from a sleep state to a working state according to a first service flow rate threshold.

12. The method according to claim 9 or 10, characterized in that: The first PCS includes a plurality of first PCS channels, wherein the first PCS switches the first PCS from a working state to a dormant state according to the second indication information, including: The first PCS switches the plurality of first PCS channels from a working state to a dormant state; or, The first PCS switches part of the plurality of first PCS channels from a working state to a dormant state according to a second service flow rate threshold.

13. The method according to claim 7, characterized in that The first PCS includes a plurality of first PCS channels, and the first PCS sends the first indication code block to the first PMA, including: The first PCS sends the first indication code block via at least one first PCS channel among the plurality of first PCS channels.

14. The method according to claim 9, characterized in that The first PCS includes a plurality of first PCS channels, and the first PCS sends the second indication code block to the first PMA, including: The first PCS sends the second indication code block via at least one first PCS channel among the plurality of first PCS channels.

15. The method according to any one of claims 2 to 14, characterized in that: The first PHY includes a first physical medium dependent PMD, and the first PHY switches the first PHY from a sleep state to a working state and switches a first SerDes corresponding to the first PHY from a keep-alive state to a working state according to the first indication information, including: The first PHY switches the first PMD from a keep-alive state to a working state according to the first indication information; The first PHY switches the first SerDes corresponding to the first PMD from a keep-alive state to a working state.

16. The method according to claim 15, characterized in that The first PMD includes a plurality of first PMD channels, and the first PHY switches the first PMD from a keep-alive state to a working state according to the first indication information, including: The first PMD switches the plurality of first PMD channels from a keep-alive state to a working state; or, The first PMD switches some of the first PMD channels among the multiple first PMD channels from a keep-alive state to a working state according to a first service flow rate threshold.

17. The method according to claim 2 or 5, characterized in that: When the first SerDes is in a keep-alive state, the method further includes: The first PHY periodically sends a keep-alive code block to the receiving device via the first SerDes.

18. The method according to any one of claims 1 to 17, characterized in that: The length of the first indication code block is 10 bits, 64 bits, 66 bits, 128 bits or 130 bits.

19. A data processing method, applied to a receiving device, wherein the receiving device comprises a second physical layer PHY, characterized in that: include: The second PHY receives a first indication code block sent by the first PHY in the transmitting device, where the first indication code block is used to instruct the second PHY to switch from a sleep state to a working state, and to instruct a second serializer / deserializer SerDes corresponding to the second PHY to switch from a keep-alive state to a working state; The second PHY switches the second PHY from a sleep state to a working state and switches the second SerDes corresponding to the second PHY from a keep-alive state to a working state according to the first indication code block.

20. The method according to claim 19, characterized in that The second PHY includes a second physical coding sublayer PCS and a second physical medium attachment PMA, wherein the switching of the second PHY from a sleep state to an operating state includes the switching of the second PCS from a sleep state to an operating state and the switching of the second PMA from a sleep state to an operating state.

21. The method according to claim 19 or 20, characterized in that Also includes: The second PHY receives a second indication code block sent by the first PHY in the transmitting device, where the second indication code block is used to indicate that the second PHY switches from a working state to a dormant state, and indicates that the second SerDes corresponding to the second PHY switches from a working state to a dormant state. The operation state is switched to keep-alive state; The second PHY switches the second PHY from a working state to a sleep state and switches the second SerDes corresponding to the second PHY from a working state to a keep-alive state according to the second indication code block.

22. The method according to claim 21, characterized in that The second PHY includes a second PCS and a second PMA, wherein the switching of the second PHY from an operating state to a sleep state includes the switching of the second PCS from an operating state to a sleep state and the switching of the second PMA from an operating state to a sleep state.

23. The method according to claim 20, characterized in that The second PHY switches the second PHY from a sleep state to a working state according to the first indication code block, including: The second PMA switches the second PMA from a sleep state to a working state according to the first indication code block; The second PMA sends first indication information to the second PCS; The second PCS receives the first indication information, and switches the second PCS from a sleep state to a working state.

24. The method according to claim 22, characterized in that The second PHY switches the second PHY from a working state to a sleep state according to the second indication code block, including: The second PMA switches the second PMA from a working state to a dormant state according to the second indication code block; The second PMA sends second indication information to the second PCS; The second PCS receives the second indication information, and switches the second PCS from a working state to a sleeping state.

25. The method according to claim 22, characterized in that The second PCS includes a plurality of second PCS channels, wherein the second PCS receives the first indication information and switches the second PCS from a sleep state to a working state, including: The second PCS switches the plurality of second PCS channels from a dormant state to a working state; or, The second PCS switches part of the plurality of second PCS channels from a dormant state to a working state according to a first service flow rate threshold.

26. The method according to any one of claims 19 to 25, characterized in that: The second PHY includes a second physical medium dependent PMD, and the second PHY switches the second SerDes corresponding to the second PHY from a keep-alive state to a working state according to the first indication code block, including: The second PHY switches the second PMD from a keep-alive state to a working state according to the first indication code block; The second PHY switches the second SerDes corresponding to the second PMD from a keep-alive state to a working state.

27. The method according to claim 26, characterized in that The second PMD includes a plurality of second PMD channels, and the second PHY switches the second PMD from a keep-alive state to a working state according to the first indication code block, including: The second PMD switches the plurality of second PMD channels from a keep-alive state to a working state; or, The second PMD switches some of the second PMD channels among the multiple second PMD channels from a keep-alive state to a working state according to the first service flow rate threshold.

28. The method according to claim 24, characterized in that The second PCS includes a plurality of second PCS channels, and the second PCS receives the second indication information, including: The second PCS receives the second indication information via at least one second PCS channel among the plurality of second PCS channels.

29. The method according to claim 19 or 21, characterized in that When the second SerDes is in a keep-alive state, the method further includes: The second PHY periodically receives a keep-alive code block via the second SerDes.

30. The method according to any one of claims 19 to 29, characterized in that: The length of the first indication code block is 10 bits, 64 bits, 66 bits, 128 bits or 130 bits.

31. A sending device, comprising a first media access control MAC layer and a first physical layer PHY, characterized in that: include: a transceiver unit, configured to receive first indication information from a first MAC layer through the first PHY, where the first indication information is used to instruct the sending device to send a service flow to the receiving device; a processing unit, configured to obtain a first indication code block through the first PHY according to the first indication information, wherein the first indication code block is used to instruct the second PHY of the receiving device to switch from a sleep state to a working state, and to instruct a second serializer / deserializer SerDes corresponding to the second PHY to switch from a keep-alive state to a working state; The transceiver unit is further configured to send the first indication code block to the receiving device through the first PHY.

32. The device according to claim 31, characterized in that The processing unit is further configured to switch the first PHY from a sleep state to a working state and switch a first SerDes corresponding to the first PHY from a keep-alive state to a working state according to the first indication information through the first PHY.

33. The device according to claim 32, characterized in that The first PHY includes a first physical coding sublayer PCS and a first physical medium attachment PMA, wherein the switching of the first PHY from a sleep state to an operating state includes the switching of the first PCS from a sleep state to an operating state and the switching of the first PMA from a sleep state to an operating state.

34. The device according to any one of claims 31 to 33, characterized in that The transceiver unit is further used to receive second indication information from the first MAC layer through the first PHY, where the second indication information is used to instruct the sending device to stop sending the service flow to the receiving device; The processing unit is further used to obtain a second indication code block through the first PHY according to the second indication information, where the second indication code block is used to instruct the second PHY of the receiving device to switch from a working state to a sleep state, and to instruct the second SerDes corresponding to the second PHY to switch from a working state to a keep-alive state; The transceiver unit is further configured to send the second indication code block to the receiving device through the first PHY.

35. The device according to claim 34, characterized in that Also includes: The transceiver unit is further configured to switch the first PHY from a working state to a sleep state and switch the first SerDes corresponding to the first PHY from a working state to a keep-alive state according to the second indication information through the first PHY.

36. The device according to claim 35, characterized in that The first PHY includes a first PCS and a first PMA, wherein the switching of the first PHY from a working state to a sleeping state includes the switching of the first PCS from a working state to a sleeping state and the switching of the first PMA from a working state to a sleeping state.

37. The device according to claim 33, characterized in that The processing unit is specifically configured to switch the first PCS from a sleep state to a working state according to the first indication information through the first PCS, and obtain the first indication code block; The transceiver unit is specifically configured to send the first indication code block to the first PMA through the first PCS; The processing unit is specifically configured to switch the first PMA from a sleep state to a working state according to the received first indication code block through the first PMA.

38. The device according to claim 33, characterized in that The processing unit is specifically configured to switch the first PCS from a sleep state to a working state according to the first indication information through the first PCS, and send the first indication information to the first PMA; The processing unit is specifically configured to switch the first PMA from a sleep state to a working state according to the received first indication information through the first PMA, and obtain the first indication code block.

39. The device according to claim 36, characterized in that The processing unit is specifically configured to switch the first PCS from a working state to a dormant state according to the second indication information through the first PCS, and obtain the second indication code block; The transceiver unit is specifically configured to send the second indication code block to the first PMA through the first PCS; The processing unit is specifically configured to switch the first PMA from a working state to a sleeping state according to the received second indication code block through the first PMA.

40. The apparatus according to claim 36, characterized in that The processing unit is specifically configured to switch the first PCS from a working state to a dormant state according to the second indication information through the first PCS, and send the second indication information to the first PMA; The processing unit is specifically configured to switch the first PMA from a working state to a sleeping state according to the received second indication information through the first PMA, and obtain the second indication code block.

41. The apparatus according to claim 37 or 38, characterized in that The first PCS includes a plurality of first PCS channels, wherein the processing unit is specifically configured to switch the plurality of first PCS channels from a sleep state to a working state through the first PCS; or, The first PCS switches some of the first PCS channels among the plurality of first PCS channels from a sleep state to a working state according to a first service flow rate threshold.

42. The apparatus according to claim 39 or 40, characterized in that The first PCS includes a plurality of first PCS channels, and the processing unit is specifically configured to switch the plurality of first PCS channels from a working state to a dormant state through the first PCS; or, The first PCS switches part of the plurality of first PCS channels from a working state to a dormant state according to a second service flow rate threshold.

43. A receiving device, comprising a second physical layer PHY, characterized in that: include: a transceiver unit, configured to receive, through the second PHY, a first indication code block sent by the first PHY in the transmitting device, wherein the first indication code block is used to instruct the second PHY to switch from a sleep state to a working state, and to instruct a second serializer / deserializer SerDes corresponding to the second PHY to switch from a keep-alive state to a working state; A processing unit is used to switch the second PHY from a sleep state to a working state and switch the second SerDes corresponding to the second PHY from a keep-alive state to a working state according to the first indication code block through the second PHY.

44. The device according to claim 43, characterized in that The second PHY includes a second physical coding sublayer PCS and a second physical medium attachment PMA, wherein the switching of the second PHY from a sleep state to an operating state includes the switching of the second PCS from a sleep state to an operating state and the switching of the second PMA from a sleep state to an operating state.

45. Apparatus according to claim 43 or 44, characterised in that The transceiver unit is further used to receive, through the second PHY, a second indication code block sent by the first PHY in the sending device, wherein the second indication code block is used to indicate that the second PHY is switched from a working state to a sleep state, and indicates that the second SerDes corresponding to the second PHY is switched from a working state to a keep-alive state; The processing unit is further configured to switch the second PHY from a working state to a sleep state and switch the second SerDes corresponding to the second PHY from a working state to a keep-alive state according to the second indication code block through the second PHY.

46. ​​The device according to claim 45, characterized in that The second PHY includes a second PCS and a second PMA, wherein the switching of the second PHY from an operating state to a sleep state includes the switching of the second PCS from an operating state to a sleep state and the switching of the second PMA from an operating state to a sleep state.

47. The apparatus according to claim 44, characterized in that The processing unit is specifically configured to switch the second PMA from a sleep state to a working state according to the first indication code block through the second PMA; The transceiver unit is specifically configured to send first indication information to the second PCS through the second PMA; The transceiver unit is specifically configured to receive the first indication information through the second PCS, and switch the second PCS from a sleep state to a working state.

48. The apparatus according to claim 46, characterized in that The processing unit is specifically configured to switch the second PMA from a working state to a dormant state according to the second indication code block through the second PMA; The transceiver unit is specifically configured to send second indication information to the second PCS through the second PMA; The transceiver unit is specifically configured to receive the second indication information through the second PCS, and switch the second PCS from a working state to a dormant state.

49. The device according to claim 46, characterized in that The second PCS includes a plurality of second PCS channels, and the processing unit is specifically configured to switch the plurality of second PCS channels from a sleep state to a working state through the second PCS; or, The second PCS switches part of the plurality of second PCS channels from a dormant state to a working state according to a first service flow rate threshold.

50. The device according to any one of claims 43 to 49, characterized in that The second PHY includes a second physical medium dependent PMD, and the processing unit is specifically configured to switch the second PMD from a keep-alive state to a working state according to the first indication code block through the second PHY; The second PHY switches the second SerDes corresponding to the second PMD from a keep-alive state to a working state.

51. A chip, characterized in that: The chip comprises a processor, and the processor is used to execute the method according to any one of claims 1-18 or to execute the method according to any one of claims 19-30.

52. An integrated circuit, characterized in that: The integrated circuit comprises an interface circuit and a control circuit, wherein the interface circuit is coupled to the control circuit; The interface circuit is used to receive first indication information from the first MAC layer through the first PHY, where the first indication information is used to instruct the sending device to send a service flow to the receiving device; The control circuit is used to obtain a first indication code block according to the first indication information through the first PHY, where the first indication code block is used to instruct the second PHY of the receiving device to switch from a sleep state to a working state, and to instruct the second serializer / deserializer SerDes corresponding to the second PHY to switch from a keep-alive state to a working state; The interface circuit is further configured to send the first indication code block to the receiving device through the first PHY.

53. An integrated circuit, characterized in that: The integrated circuit comprises an interface circuit and a control circuit, wherein the interface circuit is coupled to the control circuit; The interface circuit is used to receive, through the second PHY, a first indication code block sent by the first PHY in the sending device, The first indication code block is used to instruct the second PHY to switch from a sleep state to a working state, and to instruct a second serializer / deserializer SerDes corresponding to the second PHY to switch from a keep-alive state to a working state; The control circuit is used to switch the second PHY from a sleep state to a working state and switch the second SerDes corresponding to the second PHY from a keep-alive state to a working state according to the first indication code block through the second PHY.

Images