Display device

Abstract

A display device (10) includes: a first control line (L1) connected to each of K pixel circuits (P1 to P3); a second control line (L2) connected to each of M pixel circuits (P4 to P6); and a first junction line (J1), which is disposed in a higher layer than the first control line (L1) and the second control line (L2) such that at least one of the two ends is located in a display area, and which electrically connects with the first control line (L1) and the second control line (L2).

Description

display device

[0001] The present disclosure relates to a display device.

[0002] Japanese Patent Application Laid-Open No. 2004-122222 discloses a display device in which gate lines are formed to extend to the outer periphery of a light-emitting region.

[0003] Japanese Patent Publication No. 2005-258423

[0004] When forming control lines and a plurality of pixel circuits connected to the control lines, static charges accumulated on the long control lines can damage elements in the pixel circuits.

[0005] The display device according to the present disclosure includes a first set consisting of K pixel circuits arranged in a first direction, where K and M are each integers of 2 or greater, and a second set consisting of M pixel circuits arranged in the first direction, and is a display area in which the first set and the second set are adjacent in the first direction, and a non-display area, and includes a first control line connected to each of the K pixel circuits, a second control line connected to each of the M pixel circuits, and a first relay line, at least one of both ends of which is located in the display area and electrically connected to the first control line and the second control line.

[0006] According to the present disclosure, the manufacturing yield of display devices can be improved.

[0007] FIG. 1 is a cross-sectional view showing an example of the configuration of a display device according to the present embodiment. FIG. 2 is a circuit diagram showing an example of the configuration of a pixel circuit according to the present embodiment. FIG. 3 is a schematic diagram showing an example of the configuration of a display device according to the present embodiment. FIG. 4 is a plan view showing an example of the configuration of a display device according to the present embodiment. FIG. 5 is a cross-sectional view showing an example of the configuration of a display device according to the present embodiment. FIG. 6 is a circuit diagram showing an example of the configuration of a display device according to the present embodiment. FIG. 7 is a circuit diagram showing an example of the configuration of a display device according to the present embodiment. FIG. 8 is a plan view showing an example of the configuration of a display device according to the present embodiment. FIG. 9 is a cross-sectional view showing an example of the configuration of a display device according to the present embodiment. FIG. 10 is a plan view showing an example of the configuration of a display device according to the present embodiment. FIG. 11 is a cross-sectional view showing an example of the configuration of a display device according to the present embodiment. FIG. 12 is a schematic diagram showing an example of the configuration of a display device according to the present embodiment. FIG. 13 is a schematic diagram showing an example of the configuration of a display device according to the present embodiment. FIG. 14 is a schematic diagram showing an example of the configuration of a display device according to the present embodiment. FIG. 15 is a schematic diagram showing an example of the configuration of a display device according to the present embodiment. FIG. 16 is a schematic diagram showing an example of the configuration of a display device according to the present embodiment. FIG. 1 is a schematic diagram showing a configuration example of a display device according to the present embodiment. FIG. 1 is a schematic diagram showing a configuration example of a display device according to the present embodiment. FIG. 2 is a schematic diagram showing a configuration example of a display device according to the present embodiment. FIG. 3 is a schematic diagram showing a configuration example of a display device according to the present embodiment. FIG. 4 is a schematic diagram showing a configuration example of a display device according to the present embodiment. FIG. 5 is a schematic diagram showing a configuration example of a display device according to the present embodiment. FIG. 6 is a schematic diagram showing a configuration example of a display device according to the present embodiment. FIG. 7 is a schematic diagram showing a configuration example of a display device according to the present embodiment. FIG. 8 is a schematic diagram showing a configuration example of a display device according to the present embodiment. FIG. 9 is a schematic diagram showing a configuration example of a display device according to the present embodiment.Fig. 1 is a schematic diagram showing a configuration example of a display device according to the present embodiment; Fig. 2 is a schematic diagram showing a configuration example of a display device according to the present embodiment; Fig. 3 is a schematic diagram showing a configuration example of a display device according to the present embodiment; Fig. 4 is a schematic diagram showing an arrangement of sub-pixels of a display device; Fig. 5 is a schematic diagram showing an arrangement of sub-pixels of a display device.

[0008] FIG. 1 is a cross-sectional view showing an example of the configuration of a display device according to this embodiment. FIG. 2 is a circuit diagram showing an example of the configuration of a pixel circuit according to this embodiment. As shown in FIGS. 1 and 2 , a display device 10 includes a substrate 2, a pixel circuit layer 3, and a light-emitting element layer 5. A glass substrate, a resin substrate, or the like can be used as the substrate 2. The substrate 2 may be flexible. The pixel circuit layer (TFT layer) 3 includes a plurality of pixel circuits P. The light-emitting element layer 5 includes a plurality of light-emitting elements ED. The light-emitting elements ED may include an organic light-emitting layer or a quantum dot light-emitting layer.

[0009] The pixel circuit P in FIG. 2 includes transistors T1 to T7 and a capacitance element C1. The source of transistor T4 (drive transistor) is connected to a high-potential power line PL (ELVDD) via transistor T5 (power supply connecting transistor) and to a data signal line DL via transistor T3 (write transistor). The drain of transistor T4 is connected to the anode of light-emitting element ED via transistor T6 (light-emission control transistor) and to the gate of transistor T4 via transistor T2 (threshold compensation transistor). The gate of transistor T4 is connected to the power line PL via capacitance element C1 and to an initialization power line Vi via transistor T1 (initialization transistor). The drain of transistor T6 is connected to the power line Vi via transistor T7 (reset transistor).

[0010] The gate of transistor T1 is connected to the scanning signal line Gn-1 of the previous stage, the gates of transistors T2, T3, and T7 are connected to the scanning signal line Gn of the current stage, and the gates of transistors T5 and T6 are connected to the light-emission control line En of the current stage. For example, P-channel LTPS transistors can be used as transistors T1 to T7 in FIG. 2 , but this is not limiting. P-channel LTPS transistors may be used as transistors T3 to T6, and N-channel oxide semiconductor transistors may be used as transistors T1, T2, and T7. Hereinafter, the scanning signal lines and light-emission control lines may be collectively referred to as "control lines."

[0011] FIG. 3 is a schematic diagram showing an example of the configuration of a display device according to this embodiment. FIG. 4 is a plan view showing an example of the configuration of a display device according to this embodiment. FIG. 5 is a cross-sectional view showing an example of the configuration of a display device according to this embodiment. The display device 10 includes a first set F1 consisting of K pixel circuits P1 to P3 arranged in a first direction X1, and a second set F2 consisting of M pixel circuits P4 to P6 arranged in the first direction X1, where K and M are integers greater than or equal to 2. The display device 10 also includes a display area DA in which the first set F1 and the second set F2 are adjacent to each other in the first direction X1, and a non-display area NA located outside the display area DA (e.g., around the display area DA). In FIGS. 3 and 4, K=3 and M=3 as an example.

[0012] The display device 10 includes a first control line L1 connected to each of K pixel circuits P1 to P3, a second control line L2 connected to each of M pixel circuits P4 to P6, and a first relay line J1, at least one of whose ends is located in the display area DA and electrically connected to the first control line L1 and the second control line L2.

[0013] 4, the first relay line J1 may overlap the first control line L1 and the second control line L2 in a plan view. As shown in Fig. 5, the first relay line J1 may be located in a layer above the first control line L1 and the second control line L2.

[0014] In the display device 10, the first control line L1 and the second control line L2 are formed separately, which reduces the risk of damage to the functional transistors connected to the first control line L1 and the second control line L1 due to static electricity during the formation of the display device 10.

[0015] The pixel circuit layer 3 may include, in this order, a semiconductor layer SC, a gate insulating film 15, a metal layer GM, an inorganic insulating film 16, a metal layer SE, an organic insulating film 17 (e.g., a polyimide film), a metal layer MF, and an organic insulating film 18 (planarization film). The first control line L1 and the second control line L2 may be included in the metal layer GM, the first relay line J1 may be included in the metal layer SE, and the (vertical) wiring YL may be included in the metal layer MF. The organic insulating film 17 may be located between the first relay line J1 and the wiring YL. The channel of the functional transistor TF of each of the pixel circuits P1 to P3 may be formed in a portion of the semiconductor layer SC where the first control line L1 overlaps with the functional transistor TF, and the channel of the functional transistor TF of each of the pixel circuits P4 to P6 may be formed in a portion of the semiconductor layer SC where the second control line L2 overlaps with the functional transistor TF. Separating the first control line L1 and the second control line L2 reduces the risk of the functional transistor TF being damaged by static electricity.

[0016] The first control line L1 and the first relay line J1 may be connected by one or more contact holes (H2 and H3), and the second control line L2 and the first relay line J1 may be connected by one or more contact holes (H4). The first control line L1 and the first relay line J1 may be connected by multiple contact holes (H2 and H3). Such a redundant design reduces disconnection due to contact failure and improves yield.

[0017] Each of the two or more pixel circuits (P2 and P3) in the first set F1 may include one contact hole (H2 / H3) that connects the first control line L1 and the first relay line J1, thereby achieving a redundant design while maintaining the layout area of ​​each pixel circuit.

[0018] The number of contact holes (two) connecting the first control line L1 and the first relay line J1 may be different from the number of contact holes (one) connecting the second control line L2 and the first relay line J1. Both ends of the first relay line J1 may be located in the display area DA. The material of the first relay line J1 may have a lower electrical resistance than the materials of the first control line L1 and the second control line L2. This reduces distortion of the control signal due to the first relay line J1.

[0019] 3 and 4, the non-display area NA may include a first driver D1, and a control signal from the first driver D1 may be transmitted to a second control line L2 via a first relay line J1. The non-display area NA may include a second driver D2, and a control signal from the second driver D2 may be transmitted to the first control line L1 via the first relay line J1.

[0020] 3 and 4, the display device 10 includes a first connection wiring W1 connected to the first driver D1 and spanning an edge of the display area DA, the first connection wiring W1 being located in the same layer as the first relay line J1 and electrically connected to the first control line L1. The display device 10 includes a second connection wiring W2 connected to the second driver D2 and spanning an edge of the display area DA, the second connection wiring W2 being located in the same layer as the first relay line J1 and electrically connected to the second control line L2.

[0021] 6 and 7 are circuit diagrams showing examples of the configuration of a display device according to this embodiment. As shown in FIGS. 3 to 7, a first control line L1 and a second control line L2 are arranged in a first direction X1. The first control line L1 is electrically connected to the gate terminals of the plurality of functional transistors TF included in a first set F1, and the second control line L2 is connected to the gate terminals of the plurality of functional transistors TF included in a second set F2. One conduction terminal of each functional transistor TF is connected to a wiring YL.

[0022] 6 , the wiring YL may be the data signal line DL, the first control line L1 (Gn1) and the second control line L2 (Gn2) may function as scanning signal lines, and each of the multiple functional transistors TF may be a write transistor T3 (T3 is a switching transistor connected to the data signal line DL). The data signal line DL may extend in a second direction X2 perpendicular to the first direction X1. An organic insulating film 17 may be located between the first relay line J1 and the multiple data signal lines DL (YL) ( FIGS. 4 and 5 ).

[0023] 7, the wiring YL may be the power supply line PL, the first control line L1 (En1) and the second control line L2 (En2) may function as light-emitting control lines, and each of the multiple functional transistors TF may be a power supply connecting transistor T5 (T5 is a switching transistor connected to the power supply line PL). The power supply line PL may extend in the second direction X2. An organic insulating film 17 may be located between the first relay line J1 and the multiple power supply lines PL (YL) (FIGS. 4 and 5).

[0024] 3 to 5 , in the display area DA, a third set F3 consisting of N pixel circuits (P7 to P9) arranged in the first direction X1, where N is an integer greater than or equal to 2, may be adjacent to the second set F2 in the first direction X1. The display device 10 may include a third control line L3 connected to each of the N pixel circuits (P7 to P9), and a second relay line J2, at least one of both ends of which is located in the display area DA and electrically connected to the second control line L2 and the third control line L3. The second relay line J2 may overlap the second control line L2 and the third control line L3 in a plan view, and the first relay line J1 and the second relay line J2 may extend in the first direction X1 and be arranged side by side in the first direction X1.

[0025] In the display device 10 shown in FIGS. 3 to 5, the first relay line J1 and the second relay line J2 are formed separately, which reduces the risk of the functional transistor TF being damaged by static electricity during the formation of the pixel circuit layer 3.

[0026] The second set F2 includes M contact holes (H4 to H6) provided corresponding to the M pixel circuits (P4 to P6), respectively, and the M contact holes (H4 to H6) may include a contact hole (H4) connecting the second control line L2 and the first relay line J1, and contact holes (H5 and H6) connecting the second control line L2 and the second relay line J2. The number of contact holes connecting the second control line L2 and the first relay line J1 may be different from the number of contact holes connecting the second control line L2 and the second relay line J2.

[0027] The display device 10 may include K light-emitting elements Q1 to Q3 provided corresponding to K pixel circuits (P1 to P3), M light-emitting elements Q4 to Q6 provided corresponding to M pixel circuits (P4 to P6), and N light-emitting elements Q7 to Q9 provided corresponding to N pixel circuits (P7 to P9). The pixel circuits P1 to P9 may be collectively referred to as pixel circuit P, and the light-emitting elements Q1 to Q9 may be collectively referred to as light-emitting element Q. A pixel circuit P and a light-emitting element Q connected thereto may constitute a sub-pixel SP (FIGS. 41 and 42).

[0028] K, M, and N may be the same multiple of three, and the K light-emitting elements (Q1 to Q3) may include red light-emitting elements (R), green light-emitting elements (G), and blue light-emitting elements (B) in a ratio of 1:1:1. K=M=N=3 may be used. As an example, Q1 may be a blue light-emitting element B, Q2 may be a red light-emitting element R, and Q3 may be a green light-emitting element G, and one pixel is formed by the three light-emitting elements R, G, and B, Q1 to Q3. This arrangement corresponds to the RGB real arrangement described below (Figure 41). Furthermore, the number of pixel circuits K, M, and N connected to one control wiring may be K=M=N=6 or K=M=N=9 (Figures 30 to 37, etc.).

[0029] FIG. 8 is a schematic diagram showing an example of the configuration of a display device according to this embodiment. FIG. 9 is a plan view showing an example of the configuration of a display device according to this embodiment. FIG. 10 is a cross-sectional view showing an example of the configuration of a display device according to this embodiment. As shown in FIGS. 8 to 10 , one pixel circuit P4 of the second set F2 may include two contact holes (H4 and Ha) connecting the second control line L2 and the first relay line J1. In addition to M contact holes (H4 to H6), the second set F2 may also include a redundant contact hole Ha located in at least one pixel circuit (P4) of the second set F2, and the redundant contact hole Ha may be connected to the second control line L2 and the first relay line J1. This redundant design ensures that the electrical connection between the first control line L1 and the second control line L1 and the first relay line J1 is maintained even if one of the contact holes becomes defective. The pixel circuit P4 in which the redundant contact hole Ha is located may correspond to a blue light-emitting element Q4 (for example, when the blue light-emitting area is smaller than the red and green light-emitting areas).

[0030] FIG. 11 is a schematic diagram showing a configuration example of a display device according to this embodiment. FIG. 12 is a plan view showing a configuration example of a display device according to this embodiment. FIG. 13 is a cross-sectional view showing a configuration example of a display device according to this embodiment. As shown in FIGS. 11 to 13 , the first control line L1 and the first relay line J1 may be connected by a plurality of contact holes (H3 and H4), and the second control line L2 and the first relay line J1 may be connected by a plurality of contact holes (H5 and H6). The number of contact holes (two) connecting the first control line L1 and the first relay line J1 may be the same as the number of contact holes (two) connecting the second control line L2 and the first relay line J1. By using such a redundant design, the electrical connection between the first control line L1 and the second control line L2 and the first relay line J1 is maintained even if one of the contact holes becomes defective.

[0031] The second set F2 includes M contact holes (H5 to H8) provided corresponding to the M pixel circuits (P5 to P8), respectively, and the M contact holes (H5 to H8) may include contact holes (H5 and H6) connecting the second control line L2 and the first relay line J1, and contact holes (H7 and H8) connecting the second control line L2 and the second relay line J2. The number of contact holes (2) connecting the second control line L2 and the first relay line J1 may be the same as the number of contact holes (2) connecting the second control line L2 and the second relay line J2.

[0032] The display device 10 may include K light-emitting elements Q1 to Q4 corresponding to K pixel circuits (P1 to P4), M light-emitting elements Q5 to Q8 corresponding to M pixel circuits (P5 to P8), and N light-emitting elements (Q9, etc.) corresponding to N pixel circuits (P9 to P12). K, M, and N are all multiples of four, and, for example, the K light-emitting elements may include red (R), green (G), and blue (B) light-emitting elements in a numerical ratio of 1:2:1. For example, K=M=N=4, and Q1 and Q3 may be green (G) light-emitting elements, Q2 may be red (R), and Q4 may be blue (B). In this case, one pixel may be formed by the green light-emitting element Q1 (G) and the red light-emitting element Q2 (R), and one pixel may be formed by the green light-emitting element Q3 (G) and the blue light-emitting element Q4 (B). This arrangement corresponds to a diamond pentile arrangement (see FIG. 42), which will be described later. Of course, the ratio of the numbers of light-emitting elements included when K=M=N=4 is a multiple is not limited to this, and may be R:G:B=2:1:1 or R:G:B=1:1:2. Furthermore, the numbers K, M, and N of pixel circuits connected to one control wiring may be K=M=N=8 or K=M=N=12 (see FIG. 40).

[0033] 14 to 40 are schematic diagrams showing examples of the configuration of the display device according to this embodiment. In Fig. 14 to 40, the lines drawn downward from the black circles on the relay lines (J1, etc.) or the connection lines (W1, etc.) represent contact holes H.

[0034] The display device 10 shown in Figures 14 to 40 includes a first set F1 consisting of K pixel circuits P arranged in a first direction X1, where K and M are both integers of 2 or greater, and a second set F2 consisting of M pixel circuits P arranged in the first direction X1, and includes a display area DA in which the first set F1 and the second set F2 are adjacent to each other in the first direction X1, and a non-display area NA, and includes a first control line L1 connected to each of the K pixel circuits P, a second control line L2 connected to each of the M pixel circuits P, and a first relay line J1, at least one of whose ends is located in the display area DA and electrically connected to the first control line L1 and the second control line L2.

[0035] As shown in FIG. 14 , two control lines (L1 and L2) and one relay line (J1) may be provided per row. As shown in FIGS. 14 and 15 , the first control line L1 and the first relay line J1 may be connected by a single contact hole. As shown in FIG. 16 , K=M=2, a contact hole H may be provided in each pixel circuit P, and each relay line (e.g., J1) may be connected to two control lines (e.g., the first control line L1 and the second control line L2) by a single contact hole. As shown in FIG. 17 , the first control line L1 and the second control line L2 may be electrically connected to the first driver D1 but not to the second driver D2. One end of the first relay line J1 may be connected to the first driver D1. The contact hole H connected to the first relay line J1 may be located in the gap between adjacent pixel circuits P.

[0036] As shown in FIG. 18 , three or more control lines (e.g., L1 to L3) and one relay line (J1) may be provided per row (subpixel row). As shown in FIG. 19 , the first relay line J1 may be connected to three control lines (L1 to L3), and the second relay line J2 may be connected to two control lines (L3 and L4). As shown in FIGS. 20 to 22 and 23A and 23B , the display device 10 may be provided with a first driver D1 electrically connected to the first relay line J1, but may not be provided with a second driver D2. This is because the first connection line W1, first control line L1, first relay line J1, second control line L2, etc. are connected seamlessly within the display area DA as a single signal line from one end of the display area DA to the other, and the signal output from the first driver D1 is transmitted from one end of the display area DA to the other via the first connection line W1, first control line L1, first relay line J1, second control line L2, etc.

[0037] As shown in Fig. 24, one end of the first control line L1 may be directly connected to the first driver D1. As shown in Figs. 25 to 29, the display device 10 includes an edge control line LF connected to the first driver D1 and spanning an edge of the display area DA, and the edge control line LF may be located in the same layer as the first control line L1 and connected to one or more pixel circuits P. The display device 10 includes an edge control line LS connected to the second driver D2 and spanning an edge of the display area DA, and the edge control line LS may be located in the same layer as the first control line L1 and connected to one or more pixel circuits P.

[0038] As shown in FIGS. 30 to 37, K=M=6 may be set. The first relay line J1 may be connected to the first control line L1 through three contact holes and to the second control line L2 through three contact holes (FIG. 30). The first relay line J1 may be connected to the first control line L1 through four contact holes and to the second control line L2 through two contact holes (FIG. 31). The first relay line J1 may be connected to the first control line L1 through five contact holes and to the second control line L2 through one contact hole (FIG. 32). A redundant contact hole may be added to the configuration of FIG. 32, and the first relay line J1 may be connected to the second control line L2 through two contact holes formed in the same pixel circuit (FIG. 33). The first relay line J1 may be connected to the first control line L1 through one contact hole formed in one pixel circuit P and to the second control line L2 through one contact hole formed in another pixel circuit P (FIG. 34). The first relay line J1 may be connected to the first control line L1 through two contact holes formed in one pixel circuit P, and may be connected to the second control line L2 through two contact holes formed in another pixel circuit P ( FIG. 35 ). The first relay line J1 may be connected to the first control line L1 through two contact holes, and may be connected to the second control line L2 through two contact holes. In this case, the two contact holes connected to the second control line L2 may be provided in adjacent pixel circuits P ( FIG. 36 ), or the two contact holes (H and Ha) connected to the second control line L2 may be provided in one pixel circuit P ( FIG. 37 ).

[0039] As shown in FIG. 38 , K=M=5 may be set. The first relay line J1 may be connected to the first control line L1 through three contact holes and to the second control line L2 through two contact holes. As shown in FIG. 39 , K=M=7 may be set. The first relay line J1 may be connected to the first control line L1 through four contact holes and to the second control line L2 through three contact holes. As shown in FIG. 40 , K=M=8 may be set. The first relay line J1 may be connected to the first control line L1 through four contact holes and to the second control line L2 through four contact holes.

[0040] 41 and 42 are schematic diagrams showing the arrangement of subpixels in a display device. Here, each subpixel includes a pixel circuit and a light-emitting element. FIG. 41 is called an RGB real layout, in which one pixel is composed of a subpixel SP including a red light-emitting element R, a subpixel SP including a green light-emitting element G, and a subpixel SP including a blue light-emitting element B. In the RGB real layout, K can be a multiple of 3, and K=M (see, for example, FIGS. 3, 8, and 30). In particular, K=3 or K=6. FIG. 42 is called a diamond pentile layout, in which one pixel is composed of a subpixel SP including R and a subpixel SP including G, or a subpixel SP including B and a subpixel SP including G. In the diamond pentile layout, K can be a multiple of 2, and K=M (see, for example, FIGS. 11, 15, and 40). In particular, K=4.

[0041] When forming multiple contact holes in one pixel circuit, these contact holes can be provided in the pixel circuit of the subpixel having the smallest light-emitting area among the three subpixels including the R, G, and B light-emitting elements.

[0042] [Notes] The above-described embodiments are for the purpose of illustration and description, and are not intended to be limiting. Based on these examples and descriptions, it will be apparent to those skilled in the art that many variations are possible.

[0043] P (P1 to P9) Pixel circuit Q (Q1 to Q9) Light-emitting element H (H1 to H9, Ha) Contact hole L1 First control line L2 Second control line L3 Third control line J1 First relay line J2 Second relay line W1 First connection wiring W2 Second connection wiring YL (DL, PL) Wiring (data signal line, power supply line) F1 First group F2 Second group F3 Third group D1 First driver D2 Second driver DA Display area NA Non-display area 10 Display device

Claims

1. A display device including a first set consisting of K pixel circuits aligned in a first direction, where K and M are integers of 2 or greater, and a second set consisting of M pixel circuits aligned in the first direction, the display device having a display area and a non-display area in which the first and second sets are adjacent in the first direction, the display device including: a first control line connected to each of the K pixel circuits; a second control line connected to each of the M pixel circuits; and a first relay line, at least one of both ends of which is located in the display area and electrically connected to the first control line and the second control line.

2. The display device according to claim 1, wherein the first relay line overlaps with the first control line and the second control line in a plan view.

3. The display device according to claim 1 or 2, wherein the first relay line is located in a layer above the first control line and the second control line.

4. A display device as described in any one of claims 1 to 3, wherein the first control line and the second control line are arranged in the first direction, the first control line is connected to the gate of a functional transistor included in each of the K pixel circuits, and the second control line is connected to the gate of a functional transistor included in each of the M pixel circuits.

5. A display device according to any one of claims 1 to 4, wherein the first control line and the first relay line are connected by one or more contact holes, and the second control line and the first relay line are connected by one or more contact holes.

6. The display device according to claim 5, wherein the first control line and the first relay line are connected by a plurality of contact holes.

7. The display device according to claim 5 or 6, wherein the second control line and the first relay line are connected by a plurality of contact holes.

8. A display device according to any one of claims 5 to 7, wherein the number of contact holes connecting the first control lines and the first relay lines is the same as the number of contact holes connecting the second control lines and the first relay lines.

9. A display device according to any one of claims 5 to 7, wherein the number of contact holes connecting the first control lines and the first relay lines is different from the number of contact holes connecting the second control lines and the first relay lines.

10. The display device according to any one of claims 5 to 9, wherein one pixel circuit of the second set includes two contact holes connecting the second control line and the first relay line.

11. The display device according to claim 10, wherein each of the two or more pixel circuits in the first set includes one contact hole connecting the first control line and the first relay line.

12. The display device according to any one of claims 1 to 11, wherein both ends of the first relay line are located in the display area.

13. The display device according to any one of claims 1 to 12, wherein the first relay line has a smaller electrical resistance per unit length than the first control line and the second control line.

14. A display device according to any one of claims 1 to 13, wherein the non-display area includes a first driver, and a control signal from the first driver is transmitted to the second control line via the first relay line.

15. The display device according to claim 14, wherein the non-display area includes a second driver, and a control signal from the second driver is transmitted to the first control line via the first relay line.

16. A display device as described in any one of claims 1 to 15, wherein in the display area, a third set consisting of N pixel circuits aligned in a first direction, where N is an integer of 2 or greater, is adjacent to the second set in the first direction, and includes: a third control line connected to each of the N pixel circuits; and a second relay line, at least one of both ends of which is located in the display area and electrically connected to the second control line and the third control line.

17. The display device of claim 16, wherein the second relay line overlaps with the second control line and the third control line in a planar view, and the first relay line and the second relay line extend in the first direction and are aligned in the first direction.

18. A display device as described in claim 16 or 17, comprising: K light-emitting elements provided corresponding to each of the K pixel circuits; M light-emitting elements provided corresponding to each of the M pixel circuits; and N light-emitting elements provided corresponding to each of the N pixel circuits.

19. The display device described in claim 18, wherein the second set comprises M contact holes provided corresponding to each of the M pixel circuits, and the M contact holes include a contact hole connecting the second control line and the first relay line, and a contact hole connecting the second control line and the second relay line.

20. The display device according to claim 19, wherein the number of contact holes connecting the second control lines and the first relay lines is the same as the number of contact holes connecting the second control lines and the second relay lines.

21. The display device according to claim 19, wherein the number of contact holes connecting the second control lines and the first relay lines is different from the number of contact holes connecting the second control lines and the second relay lines.

22. The display device according to any one of claims 19 to 21, wherein K, M and N are the same multiple of 3, and the K light-emitting elements include red light-emitting elements, green light-emitting elements and blue light-emitting elements in a numerical ratio of 1:1:

1.

23. The display device according to claim 22, wherein K=M=N=3, or K=M=N=6, or K=M=N=9.

24. The display device according to any one of claims 19 to 21, wherein K, M and N are the same multiple of 4, and the K light-emitting elements include red light-emitting elements, green light-emitting elements and blue light-emitting elements in a ratio of 1:2:

1.

25. The display device of claim 24, wherein K=M=N=4, K=M=N=8, or K=M=N=12.

26. A display device as described in any one of claims 19 to 25, wherein the second set includes, in addition to the M contact holes, a redundant contact hole located in at least one pixel circuit of the second set, and the redundant contact hole is connected to the second control line and the first relay line.

27. The display device according to claim 26, wherein the pixel circuit in which the redundant contact hole is located is connected to a blue light-emitting element.

28. The display device according to claim 3, further comprising a plurality of data signal lines extending in a second direction perpendicular to the first direction, and an organic insulating film is positioned between the first relay line and the plurality of data signal lines.

29. The display device according to claim 4, further comprising a power supply line, wherein the functional transistor is a switching transistor connected to the power supply line.

30. The display device according to claim 4, further comprising a data signal line, and the functional transistor is a switching transistor connected to the data signal line.

31. The display device according to claim 14, further comprising a first connection wiring connected to the first driver and spanning an edge of the display area, the first connection wiring being located in the same layer as the first relay line and being electrically connected to the first relay line.

32. The display device according to claim 15, further comprising a second connection wiring connected to the second driver and spanning an edge of the display area, the second connection wiring being located in the same layer as the first relay line and being electrically connected to the first relay line.

33. The display device of claim 14, further comprising an edge control line connected to the first driver and spanning an edge of the display area, the edge control line being located in the same layer as the first control line and connected to one or more pixel circuits.

34. The display device according to claim 14, wherein one end of the first relay line is connected to the first driver.

35. The display device according to claim 14, wherein one end of the first control line is connected to the first driver.

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