Gate drive unit and display apparatus

Abstract

A gate drive unit and a display apparatus. A pull-up control module (101) of one gate drive circuit (10) receives a gate control signal output by means of an upper-stage gate drive circuit (10), so that the stage transmission control of multiple stages of gate drive circuits (10) can be realized without providing a stage transmission module in the gate drive circuit (10), thereby helping to reduce the number of transistors used in the gate drive circuit (10) and reduce a layout space occupied by the gate drive circuit (10).

Description

Gate driving unit and display device Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate driving unit and a display device. Background Art

[0002] Existing gate drive units typically require 15 thin-film transistors to output square wave pulse signals row by row, occupying a significant amount of space within the display panel layout, hindering the realization of a narrow-bezel design. Furthermore, compared to large-size display devices, applying a gate drive circuit with the same topology to a small-size display device requires more space within the sub-pixel layout than in a medium- to large-size display device, compromising the display quality of the small-size display device. SUMMARY OF THE INVENTION

[0003] The embodiments of the present application provide a gate drive unit and a display device, which can improve the problem that the gate drive circuit occupies a large layout space, which is not conducive to achieving a narrow-frame design for the display panel, and the gate drive circuit seriously squeezes the layout space of sub-pixels when the gate drive circuit is applied to a small-sized display device.

[0004] An embodiment of the present application provides a gate drive unit comprising a plurality of cascaded gate drive circuits, at least one of which comprises a pull-up control module, a pull-up module, a pull-down maintenance module, and a pull-down module. The pull-up control module is electrically connected to a first node, configured to receive a gate control signal output by an upper-level gate drive circuit and transmit a first power supply signal to the first node. The pull-up module is electrically connected to the first node, configured to transmit a first clock signal to a signal output terminal of the gate drive circuit at the current level based on the potential of the first node. The pull-down maintenance module is electrically connected to the first node, configured to transmit a second power supply signal to the first node based on a second clock signal and a third clock signal. The pull-down module is electrically connected to the first node, configured to transmit the second power supply signal to the first node based on a gate control signal output by a lower-level gate drive circuit.

[0005] Optionally, in some embodiments of the present application, the pull-up control module includes a pull-up control transistor, the control end of the pull-up control transistor is configured to receive the gate control signal output by the upper gate drive circuit, the input end of the pull-up control transistor is configured to receive the first power supply signal, and the output end of the pull-up control transistor is electrically connected to the first node.

[0006] Optionally, in some embodiments of the present application, the pull-up module includes a pull-up transistor and a storage capacitor, the control end of the pull-up transistor is electrically connected to the first node, the input end of the pull-up transistor is configured to receive the first clock signal, and the output end of the pull-up transistor is electrically connected to the signal output end of the gate drive circuit at this level; the storage capacitor is connected in series between the control end of the pull-up transistor and the output end of the pull-up transistor.

[0007] Optionally, in some embodiments of the present application, the pull-down hold module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The control terminal of the first transistor is configured to receive the third clock signal, and the input terminal of the first transistor is configured to receive the third power supply signal. The control terminal of the second transistor is electrically connected to the first node, the output terminal of the second transistor is electrically connected to the output terminal of the first transistor, and the input terminal of the second transistor is configured to receive the second power supply signal. The control terminal of the third transistor is electrically connected to the output terminal of the first transistor, and the input terminal of the third transistor is configured to receive the third power supply signal. The control terminal of the fourth transistor is electrically connected to the first node, the input terminal of the fourth transistor is configured to receive the second power supply signal, and the output terminal of the fourth transistor is electrically connected to the output terminal of the third transistor. The control terminal of the fifth transistor is electrically connected to the output terminal of the third transistor, the input terminal of the fifth transistor is configured to receive the second power supply signal, and the output terminal of the fifth transistor is electrically connected to the first node. The control terminal of the sixth transistor is configured to receive the second clock signal, the input terminal of the sixth transistor is configured to receive the second power signal, and the output terminal of the sixth transistor is electrically connected to the control terminal of the fifth transistor.

[0008] Optionally, in some embodiments of the present application, the pull-down maintenance module also includes a seventh transistor, the control end of the seventh transistor is configured to receive the second clock signal, the input end of the seventh transistor is configured to receive the second power supply signal, and the output end of the seventh transistor is electrically connected to the control end of the third transistor.

[0009] Optionally, in some embodiments of the present application, the pull-down maintenance module also includes an eighth transistor, the control end of the eighth transistor is electrically connected to the control end of the fifth transistor, the input end of the eighth transistor is configured to receive the second power supply signal, and the output end of the eighth transistor is electrically connected to the signal output end of the gate drive circuit at this level.

[0010] Optionally, in some embodiments of the present application, the gate drive unit further includes a reset module, the reset module includes a reset transistor, the control end of the reset transistor is configured to receive a reset control signal, the input end of the reset transistor is configured to receive the third power supply signal, and the output end of the reset transistor is electrically connected to the control end of the fifth transistor.

[0011] Optionally, in some embodiments of the present application, the pull-down module includes a pull-down transistor, the control end of the pull-down transistor is configured to receive the gate control signal output by the gate drive circuit of the lower level, the input end of the pull-down transistor is configured to receive the second power supply signal, and the output end of the pull-down transistor is electrically connected to the signal output end of the gate drive circuit of this level.

[0012] Optionally, in some embodiments of the present application, the pull-up control module of the N-th level gate driving circuit receives the gate control signal output by the NX-th level gate driving circuit located before the N-th level gate driving circuit, and the pull-down module of the N-th level gate driving circuit receives the gate control signal output by the N+Y-th level gate driving circuit located after the N-th level gate driving circuit; wherein, Y>X, N>1, X>0.

[0013] The present application also provides a display device, comprising any of the above-mentioned gate driving units and a plurality of sub-pixels; wherein the plurality of sub-pixels are electrically connected to the plurality of gate driving circuits. Beneficial effects

[0014] Compared with the prior art, the embodiments of the present application provide a gate drive unit and a display device. By enabling the pull-up control module of the gate drive circuit to receive the gate control signal output by the upper-level gate drive circuit, the stage transmission module can be omitted in the gate drive circuit, thereby realizing stage transmission control of the multi-stage gate drive circuit, which is beneficial to reducing the number of transistors used in the gate drive circuit and reducing the layout space occupied by the gate drive circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] FIG1 is a schematic structural diagram of a gate driving unit provided in an embodiment of the present application;

[0016] 2A and 2B are schematic structural diagrams of a gate drive circuit provided in an embodiment of the present application;

[0017] FIG3 is a timing diagram corresponding to the gate drive circuit provided in an embodiment of the present application;

[0018] 4A and 4B are simulation diagrams corresponding to the gate drive circuit provided in an embodiment of the present application;

[0019] FIG5 is a schematic structural diagram of a display device provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0020] To make the purpose, technical solutions and effects of this application clearer and more specific, the following further describes this application in detail with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are only used to explain this application and are not intended to limit this application.

[0021] Specifically, Figure 1 is a structural schematic diagram of a gate driving unit provided in an embodiment of the present application. The embodiment of the present application provides a gate driving unit, including multiple cascaded gate driving circuits 10, and the multiple cascaded gate driving circuits 10 are configured to generate multiple gate control signals Scan.

[0022] 2A and 2B are schematic structural diagrams of gate drive circuits provided in embodiments of the present application; at least one gate drive circuit 10 includes a pull-up control module 101 , a pull-up module 102 , a pull-down maintaining module 103 , and a pull-down module 104 .

[0023] The pull-up control module 101 is electrically connected to the first node Q. The pull-up control module 101 is configured to receive a gate control signal output by an upper gate driving circuit and transmit a first power signal VGH to the first node Q to raise the potential of the first node Q.

[0024] Optionally, the pull-up control module 101 includes a pull-up control transistor Tuc, the control end of the pull-up control transistor Tuc is configured to receive the gate control signal output by the upper gate drive circuit, the input end of the pull-up control transistor Tuc is configured to receive the first power supply signal VGH, the output end of the pull-up control transistor Tuc is electrically connected to the first node Q, and the pull-up control transistor Tuc is configured to transmit the first power supply signal VGH to the first node Q according to the gate control signal output by the upper gate drive circuit to raise the potential of the first node Q.

[0025] Optionally, the pull-up control module 101 of the N-th stage gate driver circuit receives a gate control signal Scan(NX) output by an N-th stage gate driver circuit located before the N-th stage gate driver circuit, and transmits the first power supply signal VGH to the first node Q of the N-th stage gate driver circuit according to the gate control signal Scan(NX) output by the N-th stage gate driver circuit, thereby raising the potential of the first node Q in the N-th stage gate driver circuit. Where X>0.

[0026] Optionally, the pull-up control module 101 in the first gate driving circuit in the multi-stage gate driving circuit can receive a start signal to transmit the first power signal VGH to the first node Q according to the start signal, thereby raising the potential of the first node Q in the first gate driving circuit.

[0027] Please continue to refer to Figures 2A to 2B. The pull-up module 102 is electrically connected to the first node Q. The pull-up module 102 is configured to transmit the first clock signal CK1 to the signal output end of the gate drive circuit 10 at this level according to the potential of the first node Q. The signal output end is configured to output the gate control signal Scan.

[0028] Optionally, the pull-up module 102 includes a pull-up transistor To and a storage capacitor Cst.

[0029] The control end of the pull-up transistor To is electrically connected to the first node Q, the input end of the pull-up transistor To is configured to receive the first clock signal CK1, and the output end of the pull-up transistor To is electrically connected to the signal output end of the gate drive circuit 10 at this level. The pull-up transistor To is configured to be turned on or off according to the potential of the first node Q, so that when the pull-up transistor To is turned on, the first clock signal CK1 is transmitted to the signal output end of the gate drive circuit 10 at this level, so that the gate control signal Scan output by the signal output end of the gate drive circuit 10 at this level can have a valid pulse.

[0030] The storage capacitor Cst is connected in series between the control end of the pull-up transistor To and the output end of the pull-up transistor To. The storage capacitor Cst is used to maintain the potential of the first node Q.

[0031] 2A to 2B , the pull-down maintaining module 103 is electrically connected to the first node Q. The pull-down maintaining module 103 is configured to transmit the second power signal VSSQ to the first node Q according to the second clock signal CK2 and the third clock signal CK3 .

[0032] Optionally, the pull-down maintaining module 103 includes a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , and a sixth transistor T6 .

[0033] The control terminal of the first transistor T1 is configured to receive the third clock signal CK3 , and the input terminal of the first transistor T1 is configured to receive the third power signal VDD.

[0034] The control end of the second transistor T2 is electrically connected to the first node Q, the output end of the second transistor T2 is electrically connected to the output end of the first transistor T1, and the input end of the second transistor T2 is configured to receive the second power signal VSSQ.

[0035] The control end of the third transistor T3 is electrically connected to the output end of the first transistor T1 , and the input end of the third transistor T3 is configured to receive the third power signal VDD.

[0036] The control terminal of the fourth transistor T4 is electrically connected to the first node Q, the input terminal of the fourth transistor T4 is configured to receive the second power signal VSSQ, and the output terminal of the fourth transistor T4 is electrically connected to the output terminal of the third transistor T3.

[0037] The control end of the fifth transistor T5 is electrically connected to the output end of the third transistor T3 , the input end of the fifth transistor T5 is configured to receive the second power signal VSSQ , and the output end of the fifth transistor T5 is electrically connected to the first node Q .

[0038] The control terminal of the sixth transistor T6 is configured to receive the second clock signal CK2 , the input terminal of the sixth transistor T6 is configured to receive the second power signal VSSQ, and the output terminal of the sixth transistor T6 is electrically connected to the control terminal of the fifth transistor T5 .

[0039] Optionally, the pull-down maintenance module 103 also includes a seventh transistor T7, the control end of the seventh transistor T7 is configured to receive the second clock signal CK2, the input end of the seventh transistor T7 is configured to receive the second power supply signal VSSQ, the output end of the seventh transistor T7 is electrically connected to the control end of the third transistor T3, and the seventh transistor T7 is configured to be turned on or off according to the second clock signal CK2, so as to control the third transistor T3 to be turned off through the second power supply signal VSSQ when the seventh transistor T7 is turned on.

[0040] Optionally, the pull-down maintaining module 103 further includes an eighth transistor T8, wherein a control terminal of the eighth transistor T8 is electrically connected to the control terminal of the fifth transistor T5, an input terminal of the eighth transistor T8 is configured to receive the second power supply signal VSSQ, and an output terminal of the eighth transistor T8 is electrically connected to the signal output terminal of the gate driver circuit at this stage. The eighth transistor T8 is configured to be turned on synchronously with the fifth transistor T5 to pull down the potential of the signal output terminal of the gate driver circuit 10 via the second power supply signal VSSQ.

[0041] 2A to 2B , the pull-down module 104 is electrically connected to the first node Q. The pull-down module 104 is configured to transmit the second power signal VSSQ to the first node Q according to the gate control signal output by the lower gate driving circuit.

[0042] Optionally, the pull-down module 104 includes a pull-down transistor Td, the control end of the pull-down transistor Td is configured to receive the gate control signal output by the lower-level gate drive circuit, the input end of the pull-down transistor Td is configured to receive the second power supply signal VSSQ, the output end of the pull-down transistor Td is electrically connected to the signal output end of the gate drive circuit at this level, and the pull-down transistor Td is configured to be turned on or off according to the gate control signal output by the lower-level gate drive circuit, so that when the pull-down transistor Td is turned on, the second power supply signal VSSQ is transmitted to the first node Q to lower the potential of the first node Q.

[0043] Optionally, the pull-down module of the N-th level gate driving circuit receives the gate control signal Scan(N+Y) output by the N+Y-th level gate driving circuit located after the N-th level gate driving circuit, so that the pull-down module of the N-th level gate driving circuit pulls down the potential of the first node Q of the N-th level gate driving circuit according to the gate control signal Scan(N+Y) output by the N+Y-th level gate driving circuit; wherein, Y>0.

[0044] Optionally, the pull-up control module of the N-th stage gate driver circuit receives a gate control signal Scan(NX) output by an NX-th stage gate driver circuit located before the N-th stage gate driver circuit, and the pull-down module of the N-th stage gate driver circuit receives a gate control signal Scan(N+Y) output by an N+Y-th stage gate driver circuit located after the N-th stage gate driver circuit. Y>X, so that the potential of the first node Q of the N-th stage gate driver circuit is pulled up and down in an asymmetric manner, so that the duration corresponding to the potential of the first node Q of the N-th stage gate driver circuit is pulled down is shorter than the duration corresponding to the potential of the first node Q being pulled up, which is conducive to maintaining the potential stability of the first node Q.

[0045] Optionally, the pull-up control module of the N-th level gate driving circuit receives the gate control signal Scan(N-4) output by the N-4-th level gate driving circuit located before the N-th level gate driving circuit, and the pull-down module of the N-th level gate driving circuit receives the gate control signal Scan(N+6) output by the N+6-th level gate driving circuit located after the N-th level gate driving circuit.

[0046] Optionally, to save layout space and power consumption, the multiple stages of the gate driving circuits 10 included in the gate driving unit share M clock signals. Optionally, X=M / 2.

[0047] Optionally, the gate drive unit further includes a reset module 105, wherein the reset module 105 is configured to reset the potential of the first node Q according to a reset control signal Reset and a third power supply signal VDD. Optionally, the reset module 105 is configured to reset the potential of the signal output terminal according to the reset control signal Reset and the third power supply signal VDD.

[0048] Optionally, the reset module 105 includes a reset transistor Ti, wherein a control terminal of the reset transistor Ti is configured to receive a reset control signal Reset, an input terminal of the reset transistor Ti is configured to receive the third power supply signal VDD, and an output terminal of the reset transistor Ti is electrically connected to the control terminal of the fifth transistor T5. The reset transistor Ti is configured to be turned on or off according to the reset control signal Reset, so that when the reset transistor Ti is turned on, the third power supply signal VDD is used to control the fifth transistor T5 and the eighth transistor T8 to be turned on, thereby resetting the potential of the first node Q and the potential of the signal output terminal via the second power supply signal VSSQ, thereby clearing residual charge at the first node Q and the signal output terminal.

[0049] Optionally, when the gate drive unit is applied to a display panel, the reset control signal Reset may have an active pulse at power-on to reset the potentials of the first node and the signal output terminal of the multi-stage gate drive circuit; and / or the reset control signal Reset may have an active pulse during the blanking interval between frames to reset the potentials of the first node and the signal output terminal of the multi-stage gate drive circuit. The active pulse of the start signal received by the first gate drive circuit in the multi-stage gate drive circuit may be located after the active pulse of the reset control signal Reset, so that each stage of the gate drive circuit can output a corresponding gate control signal Scan based on the same potential of the first node Q and the potential of the signal output terminal, thereby improving the uniformity of the gate control signals Scan output by the multiple gate drive circuits.

[0050] Optionally, a voltage value corresponding to the first power signal VGH is greater than a voltage value corresponding to the second power signal VSSQ.

[0051] Optionally, when the potential of the first node Q in the gate driving circuit 10 jumps from a high level to a low level, in order not to have a large voltage coincidence point with the jump of the potential of the second node P (i.e., the control terminal of the fifth transistor) from a low level to a high level, the starting moment of the effective pulse of the second clock signal CK2 lags behind the starting moment of the effective pulse of the first clock signal CK1, the starting moment of the effective pulse of the third clock signal CK3 lags behind the starting moment of the effective pulse of the second clock signal CK2, and the effective pulse of the third clock signal CK3 does not coincide with the pulse of the first clock signal CK1.

[0052] Optionally, in order to reduce the layout space and power consumption, multiple levels of the gate driving circuit 10 share multiple clock signals. Therefore, according to the level where the gate driving circuit 10 is located, the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 corresponding to each level of the gate driving circuit 10 can be determined from multiple clock signals.

[0053] Optionally, if multiple levels of the gate driving circuit 10 share M clock signals, then the first clock signal CK1 received by the Nth level of the gate driving circuit 10 is CK(m), the second clock signal CK2 received by the Nth level of the gate driving circuit 10 is CK(m + A), and the third clock signal CK3 received by the Nth level of the gate driving circuit 10 is CK(m + B). Where 0 < m ≤ M, m < m + A ≤ M, m + A < m + B ≤ M, A > 0, B > 0; when N ≤ M, m = N; when N > M, m = N - aM, m > 0, a > 0 and a is an integer.

[0054] Optionally, B = M / 2, so that the effective pulse of the third clock signal CK3 and the effective pulse of the first clock signal CK1 do not coincide (that is, the third clock signal CK3 and the first clock signal CK1 form mutual coupling), so that after the gate control signal Scan output by the gate driving circuit 10 outputs an effective pulse through the signal output terminal, the potential of the first node Q is pulled down, avoiding the influence on the output gate control signal Scan when pulling down the potential of the first node Q.

[0055] Optionally, the difference between B and A can be 1 to 3, so that when the potential of the first node Q in the gate driving circuit 10 jumps from a high level to a low level, it does not have a large voltage coincidence point with the jump of the potential of the second node P from a low level to a high level.

[0056] Optionally, A is 2, 3, or 4, and B is 4, 5, 6, or 7. Optionally, A is 2 and B is 6 to improve the risk that the charging of the first node Q is affected and a large current occurs because when the potential of the first node Q in the gate drive circuit 10 jumps from a high level to a low level, there is a large voltage overlap with the potential of the second node P (i.e., the control terminal of the fifth transistor) changes from a low level to a high level.

[0057] Optionally, A and B can be determined based on the received upper-level gate control signal and lower-level gate control signal to reduce signal selection complexity. For example, if the pull-up control module of the N-th stage gate driver circuit receives a gate control signal Scan(NX), and the pull-down module of the N-th stage gate driver circuit receives a gate control signal Scan(N+Y), then B=X and A=YX.

[0058] Optionally, at least one of the pull-up control transistor Tuc, the pull-up transistor To, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the pull-down transistor Td and the reset transistor Ti included in the gate drive circuit 10 may be a silicon transistor or an oxide transistor.

[0059] Figure 3 is a timing diagram corresponding to the gate drive circuit provided in an embodiment of the present application. Taking the multi-level gate drive circuit 10 sharing 12 clock signals, the first clock signal CK1 received by the N-level gate drive circuit is CK(m), the second clock signal CK2 received by the N-level gate drive circuit is CK(m+A), the third clock signal CK3 received by the N-level gate drive circuit is CK(m+B), the upper-level gate control signal received by the N-level gate drive circuit is Scan(NX), the lower-level gate control signal received by the N-level gate drive circuit is Scan(N+Y), and the transistors included in the N-level gate drive circuit are N-type transistors as an example, the working principle of the N-level gate drive circuit is explained as follows.

[0060] In which, in the reset stage before the multi-stage gate drive circuit 10 outputs multiple gate control signals Scan, the reset control signal Reset is at a high level, the reset transistor Ti in the multi-stage gate drive circuit 10 is turned on, and then the eighth transistor T8 and the fifth transistor T5 are both turned on, so that the potential of the first node Q of the multi-stage gate drive circuit 10 is at a low level, and the potential of the second node P is at a high level.

[0061] First stage t1: the upper gate control signal Scan(NX) is at a high level, and the first clock signal CK(m), the second clock signal CK(m+A), the third clock signal CK(m+B) and the lower gate control signal Scan(N+Y) are at a low level.

[0062] The pull-up control transistor Tuc is turned on, and the first power supply signal VGH is transmitted to the first node Q via the pull-up control transistor Tuc to raise the potential of the first node Q. The second transistor T2, the fourth transistor T4, and the pull-up transistor To are turned on, so that the potential of the second node P is pulled down. The third transistor T3, the fifth transistor T5, and the eighth transistor T8 are turned off according to the second power supply signal VSSQ. The first clock signal CK1 is transmitted to the signal output end, so that the gate control signal Scan(N) output by the signal output end has a low level.

[0063] Second stage t2: the upper gate control signal Scan(NX) and the first clock signal CK(m) are at high level, and the second clock signal CK(m+A), the third clock signal CK(m+B) and the lower gate control signal Scan(N+Y) are at low level.

[0064] The potential of the first node Q is further raised by the coupling of the first clock signal CK(m) changing from a low level to a high level, so that the second transistor T2, the fourth transistor T4 and the pull-up transistor To remain turned on, and the third transistor T3, the fifth transistor T5 and the eighth transistor T8 remain turned off; the first clock signal CK1 is transmitted to the signal output end, so that the gate control signal Scan(N) output by the signal output end has a high level.

[0065] In the third stage t3, the first clock signal CK(m) is at a high level, and the upper gate control signal Scan(NX), the second clock signal CK(m+A), the third clock signal CK(m+B) and the lower gate control signal Scan(N+Y) are at a low level.

[0066] The storage capacitor Cst maintains the potential of the first node Q, so that the second transistor T2, the fourth transistor T4 and the pull-up transistor To remain turned on, and the third transistor T3, the fifth transistor T5 and the eighth transistor T8 remain turned off; the first clock signal CK1 is transmitted to the signal output end, so that the gate control signal Scan(N) output by the signal output end still has a high level.

[0067] Fourth stage t4: the first clock signal CK(m) and the second clock signal CK(m+A) are at high level, and the upper gate control signal Scan(NX), the third clock signal CK(m+B) and the lower gate control signal Scan(N+Y) are at low level.

[0068] The sixth transistor T6 and the seventh transistor T7 are turned on according to the second clock signal CK(m+A), the storage capacitor Cst maintains the potential of the first node Q, so that the third transistor T3, the fifth transistor T5, and the eighth transistor T8 continue to be turned off according to the second power supply signal VSSQ, the second transistor T2, the fourth transistor T4, and the pull-up transistor To remain turned on, and the first clock signal CK1 is transmitted to the signal output end, so that the gate control signal Scan(N) output by the signal output end maintains a high level.

[0069] Fifth stage t5: the second clock signal CK(m+A) is at a high level, and the upper gate control signal Scan(NX), the first clock signal CK(m), the third clock signal CK(m+B) and the lower gate control signal Scan(N+Y) are at a low level.

[0070] The sixth transistor T6 and the seventh transistor T7 remain turned on, causing the third transistor T3, the fifth transistor T5, and the eighth transistor T8 to remain turned off in response to the second power supply signal VSSQ. The potential of the first node Q is pulled low by the first clock signal CK(m) changing from a high level to a low level. Furthermore, due to the low level of the first clock signal CK1, the gate control signal Scan(N) outputted from the signal output terminal is at a low level.

[0071] The sixth stage t6: the second clock signal CK(m+A) and the third clock signal CK(m+B) are at high level, the lower gate control signal Scan(N+Y), the upper gate control signal Scan(NX) and the first clock signal CK(m) are at low level.

[0072] The pull-down transistor Td is turned on in response to the lower-stage gate control signal Scan(N+Y), further pulling down the potential of the first node Q and turning off the second transistor T2, the fourth transistor T4, and the pull-up transistor To. The sixth and seventh transistors T6 and T7 remain on, the first transistor T1 is turned on in response to the third clock signal CK(m+B), and the control terminal of the third transistor T3 is affected by the third power signal VDD and the second power signal VSSQ. In some embodiments, if the difference between the third power signal VDD and the second power signal VSSQ is less than the threshold voltage of the third transistor T3, the third transistor T3 remains off, causing the potential of the second node P to remain low due to the influence of the second power signal VSSQ transmitted by the sixth transistor T6. The fifth and eighth transistors T5 and T8 remain off, allowing sufficient time for the potential of the first node Q to drop to a low level. This mitigates the problem of a significant overlap between the voltage corresponding to the first node Q and the voltage corresponding to the second node P when the potential of the first node Q is delayed due to the influence of the coupling capacitor and the potential of the second node P is in a rising phase.

[0073] Seventh stage t7: the third clock signal CK(m+B) is at a high level and the lower gate control signal Scan(N+Y), the upper gate control signal Scan(NX), the second clock signal CK(m+A) and the first clock signal CK(m) are at a low level.

[0074] The pull-down transistor Td remains on, so that the potential of the first node Q remains at a low level, and the second transistor T2, the fourth transistor T4, and the pull-up transistor To are turned off. The first transistor T1 remains on, so that the third transistor T3, the fifth transistor T5, and the eighth transistor T8 are turned on. The second power supply signal VSSQ is output to the signal output terminal, so that the gate control signal Scan(N) output by the signal output terminal still has a low level.

[0075] Afterwards, the first clock signal CK(m), the second clock signal CK(m+A), and the third clock signal CK(m+B) transition between low and high levels. However, because the upper gate control signal Scan(NX) remains at a low level, the potential of the first node Q may be affected by the first clock signal CK(m) in actual applications, resulting in coupled transitions at the transition point of the first clock signal CK(m). The potential of the second node P remains low when affected by the second clock signal CK(m+A) and remains high when affected by the third clock signal CK(m+B).

[0076] Figures 4A and 4B are simulation diagrams corresponding to the gate drive circuit provided in an embodiment of the present application. The inventors of the present application conducted a reliability simulation of the gate drive unit of the present application in a high temperature and high humidity environment. The resulting simulation waveforms show that: the potential of the second node P of the single-stage gate drive circuit 10 fluctuates between high and low potentials, which is in line with the design expectations; the potential variation of the first node Q is in line with the design expectations; the gate control signal Scan outputted from the signal output terminal is output normally, and the stability of the output of the gate drive circuit 10 can be maintained, as shown in Figure 4A. The multi-stage gate drive circuit 10 can achieve normal level transmission function, and the multi-stage gate drive circuit 10 can output the gate control signal Scan with square pulses row by row, as shown in Figure 4B. Therefore, the gate drive circuit 10 provided in the present application can achieve output function and reliability similar to that of the conventional gate drive circuit 10 using a smaller number of transistors. As an application embodiment of the present application, the gate drive circuit 10 of the present application has been applied to a 27-inch full HD resolution model for verification, and the verification results are shown in the simulation results of Figures 4A and 4B.

[0077] The gate drive circuit 10 provided in the present application omits the stage transmission module so that the pull-up control unit of the gate drive circuit 10 is no longer affected by the stage transmission signal, thereby reducing the number of transistors used in the stage gate drive circuit 10, so that the single-stage gate drive circuit 10 only requires 12 transistors at most, which can maintain the same stability and reliability as the traditional gate drive circuit 10, which is conducive to enabling the gate drive unit to meet the design requirements of extremely narrow-frame products. When the gate drive unit is used in a small-size display panel, it can reduce the gate drive circuit 10 from squeezing out the sub-pixel layout space.

[0078] Furthermore, prior art also utilizes gate drive circuits with multi-level output capabilities (i.e., a single-stage gate drive circuit 10 simultaneously outputs two or more levels of gate control signals Scan) to reduce the number of gate drive circuits included in a gate drive unit, thereby reducing the average number of transistors contained in each gate drive circuit within the gate drive unit. However, when a single-stage gate drive circuit simultaneously outputs multiple levels of gate control signals Scan, the overall load on the gate drive circuit and the gate drive unit is increased, and the size of each transistor also needs to be increased to meet the required performance requirements. Therefore, gate drive circuits that simultaneously output multiple levels of gate control signals Scan consume a large amount of power, and to meet stability and reliability requirements, the layout space occupied by the gate drive circuit is further increased. Furthermore, gate drive circuits that simultaneously output multiple levels of gate control signals Scan also have stability issues. To improve this stability, two power supply signals lower than the first power supply signal VGH must be introduced to lower the potential of the first node and the signal output terminal. However, the present application only requires the use of a single power supply signal (i.e., the second power supply signal VSSQ) lower than the first power supply signal VGH to maintain the stability and reliability of the gate drive circuit 10.

[0079] Therefore, compared with the gate drive circuit that simultaneously outputs multiple levels of gate control signals Scan, the gate drive circuit 10 provided in the present application has lower power consumption, reduces the layout space occupied by the gate drive circuit 10, and does not need to adjust the transistor size to meet the stability and reliability requirements; the number of applied signals is also smaller, which helps to reduce the control difficulty.

[0080] FIG5 is a schematic diagram of the structure of a display device provided in an embodiment of the present application. The present application further provides a display device comprising any of the above-mentioned gate driving units and a plurality of sub-pixels Pi, wherein the plurality of sub-pixels are electrically connected to the plurality of gate driving circuits 10.

[0081] Optionally, the display device includes a passive light-emitting display device (such as a liquid crystal display device, etc.), a self-luminous display device (such as a display device including light-emitting devices such as organic light-emitting diodes, sub-millimeter light-emitting diodes, and micro light-emitting diodes).

[0082] Optionally, the sub-pixel Pi includes a pixel driving circuit, and the pixel driving circuit includes at least one transistor, and a control terminal of the transistor receives a corresponding gate control signal Scan.

[0083] Optionally, the pixel driving circuit may adopt a topology structure in the form of 2T1C (i.e., 2 transistors, 1 capacitor), 5T2C (i.e., 5 transistors, 2 capacitors), 7T1C (i.e., 7 transistors, 1 capacitor), 8T2C (i.e., 8 transistors, 2 capacitors), etc.

[0084] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for technical personnel in this field, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A gate driving unit, wherein: A plurality of cascaded gate drive circuits are included, at least one of the gate drive circuits comprising: A pull-up control module, electrically connected to the first node, configured to receive a gate control signal output by an upper gate driving circuit and transmit a first power supply signal to the first node; a pull-up module, electrically connected to the first node, and configured to transmit the first clock signal to the signal output terminal of the gate driving circuit at this stage according to the potential of the first node; a pull-down maintaining module, electrically connected to the first node, and configured to transmit a second power signal to the first node according to a second clock signal and a third clock signal; and The pull-down module is electrically connected to the first node and is configured to transmit the second power signal to the first node according to a gate control signal output by a lower-level gate driving circuit.

2. The gate driving unit according to claim 1, wherein: The pull-up control module comprises: A pull-up control transistor, wherein the control end of the pull-up control transistor is configured to receive the gate control signal output by the upper gate drive circuit, the input end of the pull-up control transistor is configured to receive the first power supply signal, and the output end of the pull-up control transistor is electrically connected to the first node.

3. The gate driving unit according to claim 1, wherein: The pull-up module comprises: a pull-up transistor, wherein a control terminal of the pull-up transistor is electrically connected to the first node, an input terminal of the pull-up transistor is configured to receive the first clock signal, and an output terminal of the pull-up transistor is electrically connected to the signal output terminal of the gate drive circuit at this level; and A storage capacitor is connected in series between the control end of the pull-up transistor and the output end of the pull-up transistor.

4. The gate driving unit according to claim 1, wherein: The pull-down maintaining module comprises: a first transistor, wherein a control terminal of the first transistor is configured to receive the third clock signal, and an input terminal of the first transistor is configured to receive a third power supply signal; a second transistor, wherein a control terminal of the second transistor is electrically connected to the first node, an output terminal of the second transistor is electrically connected to an output terminal of the first transistor, and an input terminal of the second transistor is configured to receive the second power signal; a third transistor, wherein a control terminal of the third transistor is electrically connected to the output terminal of the first transistor, and an input terminal of the third transistor is configured to receive the third power signal; a fourth transistor, wherein a control terminal of the fourth transistor is electrically connected to the first node, an input terminal of the fourth transistor is configured to receive the second power signal, and an output terminal of the fourth transistor is electrically connected to an output terminal of the third transistor; a fifth transistor, wherein a control terminal of the fifth transistor is electrically connected to the output terminal of the third transistor, an input terminal of the fifth transistor is configured to receive the second power signal, and an output terminal of the fifth transistor is electrically connected to the first node; and A sixth transistor, wherein the control end of the sixth transistor is configured to receive the second clock signal, the input end of the sixth transistor is configured to receive the second power supply signal, and the output end of the sixth transistor is electrically connected to the control end of the fifth transistor.

5. The gate driving unit according to claim 4, wherein: The pull-down maintaining module also includes: A seventh transistor, wherein the control end of the seventh transistor is configured to receive the second clock signal, the input end of the seventh transistor is configured to receive the second power supply signal, and the output end of the seventh transistor is electrically connected to the control end of the third transistor.

6. The gate driving unit according to claim 4, wherein: The pull-down maintaining module also includes: An eighth transistor, wherein the control end of the eighth transistor is electrically connected to the control end of the fifth transistor, the input end of the eighth transistor is configured to receive the second power supply signal, and the output end of the eighth transistor is electrically connected to the signal output end of the gate drive circuit at this level.

7. The gate driving unit according to claim 4, wherein: It also includes a reset module, the reset module including: A reset transistor, wherein the control end of the reset transistor is configured to receive a reset control signal, the input end of the reset transistor is configured to receive the third power supply signal, and the output end of the reset transistor is electrically connected to the control end of the fifth transistor.

8. The gate driving unit according to claim 1, wherein: The pull-down module comprises: A pull-down transistor, wherein the control end of the pull-down transistor is configured to receive the gate control signal output by the gate drive circuit of the lower level, the input end of the pull-down transistor is configured to receive the second power supply signal, and the output end of the pull-down transistor is electrically connected to the signal output end of the gate drive circuit of this level.

9. The gate driving unit according to claim 1, wherein: The pull-up control module of the Nth-level gate driving circuit receives the gate control signal output by the NXth-level gate driving circuit located before the Nth-level gate driving circuit, and the pull-down module of the Nth-level gate driving circuit receives the gate control signal output by the N+Yth-level gate driving circuit located after the Nth-level gate driving circuit; wherein, Y>X, N>1, X>0.

10. A display device, wherein: include: Multiple sub-pixels; The gate driving unit comprises a plurality of cascaded gate driving circuits, the plurality of sub-pixels are electrically connected to the plurality of gate driving circuits, and at least one of the gate driving circuits comprises: A pull-up control module, electrically connected to the first node, configured to receive a gate control signal output by an upper gate driving circuit and transmit a first power supply signal to the first node; a pull-up module, electrically connected to the first node, and configured to transmit the first clock signal to the signal output terminal of the gate driving circuit at this stage according to the potential of the first node; a pull-down maintaining module, electrically connected to the first node, and configured to transmit a second power signal to the first node according to a second clock signal and a third clock signal; and The pull-down module is electrically connected to the first node and is configured to transmit the second power signal to the first node according to a gate control signal output by a lower-level gate driving circuit.

11. The display device according to claim 10, wherein: The pull-up control module comprises: A pull-up control transistor, wherein the control end of the pull-up control transistor is configured to receive the gate control signal output by the upper gate drive circuit, the input end of the pull-up control transistor is configured to receive the first power supply signal, and the output end of the pull-up control transistor is electrically connected to the first node.

12. The display device according to claim 10, wherein: The pull-up module comprises: a pull-up transistor, wherein a control terminal of the pull-up transistor is electrically connected to the first node, an input terminal of the pull-up transistor is configured to receive the first clock signal, and an output terminal of the pull-up transistor is electrically connected to the signal output terminal of the gate drive circuit at this level; and A storage capacitor is connected in series between the control end of the pull-up transistor and the output end of the pull-up transistor.

13. The display device according to claim 10, wherein: The pull-down maintaining module comprises: a first transistor, wherein a control terminal of the first transistor is configured to receive the third clock signal, and an input terminal of the first transistor is configured to receive a third power supply signal; a second transistor, wherein a control terminal of the second transistor is electrically connected to the first node, an output terminal of the second transistor is electrically connected to an output terminal of the first transistor, and an input terminal of the second transistor is configured to receive the second power signal; a third transistor, wherein a control terminal of the third transistor is electrically connected to the output terminal of the first transistor, and an input terminal of the third transistor is configured to receive the third power signal; a fourth transistor, wherein a control terminal of the fourth transistor is electrically connected to the first node, an input terminal of the fourth transistor is configured to receive the second power signal, and an output terminal of the fourth transistor is electrically connected to an output terminal of the third transistor; a fifth transistor, wherein a control terminal of the fifth transistor is electrically connected to the output terminal of the third transistor, an input terminal of the fifth transistor is configured to receive the second power signal, and an output terminal of the fifth transistor is electrically connected to the first node; and A sixth transistor, wherein the control end of the sixth transistor is configured to receive the second clock signal, the input end of the sixth transistor is configured to receive the second power supply signal, and the output end of the sixth transistor is electrically connected to the control end of the fifth transistor.

14. The display device according to claim 13, wherein: The pull-down maintaining module also includes: A seventh transistor, wherein the control end of the seventh transistor is configured to receive the second clock signal, the input end of the seventh transistor is configured to receive the second power supply signal, and the output end of the seventh transistor is electrically connected to the control end of the third transistor.

15. The display device according to claim 13, wherein: The pull-down maintaining module also includes: An eighth transistor, wherein the control end of the eighth transistor is electrically connected to the control end of the fifth transistor, the input end of the eighth transistor is configured to receive the second power supply signal, and the output end of the eighth transistor is electrically connected to the signal output end of the gate drive circuit at this level.

16. The display device according to claim 13, wherein: It also includes a reset module, the reset module including: A reset transistor, wherein the control end of the reset transistor is configured to receive a reset control signal, the input end of the reset transistor is configured to receive the third power supply signal, and the output end of the reset transistor is electrically connected to the control end of the fifth transistor.

17. The display device according to claim 10, wherein: The pull-down module comprises: A pull-down transistor, wherein the control end of the pull-down transistor is configured to receive the gate control signal output by the gate drive circuit of the lower level, the input end of the pull-down transistor is configured to receive the second power supply signal, and the output end of the pull-down transistor is electrically connected to the signal output end of the gate drive circuit of this level.

18. The display device according to claim 10, wherein: The pull-up control module of the Nth-level gate driving circuit receives the gate control signal output by the NXth-level gate driving circuit located before the Nth-level gate driving circuit, and the pull-down module of the Nth-level gate driving circuit receives the gate control signal output by the N+Yth-level gate driving circuit located after the Nth-level gate driving circuit; wherein, Y>X, N>1, X>0.

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