Array substrate and display panel

Abstract

An array substrate and a display panel. The array substrate comprises: a base and a driving circuit layer located on the base, wherein a pixel circuit and a light-emission control signal line are provided in the driving circuit layer, the pixel circuit comprises a driving transistor, a first initialization transistor and a first connecting portion, and the first connecting portion is connected between a first electrode of the driving transistor and the first initialization transistor; there is an overlapping portion between an orthographic projection of the first connecting portion on the base and an orthographic projection of the light-emission control signal line on the base; an orthographic projection, on the base, of a shielding portion provided in the driving circuit layer overlaps the overlapping portion; the film layer where the shielding portion is located is located between the film layer where the light-emission control signal line is located and the film layer where the first connecting portion is located; and / or, at least one organic insulating layer is provided between the film layer where the first connecting portion is located and the film layer where the light-emission control signal line is located, and / or, the thickness of an insulating layer between the film layer where the first connecting portion is located and the film layer where the light-emission control signal line is located is greater than 3 microns.

Description

Array substrate and display panel

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on September 20, 2023, with application number 202311222580.4, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of display technology, for example, to an array substrate and a display panel. Background Art

[0003] With the rapid development of display technology, the application of display products based on organic light emitting devices (OLED) is becoming more and more widespread.

[0004] However, the display uniformity of OLED display panels needs to be improved.

[0005] Summary of the Invention

[0006] The present application provides an array substrate and a display panel to improve the display uniformity of the display panel.

[0007] An embodiment of the present application provides an array substrate, comprising: a substrate and a driving circuit layer located on the substrate, wherein a pixel circuit and a light-emitting control signal line are provided in the driving circuit layer, the pixel circuit comprises a driving transistor, a first initialization transistor and a first connection portion, the first connection portion being connected between the first electrode of the driving transistor and the first initialization transistor; the first connection portion and the light-emitting control signal line have an overlapping portion in their orthographic projection on the substrate; a shielding portion is further provided in the driving circuit layer, and the orthographic projection of the shielding portion on the substrate overlaps with the overlapping portion; the film layer where the shielding portion is located is located between the film layer where the light-emitting control signal line is located and the film layer where the first connection portion is located; and / or, at least one organic insulating layer is provided between the film layer where the first connection portion is located and the film layer where the light-emitting control signal line is located; and / or, the thickness of the insulating layer between the film layer where the first connection portion is located and the film layer where the light-emitting control signal line is located is greater than 3 microns.

[0008] An embodiment of the present application provides a display panel, which includes an array substrate according to any one of the embodiments of the present application.

[0009] The technical solution of the embodiment of the present application is to set a shielding part, and the orthographic projection of the shielding part on the substrate overlaps with the overlapping part. The film layer where the shielding part is located is located between the film layer where the light-emitting control signal line is located and the film layer where the first connecting part is located, so that the shielding part forms a shielding effect on the signal transmitted on the light-emitting control signal line, eliminates or reduces the degree of coupling (for example, the degree of potential reduction) of the parasitic capacitance generated in the overlapping part between the light-emitting control signal line and the first connecting part on the first pole potential of the driving transistor, and the coupling difference of the parasitic capacitance in the pixel circuits at different positions to the first pole potential of the driving transistor will also be reduced, so that the degree of influence of the parasitic capacitance on the driving current of the pixel circuits at different positions is the same or close, thereby making the display brightness of the light-emitting devices at different positions tend to be consistent under the same gray scale, which is beneficial to improving the display uniformity of the display panel and improving the display effect of the display panel. By providing at least one organic insulating layer between the film layer where the first connecting portion is located and the film layer where the light-emitting control signal line is located, the distance between the light-emitting control signal line and the first connecting portion is increased, and the dielectric constant of the parasitic capacitance in the overlapping portion is reduced, thereby reducing the parasitic capacitance, and further reducing the effect of the parasitic capacitance on the brightness of the light-emitting device, which is beneficial to improving the display effect of the display panel. By ensuring that the thickness of the insulating layer between the film layer where the first connecting portion is located and the film layer where the light-emitting control signal line is located is greater than 3 microns, the distance between the light-emitting control signal line and the first connecting portion is increased, thereby reducing the parasitic capacitance, and further reducing the effect of the parasitic capacitance on the brightness of the light-emitting device, which is beneficial to improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG1 is a schematic diagram of a circuit structure of a pixel circuit in the related art;

[0011] FIG2 is a timing diagram of a pixel circuit in the related art;

[0012] FIG3 is a schematic diagram of a layout structure of a pixel circuit in the related art;

[0013] FIG4 is a schematic diagram of a layout structure of an array substrate provided in an embodiment of the present application;

[0014] FIG5 is a cross-sectional view of FIG4 along the direction a0-a0';

[0015] FIG6 is a schematic diagram of a circuit structure of a pixel circuit provided in an embodiment of the present application;

[0016] FIG7 is a schematic diagram of a layout structure of another array substrate provided in an embodiment of the present application;

[0017] FIG8 is a cross-sectional view of FIG7 along the a1-a2 direction;

[0018] FIG9 is a schematic diagram of a layout structure of another array substrate provided in an embodiment of the present application;

[0019] FIG10 is a cross-sectional view taken along the b1-b2 direction in FIG4;

[0020] FIG11 is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present application;

[0021] FIG12 is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present application;

[0022] FIG13 is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present application;

[0023] FIG14 is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present application;

[0024] FIG15 is a cross-sectional view of FIG14 taken along the f1-f2 direction;

[0025] FIG16 is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present application;

[0026] FIG17 is another cross-sectional view along the a1-a2 direction of FIG7;

[0027] FIG18 is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present application;

[0028] FIG19 is a cross-sectional view of FIG18 taken along the k1-k2 direction;

[0029] FIG20 is a schematic diagram of the layout structure of the first conductive layer and the second active layer of the array substrate provided in an embodiment of the present application;

[0030] FIG21 is a schematic diagram of the layout structure of the second conductive layer of the array substrate provided in an embodiment of the present application;

[0031] FIG22 is a schematic diagram of the layout structure of the third conductive layer and the first active layer of the array substrate provided in an embodiment of the present application;

[0032] FIG23 is a schematic diagram of the layout structure of the fourth conductive layer of an array substrate provided in an embodiment of the present application;

[0033] FIG24 is a schematic diagram of the layout structure of the fourth conductive layer of another array substrate provided in an embodiment of the present application;

[0034] FIG25 is a schematic diagram of the layout structure of the fifth conductive layer of an array substrate provided in an embodiment of the present application;

[0035] FIG26 is a schematic diagram of the layout structure of the sixth conductive layer of the array substrate provided in an embodiment of the present application;

[0036] FIG27 is a schematic diagram of the layout structure of the shielding layer of the array substrate provided in an embodiment of the present application;

[0037] FIG28 is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present application;

[0038] FIG29 is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present application;

[0039] FIG30 is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present application;

[0040] FIG31 is a schematic diagram of a circuit structure of another pixel circuit provided in an embodiment of the present application;

[0041] FIG32 is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present application;

[0042] FIG33 is a schematic structural diagram of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0044] Figure 1 is a schematic diagram of the circuit structure of a pixel circuit in the related art. As shown in Figure 1, the pixel circuit includes a first transistor T1', a second transistor T2', a third transistor T3', a fourth transistor T4', a fifth transistor T5', a sixth transistor T6', a seventh transistor T7', an eighth transistor T8', and a first capacitor C1. Figure 2 is a timing diagram of a pixel circuit in the related art. As shown in Figure 2, the driving process of the pixel circuit includes an initialization phase t1, a threshold compensation and data writing phase t2, and a light-emitting phase t3. In the initialization stage t1, the second scan signal S2 on the second scan line Scan2 is at a low level, and the second scan signal S2 controls the seventh transistor T7' and the eighth transistor T8' to be turned on. The third scan signal S3 on the third scan line Scan3 is at a high level, and the third scan signal S3 controls the fourth transistor T4' to be turned on. The eighth transistor T8' transmits the first reset signal transmitted on the first reset signal line Vr1 to the source of the first transistor T1', thereby resetting the source of the first transistor T1'; the seventh transistor T7' transmits the second reset signal transmitted on the second reset signal line Vr2 to the anode of the light-emitting diode D1, thereby resetting the anode of the light-emitting diode D1; the fourth transistor T4' transmits the third reset signal transmitted on the third reset signal line Vr3 to the gate of the first transistor T1', thereby resetting the gate of the first transistor T1'. During the threshold compensation and data writing phase t2, the first scan signal S1 on the first scan line Scan1 is at a low level, and the first scan signal S1 controls the second transistor T2' to turn on. The fourth scan signal S4 on the fourth scan line Scan4 is at a high level, and the fourth scan signal S4 controls the third transistor T3' to turn on. The data voltage transmitted on the data line Data is transmitted to the gate of the first transistor T1' through the second transistor T2', the first transistor T1', and the third transistor T3'. The third transistor T3' captures the threshold voltage of the first transistor T1', thereby achieving threshold compensation and data writing for the first transistor T1'. During the light-emitting phase t3, when the enable signal E2 on the enable line E1 is at a low level, the fifth transistor T5' and the sixth transistor T6' are controlled to turn on. The fifth transistor T5', the first transistor T1', and the sixth transistor T6' form a drive current path, providing drive current to the light-emitting diode D1, causing the light-emitting diode D1 to emit light.

[0045] FIG3 is a schematic diagram of a layout structure of a pixel circuit in the related art. As shown in FIG3 , the source of the first transistor T1′ and the drain of the eighth transistor T8′ are electrically connected via a connection portion L1. There is an overlap between the enable line E1 and the connection portion L1, thereby forming a parasitic capacitor C2. During the light-emitting phase of the pixel circuit driving process, the parasitic capacitor C2 affects the source potential of the first transistor T1′, thereby affecting the voltage difference between the gate and source of the first transistor T1′, thereby affecting the driving current of the first transistor T1′, and further affecting the light-emitting effect of the light-emitting diode D1, so that the light-emitting diode D1 cannot emit light according to the preset brightness. In addition, an enable line E1 is connected to the fifth transistor T5′ and multiple sixth transistors T6′ in multiple pixel circuits located in a row, so that the voltage drop of the signal transmitted on the enable line E1 is different at different locations, thereby causing the potential at different locations on the enable line E1 to be different, resulting in different coupling potentials of the parasitic capacitor C2 to the first transistor T1′ in the pixel circuits at different locations. The magnitude of the high and low levels of the enable signal on the enable line E1 connected to the pixel circuits in different rows is related to the distance between the enable line E1 and the driver chip. For example, the greater the distance between the enable line E1 and the driver chip, the smaller the absolute values ​​of the positive high and negative low levels on the enable line E1. This results in differences in the potential of the enable line E1 connected to the pixel circuits in different rows, which in turn results in differences in the coupling potential of the parasitic capacitance C2 in the pixel circuits in different rows to the first transistor T1'. Therefore, the magnitude of the coupling potential corresponding to the pixel circuits at different positions will vary, that is, the degree of influence of the parasitic capacitance C2 in the pixel circuits at different positions on the source potential of the first transistor T1' will vary, resulting in different degrees of influence of the parasitic capacitance C2 in the pixel circuits at different positions on the drive current, and thus different effects of the parasitic capacitance C2 in the pixel circuits at different positions on the luminous brightness of the light-emitting diode D1, which reduces the display uniformity of the display panel. As shown in Figure 2, when the target display brightness is low, pulse width modulation (PWM) technology is used for dimming. That is, the brightness of the light-emitting diode D1 is controlled by controlling the duration of the light-emitting diode D1. The greater the number of pulses, the greater the voltage fluctuation on the enable line E1, and the greater the difference in the coupling of the parasitic capacitance C2 in the pixel circuit at different locations to the source potential of the first transistor T1'. In other words, the influence of the parasitic capacitance C2 in the pixel circuit at different locations on the drive current varies greatly, resulting in large differences in the brightness of the light-emitting diode D1 at different locations, which in turn affects the display uniformity of the display panel.

[0046] The present embodiment provides an array substrate. Figure 4 is a schematic diagram of the layout structure of an array substrate provided by the embodiment of the present application, Figure 5 is a cross-sectional view of Figure 4 along the a0-a0' direction, and Figure 6 is a schematic diagram of the circuit structure of a pixel circuit provided by the embodiment of the present application. Referring to Figures 4 to 6, the array substrate includes: a substrate 110 and a driving circuit layer located on the substrate 110, wherein the driving circuit layer is provided with a pixel circuit and a light-emitting control signal line EM, and the pixel circuit includes a driving transistor T1, a first initialization transistor T2 and a first connecting portion 101, wherein the first connecting portion 101 is connected between the first electrode of the driving transistor T1 and the first initialization transistor T2; the first connecting portion 101 is connected to the light-emitting control signal line EM. There is an overlapping portion 102 in the orthographic projection of the control signal line EM on the substrate; referring to Figure 4, a shielding portion 103 is also provided in the driving circuit layer, and the orthographic projection of the shielding portion 103 on the substrate 110 overlaps with the overlapping portion 102; the film layer where the shielding portion 103 is located is located between the film layer where the light-emitting control signal line EM is located and the film layer where the first connecting portion 101 is located; and / or, at least one organic insulating layer is provided between the film layer where the first connecting portion 101 is located and the film layer where the light-emitting control signal line EM is located; and / or, the thickness D of the insulating layer between the film layer where the first connecting portion 101 is located and the film layer where the light-emitting control signal line EM is located is greater than 3 microns.

[0047] The array substrate may include a plurality of pixel circuits, each of which may be connected to a light-emitting device OLED in the display panel. The pixel circuit may be a circuit composed of devices such as thin-film transistors and capacitors, and the pixel circuit is configured to provide a driving current to the light-emitting device OLED so that the light-emitting device OLED emits light in response to the driving current. The first electrode of the driving transistor T1 may be the source electrode of the driving transistor T1 or the drain electrode of the driving transistor T1. Optionally, the film layer where the light-emitting control signal line EM is located, the film layer where the shielding portion 103 is located, and the film layer where the first connecting portion 101 is located are stacked in sequence along the thickness direction Z of the substrate (for example, in a direction away from the substrate). The shielding portion 103 may include a conductive material such as a metal material or indium tin oxide (ITO).

[0048] In some embodiments, a shielding portion 103 is provided, the shielding portion 103 being located between the film layer where the light-emitting control signal line EM is located and the film layer where the first connecting portion 101 is located. The shielding portion 103 is located between the light-emitting control signal line EM and the first connecting portion 101, so that the shielding portion 103 shields the signal on the light-emitting control signal line EM, thereby eliminating or reducing the degree of coupling (e.g., the degree of potential reduction) between the parasitic capacitance generated by the light-emitting control signal line EM and the first connecting portion 101 at the overlapping portion 102 and the first electrode potential of the driving transistor T1. The coupling difference between the parasitic capacitance in different pixel circuits and the first electrode potential of the driving transistor T1 is also reduced. In this way, the degree of influence of the parasitic capacitance in the pixel circuits at different locations on the driving current is made equal or similar, thereby making the display brightness of different light-emitting devices OLED at the same grayscale tend to be consistent, which is beneficial to improving the display uniformity of the display panel and improving the display effect of the display panel.

[0049] In some embodiments, the film layer where the first connecting portion 101 is located and the film layer where the light-emission control signal line EM is located are stacked along the substrate thickness direction Z. By disposing at least one organic insulating layer between the film layer where the first connecting portion 101 is located and the film layer where the light-emission control signal line EM is located, and disposing at least one organic insulating layer between the first connecting portion 101 and the light-emission control signal line EM, and the orthographic projection of the at least one organic insulating layer on the substrate overlaps with the overlapping portion 102, the dielectric layer between the first connecting portion 101 and the light-emission control signal line EM is thicker, and the distance between the first connecting portion 101 and the light-emission control signal line EM (the distance along the substrate thickness direction Z) is longer, thereby reducing the parasitic capacitance of the overlapping portion 102. Furthermore, the organic insulating layer can reduce the dielectric constant of the parasitic capacitance, thereby further reducing the parasitic capacitance of the overlapping portion 102.

[0050] In some embodiments, after at least one organic insulating layer is provided between the film layer where the first connecting portion 101 is located and the film layer where the light-emitting control signal line EM is located, a shielding portion 103 may be further provided to further reduce the influence of the parasitic capacitance of the overlapping portion 102 on the potential of the first electrode of the driving transistor T1, reduce the influence of the parasitic capacitance on the driving current of the driving transistor T1, and further reduce the influence of the parasitic capacitance on the luminous brightness of the light-emitting device OLED, which is beneficial to improving the display effect of the display panel.

[0051] In some embodiments, the thickness D of the insulating layer between the film layer where the first connection portion 101 is located and the film layer where the light-emitting control signal line EM is located (the thickness along the thickness direction Z of the substrate 110, the insulating layer between the film layer where the first connection portion 101 is located and the film layer where the light-emitting control signal line EM is located can be a single-layer insulating layer, D can be the thickness of the single-layer insulating layer, or the insulating layer between the film layer where the first connection portion 101 is located and the film layer where the light-emitting control signal line EM is located can be a multi-layer insulating layer, D can be the sum of the thicknesses of the multi-layer insulating layers) is greater than 3 microns, the film layer where the first connection portion 101 is located and the light-emitting control signal line EM are located The orthographic projection of the insulating layer between the film layers where the light control signal line EM is located on the substrate overlaps with the overlapping portion 102, so that the thickness of the dielectric layer between the first connecting portion 101 and the light control signal line EM is relatively large, greater than 3 microns, which is equivalent to the facing distance between the first connecting portion 101 and the light control signal line EM at the overlapping portion being greater than 3 microns. The facing distance between the first connecting portion 101 and the light control signal line EM (the distance along the thickness direction Z of the substrate) is large, which can reduce the parasitic capacitance of the overlapping portion 102, for example, to less than 0.85fF, 1pF=1000fF.

[0052] The technical solution of this embodiment is to set a shielding part, and the orthographic projection of the shielding part on the substrate overlaps with the overlapping part. The film layer where the shielding part is located is located between the film layer where the light-emitting control signal line is located and the film layer where the first connecting part is located, so that the shielding part forms a shielding effect on the signal transmitted on the light-emitting control signal line, eliminates or reduces the coupling degree (potential lowering degree) of the parasitic capacitance generated by the light-emitting control signal line and the first connecting part in the overlapping part to the first pole potential of the driving transistor, and the coupling difference of the parasitic capacitance in the pixel circuits at different positions to the first pole potential of the driving transistor will also be reduced, so that the influence degree of the parasitic capacitance on the driving current of the pixel circuits at different positions is the same or close, thereby making the display brightness of the light-emitting devices at different positions tend to be consistent under the same gray scale, which is beneficial to improving the display uniformity of the display panel and improving the display effect of the display panel. By providing at least one organic insulating layer between the film layer where the first connecting portion is located and the film layer where the light-emitting control signal line is located, the distance between the light-emitting control signal line and the first connecting portion is increased, and the dielectric constant of the parasitic capacitance of the overlapping portion is reduced, thereby reducing the parasitic capacitance, and further reducing the effect of the parasitic capacitance on the luminous brightness of the light-emitting device, which is beneficial to improving the display effect of the display panel. By increasing the thickness of the insulating layer between the film layer where the first connecting portion is located and the film layer where the light-emitting control signal line is located to greater than 3 microns, the distance between the light-emitting control signal line and the first connecting portion is increased, thereby reducing the parasitic capacitance, and further reducing the effect of the parasitic capacitance on the luminous brightness of the light-emitting device, which is beneficial to improving the display effect of the display panel. Based on the above technical solution, optionally, the shielding portion 103 is connected to a DC potential.

[0053] If the DC potential is a fixed signal, then when the potential of the light-emitting control signal line EM changes, the potential of the shielding portion 103 does not change. Therefore, the amount of potential change on the first connecting portion 101 affected by the potential change of the light-emitting control signal line EM is reduced or even zero. This reduces the coupling degree between the light-emitting control signal line EM and the potential of the first electrode of the driving transistor T1. This reduces the coupling degree between the potential change of the light-emitting control signal line EM and the potential of the first electrode of the driving transistor T1. This also reduces the difference in coupling between the parasitic capacitance in pixel circuits at different locations and the potential of the first electrode of the driving transistor. This reduces the effect of the parasitic capacitance in pixel circuits at different locations on the driving current to the same or similar degree. This further improves the display uniformity of the light-emitting devices OLED at different locations at the same grayscale. The DC potential can be a DC potential connected to the pixel circuits, scanning circuits, etc. on the array substrate. This is equivalent to the shielding portion being electrically connected to the pixel circuits, scanning circuits, etc. on the array substrate and connected to the same DC potential, eliminating the need for an additional power supply. The DC potential can also be obtained by providing additional power and signal lines.

[0054] Optionally, a first power line and / or an initialization signal line is further provided in the driving circuit layer, and the shielding portion 103 is electrically connected to the first power line or the initialization signal line.

[0055] The first power line transmits a first power supply voltage, which can be either a high-level voltage or a low-level voltage. Therefore, when the shielding portion 103 is connected to the first power line, the signal transmitted by the shielding portion 103 is a DC signal, i.e., a signal with a fixed potential, thereby reducing the coupling between the light-emission control signal line EM and the potential of the first electrode of the driving transistor T1. The initialization signal line transmits an initialization signal, which is a fixed-potential signal. Therefore, when the shielding portion 103 is connected to the initialization signal line, the signal transmitted by the shielding portion 103 is a fixed-potential signal, thereby also reducing the coupling between the light-emission control signal line EM and the potential of the first electrode of the driving transistor T1. A DC signal line connected to the shielding portion 103 can be selected as close as possible, such as the first power line or the initialization signal line, to reduce wiring complexity.

[0056] Based on the above-mentioned technical solutions, the following describes the arrangement in which at least one organic insulating layer is provided between the film layer where the first connecting portion 101 is located and the film layer where the light-emitting control signal line is located, but this does not serve as a limitation to the present application.

[0057] Optionally, the driving circuit layer includes a first conductive layer M1 , a second conductive layer M2 , a third conductive layer M3 , a fourth conductive layer M4 and a fifth conductive layer M5 that are stacked; optionally, the light emitting control signal line EM is provided in the first conductive layer M1 .

[0058] Optionally, the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, the fourth conductive layer M4, and the fifth conductive layer M5 are stacked sequentially in a direction away from the substrate. Optionally, the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, the fourth conductive layer M4, and the fifth conductive layer M5 may include one or more of a metal layer, an indium tin oxide (ITO) layer, and the like.

[0059] Optionally, the first connection portion 101 is disposed on the fourth conductive layer M4 or on a side of the fourth conductive layer M4 away from the substrate 110. Optionally, when the shielding portion 103 is disposed in the driving circuit layer, the first connection portion 101 is disposed on the fourth conductive layer M4 or on a side of the fourth conductive layer M4 away from the substrate 110. Optionally, when at least one organic insulating layer is disposed between the film layer where the first connection portion 101 is located and the film layer where the light-emitting control signal line is located, the first connection portion 101 is disposed on a side of the fourth conductive layer M4 away from the substrate 110.

[0060] In some embodiments, FIG7 is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present application, and FIG8 is a cross-sectional view of FIG7 along the a1-a2 direction. Optionally, referring to FIG7 and FIG8 , the first connection portion 101 is optionally provided on a side of the fourth conductive layer M4 away from the substrate 110. In this way, the distance between the first connection portion 101 and the light-emitting control signal line EM is large, which helps to reduce the parasitic capacitance of the overlapping portion 102 between the first connection portion 101 and the light-emitting control signal line EM. In addition, the first connection portion 101 is provided on a side of the fourth conductive layer M4 away from the substrate 110 to facilitate the provision of an organic insulating layer, which can be provided between two of the second conductive layer M2, the third conductive layer M3, the fourth conductive layer M4, and the fifth conductive layer M5. Organic insulating layers may also be provided between the second conductive layer M2 and the third conductive layer M3, between the third conductive layer M3 and the fourth conductive layer M4, and between the fourth conductive layer M4 and the fifth conductive layer M5, thereby greatly reducing the parasitic capacitance of the overlapping portion 102, which is beneficial to reducing the influence of the parasitic capacitance corresponding to the overlapping portion 102 on the display effect of the display panel.

[0061] 7 and 8 illustrate the case where the first connection portion 101 is located in the fifth conductive layer M5, but this is not intended to be limiting. FIG8 illustrates the case where an organic insulating layer (a first organic planarization layer PLN1, for example, located between the fourth conductive layer M4 and the fifth conductive layer M5) is provided, but this is not intended to be limiting.

[0062] Optionally, the pixel circuit further includes a data write transistor T3. As shown in FIG8 , a first electrode T31 and a second electrode T32 of the data write transistor T3 are provided on the fourth conductive layer M4, and a gate T33 of the data write transistor T3 is provided on the first conductive layer M1. The first electrode T31 of the data write transistor T3 serves as the source of the data write transistor T3, and the second electrode T32 of the data write transistor T3 serves as the drain of the data write transistor T3. Alternatively, the first electrode T31 of the data write transistor T3 serves as the drain of the data write transistor T3, and the second electrode T32 of the data write transistor T3 serves as the source of the data write transistor T3.

[0063] Optionally, referring to FIG. 6 and FIG. 8 , the pixel circuit includes a storage capacitor Cst, and a first electrode C01 of the storage capacitor Cst is disposed on the second conductive layer M2 .

[0064] Optionally, the pixel circuit also includes a switching tube, which is connected to the gate of the driving transistor T1, and the first gate G1 of the switching tube is set on the third conductive layer M3; the fifth conductive layer M5 is provided with a first power line VDD, and the first power line VDD is set to provide a first power supply voltage for the pixel circuit.

[0065] The switch tube can be an N-type transistor. This reduces leakage current, resulting in minimal changes in the gate potential of the driver transistor T1. This helps maintain the gate potential of the driver transistor T1, thereby ensuring a more stable drive current generated by the driver transistor T1 and, in turn, a more stable luminous brightness of the light-emitting device OLED. The first gate of the switch tube can be, for example, a top gate. The first gate of the switch tube is disposed on the third conductive layer M3. The third conductive layer M3 can be made of nano-cesium tungsten oxide (GATO) material.

[0066] Exemplarily, referring to Figure 6, the switch tube includes a threshold compensation transistor T4 and / or a third initialization transistor T5, the threshold compensation transistor T4 and the third initialization transistor T5 are connected to the gate of the driving transistor T1, and the threshold compensation transistor T4 and the third initialization transistor T5 can be N-type transistors.

[0067] Optionally, referring to FIG6 , a first terminal of the light-emitting device OLED is connected to the pixel circuit, and a second terminal of the light-emitting device OLED is connected to the second power line VSS. The first terminal of the light-emitting device OLED serves as an anode, and the second terminal of the light-emitting device OLED serves as a cathode; alternatively, the first terminal of the light-emitting device OLED serves as a cathode, and the second terminal of the light-emitting device OLED serves as an anode.

[0068] Optionally, as shown in FIG8 , the first electrode T51 and the second electrode T52 of the third initialization transistor T5 are located in the fourth conductive layer M4, and the first gate G1 (top gate) of the third initialization transistor T5 is located in the third conductive layer M3. The third initialization transistor T5 may be provided with a single gate or a dual-gate structure. Optionally, the second gate G2 (bottom gate) of the third initialization transistor T5 is located in the second conductive layer M2, and the first gate G1 and the second gate G2 of the third initialization transistor T5 are connected together and receive the same signal, or the first gate G1 and the second gate G2 of the third initialization transistor T5 are insulated and receive different signals. The first electrode T51 of the third initialization transistor T5 is the source of the third initialization transistor T5, and the second electrode T52 of the third initialization transistor T5 is the drain of the third initialization transistor T5; alternatively, the first electrode T51 of the third initialization transistor T5 is the drain of the third initialization transistor T5, and the second electrode T52 of the third initialization transistor T5 is the source of the third initialization transistor T5. The active portion of the third initialization transistor T5 is located between the first gate G1 and the second gate G2 of the third initialization transistor T5.

[0069] In some embodiments, as shown in Figures 7 and 8 , the first connecting portion 101 is optionally provided on the fifth conductive layer M5. An organic insulating layer is provided between the fourth conductive layer M4 and the fifth conductive layer M5. Alternatively, an inorganic insulating layer is provided between any two adjacent layers of the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, and the fourth conductive layer M4. This further increases the distance between the first connecting portion 101 and the light-emission control signal line EM, thereby further reducing the parasitic capacitance of the overlapping portion 102 between the first connecting portion 101 and the light-emission control signal line EM.

[0070] Based on the above-mentioned multiple technical solutions, optionally, referring to FIG4 , the overlapping portion 102 is located within the orthographic projection of the shielding portion 103 on the substrate 110. This ensures that the orthographic projection of the shielding portion 103 on the substrate 110 completely covers the overlapping portion 102, achieving a good shielding effect. Furthermore, the orthographic projection of the shielding portion 103 on the substrate 110 can also cover the portion where the orthographic projection of the first connecting portion 101 on the substrate 110 does not overlap with the orthographic projection of the light-emitting control signal line EM on the substrate 110. This can shield a portion of the lateral capacitance between the first connecting portion 101 and the light-emitting control signal line EM, thereby better shielding the parasitic capacitance and further reducing the impact of the parasitic capacitance on the potential of the first electrode of the driving transistor T1.

[0071] As an implementation scheme of this embodiment, based on the above-mentioned multiple implementation schemes, the setting of the shielding part is described below, but it does not serve as a limitation to this application.

[0072] In some embodiments, Figure 9 is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present application, and Figure 10 is a cross-sectional view of Figure 4 along the b1-b2 direction. Optionally, referring to Figures 6, 9 and 10, the pixel circuit also includes a second initialization transistor T6; the driving circuit layer is also provided with a first initialization signal line Vref1 and a second initialization signal line Vref2, the first initialization transistor T2 is connected between the first initialization signal line Vref1 and the first electrode of the driving transistor T1, and the second initialization transistor T6 is connected between the second initialization signal line Vref2 and the first end of the light-emitting device OLED; the shielding portion 103 is electrically connected to the first initialization signal line Vref1 or the second initialization signal line Vref2.

[0073] Figures 4 and 10 illustrate the connection between the shielding portion 103 and the first initialization signal line Vref1. The shielding portion 103 and the first initialization signal line Vref1 (extending along the first direction X) can be arranged in the same layer. Optionally, the shielding portion 103 is arranged in the third conductive layer M3. Figure 9 illustrates the connection between the shielding portion 103 and the second initialization signal line Vref2. As shown in Figure 9, the shielding portion 103 is connected to the second initialization signal line Vref2 through a via and a second connecting portion in a conductive layer (e.g., a fourth conductive layer) on the side of the shielding portion 103 away from the substrate. The shielding portion 103 and the second initialization signal line Vref2 (extending along the first direction) can be arranged in the same layer. Optionally, the shielding portion 103 is arranged in the third conductive layer M3. Multiple structures arranged in the same layer can be obtained by patterning the same film layer, thereby simplifying the process. The materials of the multiple structures arranged in the same layer can be the same and can be prepared simultaneously by the same process. The shielding portions 103 of pixel circuits at different positions can be connected to different signal lines or the same signal line.

[0074] The aforementioned initialization signal lines include a first initialization signal line Vref1 and a second initialization signal line Vref2. The signals transmitted on the first initialization signal line Vref1 and the second initialization signal line Vref2 are DC signals, i.e., signals with a fixed potential. Therefore, by electrically connecting the shielding portion 103 to the first initialization signal line Vref1 and / or the second initialization signal line Vref2, the potential on the shielding portion 103 can be kept constant, thereby reducing the degree of coupling between the light-emitting control signal line EM and the potential of the first electrode of the driving transistor T1. This also reduces the difference in coupling between the parasitic capacitance of pixel circuits at different locations and the potential of the first electrode of the driving transistor. This, in turn, makes the luminous brightness of different light-emitting devices OLED at the same grayscale similar, which is beneficial for improving the display uniformity of the display panel. The shielding portion 103 is relatively close to the first initialization signal line Vref1 and / or the second initialization signal line Vref2, thereby facilitating wiring connections.

[0075] Optionally, the gate of the first initialization transistor T2 and the gate of the second initialization transistor T6 are electrically connected to the same scan signal line. In this way, the first initialization transistor T2 and the second initialization transistor T6 can be controlled to be turned on simultaneously, thereby simultaneously initializing the first electrode of the driving transistor T1 and the light-emitting device OLED, facilitating control; and the number of scan signal lines is reduced, facilitating routing design.

[0076] Optionally, the driving circuit layer further includes a third conductive layer M3; the pixel circuit further includes a switch tube; the switch tube is connected to the gate of the driving transistor T1; and the third conductive layer M3 is provided with a first gate of the switch tube.

[0077] Optionally, the first initialization signal line Vref1 and / or the second initialization signal line Vref2 are provided in the third conductive layer M3. In this way, when the first connection portion 101 is provided in the fourth conductive layer M4 or provided on the side of the fourth conductive layer M4 away from the substrate 110 (for example, provided in the fifth conductive layer M5), the shielding portion 103 can shield the first connection portion 101 from the light-emitting control signal line EM, thereby reducing the degree of coupling of the light-emitting control signal line EM with the potential of the first electrode of the driving transistor T1. The coupling difference between the parasitic capacitance in the pixel circuits at different positions and the potential of the first electrode of the driving transistor is also reduced, which helps to reduce the influence of the parasitic capacitance on the display effect of the display panel.

[0078] Optionally, as shown in FIG10 , the gate T11 of the driving transistor T1 and the light-emission control signal line EM are disposed on the first conductive layer M1, the first plate C01 of the storage capacitor Cst is disposed on the second conductive layer M2, the shielding portion 103 is disposed on the third conductive layer M3, and the first connecting portion 101 and the first electrode T21 of the first initialization transistor T2 (the electrode connected to the first electrode of the driving transistor T1) are disposed on the fourth conductive layer M4. This facilitates connecting the shielding portion 103 to the first initialization signal line Vref1 located on the third conductive layer M3, allowing the shielding portion 103 to receive a DC signal, thereby more effectively shielding the first connecting portion 101 and the light-emission control signal line EM.

[0079] Optionally, as shown in FIG10 , the driving circuit layer further includes a first buffer layer B1, a first gate insulating layer GI1, a capacitor insulating layer CI, a second buffer layer B2, a second gate insulating layer, a first organic planarization layer PLN1, and a second organic planarization layer PLN2. The first buffer layer B1 is located between the substrate 110 and the first conductive layer M1. The first buffer layer B1 has an isolation function, which can prevent damage to the substrate 110 during subsequent film etching and improve the adhesion of the first conductive layer M1. The first gate insulating layer GI1 is located between the first buffer layer B1 and the first conductive layer M1 and is used to isolate the gate on the first conductive layer M1 (for example, the first electrode T11 of the driving transistor T1). The capacitor insulating layer CI is located between the first conductive layer M1 and the second conductive layer M2 and is used to isolate the first electrode C01 of the storage capacitor Cst on the second conductive layer M2, preventing the signal on the first conductive layer M1 from interfering with the potential on the first electrode C01. The second buffer layer B2 is located between the second conductive layer M2 and the third conductive layer M3 and has buffering, protection, and insulation functions. The second gate insulating layer is located between the third conductive layer M3 and the first active layer, and the interlayer insulating layer ILD is located between the third conductive layer M3 and the fourth conductive layer M4. The second gate insulating layer is used to isolate the gate on the third conductive layer M3 (for example, the top gate of the switching transistor described above) to achieve an insulating effect. The first organic planarization layer PLN1 is located on the side of the third conductive layer M3 away from the substrate 110, and the second planarization layer PLN2 is located on the side of the first organic planarization layer PLN1 away from the substrate 110.

[0080] Figure 11 is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present application. Optionally, as shown in Figure 11, the orthographic projection of the first initialization signal line Vref1 on the substrate 110 is located between the orthographic projection of the second initialization signal line Vref2 on the substrate 110 and the orthographic projection of the shielding portion 103 on the substrate 110; the orthographic projection of the first initialization signal line Vref1 on the substrate 110 is located between the orthographic projection of the second initialization signal line Vref2 on the substrate 110 and the orthographic projection of the light-emitting control signal line EM on the substrate 110.

[0081] Optionally, as shown in FIG11 , the first initialization signal line Vref1, the second initialization signal line Vref2, and the light-emission control signal line EM extend in a first direction X (which may be an extending trend or a substantially extending direction) and are arranged along a second direction Y, with the first direction X intersecting the second direction Y. In other words, the first initialization signal line Vref1 and the light-emission control signal line EM do not overlap, and the second initialization signal line Vref2 and the light-emission control signal line EM do not overlap.

[0082] Optionally, as shown in Figures 9 and 11, the second initialization signal line Vref2 is electrically connected to the shielding portion 103 via the second connecting portion 104, and the second connecting portion 104 is arranged to be insulated from and cross-connected with the first initialization signal line Vref1. Optionally, as shown in Figure 11, the film layer where the second connecting portion 104 is located is located on the side of the film layer where the first initialization signal line Vref1 is located away from the substrate 110. Optionally, as shown in Figure 11, the first connecting portion 101 and the second connecting portion 104 are arranged in the same layer. In this way, it is convenient to electrically connect the second initialization signal line Vref2 to the shielding portion 103 without connecting the first initialization signal line Vref1 and the second initialization signal line Vref2, so that different initialization signals can be set for the first initialization signal line Vref1 and the second initialization signal line Vref2 as needed.

[0083] In some embodiments, Figure 12 is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present application. Optionally, referring to Figures 6 and 12, the pixel circuit also includes a storage capacitor Cst, and the first electrode C01 of the storage capacitor Cst is connected to the first power line VDD; the first electrode C01 is electrically connected to the shielding portion 103 as an integrated structure and is arranged on the same layer.

[0084] The first plate C01 of the storage capacitor Cst is connected to a DC signal, so that the shielding portion 103 is connected to a DC signal, that is, a signal with a fixed potential. This can prevent the potential on the shielding portion 103 from changing, thereby reducing the degree of coupling of the light-emitting control signal line EM to the potential of the first electrode of the driving transistor T1. The coupling difference between the parasitic capacitance in the pixel circuit at different positions and the potential of the first electrode of the driving transistor is also reduced, thereby making the luminous brightness of different light-emitting devices OLED at the same grayscale close, which is beneficial to improving the display uniformity of the display panel.

[0085] Optionally, with reference to FIG12 , the driving circuit layer further includes a second conductive layer M2, and the second conductive layer M2 is provided with a first plate C01 of a storage capacitor Cst. Optionally, the second plate of the storage capacitor Cst is reused as the gate of the driving transistor T1. In this way, when the first connecting portion 101 is provided on the fourth conductive layer M4 or on the side of the fourth conductive layer M4 away from the substrate 110 (for example, provided on the fifth conductive layer M5), the shielding portion 103 can shield the first connecting portion 101 from the light-emitting control signal line EM, thereby reducing the degree of coupling of the light-emitting control signal line EM to the potential of the first pole of the driving transistor T1. The coupling difference of the parasitic capacitance in the pixel circuits at different positions to the first pole potential of the driving transistor will also be reduced, which is beneficial to reducing the influence of the parasitic capacitance on the display effect of the display panel.

[0086] In some embodiments, FIG13 is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present application. Optionally, referring to FIG13 , a first power line VDD is provided in the driving circuit layer, and the first power line VDD includes a first sub-line L1 and a second sub-line L2 that are electrically connected. The pixel circuit further includes a first emission control transistor T7, which is electrically connected to the second sub-line L2. The second sub-line L2 is electrically connected to the shielding portion 103. Optionally, the shielding portion 103 extends along a first direction, the first sub-line L1 extends along a first direction X, and the extension direction of the second sub-line L2 intersects the first direction X. The first sub-line L1 and the second sub-line L2 are provided in the same layer. Optionally, the first emission control transistor T7 is connected between the first electrode of the driving transistor T1 and the second sub-line L2, and the gate of the first emission control transistor T7 is electrically connected to the emission control signal line EM. This allows the shielding portion 103 to be connected to a DC potential, thereby reducing the degree of coupling of the parasitic capacitance to the potential of the first electrode of the first transistor T1.

[0087] Optionally, the driving circuit layer further includes a fourth conductive layer M4 and a fifth conductive layer M5, the first connecting portion 101 is disposed on the fifth conductive layer M5, and the shielding portion 103 is disposed on the fourth conductive layer M4. In this manner, the film layer where the shielding portion 103 is located is located between the film layer where the first connecting portion 101 is located and the film layer where the light-emission control signal line EM is located, thereby shielding the signal transmitted on the light-emission control signal line EM, thereby reducing the degree of coupling between the light-emission control signal line EM and the potential of the first electrode of the driving transistor T1. This also reduces the difference in coupling between the parasitic capacitance in pixel circuits at different locations and the potential of the first electrode of the driving transistor, thereby facilitating the reduction in the impact of the parasitic capacitance on the display quality of the display panel.

[0088] The first direction X may be a row direction of the array substrate, ie, a row direction in which the pixel circuit array is arranged. The first sub-line L1 may be electrically connected to the first electrode C01 of the storage capacitor Cst.

[0089] Optionally, as shown in FIG. 13 , the first sub-line L1 and the second sub-line L2 are provided in the fifth conductive layer M5 ; the second sub-line L2 is electrically connected to the shielding portion 103 through a via hole.

[0090] By electrically connecting the second sub-line L2 of the first power line VDD to the shielding portion 103, a DC signal is connected to the shielding portion 103, so that no sudden change in potential occurs on the shielding portion 103. This is beneficial for reducing the degree of coupling of the light-emitting control signal line EM to the potential of the first electrode of the driving transistor T1. The coupling difference between the parasitic capacitance in the pixel circuit at different positions and the potential of the first electrode of the driving transistor is also reduced, thereby making the luminous brightness of different light-emitting devices OLED at the same gray scale close, which is beneficial for further improving the display uniformity of the display panel.

[0091] Optionally, as shown in FIG13 , among three adjacent pixel circuits along a first direction X, the shielding portion 103 in the middle pixel circuit is connected to the shielding portion 103 in the pixel circuit on one side; the distance (which may be the distance along the first direction X) between the first connecting portion 101 in the middle pixel circuit and the first connecting portion 101 in the pixel circuit on one side is smaller than the distance (which may be the distance along the first direction X) between the first connecting portion 101 in the middle pixel circuit and the first connecting portion 101 in the pixel circuit on the other side. In other words, the shielding portions 103 in two adjacent pixel circuits in the first direction X are connected, and the first connecting portions 101 in the two adjacent pixel circuits are arranged adjacent to each other. This is equivalent to one shielding portion 103 corresponding to two adjacent pixel circuits in the first direction. The first direction X may be the row direction. The second direction Y may be the column direction. FIG13 exemplarily illustrates two rows and four columns of pixel circuits, where, among the four pixel circuits in the same row, the distance between the first connecting portions 101 in the two left pixel circuits is smaller than the distance between the first connecting portions 101 in the two center pixel circuits. Optionally, two adjacent pixel circuits in the first direction are arranged in mirror symmetry. In this way, the number of shielding parts 103 can be reduced, and there is no need to prepare a shielding part 103 for each pixel circuit, which makes wiring simple and convenient.

[0092] Optionally, as shown in Figures 4, 9 and 13, one shielding portion 103 corresponds to one pixel circuit. A plurality of pixel circuits are each provided with a shielding portion 103, and the shielding portions 103 in two adjacent pixel circuits are provided at intervals.

[0093] Based on the above-mentioned multiple technical solutions, the parasitic capacitance corresponding to the overlapping portion 102 of the orthographic projection of the first connecting portion 101 on the substrate and the orthographic projection of the light-emitting control signal line EM on the substrate is an orthogonal capacitance. The portion where the first connecting portion 101 and the light-emitting control signal line EM do not overlap may generate lateral capacitance. In order to further reduce the influence of the parasitic capacitance on the potential of the first electrode of the driving transistor T1, the strategy for reducing the lateral capacitance is described below, but it does not serve as a limitation of this application.

[0094] Optionally, referring to Figure 4, the light-emitting control signal line EM includes a main portion EM1 extending along a first direction X and an extension portion EM2 extending in a third direction H, and the first direction X intersects the third direction H; the orthographic projection of the shielding portion 103 on the substrate 110 at least partially covers the orthographic projection of the extension portion EM2 on the substrate 110.

[0095] If the third direction H is oblique relative to the first direction X, an angle exists between the main portion EM1 and the extension portion EM2. If the first connection portion 101 is close to the angle, lateral capacitance is likely to be generated at the angle. By ensuring that the orthographic projection of the shielding portion 103 on the substrate 110 at least partially covers the orthographic projection of the extension portion EM2 on the substrate 110, the shielding portion 103 can be ensured to cover the angle between the main portion EM1 and the extension portion EM2. This allows the shielding portion 103 to shield the signal on the light-emitting control signal line EM, thereby reducing the lateral capacitance at the angle. This further reduces the effect of parasitic capacitance on the potential of the first connection portion 101, thereby reducing the effect of parasitic capacitance on the potential of the first electrode of the driving transistor T1, and further reducing the effect of parasitic capacitance on the drive current generated by the driving transistor T1. This reduces the effect of parasitic capacitance on the luminous brightness of the light-emitting device OLED, thereby further improving the display effect of the display panel.

[0096] Figure 14 is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present application, and Figure 15 is a cross-sectional view of Figure 14 along the f1-f2 direction. Optionally, referring to Figures 14 and 15, the array substrate further includes a shielding layer M0, which is located between the substrate 110 and the driving circuit layer; there is a gap 120 between the orthographic projection of the first connecting portion 101 on the substrate 110 and the orthographic projection of the light-emitting control signal line EM on the substrate 110; the orthographic projection of the shielding layer M0 on the substrate 110 at least partially overlaps with the gap 120.

[0097] The first connection portion 101 and the light-emitting control signal line EM are coupled at the gap 120 to generate lateral capacitance. The orthographic projection of the shielding layer M0 on the substrate 110 at least partially overlaps with the gap 120. Although the shielding layer M0 is not located between the film layer where the first connection portion 101 is located and the film layer where the light-emitting control signal line EM is located, the electric field lines formed by the lateral capacitance are multi-directional. Therefore, the shielding layer M0 can shield some of the electric field lines, thereby achieving the effect of reducing the lateral capacitance, which is beneficial for further reducing the parasitic capacitance generated by the coupling between the light-emitting control signal line EM and the first connection portion 101, thereby reducing the impact of the parasitic capacitance on the potential of the first electrode of the driving transistor T1.

[0098] Optionally, at least a portion of the shielding layer M0 is connected to a DC potential.

[0099] Optionally, the shielding layer M0 is electrically connected to the first power line VDD. Therefore, when a DC signal is applied to the shielding layer M0, the potential on the shielding layer M0 does not fluctuate, allowing the shielding layer M0 to provide effective shielding, thereby reducing the lateral capacitance between the first connection portion 101 and the light-emission control signal line EM. Furthermore, by applying a stable voltage to the shielding layer M0, it can provide electrostatic shielding. The shielding layer M0 may include a metal layer, for example.

[0100] Optionally, the orthographic projection of the shielding layer M0 on the substrate 110 overlaps at least partially with the active portion of the channel region of the driving transistor T1. In this manner, the shielding layer M0 can provide an electrostatic shield for the driving transistor T1, preventing static electricity from affecting the characteristics of the driving transistor T1 and preventing variations in the threshold voltage of the driving transistor T1, thereby ensuring the stability of the driving current of the driving transistor T1. Furthermore, static charge can be prevented from damaging the gate of the driving transistor T1, thereby protecting the driving transistor T1.

[0101] Optionally, the shielding layer M0 is an electrostatic shielding layer and / or a light-shielding layer.

[0102] When the shielding layer M0 is an electrostatic shielding layer, it can prevent static electricity from affecting the characteristics of the driving transistor T1 and thus the display effect of the display panel. When the shielding layer M0 is a light shielding layer, it can reduce the impact of ambient light on the characteristics of the driving transistor T1, thereby ensuring the stability of the driving current of the driving transistor T1 and improving the display effect of the display panel.

[0103] Based on the above-mentioned multiple technical solutions, optionally, referring to FIG4 , a first initialization signal line Vref1 is further provided in the driving circuit layer; a first initialization transistor T2 is connected between the first initialization signal line Vref1 and the first electrode of the driving transistor T1; the first initialization signal line Vref1 and the light-emitting control signal line EM extend in a first direction X (or extend in a trend) and are arranged along a second direction Y; the orthographic projection of the first initialization signal line Vref1 on the substrate 110 and the orthographic projection of the light-emitting control signal line EM on the substrate 110 are separated and do not overlap. In other words, the position of the original first initialization signal line Vref1 remains unchanged, and the first initialization signal line Vref1 is not moved to serve as the shielding portion 103. When the shielding portion 103 is connected to the first initialization signal line Vref1, the shielding portion 103 and the first initialization signal line Vref1 can be a whole or can be connected together as separate structures, which is not limited here.

[0104] Optionally, referring to FIG. 4 , shielding portion 103 and first initialization signal line Vref1 are electrically connected to form an integral structure and are disposed on the same layer. Shielding portion 103 is connected to one side of two opposing sides of first initialization signal line Vref1 along a second direction Y, where the first direction X and the second direction Y intersect, and may be, for example, perpendicular. In other words, shielding portion 103 may be a portion of the first initialization signal line Vref1 extending from one side of two opposing sides in the second direction Y, i.e., extending toward the overlapping portion 102. This ensures that the orthographic projection of shielding portion 103 on substrate 110 overlaps with overlapping portion 102, achieving a good shielding effect and effectively reducing the impact of parasitic capacitance corresponding to overlapping portion 102 on the potential of the first electrode of driving transistor T1.

[0105] Optionally, Figure 16 is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present application. Referring to Figure 16, the driving circuit layer also includes a first active layer 130, a third conductive layer M3, a second active layer 140 and a first conductive layer M1. The active part of the driving transistor T1 is located in the second active layer 140, the gate of the driving transistor T1 is located in the first conductive layer M1, and the first initialization signal line Vref1 is located in the third conductive layer M3 or on the side of the third conductive layer M3 away from the substrate 110.

[0106] Optionally, the second active layer 140 , the first conductive layer M1 , the first active layer 130 and the third conductive layer M3 are stacked in sequence in a direction away from the substrate 110 .

[0107] Optionally, the pixel circuit further includes a threshold compensation transistor T4, which is connected between the gate and the second electrode of the driving transistor T1, with an active portion of the threshold compensation transistor T4 located in the first active layer 130 and a gate of the threshold compensation transistor T4 located in the third conductive layer M3. Furthermore, the pixel circuit further includes a third initialization transistor T5, which is electrically connected to the gate of the driving transistor T1, with an active portion of the third initialization transistor T5 located in the first active layer 130 and a gate of the third initialization transistor T5 located in the third conductive layer M3. Optionally, the second active layer 140 includes polysilicon, and the first active layer 130 includes a metal oxide.

[0108] The second active layer 140 includes polysilicon, such as PSi. The driving transistor T1 may be a P-type transistor, and the active portion of the driving transistor T1 is located in the second active layer 140. The gate of the driving transistor T1 is located in the first conductive layer M1, conveniently overlapping with the active portion of the second active layer 140. The threshold compensation transistor T4 and the third initialization transistor T5 may be N-type transistors, and the gates of the threshold compensation transistor T4 and the third initialization transistor T5 are located in the third conductive layer M3, conveniently overlapping with the active portion of the first active layer 130.

[0109] Optionally, the shielding layer M0, the first buffer layer B1, the second active layer 140, the first gate insulation layer GI1, the first conductive layer M1, the capacitor insulation layer CI, the second conductive layer M2, the second buffer layer B2, the first active layer 130, the second gate insulation layer GI2, the third conductive layer M3, the interlayer insulating layer ILD, the fourth conductive layer M4, the first organic planarization layer PLN1, the fifth conductive layer M5, the second organic planarization layer PLN2 and the sixth conductive layer M6 are stacked in sequence in a direction away from the substrate 110.

[0110] Optionally, the pixel circuit further includes a first light-emitting control transistor T7, which is connected between the first electrode of the driving transistor T1 and the first power line VDD; the gate of the first light-emitting control transistor T7 is electrically connected to the light-emitting control signal line EM; and / or, the pixel circuit further includes a second light-emitting control transistor T8, which is connected between the second electrode of the driving transistor T1 and the first end of the light-emitting device OLED; the gate of the second light-emitting control transistor T8 is electrically connected to the light-emitting control signal line EM; and / or, the pixel circuit further includes a data writing transistor T3, which is connected between the data line Data and the first electrode of the driving transistor T1; and / or, the pixel circuit further includes a storage capacitor Cst, which is connected between the first power line VDD and the gate of the driving transistor T1.

[0111] Optionally, referring to Figures 4 and 6 , the drive circuit layer further includes a first scan signal line SP1. The first scan signal line SP1 is electrically connected to the gate of the data write transistor T3. The first scan signal line SP1 is configured to control the data write transistor T3 to be conductive during a data write phase, thereby writing the data voltage on the data line Data to the first electrode of the drive transistor T1. Optionally, the first scan signal line SP1 is provided in the first conductive layer M1.

[0112] Optionally, referring to Figures 4 and 6 , the drive circuit layer further includes a second scan signal line SP2. The second scan signal line SP2 is electrically connected to the gates of the first initialization transistor T1 and the second initialization transistor T6. The second scan signal line SP2 is configured to control the first initialization transistor T1 and the second initialization transistor T6 to conduct during the first initialization phase to initialize the first electrode of the drive transistor T1 and the light-emitting device OLED. Optionally, the second scan signal line SP2 is provided in the first conductive layer M1.

[0113] Optionally, referring to Figures 4 and 6, the drive circuit layer further includes a third scan signal line SN1, which is electrically connected to the gate of the third initialization transistor T5. The third scan signal line SN1 is configured to control the third initialization transistor T5 to be conductive during the second initialization phase to initialize the gate of the drive transistor T1. Optionally, the third scan signal line SN1 is provided on the second conductive layer M2 and the third conductive layer M3. Optionally, the third scan signal line SN1 on the second conductive layer M2 is connected to the third scan signal line SN1 on the third conductive layer M2, for example, in a display area of ​​the display panel near a border area.

[0114] Optionally, referring to Figures 4 and 6, the driving circuit layer further includes a fourth scan signal line SN2, which is electrically connected to the gate of the threshold compensation transistor T4. The fourth scan signal line SN2 is configured to control the threshold compensation transistor T4 to be conductive during the threshold compensation phase, so that the threshold compensation transistor T4 performs threshold compensation on the driving transistor T1. Optionally, the fourth scan signal line SN2 is provided on the third conductive layer M3 and the second conductive layer M2. Optionally, the fourth scan signal line SN2 on the second conductive layer M2 is connected to the fourth scan signal line SN2 on the third conductive layer M2, for example, in the display area of ​​the display panel near the border area.

[0115] Optionally, referring to FIG9 , the first connecting portion 101 includes a first portion 1011 and a second portion 1012. The first portion 1011 is electrically connected to the first electrode of the driving transistor T1, and the second portion 1012 is electrically connected to the first initialization transistor T2. The first portion 1011 extends along a first direction X, and the second portion 1012 extends along a second direction Y. The first direction X and the second direction Y intersect. The second portion 1012 overlaps with the orthographic projection of the light-emitting control signal line EM on the substrate 110. The orthographic projection of the first portion 1011 on the substrate 110 is located on one of two opposite sides of the orthographic projection of the light-emitting control signal line EM on the substrate 110 along the second direction Y. This configuration ensures that when the shielding portion 103 shields the overlapping portion 102, it does not overlap with the via hole, thus avoiding the via hole and preventing the shielding portion 103 from being damaged or short-circuited. Optionally, a gap 120 is provided between the orthographic projection of the first portion 1011 on the substrate 110 and the orthographic projection of the light-emitting control signal line EM on the substrate 110. By arranging that the orthographic projection of the shielding layer M0 on the substrate 110 at least partially overlaps with the gap 120, the shielding layer M0 can shield part of the electric power line, thereby achieving the effect of reducing lateral capacitance.

[0116] Alternatively, referring to FIG14 , the first connection portion 101 includes a first portion 1011, a second portion 1012, and a third portion 1013 connected in sequence, the first portion 1011 being electrically connected to the first electrode of the driving transistor T1, the third portion 1013 being electrically connected to the first initialization transistor T2, the first portion 1011 and the third portion 1013 extending along a first direction X, the second portion 1012 extending along a second direction Y, the first direction X and the second direction Y intersecting, the second portion 1012 and the light emitting control signal line EM on the substrate 110. There is an overlapping part in the orthographic projection on the substrate 110; the orthographic projections of the first part 1011 and the third part 1013 on the substrate 110 are respectively located on two opposite sides of the orthographic projection of the light-emitting control signal line EM on the substrate 110 along the second direction Y; optionally, there is a gap 120 between the orthographic projection of the first part 1011 on the substrate 110 and the orthographic projection of the light-emitting control signal line EM on the substrate 110; there is a gap 120 between the orthographic projection of the third part 1013 on the substrate 110 and the orthographic projection of the light-emitting control signal line EM on the substrate 110.

[0117] To facilitate routing design, the first connecting portion 101 is configured to include a first portion 1011, a second portion 1012, and a third portion 1013 that are sequentially connected. For example, the first portion 1011, the second portion 1012, and the third portion 1013 are integrally formed. This allows the shielding portion 103 to avoid overlapping with the via when shielding the overlapping portion 102, thereby avoiding the via and preventing the via from damaging or short-circuiting the shielding portion 103. The first portion 1011 and the third portion 1013 extend in the same direction (or extending in the same direction) as the light-emission control signal line EM. A gap 120 is defined between the orthographic projection of the first portion 1011 on the substrate 110 and the orthographic projection of the light-emission control signal line EM. A gap 120 is defined between the orthographic projection of the third portion 1013 on the substrate 110 and the orthographic projection of the light-emission control signal line EM on the substrate 110. This gap 120 facilitates coupling and forming lateral capacitance. In the technical solution of this embodiment, by arranging the orthographic projection of shielding layer M0 on substrate 110 to at least partially overlap gap 120, shielding layer M0 can shield some of the electric lines, thereby reducing lateral capacitance. Furthermore, shielding portion 103 can also cover gap 120, that is, the orthographic projection of shielding portion 103 on substrate 110 at least partially overlaps gap 120, thereby further reducing lateral capacitance.

[0118] Figure 17 is another cross-sectional view of Figure 7 along the a1-a2 direction. Optionally, referring to Figure 17, multiple organic insulating layers are arranged between the film layer where the first connecting portion 101 is located and the film layer where the light-emitting control signal line EM is located; and / or, the organic insulating layer includes an organic planarization layer; and / or, at least one organic insulating layer and at least one inorganic insulating layer are stacked along the thickness direction Z of the substrate 110 between the film layer where the first connecting portion 101 is located and the film layer where the light-emitting control signal line EM is located.

[0119] By providing multiple layers of organic insulating layers between the film layer where the first connecting portion 101 is located and the film layer where the light-emitting control signal line EM is located, the dielectric layer thickness between the first connecting portion 101 and the light-emitting control signal line EM is increased, and the distance between the first connecting portion 101 and the light-emitting control signal line EM is increased, thereby reducing the parasitic capacitance of the overlapping portion 102. Furthermore, the multiple layers of organic insulating layers can effectively reduce the dielectric constant of the parasitic capacitance, thereby further reducing the parasitic capacitance of the overlapping portion 102. As shown in FIG15 , the organic insulating layer includes a first organic planarization layer PLN1 and a third organic planarization layer PLN3. The first organic planarization layer PLN1 is located on the side of the third conductive layer M3 away from the substrate 110. The third organic planarization layer PLN is located on the surface of the first organic planarization layer PLN1 away from the substrate 110. The second planarization layer PLN2 is located on the surface of the third organic planarization layer PLN away from the substrate 110. For example, the third organic planarization layer PLN3 may be an additional organic planarization layer. In this way, the first organic planarization layer PLN1 and the third organic planarization layer PLN3 can isolate the first connection part 101 and the light-emitting control signal line EM, which is beneficial to reducing the parasitic capacitance between the light-emitting control signal line EM and the first connection part 101, and further reducing the influence of the parasitic capacitance on the potential of the first electrode of the driving transistor T1.

[0120] By disposing at least one organic insulating layer and at least one inorganic insulating layer (e.g., one or more of the capacitor insulating layer CI, the second buffer layer B2, the second gate insulating layer GI2, and the interlayer insulating layer ILD) stacked along the thickness direction Z of the substrate 110 between the film layer where the first connecting portion 101 is located and the film layer where the light-emitting control signal line EM is located, the orthographic projection of the one or more organic insulating layers on the substrate 110 overlaps with the overlapping portion 102, and the orthographic projection of the one or more inorganic insulating layers on the substrate 110 overlaps with the overlapping portion 102. This further increases the distance between the first connecting portion 101 and the light-emitting control signal line EM in the thickness direction Z of the display panel, which helps further reduce the parasitic capacitance between the light-emitting control signal line EM and the first connecting portion 101. The inorganic insulating layer may include one or more of silicon oxide, silicon nitride, silicon oxynitride, etc. The organic insulating layer may include one or more of polyimide, polyacrylate, polyetherimide, polyethylene terephthalate, polyethylene naphthalate, etc.

[0121] Optionally, an organic insulating layer is provided between the film layer where the first connecting portion 101 is located and the film layer where the light-emitting control signal line EM is located, or at least one organic insulating layer and at least one inorganic insulating layer. The thickness D of the insulating layer between the film layer where the first connecting portion 101 is located and the film layer where the light-emitting control signal line EM is located is greater than 2.6 microns, which is equivalent to the facing distance between the first connecting portion 101 and the light-emitting control signal line EM at the overlapping point being greater than 2.6 microns, so as to reduce the parasitic capacitance between the light-emitting control signal line EM and the first connecting portion 101, for example, to less than 0.85fF.

[0122] Optionally, only an inorganic insulating layer is provided between the film layer where the first connecting portion 101 is located and the film layer where the light-emitting control signal line EM is located, and the thickness D of the insulating layer between the film layer where the first connecting portion 101 is located and the film layer where the light-emitting control signal line EM is located (corresponding to the insulating layer at the overlapping portion 102) is greater than 3 microns, which is equivalent to the facing distance between the first connecting portion 101 and the light-emitting control signal line EM at the overlapping portion being greater than 3 microns, so as to reduce the parasitic capacitance between the light-emitting control signal line EM and the first connecting portion 101, for example, to less than 0.85fF.

[0123] Based on the above-mentioned multiple technical solutions, FIG18 is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present application, and FIG19 is a cross-sectional view of FIG18 along the k1-k2 direction. Referring to FIG18 and FIG19 , the drive circuit layer optionally further includes a sixth conductive layer M6, which is located on a side of the fifth conductive layer M5 away from the substrate 110. The sixth conductive layer M6 includes a first power line VDD and a data line Data. The first power line VDD provides a first power supply voltage to the pixel circuit, and the data line Data is configured to provide a data voltage to the pixel circuit, so that the pixel circuit generates a drive current based on the data voltage and the first power supply voltage.

[0124] As shown in FIG. 19 , the fourth conductive layer M4 further includes a first electrode of the driving transistor T1 (eg, a source electrode of the driving transistor T1 ).

[0125] Optionally, in some embodiments, after the routing of the first power line VDD and the data line Data is completed, if there is space in the sixth conductive layer M6 for the first connecting portion 101, the first connecting portion 101 can be disposed in the sixth conductive layer M6. In this way, the distance between the first connecting portion 101 and the light-emitting control signal line EM can be further increased, further reducing the parasitic capacitance generated by the coupling between the first connecting portion 101 and the light-emitting control signal line EM, thereby ensuring the stability of the first electrode potential of the driving transistor T1 and, in turn, the stability of the driving current generated by the driving transistor T1. An organic insulating layer can be disposed between the fifth conductive layer M5 and the sixth conductive layer M6. The sixth conductive layer M6 may include one or more of a metal layer, an indium tin oxide (ITO) layer, and the like.

[0126] When the first connecting portion 101 is disposed on the sixth conductive layer M6, the shielding portion 103 can be disposed on the third conductive layer M3, the fourth conductive layer M4, or the fifth conductive layer M5. When the shielding portion 103 is disposed on the fifth conductive layer M5, the shielding portion 103 can be connected to the first power line VDD on the fifth conductive layer M5, so that the shielding portion 103 is connected to a DC potential, thereby better shielding the light-emission control signal line EM from the first connecting portion 101.

[0127] On the basis of the above-mentioned multiple technical solutions, the structure of multiple film layers in the array substrate is described below, but it is not intended to limit the present application.

[0128] Figure 20 is a schematic diagram of the layout structure of the first conductive layer and the second active layer of the array substrate provided in an embodiment of the present application. Optionally, referring to Figure 20, the first conductive layer M1 includes a light-emitting control signal line EM whose extension direction (or extension trend) is a first direction X, a first scanning signal line SP1, a second scanning signal line SP2, a third initialization signal line Vref3, and a second electrode C02 of the storage capacitor Cst (that is, the gate of the driving transistor T1).

[0129] FIG21 is a schematic diagram of the layout structure of the second conductive layer of the array substrate provided in an embodiment of the present application. Optionally, referring to FIG21 , the second conductive layer M2 includes a first electrode C01 of a storage capacitor Cst, a third scan signal line SN1, and a fourth scan signal line SN2 extending in a first direction X. The region where the third scan signal line SN1 on the second conductive layer M2 overlaps with the first active layer 130 can form the bottom gate of the third initialization transistor T5. The region where the fourth scan signal line SN2 on the second conductive layer M2 overlaps with the first active layer 130 can form the bottom gate of the threshold compensation transistor T4.

[0130] FIG22 is a schematic diagram of the layout structure of the third conductive layer and the first active layer of the array substrate provided in an embodiment of the present application. Optionally, referring to FIG22 , the third conductive layer M3 includes a first initialization signal line Vref1, a second initialization signal line Vref2, a third scan signal line SN1, and a fourth scan signal line SN2, each extending in a first direction X. The region where the third scan signal line SN1 on the third conductive layer M3 overlaps with the first active layer 130 may form the top gate of the third initialization transistor T5. The region where the fourth scan signal line SN2 on the third conductive layer M3 overlaps with the first active layer 130 may form the top gate of the threshold compensation transistor T4.

[0131] The third scan signal line SN1 on the second conductive layer M2 is electrically connected to the third scan signal line SN1 on the third conductive layer M3, for example, through a via. The fourth scan signal line SN2 on the second conductive layer M2 is electrically connected to the fourth scan signal line SN2 on the third conductive layer M3, for example, through a via. In this way, the bottom gate and top gate of the threshold compensation transistor T4 are connected, and the bottom gate and top gate of the third initialization transistor T5 are connected.

[0132] FIG. 22 shows a case where the shielding portion 103 is in the third conductive layer M3 and is electrically connected to the first initialization signal line Vref1 , but this is not limiting.

[0133] FIG23 is a schematic diagram of the layout structure of the fourth conductive layer of an array substrate provided in an embodiment of the present application. Optionally, referring to FIG23 , the fourth conductive layer M4 includes a first connecting portion 101, a first initialization signal line Vref1 extending in (or extending in) a second direction Y, a second initialization signal line Vref2, and a third initialization signal line Vref3. As shown in FIG22 , the first initialization signal line Vref1 (extending in the first direction X) on the third conductive layer M3 and the first initialization signal line Vref1 (extending in the second direction Y) on the fourth conductive layer M4 form a mesh structure, thereby ensuring that the first initialization signals transmitted by the first initialization signal line Vref1 to different locations (in different pixel circuits) are close to each other, which helps improve the display uniformity of the display panel. Similarly, the second initialization signal line Vref2 (extending in the first direction X) on the third conductive layer M3 and the second initialization signal line Vref2 (extending in the second direction Y) on the fourth conductive layer M4 form a mesh structure. The third initialization signal line Vref3 (extending in the first direction X) on the first conductive layer M1 and the third initialization signal line Vref3 (extending in the second direction Y) on the fourth conductive layer M4 also form a mesh structure, which helps improve the display uniformity of the display panel. The first power line (extending in the first direction X) on the fifth conductive layer M5 and the first power line (extending in the second direction Y) on the sixth conductive layer M6 form a mesh structure.

[0134] Each signal line may extend in a straight line, a broken line, a curve, or other irregular shapes (such as a tree branch, etc.) along its extension direction (general extension direction or extension trend).

[0135] Optionally, the shielding portion 103 may be electrically connected to the third initialization signal line Vref3 to provide access to a DC potential. Among the first initialization signal line Vref1, the second initialization signal line Vref2, and the third initialization signal line Vref3 extending along the first direction X, among the first initialization signal lines Vref1, the second initialization signal line Vref2, and the third initialization signal line Vref3 corresponding to the same row of pixel circuits, the orthographic projection of the third initialization signal line Vref3 on the substrate 110 is located on a side of the orthographic projection of the shielding portion 103 on the substrate 110 that is away from the orthographic projections of the first initialization signal line Vref1 and the second initialization signal line Vref2 on the substrate 110. Compared to the third initialization signal line Vref3, the first initialization signal line Vref1 and the second initialization signal line Vref2 are closer to the shielding portion 103. Therefore, connecting the shielding portion 103 to the first initialization signal line Vref1 or the second initialization signal line Vref2 facilitates wiring.

[0136] Figure 24 is a schematic diagram of the layout structure of the fourth conductive layer of another array substrate provided in an embodiment of the present application. Optionally, referring to Figure 24, when the first connecting portion 101 is arranged on the side of the fourth conductive layer M4 away from the substrate 110, the first connecting portion 101 is not arranged on the fourth conductive layer M4.

[0137] Figure 25 is a schematic diagram of the layout structure of a fifth conductive layer of an array substrate provided in an embodiment of the present application. Optionally, referring to Figure 25 , the fifth conductive layer M5 includes a first power line VDD extending in a first direction X. The first sub-line L1 corresponds to the main body, and the second sub-line L2 corresponds to the branch. Figure 25 illustrates the first connection portion 101 in the fifth conductive layer M5, but is not intended to be limiting.

[0138] Figure 26 is a schematic diagram of the layout structure of the sixth conductive layer of the array substrate provided in an embodiment of the present application. Optionally, referring to Figure 26, the sixth conductive layer M6 includes a first power line VDD whose extension direction (or extension trend) is the second direction Y and a data line Data whose extension direction (or extension trend) is the second direction Y.

[0139] Optionally, as shown in FIG26 , the sixth conductive layer M6 further includes a data connection line Fa, which is configured to connect the driver chip and the data line Data. By arranging the data connection line Fa in the sixth conductive layer M6, the routing of the display panel frame area (non-display area) can be reduced, which is conducive to achieving a narrow frame.

[0140] FIG27 is a schematic diagram of the layout structure of the shielding layer of the array substrate provided in an embodiment of the present application. Optionally, referring to FIG27 , the orthographic projection of the shielding layer M0 on the substrate 110 at least partially overlaps with the gap 120 .

[0141] Figure 28 is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present application, and Figure 28 shows a case where the first connecting portion 101 is located in the fifth conductive layer M5. Figure 29 is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present application, and Figure 29 shows a case where the first connecting portion 101 is located in the fourth conductive layer M4, and the shielding portion 103 is electrically connected to the first electrode C01 of the storage capacitor Cst. Figure 30 is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present application, and Figure 30 shows a case where the first connecting portion 101 is located in the fifth conductive layer M5, and the shielding portion 103 is located in the fourth conductive layer M4. Optionally, referring to Figures 28 to 30, the orthographic projection of the first initialization signal line Vref1 on the substrate 110 is separated from the orthographic projection of the light-emitting control signal line EM on the substrate 110, that is, they do not overlap.

[0142] Optionally, FIG31 is a schematic circuit structure diagram of another pixel circuit provided in an embodiment of the present application, wherein the pixel circuit further includes a first light-emitting control transistor T7, connected between the second electrode of the driving transistor T1 and the first power line VDD; the gate of the first light-emitting control transistor T7 is electrically connected to the light-emitting control signal line EM; and / or the pixel circuit further includes a second light-emitting control transistor T8, connected between the first electrode of the driving transistor T1 and the first end of the light-emitting device OLED; the gate of the second light-emitting control transistor T8 is electrically connected to the light-emitting control signal line EM; and / or the pixel circuit further includes a data writing transistor T3, connected between the data line Data and the second electrode of the driving transistor T1; and / or the pixel circuit further includes a storage capacitor Cst, connected between the first power line VDD and the gate of the driving transistor T1. Optionally, the pixel circuit further includes a threshold compensation transistor T4, connected between the gate and the first electrode of the driving transistor T1.

[0143] The difference between the circuit structure of Figure 31 and the circuit structure of Figure 6 is that the connection position of the first initialization transistor T2 is different. It is equivalent to the first initialization transistor T2 in Figure 31 being connected to the drain of the driving transistor T1, while the first initialization transistor T2 in Figure 6 is connected to the source of the driving transistor T1. The structures and functions of the corresponding elements in the circuit structure of Figure 31 and the circuit structure of Figure 6 are the same or similar and will not be repeated here. The first electrode of the driving transistor T1 in Figure 31 is equivalent to the drain, and the second electrode of the driving transistor T1 is equivalent to the source. The first electrode of the driving transistor T1 in Figure 6 is equivalent to the source, and the second electrode of the driving transistor T1 is equivalent to the drain.

[0144] Figure 32 is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present application. The layout structure in Figure 32 corresponds to the circuit in Figure 31. The circuit in Figure 6 corresponds to the layout structure and film layer structure of Figures 4 to 30. The end of the first connection portion 101 in the layout structure and film layer structure corresponding to the circuit in Figure 6 that is connected to the driving transistor T1 is changed from being connected to the source of the driving transistor to being connected to the drain of the driving transistor. The positions and functions of multiple components such as the corresponding shielding portion 103 are the same or similar, and are not described in detail here. The pixel circuit (such as the circuit in Figure 6 and the circuit in Figure 31) can be dimmed using pulse width modulation (PWM) technology, and the light-emitting control signal may include multiple pulses during the light-emitting stage within a picture refresh cycle. The timing waveform diagram and working process of the circuit in Figure 6 and the circuit in Figure 31 are the same or similar to those in Figures 1 and 2, and are not described in detail here.

[0145] Optionally, the first light emitting control transistor T7 is connected between the second electrode of the driving transistor T1 and the second sub-line L2.

[0146] This embodiment also provides a display panel. FIG33 is a schematic structural diagram of a display panel provided in an embodiment of the present application. As shown in FIG33 , the display panel includes an array substrate provided in any of the above-described embodiments. The display panel can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, or digital photo frame. The display panel includes the array substrate provided in any embodiment of the present application, and thus has the same beneficial effects as the array substrate provided in any embodiment of the present application, which will not be further described here.

[0147] The above specific embodiments do not constitute a limitation on the scope of protection of this application. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application shall be included within the scope of protection of this application.

Claims

1. An array substrate, comprising: A substrate and a driving circuit layer located on the substrate, wherein the driving circuit layer is provided with a pixel circuit and a light-emitting control signal line, wherein the pixel circuit comprises a driving transistor, a first initialization transistor and a first connection portion, wherein the first connection portion is connected between a first electrode of the driving transistor and the first initialization transistor; and an orthographic projection of the first connection portion and the light-emitting control signal line on the substrate has an overlapping portion; The driving circuit layer is further provided with a shielding portion, the orthographic projection of the shielding portion on the substrate overlaps with the overlapping portion; the film layer where the shielding portion is located is located between the film layer where the light emitting control signal line is located and the film layer where the first connecting portion is located; And / or, at least one organic insulating layer is provided between the film layer where the first connecting portion is located and the film layer where the light emitting control signal line is located; And / or, the thickness of the insulating layer between the film layer where the first connecting portion is located and the film layer where the light emitting control signal line is located is greater than 3 micrometers.

2. The array substrate according to claim 1, wherein: The shielding portion is connected to a DC potential; 3. The array substrate according to claim 1, wherein: The driving circuit layer is further provided with a first power line and / or an initialization signal line, and the shielding portion is electrically connected to the first power line or the initialization signal line.

4. The array substrate according to claim 1, wherein: The driving circuit layer includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer which are stacked; The light emitting control signal line is arranged on the first conductive layer; The pixel circuit further includes a storage capacitor, wherein a first electrode plate of the storage capacitor is disposed on the second conductive layer; The pixel circuit further includes a switch tube, the switch tube is connected to the gate of the driving transistor, and a first gate of the switch tube is arranged on the third conductive layer; The first connecting portion is disposed on the fourth conductive layer or on a side of the fourth conductive layer away from the substrate; The fifth conductive layer is provided with a first power line, and the first power line is configured to provide a first power voltage for the pixel circuit.

5. The array substrate according to claim 4, wherein: The first connecting portion is disposed on the fifth conductive layer; The organic insulating layer is disposed between the fourth conductive layer and the fifth conductive layer; The first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer An inorganic insulating layer is disposed between any two adjacent ones.

6. The array substrate according to any one of claims 1 to 5, wherein: The overlapping portion is located within the orthographic projection of the shielding portion on the substrate; The film layer where the light-emitting control signal line is located, the film layer where the shielding portion is located, and the film layer where the first connecting portion is located are stacked in sequence in a direction away from the substrate.

7. The array substrate according to any one of claims 1 to 5, wherein: The pixel circuit further includes a second initialization transistor; the driving circuit layer is further provided with a first initialization signal line and a second initialization signal line, the first initialization transistor is connected between the first initialization signal line and the first electrode of the driving transistor, and the second initialization transistor is connected between the second initialization signal line and the first end of the light emitting device; The shielding portion is electrically connected to the first initialization signal line or the second initialization signal line; A gate of the first initialization transistor and a gate of the second initialization transistor are electrically connected to the same scan signal line.

8. The array substrate according to claim 7, wherein: The driving circuit layer further includes a third conductive layer; the pixel circuit further includes a switch tube; The switch tube is connected to the gate of the driving transistor; the third conductive layer is provided with a first gate of the switch tube; The shielding portion is disposed on the third conductive layer; The first initialization signal line and / or the second initialization signal line are arranged in the third conductive layer; The orthographic projection of the first initialization signal line on the substrate is located between the orthographic projection of the second initialization signal line on the substrate and the orthographic projection of the shielding portion on the substrate; The orthographic projection of the first initialization signal line on the substrate is located between the orthographic projection of the second initialization signal line on the substrate and the orthographic projection of the light emission control signal line on the substrate; The first initialization signal line, the second initialization signal line and the light emitting control signal line extend in a first direction and are arranged along a second direction, and the first direction intersects with the second direction; The second initialization signal line is electrically connected to the shielding part via a second connection part, and the second connection part is cross-insulated with the first initialization signal line; The film layer where the second connecting portion is located is located on a side of the film layer where the first initialization signal line is located away from the substrate; The first connection portion and the second connection portion are arranged in the same layer.

9. The array substrate according to any one of claims 1 to 5, wherein: The pixel circuit further comprises a storage capacitor, wherein a first electrode plate of the storage capacitor is connected to a first power line; The first electrode plate and the shielding portion are electrically connected to form an integral structure and are arranged on the same layer; The driving circuit layer further comprises a second conductive layer, wherein the second conductive layer is provided with a first electrode plate of the storage capacitor; The second electrode plate of the storage capacitor is reused as the gate of the driving transistor.

10. The array substrate according to any one of claims 1 to 5, wherein: The driving circuit layer is provided with a first power line, the first power line includes a first sub-line and a second sub-line electrically connected; the pixel circuit further includes a first light emission control transistor, the first light emission control transistor is electrically connected to the second sub-line; The second sub-wire is electrically connected to the shielding portion; The shielding portion extends along a first direction, the first sub-line extends along the first direction, and the extension direction of the second sub-line intersects the first direction; the first sub-line and the second sub-line are arranged in the same layer; The first light emission control transistor is connected between the first electrode of the driving transistor and the second sub-line, or the first light emission control transistor is connected between the second electrode of the driving transistor and the second sub-line; The gate of the first light emission control transistor is electrically connected to the light emission control signal line; The driving circuit layer further includes a fourth conductive layer and a fifth conductive layer, the shielding part is arranged on the fourth conductive layer; the first sub-line and the second sub-line are arranged on the fifth conductive layer; the second sub-line is electrically connected to the shielding part through a via.

11. The array substrate according to claim 10, wherein: Among the three pixel circuits adjacent to each other along the first direction, the shielding portion in the pixel circuit located in the middle is connected to the shielding portion in the pixel circuit located on one side; the distance between the first connecting portion in the pixel circuit located in the middle and the first connecting portion in the pixel circuit located on one side is smaller than the distance between the first connecting portion in the pixel circuit located in the middle and the first connecting portion in the pixel circuit located on the other side; Two pixel circuits adjacent to each other along the first direction are arranged in mirror symmetry.

12. The array substrate according to claim 1, wherein: The light-emitting control signal line includes a main body portion extending along a first direction and an extending portion extending along a third direction, wherein the first direction intersects the third direction; The orthographic projection of the shielding portion on the substrate at least partially covers the orthographic projection of the extending portion on the substrate.

13. The array substrate according to claim 1, further comprising a shielding layer, wherein the shielding layer is located between the substrate and the driving circuit layer; There is a gap between the orthographic projection of the first connecting portion on the substrate and the orthographic projection of the light emitting control signal line on the substrate; The orthographic projection of the shielding layer on the substrate at least partially overlaps with the gap; At least part of the shielding layer is connected to a DC potential; The shielding layer is electrically connected to the first power line; The orthographic projection of the shielding layer on the substrate overlaps at least a portion of an active portion of a channel region of the driving transistor; The shielding layer is: an electrostatic shielding layer and / or a light shielding layer.

14. The array substrate according to any one of claims 1 to 5, wherein: The driving circuit layer is also provided with a first initialization signal line; the first initialization transistor is connected between the first initialization signal line and the first electrode of the driving transistor, The extension direction of the first initialization signal line and the light-emitting control signal line is a first direction, and the first initialization signal line and the light-emitting control signal line are arranged along a second direction; the orthographic projection of the first initialization signal line on the substrate and the orthographic projection of the light-emitting control signal line on the substrate are separated, and the first direction and the second direction intersect.

15. The array substrate according to claim 14, wherein: The shielding part is electrically connected to the first initialization signal line to form an integrated structure and is arranged on the same layer; the shielding part is connected to one side of two sides of the first initialization signal line that are opposite to each other along the second direction; The driving circuit layer further comprises a first active layer, a third conductive layer, a second active layer and a first conductive layer, the active portion of the driving transistor is located in the second active layer, the gate of the driving transistor is located in the first conductive layer, and the first initialization signal line is located in the third conductive layer or on a side of the third conductive layer away from the substrate; The pixel circuit further includes a threshold compensation transistor, the threshold compensation transistor is connected between the gate and the second electrode of the driving transistor, or the threshold compensation transistor is connected between the gate and the first electrode of the driving transistor, the active portion of the threshold compensation transistor is located in the first active layer, and the gate of the threshold compensation transistor is located in the third conductive layer; The pixel circuit further includes a third initialization transistor, the third initialization transistor is electrically connected to the gate of the driving transistor, an active portion of the third initialization transistor is located in the first active layer, and a gate of the third initialization transistor is located in the third conductive layer; The second active layer includes polysilicon, and the first active layer includes metal oxide.

16. The array substrate according to claim 1, wherein: The pixel circuit further includes: a first light emission control transistor, the first light emission control transistor is connected between the first electrode of the driving transistor and the first power line; the gate of the first light emission control transistor is electrically connected to the light emission control signal line; a second light emitting control transistor, wherein the second light emitting control transistor is connected between the second electrode of the driving transistor and the first end of the light emitting device; and a gate of the second light emitting control transistor is electrically connected to the light emitting control signal line; A data writing transistor, wherein the data writing transistor is connected between the data line and the first electrode of the driving transistor; a storage capacitor connected between the first power line and the gate of the driving transistor; Alternatively, the pixel circuit further comprises a first light emission control transistor, wherein the first light emission control transistor is connected between the second electrode of the driving transistor and the first power supply line; and a gate of the first light emission control transistor is electrically connected to the light emission control signal line; a second light emitting control transistor, wherein the second light emitting control transistor is connected between the first electrode of the driving transistor and the first end of the light emitting device; and a gate of the second light emitting control transistor is electrically connected to the light emitting control signal line; A data writing transistor, wherein the data writing transistor is connected between the data line and the second electrode of the driving transistor; A storage capacitor is connected between the first power line and the gate of the driving transistor.

17. The array substrate according to claim 1 or 15, wherein: The first connecting portion includes a first portion, a second portion, and a third portion that are connected in sequence, the first portion is electrically connected to the first electrode of the driving transistor, the third portion is electrically connected to the first initialization transistor, the first portion and the third portion extend along a first direction, the second portion extends along a second direction, the first direction and the second direction intersect, and the second portion and the orthographic projection of the light emitting control signal line on the substrate have an overlapping portion; the orthographic projections of the first portion and the third portion on the substrate are respectively located on opposite sides of the orthographic projection of the light emitting control signal line on the substrate along the second direction; There is a gap between the orthographic projection of the first part on the substrate and the orthographic projection of the light emitting control signal line on the substrate; there is a gap between the orthographic projection of the third part on the substrate and the orthographic projection of the light emitting control signal line on the substrate.

18. The array substrate according to any one of claims 1 to 5, wherein: A plurality of organic insulating layers are arranged between the film layer where the first connecting portion is located and the film layer where the light emitting control signal line is located; And / or, the organic insulating layer includes an organic planarization layer; And / or, at least one organic insulating layer and at least one inorganic insulating layer are stacked along the thickness direction of the substrate between the film layer where the first connecting portion is located and the film layer where the light emitting control signal line is located; And / or, an organic insulating layer is arranged between the film layer where the first connecting portion is located and the film layer where the light-emitting control signal line is located, and the thickness of the insulating layer between the film layer where the first connecting portion is located and the film layer where the light-emitting control signal line is located is greater than 2.6 microns.

19. The array substrate according to any one of claims 1 to 5, wherein: Only an inorganic insulating layer is arranged between the film layer where the first connecting portion is located and the film layer where the light-emitting control signal line is located, and the thickness of the insulating layer between the film layer where the first connecting portion is located and the film layer where the light-emitting control signal line is located is greater than 3 microns.

20. A display panel comprising the array substrate according to any one of claims 1 to 19.

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