Display pixel comprising light-emitting devices and display screen having such display pixels

Abstract

Display pixel comprising light-emitting devices and display screen having such display pixels The present description concerns a display pixel (12i,j) comprising a light-emitting device (LED), a current source (CS) supplying the light-emitting device, and a driver circuit (50) receiving a digital color signal (R, G, B). The digital color signal comprises a number NB of bits each having a rank from the least significant bit to the most significant bit. The driver circuit receives said NB bits in a first order and then in a second order, and, for each received bit, turns on the current source when said bit is at a first logical value during a duration that depends on the rank of said bit or turns off the current source during said duration when said bit is at a second logical value, said durations increasing from the least significant bit to the most significant bit.

Description

DESCRIPTIONTITLE : Display pixel comprising light-emitting devices and display screen having such display pixelsThis application claims the priority benefit of French patent application number 23 / 09976 , filed on 20 / 09 / 2023 , entitled "Display pixel comprising light-emitting devices and display screen having such display pixel s" , which is hereby incorporated by reference to the maximum extent allowable by law .Technical background

[0001] The present disclosure concerns a display pixel comprising light-emitting devices , for example lightemitting diodes , and a display screen having such display pixels .Prior art

[0002] A pixel of an image corresponds to the unit element of the image displayed by a display screen . For the display of color images , the display screen generally comprises , for the display of each pixel of the image , at least three components , also called display sub-pixels , which each emit a light radiation, called image pixel color component substantially in a single color ( for example , red, green, and blue ) . The superposition of the image pixel color components emitted by the three display sub-pixels provides the observer with the colored sensation corresponding to the pixel of the displayed image . In this case , the assembly formed by the three display sub-pixels used for the display of a pixel of an image is called display pixel of the display screen . Each display sub-pixel may comprise a light source , particularly a light-emitting diode .

[0003] The display pixels may be distributed in an array, each display pixel being located at the intersection of a row ( also called line ) and of a column of the array . Electrodes are provided along the rows and the columns to connect each display pixels to control circuits . Generally, each row of display pixels is successively selected by signal transmitted along the row electrodes , and the display pixels of the selected row are programmed to display the desired image pixels by signals transmitted along the column electrodes .

[0004] It is known to control a light emitting diode by pulsewidth modulation, also called PWM (English acronym for Pulse Width Modulation) . This type of control consists in circulating successive current pulses of constant intensity in the light-emitting diode , the pulses being repeated cyclically, the duty cycle determining the light intensity emitted by the light-emitting diode . Such a control advantageously makes it possible to operate the lightemitting diode at its optimum operating point where the ef ficiency of the light-emitting diode , equal to the ratio between the light power emitted by the light-emitting diode and the electrical power consumed by the light-emitting diode , is maximum . Moreover, a pulse-width modulation command allows the current density crossing the lightemitting diode to remain constant . This is advantageous since , for some types of light-emitting diodes , the central wavelength of the radiation emitted by the light-emitting diode may vary with the current density crossing the lightemitting diode .

[0005] The light emitting diode can be supplied by a controllable current source . The controllable current source can comprise a current source in series with a switch . The switch is commanded to obtained the pulse-widthmodulation while the current source delivers the constant current . The current source can comprise a MOS transistor, the intensity of the current crossing the MOS transistor being dependent on the gate voltage of the MOS transistor . The gate voltage of the MOS transistor can correspond to a voltage stored across a capacitor . However, some leakage currents can lead to a variation of the voltage stored across a capacitor leading to a variation of the intensity of the current provided by current source over time . It can be necessary to provide a refresh circuit that can be complex in order to frequently refresh the voltage across the capacitor .

[0006] The current pulses provided by the controllable current source controlled by pulse-width modulation can have di f ferent durations . The document KR 102 378 251 discloses that the order of the di f ferent durations for an odd frame can be di f ferent from the order of the di f ferent durations for an even frame .Summary of the invention

[0007] An obj ect of an embodiment is to provide a display pixel comprising light-emitting diodes and a display screen comprising such display pixels overcoming all or part of the disadvantages of existing display pixels comprising light-emitting diodes and display screens comprising such display pixels .

[0008] One embodiment provides a display pixel comprising at least one light-emitting device , a controllable current source supplying said light-emitting device with a current , a driver circuit configured to turn on or of f the controllable current source , and to receive bits of a digital color signal associated to an image pixel to be displayed, and a storage circuit configured to store saiddigital color signal , said digital color signal comprising a number NB of bits each having a rank from the least signi ficant bit of the digital color signal to the most signi ficant bit of the digital color signal , each bit of the digital color signal having a first logical value or a second logical value , said storage circuit being configured to provide to the driver circuit , during a display phase of the image pixel , at least some of said NB bits in a first order and then in a second order, di f ferent from the first order, said driver circuit being configured, during the display phase of the image pixel , for each received bit , to turn on the controllable current source when said bit is at the first logical value during a duration that depends on the rank of said bit or to turn of f the controllable current source during said duration when said bit is at the second logical value , said durations increasing from the least signi ficant bit to the most signi ficant bit . This advantageously allows the di f ferential nonlinearity of the display pixel to be reduced . Moreover, there can advantageously be no sudden steep variations in the evolution of current with respect to the value of the digital color signal . Moreover, there is advantageously no need for a complex refresh circuit for refreshing the storage circuit .

[0009] According to an embodiment , said driver circuit is configured to receive at least some of said NB bits in the first order according to decreasing ranks of the bits and in the second order according to increasing ranks of the bits , or inversely . This advantageously allows risk of occurrence of the dynamic false contour phenomenon to be reduced .

[0010] According to an embodiment , said driver circuit is configured to receive at least some of said NB bits in thefirst order comprising successive first , second, and third bits , the rank of the second bit being higher than the rank of the first bit and the rank of the third bit , or the rank of the second bit being lower than the rank of the first bit and the rank of the third bit .

[0011] According to an embodiment , said drive circuit is configured, after the reception of said bits in the second order, to further receive said bits in a third order and then in a fourth order, di f ferent from the third order . This advantageously further allows to reduce dynamic false contour phenomena .

[0012] According to an embodiment , the third order is identical to the first order and the fourth order is identical to the second order, or the third order is identical to the second order and the fourth order is identical to the first order .

[0013] According to an embodiment , the controllable current source comprises a switch in series with a constant current source , the driver circuit being configured, for each received bit , to turn on said switch during said duration when said bit is at the first logical value or to turn of f said switch during said duration when said bit is at the second logical value .

[0014] According to an embodiment , the constant current source comprises a MOS transistor and a capacitor, said MOS transistor having its drain or its source coupled to said switch and said capacitor having an electrode connected to the gate of said MOS transistor .

[0015] According to an embodiment , the storage circuit comprises NB memory cells DFFi , i varying from 0 to NB- 1 , for storing the bits of the digital color signal , wherein each memory cell DFFi is a flip- flop clocked by a timingsignal . The structure of the storage circuit i s advantageously made simple .

[0016] According to an embodiment , the storage circuit comprises NB first multiplexers MUXi , i varying from 0 to NB- 1 , each being controlled by a control signal , each first multiplexer MUXi , i being in the range from 1 to NB-2 , comprising a first input connected to the output of memory cell DFFi-i , a second input connected to the output of memory cell DFFi+1and an output connected to the input of memory cell DFFi , wherein each first multiplexer MUXi , i being in the range from 1 to NB-2 , is configured to send the signal provided by memory cell DFFi-i at its output when the control signal is at a first logical value , and to send the signal provided by memory cell DFFi+iat its output when the control signal is at a second logical value , wherein first multiplexer MUXNB-I comprises a first input connected to the output of memory cell DFFNB-2, a second input connected to the output of memory cell DFF0and an output connected to the input of memory cell DFFNB-I , wherein first multiplexer MUXNB-! is configured to send the signal provided by memory cell DFFNB-2at its output when the control signal is at the first logical value , and to send the signal provided by memory cell DFF0at its output when the control signal is at the second logical value , wherein first multiplexer MUX0comprises a first input connected to the output of memory cell DFFNE-X , a second input connected to the output of memory cell DFFBand wherein first multiplexer MUX0is configured to send the signal provided by memory cell DFFNB_ i at its output when the control signal is at the first logical value , and to send the signal provided by memory cell DFFBat its output when the control signal is at the second logical value .

[0017] According to an embodiment , the storage circuit comprises a second multiplexer, controlled by the control signal and comprising a first input connected to the output of memory cell DFFNB-I , a second input connected to the output of memory cell , and an output providing said bits to the driver circuit , the second multiplexer being configured to send the signal provided by memory cell DFFNB_ i at its output when the control signal is at the first logical value , and to send the signal provided by memory cell DFF0at its output when the control signal is at the second logical value .

[0018] According to an embodiment , said storage circuit is configured to provide to the driver circuit all the bits of the digital color signal in the first order and then in the second order except for the least signi ficant bit of the digital color signal that is provided only once . It can be advantageous that the least signi ficant bit displayed during the shortest duration is displayed only once , when it can be di f ficult to generate successive pulses to provide the two successive shortest durations , for example due to latencies in the operation of the display screen .

[0019] Another embodiment provides a display screen comprising : display pixels as previously defined; first electrodes coupled to the display pixels ; a first circuit for delivering a selection signal on each first electrode for the selection of the display pixels coupled to the first electrode ; second electrodes coupled to the display pixels ; and a second circuit for delivering data signals on the second electrodes .

[0020] According to an embodiment , the selection signal comprises pulses spaced from said durations in the first order and then in the second order, the storage being clocked by the selection signal to provide to the driver circuit at least some of said NB bits in the first order and then in the second order .

[0021] Another embodiment provides a method for commanding a display pixel comprising at least one light-emitting device , a controllable current source supplying said lightemitting device with a current , a driver circuit configured to turn on or of f the controllable current source , and to receive bits of a digital color signal associated to an image pixel to be displayed, and a storage circuit configured to store said digital color signal , said digital color signal comprising a number NB of bits each having a rank from the least signi ficant bit of the digital color signal to the most signi ficant bit of the digital color signal , each bit of the digital color signal having a first logical value or a second logical value , the method comprising the steps of providing during a display phase of the image pixel , by the storage circuit to the driver circuit at least some of said NB bits in a first order and then in a second order, di f ferent from the first order, and having said driver circuit , during the display phase of the image pixel , for each received bit , to turn on the controllable current source when said bit is at the first logical value during a duration that depends on the rank of said bit or to turn of f the controllable current source during said duration when said bit is at the second logical value , said durations increasing from the least signi ficant bit to the most signi ficant bit .

[0022] According to an embodiment , the controllable current source comprises a switch in series with a constant currentsource and the constant current source comprises a MOS transistor and a capacitor . The refresh of the voltage across the capacitor is prevented while the storage circuit is providing to the driver circuit at least some of said NB bits in the first order and then in the second order . Since the refresh of the voltage across the capacitor is not to be performed frequently, in particular during the display phase , the structure of a refresh circuit that refreshes the voltage across the capacitor can advantageously be simple .

[0023] According to an embodiment , the method comprises providing to the display pixel a selection signal comprising pulses spaced from said durations in the first order and then in the second order, the storage being clocked by the selection signal to provide to the driver circuit at least some of said NB bits in the first order and then in the second order .Brief description of the drawings

[0024] The foregoing features and advantages , as well as others , will be described in detail in the rest of the disclosure of speci fic embodiments given by way of illustration and not limitation with reference to the accompanying drawings , in which :

[0025] Figure 1 partially and schematically shows an embodiment of a display screen;

[0026] Figure 2 shows an example of a block diagram of a display pixel of the display screen of Figure 1 ;

[0027] Figure 3 shows examples of timing diagrams of a signal used by the display pixel of Figure 2 for controlling a light-emitting diode by pulse-width modulation and of the current supplied to the light-emitting diode ;

[0028] Figure 4 shows an example of a controllable current source of the display pixel of Figure 2 ;

[0029] Figure 5 shows the evolution of the current provided by the controllable current source of Figure 4 with a first configuration of leakage currents ;

[0030] Figure 6 shows the evolution of the di f ferential nonlinearity of the display pixel with the current evolution shown in Figure 5 with respect to the color signal to be displayed;

[0031] Figure 7 shows the evolution of the brightness of the display pixel with the current evolution shown in Figure 5 with respect to the color signal to be displayed;

[0032] Figure 8 shows the evolution of the current provided by a controllable current source of Figure 4 with a second configuration of leakage currents ;

[0033] Figure 9 shows the evolution of the di f ferential nonlinearity of the display pixel with the current evolution shown in Figure 8 with respect to the color signal to be displayed;

[0034] Figure 10 shows the evolution of the brightness of the display pixel with the current evolution shown in Figure 8 with respect to the color signal to be displayed;

[0035] Figure 11 illustrates the successive display of two image pixels corresponding to successive gray levels ;

[0036] Figure 12 shows the evolution of the turn-on period over time for the display of the image pixels shown in Figure 11 ;

[0037] Figure 13 illustrates a method for determining of the turn-on period during one frame over time ;

[0038] Figure 14 shows a block diagram of an example of a storage circuit of the display pixel of Figure 2 ;

[0039] Figure 15 shows a block diagram of an example of a refresh circuit of the display pixel of Figure 2 ;

[0040] Figure 16 shows the evolution of the current provided by the controllable current source of Figure 4 with the first configuration of leakage currents according to an embodiment of operation of the display pixel ;

[0041] Figure 17 shows the evolution of the di f ferential nonlinearity of the display pixel with the current evolution shown in Figure 16 with respect to the color signal to be displayed;

[0042] Figure 18 shows the evolution of the brightness of the display pixel with the current evolution shown in Figure 16 with respect to the color signal to be displayed;

[0043] Figure 19 shows the evolution of the current provided by the controllable current source of Figure 4 with the second configuration of leakage currents according to an embodiment of operation of the display pixel ;

[0044] Figure 20 shows the evolution of the di f ferential nonlinearity of the display pixel with the current evolution shown in Figure 19 with respect to the color signal to be displayed;

[0045] Figure 21 shows the evolution of the brightness of the display pixel with the current evolution shown in Figure 19 with respect to the color signal to be displayed;

[0046] Figure 22 illustrates an embodiment of the operation of the display pixel for the successive display of two image pixels corresponding to successive gray levels ;

[0047] Figure 23 shows the evolution of the turn-on period over time for the display of the image pixels shown in Figure 22;

[0048] Figure 24 illustrates another embodiment of the operation of the display pixel for the successive display of two image pixels corresponding to successive gray levels ;

[0049] Figure 25 shows the evolution of the turn-on period over time for the display of the image pixels shown in Figure 24;

[0050] Figure 26 illustrates embodiments of the operation of the display pixel for the display of an image pixel;

[0051] Figure 27 illustrates other embodiments of the operation of the display pixel for the display of an image pixel; and

[0052] Figure 28 shows a block diagram of an embodiment of the storage circuit of the display pixel of Figure 2.Description of the embodiments

[0053] Unless indicated otherwise, when reference is made to two elements connected together, this signifies a direct connection without any intermediate elements other than conductors, and when reference is made to two elements coupled together, this signifies that these two elements can be connected or they can be coupled via one or more other elements.

[0054] Further, a signal which alternates between a first constant state, for example, a low logical state, noted "0", and a second constant state, for example, a high logical state, noted "1", is called a "binary signal". The high and low states of different binary signals of a same electronic circuit may be different. In practice, thebinary signals may correspond to voltages or to currents which may not be perfectly constant in the high or low state .

[0055] Further, unless indicated otherwise, when it is spoken of a voltage at a conductive pad, the difference between the potential at said conductive pad and a reference potential, for example, the ground, taken as equal to 0 V, is considered.

[0056] Further, the "power terminals" of a metal-oxide- semiconductor field-effect transistor, also called MOS transistor, refer to the source and the drain of the MOS transistor .

[0057] Unless specified otherwise, the expressions "around", "approximately", "substantially" and "in the order of" signify within 10%, and preferably within 5%. Further the expression "substantially constant" means which varies by less than 10% over time with respect to a reference value.

[0058] A light-emitting diode is said to be a three- dimensional light-emitting diode when it comprises a three- dimensional semiconductor element of micrometric or nanometric size extending in a preferred direction, for example a microwire or a nanowire, covered with an active area. In particular, a three-dimensional light-emitting diode is said to be of the radial type when its active zone extends at least over the side walls of the three- dimensional semiconductor element.

[0059] Figure 1 partially and schematically shows a known example of a display screen 10. Display screen 10 comprises display pixels 12ifj , for example, arranged in M rows and in N columns, M being an integer varying from 1 to 8,000 and N being an integer varying from 1 to 16,000, i being an integer varying from 1 to M, and j being an integervarying from 1 to N. As an example, in Figure 1, M and N are equal to 6. Each display pixel 12lfj is coupled to a source of a low reference potential Gnd, for example, the ground, via an electrode 14i and to a source of a high reference potential Vcc via an electrode 16j . As an example, electrodes 14i are shown as being aligned along the rows in Figure 1 and electrodes 16j are shown as being aligned along the columns in Figure 1, the reverse layout being possible. The power supply voltage of the display screen corresponds to the voltage between high reference potential Vcc and low reference potential Gnd, and is noted Vcc like the high reference potential. Power supply voltage Vcc particularly depends on the arrangement of the light-emitting diodes and on the technology according to which the light-emitting diodes are manufactured. As an example, power supply voltage Vcc may be in the order of from 3.5 V to 5.5 V.

[0060] For each row, the display pixels 12ifj in the row are coupled to a row electrode 18i. For each column, the display pixels 12ifj in the column are coupled to a column electrode 20j. Display screen 10 comprises a selection circuit 22 coupled to row electrodes 18i and adapted to delivering a selection signal Comi on each row electrode 18±. Display screen 10 comprises a data delivery circuit 24 coupled to column electrodes 20j and adapted to delivering a data signal Dataj on each column electrode 20j. Selection circuit 22 and control circuit 24 are controlled by a circuit 26, for example comprising a microprocessor.

[0061] Figure 2 shows an example of a block diagram of a display pixel 12ifj of display screen 10. For a color display screen, display pixel 12ifj comprises at least three lightemitting circuits emitting radiations of different colors. Each light-emitting circuit comprises at least one lightemitting diode LED that is series-coupled to a controllablecurrent source CS , a single light-emitting circuit being shown in Figure 2 . Each light-emitting diode LED is series- coupled to a controllable current source CS , for example comprising a MOS transistor in series with a current source providing a constant current . In the present example , for each light-emitting diode LED, the anode of light-emitting diode LED receives high reference potential Vcc and the cathode of light-emitting diode LED is for example coupled to a terminal of controllable current source CS , the other terminal of controllable current source CS receiving low reference potential Gnd . In case of a monochrome display screen, each display pixel 12i fj can comprise a lightemitting circuit having a single light-emitting diode LED .

[0062] Display pixel 12i fj further comprises a driver circuit 40 for driving controllable current source CS . Driver circuit 40 may particularly comprise electronic components such as MOS transistors . Driver circuit 40 comprises a storage circuit 48 ( Color Data registers ) clocked by a clock signal Clk configured to store digital color signals R, G, B based on received digital signal Data . Digital color signals R, G, B comprise each a number NB of bits , from the most signi ficant bit , called MSB, to the least signi ficant bit , called LSB, and are representative of the image pixel color components to be displayed . Driver circuit 40 comprises a circuit 50 ( LED driver ) configured to control the controllable current sources CS coupled to light-emitting diodes LED with s ignals I_red, I_green, and I_blue , obtained from digital color signals R, G, B, and from a signal PWM . Signal Data can correspond to signal Dataj transmitted to display pixel 12i fj on column electrode 20j during a writing phase . Signal PWM can correspond to selection and timing signal Comi transmitted to display pixel 12i fj on row electrode 18i during a display phase .

[0063] Figure 3 shows timing diagrams of signal PWM and signals I_red_l, I_red_2, I_red_3, and I_red_4 corresponding to signal I_red provided by circuit 50 of display pixel 12ifj of Figure 2 for the display of four different digital color signals R. According to an embodiment, light-emitting diodes LED of display pixel 12lfj are controlled by pulse-width modulation. For this purpose, during a display cycle, signal PWM exhibits a succession of pulses P at logical state "1" which rates the operation of circuit 50 for the control of light-emitting diode LED by pulse-width modulation. The number of pulses P in the succession of pulses can correspond to the number NB+1. Each pair of successive pulses P delimits a duration Di, i being in the range from NB-1 to 0.

[0064] As an example, when current source CS corresponds to current source providing a constant current in series with a switch, the switch is closed or is opened according to the logical value "0" or "1" of each bit of digital color signal R, G, or B, from the most significant bit MSB to the least significant bit LSB, at the rate of the pulses P of signal PWM, the switch being maintained open or closed until the next pulse P of signal PWM. Therefore, controllable current source CS is switched on or off during NB successive durations Di according to the logical values of the bits of digital color signal R, G, or B. For example, current source CS can be switched on during a duration Di when the bit of the color digital data R, G, or B associated with this time interval is at logical value "1" and can be switched off during a duration Di when the bit of the color digital data R, G, or B associated with this time interval is at logical value "0".

[0065] In a display cycle, the duration Di, i being in the range from NB-1 to 0, between two successive pulses P ofsignal PWM is divided each time by two , so that the total duration for which the light-emitting diode LED is on depends on the value of digital color signal R, G, or B . The display phase of an image pixel can comprise two or more display cycles . That is to say the succession of pulses P of signal PWM shown in Figure 3 can be repeated until the display of another image pixel .

[0066] In Figure 3 , as an example , number NB is equal to 7 and only one display cycle is shown . Signal I_red_l is obtained for the display of an image pixel color component corresponding to color signal R equal to " 1010101" . Signal I_red_2 is obtained for the display of an image pixel color component corresponding to color signal R equal to " 0101010" . Signal I_red_3 is obtained for the display of an image pixel color component corresponding to color signal R equal to " 1111111" . Signal I_red_4 is obtained for the display of an image pixel color component corresponding to color signal R equal to " 0000000" .

[0067] Figure 4 shows a block diagram of an example of controllable current source CS of display pixel 12i fj of Figure 2 . In the present example , for each light-emitting diode LED, the anode of light-emitting diode LED receives high reference potential Vcc, and the cathode of lightemitting diode LED is for example coupled to a terminal of controllable current source CS , the other terminal of controllable current source CS receiving low reference potential Gnd . As a variation, the cathode of lightemitting diode LED receives low reference potential Gnd and the anode of light-emitting diode LED is coupled to a terminal of controllable current source CS , the other terminal of controllable current source CS receiving high reference potential Vcc . As an example , controllable current source CS comprises a switch SW1 that is series-coupled to a transistor Tl . Display pixel 12l fj further comprises a capacitor C for setting the voltage at the gate of transistor Tl . Capacitor C has a first electrode coupled, preferably connected, to the gate of transistor Tl , and a second electrode receiving low reference potential Gnd . The voltage at the gate of transistor Tl can correspond to the voltage across capacitor C . Switch SW1 is commanded by signals I_red ( or I_green or I_blue ) . Current ICs crossing light-emitting diode LED corresponds to the current at the drain of transistor Tl .

[0068] In operation, there can be current leakages at the level of capacitor C . In Figure 4 , possible current leakages are shown by a first constant current source LI and a second constant current source L2 . First constant current source LI has a first terminal receiving high reference potential Vcc and a second terminal connected to the first electrode of capacitor C . First constant current source LI provides a current LI to the first electrode of capacitor C . Second constant current source L2 has a first terminal connected to the first electrode of capacitor C and a second terminal connected to the second electrode of capacitor C . Second constant current source L2 draws a current L2 from the first electrode of capacitor C .

[0069] Figure 5 shows the evolution of current ICs over time during a display phase DP in a first configuration of the leakage currents and durations D5 to DO of the successive values of signal I_red, only one display cycle being shown . Duration D5 is associated to the MSB of digital color data R to be displayed and duration DO is associated to the LSB of digital color data R to be displayed . In the f irst configuration, the intensity of leakage current LI is inferior to the intensity of leakage current L2 , so that the voltage across capacitor C decreases with time . As anexample, current ICs decreases from 30 pA to 20 pA during the display phase. As an example, number NB is equal to 6. Digital color signal R can take 64 different values.

[0070] Figure 6 shows the evolution of the differential nonlinearity DNL of display pixel 12ifj with the evolution of current ICs shown in Figure 5 with respect to the value of digital color signal R indicated in decimal. The differential nonlinearity DNL describes the deviation between the two values of the mean current supplied to the light-emitting diode during a display phase corresponding to adjacent input digital values of digital color signal R. In the first configuration of the leakage currents, DNL is superior to 1 bit at some transitions between two adjacent input digital values, in particular when a high number of bits toggle between the two adjacent input digital values, for example at the transition between adjacent input digital values "011111" and "100000".

[0071] Figure 7 shows the evolution of brightness BR of display pixel 12ifj with the evolution of current ICs shown in Figure 5 with respect to the value of digital color signal R indicated in decimal. Ideally, brightness BR should be proportional to digital color signal R. However, Figure 5 shows that the evolution of brightness BR comprises sudden steep increases.

[0072] Figure 8 shows the evolution of current ICs over time during a display phase DP in a second configuration of the leakage currents and durations D5 to DO of the successive values of signal I_red, only one display cycle being shown. In the second configuration, the intensity of leakage current LI is superior to the intensity of leakage current L2, so that the voltage across capacitor C increases with time. As an example, current ICs increases from 20 pA to30 pA during the display phase. Moreover, Figure 8 shows signal I_red that is the same as in Figure 5.

[0073] Figure 9 shows the evolution of the differential nonlinearity DNL of display pixel 12ifj with the evolution of current ICs shown in Figure 8 with respect to digital color signal R indicated in decimal. In the second configuration of the leakage currents, DNL is inferior to -1 bit at some transitions between two adjacent input digital values, in particular when a high number of bits toggle between the two adjacent input digital values, for example at the transition between adjacent input digital values "011111" and "100000".

[0074] Figure 10 shows the evolution of brightness BR of display pixel 12ifj with the evolution of current ICs shown in Figure 8 with respect to the digital color signal R indicated in decimal. The curve of evolution of the brightness is non-monotonic.

[0075] With digital driving displays, there can be some problems in rendering dynamic images. When displaying moving pictures, the human eyes can perceive some grayscales that do not actually exist at the edge of the grayscales. This kind of grayscale disorder is called dynamic false contour (DFC) phenomenon. The dynamic false contour phenomenon is a kind of false visual perception formed on the retina when observing moving images in the digital driving displays. It does not exist on the image source actually.

[0076] Figure 11 shows a timing diagram of signal I_red for two successive frames Fl and F2 during which two successive image pixels are displayed by display pixel 12ifj . Each frame Fl, F2 comprises successively a writing phase WRT during which signal data Dataj are sent to display pixel12 irj , a display phase DP during which the image pixel is displayed by display pixel 12l fj , and a waiting phase of f , until the end of the frame Fl , F2 , during which no image pixel is displayed by display pixel 12i fj . As an example , number NB of bits of digital color signal R is equal to 6 . The first image pixel color component corresponds to digital color signal R equal to " 10000" ( gray level equal to " 16" ) and the second image pixel color component corresponds to digital color signal R equal to " 01111" ( gray level equal to " 15" ) . Each duration D4 to DO shown in gray for each frame Fl and F2 corresponds to switch SW1 of controllable current source CS being closed and each duration D4 to DO shown in white corresponds to switch SW1 of controllable current source CS being open .

[0077] The risk of occurrence of the dynamic false contour phenomenon is estimated using a criterium called turn-on period during one frame time over time , as it is explained hereafter . The risk of occurrence of the dynamic false contour phenomenon is reduced when the variations of the turn-on period during one frame time over time are reduced .

[0078] Figure 12 shows the evolution of the turn-on period TUP during one frame time over time for the display of the image pixels shown in Figure 11 . The x axis corresponds to the position P of the sliding window as it is explained hereafter . A high variation of turn-on period TUP can be measured .

[0079] Figure 13 illustrates a method for determining the turn-on period TUP during one frame over time . Successive first and second frames are considered . The first frame FRAME1 corresponds to the display of the first image pixel color component corresponding to digital color signal R equal to " 10000" ( gray level equal to " 16" ) and the secondframe FRAME2 corresponds to the display of the second image pixel color component corresponding to digital color signal R equal to "01111" (gray level equal to "15") . Each frame is divided in a number NF of steps, a step corresponding to duration DO. In the example of Figure 13, NF is equal to 43. A sliding window is shifted from the first frame to the second frame one step at a time. For each position P of the sliding window, the turn-on period TUP is equal to the number of steps in the sliding window for which lightemitting diode LED is switched on for the first and second frames is determined.

[0080] Figure 14 shows a block diagram of an embodiment of the storage circuit 48 of display pixel 12ifj of Figure 2 that allows the display phase shown in Figures 3, 5, 8, or 11 to be obtained.

[0081] Storage circuit 48 comprises memory cells DFF0to DFFNB_ i. Each memory cell DFFi, i being in the range from 0 to NB-1, is configured to store one bit of digital color signal R, G, or B. According to an embodiment, each memory cell DEFi corresponds to a flip-flop, for example a D flip-flop having an input D and an output Q, clocked by a signal Clk or PWM according to the operation phase of the display pixel. For each memory cell DFFi, i being in the range from 0 to NB-2, output Q of memory cell DFFBis connected to input D of memory cell DFF1+1. Output Q of memory cell DFFNB_ i provides signal I_red. Storage circuit 48 further comprises a multiplexer MUX commanded by a signal Mode. Multiplexer MUX comprises a first input "0" receiving signal Data, a second input "1" connected to output Q of memory cell DFFNB-I, and an output connected to input D of memory cell DFF0. When signal Mode is at a first logical value, for example "0", multiplexer MUX sends signal Data at its output. When signal Mode is at a second logicalvalue, for example "1", multiplexer MUX sends the signal provided by memory cell DFFNB-I at its output.

[0082] During a writing phase, signal Mode is at logical value "0" and memory cell DFFi, i being in the range from 0 to NB-1, are clocked by signal Clk. Signal Data corresponds to the bits of digital color signal R that are successively provided, from the most significant bit to the least significant bit, to multiplexer MUX, and that move through the succession of memory cells DFFi, i being in the range from 0 to NB-1, so that, at the end of the writing phase, the most significant bit is stored in memory cell DFFNB-I and the least significant bit is stored in memory cell DFF0.

[0083] During a display phase, signal Mode is set at logical value "1" and memory cells DFFi, 1 being in the range from 0 to NB-1, are clocked by signal PWM. Multiplexer MUX provides at its output the signal provided by memory cell DFFNB-I . Therefore, signal I_red is successively equal to each bit of digital color signal R from the most significant bit to the least significant bit.

[0084] It would be desirable to overcome the disadvantages of existing display pixels explained before as regards DNL and DFC while still keeping a display pixel having a storage circuit comprising memory cells corresponding to flipflops .

[0085] In order to prevent the voltage across capacitor C from varying, it can be necessary to provide a refresh circuit that refreshes the voltage across capacitor C.

[0086] Figure 15 shows a block diagram of an embodiment of a refresh circuit 60 of display pixel 12ifj of Figure 2 configured to refresh the voltage across capacitor C. Refresh circuit 60 comprises a resistor R in series with aswitch SW2 commanded by a binary signal Rsh . Signal Rsh is provided by a refresh command circuit 62 . Refresh circuit 60 further comprises a current mirror comprising MOS transistors T2 and T3 , for example PMOS transistors . The sources of transistors T2 and T3 receive high reference voltage Vcc . The drain of transistor T2 is coupled, preferably connected, to a terminal of resistor R . The other terminal of resistor R is coupled, preferably connected, to a terminal of switch SW2 . The other terminal of switch SW2 receives low voltage reference Gnd . The gate of transistor T2 is coupled, preferably connected, to the gate of transistor T3 and to the drain of transistor T2 . Refresh circuit 60 further comprises a MOS transistor T4 , for example an NMOS transistor . The drain of transistor T4 is coupled, preferably connected, to the drain of transistor T3 . The source of transistor T4 receives low voltage reference Gnd . The gate of transistor T4 is connected to the drain of transistor T4 . Refresh circuit 60 further comprises a switch SW3 commanded by signal Rsh . A terminal of switch SW3 is coupled, preferably connected, to the gate of transistor T4 . The other terminal of switch SW3 is coupled, preferably connected, to the first electrode of capacitor C . The ratio of the si zes between transistor T2 and transistor T3 is l : n . The ratio of the si zes between transistor T1 and transistor T4 is l : m .

[0087] Refresh command circuit 62 can be complex when a refresh of the voltage across capacitor C is to be performed frequently, in particular during the display phase .

[0088] According to an embodiment , the display phase of an image pixel comprises a least a first display cycle and a second display cycle and the order of the bits of the digital color signal R, G, or B that are displayed in the first display cycle is di f ferent from the order of the bitsof the digital color signal R, G, or B that are di splayed in the second display cycle . This means that for a digital color signal R, G, or B having NB bits , each bit of rank i being associated with duration Di , i being in the range from NB- 1 to 0 , the order of the successive durations Di during which the controllable current source CS is turned on or of f in the first display cycle is di f ferent from the order of the successive durations Di during which the controllable current source CS is turned on or of f in the second display cycle .

[0089] According to an embodiment that is illustrated by Figure 16 described hereafter, the order of the durations Di in the first display cycle is inverted with respect to the order of the durations Di in the second display cycle , possibly with the exception of the duration at the end of the first display cycle that may be not repeated at the beginning of the second display cycle . That means that the first duration of the first display cycle is the last duration of the second display cycle , the second duration of the first display cycle is the penultimate duration of the second display cycle , and so on . The last duration of the first display cycle can be the first duration of the second display cycle , or the last duration of the first display cycle is not present in the second display cycle and the first duration of the second display cycle is the penultimate duration of the first display cycle .

[0090] Figure 16 shows the evolution of current ICs over time in the first configuration of leakage currents ( leakage current LI superior to leakage current L2 ) and durations of the successive values of signal I_red with a display phase DP of an image pixel comprising successive first and second display cycles Cl and C2 , the order of the bits of the digital color signal R displayed in the first displaycycle Cl being the opposite of the order of the bits of the digital color signal R displayed in the second display cycle C2. According to an embodiment, in the first display cycle Cl, switch SW1 of controllable current source CS is commanded by the bits of digital color signal R successively from the most significant bit to the least significant bit and, in the second display cycle C2, switch SW1 of controllable current source CS is commanded by the bits of digital color signal R successively from the least significant bit to the most significant bit. In the present embodiment, the least significant bit LSB is displayed once at the end of the first display cycle and once at the beginning of the second display cycle. As a variation, the least significant bit may be displayed only once at the end of the first display cycle, the second display cycle beginning with the bit after the least significant bit (LSB+1) .

[0091] Figure 17 shows the evolution of the differential nonlinearity DNL of the display pixel 12irj with the evolution of current ICs shown in Figure 16 with respect to the value of digital color signal R indicated in decimal. Differential nonlinearity DNL is equal to zero for each value of digital color signal R.

[0092] Figure 18 shows the evolution of the brightness BR of display pixel 12lfj with the evolution of current ICs shown in Figure 16 with respect to the value of color signal R, G, or B indicated in decimal. Brightness BR is proportional to the value of color signal R, G, or B. There is no sudden steep variations.

[0093] Figure 19 shows the evolution of current ICs over time during a display phase in the second configuration (leakage current LI inferior to leakage current L2) and durationsof the successive values of signal I_red with a display phase being the same as in Figure 16 .

[0094] Figure 20 shows the evolution of the di f ferential nonlinearity DNL of the display pixel 12i fj with the evolution of current ICs shown in Figure 18 with respect to the value of digital color signal R indicated in decimal . Di f ferential nonlinearity DNL is equal to zero for each value of digital color signal R .

[0095] Figure 21 shows the evolution of the brightness BR of display pixel 12i fj with the evolution of current ICs shown in Figure 19 with respect to the value of color signal R, G, or B indicated in decimal . Brightness BR is proportional to the value of color signal R, G, or B . There is no sudden steep variations .

[0096] The DNL is kept at zero regardless of the type of leakage of capacitor C . There is no need for a complex refresh circuit for refreshing the voltage across capacitor C .

[0097] Figure 22 is a figure similar to Figure 11 except that , for each frame Fl and F2 , the display phase DP comprises two display cycles Cl and C2 according to the embodiment shown in Figures 16 and 19 , and except that the least signi ficant bit displayed during duration DO is not displayed twice but only once . In particular, in the first display cycle Cl , switch SW1 of controllable current source CS is commanded by the bits of digital color signal R successively from the most signi ficant bit during duration D4 to the least signi ficant bit during duration DO and, in the second display cycle C2 , switch SW1 of controllable current source CS is commanded by the bits of digital color signal R successively from the bit after the least signi ficant bit during duration DI to the most signi ficantbit during duration D4 . It can be advantageous that the least signi ficant bit displayed during duration DO is displayed only once , when it can be di f ficult to generate successive pulses to provide the two successive durations DO , for example due to latencies in the operation o f the display screen .

[0098] Figure 23 shows the evolution of the turn-on period TUP over time for the display of the image pixels shown in Figure 22 . The units of the time axis are arbitrary . The extrema of turn-on period TUP shown in Figure 23 are reduced with respect to turn-on period TUP shown in Figure 12 . The risk of occurrence of the dynamic false contour phenomenon is therefore advantageously reduced .

[0099] Figure 24 is a figure similar to Figure 22 except that , for each frame Fl and F2 , the display phase DP comprises four display cycles Cl , C2 , C3 , and C4 . According to an embodiment , in the first display cycle Cl , switch SW1 of controllable current source CS is commanded by the bits of the digital color signal R successively from the most signi ficant bit during duration D4 to the bit after the least signi ficant bit during duration DI . In the second display cycle C2 , switch SW1 of controllable current source CS is commanded by the bits of the digital color signal R successively from the second bit after the least signi ficant bit during duration D2 to the most signi ficant bit during duration D4 , and then by the least signi ficant bit during DO . The third display cycle C3 is identical to the first display cycle Cl and the fourth display cycle C4 is identical to the second display cycle C2 .

[0100] Figure 25 shows the curve of evolution of the turn-on period TUP over time for the display of the image pixels shown in Figure 24 . The extrema of turn-on period TUP shownin Figure 25 are reduced with respect to turn-on period TUP shown in Figure 25 . The risk of occurrence of the dynamic false contour phenomenon is therefore further advantageously reduced .

[0101] Figure 26 shows the durations of the successive values of signal I_red with a display phase of an image pixel comprising successive first and second display cycles Cl and C2 according to three embodiments .

[0102] In the upper timing diagram, in first display cycle Cl , switch SW1 of controllable current source CS is commanded by the bits of the digital color signal R successively from the least signi ficant bit during duration DO to the most signi ficant bit during duration D4 and, in second display cycle C2 , switch SW1 of controllable current source CS is commanded by the bits of the digital color signal R successively from the most signi ficant bit during duration D4 to the least signi ficant bit during duration DO . Display phase is followed by a waiting phase of f .

[0103] In the embodiments previously disclosed, waiting phase of f follows the display phase . However, when the display phase comprises at least two display cycles , a waiting phase of f can be provided after each display cycle of the display phase .

[0104] In the middle timing diagram, in first display cycle Cl , switch SW1 of controllable current source CS is commanded by the bits of the digital color signal R successively from the least signi ficant bit during duration DO to the most signi ficant bit during duration D4 , first display cycle Cl being followed by a waiting phase of f , and, in second display cycle C2 , switch SW1 of controllable current source CS is commanded by the bits of the digital color signal R successively from the most signi ficant bitduring duration D4 to the least significant bit followed during duration DO, second display cycle C2 being followed by a waiting phase off.

[0105] In the lower timing diagram, in first display cycle Cl, switch SW1 of controllable current source CS is commanded by the bits of the digital color signal R successively from the most significant bit during duration D4 to the least significant bit during duration DO, first display cycle Cl being followed by a waiting phase off and, in second display cycle C2, switch SW1 of controllable current source CS is commanded by the bits of the digital color signal R successively from the least significant bit during duration DO to the most significant bit during duration D4, second display cycle C2 being followed by a waiting phase off.

[0106] Figure 27 shows four examples of timing diagrams of signal I_red a display phase comprising first, second, third, and fourth display cycles Cl, C2, C3, and C4 according to four embodiments.

[0107] In the uppest timing diagram, in first display cycle Cl, switch SW1 of controllable current source CS is commanded by the bits of the digital color signal R successively from the most significant bit during duration D4 to the least significant bit during duration DO, in second display cycle C2, switch SW1 of controllable current source CS is commanded by the bits of the digital color signal R successively from the least significant bit during duration DO to the most significant bit during duration D4, third display cycle C3 being identical to first display cycle Cl, and fourth display cycle C4 being identical to second display cycle C2.

[0108] In the upper middle timing diagram, in first display cycle Cl , switch SW1 of controllable current source CS is commanded by the bits of the digital color signal R successively from the least signi ficant bit during duration DO to the most signi ficant bit during duration D4 , in second display cycle C2 , switch SW1 of controllable current source CS is commanded by the bits of the digital color signal R successively from the most signi ficant bit during duration D4 to the least signi ficant bit during duration DO , third display cycle C3 being identical to f irst display cycle Cl , and fourth display cycle C4 being identical to second display cycle C2 .

[0109] In the lower middle timing diagram, in first display cycle Cl , switch SW1 of controllable current source CS is commanded by the bits of the digital color signal R successively from the most signi ficant bit during duration D4 to the least signi ficant bit during duration DO , in second display cycle C2 , switch SW1 of controllable current source CS is commanded by the bits of the digital color signal R successively from the least signi ficant bit during duration DO to the most signi ficant bit during duration D4 , third display cycle C3 being identical to second display cycle C2 , and fourth display cycle C4 being identical to first display cycle Cl .

[0110] In the lowest timing diagram, in first display cycle Cl , switch SW1 of controllable current source CS is commanded by the bits of the digital color signal R successively from the least signi ficant bit during duration DO to the most signi ficant bit during duration D4 , in second display cycle C2 , switch SW1 of controllable current source CS is commanded by the bits of the digital color signal R successively from the most signi ficant bit during duration D4 to the least signi ficant bit during duration DO , thirddisplay cycle C3 being identical to second display cycle C2, and fourth display cycle C4 being identical to first display cycle Cl.

[0111] Figure 28 shows a block diagram of an embodiment of the storage circuit 48 of display pixel 12lfj of Figure 2 that allows the display phase shown in Figure 16 to be obtained .

[0112] Storage circuit 48 comprises memory cells DFF0to DFFNB_1. Each memory cell DFFi, i being in the range from 0 to NB-1, is configured to store one bit of digital color signal R, G, or B. According to an embodiment, each memory cell DFFi corresponds to a flip-flop, for example a D flip-flop having an input D and an output Q, clocked by a signal Clk or PWM according to the operation phase of the display pixel. Storage circuit 48 further comprises multiplexers MUX0to MUXNB-I commanded by a signal Dir. Each multiplexer MUXi, i being in the range from 1 to NB-2, comprises a first input "0" connected to output Q of memory cell DEEi-i, a second input "1" connected to output Q of memory cell DEEi+i and an output connected to input D of memory cell DFFi. When signal Dir is at a first logical value, for example "0", multiplexer MUX±, i being in the range from 1 to NB-2, sends the signal provided by memory cell DFFi-! at its output. When signal Dir is at a second logical value, for example "1", multiplexer MUX±, i being in the range from 1 to NB-2, sends the signal provided by memory cell DFF1+1at its output. Multiplexer MUXNB_! comprises a first input "0" connected to output Q of memory cell DFFNB-2, a second input "1" connected to output Q of memory cell DFF0and an output connected to input D of memory cell DFFNB-I . When signal Dir is at the first logical value, for example "0", multiplexer MUXNB-I sends the signal provided by memory cell DFFNB-2at its output. When signal Dir is at the second logical value,for example "1", multiplexer MUXNB_i sends the signal provided by memory cell DFF0at its output. Multiplexer MUX0comprises a first input "0" connected to output Q of memory cell DFFNB-I, a second input "1" connected to output Q of memory cell DFFi. When signal Dir is at the first logical value, for example "0", multiplexer MUX0sends the signal provided by memory cell DFFNB-I at its output. When signal Dir is at the second logical value, for example "1", multiplexer MUX0sends the signal provided by memory cell DFFi at its output.

[0113] Storage circuit 48 further comprises a multiplexer MUXI commanded by a signal Mode. Multiplexer MUXI comprises a first input "0" receiving signal Data, a second input "1" connected to output Q of multiplexer MUX0and an output connected to input D of memory cell DFF0. When signal Mode is at a first logical value, for example "0", multiplexer MUXI sends signal Data at its output. When signal Mode is at a second logical value, for example "1", multiplexer MUXI sends the signal provided by multiplexer MUX0at its output. Storage circuit 48 further comprises a multiplexer MUXO commanded by signal Dir. Multiplexer MUXO comprises a first input "0" connected to output Q of memory cell DFFNB_ !, a second input "1" connected to output Q of memory cell DFF0, and an output providing signal I_red. When signal Dir is at the first logical value, for example "0", multiplexer MUXO sends the signal provided by memory cell DFFNB_i at its output. When signal Dir is at the second logical value, for example "1", multiplexer MUXO sends the signal provided by memory cell DFF0at its output.

[0114] During a writing phase, signal Mode is at logical value "0", signal Dir is at logical value "0", and memory cells DFFi, i being in the range from 0 to NB-1, are clocked by signal Clk. Signal Data corresponds to the bits ofdigital color signal R that are successively provided, from the most significant bit to the least significant bit, to multiplexer MUXI . The bits provided by multiplexer MUXI move through the succession of memory cells DFFi, i being in the range from 0 to NB-1, so that, at the end of the writing phase, the most significant bit is stored in memory cell DFFNB-I and the least significant bit is stored in memory cell DFF0.

[0115] During a display phase, signal Mode is set at logical value "1" and memory cells DFFi, i being in the range from 0 to NB-1, are clocked by signal PWM. Multiplexer MUXI provides at its output the signal provided by multiplexer MUXx . In the first display cycle, signal Dir is at logical value "0", so that multiplexer MUXO provides at its output the signal provided by memory cell DFFNB-I . Moreover, each multiplexer MUXi, i being in the range from 1 to NB-1, sends the signal provided by memory cell DFFi-! at its output. Therefore, signal I_red is successively equal to each bit of digital color signal R from the most significant bit to the least significant bit. In the second display cycle, signal Dir is at logical value "1", so that multiplexer MUXO provides at its output the signal provided by memory cell DFF0. Moreover, each multiplexer MUXB, i being in the range from 0 to NB-2, sends the signal provided by memory cell DFF1+1at its output. Therefore, signal I_red is successively equal to each bit of digital color signal R from the least significant bit to the most significant bit.

[0116] Signals Mode and Dir can be generated by driver circuit 40 based on timing signal Comi and data signal Dataj . Storage circuit 48 shown in Figure 28 advantageously has a structure having flip-flop memory cells DFF0to DFFNB_ !, as with storage circuit 48 shown in Figure 14.

[0117] Various embodiments and variants have been described .Those skilled in the art will understand that certain features of these various embodiments and variants may be combined, and other variants will occur to those skilled in the art .

[0118] Finally, the practical implementation of the described embodiments and variations is within the abilities of those skilled in the art based on the functional indications given hereabove .

Claims

CLAIMS1. A display pixel (12ifj) comprising at least one lightemitting device (LED) , a controllable current source (CS) supplying said light-emitting device (LED) with a current, a driver circuit (50) configured to turn on or off the controllable current source (CS) , and to receive bits of a digital color signal (R, G, B) associated to an image pixel to be displayed, and a storage circuit (48) configured to store said digital color signal (R, G, B) , said digital color signal (R, G, B) comprising a number NB of bits each having a rank from the least significant bit of the digital color signal to the most significant bit of the digital color signal, each bit of the digital color signal having a first logical value or a second logical value, said storage circuit (48) being configured to provide to the driver circuit (50) , during a display phase of the image pixel, at least some of said NB bits in a first order and then in a second order, different from the first order, said driver circuit (50) being configured, during the display phase of the image pixel, for each received bit, to turn on the controllable current source (CS) when said bit is at the first logical value during a duration that depends on the rank of said bit or to turn off the controllable current source (CS) during said duration when said bit is at the second logical value, said durations increasing from the least significant bit to the most significant bit.

2. The display pixel according to claim 1, wherein said driver circuit (50) is configured to receive at least some of said NB bits in the first order according to decreasing ranks of the bits and in the second order according to increasing ranks of the bits, or inversely.

3. The display pixel according to claim 1 or 2, wherein said driver circuit (50) is configured to receive at least some of said NB bits in the first order comprising successive first, second, and third bits, the rank of the second bit being higher than the rank of the first bit and the rank of the third bit, or the rank of the second bit being lower than the rank of the first bit and the rank of the third bit .

4. The display pixel according to any of claims 1 to 3, wherein said drive circuit (50) is configured, after the reception of said bits in the second order, to further receive said bits in a third order and then in a fourth order, different from the third order.

5. The display pixel according to claim 4, wherein the third order is identical to the first order and the fourth order is identical to the second order, or wherein the third order is identical to the second order and the fourth order is identical to the first order.

6. The display pixel according to any of claims 1 to 5, wherein the controllable current source (CS) comprises a switch (SW1) in series with a constant current source (Tl) , the driver circuit (50) being configured, for each received bit, to turn on said switch (SW1) during said duration when said bit is at the first logical value or to turn off said switch (SW1) during said duration when said bit is at the second logical value.

7. The display pixel according to claim 6, wherein the constant current source (Tl) comprises a MOS transistor (Tl) and a capacitor (Cl) , said MOS transistor (Tl) having its drain or its source coupled to said switch (SW1) andsaid capacitor (Cl) having an electrode connected to the gate of said MOS transistor (Tl) .

8. The display pixel according to any of claims 1 to 7, wherein the storage circuit (48) comprises NB memory cells DFFB, i varying from 0 to NB-1, for storing the bits of the digital color signal (R, G, B) , wherein each memory cell DFFBis a flip-flop clocked by a timing signal (CLK, PWM) .

9. The display pixel according to claim 8, wherein the storage circuit (48) comprises NB first multiplexers MUXB, i varying from 0 to NB-1, each being controlled by a control signal (Dir) , each first multiplexer MUXi, i being in the range from 1 to NB-2, comprising a first input connected to the output of memory cell DFFi-i, a second input connected to the output of memory cell DFFi+1and an output connected to the input of memory cell DFFi, wherein each first multiplexer MUXi, i being in the range from 1 to NB-2, is configured to send the signal provided by memory cell DFFB_1 at its output when the control signal (Dir) is at a first logical value, and to send the signal provided by memory cell DFFi+1at its output when the control signal (Dir) is at a second logical value, wherein first multiplexer MUXNB_ ! comprises a first input connected to the output of memory cell DFFNB-2, a second input connected to the output of memory cell DFF0and an output connected to the input of memory cell DFFNB-I, wherein first multiplexer MUXNB-! is configured to send the signal provided by memory cell DFFNB_2 at its output when the control signal (Dir) is at the first logical value, and to send the signal provided by memory cell DFF0at its output when the control signal (Dir) is at the second logical value, wherein first multiplexer MUX0comprises a first input connected to the output of memory cell DFFNB-X, a second input connected to the outputof memory cell DFFBand wherein first multiplexer MUX0is configured to send the signal provided by memory cell DFFNB_ i at its output when the control signal (Dir) is at the first logical value, and to send the signal provided by memory cell DFFBat its output when the control signal (Dir) is at the second logical value.

10. The display pixel according to claim 9, wherein the storage circuit (48) comprises a second multiplexer (MUXO) , controlled by the control signal (Dir) and comprising a first input connected to the output of memory cell DFFNB-I, a second input connected to the output of memory cell, and an output providing said bits to the driver circuit (50) , the second multiplexer (MUXO) being configured to send the signal provided by memory cell DFFNB-X at its output when the control signal (Dir) is at the first logical value, and to send the signal provided by memory cell DFF0at its output when the control signal (Dir) is at the second logical value.

11. The display pixel according to any of claims 1 to 10, wherein said storage circuit (48) is configured to provide to the driver circuit (50) all the bits of the digital color signal in the first order and then in the second order except for the least significant bit of the digital color signal that is provided only once.

12. A display screen (10) comprising: display pixels (12lfj) according to any of claims 1 to 11; first electrodes (18B) coupled to the display pixels (12lfj) ; a first circuit (22) for delivering a selection signal (Comi) on each first electrode for the selection of the display pixels (12ifj) coupled to the first electrode; second electrodes (20j) coupled to the display pixels ( 121 , j ) ; anda second circuit (24) for delivering data signals (Dataj) on the second electrodes.

13. A method for commanding a display pixel (12ifj) comprising at least one light-emitting device (LED) , a controllable current source (CS) supplying said lightemitting device (LED) with a current, a driver circuit (50) configured to turn on or off the controllable current source (CS) , and to receive bits of a digital color signal (R, G, B) associated to an image pixel to be displayed, and a storage circuit (48) configured to store said digital color signal (R, G, B) , said digital color signal (R, G, B) comprising a number NB of bits each having a rank from the least significant bit of the digital color signal to the most significant bit of the digital color signal, each bit of the digital color signal having a first logical value or a second logical value, the method comprising the steps of providing, during a display phase of the image pixel, by the storage circuit (48) to the driver circuit (50) at least some of said NB bits in a first order and then in a second order, different from the first order, and having said driver circuit (50) , during the display phase of the image pixel, for each received bit, to turn on the controllable current source (CS) when said bit is at the first logical value during a duration that depends on the rank of said bit or to turn off the controllable current source (CS) during said duration when said bit is at the second logical value, said durations increasing from the least significant bit to the most significant bit.

14. The method according to claim 13, wherein the controllable current source (CS) comprises a switch (SW1) in series with a constant current source (Tl) , wherein the constant current source (Tl) comprises a MOS transistor(Tl) and a capacitor (Cl) , wherein the refresh of the voltage across the capacitor (Cl) is prevented while the storage circuit (48) is providing to the driver circuit (50) at least some of said NB bits in the first order and then in the second order.

Images