Shift register unit, display panel and drive method therefor, and display apparatus

Abstract

Disclosed in the present application are a shift register unit, a display panel and a drive method therefor, and a display apparatus. The shift register unit comprises an input sub-circuit, a control sub-circuit, a first output sub-circuit and a second output sub-circuit, wherein the input sub-circuit is configured to provide a signal of an input signal end to a third node in response to signals of a first clock signal end and a third clock signal end; the control sub-circuit is configured to control signals of a first node and a second node in response to signals of a first power source signal end, a second power source signal end, the first clock signal end, a second clock signal end and the third clock signal end; the first output sub-circuit is configured to cause a cascaded output end to output a cascaded signal in response to the signals of the first node and the second node; and the second output sub-circuit is configured to cause a drive output end to output a gate scanning signal in response to the signals of the first node and the second node.

Description

Shift register unit, display panel and driving method thereof, and display device Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a shift register unit, a display panel and a driving method thereof, and a display device. Background Art

[0002] In the current display industry, to save power, many manufacturers have proposed a zoned frequency conversion solution. This involves dividing a display panel into multiple zones, each with a different refresh rate. This allows the refreshed zone to update while the non-refreshed zone retains the previous frame's data, further conserving power.

[0003] The circuit design of partition refresh drive GOA is the key to realize partition refresh.

[0004] Summary of the Invention

[0005] The purpose of the present application is to provide a shift register unit, a display panel and a driving method thereof, and a display device that can realize partition refresh.

[0006] The present application discloses a shift register unit, which includes:

[0007] an input subcircuit connected to the third node, the input signal terminal, the first clock signal terminal, and the third clock signal terminal, and configured to provide the signal of the input signal terminal to the third node in response to the signals of the first clock signal terminal and the third clock signal terminal;

[0008] a control subcircuit connected to the third node, the first node, the second node, the first power signal terminal, the second power signal terminal, the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal, and configured to control the signals of the first node and the second node in response to the signals of the first power signal terminal, the second power signal terminal, the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal, and to provide the signal of the third node to the first node or the second node;

[0009] a first output sub-circuit connected to the first node, the second node, the third clock signal terminal, the first power signal terminal, and the cascade output terminal, and configured to respond to signals of the first node and the second node so that the cascade output terminal outputs a cascade signal;

[0010] The second output sub-circuit is connected to the first node, the second node, the control signal terminal, the first power signal terminal and the driving output terminal, and is configured to respond to the signals of the first node and the second node to enable the driving output terminal to output a gate scanning signal.

[0011] In some embodiments, the second output sub-circuit includes:

[0012] A first output module, connected to the control signal terminal, the first node, and the driving output terminal, is configured to transmit the signal of the control signal terminal to the driving output terminal under the control of the first node;

[0013] The second output module is connected to the first power signal terminal, the second node and the driving output terminal, and is configured to transmit the signal of the first power signal terminal to the driving output terminal under the control of the second node.

[0014] In some embodiments, the first output module includes a fourteenth transistor, a first electrode of the fourteenth transistor is connected to the control signal terminal, a second electrode of the fourteenth transistor is connected to the drive output terminal, and a control electrode of the fourteenth transistor is connected to the second node.

[0015] In some embodiments, the second output module includes a fifteenth transistor, a first electrode of the fifteenth transistor is connected to the first power signal terminal, a second electrode of the fifteenth transistor is connected to the drive output terminal, and a control electrode of the fifteenth transistor is connected to the second node.

[0016] In some embodiments, the first output sub-circuit includes:

[0017] a fourth transistor, wherein a first electrode of the fourth transistor is connected to the third clock signal terminal, a second electrode of the fourth transistor is connected to the cascade output terminal, and a control electrode of the fourth transistor is connected to the first node;

[0018] A fifth transistor, wherein a first electrode of the fifth transistor is connected to the first power signal terminal, a second electrode of the fifth transistor is connected to the cascade output terminal, and a control electrode of the fifth transistor is connected to the second node.

[0019] In some embodiments, the first output sub-circuit further includes a third capacitor, a first end of the third capacitor is connected to the first electrode of the fourth transistor, and a second end of the third capacitor is connected to the control electrode of the fourth transistor; and / or,

[0020] The first output sub-circuit further includes a fourth capacitor, a first end of the fourth capacitor is connected to the cascade output end, and a second end of the fourth capacitor is connected to the first power signal end.

[0021] In some embodiments, the input sub-circuit includes a thirteenth transistor and a second transistor:

[0022] A first electrode of the thirteenth transistor is connected to the input signal terminal, a second electrode of the thirteenth transistor is connected to the first electrode of the second transistor, and a control electrode of the thirteenth transistor is connected to the third clock signal terminal;

[0023] The second electrode of the second transistor is connected to the third node, and the control electrode of the second transistor is connected to the first clock signal terminal.

[0024] In some embodiments, the control subcircuit includes a first control submodule, a first voltage stabilization module, and a second voltage stabilization module:

[0025] The first control submodule is connected to the third node, the fourth node, the fifth node, the first power signal terminal, the second power signal terminal, the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal, and is configured to control the signals of the fourth node and the fifth node in response to the signals of the first power signal terminal, the second power signal terminal, the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal, and to provide the signal of the third node to the fourth node or the fifth node;

[0026] The first voltage stabilizing module is connected to the fourth node, the first node and the first power signal terminal, and is configured to provide the voltage of the fourth node to the first node in response to a signal from the first power signal terminal;

[0027] The second voltage stabilizing module is connected to the fifth node, the second node and the first power signal terminal, and is configured to provide the voltage of the fifth node to the second node in response to a signal of the first power signal terminal.

[0028] In some embodiments, the first control submodule includes a first transistor, a sixth transistor, an eighth transistor, a ninth transistor, a tenth transistor, a third transistor, a seventh transistor, an eleventh transistor, a twelfth transistor, and a first capacitor and a second capacitor; wherein,

[0029] The first electrode of the first transistor is connected to the first clock signal terminal, the second electrode of the first transistor is connected to the sixth node, and the control electrode of the first transistor is connected to the third node;

[0030] A first electrode of the sixth transistor is connected to the first power signal terminal, a second electrode of the sixth transistor is connected to the sixth node, and a control electrode of the sixth transistor is connected to the first clock signal terminal;

[0031] A first electrode of the eighth transistor is connected to the sixth node, a second electrode of the eighth transistor is connected to the control electrode of the ninth transistor, and the control electrode of the eighth transistor is connected to the first power signal terminal;

[0032] The first electrode of the ninth transistor is connected to the second clock signal terminal, and the second electrode of the ninth transistor is connected to the first electrode of the tenth transistor;

[0033] The second electrode of the tenth transistor is connected to the fourth node, and the control electrode of the tenth transistor is connected to the second clock signal terminal;

[0034] A first electrode of the third transistor is connected to the second clock signal terminal, a second electrode of the third transistor is connected to the second electrode of the seventh transistor, and a control electrode of the third transistor is connected to the fifth node;

[0035] The first electrode of the seventh transistor is connected to the second power signal terminal, and the control electrode of the seventh transistor is connected to the sixth node;

[0036] The first electrode of the eleventh transistor is connected to the third node, the second electrode of the eleventh transistor is connected to the fifth node, and the control electrode of the eleventh transistor is connected to the first power signal terminal;

[0037] A first electrode of the twelfth transistor is connected to the third clock signal terminal, a second electrode of the twelfth transistor is connected to the fourth node, and a control electrode of the twelfth transistor is connected to the fifth node;

[0038] A first electrode of the first capacitor is connected to the fifth node, and a second electrode of the first capacitor is connected to the second electrode of the third transistor;

[0039] A first electrode of the second capacitor is connected to the control electrode of the ninth transistor, and a second electrode of the second capacitor is connected to the second electrode of the ninth transistor;

[0040] The first voltage stabilizing module includes a sixteenth transistor, a first electrode of the sixteenth transistor is connected to the fourth node, a second electrode of the sixteenth transistor is connected to the first node, and a control electrode of the sixteenth transistor is connected to the first power signal terminal;

[0041] The second voltage stabilization module includes a seventeenth transistor, a first electrode of the seventeenth transistor is connected to the fifth node, and a second electrode of the seventeenth transistor is connected to the first node.

[0042] In some embodiments, the control subcircuit includes a second control submodule, a third voltage stabilization module, and a fourth voltage stabilization module:

[0043] The second control submodule is connected to the third node, the fourth node, the first node, the first power signal terminal, the second power signal terminal, the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal, and is configured to control the signal of the fourth node in response to the signals of the first power signal terminal, the second power signal terminal, the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal, and provide the signal of the third node to the fourth node;

[0044] The third voltage stabilizing module is connected to the fourth node, the first node and the first power signal terminal, and is configured to provide the voltage of the fourth node to the first node in response to a signal from the first power signal terminal;

[0045] The fourth voltage stabilizing module is connected to the third node, the second node and the first power signal terminal, and is configured to provide the voltage of the third node to the second node in response to a signal of the first power signal terminal.

[0046] In some embodiments, the second control submodule includes a first transistor, a sixth transistor, an eighth transistor, a ninth transistor, a tenth transistor, a third transistor, a seventh transistor, a twelfth transistor, and a first capacitor and a second capacitor; wherein,

[0047] The first electrode of the first transistor is connected to the first clock signal terminal, the second electrode of the first transistor is connected to the sixth node, and the control electrode of the first transistor is connected to the third node;

[0048] A first electrode of the sixth transistor is connected to the first power signal terminal, a second electrode of the sixth transistor is connected to the sixth node, and a control electrode of the sixth transistor is connected to the first clock signal terminal;

[0049] A first electrode of the eighth transistor is connected to the sixth node, a second electrode of the eighth transistor is connected to the control electrode of the ninth transistor, and the control electrode of the eighth transistor is connected to the first power signal terminal;

[0050] The first electrode of the ninth transistor is connected to the second clock signal terminal, and the second electrode of the ninth transistor is connected to the first electrode of the tenth transistor;

[0051] The second electrode of the tenth transistor is connected to the fourth node, and the control electrode of the tenth transistor is connected to the second clock signal terminal;

[0052] A first electrode of the third transistor is connected to the second clock signal terminal, a second electrode of the third transistor is connected to the second electrode of the seventh transistor, and a control electrode of the third transistor is connected to the third node;

[0053] The first electrode of the seventh transistor is connected to the second power signal terminal, and the control electrode of the seventh transistor is connected to the sixth node;

[0054] A first electrode of the twelfth transistor is connected to the third clock signal terminal, a second electrode of the twelfth transistor is connected to the fourth node, and a control electrode of the twelfth transistor is connected to the third node;

[0055] A first electrode of the first capacitor is connected to the third node, and a second electrode of the first capacitor is connected to the second electrode of the third transistor;

[0056] A first electrode of the second capacitor is connected to the control electrode of the ninth transistor, and a second electrode of the second capacitor is connected to the second electrode of the ninth transistor;

[0057] The third voltage stabilizing module includes a sixteenth transistor, wherein a first electrode of the sixteenth transistor is connected to the fourth node, a second electrode of the sixteenth transistor is connected to the first node, and a control electrode of the sixteenth transistor is connected to the first power signal terminal;

[0058] The fourth voltage stabilizing module includes an eleventh transistor, a first electrode of the eleventh transistor is connected to the third node, and a second electrode of the eleventh transistor is connected to the first node.

[0059] In some embodiments, the control subcircuit includes a third control submodule and a fifth voltage stabilization module:

[0060] The third control submodule is connected to the third node, the first node, the first power signal terminal, the second power signal terminal, the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal, and is configured to control the signal of the first node in response to the signals of the first power signal terminal, the second power signal terminal, the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal, and provide the signal of the third node to the first node;

[0061] The fifth voltage stabilizing module is connected to the third node, the second node and the first power signal terminal, and is configured to provide the voltage of the third node to the second node in response to a signal of the first power signal terminal.

[0062] In some embodiments, the third control submodule includes a first transistor, a sixth transistor, an eighth transistor, a ninth transistor, a tenth transistor, a third transistor, a seventh transistor, a twelfth transistor, and a first capacitor and a second capacitor; wherein,

[0063] The first electrode of the first transistor is connected to the first clock signal terminal, the second electrode of the first transistor is connected to the sixth node, and the control electrode of the first transistor is connected to the third node;

[0064] A first electrode of the sixth transistor is connected to the first power signal terminal, a second electrode of the sixth transistor is connected to the sixth node, and a control electrode of the sixth transistor is connected to the first clock signal terminal;

[0065] A first electrode of the eighth transistor is connected to the sixth node, a second electrode of the eighth transistor is connected to the control electrode of the ninth transistor, and the control electrode of the eighth transistor is connected to the first power signal terminal;

[0066] The first electrode of the ninth transistor is connected to the second clock signal terminal, and the second electrode of the ninth transistor is connected to the first electrode of the tenth transistor;

[0067] The second electrode of the tenth transistor is connected to the first node, and the control electrode of the tenth transistor is connected to the second clock signal terminal;

[0068] A first electrode of the third transistor is connected to the second clock signal terminal, a second electrode of the third transistor is connected to the second electrode of the seventh transistor, and a control electrode of the third transistor is connected to the third node;

[0069] The first electrode of the seventh transistor is connected to the second power signal terminal, and the control electrode of the seventh transistor is connected to the sixth node;

[0070] A first electrode of the twelfth transistor is connected to the third clock signal terminal, a second electrode of the twelfth transistor is connected to the first node, and a control electrode of the twelfth transistor is connected to the third node;

[0071] A first electrode of the first capacitor is connected to the third node, and a second electrode of the first capacitor is connected to the second electrode of the third transistor;

[0072] A first electrode of the second capacitor is connected to the control electrode of the ninth transistor, and a second electrode of the second capacitor is connected to the second electrode of the ninth transistor;

[0073] The fifth voltage stabilizing module includes an eleventh transistor, a first electrode of the eleventh transistor is connected to the third node, and a second electrode of the eleventh transistor is connected to the first node.

[0074] In some embodiments, the control subcircuit includes a fourth control submodule and a sixth voltage stabilization module:

[0075] The fourth control submodule is connected to the third node, the first node, the fifth node, the first power signal terminal, the second power signal terminal, the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal, and is configured to control the signals of the first node and the fifth node in response to the signals of the first power signal terminal, the second power signal terminal, the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal, and to provide the signal of the third node to the first node or the fifth node;

[0076] The sixth voltage stabilizing module is connected to the fifth node, the second node and the first power signal terminal, and is configured to provide the voltage of the fifth node to the second node in response to a signal of the first power signal terminal.

[0077] In some embodiments, the fourth control submodule includes a first transistor, a sixth transistor, an eighth transistor, a ninth transistor, a tenth transistor, a third transistor, a seventh transistor, an eleventh transistor, a twelfth transistor, and a first capacitor and a second capacitor; wherein,

[0078] The first electrode of the first transistor is connected to the first clock signal terminal, the second electrode of the first transistor is connected to the sixth node, and the control electrode of the first transistor is connected to the third node;

[0079] A first electrode of the sixth transistor is connected to the first power signal terminal, a second electrode of the sixth transistor is connected to the sixth node, and a control electrode of the sixth transistor is connected to the first clock signal terminal;

[0080] A first electrode of the eighth transistor is connected to the sixth node, a second electrode of the eighth transistor is connected to the control electrode of the ninth transistor, and the control electrode of the eighth transistor is connected to the first power signal terminal;

[0081] The first electrode of the ninth transistor is connected to the second clock signal terminal, and the second electrode of the ninth transistor is connected to the first electrode of the tenth transistor;

[0082] The second electrode of the tenth transistor is connected to the first node, and the control electrode of the tenth transistor is connected to the second clock signal terminal;

[0083] A first electrode of the third transistor is connected to the second clock signal terminal, a second electrode of the third transistor is connected to the second electrode of the seventh transistor, and a control electrode of the third transistor is connected to the fifth node;

[0084] The first electrode of the seventh transistor is connected to the second power signal terminal, and the control electrode of the seventh transistor is connected to the sixth node;

[0085] The first electrode of the eleventh transistor is connected to the third node, the second electrode of the eleventh transistor is connected to the fifth node, and the control electrode of the eleventh transistor is connected to the first power signal terminal;

[0086] A first electrode of the twelfth transistor is connected to the third clock signal terminal, a second electrode of the twelfth transistor is connected to the first node, and a control electrode of the twelfth transistor is connected to the fifth node;

[0087] A first electrode of the first capacitor is connected to the fifth node, and a second electrode of the first capacitor is connected to the second electrode of the third transistor;

[0088] A first electrode of the second capacitor is connected to the control electrode of the ninth transistor, and a second electrode of the second capacitor is connected to the second electrode of the ninth transistor;

[0089] The sixth voltage stabilization module includes a seventeenth transistor, a first electrode of the seventeenth transistor is connected to the fifth node, and a second electrode of the seventeenth transistor is connected to the first node.

[0090] In some embodiments, the control subcircuit includes a fifth control submodule and a seventh voltage stabilization module:

[0091] The fifth control submodule is connected to the third node, the fourth node, the second node, the first power signal terminal, the second power signal terminal, the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal, and is configured to control the signals of the fourth node and the second node in response to the signals of the first power signal terminal, the second power signal terminal, the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal, and to provide the signal of the third node to the fourth node or the second node;

[0092] The seventh voltage stabilizing module is connected to the fourth node, the first node and the first power signal terminal, and is configured to provide the voltage of the fourth node to the first node in response to a signal of the first power signal terminal.

[0093] In some embodiments, the fifth control submodule includes a first transistor, a sixth transistor, an eighth transistor, a ninth transistor, a tenth transistor, a third transistor, a seventh transistor, an eleventh transistor, a twelfth transistor, and a first capacitor and a second capacitor; wherein,

[0094] The first electrode of the first transistor is connected to the first clock signal terminal, the second electrode of the first transistor is connected to the sixth node, and the control electrode of the first transistor is connected to the third node;

[0095] A first electrode of the sixth transistor is connected to the first power signal terminal, a second electrode of the sixth transistor is connected to the sixth node, and a control electrode of the sixth transistor is connected to the first clock signal terminal;

[0096] A first electrode of the eighth transistor is connected to the sixth node, a second electrode of the eighth transistor is connected to the control electrode of the ninth transistor, and the control electrode of the eighth transistor is connected to the first power signal terminal;

[0097] The first electrode of the ninth transistor is connected to the second clock signal terminal, and the second electrode of the ninth transistor is connected to the first electrode of the tenth transistor;

[0098] The second electrode of the tenth transistor is connected to the fourth node, and the control electrode of the tenth transistor is connected to the second clock signal terminal;

[0099] A first electrode of the third transistor is connected to the second clock signal terminal, a second electrode of the third transistor is connected to the second electrode of the seventh transistor, and a control electrode of the third transistor is connected to the second node;

[0100] The first electrode of the seventh transistor is connected to the second power signal terminal, and the control electrode of the seventh transistor is connected to the sixth node;

[0101] The first electrode of the eleventh transistor is connected to the third node, the second electrode of the eleventh transistor is connected to the second node, and the control electrode of the eleventh transistor is connected to the first power signal terminal;

[0102] A first electrode of the twelfth transistor is connected to the third clock signal terminal, a second electrode of the twelfth transistor is connected to the fourth node, and a control electrode of the twelfth transistor is connected to the second node;

[0103] A first electrode of the first capacitor is connected to the second node, and a second electrode of the first capacitor is connected to the second electrode of the third transistor;

[0104] A first electrode of the second capacitor is connected to the control electrode of the ninth transistor, and a second electrode of the second capacitor is connected to the second electrode of the ninth transistor;

[0105] The seventh voltage stabilization module includes a sixteenth transistor, a first electrode of the sixteenth transistor is connected to the fourth node, a second electrode of the sixteenth transistor is connected to the first node, and a control electrode of the sixteenth transistor is connected to the first power signal terminal.

[0106] The present application also discloses a display panel, which includes:

[0107] A base substrate, comprising a display area and a non-display area;

[0108] The display area includes:

[0109] multiple sub-pixels;

[0110] a plurality of scan lines, wherein a row of the sub-pixels in the plurality of sub-pixels is correspondingly coupled to at least one of the scan lines;

[0111] The non-display area includes:

[0112] The gate drive circuit includes several shift register units as described above, wherein the drive output end of each shift register unit is correspondingly connected to at least one of the multiple scan lines; in two adjacent shift register units, the input signal end of the next shift register unit is coupled to the cascade output end of the previous shift register unit.

[0113] In some embodiments, the display panel further includes a plurality of control signal lines coupled to the gate driving circuit; an extension direction of the plurality of control signal lines is the same as an arrangement direction of the plurality of shift register units.

[0114] In some embodiments, the orthographic projections of the plurality of control signal lines on the base substrate are located between the orthographic projection of the gate driving circuit on the base substrate and the display area.

[0115] In some embodiments, the multiple control signal lines include a first control sub-signal line and a second control sub-signal line; the first control sub-signal line is coupled to the control signal end of the odd-numbered shift register unit, and the second control sub-signal line is coupled to the control signal end of the even-numbered shift register unit.

[0116] In some embodiments, the display panel further comprises a plurality of auxiliary control signal lines, and an insulating layer is provided between the plurality of auxiliary control signal lines and the plurality of control signal lines;

[0117] The plurality of auxiliary control signal lines correspond one-to-one to the plurality of control signal lines, and the corresponding auxiliary control signal lines and control signal lines are coupled to each other through vias penetrating the insulating layer.

[0118] In some embodiments, the display panel further includes a plurality of clock signal lines, and an extension direction of the plurality of clock signal lines is the same as an arrangement direction of the plurality of shift register units.

[0119] In some embodiments, the orthographic projection of the gate driving circuit on the substrate is located between the orthographic projections of the plurality of clock signal lines on the substrate and the orthographic projections of the plurality of control signal lines on the substrate.

[0120] In some embodiments, the display panel includes a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line; wherein,

[0121] The first clock signal terminals of the odd-numbered shift register units and the second clock signal terminals of the even-numbered shift register units are coupled to the first clock signal line;

[0122] The second clock signal terminals of the odd-numbered shift register units and the first clock signal terminals of the even-numbered shift register units are coupled to the second clock signal line;

[0123] The third clock signal terminal of the odd-numbered shift register unit is coupled to the fourth clock signal line;

[0124] The third clock signal terminal of the even-numbered shift register unit is coupled to the third clock signal line.

[0125] In some embodiments, when the first output sub-circuit includes a fourth capacitor, an orthographic projection of the fourth capacitor C4 on the substrate is located on a side of the shift register unit currently located by the fourth capacitor that is close to the next stage shift register unit.

[0126] In some embodiments, the fourth capacitor C4 is less than 120 farads.

[0127] In some embodiments, when the first output sub-circuit includes a fourth transistor and the second output sub-circuit includes a fourteenth transistor, the orthographic projection of the fourteenth transistor on the substrate is located between the orthographic projection of the fourth transistor on the substrate and the display area; when the first output sub-circuit includes a fifth transistor and the second output sub-circuit includes a fifteenth transistor, the orthographic projection of the fifteenth transistor on the substrate is located between the orthographic projection of the fifth transistor on the substrate and the display area.

[0128] In some embodiments, a channel width of the fourteenth transistor is greater than a channel width of the fourth transistor.

[0129] In some embodiments, a channel width of the fourteenth transistor is not less than 100 micrometers.

[0130] In some embodiments, a channel width of the fourth transistor is no greater than 60 micrometers.

[0131] In some embodiments, a channel width of the fifteenth transistor is greater than a channel width of the fifth transistor.

[0132] In some embodiments, a channel width of the fifteenth transistor is not less than 100 microns.

[0133] In some embodiments, a channel width of the fifth transistor is no greater than 60 micrometers.

[0134] The present application also discloses a display device, comprising:

[0135] The display panel as described above;

[0136] a drive control circuit coupled to the display panel and configured to input a first signal to the control signal terminals of the plurality of shift register units when determining to adopt a full-screen refresh mode, so as to cause the plurality of shift register units to sequentially output gate scan signals and drive the scan lines row by row;

[0137] When the partial refresh mode is determined to be adopted, a second signal is input to the control signal terminals of the plurality of shift register units, so that some of the plurality of shift register units sequentially output gate scan signals and the remaining shift register units output invalid scan signals.

[0138] The present application also discloses a driving method for driving the display panel as described above, which comprises:

[0139] When it is determined to adopt the full-area refresh mode, outputting a first signal to the control signal terminals of the plurality of shift register units, so that the plurality of shift register units sequentially output gate scan signals and drive the scan lines row by row;

[0140] When it is determined to adopt the partition refresh mode, a second signal is output to the control signal end of the multiple shift register units, so that some of the multiple shift register units output gate scan signals in sequence, and the remaining shift register units output invalid scan signals to drive some of the scan lines.

[0141] In some embodiments, the first signal is a clock signal.

[0142] In some embodiments, the second signal includes a fixed signal portion having a clock signal and a fixed signal portion having a second level, the fixed signal portion having the clock signal is input into some of the shift register units, and the fixed signal portion having the second level is input into the remaining shift register units.

[0143] Compared to related art, the second output subcircuit of the present invention is connected to a control signal terminal and a drive output terminal. Under the control of the first node, the control signal terminal is connected to the drive output terminal, and the control signal terminal is connected to one of the multiple control signal lines. The drive output terminal can output a gate scan signal for controlling a partition refresh.

[0144] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0145] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the specification and, together with the description, serve to explain the principles of the specification.

[0146] FIG1 is a schematic structural diagram of a shift register unit provided in an embodiment of the present application;

[0147] FIG2 is a circuit diagram of a shift register unit provided in an embodiment of the present application;

[0148] FIG3 is a schematic diagram of some structures of a display panel provided in an embodiment of the present application;

[0149] FIG4 is a schematic diagram of some structures of a display device provided in an embodiment of the present application;

[0150] FIG5 is a flow chart of a driving method provided in an embodiment of the present application;

[0151] FIG6 is a signal timing diagram provided in an embodiment of the present application;

[0152] FIG7 is another signal timing diagram provided in an embodiment of the present application;

[0153] FIG8 is a schematic diagram of a partial layout structure of a shift register unit provided in an embodiment of the present application;

[0154] FIG9 is a partial enlarged schematic diagram of the shift register unit shown in FIG8 ;

[0155] FIG10 is another partially enlarged schematic diagram of the shift register unit shown in FIG8 ;

[0156] 11 to 16 are schematic structural diagrams of each level of the partial layout of the shift register unit in FIG9 ;

[0157] FIG17 is a circuit diagram of another shift register unit provided in an embodiment of the present application;

[0158] FIG18 is a circuit diagram of another shift register unit provided in an embodiment of the present application;

[0159] FIG19 is a circuit diagram of another shift register unit provided in an embodiment of the present application;

[0160] FIG20 is a circuit diagram of another shift register unit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0161] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with this specification. Rather, they are merely examples of apparatus and methods consistent with certain aspects of this specification, as detailed in the appended claims.

[0162] The terminology used in this application is for the purpose of describing specific embodiments only and is not intended to limit the present disclosure. Unless otherwise defined, technical or scientific terms used in this specification should have the same ordinary meaning as those understood by persons of ordinary skill in the art to which this application belongs. The terms "first," "second," and similar terms used in this specification and claims do not denote any order, quantity, or importance, but are simply used to distinguish one component from another. Similarly, terms such as "a" or "an" do not denote a limitation of quantity, but rather indicate the presence of one. "Multiple" or "several" refer to two or more. Unless otherwise indicated, terms such as "front," "rear," "lower," and / or "upper" are used for convenience only and are not intended to limit the scope of the present disclosure to a specific location or spatial orientation. Terms such as "include" or "comprising" mean that the elements or items preceding the term "include" or "comprising" include the elements or items listed after the term and their equivalents, and do not exclude other elements or items. Terms such as "connected" or "connected" are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect.

[0163] The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. As used in this specification and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0164] The transistors used in this disclosure may be triodes, thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two electrodes of the transistor other than the control electrode, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode. The energy storage unit used in this disclosure may be a capacitor.

[0165] In actual operation, when the transistor is a triode, the control electrode may be a base, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base, the first electrode may be an emitter, and the second electrode may be a collector.

[0166] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode can be a gate, the first electrode can be a drain, and the second electrode can be a source; or, the control electrode can be a gate, the first electrode can be a source, and the second electrode can be a drain.

[0167] For example, to reduce the manufacturing process, all transistors can be P-type transistors; alternatively, all transistors can be N-type transistors, which is not limited here. Furthermore, N-type transistors are turned on by a high-level signal and turned off by a low-level signal; P-type transistors are turned off by a high-level signal and turned on by a low-level signal. In this application, all transistors are P-type transistors as an example for description.

[0168] An embodiment of the present application provides a shift register unit, as shown in FIG. 1 and FIG. 2 , including an input sub-circuit 10 , a control sub-circuit 20 , a first output sub-circuit 30 , and a second output sub-circuit 40 .

[0169] The input sub-circuit 10 is connected to the third node N3, the input signal terminal IN, the first clock signal terminal CKA and the third clock signal terminal CKD, and is configured to provide the signal of the input signal terminal IN to the third node N3 in response to the signals of the first clock signal terminal CKA and the third clock signal terminal CKD.

[0170] The control subcircuit 20 is connected to the third node N3, the first node N1, the second node N2, the first power signal terminal VGA, the second power signal terminal VGB, the first clock signal terminal CKA, the second clock signal terminal CKB and the third clock signal terminal CKD, and is configured to control the signals of the first node N1 and the second node N2 in response to the signals of the first power signal terminal VGA, the second power signal terminal VGB, the first clock signal terminal CKA, the second clock signal terminal CKB and the third clock signal terminal CKD, and to provide the signal of the third node N3 to the first node N1 or the second node N2.

[0171] The first output sub-circuit 30 is connected to the first node N1, the second node N2, the third clock signal terminal CKD, the first power signal terminal VGA and the cascade output terminal OT, and is configured to respond to the signals of the first node N1 and the second node N2 to enable the cascade output terminal OT to output a cascade signal.

[0172] The second output sub-circuit 40 is connected to the first node N1, the second node N2, the control signal terminal VFE, the first power signal terminal VGA and the driving output terminal OUT, and is configured to respond to the signals of the first node N1 and the second node N2 to enable the driving output terminal OUT to output a gate scanning signal.

[0173] The shift register unit provided in the embodiments of the present application controls the gate scanning signal driving the output terminal OUT by controlling the signal at the control signal terminal VFE. When the shift register unit is applied to a display panel, the signal at the control signal terminal VFE can be controlled to scan any area of ​​the display panel, thereby achieving flexible adjustment of the refresh rate of different areas, saving power and reducing losses.

[0174] As shown in FIG. 1 and FIG. 2 , in some embodiments of the present application, the input sub-circuit 10 includes a thirteenth transistor T13 and a second transistor T2 .

[0175] A first electrode of the thirteenth transistor T13 is connected to the input signal terminal IN, a second electrode of the thirteenth transistor T13 is connected to the first electrode of the second transistor T2, and a control electrode of the thirteenth transistor T13 is connected to the third clock signal terminal CKD.

[0176] A second electrode of the second transistor T2 is connected to the third node N3 , and a control electrode of the second transistor T2 is connected to the first clock signal terminal CKA.

[0177] In some embodiments, the control subcircuit 20 includes a first control submodule 211 , a first voltage stabilizing module 221 , and a second voltage stabilizing module 222 , to stabilize the voltages of the first node N1 and the second node N2 , respectively.

[0178] The first control submodule 211 is connected to the third node N3, the fourth node N4, the fifth node N5, the first power signal terminal VGA, the second power signal terminal VGB, the first clock signal terminal CKA, the second clock signal terminal CKB and the third clock signal terminal CKD, and is configured to control the signals of the fourth node N4 and the fifth node N5 in response to the signals of the first power signal terminal VGA, the second power signal terminal VGB, the first clock signal terminal CKA, the second clock signal terminal CKB and the third clock signal terminal CKD, and to provide the signal of the third node N3 to the fourth node N4 or the fifth node N5.

[0179] The first voltage stabilizing module 221 is connected to the fourth node N4 , the first node N1 and the first power signal terminal VGA, and is configured to provide the voltage of the fourth node N4 to the first node N1 in response to a signal from the first power signal terminal VGA.

[0180] The second voltage stabilization module 222 is connected to the fifth node N5, the second node N2 and the first power signal terminal VGA, and is configured to provide the voltage of the fifth node N5 to the second node N2 in response to the signal of the first power signal terminal VGA.

[0181] Specifically, referring to FIG. 2 , in some embodiments, the first control submodule 211 includes a first transistor T1, a sixth transistor T6, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a third transistor T3, a seventh transistor T7, an eleventh transistor T11, a twelfth transistor T12, and a first capacitor C1 and a second capacitor C2; wherein,

[0182] A first electrode of the first transistor T1 is connected to the first clock signal terminal CKA, a second electrode of the first transistor T1 is connected to the sixth node N6, and a control electrode of the first transistor T1 is connected to the third node N3;

[0183] A first electrode of the sixth transistor T6 is connected to the first power signal terminal VGA, a second electrode of the sixth transistor T6 is connected to the sixth node N6, and a control electrode of the sixth transistor T6 is connected to the first clock signal terminal CKA;

[0184] A first electrode of the eighth transistor T8 is connected to the sixth node N6, a second electrode of the eighth transistor T8 is connected to the control electrode of the ninth transistor T9, and the control electrode of the eighth transistor T8 is connected to the first power signal terminal VGA;

[0185] A first electrode of the ninth transistor T9 is connected to the second clock signal terminal CKB, and a second electrode of the ninth transistor T9 is connected to a first electrode of the tenth transistor T10;

[0186] A second electrode of the tenth transistor T10 is connected to the fourth node N4, and a control electrode of the tenth transistor T10 is connected to the second clock signal terminal CKB;

[0187] A first electrode of the third transistor T3 is connected to the second clock signal terminal CKB, a second electrode of the third transistor T3 is connected to the second electrode of the seventh transistor T7, and a control electrode of the third transistor T3 is connected to the fifth node N5;

[0188] A first electrode of the seventh transistor T7 is connected to the second power signal terminal VGB, and a control electrode of the seventh transistor T7 is connected to the sixth node N6;

[0189] a first electrode of the eleventh transistor T11 connected to the third node N3, a second electrode of the eleventh transistor T11 connected to the fifth node N5, and a control electrode of the eleventh transistor T11 connected to the first power signal terminal CKA;

[0190] A first electrode of the twelfth transistor T12 is connected to the third clock signal terminal CKD, a second electrode of the twelfth transistor T12 is connected to the fourth node N4, and a control electrode of the twelfth transistor T12 is connected to the fifth node N5;

[0191] A first electrode of the first capacitor C1 is connected to the fifth node N5, and a second electrode of the first capacitor C1 is connected to the second electrode of the third transistor T3;

[0192] A first electrode of the second capacitor C2 is connected to the control electrode of the ninth transistor T9, and a second electrode of the second capacitor C2 is connected to the second electrode of the ninth transistor T9;

[0193] The first voltage stabilizing module 221 includes a sixteenth transistor T16, a first electrode of the sixteenth transistor T16 is connected to the fourth node N4, a second electrode of the sixteenth transistor T16 is connected to the first node N1, and a control electrode of the sixteenth transistor T16 is connected to the first power signal terminal VGA; the setting of the sixteenth transistor T16 can prevent current backflow and improve the stability of the circuit.

[0194] The second voltage stabilizing module 222 includes a seventeenth transistor T17, a first electrode of the seventeenth transistor T17 being connected to the fifth node N5, and a second electrode of the seventeenth transistor T17 being connected to the first node N1. The seventeenth transistor T17 can prevent current backflow and improve circuit stability.

[0195] It is understandable that the first voltage stabilizing module and the second voltage stabilizing module can also be configured as other voltage stabilizing circuit structures. The first capacitor C1 and the second capacitor C2 can be selected to have a capacity of 20 farad to 30 farad (i.e., 20f to 30f). For example, the first capacitor C1 is a 30f capacitor and the second capacitor C2 is a 20f capacitor.

[0196] 2 , in some embodiments, the first output sub-circuit 30 includes a fourth transistor T4 and a fifth transistor T5 .

[0197] A first electrode of the fourth transistor T4 is connected to the third clock signal terminal CKD, a second electrode of the fourth transistor T4 is connected to the cascade output terminal OT, and a control electrode of the fourth transistor T4 is connected to the first node N1;

[0198] A first electrode of the fifth transistor T5 is connected to the first power signal terminal VGA, a second electrode of the fifth transistor T5 is connected to the cascade output terminal OT, and a control electrode of the fifth transistor T5 is connected to the second node N2.

[0199] In some embodiments, the first output sub-circuit 30 further includes a third capacitor C3, a first end of the third capacitor C3 being connected to the first electrode of the fourth transistor T4, and a second end of the third capacitor C3 being connected to the control electrode of the fourth transistor T4. Optionally, the third capacitor is a 50f capacitor.

[0200] Considering that there is no load on the signal line of the first output sub-circuit 30, which may easily lead to instability of the cascade signal, a capacitor with a large capacitance is coupled to the cascade output terminal OT.

[0201] For example, as shown in FIG2 , in some embodiments, the first output sub-circuit 30 further includes a fourth capacitor C4 , a first end of the fourth capacitor C4 is connected to the cascade output terminal OT, and a second end of the fourth capacitor C4 is connected to the first power signal terminal VGA.

[0202] In some embodiments, the fourth capacitor C4 is less than 120 farads (i.e., 120f). It can be set to a relatively large capacitor less than 120 farads. Alternatively, the fourth capacitor C4 is a capacitor of 100f. This fourth capacitor C4 can make the cascade signal output by the first output sub-circuit 30 more stable.

[0203] It should be noted that, in some other embodiments, the first output sub-circuit 30 may not include the third capacitor and the fourth capacitor, or may include only one of the third capacitor and the fourth capacitor.

[0204] In some embodiments, the second output sub-circuit 40 includes:

[0205] The first output module 41, connected to the control signal terminal VFE, the first node N1 and the driving output terminal OUT, is configured to transmit the signal of the control signal terminal VFE to the driving output terminal OUT under the control of the first node N1;

[0206] The second output module 42 is connected to the first power signal terminal VGA, the second node N2 and the driving output terminal OUT, and is configured to transmit the signal of the first power signal terminal VGA to the driving output terminal OUT under the control of the second node N2.

[0207] In some embodiments, the first output module 41 includes a fourteenth transistor T14, a first electrode of the fourteenth transistor T14 is connected to the control signal terminal VFE, a second electrode of the fourteenth transistor T14 is connected to the driving output terminal OUT, and a control electrode of the fourteenth transistor T14 is connected to the second node N2.

[0208] In some embodiments, the second output module 42 includes a fifteenth transistor T15, a first electrode of the fifteenth transistor T15 is connected to the first power signal terminal VGA, a second electrode of the fifteenth transistor T15 is connected to the driving output terminal OUT, and a control electrode of the fifteenth transistor T15 is connected to the second node N2.

[0209] 1 and 17 , in another embodiment of the present application, the control sub-circuit 20 includes a second control sub-module 212 , a third voltage stabilizing module 223 , and a fourth voltage stabilizing module 224 .

[0210] The second control submodule 212 is connected to the third node N3, the fourth node N4, the first node N1, the first power signal terminal VGA, the second power signal terminal VGB, the first clock signal terminal CKA, the second clock signal terminal CKB, and the third clock signal terminal CKD, and is configured to control the signal of the fourth node N4 in response to the signals of the first power signal terminal VGA, the second power signal terminal VGB, the first clock signal terminal CKA, the second clock signal terminal CKB, and the third clock signal terminal CKD, and provide the signal of the third node N3 to the fourth node N4;

[0211] The third voltage stabilizing module 223 is connected to the fourth node N4, the first node N1 and the first power signal terminal VGA, and is configured to provide the voltage of the fourth node N4 to the first node N1 in response to the signal of the first power signal terminal VGA;

[0212] The fourth voltage stabilization module 224 is connected to the third node N3, the second node N2, and the first power signal terminal VGA, and is configured to provide the voltage of the third node N3 to the second node N2 in response to the signal of the first power signal terminal VGA.

[0213] 17 , the second control submodule 212 includes a first transistor T1, a sixth transistor T6, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a third transistor T3, a seventh transistor T7, a twelfth transistor T12, and a first capacitor C1 and a second capacitor C2; wherein,

[0214] A first electrode of the first transistor T1 is connected to the first clock signal terminal CKA, a second electrode of the first transistor T1 is connected to the sixth node N6, and a control electrode of the first transistor T1 is connected to the third node N3;

[0215] A first electrode of the sixth transistor T6 is connected to the first power signal terminal VGA, a second electrode of the sixth transistor T6 is connected to the sixth node N6, and a control electrode of the sixth transistor T6 is connected to the first clock signal terminal CKA;

[0216] A first electrode of the eighth transistor T8 is connected to the sixth node N6, a second electrode of the eighth transistor T8 is connected to the control electrode of the ninth transistor T9, and the control electrode of the eighth transistor T8 is connected to the first power signal terminal VGA;

[0217] A first electrode of the ninth transistor T9 is connected to the second clock signal terminal CKB, and a second electrode of the ninth transistor T9 is connected to a first electrode of the tenth transistor T10;

[0218] A second electrode of the tenth transistor T10 is connected to the fourth node N4, and a control electrode of the tenth transistor T10 is connected to the second clock signal terminal CKB;

[0219] A first electrode of the third transistor T3 is connected to the second clock signal terminal CKB, a second electrode of the third transistor T3 is connected to the second electrode of the seventh transistor T7, and a control electrode of the third transistor T3 is connected to the third node N3;

[0220] A first electrode of the seventh transistor T7 is connected to the second power signal terminal VGB, and a control electrode of the seventh transistor T7 is connected to the sixth node N6;

[0221] A first electrode of the twelfth transistor T12 is connected to the third clock signal terminal CKD, a second electrode of the twelfth transistor T12 is connected to the fourth node N4, and a control electrode of the twelfth transistor T12 is connected to the third node N3;

[0222] A first electrode of the first capacitor C1 is connected to the third node N3, and a second electrode of the first capacitor C1 is connected to the second electrode of the third transistor T3;

[0223] A first electrode of the second capacitor C2 is connected to the control electrode of the ninth transistor T9, and a second electrode of the second capacitor C2 is connected to the second electrode of the ninth transistor T9;

[0224] The third voltage stabilizing module 223 includes a sixteenth transistor T16, a first electrode of the sixteenth transistor T16 is connected to the fourth node N4, a second electrode of the sixteenth transistor T16 is connected to the first node N1, and a control electrode of the sixteenth transistor T16 is connected to the first power signal terminal VGA;

[0225] The fourth voltage stabilizing module 224 includes an eleventh transistor T11 . A first electrode of the eleventh transistor T11 is connected to the third node N3 , and a second electrode of the eleventh transistor T11 is connected to the first node N1 .

[0226] It should be noted that, compared to the embodiment shown in FIG2 , the embodiment shown in FIG17 directly shifts T11 rightward to form a fourth voltage stabilizing module for stabilizing the voltage of the second node N2 . For the same or similar aspects, please refer to the description of the embodiment shown in FIG2 .

[0227] 1 and 18 , in another embodiment of the present application, the control subcircuit 20 includes a third control submodule 213 and a fifth voltage stabilizing module 225 :

[0228] The third control submodule 213 is connected to the third node N3, the first node N1, the first power signal terminal VGA, the second power signal terminal VGB, the first clock signal terminal CKA, the second clock signal terminal CKB, and the third clock signal terminal CKD, and is configured to control the signal of the first node N1 in response to the signals of the first power signal terminal VGA, the second power signal terminal VGB, the first clock signal terminal CKA, the second clock signal terminal CKB, and the third clock signal terminal CKD, and provide the signal of the third node N3 to the first node N1;

[0229] The fifth voltage stabilizing module 225 is connected to the third node N3, the second node N2 and the first power signal terminal VGA, and is configured to provide the voltage of the third node N3 to the second node N2 in response to the signal of the first power signal terminal VGA.

[0230] 18 , the third control submodule 213 includes a first transistor T1, a sixth transistor T6, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a third transistor T3, a seventh transistor T7, a twelfth transistor T12, and a first capacitor C1 and a second capacitor C2; wherein,

[0231] A first electrode of the first transistor T1 is connected to the first clock signal terminal CKA, a second electrode of the first transistor T1 is connected to the sixth node N6, and a control electrode of the first transistor T1 is connected to the third node N3;

[0232] A first electrode of the sixth transistor T6 is connected to the first power signal terminal VGA, a second electrode of the sixth transistor T6 is connected to the sixth node N6, and a control electrode of the sixth transistor T6 is connected to the first clock signal terminal CKA;

[0233] A first electrode of the eighth transistor T8 is connected to the sixth node N6, a second electrode of the eighth transistor T8 is connected to the control electrode of the ninth transistor T9, and the control electrode of the eighth transistor T8 is connected to the first power signal terminal VGA;

[0234] A first electrode of the ninth transistor T9 is connected to the second clock signal terminal CKB, and a second electrode of the ninth transistor T9 is connected to a first electrode of the tenth transistor T10;

[0235] The second electrode of the tenth transistor T10 is connected to the first node N1, and the control electrode of the tenth transistor T10 is connected to the second clock signal terminal CKB;

[0236] A first electrode of the third transistor T3 is connected to the second clock signal terminal CKB, a second electrode of the third transistor T3 is connected to the second electrode of the seventh transistor T7, and a control electrode of the third transistor T3 is connected to the third node N3;

[0237] A first electrode of the seventh transistor T7 is connected to the second power signal terminal VGB, and a control electrode of the seventh transistor T7 is connected to the sixth node N6;

[0238] A first electrode of the twelfth transistor T12 is connected to the third clock signal terminal CKD, a second electrode of the twelfth transistor T12 is connected to the first node N1, and a control electrode of the twelfth transistor T12 is connected to the third node N3;

[0239] A first electrode of the first capacitor C1 is connected to the third node N3, and a second electrode of the first capacitor C1 is connected to the second electrode of the third transistor T3;

[0240] A first electrode of the second capacitor C2 is connected to the control electrode of the ninth transistor T9, and a second electrode of the second capacitor C2 is connected to the second electrode of the ninth transistor T9;

[0241] The fifth voltage stabilizing module 225 includes an eleventh transistor T11 , a first electrode of the eleventh transistor T11 is connected to the third node N3 , and a second electrode of the eleventh transistor T11 is connected to the first node N1 .

[0242] It should be noted that, compared to the embodiment shown in FIG2 , in the embodiment shown in FIG18 , T11 is directly shifted right to form a fifth voltage stabilizing module for stabilizing the voltage of the second node N2 , and no voltage stabilizing module is provided before the first node N1 . For similarities or similarities, please refer to the description of the embodiment shown in FIG2 .

[0243] 1 and 19 , in another embodiment of the present application, the control sub-circuit 20 includes a fourth control sub-module 214 and a sixth voltage stabilization module 226 :

[0244] The fourth control submodule 214 is connected to the third node N3, the first node N1, the fifth node N5, the first power signal terminal VGA, the second power signal terminal VGB, the first clock signal terminal CKA, the second clock signal terminal CKB, and the third clock signal terminal CKD, and is configured to control the signals of the first node N1 and the fifth node N5 in response to the signals of the first power signal terminal VGA, the second power signal terminal VGB, the first clock signal terminal CKA, the second clock signal terminal CKB, and the third clock signal terminal CKD, and provide the signal of the third node N3 to the first node N1 or the fifth node N5;

[0245] The sixth voltage stabilization module 226 is connected to the fifth node N5, the second node N2, and the first power signal terminal VGA, and is configured to provide the voltage of the fifth node N5 to the second node N2 in response to the signal of the first power signal terminal VGA.

[0246] Continuing with FIG19 , the fourth control submodule 214 includes a first transistor T1, a sixth transistor T6, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a third transistor T3, a seventh transistor T7, an eleventh transistor T11, a twelfth transistor T12, and a first capacitor C1 and a second capacitor C2; wherein,

[0247] A first electrode of the first transistor T1 is connected to the first clock signal terminal CKA, a second electrode of the first transistor T1 is connected to the sixth node N6, and a control electrode of the first transistor T1 is connected to the third node N3;

[0248] A first electrode of the sixth transistor T6 is connected to the first power signal terminal VGA, a second electrode of the sixth transistor T6 is connected to the sixth node N6, and a control electrode of the sixth transistor T6 is connected to the first clock signal terminal CKA;

[0249] A first electrode of the eighth transistor T8 is connected to the sixth node N6, a second electrode of the eighth transistor T8 is connected to the control electrode of the ninth transistor T9, and the control electrode of the eighth transistor T8 is connected to the first power signal terminal VGA;

[0250] A first electrode of the ninth transistor T9 is connected to the second clock signal terminal CKB, and a second electrode of the ninth transistor T9 is connected to a first electrode of the tenth transistor T10;

[0251] The second electrode of the tenth transistor T10 is connected to the first node N1, and the control electrode of the tenth transistor T10 is connected to the second clock signal terminal CKB;

[0252] A first electrode of the third transistor T3 is connected to the second clock signal terminal CKB, a second electrode of the third transistor T3 is connected to the second electrode of the seventh transistor T7, and a control electrode of the third transistor T3 is connected to the fifth node N5;

[0253] A first electrode of the seventh transistor T7 is connected to the second power signal terminal VGB, and a control electrode of the seventh transistor T7 is connected to the sixth node N6;

[0254] a first electrode of the eleventh transistor T11 connected to the third node N3, a second electrode of the eleventh transistor T11 connected to the fifth node N5, and a control electrode of the eleventh transistor T11 connected to the first power signal terminal CKA;

[0255] A first electrode of the twelfth transistor T12 is connected to the third clock signal terminal CKD, a second electrode of the twelfth transistor T12 is connected to the first node N1, and a control electrode of the twelfth transistor T12 is connected to the fifth node N5;

[0256] A first electrode of the first capacitor C1 is connected to the fifth node N5, and a second electrode of the first capacitor C1 is connected to the second electrode of the third transistor T3;

[0257] A first electrode of the second capacitor C2 is connected to the control electrode of the ninth transistor T9, and a second electrode of the second capacitor C2 is connected to the second electrode of the ninth transistor T9;

[0258] The sixth voltage stabilization module 226 includes a seventeenth transistor T17 , a first electrode of the seventeenth transistor T17 is connected to the fifth node N5 , and a second electrode of the seventeenth transistor T17 is connected to the first node N1 .

[0259] It should be noted that, compared to the embodiment shown in Figure 2 , in the embodiment shown in Figure 19 , no voltage stabilizing module is provided before the first node N1 . For the same or similar aspects, reference may be made to the description of the embodiment shown in Figure 2 above.

[0260] 1 and 20 , in another embodiment of the present application, the control sub-circuit 20 includes a fifth control sub-module 215 and a seventh voltage stabilization module 227 .

[0261] The fifth control submodule 215 is connected to the third node N3, the fourth node N4, the second node N2, the first power signal terminal VGA, the second power signal terminal VGB, the first clock signal terminal CKA, the second clock signal terminal CKB, and the third clock signal terminal CKD, and is configured to control the signals of the fourth node N4 and the second node N2 in response to the signals of the first power signal terminal VGA, the second power signal terminal VGB, the first clock signal terminal CKA, the second clock signal terminal CKB, and the third clock signal terminal CKD, and provide the signal of the third node N3 to the fourth node N4 or the second node N2;

[0262] The seventh voltage stabilization module 227 is connected to the fourth node N4 , the first node N1 and the first power signal terminal VGA, and is configured to provide the voltage of the fourth node N4 to the first node N1 in response to the signal of the first power signal terminal VGA.

[0263] 20 , the fifth control submodule 215 includes a first transistor T1, a sixth transistor T6, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a third transistor T3, a seventh transistor T7, an eleventh transistor T11, a twelfth transistor T12, and a first capacitor C1 and a second capacitor C2; wherein,

[0264] A first electrode of the first transistor T1 is connected to the first clock signal terminal CKA, a second electrode of the first transistor T1 is connected to the sixth node N6, and a control electrode of the first transistor T1 is connected to the third node N3;

[0265] A first electrode of the sixth transistor T6 is connected to the first power signal terminal VGA, a second electrode of the sixth transistor T6 is connected to the sixth node N6, and a control electrode of the sixth transistor T6 is connected to the first clock signal terminal CKA;

[0266] A first electrode of the eighth transistor T8 is connected to the sixth node N6, a second electrode of the eighth transistor T8 is connected to the control electrode of the ninth transistor T9, and the control electrode of the eighth transistor T8 is connected to the first power signal terminal VGA;

[0267] A first electrode of the ninth transistor T9 is connected to the second clock signal terminal CKB, and a second electrode of the ninth transistor T9 is connected to a first electrode of the tenth transistor T10;

[0268] A second electrode of the tenth transistor T10 is connected to the fourth node N4, and a control electrode of the tenth transistor T10 is connected to the second clock signal terminal CKB;

[0269] A first electrode of the third transistor T3 is connected to the second clock signal terminal CKB, a second electrode of the third transistor T3 is connected to the second electrode of the seventh transistor T7, and a control electrode of the third transistor T3 is connected to the second node N2;

[0270] A first electrode of the seventh transistor T7 is connected to the second power signal terminal VGB, and a control electrode of the seventh transistor T7 is connected to the sixth node N6;

[0271] a first electrode of the eleventh transistor T11 connected to the third node N3, a second electrode of the eleventh transistor T11 connected to the second node N2, and a control electrode of the eleventh transistor T11 connected to the first power signal terminal CKA;

[0272] A first electrode of the twelfth transistor T12 is connected to the third clock signal terminal CKD, a second electrode of the twelfth transistor T12 is connected to the fourth node N4, and a control electrode of the twelfth transistor T12 is connected to the second node N2;

[0273] A first electrode of the first capacitor C1 is connected to the second node N2, and a second electrode of the first capacitor C1 is connected to the second electrode of the third transistor T3;

[0274] A first electrode of the second capacitor C2 is connected to the control electrode of the ninth transistor T9, and a second electrode of the second capacitor C2 is connected to the second electrode of the ninth transistor T9;

[0275] The seventh voltage stabilization module 227 includes a sixteenth transistor T16, a first electrode of the sixteenth transistor T16 is connected to the fourth node N4, a second electrode of the sixteenth transistor T16 is connected to the first node N1, and a control electrode of the sixteenth transistor T16 is connected to the first power signal terminal VGA.

[0276] It should be noted that, compared to the embodiment shown in FIG2 , the voltage stabilizing module including the seventeenth transistor T17 is not provided before the second node N2 in the embodiment shown in FIG20 . For the same or similar points, please refer to the relevant description of the embodiment shown in FIG2 .

[0277] As shown in FIG3 , the present application further provides a display panel comprising a display area AA and a non-display area BB. The display area AA comprises a plurality of sub-pixels and a plurality of scan lines GA connected to the plurality of sub-pixels. A row of sub-pixels (the row direction is the F1 direction in FIG3 ) among the plurality of sub-pixels is connected to a scan line GA among the plurality of scan lines. The scan line GA transmits a gate scan signal to a row of sub-pixels coupled thereto to drive the row of sub-pixels. The non-display area BB comprises a gate drive circuit 100, which comprises a plurality of the above-mentioned shift register units (e.g., G1, G2, G3, G4, G5, G6, G7, G8 in FIG3 ) arranged along a column direction (the F2 direction in FIG3 ), wherein the drive output terminal OUT of each of the plurality of the above-mentioned shift register units is coupled to at least one row of scan lines GA. In two adjacent shift register units, the input signal terminal IN of the next shift register unit is coupled to the cascade output terminal OT of the previous shift register unit. In an optional embodiment, the driving output terminal OUT of each of the plurality of shift register units is correspondingly coupled to two rows of scan lines GA. The input signal terminal IN of one of the plurality of shift register units is correspondingly coupled to the cascade output terminal OT of the previous shift register unit. The input signal terminal IN of the first shift register unit is coupled to the reset signal line STV.

[0278] As shown in FIG3 , in some embodiments, the display panel further includes a plurality of control signal lines (VFE1, VFE2) coupled to the gate drive circuit 100. The plurality of control signal lines extend in the same direction as the arrangement direction of the plurality of shift register units. The plurality of control signal lines extend in the same direction as the arrangement direction of the plurality of shift register units. The plurality of control signal lines include a first control sub-signal line VFE1 and a second control sub-signal line VFE2.

[0279] The first control sub-signal line VFE1 is coupled to the control signal terminals VFE of the odd-numbered shift register units, and the second control sub-signal line is coupled to the control signal terminals VFE of the even-numbered shift register units.

[0280] As shown in FIG3 , in some embodiments, the display panel further includes a plurality of clock signal lines (CK1, CK2, CK3, and CK4) coupled to the gate driver circuit 100. The plurality of clock signal lines extend in the same direction as the arrangement direction of the plurality of shift register units. The plurality of clock signal lines include a first clock signal line CK1, a second clock signal line CK2, a third clock signal line CK3, and a fourth clock signal line CK4.

[0281] The first clock signal terminal CKA of the odd-numbered shift register unit and the second clock signal terminal CKB of the even-numbered shift register unit are coupled to the first clock signal line CK1. The second clock signal terminal CKB of the odd-numbered shift register unit and the first clock signal terminal CKA of the even-numbered shift register unit are coupled to the second clock signal line CK2. The third clock signal terminal CKD of the odd-numbered shift register unit is coupled to the fourth clock signal line CK4. The third clock signal terminal CKD of the even-numbered shift register unit is coupled to the third clock signal line CK3.

[0282] In an optional embodiment, the display panel further includes a plurality of power signal lines (VGA, VGB) coupled to the gate driving circuit 100 , and the extension direction of the plurality of power signal lines is the same as the arrangement direction of the plurality of shift register units.

[0283] In some embodiments, the display panel further includes a plurality of auxiliary control signal lines (VFE3, VFE4). An insulating layer is provided between the plurality of auxiliary control signal lines and the plurality of control signal lines. The plurality of auxiliary control signal lines correspond one-to-one to the plurality of control signal lines, and the corresponding auxiliary control signal lines and control signal lines are coupled to each other through vias penetrating the insulating layer. For example, in some embodiments, the plurality of auxiliary control signal lines include a first auxiliary control signal line VFE3 and a second auxiliary control signal line VFE4. The first auxiliary control signal line VFE3 is coupled to the first control sub-signal line VFE1, and the second auxiliary control signal line VFE4 is coupled to the second control sub-signal line VFE2.

[0284] In some embodiments, the display panel further includes a plurality of auxiliary clock signal lines (CK5, CK6, CK7, CK8). An insulating layer is provided between the plurality of auxiliary clock signal lines and the plurality of clock signal lines. The plurality of auxiliary clock signal lines correspond one-to-one to the plurality of clock signal lines, and the corresponding auxiliary clock signal lines and clock signal lines are coupled to each other through vias penetrating the insulating layer. For example, in some embodiments, the plurality of auxiliary clock signal lines include a first auxiliary clock signal line CK5, a second auxiliary clock signal line CK6, a third auxiliary clock signal line CK7, and a fourth auxiliary clock signal line CK8. The first auxiliary clock signal line CK5 is coupled to the first clock signal line CK1. The second auxiliary clock signal line CK6 is coupled to the second clock signal line CK2. The third auxiliary clock signal line CK7 is coupled to the third clock signal line CK3. The fourth auxiliary clock signal line CK8 is coupled to the fourth clock signal line CK4.

[0285] In some embodiments, the display panel further includes an auxiliary reset signal line. An insulating layer is provided between the auxiliary reset signal line and the reset signal line, and the two are coupled via a via extending through the insulating layer. For example, in some embodiments, the auxiliary reset signal line includes an auxiliary reset signal line STV1, which is coupled to the reset signal line STV.

[0286] In some embodiments, the plurality of auxiliary control signal lines, the plurality of auxiliary clock signal lines, and the auxiliary reset signal lines may be provided in the same layer, that is, formed through a same metal layer through a process such as etching.

[0287] As shown in Figures 3 and 8 to 16, in some selected embodiments, a display panel includes a base substrate 1000, on which an active layer poly, a gate layer gate1, a capacitor electrode layer gate2, a cascade layer gate3, a signal transmission trace layer SD1, and an auxiliary trace layer SD2 are sequentially arranged. An insulating layer is provided between each adjacent layer of the active layer poly, gate layer gate1, capacitor electrode layer gate2, cascade layer gate3, signal transmission trace layer SD1, and auxiliary trace layer SD2. Two layers that need to be coupled are coupled to each other vias that penetrate the insulating layer.

[0288] As shown in Figure 11, the active layer poly is provided with channels for all transistors. Optionally, the active layer poly can be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. Localized regions of the active layer poly can be selectively doped with n-type or p-type to meet the needs of forming transistors.

[0289] As shown in FIG12 , the gate layer gate1 includes the gate and scan line of each of the above transistors, wherein the gate of some transistors is reused as a plate of the above capacitor.

[0290] As shown in Figure 13, the capacitor electrode layer gate2 includes the other electrode plate of each of the above capacitors. The two electrodes with facing areas form the above capacitors.

[0291] As shown in FIG14 , the cascade layer gate3 includes a cascade line for coupling the input signal terminal IN of the next shift register unit with the first output signal terminal OUTA of the previous shift register unit.

[0292] As shown in FIG15 , the signal transmission wiring layer SD1 includes a clock signal line, a control signal line, and the source and drain of each of the above transistors.

[0293] As shown in FIG16 , the auxiliary wiring layer SD2 includes auxiliary control signal lines ( VFE3 , VFE4 ), power signal lines (VGA, VGB), auxiliary clock signal lines ( CK5 , CK6 , CK7 , CK8 ), and an auxiliary reset signal line ( STV1 ).

[0294] In some embodiments, the orthographic projections of the plurality of control signal lines ( VFE1 , VFE2 ) on the base substrate 1000 are located between the orthographic projection of the gate driving circuit 100 on the base substrate 1000 and the display area AA.

[0295] The orthographic projection of the gate driving circuit 100 on the base substrate 1000 is located between the orthographic projections of the multiple clock signal lines (CK1, CK2, CK3, CK4) on the base substrate 1000 and the orthographic projections of the multiple control signal lines (VFE1, VFE2) on the base substrate 1000.

[0296] The orthographic projection of the fourteenth transistor T14 on the substrate 1000 is located between the orthographic projection of the fourth transistor T4 on the substrate 1000 and the display area AA. The orthographic projection of the fifth transistor T15 on the substrate 1000 is located between the orthographic projection of the fifth transistor T5 on the substrate 1000 and the display area AA. Optionally, the orthographic projection of the fourteenth transistor T14 on the substrate 1000 is located between the orthographic projection of the fourth transistor T4 on the substrate 1000 and the orthographic projection of the control signal lines (VFE1, VFE2) on the substrate 1000. The orthographic projection of the fifth transistor T15 on the substrate 1000 is located between the orthographic projection of the fifth transistor T5 on the substrate 1000 and the orthographic projection of the control signal lines (VFE1, VFE2) on the substrate 1000.

[0297] It should be noted that the fourteenth transistor T14 and the fifteenth transistor T15 are larger than the fourth transistor T4, the fifth transistor T5, and other transistors to ensure the output function of the driving output terminal OUT. For example, the fourth transistor T4, the fifth transistor T5, and other transistors can be selected to have a width W to length L ratio of W / L = 3 / 3.5. The fourteenth transistor T14 and the fifteenth transistor T15 can be selected to have a width W to length L ratio greater than 3 / 3.5.

[0298] 8 and 10 , in some embodiments, the channel width of the fourteenth transistor T14 is greater than the channel width of the fourth transistor T4 .

[0299] In some embodiments, a channel width of the fourteenth transistor T14 is not less than 100 μm.

[0300] In some embodiments, the channel width of the fourth transistor T4 is no greater than 60 μm.

[0301] In some embodiments, a channel width of the fifteenth transistor T15 is greater than a channel width of the fifth transistor T5 .

[0302] In some embodiments, a channel width of the fifteenth transistor T15 is not less than 100 μm.

[0303] In some embodiments, the channel width of the fifth transistor T5 is no greater than 60 μm.

[0304] The orthographic projections of the power signal lines (VGA, VGB) on the base substrate 1000 are located between the orthographic projections of the control signal lines (VFE1, VFE2) on the base substrate 1000 and the orthographic projections of the clock signal lines (CK1, CK2, CK3, CK4) on the base substrate 1000.

[0305] In some embodiments, the orthographic projection of the first auxiliary control signal line VFE3 on the base substrate 1000 overlaps with the orthographic projection of the control sub-signal line VFE1 on the base substrate 1000, and the orthographic projection of the second auxiliary control signal line VFE4 on the base substrate 1000 overlaps with the orthographic projection of the second control sub-signal line VFE2 on the base substrate 1000. The first auxiliary control signal line VFE3 is coupled to the first control sub-signal line VFE1 through a via in the insulating layer. The second auxiliary control signal line VFE4 is coupled to the second control sub-signal line VFE2 through a via in the insulating layer.

[0306] In some embodiments, the orthographic projection of the first auxiliary clock signal line CK5 on the base substrate 1000 overlaps with the orthographic projection of the first clock signal line CK1 on the base substrate 1000. The orthographic projection of the second auxiliary clock signal line CK6 on the base substrate 1000 overlaps with the orthographic projection of the second clock signal line CK2 on the base substrate 1000. The orthographic projection of the third auxiliary clock signal line CK7 on the base substrate 1000 overlaps with the orthographic projection of the third clock signal line CK3 on the base substrate 1000. The orthographic projection of the fourth auxiliary clock signal line CK8 on the base substrate 1000 overlaps with the orthographic projection of the fourth clock signal line CK4 on the base substrate 1000.

[0307] In some embodiments, an orthographic projection of the auxiliary reset signal line STV1 on the base substrate 1000 overlaps with an orthographic projection STV of the reset signal line on the base substrate 1000 .

[0308] The overlap mentioned here can be understood as the overlap of part of the area or the whole area.

[0309] In some embodiments, the orthographic projection of the fourth capacitor C4 on the substrate 1000 is located on a side of the shift register unit close to the next stage shift register unit.

[0310] As shown in FIG. 4 , the present application further provides a display device, which includes the display panel and the driving control circuit 11 as described above.

[0311] The drive control circuit 11 is coupled to the display panel and is configured to input a first signal to the control signal terminal VFE of the multiple shift register units (for example, G1, G2, G3, G4, G5, G6, G7, and G8 in Figure 4) when it is determined to adopt the full-screen refresh mode, so that the multiple shift register units (for example, G1, G2, G3, G4, G5, G6, G7, and G8 in Figure 4) output gate scan signals in sequence to drive the scan lines GA row by row.

[0312] When it is determined to adopt the partial refresh mode, a second signal is input to the control signal terminal VFE of the plurality of shift register units (e.g., G1, G2, G3, G4, G5, G6, G7, G8 in FIG4 ), so that some of the shift register units (e.g., G1, G2, G3, G4, G5, G6, G7, G8 in FIG4 ) sequentially output gate scan signals, and the remaining shift register units output invalid scan signals. Exemplarily, the second signal is input to the control signal terminal VFE of the plurality of shift register units G1, G2, G3, G4, G5, G6, G7, G8, so that some of the shift register units G1, G2, G3, G4, G5, G6, G7, G8 sequentially output gate scan signals, and the remaining shift register units G5, G6, G7, G8 output invalid scan signals.

[0313] Exemplarily, the gate scanning signal is a high-level signal, and the invalid scanning signal is a low-level signal, or the gate scanning signal is a low-level signal, and the invalid scanning signal is a high-level signal, which is not limited here.

[0314] As shown in FIG. 5 , the present application further provides a driving method, which can be applied to the above-mentioned display device or display panel to drive the above-mentioned display panel, and can include the following steps S100 and S200:

[0315] In S100, when it is determined to adopt the full-area refresh mode, a first signal is output to the control signal terminal VFE of the multiple shift register units (for example, G1, G2, G3, G4, G5, G6, G7, and G8 in Figure 4), so that the multiple shift register units (for example, G1, G2, G3, G4, G5, G6, G7, and G8 in Figure 4) output gate scan signals in sequence to drive the scan lines row by row.

[0316] As shown in FIG6 , in some embodiments, the first signal is a clock signal, such as the V1 signal in FIG6 , which may be a clock signal alternating between a first level and a second level.

[0317] In S200, when it is determined to adopt the partition refresh mode, a second signal is output to the control signal end of the multiple shift register units (for example, G1, G2, G3, G4, G5, G6, G7, and G8 in Figure 4), so that some of the multiple shift register units (for example, G1, G2, G3, G4, G5, G6, G7, and G8 in Figure 4) output gate scan signals in sequence, and the remaining shift register units output invalid scan signals to drive some of the scan lines.

[0318] As shown in FIG7 , in some embodiments, the second signal includes a fixed signal portion having a clock signal and a fixed signal portion having a second level. The second level is the level of an inactive gate scan signal. The fixed signal portion having a clock signal is input to some of the shift register units, and the fixed signal portion having the second level is input to the remaining shift register units. For example, as shown in FIG7 , the second signal includes a fixed signal portion V2 having a clock signal and a fixed signal portion V3 having a second level. This second signal inputs a valid signal to the shift register units G1, G2, G3, and G4, causing the shift register units G1, G2, G3, and G4 to sequentially output valid gate scan signals, driving the scan lines row by row; and inputs an invalid signal to the shift register units G5, G6, G7, and G8, causing the shift register units G5, G6, G7, and G8 to output invalid scan signals, thereby driving some of the scan lines. For example, the fixed signal portion having a clock signal can be a clock signal that alternates between a first level and a second level.

[0319] Optionally, the gate scanning signal is a high-level signal and the invalid scanning signal is a low-level signal, or the gate scanning signal is a low-level signal and the invalid scanning signal is a high-level signal, which is not limited here.

[0320] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit structure shown in FIG2 as an example, in combination with the signal timing diagram shown in FIG6 , and in combination with FIG3 and FIG4 when necessary.

[0321] The control signal line includes a first control sub-signal line VFE1 and a second control sub-signal line VFE2. The first control sub-signal line VFE1 is coupled to the control signal terminal VFE of the odd-numbered shift register unit, and the second control sub-signal line VFE2 is coupled to the control signal terminal VFE of the even-numbered shift register unit. For example, the first control sub-signal line VFE1 is coupled to the control signal terminals VFE of the shift register units G1, G3, G5, and G7. The second control sub-signal line VFE2 is coupled to the control signal terminals VFE of G2, G4, G6, and G8. The clock signal line includes a first clock signal line CK1, a second clock signal line CK2, a third clock signal line CK3, and a fourth clock signal line CK4. The first clock signal terminal CKA of the odd-numbered shift register unit and the second clock signal terminal CKB of the even-numbered shift register unit are coupled to the first clock signal line CK1. The second clock signal terminals CKB of the odd-numbered shift register units and the first clock signal terminals CKA of the even-numbered shift register units are coupled to the second clock signal line CK2. The third clock signal terminals CKD of the odd-numbered shift register units are coupled to the fourth clock signal line CK4. The third clock signal terminals CKD of the even-numbered shift register units are coupled to the third clock signal line CK3. For example, the first clock signal terminals CKA of the shift register units G1, G3, G5, and G7 and the second clock signal terminals CKB of the shift register units G2, G4, G6, and G8 are coupled to the first clock signal line CK1. The second clock signal terminals CKB of the shift register units G1, G3, G5, and G7 and the first clock signal terminals CKA of the shift register units G2, G4, G6, and G8 are coupled to the second clock signal line CK2. The third clock signal terminals CKD of the shift register units G1, G3, G5, and G7 are coupled to the fourth clock signal line CK4. The third clock signal terminals CKD of the shift register units G2 , G4 , G6 , and G8 are coupled to the third clock signal line CK3 .

[0322] Assume that all transistors are P-type transistors, the effective pulse signal of the signal output by the first power sub-signal terminal VGA is a low-level signal, the effective pulse signal of the signal output by the second power sub-signal terminal VGB is a low-level signal, the first signal is a clock signal alternating between a first level and a second level, the second signal includes a fixed signal portion having a clock signal alternating between a first level and a second level and a fixed signal portion having a second level, wherein the first level is a high level and the second level is a low level.

[0323] In represents the input signal at the input signal terminal IN, ck1 represents the clock signal output by the first clock signal line CK1, ck2 represents the clock signal output by the second clock signal terminal CK2, ck3 represents the clock signal output by the third clock signal line CK3, and ck4 represents the clock signal output by the fourth clock signal terminal CK4. cka represents the first clock signal at the first clock signal terminal CLKA, ckb represents the second clock signal at the second clock signal terminal CLKB, and ckd represents the third clock signal at the second clock signal terminal CKD. ck3 and ck4 are alternately connected to the third clock signal terminal CKD between two adjacent stages. ck1 and ck2 are alternately connected to the first clock signal terminal CKA between two adjacent stages, and ck2 and ck1 are alternately connected to the second clock signal terminal CKB between two adjacent stages. vfe1 represents the control signal output by the control signal line VFE1, and vfe2 represents the control signal output by the second control signal line VFE2. vfe represents the control signal output by the control signal terminal VFE. ot1 to otn represent the cascade signals output by the cascade output terminal OT in the nth shift register unit Gn. out1 to outn represent gate scanning signals outputted from the driving signal terminal OUT in the n-th shift register unit Gn.

[0324] Since the control electrodes of the eighth transistor T8, the eleventh transistor T11, the sixteenth transistor T16, and the seventeenth transistor T17 are all coupled to the first power signal terminal VGA, which is a signal terminal that maintains a low-level output, the eighth transistor T8, the eleventh transistor T11, the sixteenth transistor T16, and the seventeenth transistor T17 are normally-on transistors. Therefore, the on-off states of the eighth transistor T8, the eleventh transistor T11, the sixteenth transistor T16, and the seventeenth transistor T17 will not be analyzed below.

[0325] Based on the shift register unit shown in FIG2 , in the first phase H1, clock signal ck1 is always a high-level signal, clock signal ck2 is always a low-level signal, clock signal ck4 is always a low-level signal, and input signal in is a low-level signal. Third node N3 is connected to input signal terminal IN, so third node N3 always remains at a low level. Eleventh transistor T11 responds to VGA, and the potential of fifth node N5 always remains at a low level. Controlled by the potential of fifth node N5, twelfth transistor T12 turns on, fourth node N4 is connected to third power sub-signal terminal CKD, fourth node N4 remains at a low level, and first node N1 remains at a low level. Controlled by the potential of fifth node N5, second node N2 remains at a low level. First output signal terminal OT outputs a low-level signal, and second output signal terminal OUT outputs a low-level signal.

[0326] In the second phase H2, the clock signal ck1 is always high, the clock signal ck2 is always low, the clock signal ck4 is always high, and the input signal in is a high. The third node N3 is high. The eleventh transistor T11 responds to VGA, and the potential of the fifth node N5 remains high. The second node N2 remains high. The fourth node N4 remains low, and the first node N1 remains low. The first output signal terminal OT outputs a low signal, and the second output signal terminal OUT outputs a low signal.

[0327] In the third phase H3, the clock signal ck1 is always high, the clock signal ck2 is always high, the clock signal ck4 is always high, and the input signal in is high. The third node N3 is low, the fifth node N5 and the second node N2 are low, the sixth node is high, the fourth node N4 is high, and the first node N1 is high. The first output signal terminal OT outputs a low signal, and the second output signal terminal OUT outputs a low signal.

[0328] In the fourth phase H4, the clock signal ck1 remains low, the clock signal ck2 remains high, the clock signal ck4 remains high, and the input signal in remains high. The third node N3 remains low. The fifth node N5 and the second node N2 remain low. The fourth node remains high, and the first node N1 remains high. The first output signal terminal OT outputs a low signal, and the second output signal terminal OUT outputs a low signal.

[0329] In the fifth stage H5, clock signal ck1 remains low, clock signal ck2 remains high, clock signal ck4 remains low, and input signal in remains low. Third node N3 remains low. Fifth node N5 and second node N2 remain low. Fourth node remains high, and first node N1 remains high. First output signal terminal OT outputs a low signal, and second output signal terminal OUT outputs a low signal.

[0330] Similarly, in the sixth stage H6, clock signal ck1 is always a low-level signal, clock signal ck2 is always a high-level signal, clock signal ck4 is always a low-level signal, and in is always a low-level signal. The third node N3 remains at a low level, and the fifth node N5 and the second node N2 remain at a low level. The sixth node N6 is at a low level, the fourth node N4 is at a low level, and the first node N1 is at a low level. The first output signal terminal OT outputs a low-level signal, and the second output signal terminal OUT outputs a low-level signal.

[0331] In the seventh stage H7, clock signal ck1 remains at a low level, clock signal ck2 remains at a low level, clock signal ck4 remains at a low level, and in remains at a low level. The third node N3 remains at a low level, as do the fifth and second nodes N5 and N2. The sixth node N6 remains at a low level, the fourth node N4 remains at a low level, and the first node N1 remains at a low level. The first output signal terminal OT outputs a high level signal, and the second output signal terminal OUT outputs a high level signal.

[0332] In the eighth stage H8, clock signal ck1 remains high, clock signal ck2 remains high, clock signal ck4 remains low, and in remains low. The third node N3 remains low, while the fifth and second nodes N5 and N2 remain low. The sixth node N6 remains high, the fourth node N4 remains low, and the first node N1 remains low. The first output signal terminal OT outputs a high signal, and the second output signal terminal OUT outputs a high signal.

[0333] In the ninth stage H9, clock signal ck1 remains high, clock signal ck2 remains low, clock signal ck4 remains low, and in remains low. The third node N3 remains low, while the fifth and second nodes N5 and N2 remain low. The sixth node N6 remains high, the fourth node N4 remains low, and the first node N1 remains low. The first output signal terminal OT outputs a high signal, and the second output signal terminal OUT outputs a high signal.

[0334] In the tenth stage H10, clock signal ck1 remains high, clock signal ck2 remains low, clock signal ck4 remains low, and in remains low. The third node N3 remains low, and the fifth and second nodes N5 and N2 remain low. The sixth node N6 remains high, the fourth node N4 remains low, and the first node N1 remains low. The first output signal terminal OT outputs a low signal, and the second output signal terminal OUT outputs a low signal.

[0335] As shown in Figure 6, in some embodiments, the valid gate scan signal output by the next shift register unit is 1H later than that of the previous shift register unit, where 1H = 2.73μs. The pulse width of the input signal in is R2 = 1.73μs. The clock signal ck1 output by the first clock signal line CK1 has a cycle of 2H, its high-level pulse width is Q1 + Q2, and its low-level pulse width is R1, R1 = 2.13μs, Q1 = 1.66μs, and Q2 = 1.67μs. The clock signal ck2 output by the second clock signal line CK2 has a cycle of 2H, its high-level pulse width is also Q1 + Q2, and its low-level pulse width is also R1. The clock signal ck3 output by the third clock signal line CK3 has a cycle of 2H. The clock signal ck4 output by the fourth clock signal line CK4 is a clock signal that alternates between a 1H high-level pulse width and a 1H low-level signal. The clock signal in ck4, which alternates with the low-level signal, has a high-level pulse width of R2 = 1.73s. The low-level pulse widths connected to the adjacent low-level signals are both Q3 = 0.5μs. The first clock signal cka at the first clock signal terminal CKA is a clock signal formed by alternating between ck1 and ck2. The second clock signal ckb at the second clock signal terminal CKB is a clock signal formed by alternating between ck1 and ck2. The third clock signal ckd at the third clock signal terminal CKD is a clock signal formed by alternating between ck3 and ck4. vfe1 is consistent with ck3, and vfe2 is consistent with ck4. For details of ck1, ck2, ck3, ck4, cka, ckb, ckd, vfe1, and vfe2, see Figure 6.

[0336] For example, in a display panel with 1024 rows of pixels, there are 512 shift register units, each of which controls two rows of pixels. Eight adjacent shift register units form a group, for a total of 64 groups. The control signal terminals VFE of the shift register units in the odd-numbered groups are coupled to the first control sub-signal line VFE1, and the control signal terminals VFE of the shift register units in the even-numbered groups are coupled to the second control sub-signal line VFE2. When the first control sub-signal line VFE1 and the second control sub-signal line VFE2 are controlled to output the second signal, the shift register units in the first to thirty-second groups output valid gate scan signals in each of the 120 frames, and the shift register units in the thirty-third to sixty-fourth groups output valid gate scan signals every other frame in the 120 frames. This allows the display panel's first 512 rows of pixels to be controlled at 120 Hz, while the last 512 rows of pixels to be controlled at 60 Hz, thereby achieving partitioned refresh. Of course, the first control sub-signal line VFE1 and the second control sub-signal line VFE2 may also be controlled to output the second signal so that any group outputs a valid gate scan signal or an invalid gate scan signal in any frame to achieve partitioned refresh of the display panel.

[0337] Other embodiments of the present invention will readily occur to those skilled in the art upon consideration of the present invention and practice of the invention claimed herein. This specification is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of this specification and include common knowledge or customary techniques in the art not claimed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present invention being indicated by the following claims.

[0338] It should be understood that the present description is not limited to the exact structure that has been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present description is limited only by the appended claims.

[0339] The above description is only a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this specification should be included in the scope of protection of this specification.

Claims

1. A shift register unit, characterized in that: include: an input subcircuit connected to the third node, the input signal terminal, the first clock signal terminal and the third clock signal terminal, and configured to provide the signal of the input signal terminal to the third node in response to the signals of the first clock signal terminal and the third clock signal terminal; a control subcircuit connected to the third node, the first node, the second node, the first power signal terminal, the second power signal terminal, the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal, and configured to control the signals of the first node and the second node in response to the signals of the first power signal terminal, the second power signal terminal, the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal, and to provide the signal of the third node to the first node or the second node; A first output subcircuit is connected to the first node, the second node, the third clock signal terminal, the first power signal terminal and the cascade output terminal, and is configured to respond to the signals of the first node and the second node so that the cascade output terminal outputs a cascade signal; The second output subcircuit is connected to the first node, the second node, the control signal terminal, the first power signal terminal and the driving output terminal, and is configured to respond to the signals of the first node and the second node to enable the driving output terminal to output a gate scanning signal.

2. The shift register unit according to claim 1, characterized in that: The second output sub-circuit comprises: A first output module, together with the control signal terminal, the first node and the driving output terminal, is configured to transmit the signal of the control signal terminal to the driving output terminal under the control of the first node; The second output module is connected to the first power signal terminal, the second node and the driving output terminal, and is configured to transmit the signal of the first power signal terminal to the driving output terminal under the control of the second node.

3. The shift register unit according to claim 2, characterized in that: The first output module includes a fourteenth transistor, a first electrode of the fourteenth transistor is connected to the control signal terminal, a second electrode of the fourteenth transistor is connected to the driving output terminal, and a control electrode of the fourteenth transistor is connected to the second node.

4. The shift register unit according to claim 2, characterized in that: The second output module includes a fifteenth transistor, a first electrode of the fifteenth transistor is connected to the first power signal terminal, a second electrode of the fifteenth transistor is connected to the driving output terminal, and a control electrode of the fifteenth transistor is connected to the second node.

5. The shift register unit according to claim 1, characterized in that: The first output sub-circuit comprises: a fourth transistor, wherein a first electrode of the fourth transistor is connected to the third clock signal terminal, a second electrode of the fourth transistor is connected to the cascade output terminal, and a control electrode of the fourth transistor is connected to the first node; A fifth transistor, wherein a first electrode of the fifth transistor is connected to the first power signal terminal, a second electrode of the fifth transistor is connected to the cascade output terminal, and a control electrode of the fifth transistor is connected to the second node.

6. The shift register unit according to claim 5, characterized in that: The first output subcircuit further includes a third capacitor, a first end of the third capacitor is connected to the first electrode of the fourth transistor, and a second end of the third capacitor is connected to the control electrode of the fourth transistor; and / or, The first output subcircuit further includes a fourth capacitor, a first end of the fourth capacitor is connected to the cascade output end, and a second end of the fourth capacitor is connected to the first power signal end.

7. The shift register unit according to claim 1, characterized in that: The input sub-circuit includes a thirteenth transistor and a second transistor: A first electrode of the thirteenth transistor is connected to the input signal terminal, a second electrode of the thirteenth transistor is connected to the first electrode of the second transistor, and a control electrode of the thirteenth transistor is connected to the third clock signal terminal; The second electrode of the second transistor is connected to the third node, and the control electrode of the second transistor is connected to the first clock signal terminal.

8. The shift register unit according to claim 1, characterized in that: The control subcircuit includes a first control submodule, a first voltage stabilizing module and a second voltage stabilizing module: The first control submodule is connected to the third node, the fourth node, the fifth node, the first power signal terminal, the second power signal terminal, the first clock signal terminal, the second clock signal terminal and the third clock signal terminal, and is configured to control the signals of the fourth node and the fifth node in response to the signals of the first power signal terminal, the second power signal terminal, the first clock signal terminal, the second clock signal terminal and the third clock signal terminal, and provide the signal of the third node to the fourth node or the fifth node; The first voltage stabilizing module is connected to the fourth node, the first node and the first power signal terminal, and is configured to provide the voltage of the fourth node to the first node in response to a signal of the first power signal terminal; The second voltage stabilizing module is connected to the fifth node, the second node and the first power signal terminal, and is configured to provide the voltage of the fifth node to the second node in response to a signal of the first power signal terminal.

9. The shift register unit according to claim 8, characterized in that: The first control submodule includes a first transistor, a sixth transistor, an eighth transistor, a ninth transistor, a tenth transistor, a third transistor, a seventh transistor, an eleventh transistor, a twelfth transistor, a first capacitor and a second capacitor; wherein, The first electrode of the first transistor is connected to the first clock signal terminal, the second electrode of the first transistor is connected to the sixth node, and the control electrode of the first transistor is connected to the third node; A first electrode of the sixth transistor is connected to the first power signal terminal, a second electrode of the sixth transistor is connected to the sixth node, and a control electrode of the sixth transistor is connected to the first clock signal terminal; The first electrode of the eighth transistor is connected to the sixth node, the second electrode of the eighth transistor is connected to the control electrode of the ninth transistor, and the control electrode of the eighth transistor is connected to the first power signal terminal; The first electrode of the ninth transistor is connected to the second clock signal terminal, and the second electrode of the ninth transistor is connected to the first electrode of the tenth transistor; The second electrode of the tenth transistor is connected to the fourth node, and the control electrode of the tenth transistor is connected to the second clock signal terminal; A first electrode of the third transistor is connected to the second clock signal terminal, a second electrode of the third transistor is connected to the second electrode of the seventh transistor, and a control electrode of the third transistor is connected to the fifth node; The first electrode of the seventh transistor is connected to the second power signal terminal, and the control electrode of the seventh transistor is connected to the sixth node; The first electrode of the eleventh transistor is connected to the third node, the second electrode of the eleventh transistor is connected to the fifth node, and the control electrode of the eleventh transistor is connected to the first power signal terminal; The first electrode of the twelfth transistor is connected to the third clock signal terminal, the second electrode of the twelfth transistor is connected to the fourth node, and the control electrode of the twelfth transistor is connected to the fifth node; A first electrode of the first capacitor is connected to the fifth node, and a second electrode of the first capacitor is connected to the second electrode of the third transistor; A first electrode of the second capacitor is connected to the control electrode of the ninth transistor, and a second electrode of the second capacitor is connected to the second electrode of the ninth transistor; The first voltage stabilizing module includes a sixteenth transistor, a first electrode of the sixteenth transistor is connected to the fourth node, a second electrode of the sixteenth transistor is connected to the first node, and a control electrode of the sixteenth transistor is connected to the first power signal terminal; The second voltage stabilizing module includes a seventeenth transistor, a first electrode of the seventeenth transistor is connected to the fifth node, and a second electrode of the seventeenth transistor is connected to the first node.

10. The shift register unit according to claim 1, characterized in that: The control subcircuit includes a second control submodule, a third voltage stabilizing module and a fourth voltage stabilizing module: The second control submodule is connected to the third node, the fourth node, the first node, the first power signal terminal, the second power signal terminal, the first clock signal terminal, the second clock signal terminal and the third clock signal terminal, and is configured to control the signal of the fourth node in response to the signals of the first power signal terminal, the second power signal terminal, the first clock signal terminal, the second clock signal terminal and the third clock signal terminal, and provide the signal of the third node to the fourth node; The third voltage stabilizing module is connected to the fourth node, the first node and the first power signal terminal, and is configured to provide the voltage of the fourth node to the first node in response to a signal of the first power signal terminal; The fourth voltage stabilizing module is connected to the third node, the second node and the first power signal terminal, and is configured to provide the voltage of the third node to the second node in response to a signal of the first power signal terminal.

11. The shift register unit according to claim 10, characterized in that: The second control submodule includes a first transistor, a sixth transistor, an eighth transistor, a ninth transistor, a tenth transistor, a third transistor, a seventh transistor, a twelfth transistor, a first capacitor and a second capacitor; wherein, The first electrode of the first transistor is connected to the first clock signal terminal, the second electrode of the first transistor is connected to the sixth node, and the control electrode of the first transistor is connected to the third node; A first electrode of the sixth transistor is connected to the first power signal terminal, a second electrode of the sixth transistor is connected to the sixth node, and a control electrode of the sixth transistor is connected to the first clock signal terminal; The first electrode of the eighth transistor is connected to the sixth node, the second electrode of the eighth transistor is connected to the control electrode of the ninth transistor, and the control electrode of the eighth transistor is connected to the first power signal terminal; The first electrode of the ninth transistor is connected to the second clock signal terminal, and the second electrode of the ninth transistor is connected to the first electrode of the tenth transistor; The second electrode of the tenth transistor is connected to the fourth node, and the control electrode of the tenth transistor is connected to the second clock signal terminal; A first electrode of the third transistor is connected to the second clock signal terminal, a second electrode of the third transistor is connected to the second electrode of the seventh transistor, and a control electrode of the third transistor is connected to the third node; The first electrode of the seventh transistor is connected to the second power signal terminal, and the control electrode of the seventh transistor is connected to the sixth node; The first electrode of the twelfth transistor is connected to the third clock signal terminal, the second electrode of the twelfth transistor is connected to the fourth node, and the control electrode of the twelfth transistor is connected to the third node; A first electrode of the first capacitor is connected to the third node, and a second electrode of the first capacitor is connected to a second electrode of the third transistor; A first electrode of the second capacitor is connected to the control electrode of the ninth transistor, and a second electrode of the second capacitor is connected to the second electrode of the ninth transistor; The third voltage stabilizing module includes a sixteenth transistor, a first electrode of the sixteenth transistor is connected to the fourth node, a second electrode of the sixteenth transistor is connected to the first node, and a control electrode of the sixteenth transistor is connected to the first power signal terminal; The fourth voltage stabilizing module includes an eleventh transistor, a first electrode of the eleventh transistor is connected to the third node, and a second electrode of the eleventh transistor is connected to the first node.

12. The shift register unit according to claim 1, wherein: The control subcircuit includes a third control submodule and a fifth voltage stabilization module: The third control submodule is connected to the third node, the first node, the first power signal terminal, the second power signal terminal, the first clock signal terminal, the second clock signal terminal and the third clock signal terminal, and is configured to control the signal of the first node in response to the signals of the first power signal terminal, the second power signal terminal, the first clock signal terminal, the second clock signal terminal and the third clock signal terminal, and provide the signal of the third node to the first node; The fifth voltage stabilizing module is connected to the third node, the second node and the first power signal terminal, and is configured to provide the voltage of the third node to the second node in response to a signal of the first power signal terminal.

13. The shift register unit according to claim 12, characterized in that: The third control submodule includes a first transistor, a sixth transistor, an eighth transistor, a ninth transistor, a tenth transistor, a third transistor, a seventh transistor, a twelfth transistor, a first capacitor and a second capacitor; wherein, The first electrode of the first transistor is connected to the first clock signal terminal, the second electrode of the first transistor is connected to the sixth node, and the control electrode of the first transistor is connected to the third node; A first electrode of the sixth transistor is connected to the first power signal terminal, a second electrode of the sixth transistor is connected to the sixth node, and a control electrode of the sixth transistor is connected to the first clock signal terminal; The first electrode of the eighth transistor is connected to the sixth node, the second electrode of the eighth transistor is connected to the control electrode of the ninth transistor, and the control electrode of the eighth transistor is connected to the first power signal terminal; The first electrode of the ninth transistor is connected to the second clock signal terminal, and the second electrode of the ninth transistor is connected to the first electrode of the tenth transistor; The second electrode of the tenth transistor is connected to the first node, and the control electrode of the tenth transistor is connected to the second clock signal terminal; A first electrode of the third transistor is connected to the second clock signal terminal, a second electrode of the third transistor is connected to the second electrode of the seventh transistor, and a control electrode of the third transistor is connected to the third node; The first electrode of the seventh transistor is connected to the second power signal terminal, and the control electrode of the seventh transistor is connected to the sixth node; The first electrode of the twelfth transistor is connected to the third clock signal terminal, the second electrode of the twelfth transistor is connected to the first node, and the control electrode of the twelfth transistor is connected to the third node; A first electrode of the first capacitor is connected to the third node, and a second electrode of the first capacitor is connected to a second electrode of the third transistor; A first electrode of the second capacitor is connected to the control electrode of the ninth transistor, and a second electrode of the second capacitor is connected to the second electrode of the ninth transistor; The fifth voltage stabilizing module includes an eleventh transistor, a first electrode of the eleventh transistor is connected to the third node, and a second electrode of the eleventh transistor is connected to the first node.

14. The shift register unit according to claim 1, characterized in that: The control subcircuit includes a fourth control submodule and a sixth voltage stabilization module: The fourth control submodule is connected to the third node, the first node, the fifth node, the first power signal terminal, the second power signal terminal, the first clock signal terminal, the second clock signal terminal and the third clock signal terminal, and is configured to control the signals of the first node and the fifth node in response to the signals of the first power signal terminal, the second power signal terminal, the first clock signal terminal, the second clock signal terminal and the third clock signal terminal, and provide the signal of the third node to the first node or the fifth node; The sixth voltage stabilizing module is connected to the fifth node, the second node and the first power signal terminal, and is configured to provide the voltage of the fifth node to the second node in response to a signal of the first power signal terminal.

15. The shift register unit according to claim 14, characterized in that: The fourth control submodule includes a first transistor, a sixth transistor, an eighth transistor, a ninth transistor, a tenth transistor, a third transistor, a seventh transistor, an eleventh transistor, a twelfth transistor, a first capacitor and a second capacitor; wherein, The first electrode of the first transistor is connected to the first clock signal terminal, the second electrode of the first transistor is connected to the sixth node, and the control electrode of the first transistor is connected to the third node; A first electrode of the sixth transistor is connected to the first power signal terminal, a second electrode of the sixth transistor is connected to the sixth node, and a control electrode of the sixth transistor is connected to the first clock signal terminal; The first electrode of the eighth transistor is connected to the sixth node, the second electrode of the eighth transistor is connected to the control electrode of the ninth transistor, and the control electrode of the eighth transistor is connected to the first power signal terminal; The first electrode of the ninth transistor is connected to the second clock signal terminal, and the second electrode of the ninth transistor is connected to the first electrode of the tenth transistor; The second electrode of the tenth transistor is connected to the first node, and the control electrode of the tenth transistor is connected to the second clock signal terminal; A first electrode of the third transistor is connected to the second clock signal terminal, a second electrode of the third transistor is connected to the second electrode of the seventh transistor, and a control electrode of the third transistor is connected to the fifth node; The first electrode of the seventh transistor is connected to the second power signal terminal, and the control electrode of the seventh transistor is connected to the sixth node; The first electrode of the eleventh transistor is connected to the third node, the second electrode of the eleventh transistor is connected to the fifth node, and the control electrode of the eleventh transistor is connected to the first power signal terminal; A first electrode of the twelfth transistor is connected to the third clock signal terminal, a second electrode of the twelfth transistor is connected to the first node, and a control electrode of the twelfth transistor is connected to the fifth node; A first electrode of the first capacitor is connected to the fifth node, and a second electrode of the first capacitor is connected to the second electrode of the third transistor; A first electrode of the second capacitor is connected to the control electrode of the ninth transistor, and a second electrode of the second capacitor is connected to the second electrode of the ninth transistor; The sixth voltage stabilization module includes a seventeenth transistor, a first electrode of the seventeenth transistor is connected to the fifth node, and a second electrode of the seventeenth transistor is connected to the first node.

16. The shift register unit according to claim 1, characterized in that: The control subcircuit includes a fifth control submodule and a seventh voltage stabilization module: The fifth control submodule is connected to the third node, the fourth node, the second node, the first power signal terminal, the second power signal terminal, the first clock signal terminal, the second clock signal terminal and the third clock signal terminal, and is configured to control the signals of the fourth node and the second node in response to the signals of the first power signal terminal, the second power signal terminal, the first clock signal terminal, the second clock signal terminal and the third clock signal terminal, and provide the signal of the third node to the fourth node or the second node; The seventh voltage stabilizing module is connected to the fourth node, the first node and the first power signal terminal, and is configured to provide the voltage of the fourth node to the first node in response to a signal of the first power signal terminal.

17. The shift register unit according to claim 16, characterized in that: The fifth control submodule includes a first transistor, a sixth transistor, an eighth transistor, a ninth transistor, a tenth transistor, a third transistor, a seventh transistor, an eleventh transistor, a twelfth transistor, a first capacitor and a second capacitor; wherein, The first electrode of the first transistor is connected to the first clock signal terminal, the second electrode of the first transistor is connected to the sixth node, and the control electrode of the first transistor is connected to the third node; A first electrode of the sixth transistor is connected to the first power signal terminal, a second electrode of the sixth transistor is connected to the sixth node, and a control electrode of the sixth transistor is connected to the first clock signal terminal; The first electrode of the eighth transistor is connected to the sixth node, the second electrode of the eighth transistor is connected to the control electrode of the ninth transistor, and the control electrode of the eighth transistor is connected to the first power signal terminal; The first electrode of the ninth transistor is connected to the second clock signal terminal, and the second electrode of the ninth transistor is connected to the first electrode of the tenth transistor; The second electrode of the tenth transistor is connected to the fourth node, and the control electrode of the tenth transistor is connected to the second clock signal terminal; A first electrode of the third transistor is connected to the second clock signal terminal, a second electrode of the third transistor is connected to the second electrode of the seventh transistor, and a control electrode of the third transistor is connected to the second node; The first electrode of the seventh transistor is connected to the second power signal terminal, and the control electrode of the seventh transistor is connected to the sixth node; The first electrode of the eleventh transistor is connected to the third node, the second electrode of the eleventh transistor is connected to the second node, and the control electrode of the eleventh transistor is connected to the first power signal terminal; The first electrode of the twelfth transistor is connected to the third clock signal terminal, the second electrode of the twelfth transistor is connected to the fourth node, and the control electrode of the twelfth transistor is connected to the second node; A first electrode of the first capacitor is connected to the second node, and a second electrode of the first capacitor is connected to the second electrode of the third transistor; A first electrode of the second capacitor is connected to the control electrode of the ninth transistor, and a second electrode of the second capacitor is connected to the second electrode of the ninth transistor; The seventh voltage stabilization module includes a sixteenth transistor, a first electrode of the sixteenth transistor is connected to the fourth node, a second electrode of the sixteenth transistor is connected to the first node, and a control electrode of the sixteenth transistor is connected to the first power signal terminal.

18. A display panel, characterized in that: include: A substrate, comprising a display area and a non-display area; The display area includes: Multiple sub-pixels; A plurality of scan lines, wherein a row of the sub-pixels in the plurality of sub-pixels is correspondingly coupled to at least one of the scan lines in the plurality of scan lines; The non-display area includes: A gate drive circuit, comprising a plurality of shift register units according to any one of claims 1 to 17, wherein a drive output terminal of each shift register unit is correspondingly connected to at least one of the plurality of scan lines; and among two adjacent shift register units, an input signal terminal of a next shift register unit is coupled to a cascade output terminal of a previous shift register unit.

19. The display panel according to claim 18, characterized in that: The display panel further comprises a plurality of control signal lines coupled to the gate driving circuit; the extension direction of the plurality of control signal lines is the same as the arrangement direction of the plurality of shift register units.

20. The display panel according to claim 19, characterized in that: The orthographic projections of the plurality of control signal lines on the base substrate are located between the orthographic projection of the gate driving circuit on the base substrate and the display area.

21. The display panel according to claim 19, characterized in that: The plurality of control signal lines include a first control sub-signal line and a second control sub-signal line; the first control sub-signal line is coupled to the control signal end of the odd-numbered shift register unit, and the second control sub-signal line is coupled to the control signal end of the even-numbered shift register unit.

22. The display panel according to claim 19, characterized in that: The display panel further comprises a plurality of auxiliary control signal lines, wherein an insulating layer is provided between the plurality of auxiliary control signal lines and the plurality of control signal lines; The plurality of auxiliary control signal lines correspond to the plurality of control signal lines one by one, and the corresponding auxiliary control signal lines and control signal lines are coupled to each other through vias penetrating the insulating layer.

23. The display panel according to claim 20, characterized in that: The display panel further includes a plurality of clock signal lines, and the extension direction of the plurality of clock signal lines is the same as the arrangement direction of the plurality of shift register units.

24. The display panel according to claim 23, characterized in that: The orthographic projection of the gate driving circuit on the base substrate is located between the orthographic projections of the plurality of clock signal lines on the base substrate and the orthographic projections of the plurality of control signal lines on the base substrate.

25. The display panel according to claim 23, characterized in that: The display panel includes a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line; wherein, The first clock signal terminals of the odd-numbered shift register units and the second clock signal terminals of the even-numbered shift register units are coupled to the first clock signal line; The second clock signal terminals of the odd-numbered shift register units and the first clock signal terminals of the even-numbered shift register units are coupled to the second clock signal line; The third clock signal terminal of the odd-numbered shift register unit is coupled to the fourth clock signal line; The third clock signal terminal of the even-numbered shift register unit is coupled to the third clock signal line.

26. The display panel according to claim 18, wherein: When the first output sub-circuit includes a fourth capacitor, the orthographic projection of the fourth capacitor C4 on the substrate is located at a side of the shift register unit currently located by the fourth capacitor close to the next-stage shift register unit.

27. The display panel according to claim 18, wherein: When the first output sub-circuit includes a fourth capacitor, the fourth capacitor C4 is smaller than 120 farads.

28. The display panel according to any one of claims 18 to 27, characterized in that: When the first output sub-circuit includes a fourth transistor and the second output sub-circuit includes a fourteenth transistor, the orthographic projection of the fourteenth transistor on the substrate is located between the orthographic projection of the fourth transistor on the substrate and the display area; when the first output sub-circuit includes a fifth transistor and the second output sub-circuit includes a fifteenth transistor, the orthographic projection of the fifteenth transistor on the substrate is located between the orthographic projection of the fifth transistor on the substrate and the display area.

29. The display panel according to claim 28, characterized in that: A channel width of the fourteenth transistor is greater than a channel width of the fourth transistor.

30. The display panel according to claim 29, characterized in that: The channel width of the fourteenth transistor is not less than 100 microns.

31. The display panel according to claim 29, characterized in that: The channel width of the fourth transistor is no greater than 60 micrometers.

32. The display panel according to claim 28, characterized in that: A channel width of the fifteenth transistor is greater than a channel width of the fifth transistor.

33. The display panel according to claim 32, characterized in that: The channel width of the fifteenth transistor is not less than 100 microns.

34. The display panel according to claim 32, characterized in that: The channel width of the fifth transistor is not greater than 60 micrometers.

35. A display device, characterized in that: include: The display panel according to any one of claims 18 to 34; A drive control circuit coupled to the display panel and configured to input a first signal to the control signal terminals of the plurality of shift register units when it is determined to adopt a full-screen refresh mode, so that the plurality of shift register units sequentially output gate scan signals and drive the scan lines row by row; When it is determined to adopt the partial refresh mode, a second signal is input to the control signal terminal of the plurality of shift register units, so that some of the plurality of shift register units output gate scanning signals in sequence, and the remaining shift register units output invalid scanning signals.

36. A driving method for driving a display panel according to any one of claims 18 to 34, characterized in that: include: When it is determined to adopt the full-area refresh mode, outputting a first signal to the control signal terminals of the plurality of shift register units, so that the plurality of shift register units sequentially output gate scanning signals and drive the scanning lines row by row; When it is determined to adopt the partition refresh mode, a second signal is output to the control signal end of the multiple shift register units, so that some of the multiple shift register units output gate scan signals in sequence, and the remaining shift register units output invalid scan signals to drive some of the scan lines.

37. The driving method according to claim 36, characterized in that: The first signal is a clock signal.

38. The driving method according to claim 36, characterized in that: The second signal includes a fixed signal portion having a clock signal and a fixed signal portion having a second level, the fixed signal portion having the clock signal is input to some of the shift register units, and the fixed signal portion having the second level is input to the remaining shift register units.

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