Array substrate, display panel and display device

Abstract

An array substrate, a display panel and a display device. The array substrate comprises: a base (1); a plurality of gate line groups (2), wherein one gate line group (2) among the plurality of gate line groups (2) comprises two gate lines (20) extending in a first direction (X); a plurality of data lines (3); a plurality of pixel electrodes (4), wherein the plurality of pixel electrodes (4) comprise a first-type pixel electrode (41) and a second-type pixel electrode (42) which are located in each area formed by the gate line groups (2) intersecting the data lines (3) and are connected to the same data line (3), the second-type pixel electrode (42) being located on the side of the first-type pixel electrode (41) that is away from the connected data line (3); and a plurality of transistors (T), wherein each transistor (T) connected to the first-type pixel electrode (41) further comprises a fourth portion (324) extending from a third portion (323) in the first direction (X) towards the side of the data line (3) connected to the first-type pixel electrode (41).

Description

Array substrate, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] Thin Film Transistor-Liquid Crystal Display (TFT-LCD) has a variety of commonly used display modes, such as twisted nematic (TN), vertically aligned (VA), fringe field switching (FFS), and in-plane switching (IPS). VA offers better dark state performance and contrast compared to other display modes.

[0003] Summary of the Invention

[0004] An embodiment of the present disclosure provides an array substrate, comprising:

[0005] substrate;

[0006] A plurality of gate line groups are located on one side of the substrate and extend along a first direction, wherein one gate line group among the plurality of gate line groups includes: two gate lines extending along the first direction;

[0007] a plurality of data lines, located on the same side of the substrate as the gate line group and extending along a second direction;

[0008] a plurality of pixel electrodes located on the same side of the substrate as the gate line group, the plurality of pixel electrodes comprising: a first type of pixel electrode located in an area formed by the intersection of the gate line group and the data line and connected to the same data line, and a second type of pixel electrode, the second type of pixel electrode being located on a side of the first type of pixel electrode away from the connected data line;

[0009] a plurality of transistors located on the same side of the substrate as the gate line group, wherein one of the plurality of transistors comprises: a gate electrically connected to the gate line, a first electrode electrically connected to the data line, and a second electrode electrically connected to the pixel electrode; the second electrode comprises: a first portion and a second portion extending along the second direction, and a third portion extending along the first direction and connecting an end of the first portion toward the pixel electrode and an end of the second portion toward the gate line;

[0010] The transistor connected to the first type pixel electrode further includes a fourth portion extending from the third portion along the first direction toward the data line connected to the first type pixel electrode.

[0011] In a possible implementation, a length of the third portion of the transistor connected to the second-type pixel electrode in the first direction is greater than a length of the third portion of the transistor connected to the first-type pixel electrode in the first direction.

[0012] In a possible implementation, the sum of the lengths of the third portion connected to the first type pixel electrode and the fourth portion in the first direction is greater than the length of the third portion connected to the second type pixel electrode in the first direction.

[0013] In a possible implementation manner, an orthographic projection of the fourth portion on the substrate is located within an orthographic projection of the first pixel electrode on the substrate.

[0014] In a possible implementation manner, a second notch is provided on the side of the gate line facing the second type pixel electrode and in the region where the transistor connected to the second type pixel electrode is located;

[0015] The second notch includes: a first notch portion and a second notch portion; the first notch portion is opposite to the gap between the first type pixel electrode and the second type pixel electrode, and the second notch portion is opposite to the second type pixel electrode.

[0016] In a possible implementation manner, a first notch is provided on the side of the gate line facing the first type pixel electrode and in a region where the transistor connected to the first type pixel electrode is located.

[0017] In a possible implementation manner, a length of the second notch in the first direction is greater than a length of the first notch in the first direction.

[0018] In a possible implementation manner, the first notch is directly opposite to only the first type of pixel electrode.

[0019] In a possible implementation, the first portion includes: a first sub-portion; and a second sub-portion extending from the first sub-portion along a side away from the third portion; an orthographic projection of the first sub-portion on the substrate overlaps with an orthographic projection of the gate on the substrate.

[0020] In a possible implementation, the first electrode includes: a fifth portion extending along the first direction, and a sixth portion extending along the second direction; one end of the fifth portion is electrically connected to the data line, and the other end is electrically connected to the sixth portion;

[0021] The sixth portion includes: a third sub-portion; and a fourth sub-portion extending from the third sub-portion along a side away from the fifth portion; an orthographic projection of the third sub-portion on the substrate overlaps with an orthographic projection of the gate on the substrate.

[0022] In a possible implementation manner, the orthographic projection of the fifth portion on the substrate is located within a gap between two gate lines in the same gate line group.

[0023] In a possible implementation manner, a minimum distance between the gate line and the pixel electrode in the second direction ranges from 6 μm to 10 μm.

[0024] In a possible implementation manner, the second electrode further includes: a connecting portion connected to an end portion of the second portion away from the third portion, wherein an orthographic projection of the connecting portion on the substrate is located within an orthographic projection of the pixel electrode on the substrate;

[0025] A first insulating layer is provided between the pixel electrode and the second electrode, and the connecting portion is electrically connected to the pixel electrode through a first via hole penetrating the first insulating layer.

[0026] In a possible implementation manner, the center of the connecting portion substantially coincides with the center of the pixel electrode.

[0027] In a possible implementation manner, a width of the connecting portion in the first direction is greater than a width of the second portion in the first direction.

[0028] In a possible embodiment, the array substrate further includes: a first common signal line located between adjacent gate line groups and extending along the first direction, and a common electrode portion connected to the first common signal line; the orthographic projection of the common electrode portion on the substrate covers the orthographic projection of the connecting portion on the substrate.

[0029] In one possible embodiment, the orthographic projection shape of the common electrode portion on the substrate is similar to the orthographic projection shape of the connecting portion on the substrate; and the orthographic projection center of the common electrode portion on the substrate coincides with the orthographic projection center of the connecting portion on the substrate.

[0030] In a possible implementation manner, a width of the common electrode portion in the second direction is greater than a width of the first common signal line in the second direction.

[0031] In a possible embodiment, the array substrate further includes: a second common signal line group located between adjacent gate line groups and extending along the second direction, the second common signal line group including two second common signal lines respectively located on different sides of the data line, and the second common signal line groups in the same extension direction are disconnected at the gate line group.

[0032] In a possible implementation manner, an orthographic projection of the second common signal line on the substrate at least partially overlaps with an orthographic projection of the pixel electrode on the substrate.

[0033] In a possible implementation, the array substrate further includes: a third common signal line located between adjacent gate line groups and extending along the second direction, wherein the third common signal line is located between the first type of pixel electrodes and the second type of pixel electrodes.

[0034] In a possible implementation manner, an orthographic projection of the third common signal line on the substrate partially overlaps with an orthographic projection of the pixel electrode on the substrate.

[0035] In a possible implementation manner, the second common signal line group and the third common signal line between adjacent gate line groups are electrically connected through the first common signal line.

[0036] In a possible implementation, at least some of the third common signal lines have overlapping ends at ends facing the gate line group, and a width of the overlapping ends in the first direction is greater than a width of the third common signal lines in the first direction except for the overlapping ends.

[0037] The array substrate further includes a lap portion at a different layer from the third common signal line, and the lap ends of the third common signal lines on both sides of the same gate line group are electrically connected via the lap portion.

[0038] In a possible implementation manner, the overlapping portion and the pixel electrode are made of the same layer and material.

[0039] In a possible implementation manner, the first common signal line, the second common signal line group, the third common signal line, and the gate line group are formed in the same layer and made of the same material.

[0040] The present disclosure also provides a display panel, which includes the array substrate provided in the present disclosure and an opposite substrate arranged opposite to the array substrate, wherein the opposite substrate is provided with a common electrode layer on a side facing the array substrate.

[0041] In a possible embodiment, a liquid crystal layer is provided on the surface of the array substrate facing the counter substrate. The liquid crystal layer has multiple liquid crystal regions in the area where the pixel electrode is located. The liquid crystal layers in different liquid crystal regions have different orientations in the initial state.

[0042] An embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 is a schematic diagram of the principle of the generation of head shake lines;

[0044] Figure 2 is a second schematic diagram of the principle of head shake pattern generation;

[0045] FIG3 is a schematic diagram of a head shake pattern;

[0046] FIG4A is a schematic diagram of an array substrate according to an embodiment of the present disclosure; ...

[0047] FIG4B is a schematic diagram of a single film layer of the gate line layer in FIG4A ;

[0048] FIG4C is a schematic diagram of a single film layer of the active layer in FIG4A ;

[0049] FIG4D is a schematic diagram of a single film layer of the data line layer in FIG4A ;

[0050] FIG4E is a schematic diagram of a single film layer of the pixel electrode layer in FIG4A ;

[0051] FIG4F1 is an enlarged schematic diagram of the dashed line frame Z in FIG4A ;

[0052] FIG4F2 may be another enlarged schematic diagram of the dashed box Z in FIG4A ;

[0053] FIG4G is a schematic cross-sectional view along the dotted line AA′ in FIG4A ;

[0054] FIG4H is a schematic cross-sectional view taken along dotted line BB′ in FIG4A ;

[0055] FIG4I is a schematic cross-sectional view taken along the dotted line CC′ in FIG4A ;

[0056] FIG4J is a schematic cross-sectional view along the dotted line DD′ in FIG4A ;

[0057] FIG5 is an equivalent circuit diagram provided by an embodiment of the present disclosure;

[0058] FIG6A is a second schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0059] FIG6B is a schematic diagram of a single film layer of the gate line layer in FIG6A;

[0060] FIG7 is a schematic diagram of liquid crystal orientation in different regions provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0062] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0063] As used herein, "about" or "approximately the same" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately the same" can mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0064] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shape that result from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0065] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0066] Dual gate design poses significant challenges to panel design and manufacturing, primarily: 1. The reduction in the number of dates and the increase in the number of gate lines make charging the panel more difficult; 2. The smaller the pixel area, the smaller the pixel storage capacitor Ccs, while the pixel's parasitic capacitance remains almost unchanged, making it susceptible to parasitic capacitance (for example, coupling capacitance Cgs (the capacitance between the gate and the pixel, where the pixel can be understood as the pixel electrode and other structures electrically connected to the pixel electrode)), resulting in head shake defects; and for VA products, the storage capacitance is further reduced compared to ADS products, making VA dual gate products even more susceptible to parasitic capacitance, resulting in head shake and other defects.

[0067] Specifically, in a dual-gate design, as shown in Figure 1, the signal applied to a long pixel has opposite polarity to the signal applied to its neighboring data lines (e.g., the first long pixel from left to right and the leftmost data line in Figure 1). When the data line (Data) signal coupled to the common electrode (COM) signal fluctuates, the long pixel appears brighter. The signal applied to a short pixel has the same polarity as the signal applied to its neighboring data lines (e.g., the first short pixel from left to right and the second data line from left to right in Figure 1). When the data line (Data) signal coupled to the common electrode (COM) signal fluctuates, the short pixel appears darker. Since half of the colors in space have the same polarity, averaging is not possible, requiring temporal averaging. However, when the head moves, several frames may be lost, further degrading the spatial averaging effect, as shown in Figure 2. When the head moves from side to side, rolling vertical streaks, known as head shakes, can be seen in the image, as shown in Figure 3.

[0068] In view of this, an embodiment of the present disclosure provides an array substrate, as shown in Figures 4A to 4H, wherein Figure 4B is a schematic diagram of a single film layer of the gate line layer in Figure 4A, Figure 4C is a schematic diagram of a single film layer of the active layer in Figure 4A, Figure 4D is a schematic diagram of a single film layer of the data line layer in Figure 4A, Figure 4E is a schematic diagram of a single film layer of the pixel electrode layer in Figure 4A, Figure 4F1 is an enlarged schematic diagram of the dotted line frame Z in Figure 4A, Figure 4F2 may be another enlarged schematic diagram of the dotted line frame Z in Figure 4A, Figure 4G is a schematic diagram of a cross-section along dotted line AA' in Figure 4A, Figure 4H is a schematic diagram of a cross-section along dotted line BB' in Figure 4A, Figure 4I is a schematic diagram of a cross-section along dotted line CC' in Figure 4A, and Figure 4J is a schematic diagram of a cross-section along dotted line DD' in Figure 4A. The array substrate includes:

[0069] Substrate 1;

[0070] A plurality of gate line groups 2 are located on one side of the substrate 1 and extend along a first direction X. One gate line group 2 among the plurality of gate line groups 2 includes: two gate lines 20 extending along the first direction X;

[0071] A plurality of data lines 3 are located on the same side of the substrate 1 as the gate line group 2 and extend along the second direction Y;

[0072] A plurality of pixel electrodes 4 are located on the same side of the substrate 1 as the gate line group 2, and the plurality of pixel electrodes 4 include: a first type pixel electrode 41 and a second type pixel electrode 42 located in an area formed by the intersection of the gate line group 2 and the data line 3 and connected to the same data line 3, and the second type pixel electrode 42 is located on a side of the first type pixel electrode 41 away from the connected data line 3; specifically, the first type pixel electrode 41 and the second type pixel electrode 42 connected to the data line 3 may be connected to the first type pixel electrode 41 via a transistor T, and the data line 3 may be connected to the second type pixel electrode 42 via a transistor. Optionally, the connection in the embodiment of the present disclosure may be a direct electrical connection or an indirect electrical connection, which is not limited herein;

[0073] A plurality of transistors T are located on the same side of the substrate 1 as the gate line group 2, wherein one transistor T among the plurality of transistors T includes: a gate 23 electrically connected to the gate line 20, a first electrode 31 electrically connected to the data line 3, a second electrode 32 electrically connected to the pixel electrode 4, and an active layer 5; the second electrode 32 includes: a first portion 321 and a second portion 322 extending along the second direction Y, and a third portion 323 extending along the first direction X and connecting an end of the first portion 321 facing the pixel electrode 4 and an end of the second portion 322 facing the gate line 20; specifically, an orthographic projection of the first portion 321 on the substrate 1 may have an overlapping area with an orthographic projection of the gate line 20 on the substrate 1; specifically, an orthographic projection of the second portion 322 on the substrate 1 may be located within an orthographic projection of the pixel electrode 4 on the substrate 1; specifically, the first portion 321 facing the end of the pixel electrode 4 may be the first portion 321 facing the end of the pixel electrode 4 or near the end; specifically, the second portion 322 facing the end of the gate line 20 may be the second portion 322 facing the end of the gate line 20 or near the end;

[0074] The transistor T connected to the first type pixel electrode 41 further includes a fourth portion 324 extending from the third portion 323 along the first direction X toward the data line 3 connected to the first type pixel electrode 41 .

[0075] In the embodiment of the present disclosure, the transistor T connected to the first-type pixel electrode 41 also includes a fourth part 324, while the transistor T connected to the second-type pixel electrode 42 does not have the fourth part, which can increase the lateral capacitance between the second electrode 32 connected to the first-type pixel electrode 41 and the gate line 20, thereby increasing the first capacitance C1 formed by the gate line 20 and the first-type pixel structure (the gate line 20 and the first-type pixel structure form a first capacitance C1, and the gate line 20 and the second-type pixel structure form a second capacitance C2, and the first capacitance C1 and the second capacitance C2 are approximately equal, wherein the first-type pixel structure may include: a first-type pixel electrode 41, and a second electrode 32 connected to the first-type pixel electrode 41; the second-type pixel structure may include: a second-type pixel electrode 42, and a second electrode 32 connected to the second-type pixel electrode 42), reducing the difference between the first capacitance C1 and the second capacitance C2, and improving the problem of bad shaking head wrinkles in the dual-gate structure display panel of the prior art.

[0076] It should be noted that, in the actual manufacturing process, it may be difficult to make the first capacitor C1 and the second capacitor C2 completely equal. Therefore, in the embodiment of the present invention, the difference between the first capacitor C1 and the second capacitor C2 can be within the range of 0F to 0.0001F, that is, the two are considered to be approximately equal. Specifically, for example, the difference between the two is within the range of 0F to 0.00007F; specifically, for example, the difference between the two is 0; specifically, for example, the difference between the two is 0.00007F; specifically, for example, the difference between the two is 0.000061F; specifically, the difference between the two is 0.000036F. Specifically, for the first capacitor C1 and the second capacitor C2 in the embodiment of the present invention, before manufacturing the array substrate, they can be obtained through software simulation.

[0077] Specifically, the transistor may further include an active layer 5. The first-type pixel structure may further include: the active layer 5 of the transistor T connected to the first-type pixel electrode 41; the second-type pixel structure may further include: the active layer 5 of the transistor T connected to the second-type pixel electrode 42. Specifically, the capacitance generated by the gate line 20 and the active layer 5 may exist only when the transistor is turned on. During the transistor-off period, it can be considered that the capacitance generated by the gate line 20 and the active layer 5 does not exist and does not affect the first capacitor C1 or the second capacitor C2. When the transistor is turned on, the active layer 5 of the transistor is electrically connected to the second electrode 32, and the second electrode 32 is electrically connected to the first type of pixel electrode 41. At this time, the first capacitor C1 may include the capacitance formed between the gate line 20 and the first type of pixel electrode 41, between the gate line 20 and the second electrode 32, and between the gate line 20 and the active layer 5; when the transistor T is turned on, the active layer 5 of the transistor T is electrically connected to the second electrode 32, and the second electrode 32 is electrically connected to the second type of pixel electrode 42. At this time, the second capacitor C2 includes the capacitance formed between the gate line 20 and the second type of pixel electrode 42, between the gate line 20 and the second electrode 32, and between the gate line 20 and the active layer 5.

[0078] Specifically, the material of the active layer 5 may be indium gallium zinc oxide (IGZO). The active layer 5 may also be amorphous silicon, low-temperature polysilicon, etc., which is not limited here.

[0079] In a possible embodiment, as shown in Figures 4A and 4D, the length a2 of the third portion 323 of the transistor T connected to the second-type pixel electrode 42 in the first direction X is greater than the length a1 of the third portion 323 of the transistor T connected to the first-type pixel electrode 41 in the first direction X.

[0080] In a possible embodiment, as shown in Figures 4A and 4D, the sum of the lengths a3 of the third portion 323 and the fourth portion 324 connected to the first type of pixel electrode 41 in the first direction X is greater than the length a2 of the third portion 323 connected to the second type of pixel electrode 42 in the first direction X.

[0081] In one possible implementation, as shown in FIG1 , the orthographic projection of the fourth portion 324 on the substrate 1 is located within the orthographic projection of the first pixel electrode 41 on the substrate 1. Specifically, the orthographic projection of the fourth portion 324 on the substrate 1 is located within the orthographic projection of the side region of the first pixel electrode 41 on the substrate 1. The side region is the region where the dark pattern is formed on the first pixel electrode 41. The fourth portion 324 added in the embodiment of the present disclosure does not cause any additional impact on the display panel.

[0082] Specifically, in the disclosed embodiment, a counter substrate opposite the array substrate may be provided with a black matrix. The black matrix may include: black matrix openings and shielding portions other than the black matrix openings. The third portion 323 and fourth portion 324 connected to the first type pixel electrode 41, and the third portion 323 connected to the second type pixel electrode 42 may all be located in the region where the shielding portions are located, thereby preventing other display issues. Specifically, the black matrix may be the counter substrate opposite the array substrate.

[0083] In one possible embodiment, referring to FIG4A and FIG4B , a second notch A2 is provided on the side of the gate line 20 facing the second type pixel electrode 42 and in the region where the transistor T connected to the second type pixel electrode 42 is located; the second notch A2 includes: a first notch portion A21 and a second notch portion A22; the first notch portion A21 is opposite to the gap between the first type pixel electrode 41 and the second type pixel electrode 42, and the second notch portion A22 is opposite to the second type pixel electrode 42. In the disclosed embodiment, by extending the second notch A2 to a position directly opposite the second type pixel electrode 42, that is, increasing the extension length of the second notch A2 in the first direction X, the lateral capacitance between the gate line 20 and the second type pixel electrode 42 can be reduced, thereby reducing the second capacitance C2 formed by the gate line 20 and the second type pixel structure, thereby reducing the difference between the first capacitance C1 and the second capacitance C2, and thus improving the problem of head shaking wrinkles in the dual-gate structure display panel of the prior art.

[0084] In one possible embodiment, as shown in Figures 4A and 4B , a first notch A1 is provided on the side of the gate line 20 facing the first-type pixel electrode 41, in a region where the transistor T connected to the first-type pixel electrode 41 is located. A length b3 of the second notch A2 in the first direction X is greater than a length b1 of the first notch A1 in the first direction X. In the disclosed embodiment, by making the length a2 of the second notch A2 in the first direction X greater than the length a1 of the first notch A1 in the first direction X, the lateral capacitance difference caused by the length of the third portion 323 of the transistor connected to the second-type pixel electrode 42 being greater than the length of the third portion 323 of the transistor connected to the first-type pixel electrode 41 in conventional array substrates can be further compensated.

[0085] In a possible implementation, referring to FIG. 4A and FIG. 4B , a length b3 of the second notch portion A22 in the first direction X is greater than a length b1 of the first notch b1 in the first direction X.

[0086] In a possible implementation, referring to FIG. 4A and FIG. 4B , the first notch A1 is only directly opposite to the first-type pixel electrode 41 .

[0087] In one possible embodiment, referring to Figures 4A and 4D , the first portion 321 includes: a first sub-portion 3211, and a second sub-portion 3212 extending from the first sub-portion 3211 along a side away from the third portion 323; the orthographic projection of the first sub-portion 3211 on the substrate 1 overlaps with the orthographic projection of the gate 23 on the substrate 1. In the embodiment of the present disclosure, the first portion 321 passes through the gate line 20 in the second direction Y, which is a full-hang design of the transistor T. Compared to the half-hang design in which the first portion 321 does not pass through the gate line 20 in the second direction Y, only partially overlaps with the gate line 20, and is partially located in the area on the side of the gate line 20 facing the second portion 322, the transistor T in the embodiment of the present disclosure can reduce the difference between the first capacitance C1 and the second capacitance C2 caused by process fluctuations.

[0088] In one possible embodiment, as shown in Figures 4A and 4D, the first electrode 31 includes: a fifth portion 311 extending along the first direction X, and a sixth portion 312 extending along the second direction Y; one end of the fifth portion 311 is electrically connected to the data line 3, and the other end is electrically connected to the sixth portion 312; the sixth portion 312 includes: a third sub-portion 3121, and a fourth sub-portion 3122 extending from the third sub-portion 3121 along a side away from the fifth portion 311; the orthographic projection of the third sub-portion 3121 on the substrate 1 overlaps with the orthographic projection of the gate 23 on the substrate 1. In the embodiment of the present disclosure, the sixth portion 312 passes through the gate line 20 in the second direction Y, which is a full-hang design of the transistor T. Compared with the half-hang design in which the sixth portion 312 does not pass through the gate line 20 in the second direction Y and only partially overlaps with the gate line 20, the transistor T in the embodiment of the present disclosure can reduce the difference between the first capacitance C1 and the second capacitance C2 caused by process fluctuations.

[0089] In one possible embodiment, as shown in FIG4A , the orthographic projection of the fifth portion 311 on the substrate 1 and the gap between two gate lines 20 in the same gate line group 2 are within the orthographic projection of the substrate 1. This prevents overlapping capacitance between the fifth portion 311 and the gate lines 20.

[0090] 4A and 4D , the width d5 ​​of the data line 3 in the first direction X at the position where the gate line 20 is set is greater than the width d2 of the data line 3 at the position relative to the second portion 322 , thereby preventing the data line 3 from being broken at the position of the gate line 20 .

[0091] In one possible embodiment, as shown in FIG4A , the minimum spacing c1 between the gate line 20 and the pixel electrode 4 in the second direction Y is in the range of 6 μm to 10 μm. Specifically, the minimum spacing between the gate line 20 and the pixel electrode 4 in the second direction Y is in the range of 6 μm, 7 μm, 8 μm, 9 μm or 10 μm. In the disclosed embodiment, the minimum spacing c1 between the gate line 20 and the pixel electrode 4 in the second direction Y is in the range of 6 μm to 10 μm, which can improve the problem of large differences in pixel voltage fluctuations between the first type pixel electrode 41 and the second type pixel electrode 42 due to the difference between the first capacitor C1 and the second capacitor C2.

[0092] In the traditional pixel design, the difference between the first capacitor C1 and the second capacitor C2 is relatively large. In order to reduce the difference between the first capacitor C1 and the second capacitor C2, in the embodiment of the present disclosure, the first capacitor C1 is compensated, that is, by setting the fourth part 324, the first capacitor C1 is increased. In addition, the second gap A2 is extended, and the distance from the gate line 20 to the pixel electrode 4 is increased to reduce the second capacitor C2. It can be obtained from the simulation results that the difference between the first capacitor C1 and the second capacitor C2 in the traditional design is 0.3. In the embodiment of the present disclosure, the difference between the first capacitor C1 and the second capacitor C2 is 0.0025, which greatly reduces the difference between the first capacitor C1 and the second capacitor C2.

[0093] In a possible embodiment, referring to Figures 4A, 4D and 4F1, specifically, Figure 4F1 may be an enlarged schematic diagram of the dotted box Z in Figure 4A, and Figure 4F2 may be another enlarged schematic diagram of the dotted box Z in Figure 4A, the second pole 32 also includes: a connecting portion 33 connected to the end of the second portion 322 away from the third portion 323, the orthographic projection of the connecting portion 33 on the substrate 1 is located within the orthographic projection of the pixel electrode 4 on the substrate 1; a first insulating layer is provided between the pixel electrode 4 and the second pole 32, and the connecting portion 33 is electrically connected to the pixel electrode 4 through a first via K penetrating the first insulating layer.

[0094] Specifically, the layer where the data line 3 is located can be located on the side of the gate line 20 layer away from the substrate 1, the layer where the pixel electrode 4 is located can be located on the side of the layer where the data line 3 is located away from the layer where the gate line 20 is located, the active layer 5 is located between the layer where the data line 3 is located and the layer where the gate line 20 is located, and a gate insulating layer can also be provided between the layer where the gate line 20 is located and the layer where the active layer 5 is located. A passivation layer can be provided between the layer where the data line 3 is located and the layer where the pixel electrode 4 is located, and a flat layer can also be provided between the passivation layer and the layer where the pixel electrode 4 is located; specifically, the first insulating layer may include: a passivation layer and a flat layer, optionally, the flat layer may be an organic film layer, optionally, the passivation layer may be a PVX layer, for example, including a silicon nitride material layer.

[0095] In a possible implementation, referring to FIG. 4A , FIG. 4D , and FIG. 4F1 , the center O1 of the connecting portion 33 substantially coincides with the center of the pixel electrode O2 .

[0096] In a possible implementation, referring to FIG. 4A , FIG. 4D , and FIG. 4F1 , a width h1 of the connecting portion 33 in the first direction X is greater than a width h2 of the second portion 322 in the first direction X.

[0097] In one possible embodiment, as shown in Figures 4A, 4B, and 4F1, the array substrate further includes: a first common signal line 24 located between adjacent gate line groups 2 and extending along a first direction X; and a common electrode portion 25 connected to the first common signal line 24; the first common signal line 24 passes through the center O2 of the pixel electrode 4; and the orthographic projection of the common electrode portion 25 on the substrate 1 overlaps the orthographic projection of the connecting portion 33 on the substrate 1. Thus, a first storage capacitor is formed by the common electrode portion 60 and the connecting portion 33.

[0098] In one possible embodiment, as shown in FIG4F2, the connection portion 33 may include a first connection portion 331 and a second connection portion 332 connected to the first connection portion 331, wherein the orthographic projection of the common electrode portion 25 on the substrate 1 overlaps the orthographic projection of the first connection portion 331 on the substrate 1, and the orthographic projection of the common electrode portion 25 on the substrate 1 does not overlap with the orthographic projection of the second connection portion 332 on the substrate 1. Compared to the structure shown in FIG4F2, the orthographic projection of the common electrode portion 25 on the substrate 1 as shown in FIG4F1 overlaps the orthographic projection of the connection portion 33 on the substrate 1, which can enable the array substrate to have a larger aperture ratio.

[0099] In a possible embodiment, referring to Figures 4A, 4B and 4F1, the orthographic projection shape of the common electrode portion 25 on the substrate 1 is similar to the orthographic projection shape of the connecting portion 33 on the substrate 1; and the orthographic projection center O3 of the common electrode portion 25 on the substrate 1 coincides with the orthographic projection center O1 of the connecting portion 33 on the substrate 1.

[0100] In a possible implementation, referring to FIG. 4A , FIG. 4B , and FIG. 4F1 , a width h3 of the common electrode portion 25 in the second direction Y is greater than a width h4 of the first common signal line 24 in the second direction Y.

[0101] In a possible embodiment, referring to FIG4F1, a spacing h5 in the second direction Y between an orthographic projection of a first common side edge 251 of the common electrode portion 25 (the first common side edge 251 may extend along the first direction X and be located on the side of the connecting portion 33 away from the second connecting portion 332) on the substrate 1 and an orthographic projection of a first via side edge K11 of the first via K (the first via side edge K11 may extend along the first direction X and be away from the side of the second connecting portion 332) on the substrate 1 may be greater than or equal to 3.5 μm and less than or equal to 7 μm, and optionally, for example, may be 3.5 μm, 4 μm, 4.5 μm, 5 μm, 6 μm, or 7 μm.

[0102] In a possible embodiment, referring to FIG4F1, the spacing h8 between the orthographic projection of the second common side edge 252 of the common electrode portion 25 (the second common side edge 252 may extend along the first direction X and be opposite to the first side edge 251) on the substrate 1 and the orthographic projection of the second via side edge K12 of the first via K (the second via side edge K12 may extend along the first direction X and be toward one side of the second connection portion 332) on the substrate 1 in the second direction Y may be approximately equal to h5. Specifically, h8 may be greater than or equal to 3.5 μm and less than or equal to 7 μm. Optionally, for example, it may be 3.5 μm, 4 μm, 4.5 μm, 5 μm, 6 μm, or 7 μm.

[0103] In a possible embodiment, referring to FIG4F1, a spacing h6 in the second direction Y between the orthographic projection of the third common side edge 253 of the common electrode portion 25 (the third common side edge 253 may extend along the second direction Y and be located on the same side of the connecting portion 33 as the third portion 323) on the substrate 1 and the orthographic projection of the third via side edge K13 of the first via K (the third via side edge K13 may extend along the second direction Y and be located on the same side of the connecting portion 33 as the third portion 323) on the substrate 1 is greater than or equal to 5 μm and less than or equal to 8 μm, and optionally, for example, may be 5 μm, 5.5 μm, 6 μm, 7 μm, 7.75 μm, or 8 μm.

[0104] In a possible embodiment, referring to FIG4F1, the spacing h7 between the orthographic projection of the fourth common side edge 254 of the common electrode portion 25 (the fourth common side edge 254 is an edge extending along the second direction Y and opposite to the third common side edge 253) on the substrate 1 and the orthographic projection of the fourth via side edge K14 of the first via K (the fourth via side edge K14 is a side edge extending along the second direction Y and opposite to the third via side edge K13) on the substrate 1 in the first direction X is greater than or equal to 1 μm and less than or equal to 3 μm, and optionally, for example, can be 1 μm, 1.75 μm, 2m or 3 μm.

[0105] In a possible implementation, as shown in FIG. 4F1 , a width h9 of the first via hole K in the first direction X is greater than or equal to 7 μm and less than or equal to 12 μm, and optionally, for example, may be 7 μm, 8 μm, 9.5 μm, or 12 μm.

[0106] In a possible implementation, as shown in FIG. 4F1 , the width h5 of the first via hole K in the second direction Y is greater than or equal to 4 μm and less than or equal to 7 μm, and optionally, for example, may be 4 μm, 5 μm, 6.5 μm, or 7 μm.

[0107] In a possible embodiment, referring to FIG4F2, a spacing h5 in the second direction Y between an orthographic projection of a first common side edge 251 of the common electrode portion 25 (the first common side edge 251 may extend along the first direction X and be located on the side of the connecting portion 33 away from the second connecting portion 332) on the substrate 1 and an orthographic projection of a first via side edge K11 of the first via K (the first via side edge K11 may extend along the first direction X and be away from the side of the second connecting portion 332) on the substrate 1 may be greater than or equal to 3.5 μm and less than or equal to 7 μm, and optionally, for example, may be 3.5 μm, 4 μm, 4.5 μm, 5 μm, 6 μm, or 7 μm.

[0108] In a possible embodiment, referring to FIG4F2, the spacing h8 between the orthographic projection of the second common side edge 252 of the common electrode portion 25 (the second common side edge 252 may extend along the first direction X and be opposite to the first side edge 251) on the substrate 1 and the orthographic projection of the second via side edge K12 of the first via K (the second via side edge K12 may extend along the first direction X and be toward one side of the second connection portion 332) on the substrate 1 in the second direction Y may be greater than or equal to 5 μm and less than or equal to 10 μm, and optionally, for example, may be 5 μm, 6.5 μm, 6.5 μm, 7 μm, 8.05 μm, or 10 μm.

[0109] In a possible embodiment, referring to FIG4F2 , a spacing h6 in the second direction Y between the orthographic projection of the third common side edge 253 of the common electrode portion 25 (the third common side edge 253 may extend along the second direction Y and be located on the same side of the connecting portion 33 as the third portion 323) on the substrate 1 and the orthographic projection of the third via side edge K13 of the first via K (the third via side edge K13 may extend along the second direction Y and be located on the same side of the connecting portion 33 as the third portion 323) on the substrate 1 is greater than or equal to 5 μm and less than or equal to 9 μm, and optionally, for example, may be 5 μm, 5.5 μm, 6 μm, 6.5 μm, 8.05 μm, or 9 μm.

[0110] In a possible embodiment, referring to FIG4F2 , a spacing h7 in the first direction X between an orthographic projection of the fourth common side edge 254 of the common electrode portion 25 (the fourth common side edge 254 is an edge extending along the second direction Y and opposite to the third common side edge 253 ) on the substrate 1 and an orthographic projection of the fourth via side edge K14 of the first via K (the fourth via side edge K14 is a side edge extending along the second direction Y and opposite to the third via side edge K13 ) on the substrate 1 is greater than or equal to 1 μm and less than or equal to 3 μm, and optionally, for example, can be 1 μm, 1.75 μm, 2m or 3 μm.

[0111] In a possible implementation, as shown in FIG. 4F2 , a width h9 of the first via hole K in the first direction X is greater than or equal to 6 μm and less than or equal to 8 μm, and optionally, for example, may be 6 μm, 7 μm, 7.5 μm, or 8 μm.

[0112] In a possible implementation, as shown in FIG. 4F2 , the width h5 of the first via hole K in the second direction Y is greater than or equal to 4 μm and less than or equal to 7 μm, and optionally, for example, may be 4 μm, 5 μm, 6.5 μm, or 7 μm.

[0113] In a possible embodiment, referring to FIG4A and FIG4B , the array substrate further includes: a second common signal line group located between adjacent gate line groups 2 and extending along the second direction Y, the second common signal line group including two second common signal lines 26 located on different sides of the data line 3, and the second common signal line group in the same extension direction is disconnected at the gate line group 2.

[0114] In one possible embodiment, as shown in Figures 4A and 4B , the orthographic projection of the second common signal line 26 on the substrate 1 at least partially overlaps with the orthographic projection of the pixel electrode 4 on the substrate 1. In this way, a second storage capacitor is formed by the second common signal line 26 and the pixel electrode 4.

[0115] In a possible implementation, referring to FIG. 4A and FIG. 4B , a width d1 of the second common signal line 26 in the first direction X is substantially equal to a width d2 of the data line 3 in the first direction X.

[0116] In a possible embodiment, referring to FIG. 4A and FIG. 4B , the array substrate further includes: a third common signal line 27 located between adjacent gate line groups 2 and extending along the second direction Y, and the third common signal line 27 is located between the first type pixel electrode 41 and the second type pixel electrode 42 .

[0117] 4A and 4B , the orthographic projection of the third common signal line 27 on the substrate 1 partially overlaps with the orthographic projection of the pixel electrode 4 on the substrate 1. Thus, a third storage capacitor is formed by the third common signal line 27 and the pixel electrode 4.

[0118] Specifically, as shown in Figure 5, the first storage capacitor, the second storage capacitor and the third storage capacitor can form a storage capacitor Ccs, and the drain of the transistor T (that is, the second electrode 32) and the structure electrically connected to the drain (such as the pixel electrode 4, the active layer 5) and the gate line 20 can form a coupling capacitor Cgs, corresponding to the first capacitor C1 or the second capacitor C2 in the embodiment of the present disclosure, and Clc can be the capacitance generated by the liquid crystal between the array substrate and the opposite substrate.

[0119] In a possible embodiment, referring to Figures 4A, 4B and 4D, the width d3 of the third common signal line 27 in the first direction X may be 10 μm to 15 μm; specifically, for example, it may be 10 μm, 11 μm, 12 μm, 13 μm, 14 μm or 15 μm; the width d2 of the data line 3 in the first direction X may be 5 μm to 15 μm, specifically, for example, it may be 5 μm, 6 μm, 7 μm, 8 μm, 10 μm or 15 μm.

[0120] In a possible implementation, referring to FIG. 4A and FIG. 4B , the second common signal line group and the third common signal line 27 between adjacent gate line groups 2 are electrically connected via the first common signal line 24 .

[0121] In a possible embodiment, referring to Figures 4A and 4B, at least part of the third common signal lines 27 have a overlapping end 28 at one end facing the gate line group 2, and the width d4 of the overlapping end 28 in the first direction X is greater than the width d3 of the third common signal line 27 in the first direction X excluding the overlapping end 28; the array substrate also includes: a overlapping portion 43 on a different layer from the third common signal line 27, and the overlapping ends 28 of the third common signal lines 27 on both sides of the same gate line group are electrically connected through the overlapping portion 43.

[0122] Specifically, refer to Figure 4J, wherein Figure 4J can be a cross-sectional schematic diagram at the dotted line DD' in Figure 4A, and the overlapping end 28 and the overlapping portion 43 can be conductively connected through a half-hanging hole. Specifically, there can be a second insulating layer between the layer where the overlapping end 28 is located and the layer where the overlapping portion 43 is located, and the second insulating layer can have a second via K2. The second via K2 partially exposes the overlapping end 28 and partially exposes the substrate 1. The overlapping portion 43 is partially in contact with the overlapping end 28 at the via K2 and partially in contact with the substrate 1, thereby realizing electrical connection between the overlapping end 28 and the overlapping portion 43 at one overlapping end 28, and the two overlapping ends 28 on both sides of the gate line group 2 are electrically connected through the integrated overlapping portion 43. In the embodiment of the present disclosure, the overlapping end 28 and the overlapping portion 43 are conductively connected through a half-hanging hole so that the second via K2 forms a step structure inside, which has a drainage effect on the alignment liquid, prevents the alignment liquid from not sticking, and improves the uniformity of the array substrate of the alignment liquid, avoids the technical effect of the moiré phenomenon on the screen, and improves the display quality.

[0123] Specifically, the second insulating layer may include: a gate insulating layer 11 , a passivation layer 12 , and a planarization layer 13 .

[0124] In one possible implementation, referring to Figures 6A and 6B , the array substrate further includes a fourth common signal line 29 connected to one side of the first common signal line 24. Specifically, the orthographic projection of the fourth common signal line 29 on the substrate 1 is located on the other side of the first common signal line 24 opposite the second electrode 32. Specifically, the length of the fourth common signal line 29 in the second direction Y may be substantially equal to the length of the second portion 322 of the second electrode 32 in the second direction Y.

[0125] In a possible embodiment, as shown in FIG4A and FIG4E , the overlapping portion 43 is made of the same layer and material as the pixel electrode 4. This simplifies the manufacturing process of the array substrate and reduces the manufacturing cost of the array substrate.

[0126] 4A and 4B , the first common signal line 24, the second common signal line group 26, and the third common signal line 27 are made of the same layer and material as the gate line group 2. This simplifies the manufacturing process of the array substrate and reduces the manufacturing cost of the array substrate.

[0127] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes an array substrate as provided in the embodiment of the present disclosure, and also includes an opposite substrate arranged opposite to the array substrate, and the opposite substrate is provided with a common electrode layer on the side facing the array substrate.

[0128] In one possible embodiment, a liquid crystal layer may be disposed between the array substrate and the counter substrate. The liquid crystal layer has multiple liquid crystal regions in the region where the pixel electrode 4 is located, and the liquid crystal layer in different regions has different orientations in the initial state. Specifically, as shown in FIG7 , for example, the liquid crystal layer has four liquid crystal regions in the region where the pixel electrode 4 is located. The orthographic projections of the four liquid crystal regions on the substrate 1 may be located in a first region and a second region on one side of the orthographic projection of the first common signal line 24 on the substrate 1, and a third region and a fourth region on the other side of the orthographic projection of the first common signal line 24. The first and third regions may be located on one side of the orthographic projection of the second portion 322 on the substrate 1, and the second and fourth regions may be located on the other side of the orthographic projection of the second portion 322 on the substrate 1. Specifically, the array substrate may have a first alignment film layer 81, and the counter substrate may have a second alignment film layer 82. The orientations of the first and second alignment film layers 81, 82 in different regions may be as shown in FIG7 , and the orientation of the first alignment film layer 81 may be perpendicular to the orientation of the second alignment film layer 82.

[0129] Specifically, the initial state of the liquid crystal layer in different liquid crystal regions can be understood as the deflection state of the liquid crystal layer in different liquid crystal regions when no electric field is applied, that is, the state when no voltage is formed between the pixel electrode 4 and the common electrode.

[0130] Specifically, in combination with Figures 4G-4I, the opposing substrate 6 may also include a black matrix layer 7 and a color filter layer (not shown in the figure), as well as a common electrode layer on the side of the color filter layer away from the substrate 1. Optionally, the common electrode layer of the opposing substrate 6 and the common signal line set on the array substrate transmit the same common signal.

[0131] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display panel provided by the embodiment of the present disclosure.

[0132] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0133] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate, wherein: include: substrate; A plurality of gate line groups are located at one side of the substrate and extend along a first direction, wherein one gate line group among the plurality of gate line groups comprises: two gate lines extending along the first direction; a plurality of data lines, located on the same side of the substrate as the gate line group, extending along a second direction; A plurality of pixel electrodes are located on the same side of the substrate as the gate line group, the plurality of pixel electrodes comprising: a first type of pixel electrode located in a region formed by the intersection of the gate line group and the data line and connected to the same data line, and a second type of pixel electrode, the second type of pixel electrode being located on a side of the first type of pixel electrode away from the connected data line; A plurality of transistors are located on the same side of the substrate as the gate line group, wherein one transistor among the plurality of transistors comprises: a gate electrically connected to the gate line, a first electrode electrically connected to the data line, and a second electrode electrically connected to the pixel electrode; the second electrode comprises: a first portion and a second portion extending along the second direction, and a third portion extending along the first direction and connecting an end of the first portion toward the pixel electrode and an end of the second portion toward the gate line; The transistor connected to the first type pixel electrode further includes: a fourth portion extending from the third portion along the first direction toward a side of the data line connected to the first type pixel electrode.

2. The array substrate according to claim 1, wherein: A length of the third portion of the transistor connected to the second-type pixel electrode in the first direction is greater than a length of the third portion of the transistor connected to the first-type pixel electrode in the first direction.

3. The array substrate according to claim 2, wherein: The sum of the lengths of the third portion connected to the first-type pixel electrode and the fourth portion in the first direction is greater than the length of the third portion connected to the second-type pixel electrode in the first direction.

4. The array substrate according to any one of claims 1 to 3, wherein: The orthographic projection of the fourth portion on the substrate is located within the orthographic projection of the first pixel electrode on the substrate.

5. The array substrate according to any one of claims 1 to 4, wherein: The gate line is provided with a second notch on a side facing the second type pixel electrode and in a region where the transistor connected to the second type pixel electrode is located; The second notch includes: a first notch portion and a second notch portion; the first notch portion is opposite to the gap between the first type pixel electrode and the second type pixel electrode, and the second notch portion is opposite to the second type pixel electrode.

6. The array substrate according to claim 5, wherein: The gate line is provided with a first notch on a side facing the first type pixel electrode and in a region where the transistor connected to the first type pixel electrode is located.

7. The array substrate according to claim 6, wherein: A length of the second notch in the first direction is greater than a length of the first notch in the first direction.

8. The array substrate according to claim 6, wherein: The first notch is directly opposite to the first type of pixel electrode only.

9. The array substrate according to any one of claims 1 to 8, wherein: The first portion includes: a first sub-portion, and a second sub-portion extending from the first sub-portion along a side away from the third portion; an orthographic projection of the first sub-portion on the substrate overlaps with an orthographic projection of the gate on the substrate.

10. The array substrate according to claim 9, wherein: The first electrode includes: a fifth portion extending along the first direction, and a sixth portion extending along the second direction; one end of the fifth portion is electrically connected to the data line, and the other end is electrically connected to the sixth portion; The sixth portion includes: a third sub-portion, and a fourth sub-portion extending from the third sub-portion along a side away from the fifth portion; an orthographic projection of the third sub-portion on the substrate overlaps with an orthographic projection of the gate on the substrate.

11. The array substrate according to claim 10, wherein: The orthographic projection of the fifth portion on the substrate is within the orthographic projection of the substrate and a gap between two gate lines in the same gate line group.

12. The array substrate according to any one of claims 1 to 11, wherein: The minimum spacing between the gate line and the pixel electrode in the second direction ranges from 6 μm to 10 μm.

13. The array substrate according to any one of claims 1 to 12, wherein: The second electrode further includes: a connecting portion connected to an end of the second portion away from the third portion, wherein an orthographic projection of the connecting portion on the substrate is located within an orthographic projection of the pixel electrode on the substrate; A first insulating layer is provided between the pixel electrode and the second electrode, and the connecting portion is electrically connected to the pixel electrode through a first via hole penetrating the first insulating layer.

14. The array substrate according to claim 13, wherein: The center of the connecting portion substantially coincides with the center of the pixel electrode.

15. The array substrate according to claim 13, wherein: A width of the connecting portion in the first direction is greater than a width of the second portion in the first direction.

16. The array substrate according to any one of claims 13 to 15, wherein: The array substrate further includes: a first common signal line located between adjacent gate line groups and extending along the first direction, and a common electrode portion connected to the first common signal line; the orthographic projection of the common electrode portion on the substrate covers the orthographic projection of the connecting portion on the substrate.

17. The array substrate according to claim 16, wherein: The orthographic projection shape of the common electrode portion on the substrate is similar to the orthographic projection shape of the connecting portion on the substrate; and the orthographic projection center of the common electrode portion on the substrate coincides with the orthographic projection center of the connecting portion on the substrate.

18. The array substrate according to claim 16, wherein: A width of the common electrode portion in the second direction is greater than a width of the first common signal line in the second direction.

19. The array substrate according to any one of claims 15 to 18, wherein: The array substrate also includes: a second common signal line group located between adjacent gate line groups and extending along the second direction, the second common signal line group includes two second common signal lines located on different sides of the data line, and the second common signal line group in the same extension direction is disconnected at the gate line group.

20. The array substrate according to claim 19, wherein: The orthographic projection of the second common signal line on the substrate at least partially overlaps with the orthographic projection of the pixel electrode on the substrate.

21. The array substrate according to any one of claims 16 to 20, wherein: The array substrate further includes: a third common signal line located between adjacent gate line groups and extending along the second direction, wherein the third common signal line is located between the first type pixel electrode and the second type pixel electrode.

22. The array substrate according to claim 21, wherein: The orthographic projection of the third common signal line on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate.

23. The array substrate according to claim 21 or 22, wherein: The second common signal line group and the third common signal line between adjacent gate line groups are electrically connected through the first common signal line.

24. The array substrate according to claim 23, wherein: At least one end of a portion of the third common signal lines facing the gate line group has a lapped end, and a width of the lapped end in the first direction is greater than a width of the third common signal line except the lapped end in the first direction; The array substrate further includes: a lap portion at a different layer from the third common signal line, and the lap ends of the third common signal lines at two sides of the same gate line group are electrically connected via the lap portion.

25. The array substrate according to claim 24, wherein: The overlapping portion and the pixel electrode are in the same layer and made of the same material.

26. The array substrate according to any one of claims 16 to 25, wherein: The first common signal line, the second common signal line group, the third common signal line and the gate line group are formed in the same layer and made of the same material.

27. A display panel, wherein: It comprises the array substrate as claimed in any one of claims 1 to 26, and further comprises an opposite substrate arranged opposite to the array substrate, wherein the opposite substrate is provided with a common electrode layer on a side facing the array substrate.

28. The display panel according to claim 27, wherein: The array substrate is provided with a liquid crystal layer on a surface facing the counter substrate. The liquid crystal layer has a plurality of liquid crystal regions in the region where the pixel electrode is located. The liquid crystal layers in different liquid crystal regions have different orientations in an initial state.

29. A display device, wherein: Comprising the display panel as claimed in claim 27 or 28.

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