Display panel and display device

Abstract

A display panel and a display device. In the display panel, a first isolation structure (601) is located between adjacent sub-pixels of a plurality of sub-pixels (SP), the first isolation structure (601) being configured to partition at least one of a plurality of film layers of a light-emitting functional layer (FL); the first isolation structure (601) comprises a first isolation portion (PT1) and a second isolation portion (PT2), the first isolation portion (PT1) being located in a first organic insulating layer (Y1), and the second isolation portion (PT2) being located in an inorganic insulating layer (Y0); the inorganic insulating layer has a plurality of through holes (H0) located in a peripheral area (R2); a second organic insulating layer (Y2) is in contact with the first organic insulating layer (Y1) via the plurality of through holes (H0). Therefore, the risk of easy stripping caused by the contact between the inorganic insulating layer and the organic insulating layers is avoided, and the contact reliability is improved, which facilitates the air removal of the organic insulating layer below the inorganic insulating layer, and improves the process reliability.

Description

Display panel and display device Technical Field

[0001] Embodiments of the present disclosure relate to a display panel and a display device. Background Art

[0002] Organic light-emitting diode (OLED) display products have advantages such as rich colors, fast response time, and foldability. OLED is gradually replacing liquid crystal display (LCD) to become the mainstream small and medium-sized display products.

[0003] Summary of the Invention

[0004] Embodiments of the present disclosure provide a display panel and a display device.

[0005] The embodiment of the present disclosure provides a display panel, comprising: a base substrate, comprising a display area and a peripheral area located on at least one side of the display area; a first organic insulating layer located in the display area and the peripheral area; a plurality of sub-pixels, comprising a plurality of light-emitting elements, wherein the plurality of light-emitting elements are located in the display area and on a side of the first organic insulating layer away from the base substrate, the plurality of light-emitting elements comprising an electrode pattern layer, a common electrode, and a light-emitting functional layer located between the electrode pattern layer and the common electrode, the electrode pattern layer comprising a plurality of independent pixel electrodes, the light-emitting functional layer comprising a plurality of film layers, the electrode pattern layer being closer to the base substrate than the common electrode; an inorganic insulating layer located in the display area; The display area and the peripheral area are located on the side of the first organic insulating layer away from the base substrate; the second organic insulating layer is located on the side of the inorganic insulating layer away from the base substrate; and a first isolation structure is located between adjacent sub-pixels of the multiple sub-pixels, and the first isolation structure is configured to isolate at least one of the multiple film layers of the light-emitting functional layer; the first isolation structure includes a first isolation portion and a second isolation portion, the first isolation portion is located in the first organic insulating layer, and the second isolation portion is located in the inorganic insulating layer, the inorganic insulating layer has a plurality of through holes located in the peripheral area, and the second organic insulating layer is in contact with the first organic insulating layer through the multiple through holes.

[0006] For example, the second organic insulating layer covers the plurality of through holes.

[0007] For example, the plurality of through holes are formed in a plurality of rows and columns.

[0008] For example, the plurality of through holes include at least two through holes that are staggered in a first direction and a second direction, wherein the first direction and the second direction are perpendicular to each other and are parallel to the base substrate.

[0009] For example, the second isolating portion protrudes from the first isolating portion at an edge to form a first protruding portion, and at least one film layer of the plurality of film layers of the light-emitting functional layer is disconnected at the first protruding portion.

[0010] For example, the base substrate also includes a first non-display area, which is a non-luminous area, and a second non-display area is provided between the first non-display area and the display area. The display panel also includes a second isolation structure located in the second non-display area, and the second isolation structure is configured to isolate at least one of the multiple film layers and is configured to isolate the common electrode. The second isolation structure includes a third isolation portion and a fourth isolation portion, the third isolation portion is located in the first organic insulating layer, and the fourth isolation portion is located in the inorganic insulating layer.

[0011] For example, the first organic insulating layer has a first removed portion at the first isolation structure, and the first organic insulating layer has a second removed portion at the second isolation structure.

[0012] For example, the maximum depth of the first removed portion is smaller than the maximum depth of the second removed portion.

[0013] For example, a maximum dimension of the first removed portion in a direction perpendicular to the base substrate is smaller than a maximum dimension of the second removed portion in a direction perpendicular to the base substrate.

[0014] For example, the fourth isolating portion protrudes from the third isolating portion at an edge to form a second protruding portion, and at least one of the plurality of film layers of the light-emitting functional layer and the common electrode are disconnected at the second protruding portion.

[0015] For example, the first isolation structure constitutes a half T-shaped structure, the second isolation structure constitutes a half T-shaped structure, and the size of the second isolation structure in the direction perpendicular to the substrate is larger than the size of the first isolation structure in the direction perpendicular to the substrate.

[0016] For example, the display panel further includes a third isolation structure, the third isolation structure is located in the second non-display area, and the third isolation structure is closer to the first non-display area than the second isolation structure.

[0017] For example, the material of the third isolation structure is different from the material of the second isolation structure.

[0018] For example, the third isolation structure is made of a conductive material.

[0019] For example, the distance between the third isolation structure and the base substrate is smaller than the distance between the second isolation structure and the base substrate.

[0020] For example, the third isolation structure is in an I-shape, and the material of the third isolation structure includes metal.

[0021] For example, the display panel further includes a conductive line, the conductive line is located in the second non-display area, and the orthographic projection of the inorganic insulating layer on the base substrate overlaps with the orthographic projection of the conductive line on the base substrate.

[0022] For example, the second organic insulating layer is located on a side of the electrode pattern layer facing away from the base substrate, and the second organic insulating layer includes a plurality of openings configured to expose the plurality of pixel electrodes.

[0023] For example, the second organic insulating layer is located on a side of the electrode pattern layer close to the base substrate, and the second organic insulating layer has a via hole so that the pixel electrode is connected to the pixel circuit through the via hole.

[0024] An embodiment of the present disclosure further provides a display device, comprising any of the above-mentioned display panels. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0026] FIG1 is a schematic diagram of a light-emitting element.

[0027] FIG2 is a cross-sectional view of a display panel.

[0028] 3A and 3B are cross-sectional views of a display panel provided by an embodiment of the present disclosure.

[0029] FIG4 is a plan view of a display panel provided by an embodiment of the present disclosure.

[0030] 5 to 7 are cross-sectional views of a partial structure of a display panel provided by an embodiment of the present disclosure.

[0031] 8 to 10 are plan views of a partial structure of a display panel provided by an embodiment of the present disclosure.

[0032] FIG11 is a schematic diagram of a display panel provided by an embodiment of the present disclosure.

[0033] 12 to 18 are flow charts of a process for manufacturing a second isolation structure and a third isolation structure in a display panel provided by an embodiment of the present disclosure.

[0034] 19 to 21 are flow charts of a process for manufacturing a first isolation structure in a display area of ​​a display panel provided by an embodiment of the present disclosure.

[0035] FIG22 is a schematic diagram of a display panel provided by an embodiment of the present disclosure, wherein the display area is protected when a second isolation structure is formed.

[0036] FIG23 is a cross-sectional view of a display panel provided by an embodiment of the present disclosure.

[0037] FIG24 is a plan view of a display panel provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0039] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0040] With the continuous development of display technology, people's pursuit of display quality is getting higher and higher. In order to further reduce power consumption, extend service life and achieve high brightness, one of the light-emitting layers in the light-emitting element of the OLED display panel can be replaced with two light-emitting layers, and a charge generation layer (CGL) is added between the two light-emitting layers. The N-type doped charge generation layer and the P-type doped charge generation layer (N / P-CGL) are used as heterojunctions, and the two light-emitting device structures are connected in series to form a double-stacked design to form a Tandem structure. The display panel with the Tandem structure realizes the series connection of dual light-emitting devices. Under the same luminous intensity, the luminous current of the light-emitting element is greatly reduced, and the life of the light-emitting element is improved, which is conducive to the development and mass production of new technologies with high lifespan, such as automotive. The display device with the Tandem structure has the advantages of long life, low power consumption and high brightness.

[0041] Figure 1 is a schematic diagram of a light-emitting element. Figure 1(a) is a schematic diagram of a conventional light-emitting element. Figure 1(b) is a schematic diagram of a light-emitting element with a tandem structure. As shown in Figure 1(b), the charge generation layers (CGLs) of different light-emitting elements in the tandem structure are connected.

[0042] Figure 1 shows a pixel electrode E1, a common electrode E2, a hole transport layer HTL, an electron transport layer ETL, a light coupling layer CPL, an antireflection layer ARL, a P-type doped charge generation layer P-CGL, an N-type doped charge generation layer N-CGL, a light-emitting layer R, a light-emitting layer G, and a light-emitting layer B. As shown in Figure 1(b), the hole transport layer HTL includes a hole transport layer HTL-1 and a hole transport layer HTL-2. As shown in Figure 1(b), the electron transport layer ETL includes an electron transport layer ETL-1 and an electron transport layer ETL-2.

[0043] For example, as shown in Figure 1, light-emitting layer R includes two sublayers containing light-emitting material r and light-emitting material r2, respectively; light-emitting layer G includes two sublayers containing light-emitting material g1 and light-emitting material g2, respectively; and light-emitting layer B includes light-emitting material b1 and light-emitting material b2. For example, light-emitting material r1 and light-emitting material r2 are two different materials that emit red light, light-emitting material g1 and light-emitting material g2 are two different materials that emit green light, and light-emitting material b1 and light-emitting material b2 are two different materials that emit blue light. In other embodiments, light-emitting layer B may include two sublayers containing light-emitting material b1 and light-emitting material b2, respectively.

[0044] Figure 1 shows a light-emitting functional layer FL located between pixel electrode E1 and common electrode E2. The light-emitting functional layer FL includes a common layer CL and a local layer LL. The local layer LL includes a light-emitting layer R, a light-emitting layer G, and a light-emitting layer B. The common layer CL includes a first common layer CL1, a second common layer CL2, and a third common layer CL3. As shown in Figure 1, the first common layer CL1 includes a hole transport layer HTL-1, the second common layer CL2 includes an electron transport layer ETL-1, a charge generation layer N-CGL, a charge generation layer P-CGL, and a hole transport layer HTL-2. The third common layer CL3 includes an electron transport layer ETL-2.

[0045] For example, the common layer CL may be manufactured using an open mask, and the local layer LL may be manufactured using a fine metal mask, but the present invention is not limited thereto.

[0046] For example, the common layer CL includes at least a charge generation layer, but is not limited thereto.

[0047] It should be noted that the light-emitting element of the Tandem structure is not limited to that shown in FIG. 1 and can be configured as required.

[0048] Fig. 2 is a cross-sectional view of a display panel. As shown in Fig. 2 , the display panel includes a plurality of sub-pixels SP. Fig. 2 shows a sub-pixel SP1 and a pixel SP2.

[0049] For clarity of illustration, FIG2 does not show all sub-pixels SP, but only shows a few sub-pixels SP.

[0050] The inventors noted that for high-resolution products, the common layer CL, such as the charge generation layer, is shared by multiple sub-pixels. Since the charge generation layer is doped and conductive, and the charge generation layers in the light-emitting functional layers of adjacent sub-pixels are connected, the conductive layers in the common layer CL, such as the charge generation layer, are prone to cause crosstalk between adjacent sub-pixels, affecting the product image quality and thus seriously affecting the display quality.

[0051] For example, crosstalk between adjacent sub-pixels occurs when a sub-pixel that should not emit light emits light. As shown in Figure 2, if the intended situation is for sub-pixel SP1 to emit light while sub-pixel SP2 does not, the conductivity of the charge generation layer causes sub-pixel SP2 to also emit light, resulting in lateral light leakage and crosstalk.

[0052] In order to avoid lateral light leakage, structures such as isolation columns can be provided to alleviate or avoid lateral light leakage and improve image quality, especially low grayscale image quality.

[0053] 3A and 3B are cross-sectional views of a display panel provided by an embodiment of the present disclosure. As shown in FIG2 to FIG3B , the display panel includes a base substrate BS, which includes a display area R1 and a peripheral area R2 located on at least one side of the display area R1. For example, the peripheral area R2 surrounds the display area R1. The peripheral area R2 is a non-display area, and the peripheral area R2 can be a wiring area. The display area R1 displays images. As shown in FIG2 to FIG3B , the base substrate BS also includes a first non-display area R3, which is a non-luminous area (non-display area), and a second non-display area R0 is provided between the first non-display area R3 and the display area R1. For example, the second non-display area R0 is a wiring area, which is a non-luminous area (non-display area).

[0054] As shown in Figure 2, the first non-display area R3 is circular. It should be noted that the embodiments of the present disclosure are described using the circular shape of the first non-display area R3 as an example, but the first non-display area R3 can also adopt other suitable shapes, not limited to a circle. Furthermore, the location of the first non-display area R3 is not limited to that shown in the figure and can be set as needed. For example, some gate lines, some data lines, and other conductive wires are wrapped around the first non-display area R3 to form a second non-display area R0. The second non-display area R0 can be a wiring area.

[0055] For example, when using an in-screen hole solution, at least part of the structure within the first non-display area R3 is removed. That is, the in-screen hole solution requires sacrificing part of the display area to form the first non-display area. For example, all structures within the first non-display area R3 of the display panel are removed. For example, after forming the encapsulation layer, a hole is excavated to remove the portion of the display panel located in the first non-display area R3. The sensor can be partially or entirely disposed within the first non-display area R3. For example, the sensor includes, but is not limited to, a camera.

[0056] In the embodiments of the present disclosure, the first non-display area R3 does not have either pixel circuits or light-emitting elements. The embodiments of the present disclosure are described using an example in which all structures within the first non-display area R3 are removed to form a through-hole. However, in other embodiments, a portion of the structure of the first non-display area R3 is removed to form a recess. In other words, at least a portion of the structure within the first non-display area R3 is removed to form a storage space for accommodating components such as sensors.

[0057] On the one hand, in order to prevent water and oxygen from invading the light-emitting elements, an isolation structure can be set in the second non-display area R0 to isolate the light-emitting functional layer of the light-emitting element and prevent water and oxygen from entering the display area R1 along the light-emitting functional layer around the first non-display area R3.

[0058] On the other hand, in order to reduce or avoid the crosstalk problem caused by the sub-functional layer with strong conductivity in the light-emitting functional layer, an isolation structure may be provided in the display area.

[0059] Figures 3A and 3B are cross-sectional views of a display panel according to an embodiment of the present disclosure. Figure 4 is a plan view of a display panel according to an embodiment of the present disclosure. Figure 3A omits the light-emitting functional layer FL and the common electrode E2.

[0060] As shown in Figures 3A and 3B, a first isolation structure 601 is provided (at the dotted box F1). By providing a passivation layer PVX2 on the planarization layer PLN3, the planarization layer PLN3 is provided with a first removed portion GRV1 (groove or through hole) at the location where the passivation layer PVX2 is provided, thereby forming a first isolation structure 601 that can be used to isolate the common layer in the light-emitting functional layer, thereby alleviating or avoiding lateral light leakage and improving image quality.

[0061] The remaining structures in FIG. 3A and FIG. 3B will be described later.

[0062] Figure 4 shows sub-pixel SP1, sub-pixel SP2, and sub-pixel SP3. For example, two sub-pixels SP1, one sub-pixel SP2, and one sub-pixel SP3 constitute a repeating unit PX. As shown in Figures 3B and 4, the sub-pixel SP includes a light-emitting element 200. As shown in Figure 4, sub-pixel SP1 includes a light-emitting element 201, sub-pixel SP2 includes a light-emitting element 202, and sub-pixel SP3 includes a light-emitting element 203. Figure 4 shows the sub-pixel with the light-emitting area of ​​the light-emitting element of the sub-pixel. As shown in Figure 4, position P2 is the outer edge of the light-emitting area of ​​the light-emitting element of the sub-pixel. Position P3 is the outer edge of the passivation layer PVX2 used to form the first isolation structure 601. Position P1 is the location of the first isolation structure 601. The outermost arc-shaped portion of the light-emitting element shown in Figure 4 (the arc-shaped portion close to position P1) is the opening N0 in the pixel defining layer PDL that exposes the first isolation structure 601 (as shown in Figures 3A and 3B). The opening N0 is provided to facilitate the first isolation structure 601 to play a role in isolating the light-emitting functional layer.

[0063] For example, the light emitting element 200 includes an organic light emitting diode, but is not limited thereto.

[0064] Figures 5 to 7 are cross-sectional views of a partial structure of a display panel provided in an embodiment of the present disclosure. Figures 8 to 10 are plan views of a partial structure of a display panel provided in an embodiment of the present disclosure. Figures 3A and 3B show the structure of the display area and the second non-display area R3. Figures 5 to 10 show a partial structure within the peripheral area R2. The structure of Figures 5 to 10 may be a schematic diagram of point A in Figure 2. The inorganic insulating layer Y0 in the display panel shown in Figures 7 and 10 may be the passivation layer PVX2 shown in Figure 3A, Figure 3B or Figure 23, but is not limited thereto.

[0065] As shown in FIG. 3A to FIG. 10 , an embodiment of the present disclosure provides a display panel including: a base substrate BS, a first organic insulating layer Y1 , a plurality of sub-pixels SP, an inorganic insulating layer Y0 , a second organic insulating layer Y2 , and a first isolation structure 601 (isolation structure 600 ). The base substrate BS includes a display area R1 and a peripheral area R2 located on at least one side of the display area R1; the first organic insulating layer Y1 is located in the display area R1 and the peripheral area R2; the multiple sub-pixels SP include multiple light-emitting elements 200, the multiple light-emitting elements 200 are located in the display area R1 and on the side of the first organic insulating layer Y1 facing away from the base substrate BS, the multiple light-emitting elements 200 include an electrode pattern layer LY, a common electrode E2, and a light-emitting functional layer FL located between the electrode pattern layer LY and the common electrode E2, the electrode pattern layer LY includes multiple pixel electrodes E1 independent of each other, the light-emitting functional layer FL includes multiple film layers, and the electrode pattern layer LY is closer to the base substrate BS than the common electrode E2; the inorganic insulating layer Y0 is located in the display area R1 and the peripheral area R2, and is located on the side of the first organic insulating layer Y1 facing away from the base substrate BS; the second organic insulating layer Y2 is located on the side of the inorganic insulating layer Y0 facing away from the base substrate BS. The first isolation structure 601 is located between adjacent sub-pixels SP of the multiple sub-pixels SP, and the first isolation structure 601 is configured to isolate at least one film layer among the multiple film layers of the light-emitting functional layer FL (at least one film layer in the common layer CL); the first isolation structure 601 includes a first isolation portion PT1 and a second isolation portion PT2, the first isolation portion PT1 is located in the first organic insulating layer Y1, and the second isolation portion PT2 is located in the inorganic insulating layer Y0, the inorganic insulating layer Y0 has a plurality of through holes H0 located in the peripheral area R2, and the second organic insulating layer Y2 is in contact with the first organic insulating layer Y1 through the plurality of through holes H0.

[0066] In the display panel provided by the embodiment of the present disclosure, the inorganic insulating layer Y0 has a plurality of through holes H0 located in the peripheral area R2, so that the second organic insulating layer Y2 contacts the first organic insulating layer Y1 through the plurality of through holes H0 (as shown in FIG7 ), thereby increasing the bonding force, avoiding the risk of easy peeling caused by the contact between the inorganic insulating layer and the organic insulating layer, improving the contact reliability, facilitating the degassing of the organic insulating layer below the inorganic insulating layer, and improving the process reliability.

[0067] As shown in FIG. 5 and FIG. 8 , an inorganic insulating thin film TL is formed on the planarization layer PLN3 .

[0068] As shown in Figures 6 and 9, a plurality of through holes H0 are formed in the inorganic insulating film TL to form an inorganic insulating portion TP (the portion of the inorganic insulating layer Y0 located in the peripheral region R2). For example, in the peripheral region R2, all portions of the inorganic insulating layer Y0 located in the peripheral region R2 and having a size greater than 10 μm × 10 μm can be provided with through holes H0.

[0069] As shown in FIG. 7 and FIG. 10 , the pixel defining layer PDL is in contact with the planarization layer PLN through a plurality of through holes H0 .

[0070] The planarization layer PLN3 in FIG3A and FIG3B and FIG5 to FIG10 is the first organic insulating layer Y1, and the pixel defining layer PDL is the second organic insulating layer Y2. The embodiments of the present disclosure include but are not limited to the above.

[0071] For example, as shown in FIG. 7 and FIG. 10 , the second organic insulating layer Y2 (pixel defining layer PDL) covers the plurality of through holes H0 to improve the bonding strength between the second organic insulating layer Y2 and the first organic insulating layer Y1 and prevent peeling.

[0072] For example, as shown in FIG. 9 , a plurality of through holes H0 are formed in a plurality of rows and columns to facilitate improving the bonding force between the second organic insulating layer Y2 and the first organic insulating layer Y1 .

[0073] For example, as shown in FIG9 , the plurality of through holes H0 include at least two through holes H0 staggered in both a first direction X and a second direction Y. The first direction X and the second direction Y are perpendicular and parallel to the base substrate BS. The staggered arrangement of the through holes H0 improves the bonding strength between the second organic insulating layer Y2 and the first organic insulating layer Y1.

[0074] Of course, in other embodiments, the plurality of through holes H0 may also be arranged in other ways. For example, the plurality of through holes H0 may be arranged in an array.

[0075] For example, as shown in Figures 3A and 3B, the second isolation portion PT2 protrudes from the first isolation portion PT1 at the edge to form a first protrusion PR1, and at least one film layer among the multiple film layers of the light-emitting functional layer FL (at least one film layer in the common layer CL) is disconnected at the first protrusion PR1.

[0076] For example, as shown in Figures 3A and 3B, the second organic insulating layer Y2 is located on a side of the electrode pattern layer LY facing away from the base substrate BS. The second organic insulating layer Y2 includes a plurality of openings PN configured to expose the plurality of pixel electrodes E1. In other words, the second organic insulating layer Y2 serves as a pixel defining layer (PDL). The pixel defining layer (PDL) includes a plurality of openings PN that expose the plurality of pixel electrodes E1. The plurality of openings PN correspond to the light-emitting regions of the sub-pixels or light-emitting elements.

[0077] Figure 11 is a schematic diagram of a display panel provided by an embodiment of the present disclosure. Figures 12 to 18 are flow charts of a process for fabricating a second isolation structure and a third isolation structure in a display panel provided by an embodiment of the present disclosure. Figures 12 to 18 illustrate a second isolation structure 602 and a third isolation structure 603 located in the second non-display region R0.

[0078] Figure 11 does not show the first isolation structure 601 located between adjacent sub-pixels SP. The first isolation structure 601 can be shown with reference to Figures 3A to 3B. Figure 11 only schematically shows one second isolation structure 602 and one third isolation structure 603. However, the number of second isolation structures 602 and third isolation structures 603 is not limited to that shown in the figure. In an embodiment of the present disclosure, the third isolation structure 603 is closer to the first non-display area R3 than the second isolation structure 602. For example, when one or more second isolation structures 602 and one or more third isolation structures 603 are provided, the one or more third isolation structures 603 are closer to the first non-display area R3 than the one or more second isolation structures 602. As shown in Figures 12 to 18, multiple third isolation structures 603 are closer to the first non-display area R3 than the second isolation structure 602.

[0079] As shown in FIG12 , a barrier layer BR is formed on a substrate BS, a buffer layer BF is formed on the barrier layer BR, a gate insulating layer GI1 is formed on the buffer layer BF, a gate insulating layer GI2 is formed on the gate insulating layer GI1, an interlayer insulating layer ILD is formed on the gate insulating layer GI2, an isolation structure intermediate pattern M0 and a conductive line CDL are formed on the interlayer insulating layer ILD, and a planarization film PLN0 is formed on the isolation structure intermediate pattern M0 and the conductive line CDL. The planarization film PLN0 includes a planarization film PLN01 and a planarization film PLN02. The planarization films PLN01 and PLN02 have different thicknesses, with the planarization film PLN01 being thicker than the planarization film PLN02. For example, the thickness of the planarization film PLN01 may be half the thickness of the planarization film PLN02, but is not limited thereto. As shown in FIG12 , the planarization film PLN01 covers the conductive line CDL, and the planarization film PLN02 covers the isolation structure intermediate pattern M0. As shown in FIG. 16 and FIG. 18 , the planarization layer PLN may play a role in protecting the conductive line CDL.

[0080] 13 , a passivation film PVX20 is formed on the planarization film PLN0. The passivation film PVX20 is an inorganic film.

[0081] As shown in FIG. 14 , the passivation film PVX20 and the planarization film PLN0 are dry-etched in sequence.

[0082] As shown in FIG15 , a dry etching process is used to etch the portions of the passivation film PVX20 and the planarization film PLN0 located in the second non-display area R0 to form a second isolation structure 602, and to form a passivation layer PVX2 (inorganic insulating layer Y0) and a planarization layer PLN (first organic insulating layer Y1). The second removed portion GRV2 can be designed to be deeper so that the depth of the second removed portion GRV2 can be adjusted to be deeper. For example, the second removed portion GRV2 can be formed by increasing the etching time or adjusting the etching gas concentration.

[0083] As shown in Figures 16 and 17, the pixel electrode E1 and the third isolation structure 603 are formed in the same patterning process. That is, the isolation structure intermediate pattern M0 and the electrode film are etched using the same patterning process to simultaneously form the pixel electrode E1 and the third isolation structure 603. Figure 17 shows the connecting electrode E0 located on the same layer as the pixel electrode E1. The connecting electrode E0 contacts the conductive line L1 to form a conductive connection structure.

[0084] Figures 19 to 21 are flow charts of a process for manufacturing a first isolation structure in a display area of ​​a display panel according to an embodiment of the present disclosure. Figure 22 is a schematic diagram of protecting a display area when forming a second isolation structure in a display panel according to an embodiment of the present disclosure.

[0085] As shown in FIG. 19 , a passivation film PVX20 (inorganic insulating film TL) is formed on the planarization film PLN0 (planarization film PLN01 ).

[0086] As shown in FIG. 20 and FIG. 21 , the passivation film PVX20 and the planarization film PLN0 (planarization film PLN01 ) are sequentially etched to form a passivation layer PVX2 (inorganic insulating layer Y0 ) and a planarization layer PLN (first organic insulating layer Y1 ).

[0087] As shown in FIG22 , in the etching process for forming the second isolation structure 602, a protective layer 700 is used to protect the structure in the display area. That is, the protective layer 700 is used to cover the structure in the display area. For example, the protective layer 700 includes a photoresist, but is not limited thereto. In the process of forming the second removed portion GRV2 in the second isolation structure 602, the process of the first isolation structure 601 in the display area is not affected, and the second removed portion GRV2 can be set deeper to better isolate the light-emitting functional layer and the common electrode in the second non-display area, so as to better eliminate the electrochemical reaction at the third isolation structure 603 in the second non-display area and avoid the generation of dark spots.

[0088] The following describes the manufacturing process of the structures in the display area, the peripheral area, and the second non-display area of ​​the display panel with reference to FIG. 3A , FIG. 3B , FIG. 5 to FIG. 10 , and FIG. 12 to FIG. 22 .

[0089] Step 1) forming a planarization film PLN0 on the base substrate on which the pixel circuit 100 and the isolation structure intermediate pattern M0 are formed.

[0090] Step 2) Thinning the portion of the planarization film PLN0 located in the second non-display area R0, while the portions of the planarization film located in the display area R1 and the peripheral area R2 are not thinned and have a normal thickness.

[0091] For example, a half-tone mask can be used for thinning. But it’s not limited to this.

[0092] Step 3) forming an inorganic insulating film (passivation film PVX20) on the planarization film PLN0. The inorganic insulating film (passivation film PVX20) is formed in the display region R1, the peripheral region R2, and the second non-display region R0.

[0093] Step 4) Use a dry etching process to etch the inorganic insulating film (passivation film PVX20) to form a through hole H0 in the peripheral area, a second isolation portion PT2, and a first removed portion GRV1 in the display area (simultaneously forming the first isolation portion PT1).

[0094] In step 5, a dry etching process is used to further remove the portion of the planarization film PLN0 located in the second non-display area R0 and form a first removed portion GRV1 in the display area R1 and a second removed portion GRV2 in the second non-display area R3.

[0095] Step 6) Protect the structure in the display area with a protective layer 700. A dry etching process is used to etch the structure 602 in the second non-display area to form the fourth isolation portion PT4 and the second removed portion GRV2 (simultaneously forming the third isolation portion PT3). The protective layer 700 is then removed. A protective layer 700, such as a photoresist, is used to cover the structure in the display area to avoid etching. The second removed portion GRV2 can be deepened.

[0096] Step 7) forming an electrode film.

[0097] In step 8, the electrode film and the isolation structure intermediate pattern M0 are etched using the same etching process to form a plurality of pixel electrodes E1 in the display area and a third isolation structure 603 in the second non-display area R0. The second sublayer 602 in the third isolation structure 603 is undercut to form an undercut structure.

[0098] The display panel provided by the embodiment of the present disclosure forms a first isolation structure 601 in the display area, and forms a second isolation structure 602 and a third isolation structure 603 in the second non-display area R3, which is beneficial for isolating the light-emitting functional layer FL and is beneficial for isolating the common electrode E2 in the second non-display area.

[0099] As shown in FIG. 2 , FIG. 3A and FIG. 3B , and FIG. 11 to FIG. 18 , the base substrate BS further includes a first non-display area R3 , which is a non-luminous area. A second non-display area R0 is provided between the first non-display area R3 and the display area R1 .

[0100] As shown in Figures 3A and 3B, Figure 12, and Figure 15, the display panel also includes a second isolation structure 602 (isolation structure 600) located in the second non-display area R0, the second isolation structure 602 is configured to isolate at least one film layer among the multiple film layers (at least one film layer in the common layer CL), and is configured to isolate the common electrode E2, the second isolation structure 602 includes a third isolation portion PT3 and a fourth isolation portion PT4, the third isolation portion PT3 is located in the first organic insulating layer Y1, and the fourth isolation portion PT4 is located in the inorganic insulating layer Y0.

[0101] In the display panel provided by the embodiments of the present disclosure, the second isolation structure 602 and the first isolation structure 601 have the same film structure to facilitate manufacturing. For example, the corresponding film layers of the second isolation structure 602 and the first isolation structure 601 can be manufactured using the same thin film formation process, or alternatively, different patterning processes can be used.

[0102] For example, as shown in Figures 3A, 15 to 17, and 18, the fourth isolation portion PT4 protrudes from the third isolation portion PT3 at the edge to form a second protrusion PR2, and at least one film layer among the multiple film layers of the light-emitting functional layer FL (at least one film layer in the common layer CL) and the common electrode E2 are disconnected at the second protrusion PR2.

[0103] For example, as shown in FIG3A , the first organic insulating layer Y1 has a first removed portion GRV1 at the first isolation structure 601, and as shown in FIG3A , FIG15 to FIG17 , and FIG18 , the first organic insulating layer Y1 has a second removed portion GRV2 at the second isolation structure 602. The first removed portion GRV1 is provided to facilitate the formation of the first protruding portion PR1, and the first removed portion GRV2 is provided to facilitate the formation of the second protruding portion PR2.

[0104] For example, as shown in FIG3A , to facilitate isolation of the common electrode E2 in the second non-display region R3 and prevent signals on the common electrode E2 from being transmitted to the second non-display region R3 and causing electrochemical reactions, thereby preventing dark spots, the maximum depth H1 of the first removed portion GRV1 is smaller than the maximum depth H2 of the second removed portion GRV2. In other words, by deepening the second removed portion GRV2 alone, the common electrode E2 is better isolated in the second non-display region R3. If the groove depths of the isolation structures differ, the groove depth of the second isolation structure 602 can be deepened individually.

[0105] In the embodiment of the present disclosure, the depth is the height difference between the recessed area (the first removed portion GRV1 or the second removed portion GRV2) and the surrounding plane area. Because each area has a different film layer underneath, the film layer itself may also have a certain height difference. The depth is obtained by comparing the recessed area with the surrounding area close to the recessed area.

[0106] For example, the maximum depth H1 of the first removed portion GRV1 is less than or equal to the thickness of the first organic insulating layer Y1. For example, the maximum depth H1 of the first removed portion GRV1 may be -0.2 μm, but not limited thereto. The maximum depth H1 of the first removed portion GRV1 may correspond to the maximum dimension of the first isolation portion PT1 in the third direction Z. For example, in some embodiments, the maximum depth H1 of the first removed portion GRV1 is less than 0.15 μm. For example, in some embodiments, the maximum depth H1 of the first removed portion GRV1 is less than 0.1 μm. For example, in some embodiments, the maximum depth H1 of the first removed portion GRV1 is less than or equal to

[0107] For example, the maximum depth H1 of the second removed portion GRV2 is less than or equal to the thickness of the first organic insulating layer Y1. For example, the maximum depth H2 of the second removed portion GRV2 is less than or equal to the thickness of the first organic insulating layer Y1. For example, the maximum depth H2 of the second removed portion GRV2 may be 0.2-0.5 μm, but is not limited thereto. Furthermore, for example, the maximum depth H2 may be 0.2-0.3 μm. The maximum depth H2 of the second removed portion GRV2 may correspond to the maximum dimension of the third partition PT3 in the third direction Z.

[0108] For example, in the embodiment of the present disclosure, the first removed portion GRV1 may be a groove or a through hole.

[0109] For example, in the embodiment of the present disclosure, the second removed portion GRV2 may be a groove or a through hole.

[0110] For example, as shown in FIG3A , to facilitate isolation of the common electrode E2 in the second non-display area R3, prevent signals on the common electrode E2 from being transmitted to the second non-display area R3 and causing electrochemical reactions, thereby preventing dark spots, the maximum dimension of the first removed portion GRV1 in a direction perpendicular to the base substrate BS is smaller than the maximum dimension of the second removed portion GRV2 in a direction perpendicular to the base substrate BS. The direction perpendicular to the base substrate BS is a third direction Z. The maximum dimension of the first removed portion GRV1 in a direction perpendicular to the base substrate BS can be dimension H1, and the maximum dimension of the second removed portion GRV2 in a direction perpendicular to the base substrate BS can be dimension H2.

[0111] For example, as shown in FIG3A , the first isolation structure 601 forms a half-T-shaped structure, and the second isolation structure 602 forms a half-T-shaped structure. The dimension of the second isolation structure 602 in a direction perpendicular to the substrate BS is greater than the dimension of the first isolation structure 601 in a direction perpendicular to the substrate BS. Because the maximum depth of the first removed portion GRV1 is less than the maximum depth of the second removed portion GRV2, the dimension of the second isolation structure 602 in a direction perpendicular to the substrate BS is greater than the dimension of the first isolation structure 601 in a direction perpendicular to the substrate BS. For example, the dimension of the second isolation structure 602 in a direction perpendicular to the substrate BS can be the sum of the maximum depth H1 of the second removed portion GRV2 and the thickness of the fourth isolation portion PT4. The dimension of the first isolation structure 601 in a direction perpendicular to the substrate BS can be the sum of the maximum depth H1 of the first removed portion GRV1 and the thickness of the second isolation portion PT2. In the embodiment of the present disclosure, the thickness of the fourth isolation portion PT4 can be equal to the thickness of the second isolation portion PT2. For example, in an embodiment of the present disclosure, as shown in FIG. 3A , the thickness of the inorganic insulating layer Y0 (passivation layer PVX2 ) is the same at all locations, but the present invention is not limited thereto.

[0112] In the embodiment of the present disclosure, the half T-shape may be a portion of the T-shape divided into two parts from the middle. For example, the second isolation portion PT2 only protrudes from the edge of one side of the first isolation portion PT1.

[0113] For example, as shown in Figures 11 and 16 to 18, the display panel further includes a third isolation structure 603 (isolation structure 600), which is located in the second non-display region R0 and is closer to the first non-display region R3 than the second isolation structure 602. Multiple isolation structures are provided in the second non-display region to better isolate the common electrode E2.

[0114] 16 to 18 , the material of the third isolation structure 603 is different from that of the second isolation structure 602. Forming isolation structures of different materials can ensure that the common electrode E2 is isolated in the second non-display region R0.

[0115] For example, as shown in FIG. 16 to FIG. 18 , the material of the third isolation structure 603 is a conductive material.

[0116] For example, as shown in Figures 16 and 18 , the spacing M3 between the third isolation structure 603 and the base substrate BS is different from the spacing M2 between the second isolation structure 602 and the base substrate BS, thereby arranging the isolated common electrode E2 at different heights in the third direction Z. For example, as shown in Figures 16 and 18 , the spacing M3 between the third isolation structure 603 and the base substrate BS is smaller than the spacing M2 between the second isolation structure 602 and the base substrate BS. Thus, the isolation structures for isolating the common electrode E2 are arranged at different heights in the third direction Z, facilitating isolation of the common electrode E2. Using the same reference for spacing comparison, for example, the spacing between the isolation structure 600 and the base substrate BS can refer to the spacing between the bottom end of the isolation structure and the base substrate BS. For example, the bottom end of the isolation structure can refer to the bottom wall of the groove where the isolation structure is located.

[0117] For example, as shown in Figures 16 to 18 , the third isolation structure 603 is I-shaped and is made of metal. This arrangement facilitates the fabrication of the third isolation structure 603. For example, the third isolation structure 603 can be formed in the same etching process as the electrode pattern layer.

[0118] For example, as shown in Figures 3A and 16 to 18, the third isolation structure 603 includes a first sublayer 6031 (fifth isolation portion PT5), a second sublayer 6032 (sixth isolation portion PT6), and a third sublayer 6033 (seventh isolation portion PT7). For example, the first sublayer 6031 (fifth isolation portion PT5), the second sublayer 6032 (sixth isolation portion PT6), and the third sublayer 6033 (seventh isolation portion PT7) can each be made of metal. The second sublayer 6032 (sixth isolation portion PT6) is recessed relative to the first sublayer 6031 (fifth isolation portion PT5) and the third sublayer 6033 (seventh isolation portion PT7), thereby forming an I-shaped structure to form the third protrusion PR3. For example, the third isolation structure 603 can be a stacked structure formed of three sublayers: titanium / aluminum / titanium (Ti / Al / Ti). During the etching process, the intermediate layer has a higher etch rate, thereby forming an undercut structure.

[0119] For example, as shown in FIG16 , the display panel further includes a conductive line CDL located in the second non-display region R0. The orthographic projection of the inorganic insulating layer Y0 on the base substrate BS overlaps with the orthographic projection of the conductive line CDL on the base substrate BS. The conductive line CDL may be at least one of a gate line or a data line. The conductive line CDL may be a winding within the second non-display region R0. The conductive line CDL bypasses the first non-display region R3 to connect the sub-pixels located on both sides of the first non-display region R3. The structure and location of the conductive line CDL are not limited to those shown in the figure.

[0120] As shown in FIG18 , a second isolation structure 602 and a third isolation structure 603 are provided so that when the light-emitting functional layer FL (common layer CL) and the common electrode E2 are subsequently formed, the light-emitting functional layer FL (common layer CL) and the common electrode E2 can be isolated at the corresponding isolation structure positions.

[0121] As shown in FIG. 18 , a portion of the light emitting function layer FL (common layer CL) and a portion of the common electrode E2 fall into the second removed portion GRV2 , so that the light emitting function layer FL (common layer CL) is disconnected at the second protrusion PR2 of the second isolation structure 602 .

[0122] As shown in Figure 18, the light-emitting functional layer FL (common layer CL) is disconnected at the second isolation structure 602 to form separation parts FL1, separation part FL2 and separation part FL3, and the light-emitting functional layer FL (common layer CL) is disconnected at the third isolation structure 603 to form separation parts FL4 and separation parts FL5.

[0123] As shown in FIG18 , the separation portion FL2 is located within the second removed portion GRV2, and the separation portion FL4 is located on the third isolation structure 603. As shown in FIG18 , the separation portion FL4 is in contact with the third isolation structure 603.

[0124] As shown in FIG18 , the common electrode E2 is disconnected at the second isolation structure 602 to form separations E21, E22, and E23, and the common electrode E2 is disconnected at the third isolation structure 603 to form separations E24 and E25. As shown in FIG18 , the separation E22 is located within the second removed portion GRV2, and the separation E24 is located on the third isolation structure 603.

[0125] Figure 3B also shows the separated portion of the light-emitting functional layer FL located in the first removed portion GRV1, the separated portion of the light-emitting functional layer FL located in the second removed portion GRV2, the separated portion of the common electrode E2 located in the first removed portion GRV1, and the separated portion of the common electrode E2 located in the second removed portion GRV2.

[0126] The embodiments of the present disclosure are described using the third isolation structure 603 as a conductive structure, but are not limited thereto. The third isolation structure 603 may also have a structure similar to the second isolation structure 602. In some embodiments, the third isolation structure 603 may not be provided. In other embodiments, the second isolation structure 602 may also not be provided.

[0127] For example, in some embodiments, one or more second isolation structures 602 may be provided. Each second isolation structure 602 is annular and surrounds the first non-display region R3. FIG11 illustrates an example of a display panel including one second isolation structure 602. The number of second isolation structures 602 may be set as needed.

[0128] For example, in some embodiments, one or more third isolation structures 603 may be provided. Each third isolation structure 603 is annular and surrounds the first non-display area R3. FIG11 illustrates a display panel including one third isolation structure 603 as an example. FIG16 to FIG18 illustrate a display panel including four third isolation structures 603 as an example. The number of third isolation structures 603 can be set as needed.

[0129] Figure 23 is a cross-sectional view of a display panel provided by an embodiment of the present disclosure. Compared to the display panel shown in Figures 3A or 3B , the position of the second isolation portion PT2 (passivation layer PVX2, inorganic insulating layer Y0) of the first isolation structure 601 in the display panel shown in Figure 23 has been adjusted. As shown in Figure 23 , the second isolation portion PT2 (passivation layer PVX2, inorganic insulating layer Y0) is located between the planarization sublayer PLN3-1 and the planarization sublayer PLN3-2.

[0130] As shown in Figures 1, 3A, 3B, and 23, embodiments of the present disclosure provide a display panel comprising: a base substrate BS, a plurality of pixel circuits 100, an insulating layer ISL, a plurality of pixel electrodes E1, a light-emitting functional layer FL, and a first isolation structure 601. The plurality of pixel circuits 100 are located on the base substrate BS. The insulating layer ISL is located on the side of the plurality of pixel circuits 100 facing away from the base substrate BS and includes a plurality of planarization layers, each comprising an organic material. The pixel electrode E1 is located on the side of the plurality of planarization layers facing away from the base substrate BS and is connected to one of the plurality of pixel circuits 100. The light-emitting functional layer FL includes a common layer CL, the orthographic projection of the common layer CL on the base substrate BS overlapping with the orthographic projections of the plurality of pixel electrodes E1 on the base substrate BS, with at least a portion of the common layer CL located on the side of the plurality of pixel electrodes E1 facing away from the base substrate BS. As shown in Figures 3A, 3B, and 23, the second isolation portion PT2 of the first isolation structure 601 includes a first protrusion PR1 of the planarization layer protruding from the underlying portion. As shown in Figures 3A, 3B, and 23, the first isolation structure 601 is configured to isolate the common layer CL (light-emitting functional layer FL) at the first protrusion PR1. As shown in Figures 3A, 3B, and 23, the first isolation structure 601 is located between adjacent pixel electrodes E1 and includes an inorganic material. The first isolation structure 601 is located on at least a portion of the planarization layer.

[0131] As shown in FIG23 , the first isolation structure 601 is separated from the plurality of pixel electrodes E1 by at least a portion of the planarization layer. For example, "the first isolation structure 601 is separated from the plurality of pixel electrodes E1 by at least a portion of the planarization layer" may mean that at least a portion of the planarization layer is disposed between the first isolation structure 601 and the plurality of pixel electrodes E1.

[0132] The display panel provided by the embodiment of the present disclosure as shown in Figure 23 has at least one of the following effects. First, the second isolation portion PT2 of the first isolation structure 601 has a first protrusion PR1 protruding from the planarization layer below it, and the pixel electrode E1 and the first isolation structure 601 are at least partially separated by the planarization layer, which ensures flatness, is conducive to flattening the pixel electrode E1, improves light efficiency, and is conducive to improving display effects (the display panel shown in Figure 3A is in the dotted box F3, and the pixel electrode E1 is located above the passivation layer PVX2 and in contact with the passivation layer PVX2). Second, the pixel electrode E1 and the first isolation structure 601 are at least partially separated by the planarization layer, and the first isolation structure 601 is located below the pixel electrode E1. Even if there is a limitation of a small distance between pixel electrodes, bilateral isolation (isolation on both sides) can still be performed to improve the isolation effect. Third, the pixel defining layer PDL is not in direct contact with the structure forming the first isolation structure 601, avoiding the risk of peeling of the pixel defining layer PDL (the pixel defining layer PDL is in contact with the passivation layer PVX2 at the dotted box F2 of the display panel shown in Figure 3A). Fourth, the structure forming the first isolation structure 601 can be set smaller, which is conducive to the exhaust of the planarization layer in the annealing process and reduces the risk of outgassing caused by subsequent high-temperature processes. Fifth, the impact on the bending performance of the display panel can be reduced. Sixth, lateral crosstalk between adjacent sub-pixels is avoided. For example, the structure forming the first isolation structure 601 includes a passivation layer PVX2.

[0133] Figures 3A, 3B, and 23 all employ double-sided partitioning (two-sided partitioning), but in other embodiments, single-sided partitioning (single-sided partitioning) may also be employed. In the single-sided partitioning approach, one first protrusion PR1 corresponds to the same first removed portion GRV1, forming one disconnection point. In the double-sided partitioning approach, two first protrusions PR1 correspond to the same first removed portion GRV1, forming two disconnection points.

[0134] For example, as shown in FIG. 23 , the second organic insulating layer Y2 is located on a side of the electrode pattern layer LY close to the base substrate BS, and the second organic insulating layer Y2 has a via hole Va so that the pixel electrode E1 is connected to the pixel circuit 100 through the via hole Va.

[0135] As shown in FIG23 , the planarization sublayer PLN3-2 (second organic insulating layer Y0) has a through hole HL2 at the first isolation structure 601. The through hole HL2 communicates with the first removed portion GRV1 and with the opening PN in the pixel defining layer PDL, thereby facilitating isolation of the light-emitting functional layer FL by the first isolation structure 601. In some embodiments, the first isolation structure 601 may also isolate the common electrode E2.

[0136] For example, as shown in Figures 3A, 3B, and 23, the display panel also includes a first connecting electrode CE1 and a second connecting electrode CE2, the pixel circuit 100 includes a transistor T1, the first connecting electrode CE1 is located on the planarization layer PLN1, and is connected to the transistor T1 through a via hole passing through the planarization layer PLN1, the second connecting electrode CE2 is located on the planarization layer PLN2, and is connected to the first connecting electrode CE1 through a via hole passing through the planarization layer PLN2, the pixel electrode E1 is located on the planarization layer PLN3, and is connected to the second connecting electrode CE2 through a via hole passing through the planarization layer PLN3.

[0137] For example, as shown in Figures 3A, 3B, and 23, transistor T1 includes a gate electrode GT1, a gate insulating layer GI1, an active layer AT1, a first electrode Ea, and a second electrode Eb. The first electrode Ea and the second electrode Eb are respectively connected to two ends of the active layer AT1. A first connecting electrode CE1 is connected to the second electrode Eb. For example, the active layer AT1 of transistor T1 is made of low-temperature polycrystalline silicon (LTPS), but is not limited thereto.

[0138] 23 also shows a via hole Vb in the planarization layer PLN2 and a via hole Vc in the insulating layer ISL. The pixel electrode E1 is connected to the second connection electrode CE2 through the via hole Va, the second connection electrode CE2 is connected to the first connection electrode CE1 through the via hole Vb, and the first connection electrode CE1 is connected to the second electrode Eb through the via hole Vc.

[0139] For example, as shown in Figures 3A, 3B, and 23, the pixel circuit 100 further includes a transistor T2, which includes a gate GT2, a gate GT3, a gate insulating layer GI2, a gate insulating layer GI3, an active layer AT2, a first electrode Ec, and a second electrode Ed, wherein the first electrode Ec and the second electrode Ed are respectively connected to the two ends of the active layer AT2. For example, the gates GT2 and GT3 of the transistor T2 form a dual-gate structure to improve the performance of the transistor T2. For example, the active layer AT2 of the transistor T2 uses an oxide semiconductor, such as indium gallium zinc oxide (IGZO), but is not limited thereto.

[0140] For example, as shown in Figures 3A, 3B, and 23, the insulating layer ISL also includes an inorganic insulating layer PVX1, which is located between the pixel circuit 100 (including the transistor T1 and the transistor T2) and the planarization layer PLN1, and the first connection electrode CE1 also passes through the inorganic insulating layer PVX1.

[0141] For example, as shown in FIG. 3A , FIG. 3B , and FIG. 23 , the inorganic insulating layer PVX1 is provided on a side of the planarization layer close to the base substrate BS.

[0142] For example, as shown in Figures 3A, 3B, and 23, the pixel electrode E1 is connected to one of the plurality of pixel circuits 100 via a via hole penetrating at least a portion of the insulating layer ISL. In the case where a connection electrode is provided, the pixel electrode E1 is connected to the connection electrode via a via hole penetrating at least a portion of the insulating layer ISL, and the connection electrode is further connected to the pixel circuit 100. In the case where no connection electrode is provided, the pixel electrode E1 is connected to the pixel circuit 100 via a via hole penetrating the insulating layer ISL.

[0143] For example, as shown in Figures 3A, 3B, and 23, the base substrate BS includes a first base substrate PI1, a barrier layer BR1, and a second base substrate PI2. Of course, the structure of the base substrate BS is not limited to the above description. For example, the base substrate BS may also adopt a single-layer structure.

[0144] For example, the base substrate BS may be a flexible base substrate, but is not limited thereto. A flexible base substrate can be bent to reduce a frame or form a foldable display panel.

[0145] As shown in Figures 3A, 3B, and 23, a barrier layer BR2 is located on a base substrate BS. A light-shielding layer LS is provided on the barrier layer BR2. A buffer layer BF1 is provided on the light-shielding layer LS. A buffer layer BF2 is provided on the buffer layer BF1. An active layer AT2 is provided on the buffer layer BF2. A gate insulating layer GI1 is provided on the active layer AT2. A gate electrode GT1 is located on the gate insulating layer GI1. A buffer layer BF3 is provided on the gate electrode GT1. A gate electrode GT2 is provided on the buffer layer BF3. A gate insulating layer GI2 is provided on the gate electrode GT2. An active layer AT2 is provided on the gate insulating layer GI2. A gate insulating layer GI3 is provided on the active layer AT2. An interlayer insulating layer ILD is provided on the gate insulating layer GI3. A first electrode Ea, a second electrode Eb, a first electrode Ec, and a second electrode Ed are provided on the interlayer insulating layer ILD. The light-shielding layer LS blocks light, thereby improving the performance of the transistor T1.

[0146] For example, the barrier layer BR2 and the barrier layer BR1 may be made of the same material, but are not limited thereto.

[0147] As shown in Figures 3A, 3B, and 23, the display panel further includes a connecting electrode Ee, which may be connected to the light shielding layer LS. The connecting electrode Ee may be connected to other signal lines, such as a power line providing a constant voltage, to reduce the resistance of the power line. For example, the power line may be a signal line providing a power supply voltage VDD. The connecting electrode Ee is located on the interlayer insulating layer ILD and may be provided in the same layer as the first electrode Ea, the second electrode Eb, the first electrode Ec, and the second electrode Ed.

[0148] As shown in FIG3A , FIG3B , and FIG23 , the display panel further includes a connecting electrode CEa and a connecting electrode CEb. The connecting electrode CEa and the connecting electrode CEb are connected to each other. The connecting electrode CEa is located on the planarization layer PLN1, and the connecting electrode CEb is located on the planarization layer PLN2. The connecting electrode CEb is connected to the connecting electrode CEa via a via hole penetrating the planarization layer PLN2. The connecting electrode CEa and the connecting electrode CE1 are located on the same layer, and the connecting electrode CEb and the connecting electrode CE2 are located on the same layer.

[0149] As shown in Figures 3A, 3B, and 23, the display panel further includes a storage capacitor Cst, which includes a first plate Ca and a second plate Cb. For example, the first plate Ca and the gate GT1 are located on the same layer, and the second plate Cb and the gate GT2 are located on the same layer.

[0150] As shown in FIG. 3A , FIG. 3B , and FIG. 23 , the display panel further includes spacers PS configured to support the fine metal mask during the process of evaporating the local layer LL in the light-emitting functional layer FL.

[0151] For example, the spacer PS can be integrated with the pixel defining layer PDL and can be manufactured using a dual-tone mask.

[0152] For example, as shown in Figures 3A, 3B, and 23, to facilitate the planarization of the pixel electrode E1, the planarization layer PLN3 includes a planarization sublayer PLN3-1 and a planarization sublayer PLN3-2. The planarization sublayer PLN3-1 is closer to the base substrate BS than the planarization sublayer PLN3-2. Of course, in other embodiments, the planarization layer PLN3 may also adopt a single-layer structure.

[0153] As shown in Figure 23, the passivation layer PVX2 is disposed on the planarization sublayer PLN3-1 (a portion of the planarization layer PLN3), and the passivation layer PVX2 and the pixel electrode E1 are separated by the planarization sublayer PLN3-2 (a portion of the planarization layer PLN3). In Figure 23, a first removed portion GRV1 is formed in the planarization sublayer PLN3-1.

[0154] In other embodiments, the position of the passivation layer PVX2 can also be adjusted to between the planarization layers PLN2 and PLN3. The passivation layer PVX2 is disposed on the planarization layer PLN2 (a portion of the planarization layer), and the passivation layer PVX2 and the pixel electrode E1 are separated by the planarization layer PLN3 (a portion of the planarization layer). In this case, a first removed portion GRV1 is formed in the planarization layer PLN2.

[0155] In other embodiments, the position of the passivation layer PVX2 can also be adjusted to between the planarization layers PLN1 and PLN2. The passivation layer PVX2 is disposed on the planarization layer PLN1 (a portion of the planarization layer), and the passivation layer PVX2 and the pixel electrode E1 are separated by the planarization layer PLN2 and the planarization layer PLN3 (a portion of the planarization layer). In this case, a first removed portion GRV1 is formed in the planarization layer PLN1.

[0156] Compared with the display panel shown in Figures 3A and 3B, the first isolation structure 601 and the second isolation structure 602 can be moved downward to form a display panel with a different structure. That is, the passivation layer PVX2 is moved downward. In this case, in the display area, the planarization layer above the passivation layer PVX2 has a through hole, which is connected to the opening N0 in the pixel defining layer PDL and is connected to the first removed portion GRV1, so as to facilitate the first isolation structure 601 to play the role of isolating the light-emitting functional layer. It should be noted that the first isolation structure 601 and the second isolation structure 602 can be set above the planarization layer PLN1 and can be separated from the pixel electrode E1 by at least part of the planarization layer at any film layer position.

[0157] In an embodiment of the present disclosure, the passivation layer PVX2 is an inorganic insulating layer Y0, the planarization layer located below the passivation layer PVX2 and in contact with the passivation layer PVX2 is a first organic insulating layer Y1, and the planarization layer located above the passivation layer PVX2 and in contact with the passivation layer PVX2 is a second organic insulating layer Y2.

[0158] For example, as shown in Figure 23, the passivation layer PVX2 is located between two adjacent sub-pixels. For example, the passivation layer PVX2 is located in the middle of the two adjacent sub-pixels, and the width of the passivation layer PVX2 can be designed to be about 5 μm, forming a partition on both sides to enhance the partition effect.

[0159] In the embodiments of the present disclosure, the first organic insulating layer Y1 may be one or more film layers. For example, the first organic insulating layer Y1 includes at least one planarization layer. In the display panel shown in Figures 3A and 3B, the first organic insulating layer Y1 is a planarization sublayer PLN3-2. In the display panel shown in Figure 23, the first organic insulating layer Y1 may be a planarization sublayer PLN3-1 or a stacked structure comprising a planarization sublayer PLN3-1, a planarization layer PLN2, and a planarization layer PLN1.

[0160] In the embodiment of the present disclosure, the first isolation structure 601 is composed of an organic insulating layer (planarization layer) and an inorganic insulating layer (passivation layer PVX2) located thereon. The second isolation structure 602 is composed of an organic insulating layer (planarization layer) and an inorganic insulating layer (passivation layer PVX2) located thereon. The number of planarization layers contained in the organic insulating layer of the first isolation structure 601 and the second isolation structure 602 may be the same or different.

[0161] As shown in Figures 3A, 3B, and 23, a plurality of pixel circuits 100 and a plurality of light emitting elements 200. As shown in Figures 3A, 3B, and 23, the pixel circuit 100 includes a transistor T1 and a transistor T2.

[0162] FIG24 is a plan view of a display panel provided by an embodiment of the present disclosure.

[0163] For example, as shown in Figure 24 , the first isolation structure 601 surrounding one light emitting element 200 includes a plurality of isolation substructures 660. As shown in Figure 24 , the first isolation structure 601 surrounding the light emitting element 201 includes two isolation substructures 660. As shown in Figure 24 , the first isolation structure 601 surrounding the light emitting element 202 includes four isolation substructures 660.

[0164] For example, as shown in Figure 24, the multiple isolation substructures 660 include at least two isolation substructures 660 located on opposite sides of the light-emitting area of ​​the light-emitting element 200 (position P2 is the outer edge of the light-emitting area, corresponding to the opening PN). Such a setting is conducive to the formation of a gap G0 between adjacent isolation substructures 660. Providing the gap G0 is conducive to the continuity of the common electrode E2 and the application of the signal on the common electrode E2. That is, it is conducive to the common electrodes E2 corresponding to adjacent light-emitting elements to form an integrated structure, which is conducive to the application of the signal. That is, the common electrode E2 can be isolated at the first isolation structure 601 and connected at the gap G0, thereby ensuring the continuity of the common electrodes E2 of different light-emitting elements. Of course, a full circle of isolation structure can also be set, that is, the isolation structure surrounds the light-emitting area in a full circle. In this case, the connection of the common electrodes E2 corresponding to different sub-pixels can be achieved through other film layers.

[0165] For example, as shown in FIG24 , the spacing between at least one of the plurality of isolation substructures 660 and two adjacent light-emitting elements 200 is unequal. As shown in FIG24 , for light-emitting element 201 and its adjacent light-emitting element 203, spacing D1 is smaller than spacing D2. As shown in FIG24 , for light-emitting element 201 and its adjacent light-emitting element 202, spacing D3 is smaller than spacing D4. The first isolation structure 601 (isolation substructure 660) between adjacent light-emitting elements is disposed near one of the light-emitting elements. When two first protrusions PR1 are disposed within an opening N0, the center line between the two first protrusions PR1 can be used as one end of the spacing calculation.

[0166] As shown in Figure 24 , position P1 is the location of a first protrusion PR1 of the first isolation structure 601, position P4 is the location of another first protrusion of the first isolation structure 601, and position P2 is the outer edge of the light-emitting area of ​​the sub-pixel's light-emitting element, corresponding to the edge of opening N0. The plan view shown in Figure 24 corresponds to a case where a first isolation structure 601 has two first protrusions PR1 and is bisected on both sides.

[0167] For example, as shown in Figure 24, the light-emitting area of ​​the first light-emitting element 201 is smaller than the light-emitting area of ​​the second light-emitting element 202, and the light-emitting area of ​​the second light-emitting element 202 is smaller than the light-emitting area of ​​the third light-emitting element 203. The first isolation structure 601 includes a first isolation structure 601 and a second isolation structure 602. The first isolation structure 601 is located at the periphery of the light-emitting area of ​​the first light-emitting element 201, and the second isolation structure 602 is located at the periphery of the light-emitting area of ​​the second light-emitting element 202.

[0168] For example, as shown in FIG24 , the first isolation structure 601 includes two first isolation substructures 6601 located on opposite sides of the light-emitting region of the first light-emitting element 201. The second isolation structure 602 includes four second isolation substructures 6602. The four second isolation substructures 6602 are arranged around the light-emitting region of the second light-emitting element 202. Two of the four second isolation substructures 6602 are located on opposite sides of the light-emitting region of the second light-emitting element 202, and the other two of the four second isolation substructures 6602 are located on opposite sides of the light-emitting region of the second light-emitting element 202. As shown in FIG24 , the four second isolation substructures 6602 are arranged sequentially around the light-emitting region of the second light-emitting element 202. As shown in FIG24 , a gap G01 is defined between two first isolation substructures 6601. As shown in FIG24 , a gap G02 is defined between two adjacent second isolation substructures 6602. The size of the gap G01 is larger than the size of the gap G02.

[0169] For example, as shown in FIG24 , the light-emitting region of the first light-emitting element 201 is surrounded by two first isolating substructures 6601 and two second isolating substructures 6602 located at the gaps in the first isolating substructures 6601. Thus, the first isolating structures 601 / isolating substructures 660 are disposed in the regions between the first light-emitting element 201 and its two adjacent second light-emitting elements 202, as well as between the first light-emitting element 201 and its two adjacent third light-emitting elements 203, thereby mitigating or avoiding crosstalk between adjacent sub-pixels.

[0170] For example, as shown in Figure 24, the light-emitting region of the third light-emitting element 203 is surrounded by four first isolation substructures 6601 and two second isolation substructures 6602. Thus, the first isolation structures 601 / isolation substructures 660 are disposed in the regions between the third light-emitting element 203 and its two adjacent second light-emitting elements 202, and between the third light-emitting element 203 and its four adjacent first light-emitting elements 201, thereby reducing or avoiding crosstalk between adjacent sub-pixels.

[0171] For example, as shown in Figure 24, the first light-emitting element 201 is configured to emit green light, the second light-emitting element 202 is configured to emit red light, and the third light-emitting element 203 is configured to emit blue light. Figure 24 illustrates an example in which the first light-emitting element 201 is configured to emit green light, the second light-emitting element 202 is configured to emit red light, and the third light-emitting element 203 is configured to emit blue light. However, the light-emitting colors of the light-emitting elements provided in the embodiments of the present disclosure are not limited to this and can be determined as needed.

[0172] For example, as shown in FIG24 , a repeating unit PX includes two first sub-pixels SP1, one second sub-pixel SP2, and one third sub-pixel SP3. For example, as shown in FIG24 , in a repeating unit PX, the second sub-pixel SP2 and the third sub-pixel SP3 are located on either side of a line connecting the centers of the two first sub-pixels SP1. Of course, the pixel arrangement of the display panel is not limited to that shown in FIG24 , and the pixel arrangement can be configured as desired.

[0173] As shown in FIG24 , the distance between the spacer structure 660 surrounding the light-emitting region of a light-emitting element and the light-emitting region of the light-emitting element is greater than the distance between the spacer structure 660 and the light-emitting region of the adjacent light-emitting element. In other words, the closer the spacer structure 660 is to the light-emitting region of the light-emitting element around which it is located, the closer it is to the light-emitting region of the light-emitting element.

[0174] FIG24 takes the example of a plurality of passivation layers PVX2 provided around the light-emitting area of ​​the light-emitting element to form the first isolation structure 601, however, it is not limited thereto. The passivation layer PVX2 provided around the light-emitting area of ​​the light-emitting element can also be provided as a full circle structure, as long as a plurality of discrete openings N0 are provided around the light-emitting area of ​​the same light-emitting element. For the plurality of isolation substructures provided in the light-emitting area of ​​the same light-emitting element, the position between adjacent openings N0 is the gap G0. That is, in the embodiment of the present disclosure, in order to facilitate the continuity of the common electrode E2, a plurality of openings N0 are provided around the light-emitting area of ​​the same light-emitting element, and the area between adjacent openings N0 is the gap G0.

[0175] 24 takes the arc shape of the first isolation structure 601 / isolator structure 660 as an example, but is not limited thereto and can be configured as needed. For example, the first isolation structure 601 / isolator structure 660 can be configured according to the shape of the outer edge of the light emitting area of ​​the light emitting element.

[0176] In an embodiment of the present disclosure, the planar shape of the first removed portion GRV1 may be as shown in FIG. 24 . The planar shape of the first removed portion GRV1 may be arc-shaped, but is not limited thereto. The planar shape of the first removed portion GRV1 may refer to the shape of the first isolation structure 601 or the isolation substructure 660 shown in FIG. 24 . Of course, the planar shape of the first removed portion GRV1 may also be annular. For example, in the area between the sub-pixels of the display area, multiple first removed portions GRV1 may be dispersed, connected into a sheet, or connected into a network.

[0177] In an embodiment of the present disclosure, the second removed portion GRV2 may be in a ring-shaped planar shape. For example, in the second non-display region R, the second removed portion GRV2 may be in the shape of one or more circles or a ring-shaped area.

[0178] In the embodiments of the present disclosure, the first protrusion PR1, the second protrusion PR2, and the third protrusion PR3 all protrude in the transverse direction and may also be referred to as transverse protrusions. In the isolation structure, the upper isolation portion protrudes from the lower isolation portion at its edge, which can also be considered as the lower isolation portion being indented to form a protrusion. The protrusion may refer to at least one of the first protrusion PR1, the second protrusion PR2, and the third protrusion PR3.

[0179] It should be noted that, in the embodiment of the present disclosure, the pixel circuit 100 includes a transistor T1, a transistor T2 and a storage capacitor. For example, the transistor T1 can be a light-emitting control transistor, and the transistor T2 can be a threshold compensation transistor or a reset control transistor, but are not limited thereto. The embodiment of the present disclosure does not limit the structure of the pixel circuit 100, and a conventional pixel circuit can be used. For example, the pixel circuit 100 can adopt a 7T1C pixel circuit, a 7T2C pixel circuit, an 8T1C pixel circuit or a 9T1C pixel circuit. Of course, the number of transistors and the number of capacitors included in the pixel circuit 100 are not limited to the above description, and can be determined as needed. The connection relationship between transistors or between transistors and capacitors is not shown in the cross-sectional view, and this is a conventional structure.

[0180] For example, in the embodiments of the present disclosure, components located on the same layer can be formed from the same film layer through the same patterning process. In the embodiments of the present disclosure, the composition or patterning process can include only a photolithography process, or a photolithography process and an etching step, or can include other processes such as printing and inkjet for forming a predetermined pattern. The photolithography process refers to a process including film formation, exposure, and development, using photoresist, a mask, an exposure machine, etc. to form a pattern. The corresponding patterning process can be selected according to the structure formed in the embodiments of the present disclosure.

[0181] For example, in an embodiment of the present disclosure, when the planarization layer PLN3 includes a planarization sublayer PLN3-1 and a planarization sublayer PLN3-2, the thickness of the planarization sublayer PLN3-1 may be 1-2 μm, and the thickness of the planarization sublayer PLN3-2 may be 1-2 μm. For example, in this case, the thickness of the planarization layer PLN3 may be 2-4 μm.

[0182] For example, in the embodiment of the present disclosure, when the planarization layer PLN3 is a single-layer structure, the thickness of the planarization layer PLN3 may be 1-2 μm.

[0183] For example, in an embodiment of the present disclosure, the thickness of the planarization layer PLN1 may be 1-2 μm.

[0184] For example, in an embodiment of the present disclosure, the thickness of the planarization layer PLN2 may be 1-2 μm.

[0185] For example, in an embodiment of the present disclosure, the thickness of the passivation layer PVX1 may be 0.1-0.25 μm.

[0186] For example, in the embodiments of the present disclosure, the base substrate BS, the barrier layer BR, the barrier layer BR1, the barrier layer BR2, the buffer layer BF1, the buffer layer BF2, the buffer layer BF3, the gate insulation layer GI1, the gate insulation layer GI2, the gate insulation layer GI3, the interlayer insulation layer ILD, the passivation layer PVX1, the passivation layer PVX2, the planarization layer PLN1, the planarization layer PLN2, the planarization layer PLN3, and the pixel defining layer PDL are all made of insulating materials.

[0187] For example, the material of the base substrate BS includes polyimide, but is not limited thereto. For example, the material of the base substrate PI1 includes polyimide, but is not limited thereto. For example, the material of the base substrate PI2 includes polyimide, but is not limited thereto. For example, the base substrate BS can be a flexible base substrate to form a flexible display panel.

[0188] For example, at least one of the barrier layers BR, BR1, BR2, buffer layers BF1, BF2, BF3, gate insulating layers GI1, GI2, GI3, interlayer insulating layer ILD, passivation layer PVX1, and PVX2 may be made of an inorganic insulating material. For example, the inorganic insulating material may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0189] For example, the pixel defining layer (PDL) and the planarization layer may be made of an organic insulating material. For example, the planarization layers PLN1, PLN2, and PLN3 may be made of an organic insulating material. For example, the organic insulating material may include one or a combination of acrylic, polyethylene terephthalate, polyimide, polyamide, polycarbonate, epoxy resin, and the like.

[0190] For example, in embodiments of the present disclosure, both the pixel defining layer (PDL) and the planarization layer may be referred to as an organic layer or an organic insulating layer. For example, each of the planarization layers PLN1, PLN2, and PLN3 may be referred to as an organic layer. The pixel defining layer (PDL) may be referred to as an organic layer. The planarization sublayer PLN3-1 may be referred to as an organic sublayer or an organic insulating sublayer, and the planarization sublayer PLN3-2 may be referred to as an organic sublayer or an organic insulating sublayer.

[0191] For example, in the embodiment of the present disclosure, the insulating layer ISL may also be referred to as an insulating material layer.

[0192] The structure of the display panel provided by the embodiments of the present disclosure is not limited to that shown in the figures. The structure of the display panel can be adjusted as needed, for example, by removing or adding some film layers, or removing or adding some components. For example, FIG3A, FIG3B, and FIG23 all take the example of the pixel electrode E1 being connected to the second electrode Eb via two connecting components (a first connecting electrode CE1 and a second connecting electrode CE2). In other embodiments, other numbers of connecting components, such as one or more than two, can be provided.

[0193] For example, in an embodiment of the present disclosure, at least one of the gate GT1, the gate GT2, the gate GT3, the first electrode Ca, the second electrode Cb, the first electrode Ea, the second electrode Eb, the first electrode Ec, the second electrode Ed, the first connecting electrode CE1, the second connecting electrode CE2, the connecting electrode CEa, the connecting electrode CEb, and the connecting electrode CEc is made of metal or alloy.

[0194] For example, in the embodiment of the present disclosure, the active layer AT1 and the active layer AT2 are semiconductor layers, and can be made of polysilicon or metal oxide semiconductor materials.

[0195] For example, in the embodiment of the present disclosure, one of the pixel electrode E1 and the common electrode E2 is the anode of the light-emitting element, and the other of the pixel electrode E1 and the common electrode E2 is the cathode of the light-emitting element. The embodiment of the present disclosure is described by taking the pixel electrode E1 as the anode and the common electrode E2 as the cathode as an example.

[0196] For example, the pixel electrode E1 is made of a conductive material. For example, the material of the pixel electrode E1 includes metal and conductive metal oxide. For example, the pixel electrode E1 has a structure in which indium tin oxide (ITO), silver (Ag), and indium tin oxide (ITO) are stacked. The material and structure of the pixel electrode E1 can be set as needed.

[0197] For example, the common electrode E2 is made of a conductive material. For example, the material of the common electrode E2 includes a metal or an alloy. For example, the material of the common electrode E2 includes a Mg / Ag alloy. The material and structure of the common electrode E2 can be set as needed.

[0198] It should be noted that the embodiments of the present disclosure are described using an example in which the common layer CL includes a first common layer CL1, a second common layer CL2, and a third common layer CL3, but the present invention is not limited thereto. The common layer CL may have a single-layer structure or a stacked-layer structure including multiple film layers. For example, in some embodiments, the common layer CL includes at least a charge generation layer.

[0199] For example, in an embodiment of the present disclosure, at least one film layer in the light-emitting functional layer FL may be manufactured by an evaporation process.

[0200] It should be noted that the embodiments of the present disclosure are described by taking the light emitting element having a Tandem structure as an example, but are not limited thereto. The light emitting element may also adopt other suitable structures.

[0201] For example, the display panel may further include an encapsulation layer configured to encapsulate the plurality of light emitting elements to prevent water and oxygen from invading.

[0202] For example, the pixel defining layer PDL can be a black pixel defining layer. Usually, the color filter on encapsulation (COE) structure can be matched with the black pixel defining layer.

[0203] For example, the display panel may further include a touch layer, and the touch layer may be disposed between the encapsulation layer and the COE structure.

[0204] For example, in an embodiment of the present disclosure, the conductive line CL, the conductive line CDL, and the third isolation structure 603 may be located at the same layer, for example, located at the same layer as the source and drain of the transistor.

[0205] In some figures of the embodiments of the present disclosure, a plan view shows a first direction X and a second direction Y, and a cross-sectional view shows a third direction Z. The first direction X and the second direction Y are both directions parallel to the main surface of the substrate BS. The third direction Z is a direction perpendicular to the main surface of the substrate BS. For example, the first direction X and the second direction Y intersect. The embodiments of the present disclosure are described using the example where the first direction X and the second direction Y are perpendicular. For example, the main surface of the substrate BS is the surface of the substrate BS used to manufacture various components. The upper surface of the substrate BS in the cross-sectional view is the main surface of the substrate BS. The third direction Z is perpendicular to the first direction X and the second direction Y.

[0206] An embodiment of the present disclosure further provides a display device, comprising any of the above-mentioned display panels.

[0207] For example, the display device can be a display device such as an organic light-emitting diode display device, as well as any product or component with a display function, such as a television, digital camera, mobile phone, watch, tablet computer, laptop computer, navigator, etc. that includes the display device. The embodiments of the present disclosure include but are not limited to the above.

[0208] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel, comprising: A substrate, comprising a display area and a peripheral area located on at least one side of the display area; A first organic insulating layer, located in the display area and the peripheral area; A plurality of sub-pixels, including a plurality of light-emitting elements, the plurality of light-emitting elements are located in the display area and on a side of the first organic insulating layer away from the base substrate, the plurality of light-emitting elements include an electrode pattern layer, a common electrode, and a light-emitting functional layer located between the electrode pattern layer and the common electrode, the electrode pattern layer includes a plurality of pixel electrodes independent of each other, the light-emitting functional layer includes a plurality of film layers, and the electrode pattern layer is closer to the base substrate than the common electrode; an inorganic insulating layer, located in the display area and the peripheral area, and located on a side of the first organic insulating layer away from the base substrate; A second organic insulating layer is located on a side of the inorganic insulating layer away from the base substrate; as well as a first isolation structure, located between adjacent sub-pixels of the plurality of sub-pixels, wherein the first isolation structure is configured to isolate at least one film layer of the plurality of film layers of the light-emitting functional layer, The first isolation structure includes a first isolation portion and a second isolation portion, the first isolation portion is located in the first organic insulating layer, and the second isolation portion is located in the inorganic insulating layer. The inorganic insulating layer has a plurality of through holes located in the peripheral region, and the second organic insulating layer contacts the first organic insulating layer through the plurality of through holes.

2. The display panel according to claim 1, wherein, The second organic insulating layer covers the plurality of through holes.

3. The display panel according to claim 1 or 2, wherein The plurality of through holes are formed in a plurality of rows and columns.

4. The display panel according to any one of claims 1-3, wherein, The plurality of through holes include at least two through holes that are staggered in a first direction and a second direction, wherein the first direction and the second direction are perpendicular and parallel to the base substrate.

5. The display panel according to any one of claims 1-4, wherein, The second isolating portion protrudes from the first isolating portion at an edge to form a first protruding portion, and at least one film layer of the plurality of film layers of the light-emitting functional layer is disconnected at the first protruding portion.

6. The display panel according to any one of claims 1-5, wherein, The base substrate also includes a first non-display area, which is a non-luminous area, and a second non-display area is provided between the first non-display area and the display area. The display panel also includes a second isolation structure located in the second non-display area, and the second isolation structure is configured to isolate at least one of the multiple film layers and to isolate the common electrode. The second isolation structure includes a third isolation portion and a fourth isolation portion, and the third isolation portion is located in the first organic insulating layer, and the fourth isolation portion is located in the inorganic insulating layer.

7. The display panel according to claim 6, wherein, The first organic insulating layer has a first removed portion at the first isolation structure, and the first organic insulating layer has a second removed portion at the second isolation structure.

8. The display panel according to claim 7, wherein, A maximum depth of the first removed portion is smaller than a maximum depth of the second removed portion.

9. The display panel according to claim 7, wherein, A maximum dimension of the first removed portion in a direction perpendicular to the base substrate is smaller than a maximum dimension of the second removed portion in a direction perpendicular to the base substrate.

10. The display panel according to any one of claims 6-9, wherein, The fourth isolation part protrudes from the third isolation part at the edge to form a second protruding part, and at least one of the multiple film layers of the light-emitting functional layer and the common electrode are disconnected at the second protruding part.

11. The display panel according to any one of claims 6-10, wherein, The first isolation structure forms a half T-shaped structure, the second isolation structure forms a half T-shaped structure, and the size of the second isolation structure in the direction perpendicular to the substrate is greater than the size of the first isolation structure in the direction perpendicular to the substrate.

12. The display panel according to any one of claims 6-11 further includes a third isolation structure, wherein, The third isolation structure is located in the second non-display area, and the third isolation structure is closer to the first non-display area than the second isolation structure.

13. The display panel according to claim 12, wherein, The material of the third isolation structure is different from the material of the second isolation structure.

14. The display panel according to claim 12 or 13, wherein, The material of the third isolation structure is a conductive material.

15. The display panel according to any one of claims 12-14, wherein, The distance between the third isolation structure and the substrate is less than the distance between the second isolation structure and the substrate.

16. The display panel according to any one of claims 12-15, wherein, The third isolation structure is in an I shape, and the material of the third isolation structure includes metal.

17. The display panel according to any one of claims 6-16 further includes a wire, wherein, The wire is located in the second non-display area, and the orthographic projection of the inorganic insulating layer on the substrate overlaps with the orthographic projection of the wire on the substrate.

18. The display panel according to any one of claims 1-17, wherein, The second organic insulating layer is located on the side of the electrode pattern layer facing away from the substrate, and the second organic insulating layer includes a plurality of openings configured to expose the plurality of pixel electrodes.

19. The display panel according to any one of claims 1-17, wherein, The second organic insulating layer is located on the side of the electrode pattern layer close to the substrate, and the second organic insulating layer has vias so that the pixel electrodes are connected to the pixel circuits through the vias.

20. A display device, comprising the display panel according to any one of claims 1-19.

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