Signal transmission circuit and electronic device

Abstract

A signal transmission circuit (20) and an electronic device (10), relating to the technical field of circuits. The signal transmission circuit (20) comprises a sending unit (210), a first receiving unit (220) and a second receiving unit (230). The sending unit (210) is connected to a preset node by means of a first wire group (240), the first receiving unit (220) is connected to the preset node by means of a second wire group (250), and the second receiving unit (230) is connected to the preset node by means of a third wire group (260). The impedance of the first receiving unit (220) and the impedance of the second receiving unit (230) are both greater than the impedance of the sending unit (210), the impedance of the second wire group (250) matches the impedance of the first receiving unit (220), and the impedance of the third wire group (260) matches the impedance of the second receiving unit (230), so as to improve the voltages of signals received by the first receiving unit (220) and the second receiving unit (230) that are connected in parallel, thereby improving the quality of the signals received by the first receiving unit (220) and the second receiving unit (230).

Description

Signal transmission circuits and electronic equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on September 27, 2023, with application number 202311281420.7 and application name “Signal Transmission Circuit and Electronic Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of circuit technology, and in particular to a signal transmission circuit and electronic equipment. Background Art

[0003] Electronic devices such as mobile phones, tablets, and laptops include a system-on-chip (SoC), a display driver chip, and a display screen. The display driver chip connects the SoC and the display screen, receiving data signals from the SoC and driving the display screen to display images.

[0004] In related technologies, to achieve high resolution and high refresh rate display screens, electronic devices may include two display driver chips. Both display driver chips are connected between the system-on-chip (SoC) and the display screen, and both display driver chips need to operate simultaneously to receive data signals output by the SoC and drive the display screen to display images.

[0005] However, when the SoC has only one signal output terminal for connecting to the display driver chip, both display driver chips need to be connected to the same node via the SoC's signal output terminal. In this case, the two display driver chips are connected in parallel, which results in a lower voltage for the data signal received by each display driver chip, affecting the quality of the data signal received by the display driver chips.

[0006] Summary of the Invention

[0007] The present application provides a signal transmission circuit and electronic device, which can improve the quality of the signal received by the display driver chip when the two display driver chips in the electronic device are connected in parallel. The technical solution is as follows:

[0008] In a first aspect, a signal transmission circuit is provided. The signal transmission circuit is applied to an electronic device and includes a transmitting unit, a first receiving unit, and a second receiving unit.

[0009] The transmitting unit has a signal output terminal for transmitting signals. The transmitting unit can be a system-on-chip in an electronic device, or an electrical component with a signal transmitting function composed of some electrical components in the system-on-chip. The first receiving unit and the second receiving unit each have an input terminal for receiving signals. The first receiving unit and the second receiving unit can be a display driver chip in an electronic device, or an electrical component with a signal receiving function composed of some electrical components in the display driver chip.

[0010] The signal output end of the sending unit is connected to the preset node through the first wire group, the input end of the first receiving unit is connected to the preset node through the second wire group, and the input end of the second receiving unit is connected to the preset node through the third wire group. That is to say, the input ends of the two receiving units and the output end of the sending unit are connected to one node, and the connection between the two receiving units is in parallel. Here, the impedance of the sending unit, the impedance of the first receiving unit and the impedance of the second receiving unit need to meet the following conditions: the impedance of the first receiving unit is greater than the impedance of the sending unit, and the impedance of the second receiving unit is greater than the impedance of the sending unit. In addition, the impedance of the second wire group needs to meet the following conditions: the difference between the impedance of the second wire group and the impedance of the first receiving unit is within the first impedance range. The impedance of the third wire group needs to meet the following conditions: the difference between the impedance of the third wire group and the impedance of the second receiving unit is within the second impedance range.

[0011] In the present application, a signal transmission circuit includes a transmitting unit, a first receiving unit, and a second receiving unit. The transmitting unit is connected to a preset node via a first wire group, the first receiving unit is connected to a preset node via a second wire group, and the second receiving unit is connected to a preset node via a third wire group, so that the transmitting unit can send signals to the first receiving unit and the second receiving unit. In an embodiment of the present application, the impedance of the first receiving unit and the impedance of the second receiving unit are both greater than the impedance of the transmitting unit. Since in the related art, the impedance of the first receiving unit, the impedance of the second receiving unit, and the impedance of the transmitting unit are all equal, the present application increases the voltage of the signal received by the first and second receiving units in parallel by increasing the impedance of the first receiving unit and the impedance of the second receiving unit, thereby improving the quality of the signal received by the first and second receiving units. In addition, the difference between the impedance of the second wire group and the impedance of the first receiving unit is within the first impedance range, so that the impedances of the connected second wire group and the first receiving unit are matched, which can avoid signal reflection when the signal is transmitted from the second wire group to the first receiving unit, thereby improving the quality of the signal received by the first receiving unit. Similarly, the difference between the impedance of the third wire group and the impedance of the second receiving unit is within the second impedance range, which can also achieve impedance matching between the connected third wire group and the second receiving unit, thereby improving the quality of the signal received by the second receiving unit.

[0012] In the signal transmission circuit provided in this application, the transmitting unit and the first receiving unit and the second receiving unit can be connected via an interface using the MIPI_D-PHY protocol or an interface using the MIPI_C-PHY protocol. These two situations are described below.

[0013] In the first case, the transmitting unit is connected to the first receiving unit and the second receiving unit via an interface using the MIPI_D-PHY protocol.

[0014] In this case, the transmitting unit may include a first impedance device and a second impedance device. The first receiving unit may include a third impedance device and a fourth impedance device. The second receiving unit may include a fifth impedance device and a sixth impedance device. The preset node may include a first node and a second node. The first wire group may include a first wire and a second wire. The second wire group may include a third wire and a fourth wire. The third wire group may include a fifth wire and a sixth wire.

[0015] The first end of the first impedance device is connectable to one of a preset voltage terminal and a ground line. The second end of the first impedance device is connected to the first node via a first conductor. The first end of the third impedance device is connected to the first node via a third conductor. The second end of the third impedance device is connected to the second end of the fourth impedance device. The first end of the fifth impedance device is connected to the first node via a fifth conductor. The second end of the fifth impedance device is connected to the second end of the sixth impedance device. The first end of the second impedance device is connectable to one of a preset voltage terminal and a ground line. The second end of the second impedance device is connected to the second node via a second conductor. The first end of the fourth impedance device is connected to the second node via a fourth conductor. The first end of the sixth impedance device is connected to the second node via a sixth conductor.

[0016] Based on this circuit structure, the impedance of the first receiving unit is greater than the impedance of the transmitting unit if the sum of the impedance of the third impedance device and the impedance of the fourth impedance device is greater than the sum of the impedance of the first impedance device and the impedance of the second impedance device. The impedance of the second receiving unit is greater than the impedance of the transmitting unit if the sum of the impedance of the fifth impedance device and the impedance of the sixth impedance device is greater than the sum of the impedance of the first impedance device and the impedance of the second impedance device.

[0017] In some embodiments, in the transmitting unit, the impedance of the first impedance device is equal to the impedance of the second impedance device. In the first receiving unit, the impedance of the third impedance device is equal to the impedance of the fourth impedance device. In the second receiving unit, the impedance of the fifth impedance device is equal to the impedance of the sixth impedance device. In this case, the impedance of the third impedance device = the impedance of the fourth impedance device > the impedance of the first impedance device = the impedance of the second impedance device; and the impedance of the fifth impedance device = the impedance of the sixth impedance device > the impedance of the first impedance device = the impedance of the second impedance device.

[0018] In some embodiments, the impedance of the third impedance device is greater than or equal to 1.2 times the impedance of the first impedance device, and less than or equal to 2 times the impedance of the first impedance device. The impedance of the fifth impedance device is also greater than or equal to 1.2 times the impedance of the first impedance device, and less than or equal to 2 times the impedance of the first impedance device. For example, if the impedance of the first impedance device is 50 ohms, the impedance of the third impedance device is between 60 ohms and 100 ohms (including the end value), and the impedance of the fifth impedance device is also between 60 ohms and 100 ohms (including the end value). In some specific embodiments, the impedance of the third impedance device and the impedance of the fifth impedance device are both twice the impedance of the first impedance device.

[0019] Based on this circuit structure, the first impedance range may include a first impedance sub-range and a second impedance sub-range, and the second impedance range may include a third impedance sub-range and a fourth impedance sub-range.

[0020] The difference between the impedance of the second conductor group and the impedance of the first receiving unit is within a first impedance range, which means that: the difference between the characteristic impedance of the third conductor and the impedance of the third impedance device is within the first impedance sub-range, and the difference between the characteristic impedance of the fourth conductor and the impedance of the fourth impedance device is within a second impedance sub-range. The minimum value of the first impedance sub-range is equal to the product of the impedance of the third impedance device and -10%, and the maximum value of the first impedance sub-range is equal to the product of the impedance of the third impedance device and 10%. The minimum value of the second impedance sub-range is equal to the product of the impedance of the fourth impedance device and -10%, and the maximum value of the second impedance sub-range is equal to the product of the impedance of the fourth impedance device and 10%.

[0021] The difference between the impedance of the third conductor group and the impedance of the second receiving unit is within the second impedance range, which means that: the difference between the characteristic impedance of the fifth conductor and the impedance of the fifth impedance device is within the third impedance sub-range, and the difference between the characteristic impedance of the sixth conductor and the impedance of the sixth impedance device is within the fourth impedance sub-range. The minimum value of the third impedance sub-range is equal to the product of the impedance of the fifth impedance device and -10%, and the maximum value of the third impedance sub-range is equal to the product of the impedance of the fifth impedance device and 10%. The minimum value of the fourth impedance sub-range is equal to the product of the impedance of the sixth impedance device and -10%, and the maximum value of the fourth impedance sub-range is equal to the product of the impedance of the sixth impedance device and 10%.

[0022] Based on this circuit structure, the difference between the impedance of the first wire group and the impedance of the transmitting unit is within a third impedance range. In other words, the impedances of the connected first wire group and the transmitting unit are matched.

[0023] Specifically, the third impedance range may include a fifth impedance sub-range and a sixth impedance sub-range. The difference between the impedance of the first conductor group and the impedance of the transmitting unit is within the third impedance range, which means that: the difference between the characteristic impedance of the first conductor and the impedance of the first impedance device is within the fifth impedance sub-range, and the difference between the characteristic impedance of the second conductor and the impedance of the second impedance device is within the sixth impedance sub-range. The minimum value of the fifth impedance sub-range is equal to the product of the impedance of the first impedance device and -10%, and the maximum value of the fifth impedance sub-range is equal to the product of the impedance of the first impedance device and 10%. The minimum value of the sixth impedance sub-range is equal to the product of the impedance of the second impedance device and -10%, and the maximum value of the sixth impedance sub-range is equal to the product of the impedance of the second impedance device and 10%.

[0024] As can be seen from the above description, the characteristic impedance of the first conductor is less than the characteristic impedance of the third conductor, and the characteristic impedance of the first conductor is less than the characteristic impedance of the fifth conductor. Based on this, on the printed circuit board of the electronic device, the width of the first conductor can be greater than the width of the third conductor, and the width of the first conductor can be greater than the width of the fifth conductor. Similarly, the characteristic impedance of the second conductor is less than the characteristic impedance of the fourth conductor, and the characteristic impedance of the second conductor is less than the characteristic impedance of the sixth conductor. Based on this, on the printed circuit board of the electronic device, the width of the second conductor can be greater than the width of the fourth conductor, and the width of the second conductor can be greater than the width of the sixth conductor.

[0025] In the second case, the transmitting unit is connected to the first receiving unit and the second receiving unit through an interface using the MIPI_C-PHY protocol.

[0026] In this case, the transmitting unit may include a first impedance device, a second impedance device, and a seventh impedance device. The first receiving unit may include a third impedance device, a fourth impedance device, and an eighth impedance device. The second receiving unit may include a fifth impedance device, a sixth impedance device, and a ninth impedance device. The preset node may include a first node, a second node, and a third node. The first wire group may include a first wire, a second wire, and a seventh wire. The second wire group may include a third wire, a fourth wire, and an eighth wire. The third wire group may include a fifth wire, a sixth wire, and a ninth wire.

[0027] The first end of the first impedance device is connectable to one of a preset voltage terminal and a ground line. The second end of the first impedance device is connected to the first node via a first conductor. The first end of the third impedance device is connected to the first node via a third conductor. The second end of the third impedance device is connected to the second end of the fourth impedance device and the second end of the eighth impedance device. The first end of the fifth impedance device is connected to the first node via a fifth conductor. The second end of the fifth impedance device is connected to the second end of the sixth impedance device and the second end of the ninth impedance device. The first end of the second impedance device is connectable to one of a preset voltage terminal and a ground line. The second end of the second impedance device is connected to the second node via a second conductor. The first end of the fourth impedance device is connected to the second node via a fourth conductor. The first end of the sixth impedance device is connected to the second node via a sixth conductor. The first end of the seventh impedance device is connectable to one of a preset voltage terminal and a ground line. The second end of the seventh impedance device is connected to the third node via a seventh conductor. The first end of the eighth impedance device is connected to the third node via an eighth conductor. The first end of the ninth impedance device is connected to the third node via a ninth conductor.

[0028] In some embodiments, in the transmitting unit, the impedance of the seventh impedance device, the impedance of the first impedance device, and the impedance of the second impedance device are all equal. In the first receiving unit, the impedance of the eighth impedance device, the impedance of the third impedance device, and the impedance of the fourth impedance device are all equal. In the second receiving unit, the impedance of the ninth impedance device, the impedance of the fifth impedance device, and the impedance of the sixth impedance device are all equal.

[0029] At the same time, the impedance of any impedance device in the first receiving unit is greater than the impedance of any impedance device in the sending unit, and the impedance of any impedance device in the second receiving unit is greater than the impedance of any impedance device in the sending unit.

[0030] In some embodiments, the impedance of the eighth impedance device is greater than or equal to 1.2 times the impedance of the seventh impedance device, and less than or equal to 2 times the impedance of the seventh impedance device. The impedance of the ninth impedance device is also greater than or equal to 1.2 times the impedance of the seventh impedance device, and less than or equal to 2 times the impedance of the seventh impedance device. For example, if the impedance of the seventh impedance device is 50 ohms, the impedance of the eighth impedance device is between 60 ohms and 100 ohms (including the end value), and the impedance of the ninth impedance device is also between 60 ohms and 100 ohms (including the end value). In some specific embodiments, the impedance of the eighth impedance device and the impedance of the ninth impedance device are both twice the impedance of the seventh impedance device.

[0031] Based on this circuit structure, the first impedance range may further include a seventh impedance sub-range, and the second impedance range may further include an eighth impedance sub-range.

[0032] The difference between the impedance of the second conductor group and the impedance of the first receiving unit is within the first impedance range, and the difference between the characteristic impedance of the eighth conductor and the impedance of the eighth impedance device is within a seventh impedance sub-range. The minimum value of the seventh impedance sub-range is equal to the product of the impedance of the eighth impedance device and -10%, and the maximum value of the seventh impedance sub-range is equal to the product of the impedance of the eighth impedance device and 10%.

[0033] The difference between the impedance of the third conductor group and the impedance of the second receiving unit is within the second impedance range, and the difference between the characteristic impedance of the ninth conductor and the impedance of the ninth impedance device is within an eighth impedance sub-range. The minimum value of the eighth impedance sub-range is equal to the product of the impedance of the ninth impedance device and -10%, and the maximum value of the eighth impedance sub-range is equal to the product of the impedance of the ninth impedance device and 10%.

[0034] Based on this circuit structure, the third impedance range may further include a ninth impedance sub-range. The difference between the impedance of the first conductor group and the impedance of the transmitting unit within the third impedance range also includes the difference between the characteristic impedance of the seventh conductor and the impedance of the seventh impedance device within the ninth impedance sub-range. The minimum value of the ninth impedance sub-range is equal to the product of the impedance of the seventh impedance device and -10%, and the maximum value of the ninth impedance sub-range is equal to the product of the impedance of the seventh impedance device and 10%.

[0035] In a second aspect, an electronic device is also provided, comprising a signal transmission circuit as described in any one of the first aspects.

[0036] The technical effect obtained by the above-mentioned second aspect is similar to the technical effect obtained by the corresponding technical means in the above-mentioned first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] FIG1 is a schematic diagram of the appearance of a first electronic device in the related art;

[0038] FIG2 is a schematic diagram of the appearance of a second electronic device in the related art;

[0039] FIG3 is a schematic diagram of the internal structure of a first electronic device in the related art;

[0040] FIG4 is a schematic diagram of the internal structure of a second electronic device in the related art;

[0041] FIG5 is a schematic structural diagram of a first signal transmission circuit in the related art;

[0042] FIG6 is a schematic diagram of a first data transmission process from an SOC to a DDIC in the related art;

[0043] FIG7 is a schematic diagram of the internal structure of a third electronic device in the related art;

[0044] FIG8 is a schematic structural diagram of a second signal transmission circuit in the related art;

[0045] FIG9 is a schematic diagram of a second data transmission process from an SOC to a DDIC in the related art;

[0046] FIG10 is a simulation circuit diagram of a first signal transmission circuit in the related art;

[0047] FIG11 is a circuit diagram of a first signal transmission circuit in the related art;

[0048] FIG12 is a simulation circuit diagram of a second signal transmission circuit in the related art;

[0049] FIG13 is a circuit diagram of a third signal transmission circuit in the related art;

[0050] 14 is a circuit diagram of a fourth signal transmission circuit in the related art;

[0051] FIG15 is a circuit diagram of a fifth signal transmission circuit in the related art;

[0052] 16 is a diagram showing impedance test results of a simulation circuit of a signal transmission circuit in the related art;

[0053] FIG17 is an eye diagram of the signal transmission circuit shown in FIG11 when performing signal transmission;

[0054] FIG18 is an eye diagram of the signal transmission circuit shown in FIG13 when performing signal transmission;

[0055] FIG19 is a schematic structural diagram of a signal transmission circuit provided in an embodiment of the present application;

[0056] FIG20 is a circuit structure diagram of a first signal transmission circuit provided in an embodiment of the present application;

[0057] FIG21 is an impedance diagram of a first signal transmission circuit provided in an embodiment of the present application;

[0058] FIG22 is a schematic diagram of wires in a first signal transmission circuit provided in an embodiment of the present application;

[0059] FIG23 is an eye diagram of the first signal transmission circuit provided in an embodiment of the present application when performing signal transmission;

[0060] FIG24 is an eye diagram of a second signal transmission circuit according to an embodiment of the present application when performing signal transmission;

[0061] FIG25 is an eye diagram of a third signal transmission circuit according to an embodiment of the present application when performing signal transmission;

[0062] FIG26 is an eye diagram of a fourth signal transmission circuit according to an embodiment of the present application when performing signal transmission;

[0063] FIG27 is an eye diagram of a fifth signal transmission circuit according to an embodiment of the present application when performing signal transmission;

[0064] FIG28 is an eye diagram of a sixth signal transmission circuit according to an embodiment of the present application when performing signal transmission;

[0065] FIG29 is a circuit structure diagram of a second signal transmission circuit provided in an embodiment of the present application;

[0066] FIG30 is an impedance diagram of a second signal transmission circuit provided in an embodiment of the present application;

[0067] FIG31 is a schematic diagram of wires in a second signal transmission circuit provided in an embodiment of the present application;

[0068] Figure 32 is a circuit structure diagram of the third signal transmission circuit provided in an embodiment of the present application.

[0069] The meanings of the figures are as follows:

[0070] Related technologies:

[0071] 10. Electronic device; 102. Total data signal; 1022. First data signal; 1023. First decompressed signal; 1024. Second data signal; 1025. Second decompressed signal; 12. Signal transmission circuit; 110. Display device; 112. Display screen;

[0072] This application:

[0073] 20. Signal transmission circuit; 210. Transmitting unit; 212. First impedance device; 214. Second impedance device; 216. Seventh impedance device; 220. First receiving unit; 222. Third impedance device; 224. Fourth impedance device; 226. Eighth impedance device; 230. Second receiving unit; 232. Fifth impedance device; 234. Sixth impedance device; 236. Ninth impedance device; 240. First conductor group; 242. First conductor; 244. Second conductor; 246. Seventh conductor; 250. Second conductor group; 252. Third conductor; 254. Fourth conductor; 256. Eighth conductor; 260. Third conductor group; 262. Fifth conductor; 264. Sixth conductor; 266. Ninth conductor. DETAILED DESCRIPTION

[0074] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0075] It should be understood that the “multiple” mentioned in this application refers to two or more. In the description of this application, unless otherwise specified, “ / ” means or, for example, A / B can mean A or B; “and / or” in this article is merely a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in order to facilitate the clear description of the technical solution of this application, words such as “first” and “second” are used to distinguish between identical or similar items with basically the same functions and effects. Those skilled in the art can understand that words such as “first” and “second” do not limit the quantity and execution order, and words such as “first” and “second” do not necessarily limit them to be different.

[0076] Before explaining the signal transmission circuit provided in the embodiments of the present application in detail, the application scenarios and related technologies of the signal transmission circuit are first explained.

[0077] Electronic devices include mobile phones, tablet computers, and laptop computers. Figures 1 and 2 illustrate the appearance of two different electronic devices 10 in the related art. In the embodiment shown in Figure 1, electronic device 10 is a mobile phone, while in the embodiment shown in Figure 2, electronic device 10 is a tablet computer. As shown in Figures 1 and 2, electronic device 10 has a display screen 112 for displaying images.

[0078] FIG3 is a schematic diagram of the internal structure of an electronic device 10 in the related art. As shown in FIG3 , the electronic device 10 includes a system on chip (SOC) and a display device 110. The display device 110 includes a display driver integrated circuit (DDIC) and a display screen 112. The DDIC is connected between the SOC and the display screen 112. When the electronic device 10 is in operation, the DDIC can receive the data signal output by the SOC and decompress the data signal to obtain a decompressed signal. The DDIC can also drive the display screen 112 based on the decompressed signal to display an image.

[0079] At present, the mobile industry processor interface (MIPI) protocol is a high-speed digital transmission protocol, which is usually used in the connection between the display device 110, camera and other devices of the electronic device 10 and the SOC. In the MIPI protocol, the display serial interface (DSI) protocol is an interface standard designed for the display device 110, which adopts the D-physical layer (PHY) or C-PHY underlying transmission protocol. That is to say, in the related art, the MIPI_D-PHY protocol or MIPI_C-PHY protocol is used to transmit communication signals between the SOC and the DDIC of the display device 110. Among them, the interface using the MIPI_D-PHY protocol consists of 1 group of clock differential lines and 4 groups of data differential lines, the clock differential line is used to transmit the clock signal, and the data differential line is used to transmit the data signal; the interface using the MIPI_C-PHY protocol consists of three groups of signal lines, each group of signal lines includes three signal lines, and the three signal lines in each group of signal lines are used to transmit clock signals and data signals.

[0080] In related art, to achieve high resolution and high refresh rate features on the display screen 112 of an electronic device 10, such as a mobile phone or tablet computer, the entire signal transmission link must be able to support sufficient data bandwidth. For example, if the display screen 112 of the electronic device 10 needs to achieve a 2K resolution and a 120Hz refresh rate, the entire signal transmission link must be able to support a data bandwidth of 8.29Gbps ​​(gigabits per second).

[0081] However, due to factors such as the design cost and resources of the electronic device 10, the DDIC of the electronic device 10 often only supports the V1.1 standard of the MIPI_D-PHY protocol or the V1.0 standard of the MIPI_C-PHY protocol. Among them, for the V1.1 standard of the MIPI_D-PHY protocol, the maximum transmission rate of each group of data differential lines is 1.2 Gbps. Therefore, the maximum transmission rate of the interface using the MIPI_D-PHY protocol with 4 groups of data differential lines is 4.8 Gbps, which does not reach 8.29 Gbps. For the V1.0 standard of the MIPI_C-PHY protocol, the maximum transmission rate of each group of signal lines is 1.1 Gsps (gigabyte symbols per second), which is about 2.5 Gbps. Therefore, the maximum transmission rate of the interface using the MIPI_C-PHY protocol with three groups of signal lines is 7.5 Gbps, which also does not reach 8.29 Gbps. Based on this, in this case, in order for the display screen 112 to achieve a 2K resolution and a 120Hz refresh rate, two DDICs need to be provided in the electronic device 10. Both DDICs are connected between the SOC and the display screen 112, and both DDICs need to work simultaneously to jointly receive the data signal output by the SOC and drive the display screen 112 to display images.

[0082] However, in the related art, the SOC may have two signal output terminals for connecting to the DDIC, or may have only one signal output terminal for connecting to the DDIC. When the SOC has two signal output terminals for connecting to the DDIC, the internal structure diagram of the electronic device 10 can be as shown in Figure 4. In this case, the signal transmission link from the SOC to the DDIC inside the electronic device 10 (hereinafter referred to as the "signal transmission circuit 12") can be as shown in Figure 5, and the data transmission process from the SOC to the DDIC can be as shown in Figure 6. Referring to Figures 4 to 6, it can be seen that the SOC has two signal output terminals, namely the signal output terminal P1 and the signal output terminal P2; the electronic device 10 has two DDICs, namely DDIC1 and DDIC2. Among them, DDIC1 is connected between the signal output terminal P1 of the SOC and the display screen 112, and DDIC2 is connected between the signal output terminal P2 of the SOC and the display screen 112. When the electronic device 10 is working, the signal output terminal P1 of the SOC is used to output the first data signal 1022 to DDIC1. After receiving first data signal 1022, DDIC1 can decompress first data signal 1022 to obtain first decompressed signal 1023. DDIC1 is further configured to drive the upper or left half of display screen 112 based on first decompressed signal 1023. Signal output terminal P2 of the SOC is configured to output second data signal 1024 to DDIC2. After receiving second data signal 1024, DDIC2 can decompress second data signal 1024 to obtain second decompressed signal 1025. DDIC2 is further configured to drive the lower or right half of display screen 112 based on second decompressed signal 1025.

[0083] When the SOC has only one signal output terminal for connecting to a DDIC, the internal structure of electronic device 10 can be shown in Figure 7. In this case, signal transmission circuit 12 can be shown in Figure 8, and the data transmission process from the SOC to the DDIC can be shown in Figure 9. As shown in Figures 7 to 9, the SOC has only one signal output terminal P0; electronic device 10 has two DDICs, namely DDIC1 and DDIC2. Both DDIC1 and DDIC2 are connected between the SOC's signal output terminal P0 and the display screen 112. When electronic device 10 is in operation, the SOC's signal output terminal P0 is used to output a total data signal 102 to DDIC1 and DDIC2. Total data signal 102 includes a first data signal 1022 and a second data signal 1024. After receiving total data signal 102, DDIC1 decompresses only first data signal 1022 to obtain a first decompressed signal 1023. DDIC1 is also used to drive the top or left half of the display screen 112 based on first decompressed signal 1023. After receiving the total data signal 102, DDIC2 decompresses only the second data signal 1024 to obtain a second decompressed signal 1025. DDIC2 is further configured to drive the lower half or right half of the display screen 112 to operate according to the second decompressed signal 1025.

[0084] Regarding the situations shown in Figures 7 to 9, the problem with the related art is that, because both DDIC1 and DDIC2 need to be connected to the signal output terminal P0 of the SOC, DDIC1 and DDIC2 are connected in parallel. In this case, due to the parallel voltage division effect, the voltage of the data signal received by each DDIC (including DDIC1 and DDIC2) will become smaller, thereby affecting the quality of the data signal received by the DDIC.

[0085] The following is a detailed explanation of the problems existing in the above-mentioned related technologies for interfaces using the MIPI_D-PHY protocol and interfaces using the MIPI_C-PHY protocol.

[0086] 1. In the first case, the SOC and DDIC are connected via an interface using the MIPI_D-PHY protocol. In this case, when the signal output terminal P0 of the SOC is connected to only one DDIC, the simulation circuit diagram of the signal transmission circuit 12 can be shown in Figure 10. Referring to Figure 10, the SOC includes five transmitting units TX, namely TX1, TX2, TX3, TX4, and TX5. One of the five transmitting units TX is used to transmit a clock signal, and the other four are used to transmit data signals. The DDIC includes five receiving units RX, namely RX1, RX2, RX3, RX4, and RX5. Similarly, one of the five receiving units RX is used to receive a clock signal, and the other four are used to receive data signals. Based on the simulation circuit shown in Figure 10, the circuit diagram of the signal transmission circuit 12 formed by any transmitting unit TX and the corresponding connected receiving unit RX can be shown in Figure 11. Referring to Figure 11, the transmitting unit TX includes a resistor Rp and a resistor Rn. The first end of the resistor Rp is used to connect to the common voltage terminal VCOM or the ground line GND, and the second end of the resistor Rp is connected to the first sub-port P01. The first end of resistor Rn is connected to the common voltage terminal VCOM or ground GND, and the second end of resistor Rn is connected to the second sub-port P02. The signal output terminal P0 of the SOC has multiple sub-ports, and the first sub-port P01 and the second sub-port P02 are both sub-ports of the signal output terminal P0 of the SOC. The receiving unit RX includes resistors RL1 and RL2. The first end of resistor RL1 is connected to the first sub-port P01, the second end of resistor RL1 is connected to the second end of resistor RL2, and the first end of resistor RL2 is connected to the second sub-port P02.

[0087] In the signal transmission circuit 12, the impedances of resistors Rp, Rn, RL1, and RL2 are all 50Ω. When the signal transmission circuit 12 is operating, if the first end of resistor Rp is connected to the common voltage terminal VCOM, then the first end of resistor Rn is connected to the ground line GND. For example, if the voltage at the common voltage terminal VCOM is 400 mV (millivolts), the voltage difference between the first end of resistor RL1 and the first end of resistor RL2 is:

[0088] Among them, V RX is the voltage of the signal received by the receiving unit RX, V com is the voltage of the common voltage terminal VCOM, R L1 is the impedance of resistor RL1, R L2 is the impedance of resistor RL2, R p is the impedance of resistor Rp, R nis the impedance of resistor Rn. That is, at this point, the voltage difference between the first end of resistor RL1 and the first end of resistor RL2 is 200 mV, and the voltage at the first end of resistor RL1 is greater than the voltage at the first end of resistor RL2. In this case, the voltage of the signal received by receiving unit RX is +200 mV, the first end of resistor RL1 receives a high-level signal, and the first end of resistor RL2 receives a low-level signal.

[0089] Conversely, when the signal transmission circuit 12 is operating, if the first end of the resistor Rp is connected to the ground line GND, then the first end of the resistor Rn is connected to the common voltage terminal VCOM. For example, if the voltage at the common voltage terminal VCOM is 400 mV (millivolts), then the voltage difference between the first end of the resistor RL1 and the first end of the resistor RL2 is 200 mV, and the voltage at the first end of the resistor RL1 is less than the voltage at the first end of the resistor RL2. In this case, the voltage of the signal received by the receiving unit RX is -200 mV, the first end of the resistor RL1 receives a low-level signal, and the first end of the resistor RL2 receives a high-level signal.

[0090] However, when the signal output terminal P0 of the SOC is connected to two DDICs, the simulation circuit diagram of the signal transmission circuit 12 can be shown in Figure 12. Referring to Figure 12, the SOC includes five transmitting units TX, namely TX1, TX2, TX3, TX4, and TX5. One of the five transmitting units TX is used to transmit a clock signal, and the other four are used to transmit data signals. DDIC1 includes five receiving units RXA, namely RXA1, RXA2, RXA3, RXA4, and RXA5. One of the five receiving units RXA is used to receive a clock signal, and the other four are used to receive data signals. DDIC2 also includes five receiving units RXB, namely RXB1, RXB2, RXB3, RXB4, and RXB5. Each transmitting unit TX is connected to a receiving unit RXA in DDIC1 and to a receiving unit RXB in DDIC2. Based on the simulation circuit shown in Figure 12, the circuit diagram of the signal transmission circuit 12 formed by any transmitting unit TX and the corresponding two connected receiving units RX can be shown in Figure 13. Referring to Figure 13, the transmitting unit TX includes a resistor Rp and a resistor Rn. The first end of the resistor Rp is used to connect to the common voltage terminal VCOM or the ground line GND, and the second end of the resistor Rp is connected to the first sub-port P01. The first end of the resistor Rn is used to connect to the common voltage terminal VCOM or the ground line GND, and the second end of the resistor Rn is connected to the second sub-port P02. Among them, the signal output terminal P0 of the SOC has multiple sub-ports, and the first sub-port P01 and the second sub-port P02 are both sub-ports of the signal output terminal P0 of the SOC. The receiving unit RXA in DDIC1 includes a resistor RL1 and a resistor RL2. The first end of the resistor RL1 is used to connect to the first sub-port P01, the second end of the resistor RL1 is connected to the second end of the resistor RL2, and the first end of the resistor RL2 is used to connect to the second sub-port P02. The receiving unit RXB in DDIC2 includes a resistor RL3 and a resistor RL4. The first end of resistor RL3 is connected to the first sub-port P01, the second end of resistor RL3 is connected to the second end of resistor RL4, and the first end of resistor RL4 is connected to the second sub-port P02. The node where the first end of resistor RL1, the first sub-port P01, and the first end of resistor RL3 are connected is called node 1, and the node where the first end of resistor RL2, the second sub-port P02, and the first end of resistor RL4 are connected is called node 2.

[0091] In the signal transmission circuit 12, the impedances of the resistors Rp, Rn, RL1, RL2, RL3, and RL4 are all 50Ω. Therefore, the impedance between node 1 and node 2 is:

[0092] Where R is the impedance between node 1 and node 2, R L3 is the impedance of resistor RL3, RL4 is the impedance of resistor RL4.

[0093] When the signal transmission circuit 12 is operating, if the first end of the resistor Rp is connected to the common voltage terminal VCOM, then the first end of the resistor Rn is connected to the ground line GND. For example, if the voltage of the common voltage terminal VCOM is 400 mV (millivolts), the voltage difference between the node 1 and the node 2 at this time can be obtained as:

[0094] Among them, V 12 is the voltage difference between node 1 and node 2. That is, at this time, the voltage difference between node 1 and node 2 is 133 mV, and the voltage at node 1 is greater than the voltage at node 2. In this case, the voltage of the signals received by receiving unit RXA and receiving unit RXB are both +133 mV, the first end of resistor RL1 and the first end of resistor RL3 both receive high-level signals, and the first end of resistor RL2 and the first end of resistor RL4 both receive low-level signals.

[0095] Conversely, when signal transmission circuit 12 is operating, if the first end of resistor Rp is connected to ground GND, then the first end of resistor Rn is connected to the common voltage terminal VCOM. For example, if the voltage at common voltage terminal VCOM is 400 mV (millivolts), the voltage difference between node 1 and node 2 is 133 mV, and the voltage at node 1 is less than the voltage at node 2. In this case, the voltage of the signals received by receiving unit RXA and receiving unit RXB is both -133 mV. The first ends of resistors RL1 and RL3 both receive low-level signals, while the first ends of resistors RL2 and RL4 both receive high-level signals.

[0096] From the above analysis, it can be seen that for an interface using the MIPI_D-PHY protocol, when the SOC's signal output terminal P0 is connected to only one DDIC, the voltage of the signal received by each receiving unit RX in the DDIC is ±200mV; when the SOC's signal output terminal P0 is connected to two DDICs, the voltage of the signal received by each receiving unit RX in the DDIC is ±133mV. Compared to the case where the signal output terminal P0 is connected to only one DDIC, when the signal output terminal P0 is connected to two DDICs, the attenuation of the signal received by each receiving unit RX in the DDIC is 20 times lg (133 / 200), where "lg" refers to the logarithm with base 10, which is approximately -3.5dB (decibels). It can be understood that for the simulation circuit of the signal transmission circuit 12 shown in Figures 10 or 12, the voltage of the signal received by any two receiving units RX in each DDIC is the same and does not affect each other. Therefore, in the following description, "the voltage of the signal received by each receiving unit RX in the DDIC" will also be referred to as "the voltage of the signal received by the DDIC."

[0097] 2. In the second scenario, the SOC and DDIC are connected via an interface using the MIPI_C-PHY protocol. In this case, when the SOC's signal output terminal P0 is connected to only one DDIC, the circuit diagram of the signal transmission circuit 12 can be as shown in Figure 14, which shows only one set of signal lines. Referring to Figure 14, the SOC includes resistors Ra, Rb, and Rc. The SOC also includes resistors Rpu_ta, Rpd_ta, Rpu_tb, Rpd_tb, Rpu_tc, and Rpd_tc.

[0098] The first end of resistor Ra is connected to the common voltage terminal VCOM or ground line GND, and the second end of resistor Ra is connected to the first sub-port P01. The first end of resistor Rb is connected to the common voltage terminal VCOM or ground line GND, and the second end of resistor Rb is connected to the second sub-port P02. The first end of resistor Rc is connected to the common voltage terminal VCOM or ground line GND, and the second end of resistor Rc is connected to the third sub-port P03. The signal output terminal P0 of the SOC has multiple sub-ports, and the first sub-port P01, the second sub-port P02, and the third sub-port P03 are each one of the sub-ports of the signal output terminal P0 of the SOC. The receiving unit RX includes resistors RM1, RM2, and RM3. The first end of resistor RM1 is connected to the first sub-port P01, the first end of resistor RM2 is connected to the second sub-port P02, and the first end of resistor RM3 is connected to the third sub-port P03. The second end of resistor RM1, the second end of resistor RM2, and the second end of resistor RM3 are connected together.

[0099] Resistors Rpu_ta and Rpd_ta are connected in series between the common voltage terminal VCOM and the ground line GND via switches K1 and K2. The second end of resistor Rpu_ta and the first end of resistor Rpd_ta are both connected to the first sub-port P01. Resistors Rpu_tb and Rpd_tb are connected in series between the common voltage terminal VCOM and the ground line GND via switches K3 and K4. The second end of resistor Rpu_tb and the first end of resistor Rpd_tb are both connected to the second sub-port P02. Resistors Rpu_tc and Rpd_tc are connected in series between the common voltage terminal VCOM and the ground line GND via switches K5 and K6. The second end of resistor Rpu_tc and the first end of resistor Rpd_tc are both connected to the third sub-port P03.

[0100] In the signal transmission circuit 12, the impedances of the resistors Ra, Rb, Rc, RM1, RM2, and RM3 are all 50Ω. The impedances of the resistors Rpu_ta, Rpd_ta, Rpu_tb, Rpd_tb, Rpu_tc, and Rpd_tc are all 100Ω. When the signal transmission circuit 12 is operating, at the same time, one of the three sub-ports of the signal output terminal P0 of the SOC outputs a high-level signal, another outputs a low-level signal, and another outputs an intermediate-level signal, the voltage of the intermediate-level signal being between the voltage of the high-level signal and the voltage of the low-level signal. Taking the voltage of the common voltage terminal VCOM as 400mV as an example, the working process of the signal transmission circuit 12 can specifically include the following six situations:

[0101] (1) The first end of resistor Ra is connected to the common voltage terminal VCOM, and the first end of resistor Rb is connected to the ground line GND. Resistor Rc is neither connected to the common voltage terminal VCOM nor to the ground line GND. Switches K5 and K6 are closed, and switches K1, K2, K3, and K4 are all turned off. In this case, the first end of resistor RM1 receives a high-level signal, the first end of resistor RM2 receives a low-level signal, and the first end of resistor RM3 receives an intermediate-level signal. The difference between the voltage of the high-level signal and the voltage of the intermediate-level signal is 100 mV, the difference between the voltage of the intermediate-level signal and the voltage of the low-level signal is 100 mV, and the difference between the voltage of the high-level signal and the voltage of the low-level signal is 200 mV.

[0102] (2) The first end of resistor Ra is connected to the ground line GND, and the first end of resistor Rb is connected to the common voltage terminal VCOM. Resistor Rc is neither connected to the common voltage terminal VCOM nor to the ground line GND. Switches K5 and K6 are closed, and switches K1, K2, K3, and K4 are all turned off. In this case, the first end of resistor RM1 receives a low-level signal, the first end of resistor RM2 receives a high-level signal, and the first end of resistor RM3 receives an intermediate-level signal. The difference between the voltage of the high-level signal and the voltage of the intermediate-level signal is 100 mV, the difference between the voltage of the intermediate-level signal and the voltage of the low-level signal is 100 mV, and the difference between the voltage of the high-level signal and the voltage of the low-level signal is 200 mV.

[0103] (3) The first end of resistor Ra is connected to the common voltage terminal VCOM, and the first end of resistor Rc is connected to the ground line GND. Resistor Rb is neither connected to the common voltage terminal VCOM nor to the ground line GND. Switches K3 and K4 are closed, and switches K1, K2, K5, and K6 are all turned off. In this case, the first end of resistor RM1 receives a high-level signal, the first end of resistor RM3 receives a low-level signal, and the first end of resistor RM2 receives an intermediate-level signal. The difference between the voltage of the high-level signal and the voltage of the intermediate-level signal is 100 mV, the difference between the voltage of the intermediate-level signal and the voltage of the low-level signal is 100 mV, and the difference between the voltage of the high-level signal and the voltage of the low-level signal is 200 mV.

[0104] (4) The first end of the resistor Ra is connected to the ground line GND, and the first end of the resistor Rc is connected to the common voltage terminal VCOM. The resistor Rb is neither connected to the common voltage terminal VCOM nor to the ground line GND. Switches K3 and K4 are closed, and switches K1, K2, K5, and K6 are all turned off. In this case, the first end of the resistor RM1 receives a low-level signal, the first end of the resistor RM3 receives a high-level signal, and the first end of the resistor RM2 receives an intermediate-level signal. The difference between the voltage of the high-level signal and the voltage of the intermediate-level signal is 100 mV, the difference between the voltage of the intermediate-level signal and the voltage of the low-level signal is 100 mV, and the difference between the voltage of the high-level signal and the voltage of the low-level signal is 200 mV.

[0105] (5) The first end of resistor Rb is connected to the common voltage terminal VCOM, and the first end of resistor Rc is connected to the ground line GND. Resistor Ra is neither connected to the common voltage terminal VCOM nor to the ground line GND. Switches K1 and K2 are closed, and switches K3, K4, K5, and K6 are all turned off. In this case, the first end of resistor RM1 receives an intermediate level signal, the first end of resistor RM3 receives a low level signal, and the first end of resistor RM2 receives a high level signal. The difference between the voltage of the high level signal and the voltage of the intermediate level signal is 100mV, the difference between the voltage of the intermediate level signal and the voltage of the low level signal is 100mV, and the difference between the voltage of the high level signal and the voltage of the low level signal is 200mV.

[0106] (6) The first end of resistor Rb is connected to the ground line GND, and the first end of resistor Rc is connected to the common voltage terminal VCOM. Resistor Ra is neither connected to the common voltage terminal VCOM nor to the ground line GND. Switches K1 and K2 are closed, and switches K3, K4, K5, and K6 are all turned off. In this case, the first end of resistor RM1 receives an intermediate level signal, the first end of resistor RM3 receives a high level signal, and the first end of resistor RM2 receives a low level signal. The difference between the voltage of the high level signal and the voltage of the intermediate level signal is 100 mV, the difference between the voltage of the intermediate level signal and the voltage of the low level signal is 100 mV, and the difference between the voltage of the high level signal and the voltage of the low level signal is 200 mV.

[0107] However, when the signal output terminal P0 of the SOC is connected to two DDICs, the circuit diagram of the signal transmission circuit 12 can be as shown in Figure 15. Referring to Figure 15, DDIC1 includes resistors RM1, RM2, and RM3, and DDIC2 includes resistors RM4, RM5, and RM6. The first end of resistor RM1 and the first end of resistor RM4 are both used to connect to the first sub-port P01, the first end of resistor RM2 and the first end of resistor RM5 are used to connect to the second sub-port P02, and the first end of resistor RM3 and the first end of resistor RM6 are both used to connect to the third sub-port P03. The second end of resistor RM1, the second end of resistor RM2, and the second end of resistor RM3 are connected together. The second end of resistor RM4, the second end of resistor RM5, and the second end of resistor RM6 are connected together.

[0108] In the signal transmission circuit 12, the impedances of resistors RM1, RM2, RM3, RM4, RM5, and RM6 are all 50Ω. The operating process of the signal transmission circuit 12 remains unchanged. According to the above analysis, when the voltage of the common voltage terminal VCOM is 400mV and the signal output terminal P0 of the SOC is connected to two DDICs, the difference between the voltage of the high-level signal and the voltage of the intermediate-level signal is 66.5mV. Compared to the case where the signal output terminal P0 is connected to only one DDIC, the attenuation amplitude of the signal received by the DDIC is 20 times lg (66.5 / 100), which is approximately -3.5dB. Similarly, when the signal output terminal P0 of the SOC is connected to two DDICs, the difference between the voltage of the intermediate-level signal and the voltage of the low-level signal is also 66.5mV. Compared to the case where the signal output terminal P0 is connected to only one DDIC, the attenuation amplitude of the signal received by the DDIC is also approximately -3.5dB. When the SOC's signal output terminal P0 is connected to two DDICs, the voltage difference between the high-level signal and the low-level signal is 133mV. Compared with the case where the signal output terminal P0 is connected to only one DDIC, the attenuation amplitude of the signal received by the DDIC is also about -3.5dB.

[0109] To this end, an embodiment of the present application provides a signal transmission circuit 12 and an electronic device 10, which can improve the quality of the data signal received by the DDIC when the signal output end of the SOC in the electronic device 10 is connected to two DDICs, that is, when the connection between the two DDICs is in parallel.

[0110] Before providing a detailed explanation of the signal transmission circuit provided in the embodiments of this application, it is important to note that in the two aforementioned scenarios, the conclusions obtained that "when the SOC's signal output terminal P0 is connected to only one DDIC, the voltage of the signal received by the DDIC is ±200mV; when the SOC's signal output terminal P0 is connected to two DDICs, the voltage of the signal received by the DDIC is ±133mV" are merely theoretical calculation results. In actual applications, considering the inevitable losses during signal transmission, when the SOC's signal output terminal P0 is connected to only one DDIC, the voltage of the signal received by the DDIC is inevitably less than 200mV; when the SOC's signal output terminal P0 is connected to two DDICs, the voltage of the signal received by the DDIC is also inevitably less than 133mV.

[0111] For example, in a specific embodiment, taking the impedance of each resistor in the signal transmission circuit 12 shown in FIG13 as 50Ω, the circuit diagram of the signal transmission circuit 12 shown in FIG13 is simulated, and the impedance test of the simulated circuit is performed. The results are shown in FIG16. As can be seen from FIG16, before node 1, that is, on the side of node 1 close to resistor Rp, the impedance of the signal transmission circuit 12 is 50Ω; after node 1, that is, on the side of node 1 close to resistor RL1, the impedance of the signal transmission circuit 12 drops sharply to 25Ω. In other words, there is a large impedance jump at the location of parallel node 1, which can affect the quality of signal transmission.

[0112] Taking the transmission rate of each set of data differential lines as 1 Gbps and the total length of each set of data differential lines as 245 mm (millimeter) as an example to simulate the signal loss of an actual electronic device 10, the waveform of the signal transmission circuit 12 shown in Figure 11 during signal transmission was displayed using an oscilloscope, and the resulting eye diagram is shown in Figure 17. In the eye diagram, the ordinate represents the signal voltage, in V (volts); the abscissa represents time. As shown in Figure 17, when the signal output terminal P0 of the SOC is connected to only one DDIC, the voltage of the signal actually received by the DDIC is ±165 mV. The waveform of the signal transmission circuit 12 shown in Figure 13 during signal transmission was displayed using an oscilloscope, and the resulting eye diagram is shown in Figure 18. As shown in Figure 18, when the signal output terminal of the SOC is connected to two DDICs, the voltage of the signal actually received by each DDIC is ±110 mV. This shows that the attenuation of the signal received by the DDIC is approximately -3.5 dB.

[0113] The signal transmission circuit provided in the embodiments of the present application is explained in detail below. In each embodiment of the present application, the connection between any electrical unit or electronic device refers to an electrical connection. The electrical connection here refers to a connection through a wire so that electrical signals can be transmitted between two electrical units or / and electronic devices. The connection between two electrical units or electronic devices can be a direct connection or an indirect connection through other electrical units or / and electronic devices.

[0114] Figure 19 is a structural diagram of a signal transmission circuit 20 provided in an embodiment of the present application. The signal transmission circuit 20 is applicable to the electronic device shown in Figure 7, that is, it is applicable to the electronic device in which "DDIC1 and DDIC2 both need to be connected to the signal output terminal P0 of the SOC". The signal transmission circuit 20 is applicable to both the case where the SOC and DDIC (including DDIC1 and DDIC2) are connected through an interface using the MIPI_D-PHY protocol, and the case where the SOC and DDIC are connected through an interface using the MIPI_C-PHY protocol. As shown in Figure 19, the signal transmission circuit 20 includes a sending unit 210, a first receiving unit 220, a second receiving unit 230, a first wire group 240, a second wire group 250 and a third wire group 260.

[0115] The transmitting unit 210 is an electrical unit for transmitting signals, where the signals may be data signals and / or clock signals. The transmitting unit 210 may be a system-on-chip (SOC) in an electronic device, or an electrical component with signal transmission functionality comprised of some electrical components in the SOC (e.g., any transmitting unit TX in the simulation circuit shown in FIG12 ). The transmitting unit 210 has a signal output terminal P0 for transmitting signals.

[0116] The first receiving unit 220 is an electrical unit for receiving signals transmitted by the transmitting unit 210. The first receiving unit 220 can be a DDIC in an electronic device, or an electrical component with a signal receiving function composed of some electrical components in the DDIC (such as any receiving unit RXA in the simulation circuit shown in FIG12 ). The first receiving unit 220 has an input terminal Q1 for receiving signals.

[0117] The second receiving unit 230 is also an electrical unit for receiving signals sent by the transmitting unit 210. The second receiving unit 230 can be a DDIC in an electronic device, or an electrical component with signal receiving functionality comprised of some electrical components in the DDIC (such as any receiving unit RXB in the simulation circuit shown in FIG12 ). The second receiving unit 230 has an input terminal Q2 for receiving signals.

[0118] In the embodiment of the present application, the signal output terminal P0 of the transmitting unit 210, the input terminal Q1 of the first receiving unit 220, and the input terminal Q2 of the second receiving unit 230 are all connected to the same node. For ease of description, this node is referred to as the "preset node Y." In other words, the signal output terminal P0 of the transmitting unit 210, the input terminal Q1 of the first receiving unit 220, and the input terminal Q2 of the second receiving unit 230 are all connected to the preset node Y, so that the first receiving unit 220 and the second receiving unit 230 can both receive the signal sent by the transmitting unit 210.

[0119] The signal output terminal P0 of the transmitting unit 210 is connected to the preset node Y via the first wire group 240. The first wire group 240 may include one or more wires, where "a plurality" refers to two or more integers. Specifically, the signal output terminal P0 of the transmitting unit 210 may include only one subport or multiple subports that are independent of each other. The preset node Y may include only one subnode or multiple subnodes that are independent of each other. Generally, the number of subports included in the signal output terminal P0 of the transmitting unit 210 is equal to the number of subnodes included in the preset node Y, and each subport in the signal output terminal P0 of the transmitting unit 210 needs to be connected to a subnode in the preset node Y via a wire. Based on this, all wires connected between the signal output terminal P0 of the transmitting unit 210 and the preset node Y can be referred to as the first wire group 240. Similarly, the input terminal of the first receiving unit 220 is connected to the preset node Y via the second wire group 250, and the input terminal Q2 of the second receiving unit 230 is connected to the preset node Y via the third wire group 260. The number of sub-ports included in the signal output terminal P0 of the sending unit 210, the input terminal Q1 of the first receiving unit 220, and the input terminal Q2 of the second receiving unit 230 are all equal and equal to the number of sub-nodes included in the preset node Y.

[0120] In this embodiment of the present application, the impedances of the transmitting unit 210, the first receiving unit 220, and the second receiving unit 230 must meet the following conditions: the impedance of the first receiving unit 220 is greater than the impedance of the transmitting unit 210, and the impedance of the second receiving unit 230 is greater than the impedance of the transmitting unit 210. Furthermore, the impedance of the second conductor group 250 must meet the following conditions: the difference between the impedance of the second conductor group 250 and the impedance of the first receiving unit 220 is within a first impedance range. This allows impedance matching between the second conductor group 250 and the first receiving unit 220. Impedance matching between one device and another means that the difference in impedance between the two devices is within a certain impedance range, so that there is no impedance jump when the two devices are connected. The impedance of the third conductor group 260 must meet the following conditions: the difference between the impedance of the third conductor group 260 and the impedance of the second receiving unit 230 is within a second impedance range. This allows impedance matching between the third conductor group 260 and the second receiving unit 230.

[0121] In the signal transmission circuit 20, the impedance of the first receiving unit 220 and the impedance of the second receiving unit 230 are both greater than the impedance of the transmitting unit 210. Since, in the related art, the impedances of the first receiving unit 220, the second receiving unit 230, and the transmitting unit 210 are all equal, the present application can increase the voltage of the signal received by the first and second receiving units 220, 230 in parallel by increasing the impedance of the first receiving unit 220 and the impedance of the second receiving unit 230, thereby improving the quality of the signals received by the first and second receiving units 220, 230. Furthermore, the impedance matching between the connected second wire group 250 and the first receiving unit 220 can prevent signal reflections when the signal is transmitted from the second wire group 250 to the first receiving unit 220, thereby improving the quality of the signal received by the first receiving unit 220. Similarly, the impedance matching between the connected third wire group 260 and the second receiving unit 230 can prevent signal reflections when the signal is transmitted from the third wire group 260 to the second receiving unit 230, thereby improving the quality of the signal received by the second receiving unit 230.

[0122] In some embodiments, the impedance of the first wire group 240 may also satisfy the following condition: the difference between the impedance of the first wire group 240 and the impedance of the transmitting unit 210 is within a third impedance range. In this way, impedance matching can be achieved between the first wire group 240 and the transmitting unit 210, thereby preventing signal reflection when the signal is transmitted from the transmitting unit 210 to the first wire group 240, thereby improving the quality of the signal received by the first receiving unit 220 and the second receiving unit 230.

[0123] As mentioned above, the signal transmission circuit 20 is applicable to both the case where the SOC and DDIC are connected via an interface using the MIPI_D-PHY protocol, and the case where the SOC and DDIC are connected via an interface using the MIPI_C-PHY protocol. In other words, the transmitting unit 210 and the first receiving unit 220 and the second receiving unit 230 can be connected via an interface using the MIPI_D-PHY protocol, or via an interface using the MIPI_C-PHY protocol. The signal transmission circuit 20 provided in the embodiment of the present application is explained in detail below for these two cases.

[0124] 1. In the first case, the transmitting unit 210 is connected to the first receiving unit 220 and the second receiving unit 230 via an interface using the MIPI_D-PHY protocol.

[0125] Figure 20 is a circuit structure diagram of a signal transmission circuit 20 provided in an embodiment of the present application, which shows a circuit structure in which a transmitting unit 210 is connected to a first receiving unit 220 and a second receiving unit 230 through an interface using the MIPI_D-PHY protocol. In this embodiment, the transmitting unit 210 is located in the SOC of the electronic device, the first receiving unit 220 is located in the DDIC1 of the electronic device, and the second receiving unit 230 is located in the DDIC2 of the electronic device. The connected SOC, DDIC1 and DDIC2 include at least two signal transmission circuits 20 as shown in Figure 20, one of which is used to transmit a data signal and the other is used to transmit a clock signal. In some specific embodiments, the connected SOC, DDIC1 and DDIC2 include five signal transmission circuits 20 as shown in Figure 20. At this time, the connection relationship between the SOC and DDIC1 and DDIC2 can be as shown in Figure 12, which will not be repeated here.

[0126] As shown in FIG20 , the transmitting unit 210 may include a first impedance device 212 and a second impedance device 214. The first receiving unit 220 includes a third impedance device 222 and a fourth impedance device 224. The second receiving unit 230 includes a fifth impedance device 232 and a sixth impedance device 234. In some embodiments, each impedance device (including the first impedance device 212, the second impedance device 214 ... the sixth impedance device 234) may be a resistor. In other embodiments, each impedance device may also be a metal oxide semiconductor field effect transistor (MOSFET). By controlling the degree of conduction of the MOSFET, the impedance of the MOSFET can be controlled.

[0127] The preset node Y includes a first node Y1 and a second node Y2. In this case, the signal output terminal P0 of the transmitting unit 210 includes two subports, namely, a first subport P01 and a second subport P02. The input terminal Q1 of the first receiving unit 220 also includes two subports, namely, a third subport Q11 and a fourth subport Q12. The input terminal Q2 of the second receiving unit 230 also includes two subports, namely, a fifth subport Q21 and a sixth subport Q22. The first wire group 240 includes a first wire 242 and a second wire 244. The second wire group 250 includes a third wire 252 and a fourth wire 254. The third wire group 260 includes a fifth wire 262 and a sixth wire 264.

[0128] The first end of the first impedance device 212 is connected to the preset voltage terminal VCOM or the ground line GND. The preset voltage terminal VCOM is referred to as the common voltage terminal in the related art and is used to provide a positive voltage, such as +400 mV. The second end of the first impedance device 212 is connected to the first node Y1 via the first conductor 242. In other words, the second end of the first impedance device 212 is the first sub-port P01. The first end of the third impedance device 222 is connected to the first node Y1 via the third conductor 252. In other words, the first end of the third impedance device 222 is the third sub-port Q11. The second end of the third impedance device 222 is connected to the second end of the fourth impedance device 224. The first end of the fifth impedance device 232 is connected to the first node Y1 via the fifth conductor 262. In other words, the first end of the fifth impedance device 232 is the fifth sub-port Q21. The second end of the fifth impedance device 232 is connected to the second end of the sixth impedance device 234. The first end of the second impedance device 214 can be connected to either the preset voltage terminal VCOM or the ground line GND. The second end of the second impedance device 214 is connected to the second node Y2 via the second wire 244. In other words, the second end of the second impedance device 214 is the second sub-port P02. The first end of the fourth impedance device 224 is connected to the second node Y2 via the fourth wire 254. In other words, the first end of the fourth impedance device 224 is the fourth sub-port Q12. The first end of the sixth impedance device 234 is connected to the second node Y2 via the sixth wire 264. In other words, the first end of the sixth impedance device 234 is the sixth sub-port Q22.

[0129] The inventive concept of the signal transmission circuit 20 shown in FIG. 20 is described below from two aspects.

[0130] (1) Impedance relationship among the transmitting unit 210 , the first receiving unit 220 , and the second receiving unit 230 .

[0131] Based on the circuit structure shown in FIG20 , the impedance of the first receiving unit 220 is greater than the impedance of the transmitting unit 210, which means that the sum of the impedance of the third impedance device 222 and the impedance of the fourth impedance device 224 is greater than the sum of the impedance of the first impedance device 212 and the impedance of the second impedance device 214. The impedance of the second receiving unit 230 is greater than the impedance of the transmitting unit 210, which means that the sum of the impedance of the fifth impedance device 232 and the impedance of the sixth impedance device 234 is greater than the sum of the impedance of the first impedance device 212 and the impedance of the second impedance device 214. For example, if the impedance of the first impedance device 212 is R1, the impedance of the second impedance device 214 is R2, the impedance of the third impedance device 222 is R3, the impedance of the fourth impedance device 224 is R4, the impedance of the fifth impedance device 232 is R5, and the impedance of the sixth impedance device 234 is R6, then:

[0132] R3+R4>R1+R2, and R5+R6>R1+R2.

[0133] In some embodiments, in the transmitting unit 210, the impedance R1 of the first impedance device 212 may be equal to the impedance R2 of the second impedance device 214. In the first receiving unit 220, the impedance R3 of the third impedance device 222 is equal to the impedance R4 of the fourth impedance device 224. In the second receiving unit 230, the impedance R5 of the fifth impedance device 232 is equal to the impedance R6 of the sixth impedance device 234. That is:

[0134] R3=R4>R1=R2, and R5=R6>R1=R2.

[0135] In some embodiments, the impedance R3 of the third impedance device 222 is between 1.2 times and 2 times (including the end value) the impedance R1 of the first impedance device 212. The impedance R5 of the fifth impedance device 232 is also between 1.2 times and 2 times (including the end value) the impedance R1 of the first impedance device 212. For example, as described in the related art, the impedance R1 of the first impedance device 212 and the impedance R2 of the second impedance device 214 can both be equal to 50Ω. Then, the impedance R3 of the third impedance device 222 and the impedance R4 of the fourth impedance device 224 can both be equal to 60Ω, 70Ω, 80Ω, 90Ω, or 100 ohms. The impedance R5 of the fifth impedance device 232 and the impedance R6 of the sixth impedance device 234 can also both be equal to 60Ω, 70Ω, 80Ω, 90Ω, or 100 ohms.

[0136] In some specific embodiments, it can be seen from the above description of the related art that when the signal output terminal P0 of the SOC is connected to only one DDIC, without considering the loss in signal transmission, the voltage of the signal received by the DDIC is

[0137] For the signal transmission circuit 20 shown in FIG20 , that is, the transmitting unit 210 is connected to both the first receiving unit 220 and the second receiving unit 230, the impedance of the first receiving unit 220 is R3 + R4 because the third impedance device 222 and the fourth impedance device 224 are connected in series. The impedance of the second receiving unit 230 is R5 + R6 because the fifth impedance device 232 and the sixth impedance device 234 are connected in series. Since the first receiving unit 220 and the second receiving unit 230 are connected in parallel between the first node Y1 and the second node Y2, the impedance R between the first node Y1 and the second node Y2 is:

[0138] In this case, the voltage difference U2 between the first node Y1 and the second node Y2 is: Without considering the loss in signal transmission, U2 is also the voltage of the signal received by the first receiving unit 220 and the second receiving unit 230 when the transmitting unit 210 is connected to the first receiving unit 220 and the second receiving unit 230 at the same time.

[0139] It can be seen that when R3=R4=R5=R6=2R1=2R2, That is, in a preferred embodiment, the impedance of the first impedance device 212 is equal to the impedance of the second impedance device 214; the impedance of the third impedance device 222 is equal to the impedance of the fourth impedance device 224, and equal to the impedance of the fifth impedance device 232; the impedance of the sixth impedance device 234 is equal to twice the impedance of the first impedance device 212.

[0140] (2) Impedance matching relationship between the connected wire group and the electrical unit.

[0141] FIG21 is an impedance diagram of a signal transmission circuit 20 provided in an embodiment of the present application, wherein impedance Z1 represents the characteristic impedance of first conductor 242, impedance Z2 represents the characteristic impedance of second conductor 244, and impedance Z6 represents the characteristic impedance of sixth conductor 264. Resistor R1 represents first impedance device 212, resistor R2 represents second impedance device 214, and resistor R6 represents sixth impedance device 234. The impedance matching relationship between the connected conductor groups and the electrical unit will be described below with reference to FIG21.

[0142] In some embodiments, when the second wire group 250 includes a third wire 252 and a fourth wire 254, and the first receiving unit 220 includes a third impedance device 222 and a fourth impedance device 224, the first impedance range may include a first impedance sub-range and a second impedance sub-range. In this case, "the difference between the impedance of the second wire group 250 and the impedance of the first receiving unit 220 is within the first impedance range" means that the difference between the characteristic impedance Z3 of the third wire 252 and the impedance of the third impedance device 222 (i.e., the resistor R3) is within the first impedance sub-range, and the difference between the characteristic impedance Z4 of the fourth wire 254 and the impedance of the fourth impedance device 224 (i.e., the resistor R4) is within the second impedance sub-range.

[0143] The minimum value of the first impedance sub-range is equal to the product of the impedance of the third impedance device 222 and -10%, and the maximum value of the first impedance sub-range is equal to the product of the impedance of the third impedance device 222 and 10%. For example, if the impedance of the third impedance device 222 is 100Ω, the minimum value of the first impedance sub-range is -10Ω, and the maximum value of the first impedance sub-range is 10Ω. In other words, the characteristic impedance Z3 of the third wire 252 connected to the third impedance device 222 has a minimum of 90Ω and a maximum of 110Ω. For another example, if the impedance of the third impedance device 222 is 60Ω, the characteristic impedance Z3 of the third wire 252 has a minimum of 54Ω and a maximum of 66Ω.

[0144] Similarly, the minimum value of the second impedance sub-range is equal to the product of the impedance of the fourth impedance device 224 and -10%, and the maximum value of the second impedance sub-range is equal to the product of the impedance of the fourth impedance device 224 and 10%. For example, if the impedance of the fourth impedance device 224 is 70Ω, the characteristic impedance Z4 of the fourth conductive line 254 is at least 63Ω and at most 77Ω.

[0145] In some embodiments, when the third wire group 260 includes a fifth wire 262 and a sixth wire 264, and the second receiving unit 230 includes a fifth impedance device 232 and a sixth impedance device 234, the second impedance range may include a third impedance sub-range and a fourth impedance sub-range. In this case, "the difference between the impedance of the third wire group 260 and the impedance of the second receiving unit 230 is within the second impedance range" means that the difference between the characteristic impedance Z5 of the fifth wire 262 and the impedance of the fifth impedance device 232 (i.e., the resistor R5) is within the third impedance sub-range, and the difference between the characteristic impedance Z6 of the sixth wire 264 and the impedance of the sixth impedance device 234 (i.e., the resistor R6) is within the fourth impedance sub-range.

[0146] The minimum value of the third impedance sub-range is equal to the product of the impedance of the fifth impedance device 232 and -10%, and the maximum value of the third impedance sub-range is equal to the product of the impedance of the fifth impedance device 232 and 10%. The minimum value of the fourth impedance sub-range is equal to the product of the impedance of the sixth impedance device 234 and -10%, and the maximum value of the fourth impedance sub-range is equal to the product of the impedance of the sixth impedance device 234 and 10%. Details thereof are omitted.

[0147] In some embodiments, when the first wire group 240 includes a first wire 242 and a second wire 244, and the transmitting unit 210 includes a first impedance device 212 and a second impedance device 214, the third impedance range may include a fifth impedance sub-range and a sixth impedance sub-range. In this case, "the difference between the impedance of the first wire group 240 and the impedance of the transmitting unit 210 is within the third impedance range" means that the difference between the characteristic impedance Z1 of the first wire 242 and the impedance of the first impedance device 212 (i.e., the resistor R1) is within the fifth impedance sub-range, and the difference between the characteristic impedance Z2 of the second wire 244 and the impedance of the second impedance device 214 (i.e., the resistor R2) is within the sixth impedance sub-range.

[0148] The minimum value of the fifth impedance sub-range is equal to the product of the impedance of the first impedance device 212 and -10%, and the maximum value of the fifth impedance sub-range is equal to the product of the impedance of the first impedance device 212 and 10%. The minimum value of the sixth impedance sub-range is equal to the product of the impedance of the second impedance device 214 and -10%, and the maximum value of the sixth impedance sub-range is equal to the product of the impedance of the second impedance device 214 and 10%. Details thereof are omitted.

[0149] In some specific embodiments, the impedances of resistors R1 and R2 are both 50Ω, and the impedances of resistors R3, R4, R5, and R6 are all 100Ω. In this case, the characteristic impedance Z1 of the first wire 242 and the characteristic impedance Z2 of the second wire 244 are both between 45Ω and 55Ω, and the characteristic impedance Z3 of the third wire 252, the characteristic impedance Z4 of the fourth wire 254, the characteristic impedance Z5 of the fifth wire 262, and the characteristic impedance Z6 of the sixth wire 264 are all between 90Ω and 110Ω. Thus, the characteristic impedance Z1 of the first wire 242 is less than the characteristic impedance Z3 of the third wire 252, and the characteristic impedance Z1 of the first wire 242 is less than the characteristic impedance Z5 of the fifth wire 262. Similarly, the characteristic impedance Z2 of the second wire 244 is less than the characteristic impedance Z4 of the fourth wire 254, and the characteristic impedance Z2 of the second wire 244 is less than the characteristic impedance Z6 of the sixth wire 264.

[0150] The characteristic impedance of the conductor can be adjusted by adjusting the dielectric constant, conductor thickness, and conductor width of the conductor. In some specific embodiments, the characteristic impedance of the conductor can be adjusted by adjusting the conductor width. Based on this, as shown in Figure 22, on the printed circuit board (PCB) of the electronic device, the width of the first conductor 242 can be greater than the width of the third conductor 252, and the width of the first conductor 242 can be greater than the width of the fifth conductor 262. The width of the second conductor 244 can be greater than the width of the fourth conductor 254, and the width of the second conductor 244 can be greater than the width of the sixth conductor 264. The distance between the third conductor 252 and the fourth conductor 254 can be greater than the distance between the first conductor 242 and the second conductor 244. In this way, the electrical structure formed by the first wire 242, the first impedance device 212, the second impedance device 214, and the second wire 244 has impedance matching; the electrical structure formed by the third wire 252, the third impedance device 222, the fourth impedance device 224, and the fourth wire 254 has impedance matching; and the electrical structure formed by the fifth wire 262, the fifth impedance device 232, the sixth impedance device 234, and the sixth wire 264 has impedance matching. In the entire signal transmission circuit 20, only the first node Y1 and the second node Y2 have impedance mutations, which can effectively reduce signal reflections caused by impedance mutations in the signal transmission circuit 20, thereby improving the quality of the signals received by the first receiving unit 220 and the second receiving unit 230.

[0151] The beneficial effects of the signal transmission circuit 20 shown in FIG. 21 are described below in conjunction with circuit simulation experiments.

[0152] In the first simulation experiment, the simulation conditions are as follows: for the signal transmission circuit 20 shown in Figure 21, the impedances of resistors R1 and R2 are both 50Ω, the impedances of resistors R3, R4, R5, and R6 are all 60Ω, the transmission rate of the data differential line is 1Gbps, the total length of the data differential line is 245mm, and the impedance of each conductor (including the first conductor 242, the second conductor 244...the sixth conductor 264) is not matched and controlled (in this case, the characteristic impedance of each conductor is much smaller than the impedance of each resistor). This simulation condition is used to simulate the signal loss of an actual electronic device, and the waveform of the signal received by the first receiving unit 220 when the signal transmission circuit 20 is transmitting the signal is displayed by an oscilloscope. The resulting eye diagram is shown in Figure 23. As can be seen from Figure 23, the voltage of the signal received by the first receiving unit 220 is ±116mV.

[0153] In the second simulation experiment, the simulation conditions were as follows: for the signal transmission circuit 20 shown in FIG21 , the impedances of resistors R1 and R2 were both 50Ω, the impedances of resistors R3, R4, R5, and R6 were all 60Ω, the data differential line transmission rate was 1 Gbps, the total length of the data differential line was 245 mm, the characteristic impedances of the first and second conductors 242 and 244 were both 50Ω, and the characteristic impedances of the third, fourth, fifth, and sixth conductors 252, 254, 262, and 264 were all 60Ω. These simulation conditions were used to simulate the signal loss of an actual electronic device. The waveform of the signal received by the first receiving unit 220 during signal transmission by the signal transmission circuit 20 was displayed using an oscilloscope. The resulting eye diagram is shown in FIG24 . FIG24 shows that the voltage of the signal received by the first receiving unit 220 is ±124 mV.

[0154] In the third simulation experiment, the simulation conditions are as follows: for the signal transmission circuit 20 shown in Figure 21, the impedances of resistors R1 and R2 are both 50Ω, the impedances of resistors R3, R4, R5, and R6 are all 70Ω, the transmission rate of the data differential line is 1Gbps, the total length of the data differential line is 245mm, and no matching control is performed on the characteristic impedance of each conductor. This simulation condition is used to simulate the signal loss of an actual electronic device, and the waveform of the signal received by the first receiving unit 220 when the signal transmission circuit 20 is transmitting the signal is displayed by an oscilloscope. The resulting eye diagram is shown in Figure 25. As can be seen from Figure 25, the voltage of the signal received by the first receiving unit 220 is ±122mV.

[0155] In the fourth simulation experiment, the simulation conditions were as follows: for the signal transmission circuit 20 shown in FIG21 , the impedances of resistors R1 and R2 were both 50Ω, the impedances of resistors R3, R4, R5, and R6 were all 70Ω, the data differential line transmission rate was 1 Gbps, the total length of the data differential line was 245 mm, the characteristic impedances of the first and second conductors 242 and 244 were both 50Ω, and the characteristic impedances of the third, fourth, fifth, and sixth conductors 252, 254, 262, and 264 were all 70Ω. These simulation conditions were used to simulate the signal loss of an actual electronic device. The waveform of the signal received by the first receiving unit 220 during signal transmission by the signal transmission circuit 20 was displayed using an oscilloscope. The resulting eye diagram is shown in FIG26 . FIG26 shows that the voltage of the signal received by the first receiving unit 220 is ±134 mV.

[0156] In the fifth simulation experiment, the simulation conditions are as follows: for the signal transmission circuit 20 shown in Figure 21, the impedances of resistors R1 and R2 are both 50Ω, the impedances of resistors R3, R4, R5, and R6 are all 100Ω, the transmission rate of the data differential line is 1Gbps, the total length of the data differential line is 245mm, and no matching control is performed on the characteristic impedance of each conductor. This simulation condition is used to simulate the signal loss of an actual electronic device, and the waveform of the signal received by the first receiving unit 220 when the signal transmission circuit 20 is transmitting the signal is displayed by an oscilloscope. The resulting eye diagram is shown in Figure 27. As can be seen from Figure 27, the voltage of the signal received by the first receiving unit 220 is ±124mV.

[0157] In the sixth simulation experiment, the simulation conditions were as follows: for the signal transmission circuit 20 shown in FIG21 , the impedances of resistors R1 and R2 were both 50Ω, the impedances of resistors R3, R4, R5, and R6 were all 100Ω, the data differential line transmission rate was 1 Gbps, the total length of the data differential line was 245 mm, the characteristic impedances of the first and second conductors 242 and 244 were both 50Ω, and the characteristic impedances of the third, fourth, fifth, and sixth conductors 252, 254, 262, and 264 were all 100Ω. These simulation conditions were used to simulate the signal loss of an actual electronic device. The waveform of the signal received by the first receiving unit 220 during signal transmission by the signal transmission circuit 20 was displayed using an oscilloscope. The resulting eye diagram is shown in FIG28 . FIG28 shows that the voltage of the signal received by the first receiving unit 220 is ±155 mV.

[0158] Comparing Figures 18, 23, 25, and 27, it can be seen that as the resistance values ​​of resistors R3, R4, R5, and R6 gradually increase from 50Ω to 100Ω, the voltage of the signal received by the first receiving unit 220 gradually increases and approaches ±165mV in Figure 17. Comparing Figures 23 and 24, comparing Figures 25 and 26, and comparing Figures 27 and 28, it can be concluded that impedance matching between the connected wires and the impedance device can not only increase the voltage of the signal received by the receiving unit, but also converge the rising and falling edges of the eye diagram signal (that is, impedance matching makes the eye diagram clearer), thereby improving the signal's anti-noise capability. This shows that impedance matching between the connected wires and the impedance device is beneficial to improving the quality of the signal received by the receiving unit. Comparing Figures 18 and 23 to 28, it can be seen that when the impedances of resistors R3, R4, R5, and R6 are all twice the impedance of resistor R1, and impedance matching is achieved between the connected wires and the impedance device, the quality of the signal received by the receiving unit is the highest. In addition, by comparing Figures 23 and 24, Figures 25 and 26, and Figures 27 and 28, it can be concluded that when impedance matching is not achieved between the connected wires and the impedance device, the voltage of the signal received by the first receiving unit 220 will be affected, and the problem of inter-code crosstalk will be caused due to signal reflection.

[0159] In addition, in conjunction with Figures 23 to 28, it can be seen that when the differential signal received by the first receiving unit 220 changes from a low level (negative voltage) to a high level (positive voltage), the voltage of the signal received by the first receiving unit 220 does not change suddenly, but rather has a climbing process. Based on this, the process of the signal changing from a low level to a high level can be divided into two stages, namely, a voltage change stage and a voltage stabilization stage. For example, for curve ① in the eye diagram shown in Figure 28, the voltage change stage is from 0.2 time units to 1.0 time units, and the voltage stabilization stage is from 1.0 time units to 2.0 time units. Comparing Figures 23 and 24, comparing Figures 25 and 26, and comparing Figures 27 and 28, it can be concluded that an increase in the characteristic impedance of the conductor only affects the duration of the voltage change stage, but does not affect the voltage of the signal received by the first receiving unit 220 during the voltage stabilization stage. In other words, achieving impedance matching between the connected conductor and the impedance device does not affect the voltage of the signal received during the voltage stabilization stage. In the voltage stabilization phase, the voltage of the signal received by the first receiving unit 220 is only related to the impedance of each resistor. In fact, in the voltage stabilization phase, the characteristic impedance of the wire can be regarded as zero.

[0160] 2. In the second case, the transmitting unit 210 is connected to the first receiving unit 220 and the second receiving unit 230 via an interface using the MIPI_C-PHY protocol.

[0161] Figure 29 is a circuit structure diagram of another signal transmission circuit 20 provided in an embodiment of the present application, which shows a circuit structure in which the transmitting unit 210 is connected to the first receiving unit 220 and the second receiving unit 230 through an interface using the MIPI_C-PHY protocol. In this embodiment, the transmitting unit 210 is located in the SOC of the electronic device, the first receiving unit 220 is located in the DDIC1 of the electronic device, and the second receiving unit 230 is located in the DDIC2 of the electronic device. The connected SOC, DDIC1 and DDIC2 may include three signal transmission circuits 20 as shown in Figure 29, which are used to transmit data signals and clock signals interspersed together.

[0162] Compared to the signal transmission circuit 20 shown in FIG20 , in the signal transmission circuit 20 shown in FIG29 , the transmitting unit 210 further includes a seventh impedance device 216. The first receiving unit 220 further includes an eighth impedance device 226. The second receiving unit 230 further includes a ninth impedance device 236. The preset node Y also includes a third node Y3. In this case, the signal output terminal P0 of the transmitting unit 210 includes three subports: a first subport P01, a second subport P02, and a seventh subport P03. The input terminal Q1 of the first receiving unit 220 also includes three subports: a third subport Q11, a fourth subport Q12, and an eighth subport Q13. The input terminal Q2 of the second receiving unit 230 also includes three subports: a fifth subport Q21, a sixth subport Q22, and a ninth subport Q23. The first wire group 240 also includes a seventh wire 246. The second wire group 250 also includes an eighth wire 256. The third wire group 260 also includes a ninth wire 266.

[0163] The first end of the seventh impedance device 216 can be connected to one of the preset voltage terminal VCOM and the ground line GND. The second end of the seventh impedance device 216 is connected to the third node Y3 via the seventh wire 246. In other words, the second end of the seventh impedance device 216 is the seventh sub-port P03. The first end of the eighth impedance device 226 is connected to the third node Y3 via the eighth wire 256. In other words, the first end of the eighth impedance device 226 is the eighth sub-port Q13. The second end of the eighth impedance device 226 is connected to the second end of the third impedance device 222 and the second end of the fourth impedance device 224. The first end of the ninth impedance device 236 is connected to the third node Y3 via the ninth wire 266. In other words, the first end of the ninth impedance device 236 is the ninth sub-port Q23. The second end of the ninth impedance device 236 is connected to the second end of the fifth impedance device 232 and the second end of the sixth impedance device 234.

[0164] When the signal transmission circuit 20 is working, one of the first end of the first impedance device 212, the first end of the second impedance device 214, and the first end of the seventh impedance device 216 is connected to the preset voltage terminal VCOM, one is connected to the ground line GND, and the last one is neither connected to the preset voltage terminal VCOM nor to the ground line GND.

[0165] The inventive concept of the signal transmission circuit 20 shown in FIG29 is described below from two aspects.

[0166] (1) Impedance relationship among the transmitting unit 210 , the first receiving unit 220 , and the second receiving unit 230 .

[0167] Based on the circuit structure shown in FIG29 , the impedance of the first receiving unit 220 is greater than the impedance of the transmitting unit 210 in the following manner: the sum of the impedance of the third impedance device 222 plus the impedance of the eighth impedance device 226 is greater than the sum of the impedance of the first impedance device 212 plus the impedance of the seventh impedance device 216; and the sum of the impedance of the fourth impedance device 224 plus the impedance of the eighth impedance device 226 is greater than the sum of the impedance of the second impedance device 214 plus the impedance of the seventh impedance device 216. The impedance of the second receiving unit 230 is greater than the impedance of the transmitting unit 210 in the following manner: the sum of the impedance of the fifth impedance device 232 plus the impedance of the ninth impedance device 236 is greater than the sum of the impedance of the first impedance device 212 plus the impedance of the seventh impedance device 216; and the sum of the impedance of the sixth impedance device 234 plus the impedance of the ninth impedance device 236 is greater than the sum of the impedance of the second impedance device 214 plus the impedance of the seventh impedance device 216. Taking the impedance of the seventh impedance device 216 as R7, the impedance of the eighth impedance device 226 as R8, and the impedance of the ninth impedance device 236 as R9 as an example, we have:

[0168] and,

[0169] In some embodiments, in the transmitting unit 210, the impedance R7 of the seventh impedance device 216, the impedance R1 of the first impedance device 212, and the impedance R2 of the second impedance device 214 are all equal. In the first receiving unit 220, the impedance R8 of the eighth impedance device 226, the impedance R3 of the third impedance device 222, and the impedance R4 of the fourth impedance device 224 are all equal. In the second receiving unit 230, the impedance R9 of the ninth impedance device 236, the impedance R5 of the fifth impedance device 232, and the impedance R6 of the sixth impedance device 234 are all equal. Simultaneously, the impedance of any impedance device in the first receiving unit 220 is greater than the impedance of any impedance device in the transmitting unit 210, and the impedance of any impedance device in the second receiving unit 230 is greater than the impedance of any impedance device in the transmitting unit 210. That is, R3 = R4 = R8 > R1 = R2 = R7, and R5 = R6 = R9 > R1 = R2 = R7.

[0170] In some embodiments, the impedance R8 of the eighth impedance device 226 is between 1.2 times and 2 times (inclusive) the impedance R7 of the seventh impedance device 216. The impedance R9 of the ninth impedance device 236 is between 1.2 times and 2 times (inclusive) the impedance R7 of the seventh impedance device 216. For example, as described in the related art, the impedance R7 of the seventh impedance device 216 can be equal to 50Ω. Then, the impedance R8 of the eighth impedance device 226 can be equal to 60Ω, 70Ω, 80Ω, 90Ω, or 100 ohms. The impedance R9 of the ninth impedance device 236 can also be equal to 60Ω, 70Ω, 80Ω, 90Ω, or 100 ohms. In some specific embodiments, R3=R4=R5=R6=R8=R9=2R1=2R2=2R7.

[0171] (2) Impedance matching relationship between the connected wire group and the electrical unit.

[0172] FIG30 is an impedance diagram of another signal transmission circuit 20 provided in an embodiment of the present application, wherein impedance Z7 is used to represent the characteristic impedance of seventh conductor 246, impedance Z8 is used to represent the characteristic impedance of eighth conductor 256, and impedance Z9 is used to represent the characteristic impedance of ninth conductor 266. Resistor R7 is used to represent seventh impedance device 216, resistor R8 is used to represent eighth impedance device 226, and resistor R9 is used to represent ninth impedance device 236. The impedance matching relationship between the connected conductor groups and the electrical units will be described below with reference to FIG30.

[0173] In some embodiments, when second wire group 250 further includes an eighth wire 256 and first receiving unit 220 further includes an eighth impedance device 226, the first impedance range may further include a seventh impedance sub-range. In this case, "the difference between the impedance of second wire group 250 and the impedance of first receiving unit 220 is within the first impedance range" also includes: the difference between the characteristic impedance Z8 of eighth wire 256 and the impedance of eighth impedance device 226 (i.e., resistor R8) is within the seventh impedance sub-range. The minimum value of the seventh impedance sub-range is equal to the product of the impedance of eighth impedance device 226 and -10%, and the maximum value of the seventh impedance sub-range is equal to the product of the impedance of eighth impedance device 226 and 10%. Details are omitted here.

[0174] In some embodiments, when the third wire group 260 further includes a ninth wire 266 and the second receiving unit 230 further includes a ninth impedance device 236, the second impedance range may further include an eighth impedance sub-range. In this case, "the difference between the impedance of the third wire group 260 and the impedance of the second receiving unit 230 is within the second impedance range" also includes: the difference between the characteristic impedance Z9 of the ninth wire 266 and the impedance of the ninth impedance device 236 (i.e., resistor R9) is within the eighth impedance sub-range. The minimum value of the eighth impedance sub-range is equal to the product of the impedance of the ninth impedance device 236 and -10%, and the maximum value of the eighth impedance sub-range is equal to the product of the impedance of the ninth impedance device 236 and 10%. These details are omitted.

[0175] In some embodiments, when first conductor group 240 further includes seventh conductor 246 and transmitting unit 210 further includes seventh impedance device 216, the third impedance range may further include a ninth impedance sub-range. In this case, "the difference between the impedance of first conductor group 240 and the impedance of transmitting unit 210 is within the third impedance range" also includes the difference between the characteristic impedance Z7 of seventh conductor 246 and the impedance of seventh impedance device 216 (i.e., resistor R7) being within the ninth impedance sub-range. The minimum value of the ninth impedance sub-range is equal to the product of the impedance of seventh impedance device 216 and -10%, and the maximum value of the ninth impedance sub-range is equal to the product of the impedance of seventh impedance device 216 and 10%. Details are omitted here.

[0176] In some specific embodiments, the impedance of resistor R7 is 50Ω, and the impedances of resistors R8 and R9 are both 100Ω. In this case, the characteristic impedance of seventh conductor 246 is between 45Ω and 55Ω, and the characteristic impedances of eighth conductor 256 and ninth conductor 266 are both between 90Ω and 110Ω. Thus, the characteristic impedance Z7 of seventh conductor 246 is less than the characteristic impedance Z8 of eighth conductor 256, and the characteristic impedance Z7 of seventh conductor 246 is less than the characteristic impedance Z9 of ninth conductor 266. Based on this, as shown in FIG31 , on the printed circuit board of the electronic device, the width of seventh conductor 246 can be greater than the width of eighth conductor 256, and the width of seventh conductor 246 can be greater than the width of ninth conductor 266. The distance between third conductor 252 and fourth conductor 254 can be greater than the distance between first conductor 242 and second conductor 244. The distance between fourth conductor 254 and eighth conductor 256 can be greater than the distance between second conductor 244 and seventh conductor 246. In this way, the electrical structure formed by the first wire 242, the first impedance device 212, the second impedance device 214, the second wire 244, the seventh wire 246, and the seventh impedance device 216 has impedance matching; the electrical structure formed by the third wire 252, the third impedance device 222, the fourth impedance device 224, the fourth wire 254, the eighth wire 256, and the eighth impedance device 226 has impedance matching; and the electrical structure formed by the fifth wire 262, the fifth impedance device 232, the sixth impedance device 234, the sixth wire 264, the ninth wire 266, and the ninth impedance device 236 has impedance matching. In the entire signal transmission circuit 20, only the first node Y1, the second node Y2, and the third node Y3 have impedance mutations, which can effectively reduce signal reflections caused by impedance mutations in the signal transmission circuit 20, thereby improving the quality of the signals received by the first receiving unit 220 and the second receiving unit 230.

[0177] It will be appreciated that in the embodiments shown in Figures 29 and 30, only the first impedance device 212 or resistor R1, the second impedance device 214 or resistor R2, and the seventh impedance device 216 or resistor R7 are shown in the transmitting unit 210. In other embodiments, as shown in Figure 32, the transmitting unit 210 may further include a resistor Rpu_ta, a resistor Rpd_ta, a resistor Rpu_tb, a resistor Rpd_tb, a resistor Rpu_tc, and a resistor Rpd_tc. The resistors Rpu_ta, Rpd_ta, Rpu_tb, Rpd_tb, Rpu_tc, and Rpd_tc are used to output intermediate level signals to the first receiving unit 220 and the second receiving unit 230 when the signal transmission circuit 20 is in operation. The operation process is as described in the related art above and will not be repeated here. It can be understood that when the signal transmission circuit 20 is working, the resistors Rpu_ta, Rpd_ta, Rpu_tb, Rpd_tb, Rpu_tc, and Rpd_tc will neither affect the voltage of the signal received by the first receiving unit 220 and the second receiving unit 230, nor affect the impedance matching relationship between each wire and the impedance device.

[0178] The present application also provides an electronic device, which includes the signal transmission circuit 20 in any of the above embodiments. The appearance of the electronic device may be as shown in FIG1 or FIG2 .

[0179] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A signal transmission circuit, characterized in that: The signal transmission circuit includes a sending unit, a first receiving unit and a second receiving unit; The signal output end of the sending unit is connected to a preset node through a first wire group, the input end of the first receiving unit is connected to the preset node through a second wire group, and the input end of the second receiving unit is connected to the preset node through a third wire group; The impedance of the first receiving unit and the impedance of the second receiving unit are both greater than the impedance of the sending unit, and the difference between the impedance of the second wire group and the impedance of the first receiving unit is within a first impedance range, and the difference between the impedance of the third wire group and the impedance of the second receiving unit is within a second impedance range.

2. The signal transmission circuit according to claim 1, characterized in that: The sending unit includes a first impedance device and a second impedance device, the first receiving unit includes a third impedance device and a fourth impedance device, and the second receiving unit includes a fifth impedance device and a sixth impedance device; the preset node includes a first node and a second node, the first wire group includes a first wire and a second wire, the second wire group includes a third wire and a fourth wire, and the third wire group includes a fifth wire and a sixth wire; The first end of the first impedance device can be connected to one of the preset voltage terminal and the ground wire; the second end of the first impedance device is connected to the first node through the first wire; the first end of the third impedance device is connected to the first node through the third wire; the second end of the third impedance device is connected to the second end of the fourth impedance device; the first end of the fifth impedance device is connected to the first node through the fifth wire; the second end of the fifth impedance device is connected to the second end of the sixth impedance device; the first end of the second impedance device can be connected to one of the preset voltage terminal and the ground wire; the second end of the second impedance device is connected to the second node through the second wire; the first end of the fourth impedance device is connected to the second node through the fourth wire; the first end of the sixth impedance device is connected to the second node through the sixth wire.

3. The signal transmission circuit according to claim 2, characterized in that: The impedance of the first impedance device is equal to the impedance of the second impedance device, the impedance of the third impedance device is equal to the impedance of the fourth impedance device, and the impedance of the fifth impedance device is equal to the impedance of the sixth impedance device.

4. The signal transmission circuit according to claim 3, characterized in that: The impedance of the third impedance device is at least 1.2 times the impedance of the first impedance device, and the impedance of the third impedance device is at most 2 times the impedance of the first impedance device; The impedance of the fifth impedance device is at least 1.2 times the impedance of the first impedance device, and the impedance of the fifth impedance device is at most 2 times the impedance of the first impedance device.

5. The signal transmission circuit according to any one of claims 2 to 4, characterized in that: The first impedance range includes a first impedance sub-range and a second impedance sub-range; the difference between the characteristic impedance of the third conductor and the impedance of the third impedance device is within the first impedance sub-range, and the difference between the characteristic impedance of the fourth conductor and the impedance of the fourth impedance device is within the second impedance sub-range; The second impedance range includes a third impedance sub-range and a fourth impedance sub-range; the difference between the characteristic impedance of the fifth conductor and the impedance of the fifth impedance device is within the third impedance sub-range, and the difference between the characteristic impedance of the sixth conductor and the impedance of the sixth impedance device is within the fourth impedance sub-range.

6. The signal transmission circuit according to claim 5, characterized in that: The minimum value of the first impedance sub-range is equal to the product of the impedance of the third impedance device and -10%, and the maximum value of the first impedance sub-range is equal to the product of the impedance of the third impedance device and 10%; the minimum value of the second impedance sub-range is equal to the product of the impedance of the fourth impedance device and -10%, and the maximum value of the second impedance sub-range is equal to the product of the impedance of the fourth impedance device and 10%; the minimum value of the third impedance sub-range is equal to the product of the impedance of the fifth impedance device and -10%, and the maximum value of the third impedance sub-range is equal to the product of the impedance of the fifth impedance device and 10%; the minimum value of the fourth impedance sub-range is equal to the product of the impedance of the sixth impedance device and -10%, and the maximum value of the fourth impedance sub-range is equal to the product of the impedance of the sixth impedance device and 10%.

7. The signal transmission circuit according to any one of claims 2 to 6, characterized in that: A difference between an impedance of the first conductor group and an impedance of the transmitting unit is within a third impedance range.

8. The signal transmission circuit according to claim 7, characterized in that: The third impedance range includes a fifth impedance sub-range and a sixth impedance sub-range; the difference between the characteristic impedance of the first conductor and the impedance of the first impedance device is within the fifth impedance sub-range, and the difference between the characteristic impedance of the second conductor and the impedance of the second impedance device is within the sixth impedance sub-range.

9. The signal transmission circuit according to claim 8, characterized in that: The minimum value of the fifth impedance sub-range is equal to the product of the impedance of the first impedance device and -10%, and the maximum value of the fifth impedance sub-range is equal to the product of the impedance of the first impedance device and 10%; The minimum value of the sixth impedance sub-range is equal to the product of the impedance of the second impedance device and -10%, and the maximum value of the sixth impedance sub-range is equal to the product of the impedance of the second impedance device and 10%.

10. The signal transmission circuit according to any one of claims 2 to 9, characterized in that: The width of the first wire is greater than that of the third wire, and the width of the first wire is greater than that of the fifth wire; the width of the second wire is greater than that of the fourth wire, and the width of the second wire is greater than that of the sixth wire.

11. The signal transmission circuit according to any one of claims 2 to 10, characterized in that: The sending unit further includes a seventh impedance device, the first receiving unit further includes an eighth impedance device, and the second receiving unit further includes a ninth impedance device; the preset node further includes a third node; the first wire group further includes a seventh wire, the second wire group further includes an eighth wire, and the third wire group further includes a ninth wire; The first end of the seventh impedance device can be connected to the preset voltage terminal and one of the ground wires; the second end of the seventh impedance device is connected to the third node through the seventh wire; the first end of the eighth impedance device is connected to the third node through the eighth wire; the second end of the eighth impedance device is connected to the second end of the third impedance device and the second end of the fourth impedance device; the first end of the ninth impedance device is connected to the third node through the ninth wire; the second end of the ninth impedance device is connected to the second end of the fifth impedance device and the second end of the sixth impedance device.

12. The signal transmission circuit according to claim 11, characterized in that: The impedance of the seventh impedance device, the impedance of the first impedance device and the impedance of the second impedance device are all equal; the impedance of the eighth impedance device, the impedance of the third impedance device and the impedance of the fourth impedance device are all equal; the impedance of the ninth impedance device, the impedance of the fifth impedance device and the impedance of the sixth impedance device are all equal; The impedance of the eighth impedance device is at least 1.2 times the impedance of the seventh impedance device, and the impedance of the eighth impedance device is at most 2 times the impedance of the seventh impedance device; The impedance of the ninth impedance device is at least 1.2 times the impedance of the seventh impedance device, and the impedance of the ninth impedance device is at most 2 times the impedance of the seventh impedance device.

13. The signal transmission circuit according to claim 11 or 12, characterized in that: The first impedance range includes a seventh impedance sub-range, and the difference between the characteristic impedance of the eighth conductor and the impedance of the eighth impedance device is within the seventh impedance sub-range; the minimum value of the seventh impedance sub-range is equal to the product of the impedance of the eighth impedance device and -10%, and the maximum value of the seventh impedance sub-range is equal to the product of the impedance of the eighth impedance device and 10%; The second impedance range includes an eighth impedance sub-range, and the difference between the characteristic impedance of the ninth conductor and the impedance of the ninth impedance device is within the eighth impedance sub-range; the minimum value of the eighth impedance sub-range is equal to the product of the impedance of the ninth impedance device and -10%, and the maximum value of the eighth impedance sub-range is equal to the product of the impedance of the ninth impedance device and 10%.

14. The signal transmission circuit according to any one of claims 11 to 13, characterized in that: The difference between the characteristic impedance of the seventh conductor and the impedance of the seventh impedance device is within a ninth impedance sub-range, the minimum value of the ninth impedance sub-range is equal to the product of the impedance of the seventh impedance device and -10%, and the maximum value of the ninth impedance sub-range is equal to the product of the impedance of the seventh impedance device and 10%.

15. An electronic device, characterized in that: Comprising the signal transmission circuit as claimed in any one of claims 1 to 14.

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