Pixel circuit and driving method therefor, and display panel and display apparatus

Abstract

A pixel circuit comprises a driving sub-circuit, a data writing sub-circuit, a first reset sub-circuit and a second reset sub-circuit; and the pixel circuit comprises a first reset stage and a data writing stage, the first reset stage being prior to the data writing stage, wherein the first reset sub-circuit is configured to transmit, to a first node in the first reset stage, a first initialization signal received at a first initialization signal end, in response to a first reset signal received at a first reset signal end; the second reset sub-circuit is configured to transmit, to a second node in the first reset stage, a second initialization signal received at a second initialization signal end, in response to a second reset signal received at a second reset signal end; and in the first reset stage, a voltage of the second initialization signal is greater than a voltage of the first initialization signal.

Description

Pixel circuit and driving method thereof, display panel, and display device

[0001] This application claims priority to the international patent application with application number PCT / CN2023 / 120988 filed on September 25, 2023, and claims priority to the Chinese patent application with application number 202410433916.X filed on April 10, 2024, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a pixel circuit and a driving method thereof, a display panel, and a display device. Background Art

[0003] With the rapid development of display technology, display devices have become increasingly ubiquitous in people's lives. Organic Light Emitting Diodes (OLEDs) are widely used in smart products such as mobile phones, televisions, and laptops due to their advantages such as self-luminescence, low power consumption, wide viewing angle, fast response, high contrast, and flexible display.

[0004] Summary of the Invention

[0005] In one aspect, a pixel circuit is provided. The pixel circuit includes a first reset phase and a data write phase, wherein the first reset phase precedes the data write phase. The pixel circuit includes a driving subcircuit, a data write subcircuit, a first reset subcircuit, and a second reset subcircuit.

[0006] The driver subcircuit is connected to a first node, a second node, and a third node. The driver subcircuit is configured to control the conduction and cutoff of the circuit between the second node and the third node under the control of the voltage of the first node. The data write subcircuit is connected to a first scan signal terminal, a data signal terminal, and the second node. The data write subcircuit is configured to transmit a data signal received at the data signal terminal to the second node in response to a first scan signal received at the first scan signal terminal during the data write phase.

[0007] The first reset sub-circuit is connected to a first initialization signal terminal, a first reset signal terminal, and the first node. The first reset sub-circuit is configured to, in response to the first reset signal received at the first reset signal terminal, transmit the first initialization signal received at the first initialization signal terminal to the first node during the first reset phase. The second reset sub-circuit is connected to a second initialization signal terminal, a second reset signal terminal, and the second node. The second reset sub-circuit is configured to, in response to the second reset signal received at the second reset signal terminal, transmit the second initialization signal received at the second initialization signal terminal to the second node during the first reset phase. Furthermore, in the first reset phase, a voltage of the second initialization signal is greater than a voltage of the first initialization signal.

[0008] In some embodiments, in the first reset phase, an absolute value of a difference between a voltage of the second initialization signal and a voltage of the first initialization signal is 10V to 13V.

[0009] In some embodiments, the pixel circuit further includes a second reset phase and a first light-emitting phase, wherein the second reset phase is located between the data writing phase and the first light-emitting phase. The second reset sub-circuit is further configured to, during the second reset phase, transmit a second initialization signal received at the second initialization signal terminal to the second node in response to a second reset signal received at the second reset signal terminal.

[0010] In some embodiments, the pixel circuit has a first refresh frequency and a second refresh frequency, the second refresh frequency being lower than the first refresh frequency. At the first refresh frequency, a frame includes one refresh period. At the second refresh frequency, a frame also includes at least one hold period, the at least one hold period being located after the refresh period. Furthermore, the hold period includes at least one third reset phase and a second light-emitting phase, the at least one third reset phase being located before the second light-emitting phase.

[0011] The pixel circuit further includes a third reset subcircuit and a first storage subcircuit. The third reset subcircuit is connected to a fourth node, a third reset signal terminal, and a third initialization signal terminal. The fourth node is configured to be connected to an anode of the light-emitting device. The third reset subcircuit is configured to transmit a third initialization signal received at the third initialization signal terminal to the fourth node in response to a third reset signal received at the third reset signal terminal during the first reset phase and the third reset phase. The first storage subcircuit is connected to a first voltage signal terminal and the fourth node. The first storage subcircuit is configured to pull up or pull down a voltage of the fourth node in response to a first voltage signal received at the first voltage signal terminal during the first reset phase and the third reset phase.

[0012] Among them, the voltage of one of the third reset signal and the first voltage signal in the refresh period is greater than the voltage in the hold period, and the voltage of the other in the hold period is greater than the voltage in the refresh period.

[0013] In some embodiments, the signals at the first voltage signal terminal and the second initialization signal terminal are the same.

[0014] In some embodiments, the signal at the third reset signal terminal is the same as the signal at the second reset signal terminal.

[0015] In some embodiments, the first storage sub-circuit includes a first capacitor, a first plate of the first capacitor is connected to the first voltage signal terminal, and a second plate of the first capacitor is connected to the fourth node.

[0016] In some embodiments, the first reset subcircuit includes a plurality of first transistors connected in series, wherein the control electrodes of the first transistors are connected to the first reset signal terminal. Two first transistors at two ends of the plurality of first transistors connected in series have a first electrode connected to the first initialization signal terminal, and a second electrode connected to the first node.

[0017] The second reset sub-circuit includes a second transistor, a first electrode of the second transistor is connected to the second reset signal terminal, a second electrode of the second transistor is connected to the second node, and a control electrode of the second transistor is connected to the second reset signal terminal.

[0018] The first transistor and the second transistor are both P-type transistors, and the non-operating voltage of the first reset signal received at the first reset signal terminal is lower than the non-operating voltage of the second reset signal received at the second reset signal terminal.

[0019] In some embodiments, the pixel circuit further includes a compensation subcircuit, which is connected to the first node, the third node and the second scan signal terminal; the compensation subcircuit is configured to, during the data writing phase, transmit the voltage of the third node to the first node in response to the second scan signal received at the second scan signal terminal.

[0020] In some embodiments, the compensation sub-circuit includes a plurality of third transistors connected in series, wherein the control electrodes of the third transistors are connected to the second scanning signal terminal. Two third transistors at both ends of the plurality of third transistors connected in series have a second electrode connected to the first node, and a first electrode connected to the third node.

[0021] The second reset sub-circuit includes a second transistor, the second transistor and the third transistor are both P-type transistors, and the non-operating voltage of the second scan signal received at the second scan signal end is less than the non-operating voltage of the second reset signal received at the second reset signal end.

[0022] In some embodiments, one frame includes a light-emitting phase, and the pixel circuit further includes a first light-emitting control subcircuit and a second light-emitting control subcircuit.

[0023] The first light-emitting control subcircuit is connected to the second node, the first power signal terminal, and the first enable signal terminal. The first light-emitting control subcircuit is configured to, during the light-emitting phase, transmit the first power signal at the first power signal terminal to the second node in response to a first enable signal received at the first enable signal terminal.

[0024] The second light-emitting control subcircuit is connected to the third node, the fourth node, and the second enable signal terminal. The second light-emitting control subcircuit is configured to, during the light-emitting phase, transmit a voltage at the third node to the fourth node in response to a second enable signal received at the second enable signal terminal; the fourth node is configured to be connected to an anode of the light-emitting device.

[0025] Wherein, in the light emitting stage, the start time of the operating voltage of the first enable signal is before the start time of the operating voltage of the second enable signal.

[0026] In another aspect, a display panel is provided. The display panel includes a plurality of pixel circuits according to any of the above embodiments, wherein the plurality of pixel circuits are arranged in M ​​rows and N columns, each row including N pixel circuits arranged along a first direction, and each column including M pixel circuits arranged along a second direction, where M>1, N>1, and M and N are integers.

[0027] In some embodiments, the pixel circuit includes a compensation subcircuit, and along the second direction, from the first row of pixel circuits to the last row of pixel circuits, the M rows of pixel circuits are respectively the 1st to the Mth rows of pixel circuits.

[0028] The display panel also includes a first gate driving circuit, which includes M+Q cascaded first shift registers. From the first-stage first shift register to the last-stage first shift register, the M+Q first shift registers are respectively the 1st to the M+Qth first shift registers.

[0029] The first shift register includes a first signal output terminal, a first reset signal terminal of the pixel circuit in the P-th row is connected to the first signal output terminal of the P-th first shift register, and a second scan signal terminal of the pixel circuit in the P-th row is connected to the first signal output terminal of the P+Q-th first shift register. P≤M, Q>0, and P and Q are integers.

[0030] In some embodiments, the pixel circuit includes a third reset subcircuit, and along the second direction, from the first row of pixel circuits to the last row of pixel circuits, the M rows of pixel circuits are respectively the 1st to the Mth rows of pixel circuits.

[0031] The display panel also includes a second gate drive circuit, which includes M cascaded second shift registers, from the first stage of the second shift register to the last stage of the second shift register, and the M second shift registers are respectively the first to the Mth second shift registers. The second shift register includes a second signal output terminal. The second reset signal terminal and the third reset signal terminal of the pixel circuit in the Pth row are connected to the second signal output terminal of the Pth second shift register, where P ≤ M, and P is an integer.

[0032] In some embodiments, the pixel circuit includes a first light-emitting control subcircuit and a second light-emitting control subcircuit, and along the second direction, from the first row of pixel circuits to the last row of pixel circuits, the M rows of pixel circuits are respectively the 1st to the Mth rows of pixel circuits.

[0033] The display panel also includes a third gate drive circuit and a fourth gate drive circuit. The third gate drive circuit includes M cascaded third shift registers, and from the first stage third shift register to the last stage third shift register, the M third shift registers are respectively the 1st to the Mth third shift registers. The third shift register includes a third signal output terminal, and the first enable signal terminal of the P-th row pixel circuit is connected to the third signal output terminal of the P-th third shift register, P≤M, and P is an integer. The fourth gate drive circuit includes M cascaded fourth shift registers, and from the first stage fourth shift register to the last stage fourth shift register, the M fourth shift registers are respectively the 1st to the Mth fourth shift registers. The fourth shift register includes a fourth signal output terminal, and the second enable signal terminal of the P-th row pixel circuit is connected to the fourth signal output terminal of the P-th fourth shift register, P≤M, and P is an integer.

[0034] In some embodiments, along the second direction, from the first row of pixel circuits to the last row of pixel circuits, the M rows of pixel circuits are respectively the 1st to the Mth rows of pixel circuits.

[0035] The display panel further includes a fifth gate drive circuit, which includes M cascaded fifth shift registers, from the first stage of the fifth shift register to the last stage of the fifth shift register, and the M fifth shift registers are respectively the first to the Mth fifth shift registers. The fifth shift register includes a fifth signal output terminal, and the first scanning signal terminal of the pixel circuit in the Pth row is connected to the fifth signal output terminal of the Pth fifth shift register, where P≤M, and P is an integer.

[0036] In another aspect, a display device is provided, comprising the display panel according to any one of the above embodiments.

[0037] In yet another aspect, a method for driving a pixel circuit is provided. The method for driving a pixel circuit is used to drive the pixel circuit described in any of the above embodiments. The method for driving a pixel circuit includes a first reset phase and a data write phase, wherein the first reset phase precedes the data write phase. The first reset phase includes a first subsegment and a second subsegment, wherein the first subsegment precedes the second subsegment. Alternatively, the first subsegment is located after the second subsegment. Alternatively, the first subsegment and the second subsegment at least partially overlap.

[0038] In the first sub-segment, the first reset sub-circuit transmits a first initialization signal received at the first initial switching signal terminal to the first node in response to a first reset signal received at the first reset signal terminal. In the second sub-segment, the second reset sub-circuit transmits a second initialization signal received at the second initial switching signal terminal to the second node in response to a second reset signal received at the second reset signal terminal.

[0039] In some embodiments, the driving method of the pixel circuit further includes a second reset phase and a first light-emitting phase, wherein the second reset phase is located between the data writing phase and the first light-emitting phase. During the second reset phase, the second reset sub-circuit transmits a second initialization signal received at the second initialization signal terminal to the second node in response to a second reset signal received at the second reset signal terminal.

[0040] In some embodiments, the pixel circuit further includes a third reset subcircuit and a first storage subcircuit. The pixel circuit has a first refresh frequency and a second refresh frequency, wherein the second refresh frequency is less than the first refresh frequency. At the first refresh frequency, a frame includes one refresh cycle. At the second refresh frequency, a frame includes one refresh cycle and at least one hold cycle, wherein the at least one hold cycle is located after the refresh cycle, and the hold cycle includes at least one third reset phase and a second light-emitting phase, wherein the at least one third reset phase is located before the second light-emitting phase.

[0041] During the first reset phase and the third reset phase, the third reset sub-circuit transmits the third initialization signal received at the third initialization signal terminal to the fourth node in response to the third reset signal received at the third reset signal terminal. The first storage sub-circuit pulls up or down the voltage of the fourth node in response to the first voltage signal received at the first voltage signal terminal. The voltage of one of the first reset signal and the first voltage signal during the refresh period is greater than the voltage during the hold period, and the voltage of the other during the hold period is greater than the voltage during the refresh period.

[0042] In some embodiments, the pixel circuit includes a first light-emission control subcircuit and a second light-emission control subcircuit, and a frame includes a light-emission phase. During the light-emission phase, the first light-emission control subcircuit transmits a first power signal at the first power signal terminal to the second node in response to a first enable signal received at the first enable signal terminal. The second light-emission control subcircuit transmits a voltage at the third node to the fourth node in response to a second enable signal received at the second enable signal terminal. The start time of the operating voltage of the first enable signal is before the start time of the operating voltage of the second enable signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0044] FIG1 is a structural diagram of a display device according to some embodiments;

[0045] FIG2 is a structural diagram of another display device according to some embodiments;

[0046] FIG3 is a cross-sectional view taken along section line AA in FIG1 ;

[0047] FIG4A is a structural diagram of a display panel according to some embodiments;

[0048] FIG4B is a structural diagram of another display panel according to some embodiments;

[0049] FIG5 is a cross-sectional view taken along section line CC in FIG4A;

[0050] FIG6 is a structural block diagram of a pixel circuit according to some embodiments;

[0051] FIG7 is a circuit diagram of the pixel circuit shown in FIG6 ;

[0052] FIG8 is a timing diagram of a pixel circuit according to some embodiments;

[0053] FIG9 is a timing diagram of another pixel circuit according to some embodiments;

[0054] FIG10 is a timing diagram of yet another pixel circuit according to some embodiments;

[0055] FIG11 is a timing diagram of yet another pixel circuit according to some embodiments;

[0056] FIG12 is a graph showing the test results of just noticeable color difference of a display panel according to some embodiments;

[0057] FIG13 is a graph showing test results of flicker values ​​of a display panel according to the related art that vary with time;

[0058] FIG14 is a graph showing test results of flicker values ​​of a display panel varying over time according to some embodiments;

[0059] FIG. 15 is a structural diagram of yet another display panel according to some embodiments. DETAILED DESCRIPTION

[0060] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0061] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0062] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0063] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0064] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0065] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0066] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0067] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0068] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0069] As used herein, "about," "approximately," or "substantially" are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0070] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0071] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0072] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0073] In this specification, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. It will be further understood that, unless expressly defined herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted as an ideal or overly formal meaning.

[0074] In this disclosure, terms such as "lower," "below," "above," and "upper," and similar terms are used to explain the relationships between components shown in the drawings. These terms may be relative and described based on directions shown in the drawings, or based on the order in which process steps are formed, but are not limited thereto.

[0075] The term "opposite" means that the first element may be directly or indirectly opposite to the second element. In the case where a third element is interposed between the first and second elements, the first and second elements may be understood to be indirectly opposite to each other although they are still opposite to each other.

[0076] In the embodiments of the present disclosure, the transistors used may be thin film transistors (TFT), metal oxide semiconductors (MOS) or other switching devices with the same characteristics. The embodiments of the present disclosure are described using thin film transistors as an example.

[0077] In the embodiments of the present disclosure, the control electrode of each thin film transistor used is the gate of the transistor, the first electrode is one of the source and drain of the thin film transistor, and the second electrode is the other of the source and drain of the thin film transistor. Since the source and drain of the thin film transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable, that is, the first electrode and the second electrode of the thin film transistor in the embodiments of the present disclosure can be structurally indistinguishable. For example, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source and the second electrode is the drain; for example, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain and the second electrode is the source.

[0078] In the embodiments of the present disclosure, the capacitor may be a capacitive device fabricated separately through a process, for example, by fabricating specialized capacitive electrodes, each of which may be implemented through a metal layer, a semiconductor layer (e.g., doped polysilicon), etc. The capacitor may also be a parasitic capacitor between transistors, or implemented through the transistor itself and other devices or circuits, or through the parasitic capacitance between circuits within the circuit itself.

[0079] In the embodiments of the present disclosure, the first node, the second node, the third node, and other nodes do not represent actual components, but represent the junction points of related electrical connections in the circuit diagram. That is, these nodes are nodes that are equivalent to the junction points of related electrical connections in the circuit diagram.

[0080] In the embodiments of the present disclosure, “operating voltage” refers to a voltage that can turn on the operated transistor included therein; correspondingly, “non-operating voltage” refers to a voltage that cannot turn off the operated transistor included therein.

[0081] As shown in FIG. 1 and FIG. 2 , some embodiments of the present disclosure provide a display device 1000 . The display device 1000 may be any device that displays an image, whether in motion (eg, video) or fixed (eg, still image), and whether textual or graphic.

[0082] For example, the display device 1000 can be any product or component with a display function, such as a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, a virtual reality (VR) device, etc.

[0083] For example, as shown in FIG1 , the display device 1000 may be a portable display product; for example, the display device 1000 may be the mobile phone shown in FIG1 . For another example, referring to FIG2 , the display device 1000 may be a wearable device; for example, the display device 1000 may be the watch shown in FIG2 .

[0084] It should be noted that, depending on different application scenarios, the display device 1000 can be a flat display device, a curved display device, a foldable display device, etc., and the shape of the display surface of the display device 1000 can be any one of a circular, elliptical, polygonal or irregular shape, which is not specifically limited in the embodiments of the present disclosure.

[0085] In the following, some embodiments of the present disclosure are schematically described by taking the display device 1000 as the mobile phone shown in FIG. 1 as an example, but the implementation manner of the present disclosure is not limited thereto.

[0086] 3 , a display device 1000 includes a display panel 100 , which may include a display side and a non-display side opposite to each other. The display side is the side of the display panel 100 used for display, i.e., the upper side in FIG3 .

[0087] The display panel 100 may be of various types and may be selected based on actual needs. For example, the display panel 100 may be an organic light emitting diode (OLED) display panel, a quantum dot light emitting diode (QLED) display panel, a micro light emitting diode (MicroLED) display panel, etc., and the present disclosure does not impose any specific limitations thereon.

[0088] In the following, some embodiments of the present disclosure are schematically described by taking the display panel 100 as an OLED display panel as an example.

[0089] For example, as shown in FIG3 , the display device 1000 may further include a housing 200 , a cover plate 300 , a circuit board 400 , and other electronic components.

[0090] 3 , the cover plate 300 may be a single-layer glass cover plate, or may include a stack of multiple sub-cover plates, which is not specifically limited in the embodiment of the present disclosure.

[0091] As shown in Figure 3, the longitudinal cross-section of the housing 200 can be, for example, U-shaped. The display panel 100 and the circuit board 400 are disposed within the housing 200, and the cover plate 300 is disposed at the opening of the housing 200. The circuit board 400 can be bonded to the display panel 100 at the end on the display side of the display panel 100 to provide the required display signals to the display panel 100. Furthermore, the circuit board 400 can be bent to the non-display side of the display panel 100, for example, to reduce the bezel of the display panel 100 and increase the screen-to-body ratio.

[0092] In some embodiments, referring to FIG. 4A , the display panel 100 has a display area A, which is a region for displaying images and is configured to dispose a plurality of sub-pixels P.

[0093] For example, referring to FIG. 4A , the display panel 100 includes a substrate 110 and a plurality of sub-pixels P disposed on one side of the substrate 110 and located in a display area A.

[0094] There are various types of the substrate 110 , which can be selected according to actual needs.

[0095] For example, the substrate 110 may be a rigid substrate, such as a glass substrate or a polymethyl methacrylate (PMMA) substrate.

[0096] For another example, the substrate 110 may be a flexible substrate, such as a polyethylene terephthalate (PET) substrate, a polyethylene naphthalate (PEN) substrate, or a polyimide (PI) substrate.

[0097] 4A and 5 , the sub-pixel P includes a light emitting device 10 and a pixel circuit 20 . The pixel circuit 20 includes a plurality of transistors 30 .

[0098] As shown in FIG. 5 , the transistor 30 includes a semiconductor channel 31 , a source 32 , a drain 33 , and a gate 34 . The source 32 and the drain 33 are both in contact with the semiconductor channel 31 .

[0099] As shown in Figure 5 , the light-emitting device 10 includes an anode 11, a light-emitting functional layer 12, and a cathode 13. The anode 11 is electrically connected to the source 32 or drain 33 of a transistor 30, and the cathode is connected to the second power signal terminal VSS (see Figure 6 ). Figure 5 illustrates the electrical connection between the anode 11 and the drain 33 of the thin-film transistor 30. It should be noted that the second power signal received by the second power signal terminal VSS can be a signal from the negative electrode of a DC power supply.

[0100] It should be noted that the above-mentioned light-emitting functional layer 12 may include only a light-emitting layer, or, in addition to the light-emitting layer, may also include at least one of an electron transporting layer (ETL), an electron injection layer (EIL), a hole transporting layer (HTL) and a hole injection layer (HIL).

[0101] In related technologies, when a display panel displays at a low frequency (e.g., less than or equal to 60 Hz), the human eye can perceive flickering in the displayed image. Research has found that during the display panel's display process, the image from the previous moment (the previous frame) often remains in the image displayed at the next moment, causing the displayed image to flicker. A frame refers to the time it takes for a display panel to display a still image.

[0102] Based on this, referring to FIG. 6 and FIG. 7 , some embodiments of the present disclosure provide a pixel circuit 20 , which includes a driving sub-circuit 21 , a data writing sub-circuit 22 , a first reset sub-circuit 23 , and a second reset sub-circuit 24 .

[0103] As shown in FIG8 , FIG9 and FIG10 , one frame F includes one refresh period F1 , and the refresh period F1 includes a first reset phase P11 and a data writing phase P12 , and the first reset phase P11 is located before the data writing phase P12 .

[0104] In some examples, referring to FIG6 , the driver sub-circuit 21 is coupled to the first node N1, the second node N2, and the third node N3. The driver sub-circuit 21 is configured to control the conduction and cutoff of the circuit between the second node N2 and the third node N3 under the control of the voltage of the first node N1; and to generate a grayscale current signal according to the voltage of the first node N1 and the voltage of the second node N2.

[0105] Exemplarily, as shown in Figure 7, the driving sub-circuit 21 includes a fourth transistor T4 (i.e., the driving transistor mentioned above), the first electrode of the fourth transistor T4 is connected to the second node N2, the second electrode of the fourth transistor T4 is connected to the third node N3, and the control electrode of the fourth transistor T4 is connected to the first node N1, and the structure is simple.

[0106] In some examples, referring to FIG6 , the data writing sub-circuit 22 is connected to the first scan signal terminal G1, the data signal terminal DATA, and the second node N2. The data writing sub-circuit 22 is configured to, during a data writing phase P12 (see FIG8 ), transmit a data signal received at the data signal terminal DATA to the second node N2 in response to the first scan signal received at the first scan signal terminal G1. Furthermore, the data signal at the second node N2 is compensated and then written to the first node N1 to facilitate subsequent generation of a grayscale current signal by the driving sub-circuit 21. For details, see below.

[0107] Exemplarily, as shown in FIG7 , the data writing sub-circuit 22 includes a fifth transistor T5 , a first electrode of the fifth transistor T5 is connected to the data signal terminal DATA, a second electrode of the fifth transistor T5 is connected to the second node N2 , and a control electrode of the fifth transistor T5 is connected to the first scan signal terminal G1 .

[0108] In some examples, referring to FIG6 , the first reset sub-circuit 23 is connected to the first initialization signal terminal INIT1, the first reset signal terminal R1, and the first node N1. The first reset sub-circuit 23 is configured to, in a first reset phase P11 (see FIG8 ), in response to the first reset signal received at the first reset signal terminal R1, transmit the first initialization signal received at the first initialization signal terminal INIT1 to the first node N1 to reset the voltage of the first node N1, eliminate the effect of the data signal of the previous frame F on the voltage of the first node N1, improve the afterimage performance, reduce the flicker value of the display panel 100, and alleviate the problem of flicker on the display screen that can be perceived by the human eye.

[0109] For example, as shown in FIG7 , the first reset sub-circuit 23 may include a plurality of first transistors T1 connected in series, wherein the control electrodes of the first transistors T1 are connected to the first reset signal terminal R1. Furthermore, two first transistors T1 at both ends of the plurality of first transistors connected in series have a first electrode connected to the first initialization signal terminal INIT1, and a second electrode connected to the first node N1, to reduce leakage current between the first node N1 and the first initialization signal terminal INIT1.

[0110] For example, as shown in FIG7 , the first reset sub-circuit 23 includes two first transistors T1 connected in series. A first electrode of one of the two first transistors T1 is connected to the first initialization signal terminal INIT1, a second electrode is connected to the first electrode of the other transistor, and a second electrode of the other transistor is connected to the first node N1. In this case, while effectively reducing leakage current between the first node N1 and the first initialization signal terminal INIT1, the first reset sub-circuit 23 includes fewer first transistors T1, thereby reducing the occupied area of ​​the pixel circuit 20.

[0111] In some examples, referring to FIG6 , the second reset sub-circuit 24 is connected to the second initialization signal terminal INIT2, the second reset signal terminal R2, and the second node N2. The second reset sub-circuit 24 is configured to, in response to the second reset signal received at the second reset signal terminal R2 during a first reset phase P11 (see FIG8 ), transmit the second initialization signal received at the second initialization signal terminal INIT2 to the second node N2 to reset the voltage of the second node N2, thereby clearing the effect of the data signal of the previous frame F on the voltage of the second node N2, improving afterimage performance, reducing the flicker value of the display panel 100, and alleviating the problem of flicker on the display screen that can be perceived by the human eye.

[0112] Exemplarily, as shown in FIG7 , the second reset sub-circuit 24 includes a second transistor T2 , a first electrode of the second transistor T2 is connected to the second initialization signal terminal INIT2 , a second electrode of the second transistor T2 is connected to the second node N2 , and a control electrode of the second transistor T2 is connected to the second reset signal terminal R2 , and has a simple structure.

[0113] The first transistor T1 and the second transistor T2 can both be P-type transistors, for example. The non-operating voltage of the first reset signal received at the first reset signal terminal R1 is lower than the non-operating voltage of the second reset signal received at the second reset signal terminal R2. In this case, the non-operating voltage at the first reset signal terminal R1 is lower, and during the process of switching from the operating voltage to the non-operating voltage, the voltage rise of the circuit wiring between the plurality of first transistors T1 connected in series can be reduced, thereby further reducing the leakage current of the first node N1.

[0114] In addition, in the first reset phase P11, the voltage of the second initialization signal is different from the voltage of the first initialization signal. For example, the voltage of the second initialization signal is greater than the voltage of the first initialization signal. In this case, before the data writing phase P12, in the first reset phase P11, the first reset sub-circuit 23 transmits the first initialization signal received at the first initial switching signal terminal INIT1 to the first node N1, and the second reset sub-circuit 24 transmits the second initialization signal received at the second initial switching signal terminal INIT2 to the second node N2, and the voltage of the second node N2 is greater than the voltage of the first node N1, so that the driving sub-circuit 21 is in a strong negative bias state, which can improve the hysteresis effect of the driving sub-circuit 21, thereby improving the afterimage performance, reducing the flicker value of the display panel 100, and improving the problem that the human eye can perceive flickering on the display screen.

[0115] In the first reset phase P11, the absolute value of the difference between the voltage of the second initialization signal and the voltage of the first initialization signal can be, for example, 10V to 13V, so that the minimum perceptible color difference can reach below 5.5, the color difference of the display panel 100 is small, and the display effect is better.

[0116] In the first reset phase P11, the difference between the voltage of the second initialization signal and the voltage of the first initialization signal is 10V, and the difference between the voltage of the second initialization signal and the voltage of the first initialization signal is 13V. Three display panels 100 are tested to obtain just noticeable color differences (JNCDs). The test results are shown in FIG12. In FIG12, the horizontal axis represents different display panels, and the vertical axis represents JNCDs.

[0117] As can be seen from Figure 12, when the difference between the voltage of the second initialization signal and the voltage of the first initialization signal is 10V, the minimum perceptible color difference can reach below 3.0; when the difference between the voltage of the second initialization signal and the voltage of the first initialization signal is 13V, the minimum perceptible color difference can reach below 5.5.

[0118] In some embodiments, referring to FIG. 8 , a refresh cycle F1 further includes a second reset phase P13 and a first light-emitting phase P14 , and the second reset phase P13 is located between the data writing phase P12 and the first light-emitting phase P14 .

[0119] On this basis, the second reset sub-circuit 24 is also configured to, in the second reset stage P13, in response to the second reset signal received at the second reset signal terminal R2, transmit the second initialization signal received at the second initial switching signal terminal INIT2 to the second node N2, so as to reset the voltage of the second node N2 and clear the influence of the data signal written in the previous data writing stage P12 on the voltage of the second node N2.

[0120] In this case, after the data writing stage P12, in the second reset stage P13, the second reset sub-circuit 24 transmits the second initialization signal received at the second initial switching signal terminal INIT2 to the second node N2, clearing the influence of the data signal written in the data writing stage P12 on the voltage of the second node N2. In this way, the deviation of the generated grayscale current signal caused by the grayscale difference of different sub-pixels P can be eliminated, thereby improving the accuracy of the grayscale current signal and improving the display quality.

[0121] In some embodiments, referring to FIG6 , the pixel circuit 20 further includes a third reset sub-circuit 25 connected to a fourth node N4, a third reset signal terminal R3, and a third initialization signal terminal INIT3. The fourth node N4 is configured to be connected to the anode of the light-emitting device 10. The third reset sub-circuit 25 is configured to transmit the third initialization signal received at the third initialization signal terminal INIT3 to the fourth node N4 in response to the third reset signal received at the third reset signal terminal R3 during the first reset phase P11 (see FIG8 ).

[0122] In this case, in the first reset stage P11, the voltage of the fourth node N4 can also be reset to clear the voltage of the fourth node N4 of the previous frame F, eliminate the difference in the voltage of the fourth node N4 caused by the grayscale difference of different sub-pixels P, improve the difference in the lighting speed of the light-emitting device 10 of different sub-pixels P, and improve the display quality.

[0123] Exemplarily, as shown in FIG7 , the third reset sub-circuit 25 includes a sixth transistor T6 , a first electrode of the sixth transistor T6 is connected to the third initialization signal terminal INIT3 , a second electrode of the sixth transistor T6 is connected to the fourth node N4 , and a control electrode of the sixth transistor T6 is connected to the third reset signal terminal R3 , and has a simple structure.

[0124] In addition, the signals of the third reset signal terminal R3 and the second reset signal terminal R2 can be the same. In this way, the third reset signal terminal R3 and the second reset signal terminal R2 can be connected to the same gate drive circuit through the same gate line, which can simplify the circuit structure. For details, please refer to the following.

[0125] In some embodiments, referring to FIG. 4A , the display panel 100 has a first refresh rate and a second refresh rate, where the second refresh rate is less than the first refresh rate. That is, the display panel 100 is a variable refresh rate display panel 100 to meet the user's needs for low power consumption and high refresh rate. In this case, the display panel 100 can, for example, display at high and low frequencies of 30 Hz, 40 Hz, 60 Hz, and 120 Hz, or at high and low frequencies of 40 Hz, 55 Hz, 82 Hz, and 165 Hz, although the embodiments of the present disclosure are not limited thereto.

[0126] That is, referring to Figures 7, 8, and 11, the pixel circuit 20 has a first refresh frequency and a second refresh frequency. At the first refresh frequency, a frame F includes a refresh period F1. At the second refresh frequency, a frame F also includes at least one hold period F2, and at least one hold period F2 is located after the refresh period F1. For example, at the second refresh frequency, a frame F includes a refresh period F1 and a hold period F2.

[0127] As shown in FIG11 , the hold period F2 includes at least one third reset phase P21 and a second light-emitting phase P22, with at least one third reset phase P21 preceding the second light-emitting phase P22. For example, as shown in FIG11 , the hold period F2 includes two third reset phases P21 and one second light-emitting phase P22, so that the third reset signal exhibits periodic changes, facilitating design. Furthermore, the hold period F2 can reset the voltage of the fourth node N4 (see FIG7 ) twice, thereby better eliminating the influence of the data signal of the previous refresh period F1 on the voltage of the fourth node N4 (see FIG7 ), thereby further improving the display effect.

[0128] On this basis, the third reset sub-circuit 25 is further configured to, in the third reset stage P21, in response to the third reset signal received at the third reset signal terminal R3, transmit the third initialization signal received at the third initialization signal terminal INIT3 to the fourth node N4, so as to avoid the long-term setting of the fourth transistor T4 of the driving sub-circuit 21 causing the threshold voltage shift, and can reset the voltage of the fourth node N4, clear the voltage of the fourth node N4 in the previous refresh cycle F1, eliminate the difference in the voltage of the fourth node N4 caused by the grayscale difference of different sub-pixels P, and improve the difference in the lighting speed of the light-emitting devices 10 of different sub-pixels P, thereby further reducing the flicker value of the display panel 100 and improving the problem that the human eye can perceive the flickering of the display screen.

[0129] In addition, referring to Figures 6 and 11 , the voltage of the third reset signal during the refresh period F1 is different from the voltage during the hold period F2. The pixel circuit 20 further includes a first storage subcircuit 26, which is connected to the first voltage signal terminal V1 and the fourth node N4. The first storage subcircuit 26 is configured to, during the first reset phase P11 and the third reset phase P21, pull up or down the voltage of the fourth node N4 in response to the first voltage signal received at the first voltage signal terminal V1.

[0130] Exemplarily, as shown in FIG7 , the first storage subcircuit 26 includes a first capacitor C1 , a first plate of the first capacitor C1 is connected to the first voltage signal terminal V1 , and a second plate of the first capacitor C1 is connected to the fourth node N4 , having a simple structure and a fast response speed.

[0131] Furthermore, the voltage of one of the third reset signal and the first voltage signal during the refresh period F1 is greater than the voltage during the hold period F2, and the voltage of the other during the hold period F2 is greater than the voltage during the refresh period F1. For example, the voltage of the third reset signal during the refresh period F1 is greater than the voltage during the hold period F2, and the voltage of the first voltage signal during the hold period F2 is greater than the voltage during the refresh period F1.

[0132] At this time, in the third reset stage P21, the first storage sub-circuit 26 can pull down the voltage of the fourth node N4 to reduce the impact of the third reset signal on the voltage increase of the fourth node N4 in the third reset stage P21, thereby reducing the sudden change in the brightness of the light-emitting device 10 during the switching between the refresh period F1 and the holding period F2, thereby reducing the flicker value of the display panel 100 and improving the problem that the human eye can perceive flickering in the display screen.

[0133] Figure 13 shows a graph of flicker values ​​of a display panel in the related art as they change over time. Figure 14 shows a graph of flicker values ​​of a display panel in accordance with some embodiments as they change over time. The pixel circuit of the display panel in the related art shown in Figure 13 does not include the first storage sub-circuit, while the pixel circuit of the display panel in Figure 14 does include the first storage sub-circuit.

[0134] As can be seen from Figures 13 and 14, the first storage sub-circuit 26 can significantly reduce the sudden change in the brightness of the light-emitting device 10 (see Figure 5) during the switching process between the refresh period F1 and the hold period F2, thereby reducing the flicker value of the display panel 100 (see Figure 5) and improving the problem of flickering on the display screen that can be perceived by the human eye.

[0135] The signals at the first voltage signal terminal V1 and the second initialization signal terminal INIT2 can be the same. That is, the voltage at the second initialization signal terminal INIT2 during the hold period F2 can be greater than the voltage during the refresh period F1. In this way, the first voltage signal terminal V1 and the second initialization signal terminal INIT2 can be connected to the same gate drive circuit via the same gate line, which can simplify the circuit structure. For details, please refer to the following.

[0136] In some embodiments, referring to FIG6 , the pixel circuit 20 further includes a compensation sub-circuit 27 connected to the first node N1, the third node N3, and the second scan signal terminal G2. The compensation sub-circuit 27 is configured to, in response to the second scan signal received at the second scan signal terminal G2 during a data writing phase P12 (see FIG8 ), transmit the voltage of the third node N3 to the first node N1 to write the compensated data signal into the first node N1.

[0137] Exemplarily, as shown in Figure 7, the compensation sub-circuit 27 includes a plurality of third transistors T3 connected in series, and the control electrode of the third transistor T3 is connected to the second scan signal terminal; two third transistors T3 located at both ends of the plurality of third transistors T3 connected in series, one of which has a first electrode connected to the third node N3, and the other has a second electrode connected to the first node N1, so as to reduce the leakage current between the first node N1 and the third node N3.

[0138] For example, as shown in FIG7 , the compensation sub-circuit 27 includes two third transistors T3 connected in series. Of the two third transistors T3, a first electrode of one is connected to the third node N3, a second electrode is connected to the first electrode of the other, and a second electrode of the other is connected to the first node N1. In this case, while effectively reducing leakage current between the first node N1 and the third node N3, the compensation sub-circuit 27 includes fewer third transistors T3, thereby reducing the occupied area of ​​the pixel circuit 20.

[0139] The second transistor T2 and the third transistor T3 can both be P-type transistors, for example. The non-operating voltage of the second scan signal received at the second scan signal terminal G2 is lower than the non-operating voltage of the second reset signal received at the second reset signal terminal R2. In this case, the non-operating voltage at the second scan signal terminal G2 is lower, and during the process of switching from the operating voltage to the non-operating voltage, the voltage rise of the circuit wiring between the plurality of third transistors T3 connected in series can be reduced, thereby further reducing the leakage current of the first node N1.

[0140] In some embodiments, referring to FIG. 6 , the pixel circuit 20 further includes a first light emitting control subcircuit 281 and a second light emitting control subcircuit 282 .

[0141] In some examples, referring to FIG6 , the first light-emitting control subcircuit 281 is connected to the second node N2, the first power signal terminal VDD, and the first enable signal terminal EM1. The first light-emitting control subcircuit 281 is configured to, during a light-emitting phase (the first light-emitting phase P14 and / or the second light-emitting phase P22), in response to a first enable signal received at the first enable signal terminal EM1, transmit the first power signal at the first power signal terminal VDD to the second node N2, so that the driver subcircuit 21 can generate a grayscale current signal based on the voltage at the first node N1 and the voltage at the second node N2. It should be noted that the first power signal can be a signal at the positive electrode of a DC power supply.

[0142] Exemplarily, as shown in Figure 7, the first light-emitting control sub-circuit 281 includes a seventh transistor T7, the first electrode of the seventh transistor T7 is connected to the first power signal terminal VDD, the second electrode of the seventh transistor T7 is connected to the second node N2, and the control electrode of the seventh transistor T7 is connected to the first enable signal terminal EM1, and the structure is simple.

[0143] In some examples, referring to FIG6 , the second light-emitting control subcircuit 282 is connected to the third node N3, the fourth node N4, and the second enable signal terminal EM2. The second light-emitting control subcircuit 282 is configured to, in a light-emitting phase (the first light-emitting phase P14 and / or the second light-emitting phase P22), transmit the voltage of the third node N3 to the fourth node N4 in response to the second enable signal received at the second enable signal terminal EM2, so that the grayscale current signal can be transmitted to the light-emitting device 10, thereby driving the light-emitting device 10 to emit light.

[0144] Exemplarily, as shown in Figure 7, the second light-emitting control sub-circuit 282 includes an eighth transistor T8, the first electrode of the eighth transistor T8 is connected to the third node N3, the second electrode of the eighth transistor T8 is connected to the fourth node N4, and the control electrode of the eighth transistor T8 is connected to the second enable signal terminal EM2, and the structure is simple.

[0145] During the light-emitting phase (the first light-emitting phase P14 and / or the second light-emitting phase P22), the start time of the operating voltage of the first enable signal may, for example, be before the start time of the operating voltage of the second enable signal. In this case, the first light-emitting control subcircuit 281 is turned on first, and the grayscale current signal can be pre-written to the third node N3. Then, the second light-emitting control subcircuit 282 is turned on, and the grayscale current signal can be quickly written from the third node N3 to the fourth node N4 to drive the light-emitting device 10, thereby improving the display quality of the display panel 100.

[0146] 6 , the pixel circuit 20 further includes a second storage subcircuit 29 connected to the first power signal terminal VDD and the first node N1. The second storage subcircuit 29 is configured to store the voltage of the first node N1 to stabilize the voltage.

[0147] Exemplarily, as shown in FIG7 , the second storage subcircuit 29 includes a second capacitor C2 , a first plate of the second capacitor C2 is connected to the first power signal terminal VDD, and a second plate of the first capacitor C1 is connected to the first node N1 , and has a simple structure.

[0148] Referring to FIG. 4A , a display panel 100 according to an embodiment of the present disclosure includes the pixel circuit 20 according to any of the aforementioned embodiments. For example, the display panel 100 includes a plurality of pixel circuits 20 arranged in multiple rows and columns. Each row includes a plurality of pixel circuits 20 arranged along a first direction X, and each column includes a plurality of pixel circuits 20 arranged along a second direction Y. The first direction X intersects the second direction Y. For example, the first direction X is substantially perpendicular to the second direction Y.

[0149] It should be noted that the first direction X may be, for example, a row direction in which the plurality of pixel circuits 20 are arranged, and the second direction Y may be, for example, a column direction in which the plurality of pixel circuits 20 are arranged.

[0150] In the following, some embodiments of the present disclosure are exemplarily described by taking the arrangement of all pixel circuits 20 in multiple rows and columns as an example, but the embodiments of the present disclosure are not limited thereto.

[0151] On this basis, as shown in FIG4A , the display panel 100 further includes a gate line GL, a data line DL, a first power line VDL, and a first initialization signal line VL1 , a second initialization signal line VL2 , and a third initialization signal line VL3 .

[0152] As shown in FIG4A , each gate line GL extends substantially along a first direction X and is configured to transmit a control signal, wherein the control signal includes any one of a first scan signal, a second scan signal, a first reset signal, a second reset signal, a third reset signal, a first enable signal, and a second enable signal. For example, a gate line GL may be connected to any one of a first scan signal terminal G1, a second scan signal terminal G2, a first reset signal terminal R1, a second reset signal terminal R2, a third reset signal terminal R3, a first enable signal terminal EM1, or a second enable signal terminal EM2 of a row of pixel circuits 20.

[0153] 4A and 6 , the data lines DL extend substantially along the second direction Y and are configured to transmit data signals. For example, one data line DL may be connected to a data signal terminal DATA of a column of pixel circuits 20 .

[0154] 4A and 6 , the first power line VDL extends substantially along the second direction Y and is configured to transmit a first power voltage signal. For example, one first power line VDL may be connected to the first voltage signal terminal VDD of a column of pixel circuits 20 .

[0155] As shown in Figures 4A and 6, the first initialization signal line VL1, the second initialization signal line VL2, and the third initialization signal line VL3 can, for example, extend substantially along the first direction X and be configured to transmit the first initialization signal, the second initialization signal, and the third initialization signal, respectively. The first initialization signal line VL1, the second initialization signal line VL2, and the third initialization signal line VL3 can, for example, be connected to the first initialization signal terminal INIT1, the second initialization signal terminal INIT2, and the third initialization signal terminal INIT3, respectively, of a column of pixel circuits 20.

[0156] In some embodiments, as shown in Figure 5, along a direction perpendicular to the substrate 110 and away from the substrate 110, the display panel 100 includes a substrate 110, a semiconductor layer ACT, a first gate insulation layer GI1, a first gate conductive layer GT1, a second gate insulation layer GI2, a second gate conductive layer GT2, an interlayer insulating layer ILD, a first source and drain conductive layer SD1, a first planar layer PLN1, a second source and drain conductive layer SD2, and a second planar layer PLN2.

[0157] On this basis, referring to Figures 4A and 5 , the semiconductor channel 31 of the transistor 30 can be, for example, located in the semiconductor layer ACT, and the gate line GL, the transistor's gate 34, and the first plates of the capacitors (first capacitor C1 and second capacitor C2) can be, for example, located in the first gate conductive layer GT1. The second plates of the capacitors (first capacitor C1 and second capacitor C2), the first initialization signal line VL1, the second initialization signal line VL2, and the third initialization signal line VL3 can be, for example, located in the second gate conductive layer GT2. The source 32, drain 33, and first power line VDL of the transistor 30 can be, for example, located in the first source-drain conductive layer SD1. The data line DL can be, for example, located in the second source-drain conductive layer SD2.

[0158] In some embodiments, as shown in FIG. 5 , the display panel 100 further includes a pixel defining layer (PDL). The pixel defining layer (PDL) is provided with a plurality of openings, and one light emitting device 10 is located in one opening.

[0159] In some embodiments, as shown in FIG. 5 , the display panel 100 further includes spacers PS. The spacers PS may be disposed between the pixel defining layer PDL and the light emitting function layer 12 to support the mask during the process.

[0160] In some embodiments, as shown in FIG5 , the display panel 100 further includes an encapsulation layer 120 . The encapsulation layer 120 is disposed on a side of the light-emitting device 10 away from the substrate 110 to reduce the risk of water and oxygen corrosion. The encapsulation layer 120 may be an encapsulation film or an encapsulation substrate, which is not specifically limited in the present disclosure.

[0161] In some embodiments, referring to FIG. 4A , the display panel 100 further includes a peripheral region B, which is disposed on at least one side of the display region A. Peripheral region B is a region that does not display an image and is configured to house, for example, the gate driver circuit 130 and the source driver circuit 140 . FIG. 4A illustrates an example in which peripheral region B surrounds the display region A.

[0162] 4A , the display panel 100 includes a gate driving circuit 130 , which is disposed on one side of the display area A along a first direction X, and drives each row of pixel circuits 20 row by row from a single side of the display area A, forming a single-sided drive.

[0163] For example, referring to FIG. 4B , the display panel 100 includes a gate driving circuit 130 . Along a first direction X, the gate driving circuit 130 is disposed on opposite sides of the display area A. The two gate driving circuits 130 drive the pixel circuits 20 in each row sequentially from opposite sides of the display area A at the same time, thereby forming a double-sided drive.

[0164] Some embodiments of the present disclosure are schematically described below using single-sided driving as an example, but the embodiments of the present disclosure are not limited thereto.

[0165] In some embodiments, referring to FIG15 , a plurality of pixel circuits 20 are arranged in M ​​rows and N columns, with each row including N pixel circuits 20 arranged along a first direction X, and each column including M pixel circuits 20 arranged along a second direction Y. M>1, N>1, and M and N are integers. FIG15 illustrates M=2170 as an example.

[0166] In some examples, as shown in FIG15 , the gate driver circuit 130 includes a first gate driver circuit 131. The first gate driver circuit 131 includes M+Q cascaded first shift registers RS1. From the first-stage first shift register RS1 to the last-stage first shift register RS1, the M+Q first shift registers RS1 are the 1st to the M+Qth first shift registers RS1, respectively. FIG15 illustrates an example where Q is 7.

[0167] 7 and 15 , the first shift register RS1 includes a first signal output terminal. The first reset signal terminal R1 of the P-th row of pixel circuits 20 is connected to the first signal output terminal of the P-th first shift register RS1. The second scan signal terminal G2 of the P-th row of pixel circuits 20 is connected to the first signal output terminal of the P+Q-th first shift register RS1. P ≤ M, Q > 0, and P and Q are integers.

[0168] It should be noted that the first reset signal terminal R1 and the second scan signal terminal G2 of the P-th row pixel circuit 20 can be respectively connected to the first signal output terminals of the P-th first shift register RS1 and the P+Q-th first shift register RS1 through different gate lines GL.

[0169] In this case, the first gate driver circuit 131 can provide the first reset signal and the second scan signal to the first reset signal terminal R1 and the second scan signal terminal G2 of all pixel circuits 20, respectively. In other words, the first reset signal terminal R1 and the second scan signal terminal G2 of a pixel circuit 20 can share a first gate driver circuit 131, which is beneficial to the narrow-frame design of the display device 1000 (see FIG. 1 ).

[0170] In some examples, as shown in Figure 15, the gate drive circuit 130 includes a second gate drive circuit 132, and the second gate drive circuit 132 includes M cascaded second shift registers RS2, from the first-stage second shift register RS2 to the last-stage second shift register RS2, and the M second shift registers RS2 are respectively the 1st to the Mth second shift registers RS2.

[0171] 7 and 15 , the second shift register RS2 includes a second signal output terminal, and the second reset signal terminal R2 and the third reset signal terminal R3 of the P-th row of pixel circuits 20 are connected to the second signal output terminal of the P-th second shift register RS2, where P≤M, and P is an integer.

[0172] It should be noted that the second reset signal terminal R2 and the third reset signal terminal R3 of the pixel circuit 20 in the P-th row may be connected to the second signal output terminal of the P-th second shift register RS2 through the same gate line GL.

[0173] In this case, the second gate driver circuit 132 can provide the second reset signal and the third reset signal, respectively, to the second reset signal terminal R2 and the third reset signal terminal R3 of all pixel circuits 20. In other words, the second reset signal terminal R2 and the third reset signal terminal R3 of a pixel circuit 20 can share the same gate line GL and be connected to the same second gate driver circuit 132, which simplifies the structure and facilitates a narrow-frame design of the display device 1000 (see FIG. 1 ).

[0174] In some examples, as shown in FIG. 15 , the gate driving circuit 130 includes a third gate driving circuit 133 and a fourth gate driving circuit 134 .

[0175] As shown in Figures 7 and 15, the third gate drive circuit 133 includes M cascaded third shift registers RS3. From the first stage third shift register RS3 to the last stage third shift register RS3, the M third shift registers RS3 are respectively the first to Mth third shift registers RS3. Among them, the third shift register RS3 includes a third signal output terminal, and the first enable signal terminal EM1 of the P-th row pixel circuit 20 is connected to the third signal output terminal of the P-th third shift register RS3, where P≤M, and P is an integer.

[0176] As shown in Figures 7 and 15, the fourth gate drive circuit 134 includes M cascaded fourth shift registers RS4. From the first stage of the fourth shift register RS4 to the last stage of the fourth shift register RS4, the M fourth shift registers RS4 are respectively the first to the Mth fourth shift registers RS4. Among them, the fourth shift register RS4 includes a fourth signal output terminal, and the second enable signal terminal EM2 of the P-th row of pixel circuits 20 is connected to the fourth signal output terminal of the P-th fourth shift register RS4, where P≤M, and P is an integer.

[0177] It should be noted that the first enable signal terminal EM1 and the second enable signal terminal EM2 of the P-th row pixel circuit 20 can be connected to the third signal output terminal of the P-th third shift register RS3 and the fourth signal output terminal of the P-th fourth shift register RS4 respectively through different gate lines GL.

[0178] In this case, the first enable signal terminal EM1 and the second enable signal terminal EM2 of the pixel circuit 20 are connected to the third gate driver circuit 133 and the fourth gate driver circuit 134, respectively, through different gate lines GL. That is, the first enable signal terminal EM1 and the second enable signal terminal EM2 of the pixel circuit 20 are controlled by different gate driver circuits 130, which makes the control timing of the first enable signal and the second enable signal more flexible, thereby improving the control accuracy of the pixel circuit 20.

[0179] In some examples, as shown in FIG7 and FIG15 , the gate driving circuit 130 includes a fifth gate driving circuit 135. The fifth gate driving circuit 135 includes M cascaded fifth shift registers RS5. From the first stage fifth shift register RS5 to the last stage fifth shift register RS5, the M fifth shift registers RS5 are respectively the first to the Mth fifth shift registers RS5. The fifth shift register RS5 includes a fifth signal output terminal. The first scan signal terminal G1 of the P-th row of pixel circuits 20 is connected to the fifth signal output terminal of the P-th fifth shift register RS5. P ≤ M, and P is an integer.

[0180] It should be noted that the first scanning signal terminal G1 of the pixel circuit 20 in the P-th row may be connected to the fifth signal output terminal of the fifth shift register RS5 through the gate line GL.

[0181] In this case, the first scanning signal terminal G1 of the pixel circuit 20 is connected to the fifth gate driving circuit 135 through the gate line GL. That is, the first scanning signal terminal G1 of the pixel circuit 20 is controlled by a single gate driving circuit 130. The control timing of the first scanning signal terminal G1 is more flexible, which is conducive to improving the control accuracy of the pixel circuit 20.

[0182] Some embodiments of the present disclosure further provide a method for driving a pixel circuit 20, for driving the pixel circuit 20 according to any of the above embodiments. Referring to FIG. 8 , a frame F includes a refresh period F1, which includes a first reset phase P11 and a data write phase P12, wherein the first reset phase P11 precedes the data write phase P12.

[0183] It should be understood that the difference between the start time of the data writing phase P12 and the end time of the first reset phase P11 can be greater than or equal to one row scanning period H, so as to reduce the risk of the rising and falling edges of various signals in the first reset phase P11 and the data writing phase P12 intersecting, thereby affecting data writing or resetting. The row scanning period H can be the duration of one operating voltage of the first scanning signal.

[0184] As shown in Figures 7 and 8, during the first reset phase P11, the first reset sub-circuit 23 transmits the first initialization signal received at the first initial switching signal terminal INIT1 to the first node N1 in response to the first reset signal received at the first reset signal terminal R1. The second reset sub-circuit 24 transmits the second initialization signal received at the second initial switching signal terminal INIT2 to the second node N2 in response to the second reset signal received at the second reset signal terminal R2. Furthermore, the driver sub-circuit 21, under the control of the voltage of the first node N1, controls the conduction of the circuit between the second node N2 and the third node N3 to transmit the second initialization signal to the third node N3.

[0185] That is, in the first reset phase P11, the first node N1, the second node N2 and the third node N3 are reset to clear the influence of the data signal of the previous frame F on the voltages of the first node N1, the second node N2 and the third node N3, thereby improving display quality.

[0186] As shown in Figures 7 and 8, when the pixel circuit 20 also includes a third reset sub-circuit 25, in the first reset phase P11, the third reset sub-circuit 25 also responds to the third reset signal received at the third reset signal terminal R3 and transmits the third initialization signal received at the third initialization signal terminal INIT3 to the fourth node N4.

[0187] That is, in the first reset stage P11, the voltage of the fourth node N4 is also reset to clear the voltage of the fourth node N4 of the previous frame F, eliminate the difference in the voltage of the fourth node N4 caused by the grayscale difference of different sub-pixels P, improve the difference in the lighting speed of the light-emitting device 10 of different sub-pixels P, and improve the display quality.

[0188] In addition, in the first reset phase P11, the voltage of the second initialization signal is greater than the voltage of the first initialization signal, so that the voltage of the second node N2 is greater than the voltage of the first node N1, so that the driving sub-circuit 21 is in a strong negative bias state, which can improve the hysteresis effect of the driving sub-circuit 21, thereby improving the afterimage performance, reducing the flicker value of the display panel 100, and improving the problem of flickering on the display screen that can be perceived by the human eye.

[0189] In some embodiments, as shown in FIG. 7 and FIG. 8 , the first reset phase P11 includes a first sub-segment P111 and a second sub-segment P112 . The first node N1 is reset in the first sub-segment P111 , and the second node N2 is reset in the second sub-segment P112 .

[0190] As shown in Figures 7 and 8, in the first sub-segment P111, the first reset sub-circuit 23 transmits the first initialization signal received at the first initialization signal terminal INIT1 to the first node N1 in response to the first reset signal received at the first reset signal terminal R1. The duration of the first sub-segment P111 can be, for example, 6, 7, 8, or 10 row scanning periods H, which is not specifically limited in the present embodiment.

[0191] As shown in Figures 7 and 8, in the second sub-segment P112, the second reset sub-circuit 24 transmits the second initialization signal received at the second initialization signal terminal INIT2 to the second node N2 in response to the second reset signal received at the second reset signal terminal R2. The duration of the second sub-segment P112 can be, for example, 6, 10, or 14 row scanning periods H, which is not specifically limited in the present embodiment.

[0192] Based on the above, the reset duration of the first node N1 and the reset duration of the second node N2 can be controlled separately, and the control timing of the reset of the first node N1 and the reset of the second node N2 is more flexible, which is conducive to improving the reset effect of the first node N1 and the second node N2.

[0193] Exemplarily, referring to Figures 8, 9 and 10, the first sub-segment P111 may be located before the second sub-segment P112 (not illustrated in Figures 8, 9 and 10); or, as shown in Figure 8, the first sub-segment P111 may be located after the second sub-segment P112; or, as shown in Figures 9 and 10, the first sub-segment P111 at least partially overlaps with the second sub-segment P112.

[0194] It should be understood that when the first sub-segment P111 is located before or after the second sub-segment P112, the difference between the first sub-segment P111 and the second sub-segment P112 can be greater than or equal to 1 row scanning period H, so as to reduce the risk of the rising edge and falling edge of each signal in the first sub-segment P111 and the second sub-segment P112 being interleaved.

[0195] For example, as shown in FIG9 and FIG10 , the first sub-segment P111 and the second sub-segment P112 at least partially overlap, so that the resetting effect of the first node N1 and the second node N2 is better, and the bias voltage of the driving sub-circuit 21 is larger, which is more conducive to improving the hysteresis effect of the driving sub-circuit 21, improving the afterimage performance, reducing the flicker value of the display panel 100, and improving the problem that the human eye can perceive flickering on the display screen.

[0196] As shown in Figures 7 and 8, during the data writing phase P12, the compensated data signal is written to the first node N1, and the second storage sub-circuit 29 is charged to store the compensated data signal. The duration of the data writing phase P12 can be, for example, the same as the duration of the first sub-segment P111.

[0197] In the data writing phase P12, the data writing sub-circuit 22 transmits the data signal received at the data signal terminal DATA to the second node N2 in response to the first scan signal received at the first scan signal terminal G1. The driving sub-circuit 21, under the control of the voltage of the first node N1, controls the conduction of the circuit between the second node N2 and the third node N3 to transmit the compensated data signal to the third node N3. The compensation sub-circuit 27 transmits the voltage of the third node N3 to the first node N1 in response to the second scan signal received at the second scan signal terminal G2 to write the compensated data signal to the first node N1.

[0198] At this time, the second storage subcircuit 29 can store the voltage of the first node N1 to play a role in voltage stabilization, thereby improving the accuracy of the grayscale current signal in the light-emitting stage (the first light-emitting stage P14 and the second light-emitting stage P22) and improving the display quality.

[0199] In some embodiments, referring to FIG. 8 , a refresh cycle F1 further includes a second reset phase P13 and a first light-emitting phase P14 , and the second reset phase P13 is located between the data writing phase P12 and the first light-emitting phase P14 .

[0200] It should be understood that the difference between the end time of the data writing phase P12 and the start time of the second reset phase P13 can be greater than or equal to one horizontal scanning period H, so as to reduce the risk of the rising and falling edges of various signals in the second reset phase P13 and the data writing phase P12 interleaving, thereby affecting data writing or resetting. Furthermore, the difference between the end time of the second reset phase P13 and the start time of the first light-emitting phase P14 can be greater than or equal to one horizontal scanning period H, so as to reduce the risk of the rising and falling edges of various signals in the second reset phase P13 and the first light-emitting phase P14 interleaving, thereby affecting the grayscale current signal.

[0201] As shown in Figures 7 and 8, in the second reset phase P13, the second reset sub-circuit 24, in response to the second reset signal received at the second reset signal terminal R2, transmits the second initialization signal received at the second initialization signal terminal INIT2 to the second node N2, thereby resetting the voltage of the second node N2 and clearing the effect of the data signal written in the data writing phase P12 on the voltage of the second node N2. The duration of the second reset phase P13 can be, for example, 6, 10, or 14 row scanning periods H, which is not specifically limited in the present embodiment.

[0202] In this case, after the data writing stage P12, the second node N2 is reset again, which can clear the influence of the data signal written in the data writing stage P12 on the voltage of the second node N2. This can eliminate the deviation of the grayscale current signal generated due to the grayscale difference of different sub-pixels P, thereby improving the accuracy of the grayscale current signal and improving the display quality.

[0203] As shown in Figures 7 and 8, when the pixel circuit 20 also includes a third reset sub-circuit 25, in the second reset phase P13, the third reset sub-circuit 25 also responds to the third reset signal received at the third reset signal terminal R3 and transmits the third initialization signal received at the third initialization signal terminal INIT3 to the fourth node N4.

[0204] That is, in the second reset stage P13, the voltage of the fourth node N4 is reset again. Resetting the fourth node N4 twice can better eliminate the adverse effects of the data signal of the previous refresh cycle F1 and the data writing stage P12 on the voltage of the fourth node N4, thereby further improving the display effect.

[0205] As shown in Figures 7 and 8, in the first light-emitting phase P14, the first light-emitting control sub-circuit 281 transmits the first power signal at the first power signal terminal VDD to the second node N2 in response to the first enable signal received at the first enable signal terminal EM1. The driving sub-circuit 21 can generate a grayscale current signal based on the voltage (data signal) at the first node N1 and the voltage (first power signal) at the second node N2, and transmit the grayscale current signal to the third node N3.

[0206] On this basis, as shown in Figures 7 and 8, the second light-emitting control subcircuit 282 transmits the voltage (grayscale current signal) of the third node N3 to the fourth node N4 in response to the second enable signal received at the second enable signal terminal EM2, so that the grayscale current signal can be transmitted to the light-emitting device 10, thereby driving the light-emitting device 10 to emit light.

[0207] As shown in FIG7 and FIG8 , in the first light-emitting stage P14, the start time of the operating voltage of the first enable signal may be, for example, before the start time of the operating voltage of the second enable signal. For example, the difference between the start time of the operating voltage of the first enable signal and the start time of the operating voltage of the second enable signal is greater than or equal to one horizontal scanning period H. For example, the difference between the start time of the operating voltage of the first enable signal and the start time of the operating voltage of the second enable signal is two horizontal scanning periods H.

[0208] In this case, the first light-emitting control subcircuit 281 is turned on first, the driving subcircuit 21 can first generate a grayscale current signal and pre-write the grayscale current signal to the third node N3, and then the second light-emitting control subcircuit 282 is turned on again, and the grayscale current signal can be quickly written from the third node N3 to the fourth node N4 to drive the light-emitting device 10, which can improve the display quality of the display panel 100.

[0209] In addition, as shown in Figures 7 and 8, in the first light-emitting stage P14, the cut-off time of the operating voltage of the first enable signal may be, for example, later than the cut-off time of the operating voltage of the second enable signal. For example, the difference between the cut-off time of the operating voltage of the first enable signal and the cut-off time of the operating voltage of the second enable signal is greater than or equal to one horizontal scanning period H. For example, the difference between the cut-off time of the operating voltage of the first enable signal and the cut-off time of the operating voltage of the second enable signal is one horizontal scanning period H.

[0210] In some embodiments, referring to FIG. 11 , a frame F includes a refresh period F1 and at least one hold period F2, wherein the at least one hold period F2 is located after the refresh period F1. Furthermore, the hold period F2 includes at least one third reset phase P21 and a second light-emitting phase P22, wherein the at least one third reset phase P21 is located before the second light-emitting phase P22.

[0211] It should be understood that the difference between the end time of the third reset stage P21 and the start time of the second light-emitting stage P22 can be greater than or equal to one row scanning period H, so as to reduce the risk of the rising edge and falling edge of each signal in the third reset stage P21 and the second light-emitting stage P22 being interlaced, thereby affecting the grayscale current signal.

[0212] As shown in FIG7 and FIG11 , in the third reset phase P21, the third reset sub-circuit 25 transmits the third initialization signal received at the third initialization signal terminal INIT3 to the fourth node N4 in response to the third reset signal received at the third reset signal terminal R3, thereby resetting the fourth node N4 and preventing a threshold voltage shift caused by a prolonged reset of the fourth transistor T4 of the driver sub-circuit 21. The duration of the third reset phase P21 may be, for example, the same as the duration of the second sub-segment P112 or the second reset phase P13.

[0213] In addition, resetting the voltage of the fourth node N4 can also clear the voltage of the fourth node N4 in the previous refresh cycle F1, eliminate the difference in the voltage of the fourth node N4 caused by the grayscale difference of different sub-pixels P, and improve the difference in the lighting speed of the light-emitting device 10 of different sub-pixels P, thereby further reducing the flicker value of the display panel 100 and improving the problem of flickering on the display screen that can be perceived by the human eye.

[0214] Furthermore, the voltage of the third reset signal during the refresh period F1 is different from the voltage during the hold period F2. During the third reset phase P21, the first storage sub-circuit 26 pulls up or down the voltage of the fourth node N4 in response to the first voltage signal received at the first voltage signal terminal V1. Here, the voltage of the first reset signal during the refresh period F1 is greater than the voltage during the hold period F2, and the voltage of the first reset signal during the hold period F2 is greater than the voltage during the refresh period F1.

[0215] That is to say, during the switching process between the refresh period F1 and the hold period F2, when the voltage change of the third reset signal pulls up the voltage of the fourth node N4, the first storage sub-circuit 26 pulls down the voltage of the fourth node N4; when the voltage change of the third reset signal pulls down the voltage of the fourth node N4, the first storage sub-circuit 26 pulls up the voltage of the fourth node N4.

[0216] In this way, the first storage subcircuit 26 can reduce the impact of the change of the third reset signal on the voltage of the fourth node N4, thereby reducing the sudden change in the brightness of the light-emitting device 10 during the switching between the refresh period F1 and the hold period F2, thereby reducing the flicker value of the display panel 100 and improving the problem that the human eye can perceive flickering in the display screen.

[0217] As shown in Figures 7 and 11, in the second light-emitting phase P22, the first light-emitting control sub-circuit 281 transmits the first power signal at the first power signal terminal VDD to the second node N2 in response to the first enable signal received at the first enable signal terminal EM1. The driving sub-circuit 21 can generate a grayscale current signal based on the voltage (data signal) at the first node N1 and the voltage (first power signal) at the second node N2, and transmit the grayscale current signal to the third node N3.

[0218] On this basis, as shown in Figures 7 and 11, the second light-emitting control subcircuit 282 transmits the voltage (grayscale current signal) of the third node N3 to the fourth node N4 in response to the second enable signal received at the second enable signal terminal EM2, so that the grayscale current signal can be transmitted to the light-emitting device 10, thereby driving the light-emitting device 10 to emit light.

[0219] As shown in FIG7 and FIG11 , in the second light-emitting stage P22, the start time of the operating voltage of the first enable signal may be, for example, before the start time of the operating voltage of the second enable signal. For example, the difference between the start time of the operating voltage of the first enable signal and the start time of the operating voltage of the second enable signal is greater than or equal to one horizontal scanning period H. For example, the difference between the start time of the operating voltage of the first enable signal and the start time of the operating voltage of the second enable signal is two horizontal scanning periods H.

[0220] In this case, the first light-emitting control subcircuit 281 is turned on first, the driving subcircuit 21 can first generate a grayscale current signal and pre-write the grayscale current signal to the third node N3, and then the second light-emitting control subcircuit 282 is turned on again, and the grayscale current signal can be quickly written from the third node N3 to the fourth node N4 to drive the light-emitting device 10, which can improve the display quality of the display panel 100.

[0221] In addition, as shown in Figures 7 and 11, in the second light-emitting stage P22, the cut-off time of the operating voltage of the first enable signal can be, for example, later than the cut-off time of the operating voltage of the second enable signal. For example, the difference between the cut-off time of the operating voltage of the first enable signal and the cut-off time of the operating voltage of the second enable signal is greater than or equal to one horizontal scanning period H. For example, the difference between the cut-off time of the operating voltage of the first enable signal and the cut-off time of the operating voltage of the second enable signal is one horizontal scanning period H.

[0222] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A pixel circuit, comprising a first reset phase and a data writing phase, wherein the first reset phase is located before the data writing phase, and comprises: A driving subcircuit connected to the first node, the second node and the third node; The driving subcircuit is configured to control the conduction and cutoff of the circuit between the second node and the third node under the control of the voltage of the first node; a data writing subcircuit connected to the first scanning signal terminal, the data signal terminal and the second node; the data writing subcircuit is configured to transmit the data signal received at the data signal terminal to the second node in response to the first scanning signal received at the first scanning signal terminal during the data writing phase; a first reset subcircuit connected to the first initialization signal terminal, the first reset signal terminal and the first node; the first reset subcircuit is configured to, in the first reset phase, transmit the first initialization signal received at the first reset signal terminal to the first node in response to the first reset signal received at the first reset signal terminal; A second reset subcircuit is connected to a second initialization signal terminal, a second reset signal terminal and the second node; the second reset subcircuit is configured to, in the first reset phase, in response to a second reset signal received at the second reset signal terminal, transmit the second initialization signal received at the second initialization signal terminal to the second node; and, in the first reset phase, a voltage of the second initialization signal is greater than a voltage of the first initialization signal.

2. The pixel circuit according to claim 1, wherein: In the first reset stage, an absolute value of a difference between a voltage of the second initialization signal and a voltage of the first initialization signal is 10V to 13V.

3. The pixel circuit according to claim 1 or 2, wherein: It also includes a second resetting phase and a first light emitting phase, wherein the second resetting phase is located between the data writing phase and the first light emitting phase; The second reset subcircuit is further configured to, in the second reset phase, transmit a second initialization signal received at the second initialization signal terminal to the second node in response to a second reset signal received at the second reset signal terminal.

4. The pixel circuit according to any one of claims 1 to 3, having a first refresh frequency and a second refresh frequency, the second refresh frequency being less than the first refresh frequency; at the first refresh frequency, one frame includes one refresh period; at the second refresh frequency, one frame also includes at least one hold period, the at least one hold period is located after the refresh period; and the hold period includes at least one third reset phase and a second light-emitting phase, the at least one third reset phase is located before the second light-emitting phase; The pixel circuit further includes: A third reset subcircuit is connected to the fourth node, the third reset signal terminal and the third initialization signal terminal; The fourth node is configured to be connected to an anode of the light-emitting device; the third reset subcircuit is configured to, in the first reset phase and the third reset phase, transmit the third initialization signal received at the third initialization signal terminal to the fourth node in response to the third reset signal received at the third reset signal terminal; a first storage subcircuit connected to the first voltage signal terminal and the fourth node; the first storage subcircuit is configured to, in the first reset phase and the third reset phase, pull up or pull down the voltage of the fourth node in response to the first voltage signal received at the first voltage signal terminal; Among them, the voltage of one of the third reset signal and the first voltage signal in the refresh period is greater than the voltage in the hold period, and the voltage of the other in the hold period is greater than the voltage in the refresh period.

5. The pixel circuit according to claim 4, wherein: The signals at the first voltage signal terminal and the second initialization signal terminal are the same.

6. The pixel circuit according to claim 4 or 5, wherein: The signal at the third reset signal terminal is the same as the signal at the second reset signal terminal.

7. The pixel circuit according to any one of claims 4 to 6, wherein: The first storage sub-circuit comprises: A first capacitor, wherein a first plate of the first capacitor is connected to the first voltage signal terminal, and a second plate of the first capacitor is connected to the fourth node.

8. The pixel circuit according to any one of claims 1 to 7, further comprising: A plurality of third transistors connected in series, wherein the control electrodes of the third transistors are connected to the second scanning signal terminal; two third transistors located at two ends of the plurality of third transistors connected in series, wherein the second electrode of one is connected to the first node, and the first electrode of the other is connected to the third node; The second reset subcircuit includes a second transistor, the second transistor and the third transistor are both P-type transistors, and the non-working voltage of the second scan signal received at the second scan signal end is less than the non-working voltage of the second reset signal received at the second reset signal end.

9. A display panel, comprising: A plurality of pixel circuits as described in any one of claims 1 to 8, wherein the plurality of pixel circuits are arranged in M ​​rows and N columns, each row includes N pixel circuits arranged along a first direction, each column includes M pixel circuits arranged along a second direction, M>1, N>1, and M and N are integers.

10. The display panel according to claim 9, wherein: The pixel circuit includes a compensation subcircuit, and along the second direction, from the first row of pixel circuits to the last row of pixel circuits, the M rows of pixel circuits are respectively the 1st to the Mth rows of pixel circuits; The display panel further includes: The first gate driving circuit includes M+Q cascaded first shift registers, from the first stage first shift register to the last stage first shift register, the M+Q first shift registers are respectively the 1st to the M+Qth first shift registers; Among them, the first shift register includes a first signal output terminal, the first reset signal terminal of the P-th row pixel circuit is connected to the first signal output terminal of the P-th first shift register; the second scan signal terminal of the P-th row pixel circuit is connected to the first signal output terminal of the P+Q-th first shift register; P≤M, Q>0, and P and Q are integers.

11. The display panel according to claim 9 or 10, wherein: The pixel circuit includes a third reset subcircuit, and along the second direction, from the first row of pixel circuits to the last row of pixel circuits, the M rows of pixel circuits are respectively the 1st to the Mth rows of pixel circuits; The display panel further includes: The second gate driving circuit includes M cascaded second shift registers, from the first-stage second shift register to the last-stage second shift register, and the M second shift registers are respectively the 1st to the Mth second shift registers; wherein, the second shift register includes a second signal output terminal, and the second reset signal terminal and the third reset signal terminal of the P-th row pixel circuit are connected to the second signal output terminal of the P-th second shift register, P≤M, and P is an integer.

12. The display panel according to any one of claims 9 to 11, wherein: The pixel circuit comprises a first light emitting control subcircuit and a second light emitting control subcircuit, and, along the second direction, from the first row of pixel circuits to the last row of pixel circuits, the M rows of pixel circuits are respectively the 1st to the Mth rows of pixel circuits; The display panel further includes: The third gate driving circuit comprises M cascaded third shift registers, from the first stage third shift register to the last stage third shift register, the M third shift registers are respectively the 1st to the Mth third shift registers; wherein the third shift register comprises a third signal output terminal, the first enable signal terminal of the Pth row pixel circuit is connected to the third signal output terminal of the Pth third shift register, P≤M, and P is an integer; The fourth gate driving circuit includes M cascaded fourth shift registers, from the first-stage fourth shift register to the last-stage fourth shift register, and the M fourth shift registers are respectively the 1st to the Mth fourth shift registers; wherein the fourth shift register includes a fourth signal output terminal, and the second enable signal terminal of the P-th row pixel circuit is connected to the fourth signal output terminal of the P-th fourth shift register, P≤M, and P is an integer.

13. The display panel according to any one of claims 9 to 12, wherein: Along the second direction, from the first row of pixel circuits to the last row of pixel circuits, the M rows of pixel circuits are respectively the 1st to the Mth rows of pixel circuits; The display panel further includes: The fifth gate driving circuit includes M cascaded fifth shift registers, from the first stage fifth shift register to the last stage fifth shift register, the M fifth shift registers are respectively the 1st to the Mth fifth shift registers; wherein, the fifth shift register includes a fifth signal output terminal, the first scanning signal terminal of the Pth row pixel circuit is connected to the fifth signal output terminal of the Pth fifth shift register, P≤M, and P is an integer.

14. A display device, comprising: The display panel according to any one of claims 9 to 13.

15. A method for driving a pixel circuit, for driving the pixel circuit according to any one of claims 1 to 8, comprising a first reset phase and a data writing phase, wherein the first reset phase is located before the data writing phase; the first reset phase comprises a first sub-segment and a second sub-segment, wherein the first sub-segment is located before the second sub-segment; or, the first sub-segment is located after the second sub-segment; or, the first sub-segment and the second sub-segment at least partially overlap; In the first sub-segment, the first reset sub-circuit transmits the first initialization signal received at the first initialization signal terminal to the first node in response to the first reset signal received at the first reset signal terminal; In the second sub-segment, the second reset sub-circuit transmits the second initialization signal received at the second initialization signal terminal to the second node in response to the second reset signal received at the second reset signal terminal.

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