Display panel and display device

Abstract

Provided are a display panel and a display device. The display panel comprises: a plurality of pixels (PX), wherein each pixel among the plurality of pixels (PX) comprises a plurality of sub-pixels (SP); in a same pixel (PX), at least one sub-pixel among the plurality of sub-pixels (SP) is a top-emitting sub-pixel (SPT), and at least one sub-pixel among the plurality of sub-pixels (SP) is a bottom-emitting sub-pixel (SPB); and the top-emitting sub-pixel (SPT) and the bottom-emitting sub-pixel (SPB) emit light towards a same side of the display panel. The display panel is conducive to the maximization of the aperture of each sub-pixel.

Description

Display panel and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to Chinese Patent Application No. 202311285063.1 filed on September 28, 2023, and the contents disclosed in the above-mentioned Chinese patent application are hereby cited in their entirety as part of the embodiments of the present disclosure. Technical Field

[0003] Embodiments of the present disclosure relate to a display panel and a display device. Background Art

[0004] In the display field, organic light-emitting diode (OLED) display panels have the characteristics of self-luminescence, high contrast, low energy consumption, wide viewing angle, fast response speed, can be used for flexible panels, wide operating temperature range, and simple manufacturing, and have broad development prospects.

[0005] Summary of the Invention

[0006] Embodiments of the present disclosure provide a display panel and a display device.

[0007] An embodiment of the present disclosure provides a display panel, comprising: a plurality of pixels, wherein each pixel of the plurality of pixels comprises a plurality of sub-pixels, and in the same pixel, at least one sub-pixel of the plurality of sub-pixels is a top-emitting sub-pixel, and at least one sub-pixel of the plurality of sub-pixels is a bottom-emitting sub-pixel, and the top-emitting sub-pixels and the bottom-emitting sub-pixels emit light toward the same side of the display panel.

[0008] For example, a light emitting area of ​​at least one top-emitting sub-pixel is smaller than a light emitting area of ​​at least one bottom-emitting sub-pixel.

[0009] For example, the pixel includes an even number of sub-pixels, and in the same pixel, the top-emitting sub-pixel and the bottom-emitting sub-pixel are arranged in a mirror image.

[0010] For example, the plurality of sub-pixels are four sub-pixels, two of the four sub-pixels are top-emitting sub-pixels, and the other two of the four sub-pixels are bottom-emitting sub-pixels.

[0011] For example, the bottom-emitting sub-pixels are blue-emitting sub-pixels and white-emitting sub-pixels, and the top-emitting sub-pixels are red-emitting sub-pixels and green-emitting sub-pixels.

[0012] For example, the pixel includes an odd number of sub-pixels, and in the same pixel, the light-emitting area of ​​at least one sub-pixel is greater than or equal to the sum of the light-emitting areas of each sub-pixel in the other two sub-pixels.

[0013] For example, the plurality of sub-pixels are three sub-pixels, two of the three sub-pixels are top-emitting sub-pixels, and the other sub-pixel is a bottom-emitting sub-pixel.

[0014] For example, the bottom-emitting sub-pixels are blue-emitting sub-pixels, and the top-emitting sub-pixels are red-emitting sub-pixels and green-emitting sub-pixels.

[0015] For example, the light-emitting area of ​​the sub-pixel emitting blue light is larger than the light-emitting area of ​​the sub-pixel emitting red light, and larger than the light-emitting area of ​​the sub-pixel emitting green light.

[0016] For example, the display panel has a base substrate, and the top-emitting sub-pixels and the bottom-emitting sub-pixels are respectively arranged on two opposite sides of the base substrate.

[0017] For example, the display panel includes a first side and a second side relative to each other, the first side is the light-emitting side, the top-emitting sub-pixel is located on the first side, and the bottom-emitting sub-pixel is located on the second side. The display panel has a transparent area on the first side, and the orthographic projection of the transparent area on the substrate overlaps with the orthographic projection of the light-emitting area of ​​the bottom-emitting sub-pixel on the substrate.

[0018] For example, the area of ​​the orthographic projection of the transparent region on the base substrate is greater than or equal to the area of ​​the orthographic projection of the light emitting region of the bottom-emitting sub-pixel on the base substrate.

[0019] For example, the sub-pixel includes a pixel circuit and a light-emitting element, and an orthographic projection of the pixel circuit of the top-emitting sub-pixel on the substrate overlaps with an orthographic projection of the pixel circuit of the bottom-emitting sub-pixel on the substrate.

[0020] For example, the orthographic projection of the light emitting element of the top-emitting sub-pixel on the substrate overlaps with the orthographic projection of the pixel circuit of the bottom-emitting sub-pixel on the substrate.

[0021] For example, the pixel circuit of the top-emitting sub-pixel is closer to the substrate than the light-emitting element of the top-emitting sub-pixel, and the pixel circuit of the bottom-emitting sub-pixel is closer to the substrate than the light-emitting element of the bottom-emitting sub-pixel.

[0022] For example, the pixel circuit includes a first transistor, a second transistor, a third transistor, and a storage capacitor, and the display panel also includes a gate line, wherein the gate line is connected to the gate of the second transistor and the gate of the third transistor, and the first transistor is located on the side of the storage capacitor away from the gate line.

[0023] For example, the second transistor and the third transistor are located on a side of the storage capacitor close to the gate line.

[0024] For example, the display panel also includes a data line, a sensing line and a first power line, the data line is connected to the second transistor, the first power line is connected to the first transistor, the sensing line is connected to the third transistor, and the data line, the sensing line, and the first power line are located on the same layer.

[0025] For example, the display panel also includes an auxiliary electrode, and the light-emitting element includes a first electrode connected to the pixel circuit, a light-emitting functional layer located on the side of the first electrode away from the base substrate, and a second electrode located on the side of the light-emitting functional layer away from the first electrode, the second electrode is connected to the auxiliary electrode, and the auxiliary electrode is located on the same layer as the data line, the sensing line, and the first power line.

[0026] For example, the display panel further includes a light shielding layer, which is located on a side of the pixel circuit close to the base substrate, the first electrode of the first transistor is connected to the first electrode of the light emitting element, and the light shielding layer is connected to the first electrode of the first transistor.

[0027] For example, the display panel also includes a first pixel defining layer, which is located on a first side of the display panel. The first pixel defining layer has a first opening and a second opening. The first opening is configured to limit the light-emitting area of ​​the top-emitting sub-pixel, and the orthographic projection of the second opening on the base substrate overlaps with the orthographic projection of the transparent area on the base substrate.

[0028] For example, the area of ​​the first opening is smaller than the area of ​​the second opening.

[0029] For example, the display panel also includes a second pixel defining layer, which is located on the second side of the display panel. The second pixel defining layer has a third opening, and the third opening is configured to limit the light-emitting area of ​​the bottom-emitting sub-pixel. The area of ​​the third opening is less than or equal to the area of ​​the second opening.

[0030] An embodiment of the present disclosure further provides a display device, comprising any of the above-mentioned display panels. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0032] FIG1 is a schematic diagram of a display panel provided by an embodiment of the present disclosure.

[0033] FIG2 is a schematic diagram of another display panel provided by an embodiment of the present disclosure.

[0034] FIG3 is a cross-sectional view of a display panel provided by an embodiment of the present disclosure.

[0035] FIG4 is a cross-sectional view of another display panel provided by an embodiment of the present disclosure.

[0036] FIG5 is a cross-sectional view of another display panel provided by an embodiment of the present disclosure.

[0037] FIG6 is a cross-sectional view of another display panel provided by an embodiment of the present disclosure.

[0038] FIG7A is a schematic diagram of a 3T1C pixel circuit in a display panel provided by an embodiment of the present disclosure.

[0039] FIG. 7B is a signal timing diagram of the pixel circuit shown in FIG. 7A during a display process.

[0040] 7C and 7D are signal timing diagrams of the pixel circuit shown in FIG. 7A during the detection process.

[0041] 8 to 15 are plan views of a single film layer in a display panel provided by an embodiment of the present disclosure.

[0042] 16 to 23 are plan views of stacked layers of multiple film layers in a display panel provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0044] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0045] FIG1 is a schematic diagram of a display panel provided in accordance with an embodiment of the present disclosure. FIG2 is a schematic diagram of another display panel provided in accordance with an embodiment of the present disclosure. FIG3 is a cross-sectional view of a display panel provided in accordance with an embodiment of the present disclosure. FIG4 is a cross-sectional view of another display panel provided in accordance with an embodiment of the present disclosure. FIG5 is a cross-sectional view of another display panel provided in accordance with an embodiment of the present disclosure. FIG6 is a cross-sectional view of another display panel provided in accordance with an embodiment of the present disclosure.

[0046] As shown in FIG. 1 and FIG. 2 , an embodiment of the present disclosure provides a display panel including a plurality of pixels PX, each of which includes a plurality of sub-pixels SP.

[0047] As shown in FIG1 , pixel PX includes four subpixels SP, namely, subpixel SP1, subpixel SP2, subpixel SP3, and subpixel SP4. As shown in FIG1 , subpixel SP1 and subpixel SP2 are arranged along direction Y, subpixel SP3 and subpixel SP4 are arranged along direction Y, subpixel SP1 and subpixel SP3 are arranged along direction X, and subpixel SP2 and subpixel SP4 are arranged along direction X. That is, the four subpixels SP are arranged in two rows and two columns. For example, in the display panel shown in FIG1 , in two adjacent columns of subpixels, in one column of subpixels, multiple subpixels SP1 and multiple subpixels SP2 are arranged alternately along direction Y, and in the other column of subpixels, multiple subpixels SP3 and multiple subpixels SP4 are arranged alternately along direction Y. For example, in the display panel shown in FIG1 , in two adjacent rows of subpixels, in one row of subpixels, multiple subpixels SP1 and multiple subpixels SP3 are arranged alternately along direction X, and in the other row of subpixels, multiple subpixels SP2 and multiple subpixels SP4 are arranged alternately along direction X.

[0048] Figure 1 illustrates an example in which sub-pixel SP1 is a red sub-pixel, sub-pixel SP2 is a green sub-pixel, sub-pixel SP3 is a blue sub-pixel, and sub-pixel SP4 is a white sub-pixel. However, the luminous colors of the sub-pixels SP are not limited to the above description and may emit light of other colors, or may be arranged in other arrangements rather than two rows and two columns. The embodiments of the present disclosure do not specifically limit the luminous colors of sub-pixels SP1, SP2, SP3, and SP4, and may be determined as needed.

[0049] As shown in FIG2 , pixel PX includes three sub-pixels SP, namely, pixel PX includes sub-pixel SP1, sub-pixel SP2, and sub-pixel SP3. As shown in FIG2 , sub-pixel SP1 and sub-pixel SP2 are arranged along direction Y and are located in the same side column of sub-pixel SP3. As shown in FIG2 , a line connecting the centers of sub-pixel SP1, sub-pixel SP2, and sub-pixel SP3 forms a triangle. For example, this triangle can be an acute-angled triangle to facilitate the arrangement of the sub-pixels. As shown in FIG2 , in two adjacent columns of sub-pixels, multiple sub-pixels SP1 and multiple sub-pixels SP2 in one column are arranged alternately, and the sub-pixels in the other column are sub-pixels of the same color.

[0050] FIG2 illustrates an example in which sub-pixel SP1 is a red sub-pixel, sub-pixel SP2 is a green sub-pixel, and sub-pixel SP3 is a blue sub-pixel. However, the luminous colors of the sub-pixels SP are not limited to the above description and may emit other colors or be arranged in a manner other than that shown in FIG2 . The embodiments of the present disclosure do not specifically limit the luminous colors of sub-pixels SP1, SP2, and SP3; these colors may be determined as needed.

[0051] 1 and 2 show a base substrate BS. A plurality of pixels PX are located on the base substrate BS.

[0052] As shown in Figures 3 to 6, in the same pixel PX, at least one sub-pixel SP among the multiple sub-pixels SP is a top-emitting sub-pixel SPT, and at least one sub-pixel SP among the multiple sub-pixels SP is a bottom-emitting sub-pixel SPB, and the top-emitting sub-pixel SPT and the bottom-emitting sub-pixel SPB emit light toward the same side of the display panel.

[0053] The display panel provided by the embodiments of the present disclosure is configured such that, in the same pixel PX, at least one sub-pixel SP among the multiple sub-pixels SP is configured as a top-emitting sub-pixel SPT, and at least one sub-pixel SP among the multiple sub-pixels SP is configured as a bottom-emitting sub-pixel SPB. That is, the multiple sub-pixels of the same pixel PX are layered, so that the sub-pixel opening is not restricted by the minimum distance of the pixel-defining layer in a same-layer design (where all the multiple sub-pixels in the same pixel are top-emitting sub-pixels or all are bottom-emitting sub-pixels). This facilitates maximizing the sub-pixel opening, particularly at high resolution. Generally speaking, the minimum distance of the pixel-defining layer is greater than 10 microns.

[0054] The display panel provided by the embodiments of the present disclosure designs different sub-pixels of a pixel in layers. The two parts are basically designed as mirror images, namely the top-emitting sub-pixel and the bottom-emitting sub-pixel. The light-emitting area of ​​the bottom-emitting sub-pixel after left-right inversion can correspond to the transparent area on the side where the top-emitting sub-pixel is located. The two parts of the pixel circuit are stacked or the two parts are made on two substrates respectively, which can maximize the sub-pixel opening under high resolution.

[0055] Figures 3 to 6 illustrate top-emitting subpixels SPT and bottom-emitting subpixels SPB. For example, the light-emitting area of ​​at least one top-emitting subpixel SPT is smaller than the light-emitting area of ​​at least one bottom-emitting subpixel SPB. By setting the area of ​​the bottom-emitting subpixel SPB larger, a significant decrease in the brightness of the bottom-emitting subpixel SPB is avoided, thereby improving display quality.

[0056] For example, as shown in Figure 1, a pixel PX includes an even number of subpixels SP. Within the same pixel PX, top-emitting subpixels SPT and bottom-emitting subpixels SPB are arranged in a mirrored configuration. The number of top-emitting subpixels SPT and bottom-emitting subpixels SPB is the same, and their configuration is mirrored. That is, half of the even-numbered subpixels SP are top-emitting subpixels SPT, and the other half are bottom-emitting subpixels SPB. This mirrored configuration facilitates space utilization and improves display quality.

[0057] For example, as shown in FIG1 , the plurality of sub-pixels SP is four sub-pixels SP, two of the four sub-pixels SP are top-emitting sub-pixels SPT, and the other two of the four sub-pixels SP are bottom-emitting sub-pixels SPB. For example, as shown in FIG1 , sub-pixels SP1 and SP2 are top-emitting sub-pixels SPT, and sub-pixels SP3 and SP4 are bottom-emitting sub-pixels SPB.

[0058] For example, the bottom-emitting sub-pixel SPB comprises a blue-emitting sub-pixel SP (sub-pixel SP3, B) and a white-emitting sub-pixel SP (sub-pixel SP4, W), while the top-emitting sub-pixel SPT comprises a red-emitting sub-pixel SP (sub-pixel SP1, R) and a green-emitting sub-pixel SP (sub-pixel SP2, G). The pixel PX comprising four sub-pixels (RGBW) can reduce the power consumption of the display panel. Depending on the lifespan of the light-emitting elements of different color sub-pixels, the top-emitting sub-pixels can be RG, while the bottom-emitting sub-pixels can be BW.

[0059] For example, as shown in FIG2 , a pixel PX includes an odd number of sub-pixels SP. To facilitate the arrangement of the sub-pixels, in the same pixel PX, the light-emitting area of ​​at least one sub-pixel SP is greater than or equal to the sum of the light-emitting areas of each of the other two sub-pixels SP. As shown in FIG2 , the light-emitting area of ​​sub-pixel SP3 is greater than the sum of the light-emitting areas of sub-pixels SP1 and SP2. Of course, in other embodiments, the light-emitting area of ​​sub-pixel SP3 may be equal to the sum of the light-emitting areas of sub-pixels SP1 and SP2.

[0060] For example, as shown in FIG2 , the plurality of sub-pixels SP are three sub-pixels SP, two of which are top-emitting sub-pixels SPT, and the other sub-pixel SP is a bottom-emitting sub-pixel SPB.

[0061] For example, as shown in FIG2 , the bottom-emitting sub-pixel SPB is a blue-emitting sub-pixel SP (sub-pixel SP3 ), and the top-emitting sub-pixel SPT is a red-emitting sub-pixel SP (sub-pixel SP1 ) and a green-emitting sub-pixel SP (sub-pixel SP2 ).

[0062] As shown in FIG2 , the top-emitting subpixel SPT is subpixel SP1 and subpixel SP2 (RG), and the bottom-emitting subpixel SPB is subpixel SP3 (B). Due to the different lifespans of the light-emitting elements of subpixels of different colors, the top-emitting subpixel can be RG, while the bottom-emitting subpixel can be B.

[0063] For example, as shown in FIG2 , the light emitting area of ​​the blue light emitting sub-pixel SP (sub-pixel SP3 ) is larger than the light emitting area of ​​the red light emitting sub-pixel SP (sub-pixel SP1 ) and larger than the light emitting area of ​​the green light emitting sub-pixel SP (sub-pixel SP2 ).

[0064] A sub-pixel with a larger light-emitting area may be used as a bottom-emitting sub-pixel SPB.

[0065] As shown in Figures 5 and 6 , in the display panel, a subpixel SP includes a light-emitting element EM. The light-emitting element EM includes a first electrode E1, a light-emitting functional layer FL located on a side of the first electrode E1 facing away from the base substrate BS, and a second electrode E2 located on a side of the light-emitting functional layer FL facing away from the first electrode E1. The first electrode E1 is connected to the pixel circuit.

[0066] For example, as shown in Figures 1 to 6 , a display panel includes a base substrate BS, with top-emitting subpixels SPT and bottom-emitting subpixels SPB disposed on opposite sides of the base substrate BS. Figures 4 and 6 illustrate the base substrate BS. Figures 3 and 5 illustrate that the base substrate BS includes a base substrate BS1 and a base substrate BS2. If the base substrate BS includes the base substrate BS1 and the base substrate BS2, they can be fabricated separately and then bonded together.

[0067] For example, as shown in Figures 3 to 6, the base substrate BS of the display panel includes a first side S1 and a second side S2 relative to each other, the first side S1 is the light-emitting side, the top-emitting sub-pixel SPT is located on the first side S1, and the bottom-emitting sub-pixel SPB is located on the second side S2. The display panel has a transparent area A0 on the first side S1, and the orthographic projection of the transparent area A0 on the base substrate BS overlaps with the orthographic projection of the light-emitting area EMR of the bottom-emitting sub-pixel SPB on the base substrate BS.

[0068] In the embodiment of the present disclosure, the top-emitting subpixel SPT emits light from the side where its second electrode E2 is located toward the side away from the substrate, and the bottom-emitting subpixel SPB emits light from the side where its first electrode E1 is located toward the side toward the substrate.

[0069] In the embodiment of the present disclosure, the light emitting region EMR of the sub-pixel SP refers to an actual light emitting region of the sub-pixel, and may correspond to an opening of the pixel defining layer.

[0070] In the embodiments of the present disclosure, transparent area A0 refers to an area without light-blocking components. Light-blocking components may include, for example, metal components. An insulating layer or a transparent or translucent metal layer may be provided within transparent area A0. As shown in Figures 5 and 6 , an insulating layer and a second electrode E2 may be provided within transparent area A0.

[0071] For example, to improve the brightness of the bottom-emitting subpixel SPB, the orthographic projection area of ​​the transparent area A0 on the base substrate BS is greater than or equal to the orthographic projection area of ​​the light-emitting region EMR of the bottom-emitting subpixel SPB on the base substrate BS.

[0072] The light emitting functional layer FL and the second electrode E2 are omitted in Figures 3 and 4. The light emitting functional layer FL and the second electrode E2 are shown in Figures 5 and 6.

[0073] As shown in Figures 3 to 6 , the display panel further includes a light shielding layer SL, a buffer layer BF located on the side of the light shielding layer SL facing away from the base substrate BS, an active layer AT located on the side of the buffer layer BF facing away from the base substrate BS, an insulating layer GI located on the side of the active layer AT facing away from the base substrate BS, a gate electrode GT located on the side of the insulating layer GI facing away from the base substrate BS, an insulating layer ILD located on the side of the gate electrode GT facing away from the base substrate BS, a first electrode Ea and a second electrode Eb of the transistor located on the side of the insulating layer ILD facing away from the base substrate BS, and a passivation layer PVX and a planarization layer PLN located on the sides of the first electrode Ea and the second electrode Eb facing away from the base substrate BS. As shown in Figures 3 to 6 , the first electrode E1 of the light-emitting element EM is connected to the first electrode Ea of the transistor via a via extending through the passivation layer PVX and the planarization layer PLN. As shown in Figures 3 to 6 , the first electrode Ea of the transistor is connected to the active layer AT via a via extending through the insulating layer ILD, and the second electrode Eb of the transistor is connected to the active layer AT via a via extending through the insulating layer ILD. As shown in FIG. 3 to FIG. 6 , the first electrode Ea of the transistor is further connected to the light shielding layer SL through a via hole penetrating the insulating layer ILD and the buffer layer BF to prevent the light shielding layer SL from floating.

[0074] As shown in Figures 3 to 6 , the pixel-defining layer (PDL) has an opening (PN) configured to expose a portion of the first electrode (E1) to form a sub-pixel or light-emitting region of the light-emitting element. Figures 3 to 6 illustrate a pixel-defining layer (PDL1) and a pixel-defining layer (PDL2). The pixel-defining layer (PDL1) is located on a first side (S1), while the pixel-defining layer (PDL2) is located on a second side (S2).

[0075] Figure 3 shows the passivation layer PVX and the planarization layer PLN. The passivation layer PVX is closer to the substrate BS than the planarization layer PLN. Figures 4 to 6 briefly show the passivation layer PVX and the planarization layer PLN, which can be referred to in Figure 3.

[0076] Figure 7A is a schematic diagram of a 3T1C pixel circuit in a display panel provided in an embodiment of the present disclosure. The pixel circuit of the display panel provided in an embodiment of the present disclosure is not limited to a 3T1C pixel circuit. This embodiment uses a 3T1C pixel circuit as an example to illustrate the structure of the display panel. As needed, the pixel circuit may further include a compensation circuit, a reset circuit, etc., which are not limited in the embodiment of the present disclosure.

[0077] 7A , the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst. The first transistor T1 is a drive transistor, and the second transistor T2 is a data write transistor. A first electrode of the second transistor T2 is electrically connected to a first plate Ca of the storage capacitor Cst and a gate of the first transistor T1. A second electrode of the second transistor T2 is connected to a data line DT and configured to receive a data signal Vdt. The gate of the second transistor T2 is connected to a gate line G1, which is configured to provide a first control signal Vg1. The second transistor T2 is configured to write the data signal Vdt into the gate of the first transistor T1 and the storage capacitor Cst in response to the first control signal Vg1. The first electrode of the first transistor T1 is electrically connected to the second plate Cb of the storage capacitor Cst and is configured to be electrically connected to the first electrode E1 of the light-emitting element. The second electrode of the first transistor T1 is connected to a first power line PL1 and configured to receive a first power supply voltage (e.g., a high power supply voltage VDD). The first power line PL1 is configured to provide the first power supply voltage. The first transistor T1 is configured to control the current used to drive the light-emitting element under the control of the voltage of the gate of the first transistor T1; the first electrode of the third transistor T3 is electrically connected to the first electrode of the first transistor T1 and the second electrode plate Cb of the storage capacitor Cst, the second electrode of the third transistor T3 is configured to be connected to the sensing line SS to connect to the external detection circuit, the gate of the third transistor T3 is connected to the gate line G2, the gate line G2 is configured to provide a second control signal Vg2, and the third transistor T3 is configured to detect the electrical characteristics of the sub-pixel to which it belongs in response to the second control signal Vg2 to achieve external compensation; the electrical characteristics include, for example, the threshold voltage and / or carrier mobility of the first transistor T1, or the threshold voltage and driving current of the light-emitting element. The external detection circuit is, for example, a conventional circuit including a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC), which is not described in detail in the embodiments of the present disclosure. Figure 7A shows the gate g, first electrode a, and second electrode b of the transistor.

[0078] As shown in FIG7A , the first electrode of the second transistor T2 , the first plate Ca of the storage capacitor Cst, and the gate of the first transistor T1 are all connected to the node G.

[0079] As shown in FIG7A , the second electrode plate Cb, the third electrode plate Cc, the first electrode of the first transistor T1 , the first electrode of the third transistor T3 , and the first electrode E1 of the light emitting element are all connected to the node S.

[0080] 7A , the second electrode E2 of the light emitting element EM is connected to the second power line PL2 to receive a second power voltage (eg, a low power voltage VSS). The second power line PL2 is configured to provide the second power voltage.

[0081] For example, the storage capacitor Cst shown in FIG7A further includes a third plate Cc. The third plate Cc is located on a side of the first plate Ca away from the second plate Cb and is electrically connected to the second plate Cb to form a parallel capacitor structure, thereby increasing the capacitance of the storage capacitor Cst. For example, in a direction perpendicular to the substrate BS, the third plate Cc, the second plate Cb, and the first plate Ca all overlap.

[0082] The transistors used in the embodiments of the present disclosure may all be thin film transistors or field effect transistors or other switching devices with the same characteristics. The embodiments of the present disclosure are all described by taking thin film transistors as an example. The source and drain of the transistors used here may be symmetrical in structure, so their source and drain may be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one of the poles is directly described as the first pole and the other pole as the second pole. In addition, transistors can be divided into N-type and P-type transistors according to the characteristics of the transistor. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages); when the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages), and the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages). It should be noted that in the following description, the transistor in FIG. 7A is an N-type transistor. However, this is not intended to limit the present disclosure.

[0083] The working principle of the pixel circuit shown in Figure 7A is explained below in conjunction with the signal timing diagrams shown in Figures 7B to 7D, where Figure 7B shows the signal timing diagram of the pixel circuit during the display process, and Figures 7C and 7D show the signal timing diagrams of the pixel circuit during the detection process.

[0084] For example, as shown in FIG7B , the display process of each frame of image includes a data writing and reset phase 1 and a light-emitting phase 2. FIG7B shows the timing waveforms of each signal in each phase. An operating process of the 3T1C pixel circuit includes: in the data writing and reset phase 1, the first control signal Vg1 and the second control signal Vg2 are both on signals, the second transistor T2 and the third transistor T3 are turned on, the data signal Vdt is transmitted to the gate of the first transistor T1 via the second transistor T2, the analog-to-digital converter writes a reset signal to the first electrode E1 of the light-emitting element (e.g., the anode of the OLED) through the sensing line SS and the third transistor T3, the first transistor T1 is turned on and generates a driving current to charge the first electrode E1 of the light-emitting element EM to the operating voltage; in the light-emitting phase 2, the first control signal Vg1 and the second control signal Vg2 are both off signals, due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains unchanged, the first transistor T1 operates in a saturated state with a constant current, and drives the light-emitting element to emit light.

[0085] For example, Figure 7C shows a signal timing diagram of the pixel circuit when detecting the threshold voltage. An operating process of the 3T1C pixel circuit includes: the first control signal Vg1 and the second control signal Vg2 are both turn-on signals, the second transistor T2 and the third transistor T3 are turned on, and the data signal Vdt is transmitted to the gate of the first transistor T1 via the second transistor T2; the analog-to-digital converter writes a reset signal to the first electrode E1 (node ​​S) of the light-emitting element EM through the sensing line SS and the third transistor T3, the first transistor T1 is turned on and charges the node S until the first transistor T1 is turned off, and the digital-to-analog converter samples the voltage on the sensing line SS to obtain the threshold voltage of the first transistor T1. This process can be performed, for example, when the display device is turned off. Vs in Figure 7C represents the voltage at node S.

[0086] For example, FIG7D shows a signal timing diagram of the pixel circuit when performing carrier mobility detection. An operating process of the 3T1C pixel circuit includes: in the first stage, the first control signal Vg1 and the second control signal Vg2 are both on signals, the second transistor T2 and the third transistor T3 are turned on, and the data signal Vdt is transmitted to the gate of the first transistor T1 via the second transistor T2; the analog-to-digital converter writes a reset signal to the first electrode E1 (node ​​S) of the light-emitting element EM through the sensing line SS and the third transistor T3; in the second stage, the first control signal Vg1 is an off signal and the second control signal Vg2 is an on signal, the second transistor T2 is turned off, and the third transistor T3 is turned on, floating the sensing line SS; due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains unchanged, the first transistor T1 operates in a saturated state with a constant current and drives the light-emitting element to emit light, and then the digital-to-analog converter samples the voltage on the sensing line SS and calculates the carrier mobility in the first transistor T1 based on the magnitude and duration of the emission current. For example, this process can be performed in the blanking phase between display phases.

[0087] Through the above detection, the electrical characteristics of the first transistor T1 can be obtained and a corresponding compensation algorithm can be implemented.

[0088] For example, the display panel may further include a data driver circuit and a scan driver circuit (not shown). The data driver circuit is configured to emit a data signal, such as the aforementioned data signal Vdt, as needed (e.g., an image signal input to the display device); the pixel circuit of each sub-pixel is further configured to receive the data signal and apply the data signal to the gate of the first transistor. The scan driver circuit is configured to output various scan signals, such as the aforementioned first control signal Vg1 and second control signal Vg2, and is, for example, an integrated circuit chip (IC) or a gate driver circuit (GOA) directly fabricated on the display panel.

[0089] For example, the display panel further includes a control circuit. For example, the control circuit is configured to control the data drive circuit to apply a data signal and the gate drive circuit to apply a scan signal. An example of the control circuit is a timing control circuit (T-con). The control circuit can be in various forms, for example, including a processor and a memory, the memory including executable code, and the processor running the executable code to perform the above-mentioned detection method.

[0090] For example, the processor may be a central processing unit (CPU) or other forms of processing devices with data processing capabilities and / or instruction execution capabilities, such as a microprocessor, a programmable logic controller (PLC), etc.

[0091] For example, the memory may include one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor may execute the desired functions of the program instructions. Various applications and various data may also be stored in the computer-readable storage medium, such as the electrical characteristic parameters obtained in the above-mentioned detection method, etc.

[0092] Figures 8 to 15 are plan views of a single film layer in a display panel provided by an embodiment of the present disclosure. Figures 16 to 23 are plan views of a stack of multiple film layers in a display panel provided by an embodiment of the present disclosure.

[0093] Figure 8 is a plan view of a light-shielding pattern LY0 in a display panel provided in accordance with an embodiment of the present disclosure. Figure 9 is a plan view of an active pattern ATL in a display panel provided in accordance with an embodiment of the present disclosure. Figure 10 is a plan view of a first conductive pattern LY1 in a display panel provided in accordance with an embodiment of the present disclosure. Figure 11 is a plan view of a via pattern VH1 in a display panel provided in accordance with an embodiment of the present disclosure. Figure 12 is a plan view of a second conductive pattern LY2 in a display panel provided in accordance with an embodiment of the present disclosure. Figure 13 is a plan view of a via pattern VH2 in a display panel provided in accordance with an embodiment of the present disclosure. Figure 14 is a plan view of an electrode pattern EL in a display panel provided in accordance with an embodiment of the present disclosure. Figure 15 is a plan view of a pixel-defining layer PDL in a display panel provided in accordance with an embodiment of the present disclosure.

[0094] Figure 16 is a plan view of a light-shielding pattern LY0 and an active pattern ATL in a display panel provided in accordance with an embodiment of the present disclosure. Figure 17 is a plan view of a light-shielding pattern LY0, an active pattern ATL, and a first conductive pattern LY1 in a display panel provided in accordance with an embodiment of the present disclosure. Figure 18 is a plan view of a stack of a light-shielding pattern LY0, an active pattern ATL, a first conductive pattern LY1, and a via pattern VH1 in a display panel provided in accordance with an embodiment of the present disclosure. Figure 19 is a plan view of a stack of a light-shielding pattern LY0, an active pattern ATL, a first conductive pattern LY1, a via pattern VH1, and a second conductive pattern LY2 in a display panel provided in accordance with an embodiment of the present disclosure. Figure 20 is a plan view of a stack of a light-shielding pattern LY0, an active pattern ATL, a first conductive pattern LY1, a via pattern VH1, a second conductive pattern LY2, and a via pattern VH21 in a display panel provided in accordance with an embodiment of the present disclosure. Figure 21 is a plan view of the stack of a light-shielding pattern LY0, an active pattern ATL, a first conductive pattern LY1, a via pattern VH1, a second conductive pattern LY2, a via pattern VH21, and a via pattern VH22 in a display panel according to an embodiment of the present disclosure. Figure 22 is a plan view of the stack of a light-shielding pattern LY0, an active pattern ATL, a first conductive pattern LY1, a via pattern VH1, a second conductive pattern LY2, a via pattern VH2, and an electrode pattern EL in a display panel according to an embodiment of the present disclosure. Figure 23 is a plan view of the stack of a light-shielding pattern LY0, an active pattern ATL, a first conductive pattern LY1, a via pattern VH1, a second conductive pattern LY2, a via pattern VH2, an electrode pattern EL, and a pixel-defining layer PDL in a display panel according to an embodiment of the present disclosure.

[0095] As shown in Figure 8 , the light-shielding pattern LY0 includes a light-shielding layer SL, a connecting electrode CE1, and a connecting electrode CE2. As shown in Figure 8 , the light-shielding layer SL also serves as the second electrode plate Cb. The connecting electrode CE1 serves as a base pad or barrier to prevent subsequent vias located there from affecting the substrate.

[0096] As shown in Figure 9, the active pattern ATL includes active layers A1, A2, and A3. Within each of these layers, the center portion is a semiconductor layer, while the adjacent portions are conductors, serving as the first and second electrodes of the transistor, respectively. As shown in Figure 9, the active layers A3 of the third transistors in two adjacent sub-pixels in the Y direction (column direction) are connected and form a single integrated structure.

[0097] As shown in FIG10 , the first conductive pattern LY1 includes a first electrode Ca, a gate line G0, and a connecting electrode CE3. The gate line G1 and the gate line G2 in FIG7A are an integral structure, both referred to as gate line G0. A portion of the gate line G0 serves as the gate of the second transistor T2, and a portion of the gate line G0 serves as the gate of the third transistor. In other words, the gate line G0, the gate of the second transistor T2, and the gate of the third transistor form an integral structure.

[0098] 11 , the via pattern VH1 includes vias V1 to V10 and vias Va to Vk. The via pattern VH1 includes vias penetrating the buffer layer BF and the insulating layer ILD, and vias penetrating the insulating layer ILD.

[0099] As shown in Figure 12, the second conductive pattern LY2 includes a first power line PL1, a data line DT, a third electrode Cc, a sensing line SS, an auxiliary electrode AE, a connecting electrode CEa, a connecting electrode CEb, and a connecting electrode CEc. As shown in Figure 12, the auxiliary electrode AE ​​is provided on the left side of the figure, while the auxiliary electrode AE ​​is not provided on the right side. That is, the auxiliary electrode AE ​​is provided on the side where the top-emitting sub-pixel is located, while the auxiliary electrode AE ​​is not provided on the side where the bottom-emitting sub-pixel is located. Of course, in other embodiments, the auxiliary electrode AE ​​may also be provided on the side where the bottom-emitting sub-pixel is located.

[0100] As shown in FIG12 , the data lines DT extend along a direction Y, and the plurality of data lines DT are arranged along a direction X. The data lines DT include a data line DT1, a data line DT2, a data line DT3, and a data line DT4. As shown in FIG12 , the data lines DT1, DT2, DT4, and DT3 are arranged in sequence along the direction X.

[0101] As shown in FIG. 13 , the via hole pattern VH2 includes an opening Ha, an opening Hb, and via holes H1 to H5 .

[0102] As shown in Fig. 14 , the electrode pattern EL includes a plurality of first electrodes E1. Fig. 14 shows four first electrodes E1. Fig. 14 shows a first electrode E11, a first electrode E12, a first electrode E13, and a first electrode E14.

[0103] As shown in FIG. 15 , the pixel defining layer PDL includes a pixel defining layer PDL1 and a pixel defining layer PDL2 .

[0104] As shown in FIG. 15 , the pixel defining layer PDL1 has an opening PN1 , an opening PN2 , an opening PN5 , an opening PN6 , and a via hole PNh.

[0105] As shown in FIG. 16 , the pixel defining layer PDL2 has an opening PN3 and an opening PN4 ​​.

[0106] Figures 8 to 23 show a marking line located in the center of the drawings. This marking line can be seen as a vertical line, a T-shaped line, or a cross. This marking line can be seen as a demarcation line. The left side of the marking line is a top-emitting sub-pixel, and the right side of the marking line is a bottom-emitting sub-pixel. For ease of description, the plan views of the top-emitting sub-pixel and the bottom-emitting sub-pixel are placed in the same figure.

[0107] Referring to Figures 13, 21, and 22, via pattern VH2 includes via pattern VH21 (see Figure 20) and via pattern VH22 (see Figure 21). Via pattern VH21 is a via that penetrates the passivation layer PVX, and via pattern VH22 is a via that penetrates the planarization layer PLN. As shown in Figure 20, via pattern VH21 includes an opening Ha, an opening Hb, a via H11, a via H21, a via H31, a via H41, and a via H51. As shown in Figure 21, via pattern VH22 includes an opening Hc, an opening Hd, a via H12, a via H22, a via H32, a via H42, and a via H52. 13 , 21 and 22 , vias H11 and H12 constitute via H1 , vias H21 and H22 constitute via H2 , vias H31 and H32 constitute via H3 , vias H41 and H42 constitute via H4 , and vias H51 and H52 constitute via H5 .

[0108] As shown in Figures 14 and 23, the second electrode E2 is connected to the connection electrode CEe through the via hole PNh. The connection electrode CEe is connected to the auxiliary electrode AE ​​through the via hole H5 to reduce the resistance of the second electrode E2.

[0109] As shown in Figures 14 and 22, the first electrode E11 is connected to the third plate Cc (node ​​S) via via H1, the first electrode 2 is connected to the third plate Cc (node ​​S) via via H2, the first electrode E13 is connected to the third plate Cc (node ​​S) via via H3, and the first electrode E14 is connected to the third plate Cc (node ​​S) via via H4. Each sub-pixel has its own pixel circuit PXC.

[0110] Referring to Figures 7A, 8 to 12, 18, and 19, the first power line PL1 is connected to one end of the connection electrode CE3 via a via V1. The other end of the connection electrode CE3 is connected to one end of the connection electrode CEa via a via V2. The other end of the connection electrode CEa is connected to the active layer A1 (the second electrode of the first transistor T1) via a via V4. The third electrode plate Cc is connected to the active layer A1 (the first electrode of the first transistor T1) and the second electrode plate Cb via a via V3. In the sub-pixel in the upper left corner of Figure 19, the middle portion of the active layer A1 is a semiconductor layer. The left side of the semiconductor layer of the active layer A1 is the first electrode of the first transistor T1, and the right side of the semiconductor layer of the active layer A1 is the second electrode of the first transistor T1.

[0111] Referring to Figures 7A, 8 to 12, 18, and 19, one end of the connecting electrode CEb is connected to the first electrode plate Ca via via V5, and the other end of the connecting electrode CEb is connected to the active layer A2 (the first electrode of the second transistor T2) via via V7. The data line DT1 is connected to the active layer A2 (the second electrode of the second transistor T2) via via V8. In the sub-pixel in the upper left corner of Figure 19, the middle portion of the active layer A2 is a semiconductor layer. The upper side of the semiconductor layer of the active layer A2 serves as the first electrode of the second transistor T2, and the lower side of the semiconductor layer of the active layer A2 serves as the second electrode of the second transistor T2.

[0112] 7A , 8 to 12 , 18 , and 19 , the third electrode plate Cc is connected to the second electrode plate Cb through a via V6 .

[0113] With reference to Figures 7A, 8 to 12, 18, and 19, one end of the connection electrode CEc is connected to the active layer A3 (the second electrode of the third transistor T3) via via V10. The other end of the connection electrode CEc is connected to one end of the connection electrode CE2 via via Va. The other end of the connection electrode CE2 is connected to the sensing line SS via via Vb. The third electrode plate Cc is connected to the active layer A3 (the first electrode of the third transistor T3) via via V9. In the sub-pixel in the upper left corner of Figure 19, the middle portion of the active layer A3 is a semiconductor layer. The upper side of the semiconductor layer is the first electrode of the third transistor T3, and the lower side of the semiconductor layer is the second electrode of the third transistor T3.

[0114] The above describes the pixel circuit for the subpixel in the upper left corner. The following describes the pixel circuit for the subpixel in the lower left corner. As shown in Figure 19 , the first electrode of the third transistor T3 is connected to the third plate Cc via via Vc. The third plate Cc is connected to the second plate Cb via via Vf. The data line DT is connected to the second electrode of the second transistor T2 via via Vd. The first electrode of the second transistor T2 is connected to one end of the connection electrode CEb via via Ve. The other end of the connection electrode CEb is connected to the first plate Ca via via Vg. The third plate Cc is connected to the first electrode of the first transistor T1 and the second plate Cb via via Vh. The second electrode of the first transistor T1 is connected to one end of the connection electrode CEa via via Vi. The other end of the connection electrode CEa is connected to one end of the connection electrode CE3 via via Vk. The other end of the connection electrode CE3 is connected to the first power line PL1 via via Vj. In Figure 19 , the electrode Ea can be the third plate Cc. The electrode Ea shown in Figures 3 to 6 is connected to the light shielding layer SL and the first electrode of the first transistor T1 through two vias. In Figure 19, the third electrode Cc is connected to the first electrode of the first transistor T1 and the second electrode Cb (light shielding layer SL) through the same via Vh.

[0115] As shown in Figure 23, a double-layer structure can be formed by folding along a marked line or a line extending in direction Y. Specifically, opening PN4 ​​overlaps with opening PN6 through folding, and opening PN3 overlaps with opening PN5 through folding. Openings PN6 and PN5 constitute transparent area A0 shown in Figures 3 to 6. This results in the display panel shown in Figure 1. Light emitted from the light-emitting region EMR3 of sub-pixel SP3 shown in Figure 23 exits from transparent area A03. Light emitted from the light-emitting region EMR4 of sub-pixel SP4 shown in Figure 23 exits from transparent area A04.

[0116] For example, as shown in FIG. 23 , the light emitting area of ​​at least one top-emitting sub-pixel SPT is smaller than the light emitting area of ​​at least one bottom-emitting sub-pixel SPB.

[0117] For example, as shown in Figures 15 and 23, in order to improve the brightness of the bottom-emitting sub-pixel SPB, the area of ​​the positive projection of the transparent area A0 on the base substrate BS is greater than or equal to the area of ​​the positive projection of the light-emitting area EMR of the bottom-emitting sub-pixel SPB on the base substrate BS.

[0118] For the bottom-emitting sub-pixel SPB, the light-emitting area of ​​the light-emitting element does not overlap with the pixel circuit. As shown in FIG23 , the pixel circuit of the bottom-emitting sub-pixel SPB is on the left, while the light-emitting area of ​​the light-emitting element is on the right.

[0119] For a top-emitting sub-pixel SPT, the light-emitting region of the light-emitting element overlaps with the pixel circuit.

[0120] For example, as shown in Figures 3 to 6, 7A, and 23, a subpixel SP includes a pixel circuit PXC and a light-emitting element EM. The orthographic projection of the pixel circuit PXC of the top-emitting subpixel SPT on the substrate BS overlaps with the orthographic projection of the pixel circuit PXC of the bottom-emitting subpixel SPB on the substrate BS. This arrangement helps save area and improve the aperture ratio of the subpixels.

[0121] For example, as shown in Figures 3 to 6, 7A, and 23, the orthographic projection of the light-emitting element EM of the top-emitting sub-pixel SPT on the substrate BS overlaps with the orthographic projection of the pixel circuit PXC of the bottom-emitting sub-pixel SPB on the substrate BS. This arrangement helps save area and improve the aperture ratio of the sub-pixels.

[0122] For example, as shown in Figures 3 to 6, Figure 7A, and Figure 23, the pixel circuit PXC of the top-emitting sub-pixel SPT is closer to the substrate BS than the light-emitting element EM of the top-emitting sub-pixel SPT, and the pixel circuit PXC of the bottom-emitting sub-pixel SPB is closer to the substrate BS than the light-emitting element EM of the bottom-emitting sub-pixel SPB.

[0123] For example, as shown in FIG. 7A and FIG. 23 , the pixel circuit PXC includes a first transistor T1 , a second transistor T2 , a third transistor T3 , and a storage capacitor Cst.

[0124] For example, as shown in Figures 7A, 10, 17, 19, and 23, the display panel further includes a gate line G0, which is connected to the gate of the second transistor T2 and the gate of the third transistor T3. The first transistor T1 is located on a side of the storage capacitor Cst away from the gate line G0. This arrangement facilitates the arrangement of the transistors and the storage capacitor Cst.

[0125] For example, as shown in Figure 19, the second transistor T2 and the third transistor T3 are located on the side of the storage capacitor Cst close to the gate line G0. The positions of the active layers A1, A2, and A3 in the figure are the positions of the first transistor T1, the second transistor T2, and the third transistor T3, respectively.

[0126] For example, as shown in Figure 19, the display panel also includes a data line DT, a sensing line SS and a first power line PL1, the data line DT is connected to the second transistor T2, the first power line PL1 is connected to the first transistor T1, the sensing line SS is connected to the third transistor T3, and the data line DT, the sensing line SS, and the first power line PL1 are located on the same layer and are all located in the second conductive pattern LY2.

[0127] For example, as shown in Figures 3 to 6 and Figure 19, the display panel also includes an auxiliary electrode AE, the light-emitting element EM includes a first electrode E1 connected to the pixel circuit PXC, a light-emitting functional layer FL located on the side of the first electrode E1 away from the base substrate BS, and a second electrode E2 located on the side of the light-emitting functional layer FL away from the first electrode E1, the second electrode E2 is connected to the auxiliary electrode AE, and the auxiliary electrode AE ​​is located on the same layer as the data line DT, the sensing line SS, and the first power line PL1, and are all located in the second conductive pattern LY2.

[0128] For example, as shown in Figures 3 to 6 , the display panel further includes a light-shielding layer SL, which is located on a side of the pixel circuit PXC close to the base substrate BS. The first electrode of the first transistor T1 is connected to the first electrode E1 of the light-emitting element EM, and the light-shielding layer SL is connected to the first electrode of the first transistor T1. The transistor shown in Figures 3 to 6 can be considered the first transistor T1.

[0129] For example, as shown in Figures 3 to 6 and Figure 15, the display panel also includes a first pixel defining layer PDL1, which is located on the first side S1 of the display panel. The first pixel defining layer PDL1 has an opening PN1 and an opening PN5. The opening PN1 is configured to limit the light-emitting area of ​​the top-emitting sub-pixel. For example, the orthographic projection of the opening PN1 on the substrate substrate BS overlaps with the orthographic projection of the top-emitting sub-pixel SPT on the substrate substrate BS, and the orthographic projection of the opening PN5 on the substrate substrate BS overlaps with the orthographic projection of the transparent area A0 on the substrate substrate BS.

[0130] For example, as shown in Figure 15, the area of ​​opening PN1 is smaller than the area of ​​opening PN5. Thus, in some embodiments, the area of ​​the top-emitting sub-pixel is smaller than the area of ​​the bottom-emitting sub-pixel.

[0131] For example, as shown in Figures 3 to 6 and 15 , the display panel further includes a second pixel defining layer PDL2, which is located on the second side S2 of the display panel. The second pixel defining layer PDL2 has an opening PN3, which is configured to define the light-emitting area of ​​the bottom-emitting sub-pixel. For example, the orthographic projection of the opening PN3 on the base substrate BS overlaps with the orthographic projection of the bottom-emitting sub-pixel SPB on the base substrate BS, and the area of ​​the opening PN3 is less than or equal to the area of ​​the opening PN5. This arrangement helps improve the aperture ratio of the sub-pixels.

[0132] The above description is based on the structure of the upper half (opening PN5, opening PN1, and opening PN3) in FIG. 15. Similarly, the lower half (opening PN6, opening PN2, and opening PN4) in FIG. 15 also has the structure described above, which will not be repeated here.

[0133] In the embodiment of the present disclosure, the light emitting element may be an organic light emitting diode (OLED), but is not limited thereto.

[0134] In the embodiment of the present disclosure, the active layer of the transistor may be an oxide semiconductor, but is not limited thereto.

[0135] In the embodiment of the present disclosure, the second electrode E2 of the top-emitting sub-pixel may be a semi-transparent electrode, and the first electrode E1 of the top-emitting sub-pixel may be a reflective electrode, but the present invention is not limited thereto.

[0136] In the embodiment of the present disclosure, the second electrode E2 of the bottom-emitting sub-pixel may be a reflective electrode, and the first electrode E1 of the top-emitting sub-pixel may be a semi-transparent electrode, but the present invention is not limited thereto.

[0137] For example, at least one of the light-shielding pattern LY0 , the first conductive pattern LY1 , ​​and the second conductive pattern LY may be made of a metal material.

[0138] For example, at least one of the buffer layer BF, the insulating layer GI, the insulating layer ILD, and the passivation layer PVX may be made of an inorganic insulating material, which includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0139] For example, at least one of the planarization layer PLN and the pixel definition layer PDL may be made of an organic insulating material, which includes, but is not limited to, resin.

[0140] For example, the base substrate BS may be a rigid substrate (eg, glass) or a flexible substrate (eg, polyimide).

[0141] 3 to 6 and 8 to 23 , the method for manufacturing the backplane of the display panel includes the following steps.

[0142] (1) A light shielding pattern LY0 is formed on a base substrate.

[0143] For example, a metal film is deposited on a transparent substrate by sputtering, patterned by photolithography and wet etching, and the photoresist on the metal surface is stripped to obtain a light-shielding pattern LY0, as shown in Figure 8. For example, the substrate is a glass substrate with a thickness of 50-1000 μm.

[0144] (2) A buffer layer BF is formed on the light shielding pattern LY0.

[0145] For example, the buffer layer BF is deposited by plasma enhanced chemical vapor deposition (PECVD) process. The buffer layer BF may be formed by overlapping one or more of SiNx, SiOx, or SiOxNy. The thickness of the buffer layer BF is 150-500 nm.

[0146] (3) An active pattern ATL is formed on the buffer layer BF.

[0147] For example, an oxide semiconductor is deposited on the buffer layer BF as a pattern ATL by a sputtering process, as shown in Figure 9. For example, the oxide semiconductor can be an amorphous oxide such as IGZO, ZnON, or ITZO.

[0148] (4) An insulating layer GI is formed on the active pattern ATL, and a first conductive pattern LY1 is formed on the insulating layer GI, as shown in FIG. 10 .

[0149] For example, a chemical vapor deposition (CVD) process is used to deposit an insulating film; then a sputtering process is used to deposit a gate metal layer on the insulating film, for example, the metal thickness is 200-1000nm, for example, the metal includes at least one of Al, Mo, Cr, Cu, and Ti, and the patterns of the gate lines, connecting electrodes, and capacitor plates are defined through photolithography and wet etching processes, while the photoresist is retained without being stripped, and the photoresist on the gate metal layer is continued to be used as a mask to dry-etch the pattern of the insulating layer GI; the active pattern ATL exposed to the outside (the part not covered by the first conductive pattern LY1) is conductorized using gases such as NH3, N2, or H2 to reduce the ohmic contact resistance with the second conductive pattern LY2.

[0150] (5) An insulating layer ILD is formed on the first conductive pattern LY1 , ​​and a via hole pattern VH1 is formed, as shown in FIG. 11 .

[0151] For example, an insulating film is deposited using a PECVD process, and a dry etching process is performed to form vias connecting the second conductive pattern LY2 and the active pattern ATL. Also, vias connecting the second conductive pattern LY2 and the light shielding pattern LY0 are formed, thereby forming an insulating layer ILD. For example, the insulating layer ILD may be a single or multi-layer SiNx or SiOx film.

[0152] (6) A second conductive pattern LY2 is formed on the insulating layer ILD.

[0153] For example, a metal film is deposited by sputtering process. The metal may be Al, Mo, Cr, Cu, Ti, etc. with a thickness of 200-1000 nm. The second conductive pattern LY2 is obtained by photolithography and wet etching process, as shown in FIG12 .

[0154] (7) A passivation layer PVX is formed on the second conductive pattern LY2.

[0155] For example, the passivation layer PVX is deposited by using a CVD process, and the material of the passivation layer PVX may be SiO 2 .

[0156] (8) A planarization layer PLN is formed on the passivation layer PVX, and a via hole pattern VH2 is formed, as shown in FIG. 13 .

[0157] For example, an organic material is deposited using a coating method (e.g., slit). After pre-baking, exposure, and development, the pixel area pattern is formed. A post-baking process at a certain temperature, such as 230°C, removes water and organic solvents, resulting in a planarization layer with a thickness of 2.0 to 3.5 μm. Subsequently, exposure and etching are performed to form a via hole pattern VH2. The via holes in the via hole pattern VH2 are used to connect the electrode pattern EL to the components in the second conductive pattern LY2.

[0158] (9) The electrode pattern EL (the first electrode E1 of the light emitting element) is formed on the planarization layer PLN, as shown in FIG. 14 .

[0159] For example, the first electrode E1 is deposited by sputtering. The material of the first electrode E1 may be Al, Mo, Cu, ITO, etc., with a thickness of 100-600 nm. The pattern of the first electrode E1 (electrode pattern EL) is obtained by photolithography and wet etching.

[0160] (10) A pixel defining layer PDL is formed on the electrode pattern EL.

[0161] For example, a coating method (such as slit) is used to deposit the pixel defining layer material, and the pattern of the solidified pixel area is exposed after pre-baking, exposure, and development. The water and organic solvent are removed by post-baking at a certain temperature, such as 230 degrees, to obtain a pixel defining layer PDL with a thickness of 1.8 to 2.0 μm.

[0162] After the above steps, the backplane process is completed.

[0163] In some figures of the embodiments of the present disclosure, the plan views show directions X and Y, and the cross-sectional views show direction Z. Directions X and Y are both directions parallel to the main surface of the substrate BS. Direction Z is a direction perpendicular to the main surface of the substrate BS. For example, directions X and Y intersect. The embodiments of the present disclosure are described using the example in which directions X and Y are perpendicular. For example, the main surface of the substrate BS is the surface of the substrate BS used to manufacture various components. In the cross-sectional views, the upper surface and / or lower surface of the substrate BS is the main surface of the substrate BS. Direction Z is perpendicular to direction X and to direction Y.

[0164] An embodiment of the present disclosure further provides a display device, comprising any of the above-mentioned display panels.

[0165] For example, the display device may be an organic light emitting diode display device. The display device may be any product or component with a display function, such as a television, a digital camera, a mobile phone, a watch, a tablet computer, a laptop computer, a navigation system, etc., that includes an organic light emitting diode display device.

[0166] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel, comprising: A plurality of pixels, wherein each pixel of the plurality of pixels includes a plurality of sub-pixels. In the same pixel, at least one of the plurality of sub-pixels is a top-emitting sub-pixel, and at least one of the plurality of sub-pixels is a bottom-emitting sub-pixel, and the top-emitting sub-pixel and the bottom-emitting sub-pixel emit light toward the same side of the display panel.

2. The display panel according to claim 1, wherein, The light-emitting area of at least one top-emitting sub-pixel is smaller than the light-emitting area of at least one bottom-emitting sub-pixel.

3. The display panel according to any one of claims 1-2, wherein, The pixel includes an even number of sub-pixels, and in the same pixel, the top-emitting sub-pixel and the bottom-emitting sub-pixel are arranged in a mirror image.

4. The display panel according to any one of claims 1 to 3, wherein, The plurality of sub-pixels are four sub-pixels, two of the four sub-pixels are top-emitting sub-pixels, and the other two of the four sub-pixels are bottom-emitting sub-pixels.

5. The display panel according to claim 4, wherein, The bottom-emitting sub-pixels are blue-light-emitting sub-pixels and white-light-emitting sub-pixels, and the top-emitting sub-pixels are red-light-emitting sub-pixels and green-light-emitting sub-pixels.

6. The display panel according to any one of claims 1-5, wherein, The pixel includes an odd number of sub-pixels, and in the same pixel, the light-emitting area of at least one sub-pixel is greater than or equal to the sum of the light-emitting areas of each of the other two sub-pixels.

7. The display panel according to any one of claims 1-6, wherein, The plurality of sub-pixels are three sub-pixels, two of the three sub-pixels are top-emitting sub-pixels, and the other one of the three sub-pixels is a bottom-emitting sub-pixel.

8. The display panel according to claim 7, wherein, The bottom-emitting sub-pixel is a blue-light-emitting sub-pixel, and the top-emitting sub-pixels are red-light-emitting sub-pixels and green-light-emitting sub-pixels.

9. The display panel according to claim 8, wherein, The light-emitting area of the blue-light-emitting sub-pixel is greater than the light-emitting area of the red-light-emitting sub-pixel and greater than the light-emitting area of the green-light-emitting sub-pixel.

10. The display panel according to any one of claims 1-9, wherein, The display panel has a substrate, and the top-emitting sub-pixel and the bottom-emitting sub-pixel are respectively arranged on opposite sides of the substrate.

11. The display panel according to claim 10, wherein, The display panel includes opposite first side and second side, the first side is the light-emitting side, the top-emitting sub-pixels are located on the first side, the bottom-emitting sub-pixels are located on the second side, and the display panel has a transparent region on the first side, and the orthographic projection of the transparent region on the substrate overlaps with the orthographic projection of the light-emitting region of the bottom-emitting sub-pixel on the substrate.

12. The display panel according to claim 11, wherein, The area of the orthographic projection of the transparent region on the substrate is greater than or equal to the area of the orthographic projection of the light-emitting region of the bottom-emitting sub-pixel on the substrate.

13. The display panel according to claim 11 or 12, wherein, The sub-pixel includes a pixel circuit and a light-emitting element, and the orthographic projection of the pixel circuit of the top-emitting sub-pixel on the substrate overlaps with the orthographic projection of the pixel circuit of the bottom-emitting sub-pixel on the substrate.

14. The display panel according to claim 13, wherein, The orthographic projection of the light-emitting element of the top-emitting sub-pixel on the substrate overlaps with the orthographic projection of the pixel circuit of the bottom-emitting sub-pixel on the substrate.

15. The display panel according to claim 13 or 14, wherein, The pixel circuit of the top-emitting sub-pixel is closer to the substrate than the light-emitting element of the top-emitting sub-pixel, and the pixel circuit of the bottom-emitting sub-pixel is closer to the substrate than the light-emitting element of the bottom-emitting sub-pixel.

16. The display panel according to any one of claims 13-15, wherein, The pixel circuit includes a first transistor, a second transistor, a third transistor, and a storage capacitor. The display panel further includes a gate line. Among them, the gate line is connected to the gates of the second transistor and the third transistor, and the first transistor is located on a side of the storage capacitor away from the gate line.

17. The display panel according to claim 16, wherein, The second transistor and the third transistor are located on a side of the storage capacitor close to the gate line.

18. The display panel according to claim 17 further includes a data line, a sensing line, and a first power line, wherein, The data line is connected to the second transistor, the first power supply line is connected to the first transistor, the sensing line is connected to the third transistor, and the data line, the sensing line, and the first power supply line are located on the same layer.

19. The display panel according to claim 18 further includes an auxiliary electrode, wherein, The light-emitting element includes a first electrode connected to the pixel circuit, a light-emitting functional layer on a side of the first electrode facing away from the substrate, and a second electrode on a side of the light-emitting functional layer facing away from the first electrode. The second electrode is connected to the auxiliary electrode, and the auxiliary electrode is located on the same layer as the data line, the sensing line, and the first power supply line.

20. The display panel according to any one of claims 16-19 further includes a light-shielding layer, wherein, The light-shielding layer is located on a side of the pixel circuit close to the substrate. A first pole of the first transistor is connected to the first electrode of the light-emitting element, and the light-shielding layer is connected to the first pole of the first transistor.

21. The display panel according to any one of claims 11-20 further includes a first pixel defining layer, wherein, The first pixel defining layer is located on a first side of the display panel. The first pixel defining layer has a first opening and a second opening. The first opening is configured to define a light-emitting area of the top-emitting sub-pixel, and a positive projection of the second opening on the substrate overlaps a positive projection of the transparent area on the substrate.

22. The display panel according to claim 21, wherein, The area of the first opening is smaller than the area of the second opening.

23. The display panel according to claim 21 or 22 further includes a second pixel defining layer, wherein, The second pixel defining layer is located on a second side of the display panel. The second pixel defining layer has a third opening. The third opening is configured to define a light-emitting area of the bottom-emitting sub-pixel, and the area of the third opening is smaller than or equal to the area of the second opening.

24. A display device, comprising the display panel according to any one of claims 1-23.

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