Processor-based circuit interrupting device having noise tolerance

Abstract

A circuit interrupting device includes a grounded neutral (GN) fault detector and a controller. The grounded neutral (GN) fault detector is configured to provide a first signal in response to a GN fault on a neutral conductor, where the first signal has a frequency above a power line frequency. The controller is configured to perform: detecting a second signal while the GN fault detector is enabled, where the second signal has a frequency above the power line frequency; causing the GN fault detector to be disabled; and based on detecting no frequency above the power line frequency while the GN fault detector is disabled, causing a load to be disconnected.

Description

PROCESSOR-BASED CIRCUIT INTERRUPTING DEVICE HAVING NOISE TOLERANCECROSS REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims the benefit of and priority to U.S. Provisional Patent Application No. 63 / 541,341, filed on September 29, 2023. The entire disclosure of the foregoing application is hereby incorporated by reference herein.TECHNICAL FIELD

[0002] The present disclosure relates to processor-based circuit interrupting devices, and more particularly, to microcontroller-based circuit interrupting devices having noise tolerance.BACKGROUND

[0003] A category of line monitors, such as power line monitors, includes the ground-fault circuit interrupter (GFCI). A GFCI should preferably be able to pass industry standards, such as Underwriter's Laboratory (UL) standards. UL standard UL934 has requirements for GFCIs that relate to 60 Hz operations. Under UL standard UL101, appliances are allowed to produce significant high frequency currents. The UL standards may coexist in a way that allows undesirable conditions to exist, even while UL standards are satisfied. There is continuing interest in improving GFCIs.SUMMARY

[0004] In accordance with aspects of the present disclosure, a circuit interrupting device includes: a grounded neutral (GN) fault detector configured to provide a first signal in response to a (GN) fault on a neutral conductor, where the first signal has a frequency above a power line frequency; and a controller. The controller is configured to perform: detecting a second signal while the GN fault detector is enabled, where the second signal has a frequency above the powerline frequency; causing the GN fault detector to be disabled; and based on detecting no frequency above the power line frequency while the GN fault detector is disabled, causing a load to be disconnected.

[0005] In various embodiments of the circuit interrupting device, the circuit interrupting device further includes: an amplifier arranged to form a positive feedback loop with the GN fault detector, where the amplifier is configured to amplify a second signal in the positive feedback loop to provide an amplified signal. The controller is further configured to perform: determining whether the amplified signal has an amplified-signal frequency above the power line frequency while the GN fault detector is enabled and while the GN fault detector is disabled.

[0006] In various embodiments of the circuit interrupting device, in the determining whether the amplified signal has an amplified-signal frequency above the power line frequency while the GN fault detector is enabled and while the GN fault detector is disabled, the controller is configured to perform: causing the GN fault detector to be enabled; determining a first frequency of the amplified signal while the GN fault detector is enabled; causing the GN fault detector to be disabled; and determining a second frequency of the amplified signal while the GN fault detector is disabled.

[0007] In various embodiments of the circuit interrupting device, in the determining whether the amplified signal has an amplified-signal frequency above the power line frequency while the GN fault detector is enabled and while the GN fault detector is disabled, the controller is configured to, at least twice, cause the GN fault detector to be enabled and cause the GN fault detector to be disabled.

[0008] In various embodiments of the circuit interrupting device, the controller is configured to repeatedly alternate causing the GN fault detector to be enabled for one cycle of the power line frequency and causing the GN fault detector to disabled for one cycle of the power line frequency.

[0009] In various embodiments of the circuit interrupting device, the controller is configured to repeatedly alternate causing the GN fault detector to be enabled for one half-cycle of the power line frequency and causing the GN fault detector to be disabled for one half-cycle of the power line frequency.

[0010] In various embodiments of the circuit interrupting device, the circuit interrupting device further includes: a comparator configured to provide an indication corresponding to each cycle of the amplified signal; and a counter configured to count the indication corresponding to each cycle of the amplified signal, where the controller is configured to read and reset the counter to determine the amplified-signal frequency.

[0011] In various embodiments of the circuit interrupting device, the circuit interrupting device further includes: a ground fault detector configured to provide a third signal in response to the first signal and in response to detection of a ground fault on a phase conductor and the neutral conductor; a second amplifier configured to amplify a fourth signal to provide a second amplified signal, where the fourth signal is based on the third signal; and a high pass filter connected between an output of the second amplifier and an input of the first amplifier.

[0012] In various embodiments of the circuit interrupting device, the circuit interrupting device further includes: a voltage reference circuit configured to provide a reference voltage, a first analog-to-digital converter (ADC), and a second ADC. The controller is further configured to perform: sampling, by the first ADC, the amplified signal to provide first signal samples, where the sampling occurs at a sampling rate; and sampling, by the second ADC, the reference voltageto provide reference voltage samples, where the sampling by the second ADC occurs at the sampling rate.

[0013] In various embodiments of the circuit interrupting device, the controller is further configured to perform: compensating the first signal samples based on the reference voltage samples.

[0014] In various embodiments of the circuit interrupting device, the controller is further configured to perform: based on determining that the amplified signal has an amplified-signal frequency above the power line frequency while the GN fault detector is enabled and while the GN fault detector is disabled, repeat, for another iteration, the determining whether the amplified signal has an amplified-signal frequency above the power line frequency while the GN fault detector is enabled and while the GN fault detector is disabled.

[0015] In accordance with aspects of the present disclosure, a method in a circuit interrupting device includes: causing a grounded neutral (GN) fault detector to be enabled, where the GN fault detector is configured to provide a first signal in response to a (GN) fault on a neutral conductor and where the first signal has a frequency above a power line frequency; detecting a second signal while the GN fault detector is enabled, where the second signal has a frequency above the power line frequency; causing the GN fault detector to be disabled; and based on detecting no frequency above the power line frequency while the GN fault detector is disabled, causing a load to be disconnected.

[0016] In various embodiments of the method, an amplifier is arranged to form a positive feedback loop with the GN fault detector, and the amplifier is configured to amplify a second signal in the positive feedback loop to provide an amplified signal. The method further includes:determining whether the amplified signal has an amplified-signal frequency above the power line frequency while the GN fault detector is enabled and while the GN fault detector is disabled.

[0017] In various embodiments of the method, the determining whether the amplified signal has an amplified-signal frequency above the power line frequency while the GN fault detector is enabled and while the GN fault detector is disabled includes: causing the GN fault detector to be enabled; determining a first frequency of the amplified signal while the GN fault detector is enabled; causing the grounded neutral fault detector to be disabled; and determining a second frequency of the amplified signal while the GN fault detector is disabled.

[0018] In various embodiments of the method, the determining whether the amplified signal has an amplified-signal frequency above the power line frequency while the GN fault detector is enabled and while the GN fault detector is disabled includes: at least twice, causing the GN fault detector to be enabled and causing the GN fault detector to be disabled.

[0019] In various embodiments of the method, the method further includes: repeatedly alternating causing the GN fault detector to be enabled for one cycle of the power line frequency and causing the GN fault detector to be disabled for one cycle of the power line frequency.

[0020] In various embodiments of the method, the method further includes: repeatedly alternating causing the GN fault detector to be enabled for one half-cycle of the power line frequency and causing the GN fault detector to be disabled for one half-cycle of the power line frequency.

[0021] In various embodiments of the method, the method further includes: providing an indication corresponding to each cycle of the amplified signal; counting the indication corresponding to each cycle of the amplified signal; and reading and resetting the count to determine the amplified-signal frequency.

[0022] In various embodiments of the method, the positive feedback loop further includes: a ground fault detector configured to provide a third signal in response to the first signal and in response to detection of a ground fault on a phase conductor and the neutral conductor; a second amplifier configured to amplify a fourth signal to provide a second amplified signal, wherein the fourth signal is based on the third signal; and a high pass filter connected between an output of the second amplifier and an input of the first amplifier.

[0023] In various embodiments of the method, the method further includes: sampling, by a first analog-to-digital converter (ADC), the amplified signal to provide first signal samples, where the sampling occurs at a sampling rate; and sampling, by a second ADC, a reference voltage to provide reference voltage samples, where the sampling by the second ADC occurs at the sampling rate.

[0024] In various embodiments of the method, the method further includes: compensating the first signal samples based on the reference voltage samples.

[0025] In various embodiments of the method, the method further includes: based on determining that the amplified signal has an amplified-signal frequency above the power line frequency while the GN fault detector is enabled and while the GN fault detector is disabled, repeating, for another iteration, the determining whether the amplified signal has an amplified- signal frequency above the power line frequency while the GN fault detector is enabled and while the GN fault detector is disabled.

[0026] In accordance with aspects of the present disclosure, a circuit interrupting device includes: a grounded neutral (GN) fault detector configured to provide a first signal in response to a (GN) fault on a neutral conductor, the first signal having a frequency above a power line frequency; and a controller configured to perform: detecting a second signal while a switch, forshunting the GN fault detector, is open, the second signal having a frequency above the power line frequency; causing the switch to close to shunt the GN fault detector; and based on detecting no frequency above the power line frequency while the switch is closed, causing a load to be disconnected.

[0027] In accordance with aspects of the present disclosure, a method in a circuit interrupting device includes: causing a grounded neutral (GN) fault detector to be enabled, where the GN fault detector is configured to provide a first signal in response to a (GN) fault on a neutral conductor, where the first signal has a frequency above a power line frequency; detecting a second signal while a switch, for shunting the GN fault detector, is open, where the second signal has a frequency above the power line frequency; causing the switch to close to shunt the GN fault detector; and based on detecting no frequency above the power line frequency while the switch is closed, causing a load to be disconnected.

[0028] In accordance with aspects of the present disclosure, a circuit interrupting device includes: a grounded neutral (GN) fault detector configured to provide a first signal in response to a (GN) fault on a neutral conductor where the first signal is in a first frequency range; an amplifier arranged to form a positive feedback loop with the GN fault detector where the amplifier is configured to amplify a second signal in the positive feedback loop to provide an amplified signal; an interrupter configured to interrupt current flow through the circuit interrupting device; and a controller. The controller is configured to perform: determining whether the amplified signal has an amplified-signal frequency in the first frequency range while the GN fault detector is enabled and while the GN fault detector is disabled, and based on determining that the amplified signal has an amplified-signal frequency in the first frequency range while the GN fault detector is enabledbut not while the GN fault detector is disabled, causing the interrupter to interrupt current flow through the circuit interrupting device.

[0029] In accordance with aspects of the present disclosure, a method in a circuit interrupting device includes obtaining an amplified signal in a positive feedback loop where the positive feedback loop includes: a grounded neutral (GN) fault detector configured to provide a first signal in response to a GN fault on a neutral conductor where the first signal is in a first frequency range, and an amplifier configured to amplify a second signal in the positive feedback loop to provide the amplified signal. The method further includes: determining whether the amplified signal has an amplified-signal frequency in the first frequency range while the GN fault detector is enabled and while the GN fault detector is disabled; and based on determining that the amplified signal has an amplified-signal frequency in the first frequency range while the GN fault detector is enabled but not while the GN fault detector is disabled, causing an interrupter to interrupt current flow through the circuit interrupting device.

[0030] The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the techniques described in this disclosure will be apparent from the description and drawings, and from the claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0031] A detailed description of embodiments of the disclosure will be made with reference to the accompanying drawings, wherein like numerals designate corresponding parts in the figures:

[0032] FIG. 1 is a block diagram of example portions of GFCI circuitry, in accordance with aspects of the present disclosure;

[0033] FIG. 2 is a diagram of an example components of a controller, in accordance with aspects of the present disclosure;

[0034] FIG. 3 is a diagram of an example circuit for providing a voltage reference, in accordance with aspects of the present disclosure;

[0035] FIG. 4 is a diagram of yet another example circuit for providing a voltage reference, in accordance with aspects of the present disclosure;

[0036] FIG. 5 is a flow diagram of an example operation in a GFCI device, in accordance with aspects of the present disclosure; and

[0037] FIG. 6 is a flow diagram of another example operation in a GFCI device, in accordance with aspects of the present disclosure.DETAILED DESCRIPTION

[0038] In the following description, certain specific details are set forth in order to provide a thorough understanding of disclosed aspects. However, one skilled in the relevant art will recognize that aspects may be practiced without one or more of these specific details or with other methods, components, materials, etc. In other instances, well-known structures associated with transmitters, receivers, or transceivers have not been shown or described in detail to avoid unnecessarily obscuring descriptions of the aspects.

[0039] Reference throughout this specification to “one aspect” or “an aspect” means that a particular feature, structure, or characteristic described in connection with the aspect is included in at least one aspect. Thus, the appearances of the phrases “in one aspect” or “in an aspect” in various places throughout this specification are not necessarily all referring to the same aspect. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more aspects.

[0040] A ground fault circuit interrupter (GFCI) is a device, e.g., in a circuit breaker, in a receptacle, or otherwise (e.g., in right angle, in-line, plug-in, or panel mount circuit interrupt devices), that operates to disconnect electrical power in the event of an electrical fault. As persons skilled in the art will understand, an electrical fault means and refers to a condition in which electrical current does not follow an intended path within an electrical device and may, instead, be diverted to undesirable paths, such as to a path to a person. Since the advent of GFCI devices, the number of fatalities from electrocution has decreased significantly.

[0041] A GFCI device must be reliable in detecting electrical faults and must also be useful. If a GFCI falsely trips its circuit breaker often and unnecessarily, electrical power to the load becomes unnecessarily interrupted and will cause users to be confused and frustrated. Modem appliances and lights, however, among other devices and equipment, may use power supplies that generate significant high frequency ground currents. When such loads are connected to a GFCI device, the significant high frequency ground currents may create fault-like conditions in a GFCI device. At the same time, actual electrical faults may also involve high frequency signals. Accordingly, it is important for a GFCI device to distinguish high frequencies signals associated with an actual electrical fault, which require circuit interruption, from high frequency signals caused by a load, which do not require circuit intermption.

[0042] A GFCI device having a controller is disclosed. As explained in further detail below, the controller can process signals to detect one or more electrical fault conditions, such as ground fault or grounded neutral (G / N) conditions, and can also process signals to distinguish actual faults from G / N-like conditions caused by high frequency signals from a load.

[0043] The controller of the GFCI device can be or include a processor, a microcontroller, a digital signal processor, a system on chip (SOC), and / or a field programmable gate array (FPGA),among other possibilities. In various embodiments, the controller is provided as a single integrated circuit (IC) chip which can be mounted on a single printed circuit board (PCB). In various embodiments, the various circuit components, including, for example, the controller, are provided as one or more integrated circuit chips. That is, the various circuit components are located on one or more integrated circuit chips.

[0044] In accordance with aspects of the present disclosure, the controller executes instructions (e.g., firmware) to determine whether a real electrical fault may be occurring or whether an electrical fault is not occurring but G / N-like conditions, e.g., high frequency ground noise from appliances that are within allowed levels, are present. As mentioned above, modem appliances and lights may use power supplies that generate significant high frequency ground currents, which may generate a high frequency ground fault and which can be misinterpreted as grounded neutral conditions and cause false tripping of GFCIs. The present disclosure decreases false tripping in a GFCI by identifying high frequency signals from loads that are not related to an actual electrical fault.

[0045] Referring now to FIG. 1, there is shown a block diagram of an example of a GFCI device that includes a controller 140. The GFCI device senses a variety of electrical faults associated with signals on a phase conductor 101 and a neutral conductor 103, which are connected between a power source 104 (e.g., 120 VAC) and a load 106. The power signals provided by the power source 104 may, for example, be power signals provided by a utility company or power signals provided to a portion of a residential or commercial electrical system, such as via a branch circuit.

[0046] The GFCI device includes a differential current transformer 112 and a grounded neutral(G / N) transformer 1 14. The differential transformer 112 detects or senses an imbalance betweencurrent flowing through the phase conductor 101 and the neutral conductor 102, which is indicative of a ground fault condition. When an imbalance is detected, the differential transformer 112 outputs a differential signal having a voltage (referred to herein as a differential voltage) that corresponds to the sensed difference between the currents flowing through the phase and neutral conductors 101, 103. When a ground fault condition occurs, the differential signal has a first frequency that corresponds to the frequency of the signals flowing through the phase and neutral conductors, e.g., a power signal frequency of about 60 Hz. A signal, which is based on the differential signal, is provided to an operational amplifier (OP A0) 116, which effectively operates to amplify the differential voltage and output a signal OPAO out that corresponds to an amplified differential voltage.

[0047] The grounded neutral transformer 114 and the differential transformer 112 are arranged or configured to be in a proper electrical phase relationship with respect to each other. This may be achieved in any suitable manner, such as, for example, physically positioning or arranging the grounded neutral transformer 114 and the differential transformer 112 in a particular orientation with respect to each other such that the direction of current flow in one transformer is along a particular direction with respect to the direction of current flow of the other transformer. A resonant circuit 120 may include a capacitor having a selected capacitive value that will create resonance upon inductance of the grounded neutral transformer 114. The resonant circuit 120 will be discussed more below.

[0048] In accordance with aspects of the present disclosure, output of the op-amp OP A0 116 is connected to a low pass filter 121 and to a high pass filter and op-amp (OPA1) 122. The low pass filter 121 is configured to extract the power line frequency component from the OPAO out signal for use in detecting “traditional” power line ground faults which exhibit the power linefrequency (e.g., 60 Hz, or another power line frequency). As shown in FIG. 1, the extracted power line component is denoted as an LPF out signal. The power line frequency component may be referred to herein as a first frequency component. Persons skilled in the art will understand how to detect a traditional ground fault using the OPAO out signal and / or the LPF out signal. For example, techniques described in U.S. Patent No. 9,276,393 may be employed. The entire contents of U.S. Patent No. 9,276,393 are hereby incorporated by reference herein.

[0049] In accordance with aspects of the present disclosure, the high pass filter and OPA1 122 are configured to remove a low frequency component from the OP AO out signal and leave a high frequency component that may be indicative of either a G / N-fault or high frequency noise from the load 106, and to amplify that high frequency component. In various embodiments, the high frequency component may, for example, have a frequency between 3 kHz - 10 kHz, or another frequency range. The high frequency component may be referred to herein as a second frequency component and is explained in more detail below.

[0050] The output of the op-amp OP Al 122 is a signal denoted as OPAl out and is connected through a resonant circuit 120 to the grounded neutral transformer 114. The OP Al 122 is in a proper electrical phase relationship with the differential transformer 112 such that OPA1 122 oscillates upon the occurrence of a grounded neutral condition at a second frequency. When a grounded neutral condition is present, the grounded neutral transformer 114 injects or outputs a signal which creates an imbalance in the currents passing through differential transformer 112, which causes the differential transformer 112 to output a differential signal that has the second frequency component.

[0051] Specifically, the grounded neutral transformer 114, the differential transformer 112, the resonant circuit 120, OP A0 116, and OPA1 122 cooperate to achieve positive feedback when agrounded neutral fault condition exists. The resonant circuit 120 may include a capacitor having a selected capacitance value that will result in resonance upon inductance of the grounded neutral transformer 114. When a grounded neutral fault occurs, the resonant circuit 120 is configured to oscillate at its resonant frequency (i.e., the second frequency), and a current in the neutral conductor 103 is detected by the differential transformer 112. When no such grounded neutral fault is detected, the resonant circuit 120 acts simply as a load and does not affect operation of the differential transformer 112. An example of positive feedback is described in U.S. Patent No. 9,276,393, which was incorporated by reference above.

[0052] Persons skilled in the art will understand other approaches for implementing proper phase relationship between a grounded neutral fault detector and an amplifier to achieve positive feedback when an actual grounded neutral fault occurs. Such other approaches and embodiments are contemplated to be within the scope of the present disclosure.

[0053] As mentioned above, high frequency signals from the load 106 may appear as a G / N- like condition if the high frequency signals are in the range of the second frequency, i.e., in the range of the resonant frequency of the resonant circuit 120 when an actual grounded neutral fault occurs. In accordance with aspects of the present disclosure, a controller 140 may operate to distinguish actual grounded neutral faults from such high frequency signals from the load by enabling and disabling the grounded neutral transformer 114 and determining whether the high frequency signals are present during both enabled and disabled periods of the grounded neutral transformer 114. That is, if the high frequency signals are present when the grounded neutral transformer 114 is enabled and also when the grounded neutral transformer 114 is disabled, the controller may conclude that the G / N-like condition is caused by high frequency signals from the load 106 (or by another cause) rather than caused by an actual grounded neutral fault. In theillustration of FIG. 1, the grounded neutral transformer 114 may be disabled by closing a switch 130 to shunt the transformer and may be enabled by opening the switch 130. In various embodiments, the switch 130 may be implemented by a transistor external to a controller 140. In various embodiments, the switch 130 may be implemented by a pin of the controller 140 switching between hi-impedance state and low output. Because high frequency signals from external sources or from a grounded neutral fault can appear or disappear in the middle of a measuring interval, the procedure of enabling and disabling the grounded neutral transformer 114 core procedure should be repeated more than once, such as twice or more than twice. Such operations will be described in more detail in connection with FIGS. 2 and FIG. 6.

[0054] Further, in various embodiments, if it is determined that the high frequency component is not a grounded neutral fault, the controller 140 and the peak detector / averaging block 142, or digital sampling by the controller 140, can determine the level of the high frequency component based on frequency measurements and decide whether to trigger the circuit interrupt.

[0055] In accordance with aspects of the present disclosure, in the example of FIG. 1, the frequency of the high frequency component signal OPAl out may be determined using a comparator 123 and a counter 125. The comparator 123 may operate to provide a particular indication for each cycle of a signal, and the counter 125 operates to track the number ofindications provided by the comparator 123. The comparator 123 may be set on a certain threshold to generate a transition when the signal at the output of OPA1 is changing. A voltage measurement block 144 in the controller 140 may measure the transitions, and the counter 125 counts these transitions. The controller 140 periodically reads and clear the counter 125 to determine whether there is any high frequency component and, if so, determine the frequency value of the high frequency component.Other types of comparators are contemplated to be within the scope of the present disclosure. Invarious embodiments, if a controller has sufficiently high processing capability and is capable of sampling OPAl out at the Nyquist rate or higher (e.g., 6-20 kHz sampling rate), then the controller 140 may sample OPAl out and determine the frequency of OPAl out without the use of a comparator 123.

[0056] With continuing reference to FIG. 1, a controller 140 may reset the counter 125 periodically and read the value in the counter 125 on a timed basis to determine the number of cycles in the OPAl out signal over time and, thus, determine the frequency of the high frequency component signal OPA1 out. For example, a 3-10 kHz signal has one cycle about every 0.1 to 0.333 milliseconds. In various embodiments, a controller may, for example, read and reset the counter 125 with power line frequency half-cycles or cycles, i.e., every 8.33 milliseconds or every 16.67 milliseconds. During each 8.33 millisecond period, a 3 kHz signal would exhibit 25 cycles and a 10 kHz signal would exhibit 83 cycles. Other timing for resetting the counter 125 are contemplated to be within the scope of the present disclosure.

[0057] Such an implementation for determining frequency of OPAl out is merely an example. Other embodiments are contemplated to be within the scope of the present disclosure. For example, in various embodiments, op amp OP A0 116 may be connected to a filter / peak detector / averaging block 142 in the controller 140. In such embodiments, such functionalities would be provided in the controller 140, and the controller 140 may detect high frequency electrical faults. To illustrate such possible embodiments, FIG. 1 shows a dashed line connecting the op amp OP A0 116 and the block 142.

[0058] If the OP A0 out signal (having power line frequency component) is directly connected to an input of op-amp OPA1, there may be difficulty detecting higher frequency oscillations using the comparator 123 in the presence of a standing ground fault below the trip threshold (e.g., 4-6mA). For example, a grounded neutral condition may occur when a ground fault below 4 mA exists. In this case, the comparator 123 may not correctly detect the output signal OPAO out with the standing ground fault and a high frequency component on top of it. To minimize the effect of a standing fault on GN fault detection, a high pass filter or a bi-pass filter can be used to remove the low frequency component. In the simplest case, this may be a capacitor between the output of OP AO and the input of OPA1.

[0059] The GFCI device of FIG. 1 also includes a voltage reference circuit 118 that generates a voltage Vref The voltage reference circuit 118 receives an input voltage signal having voltage Vdd from the power source 104 and includes one or more electrical components (e.g., shown in 3-5) for generating Vref as function of Vdd. In various embodiments, Vref = Vdd / 2. In various embodiments, the voltage reference circuit 118 may provide Vref = 1.2V or Vref=1.35V, within the range 0 < Vref < Vdd. Examples of various embodiments will be described in connection with FIGS. 3-5. For now, it is sufficient to note that the power source 104 may be a source of power line disturbances, and it is beneficial to use a voltage regulator for the voltage reference circuit 118. A voltage regulator provides a stable voltage that is not dependent on Vdd deviations compared to a resistive divider, and the voltage reference comes up faster while the controller 140 is in reset (because it can be set to a voltage below the reset voltage of the controller 140). This alleviates some problems associated with power up transitions (e.g., a GFCI in certain cases has to react to electrical faults in less the 24 milliseconds).

[0060] The block diagram of FIG. 1 is merely illustrative, and persons skilled in the art will recognize that the GFCI devices includes other components not shown in FIG. 1 or may include components different from those shown in FIG. 1. For example, certain components are illustrated in FIGS. 2-5. Also, certain components are described in U.S. Patent No. 9,276,393, which personsskilled in the art will understand, such as, without limitation, circuitry for circuit interruption (including a trip coil / solenoid) and various test, trip, and reset circuitry. Circuit interruption involves an actuator, such as a silicon controlled rectifier (SCR), Triac, or bipolar transistors, or MOSFETs. In various embodiments, the solenoid may be implemented as a holding relay. In various embodiments, the GFCI device may have a test button for initiating a manual test and for tripping the GFCI device in case of a successful test. In various embodiments, the GFCI device can be implemented with a reset lockout feature, in which the test button opens contact mechanically, and when the reset button is activated, a manual test is performed and contacts are closed only when the manual test is successful. In various embodiments, with a single-chip microcontroller solution, a GFCI device can be used with a holding relay, and the contacts can be closed on the holding relay only after a self-test or a manual test is successful. For example, a microcontroller GFCI can be used with contacts that are controlled by a solenoid. A solenoid opens contacts in case of an electrical fault, and closing the contacts again requires a manual “mechanical” input. There are different class of GFCIs - portable GFCIs: plug-in or panel mount GFCIs, such as Leviton Cat. Nos. GSRA1 or GSPA2. Such GFCIs have a holding relay. Those GFCIs, when plugged-in (e.g. powered), initiate a self-test, and close the contacts only if this self- test is successful, as described in U.S. Patent Application Publication No. US20220216687A1, which is hereby incorporated by reference herein in its entirety. However, instead of using a two chip solution, as described in U.S. Patent Application Publication No. US20220216687A1, a single microcontroller GFCI can be used, such as a solution in accordance with aspects of the present disclosure.

[0061] Additionally, some of the blocks shown in FIG. 1 may be implemented by discrete electrical components (e.g., discrete capacitors) and some components may be implemented in acontroller. For example, the op-amps OP AO and OPA1 may not be discrete components and may be provided within the controller 140. The op-amps OP AO and OPA1 may have analog gain circuits, which persons skilled in the art will recognize. The differential transformer is just one example of a ground fault detector, and the grounded neutral transformer is just one example of a grounded neutral fault detector. Other implementations of a ground fault detector and / or of a grounded neutral fault detector, as well as other corresponding implementations of the feedback loop, are contemplated. In various embodiments, if it is desirable to detect high frequency ground faults, which at high levels are dangerous to the human body, OPA1 out may be filtered using filters representative of human body models, and that output may be processed / conditioned with analog averaging / peak detection circuits, and then that output may be digitized by an ADC converter, and then a controller 140 may use the digitized samples to determine whether the high frequency signals are a high frequency ground fault that is dangerous based on the frequency indicated by the digitized samples. Such and other variations will be understood by persons skilled in the art and are within the scope of the present disclosure.

[0062] FIGS. 2-5 will now described below. Generally, FIG. 2 shows an example of a controller, and FIGS. 3-5 show examples of the voltage reference circuit 118 of FIG. 1.

[0063] Referring to FIG. 2, there is shown a diagram of an example of a controller 200 that may be used in the GFCI device (e.g., controller 140 of FIG. 1). In various embodiments, the controller 200 may be a microcontroller from Texas Instruments, Inc. identified by numbers MSPM0L13xx, where xx may be 03, 04, 05, or 06. Information on such microcontrollers are available at: https: / / www.ti.com / microcontrollers-mcus-processors / arm-based-microcontrollers / arm-cortex-mO-mcus / products.html. The data sheets of all such controllers are hereby incorporatedby reference herein in their entirety. In various embodiments, the controller 200 may not be a Texas Instruments, Inc. microcontroller and may be any other controller.

[0064] In FIG. 2, the illustrated controller is not shown with pin labels, but pin labels are shown in FIG. 1 and in FIGS. 3-5. Some examples of PIN labels include, without limitation, OPA0 IN+, OPA0 IN-, OP A0 OUT, OPA1 IN+, OPA1 IN-, OPA1 OUT, COMP IN+, COMP IN-, COMP OUT, LINE MONITOR, TEST GFCI, BUTTON, TRIP, and SCR FIRE, among other possible pin labels. The appearance of a pin label in such figures indicates that they are connected to a corresponding pin in the controller 200 of FIG. 2.

[0065] Generally, the controller 200 may include one or more analog-to-digital converters (ADC) that sample and convert analog signals to digital values. For example, in various embodiments, the controller 200 may include ADCs for sampling the Vref signal, the LPF out signal, and the OPAl out signal in FIG. 1. The controller 200 may also include one or more opamps. For example, in various embodiments, the controller 200 may include both op-amp OP A0 116 and op-amp OPA1 122 of FIG. 1. In various embodiments, the controller 200 may implement digital fdters for the low pass filter 121 and the high pass filter in block 122 of FIG. 1.

[0066] The controller 200 may perform other operations relating to GFCI operation, which persons skilled in the art will recognize. For example, some operations are described in U.S. Patent No. 9,276,393, which was incorporated by reference above. Various aspects and operations the controller 200 are described below.

[0067] In various embodiments, the controller 200 may include a processing unit 202; at least one memory unit 204, which may include one more types of memory, such as RAM, ROM, flash memory, EEPROM, etc.; a plurality of input / output pins 206; a clock unit CLK 208; op-amp(s) 116, 122; ADC(s) 227; and software or firmware modules 220 which include a series ofprogrammable instructions that are executable by the processing unit 202. The series of programmable instructions can be stored on a processor-readable medium accessible by the processing unit 202, such as memory unit 204, for performing the functions disclosed herein and to achieve a technical effect in accordance with the disclosure.

[0068] In accordance with aspects of the present disclosure, the controller 200 may include a voltage measurement circuit (e.g., 144, FIG. 1) that measures voltage levels and zero cross timing. Measured voltage levels can be used to calculate simulated test fault current used for self-test or manual test of the GFCI device (discussed below), so that a test fault threshold can be adjusted for, e.g., low voltage operations or when the GFCI device is used with a generator that goes into “sleep” mode when a load is not present. Such adjustments prevent test failures during low voltage operations or when the GFCI device is used with a generator that goes into “sleep” mode when a load is not present. Measuring zero crossing timing can also be used to detect “sleep” modes of generators and be used to adjust measurements based on real power line frequencies other than 60 Hz. In various embodiments, the controller 200 may perform periodic self-test by applying a simulated fault and measuring the response on the output of OP A0. Because operating voltage can vary significantly (for example, in generators going to sleep mode when load is not present), measuring the operating voltage allows for adjustments to avoid self-test failures due to low operating voltage conditions. In various embodiments, when operating voltage decreases below the trip solenoid capabilities, the self-test can be temporarily stopped.

[0069] The software / firmware modules 220 include several modules that may be discrete from one another or integrated together. The modules include a sampler module 224, a gain determination module 226, a test routine control module 228, an op-amp offset compensationmodule 230, an op-amp saturation compensation module 232, a reference voltage Vref correction module 234, an RMS determination module 236, and a fault determination module 238.

[0070] The sampler module 224 consults CLK 208 and controls sampling measured values, such as Vref, LPF out, and OPAl out, among others. In various embodiments, the sampling module 222 controls sampling to occur approximately every 255 / vs, or approximately 32 times per 60 Hz half cycle. In various embodiments, the sampling module 222 may control sampling to occur at or above a Nyquist rate of the expected frequency of OPAl out, e.g., at least 12-14 kHz sampling rate.

[0071] The gain determination module 226 receives a digitized form of output from the output terminal of op-amp 1 16 and performs a gain calculation in software by applying one or more equations that use one or more gain constants. The gain determination module 226 is calibrated by adjusting the one or more gain constants for the calculation to achieve the requisite sensitivity, as per requirements set by regulations, e.g., UL Standards, to sense ground faults within a predetermined range, which in the present example is 4-6 mA. The required sensitivity is achieved by selection of resistor components in a gain circuit (which persons skilled in the art will understand) and selection of the software gain constants. The software gain constants are stored in memory unit 224, e.g., in flash memory or EEPROM. Examples of gain circuits and resistor components are described in U.S. Patent No. 9,276,393.

[0072] Accordingly, by combining software calculations with the use of analog components in a gain circuit, adjustments for achieving the required sensitivity may be made to the software gain constants without adjusting any hardware components. The calibration of the software gain constants may be performed at predetermined intervals or in response to an event, by performing an automatic diagnostic routine.

[0073] Test routine control module 228 may initiate a test routine or be activated by an external event, such as activation of test button. When a test routine is initiated by manual activation of test button, the op-amp offset compensation module 226 may be activated. Operational amplifiers typically have an associated input offset voltage which is amplified along with the input signal, causing an error that is significant in the GFCI device because of the small differential voltage that is being amplified. Input offset voltage may further be influenced by ambient temperature. The opamp offset compensation module 230 compensates for the input offset voltage by measuring the differential voltage during a test routine that was initiated by activation of test button which opens contacts and excludes the possibility of an actual fault condition.

[0074] When op-amp 116 is saturated (which may be indicated when ADC 227 reads a maximum or minimum value), op-amp saturation compensation module 232 compensates by a predetermined factor. For smaller ground fault signals, this will accelerate response of the GFCI device to fault conditions without compromising noise immunity, with the ability to satisfy timing requirements for interrupting the circuit.

[0075] Vref correction module 234 may implement compensation for power source disturbances, which will be described below in connection with FIG. 4. For now, it is sufficient to note that if Vref is not constant and may meaningfully vary, then computations involving or based on Vref should take such variances into account. For example, Vref may be sampled at the same time and the same timing as other signals, and the sampled values of Vref may be used to compensate the sampled values of the other signals. Further details are described in connection with FIG. 4.

[0076] RMS determination module 236 determines an RMS value for measured signal properties for a signal, such as, for example, the OPAl out signal and / or a signal output of thedifferential transformer 112. The software modules 220 may determine RMS values that correspond to measured values and / or threshold values when performing calculations and making determinations, e.g., instead of average rectified current values, etc. UL requirements specify trip levels based on RMS rather than average current, thus providing guidelines that can be used by devices for a wide variety of applications in which power line voltage is not necessarily provided as a sine wave, such as in electrical power conversion applications. Conventionally, a GFCI device must be specially calibrated for use with such applications, because a conventional GFCI device is designed to measure average or peak current due to the power line voltage being a sine wave. RMS determination module 236, however, can determine the RMS value for an input wave of any shape by applying an appropriate algorithm without the need for calibration. That is, the RMS determination module 236 applies RMS calculated values to the input signal. In accordance with aspects of the present disclosure, the RMS determination module 236 may determine average or real RMS values of various signals (e.g., LPF out signal, OPAl out signal) for use in determining presence of ground faults and / or grounded neutral faults. Such an approach may ensure proper trip levels when the GFCI device is used in noise environments or with non-sinusoidal power (e.g., generated by power converters).

[0077] Circuit interruption is triggered by fault determination module 238. As mentioned above, persons skilled in the art will understand how to implement fault determination. An example is disclosed in U.S. Patent No. 9,276,393, which was incorporated by reference above. Furthermore, the fault determination module 238 may perform the operations of the present disclosure for distinguishing an actual grounded neutral fault from high frequency signals generated by a load. In accordance with aspects of the present disclosure, such operations include causing the controller 200 to enable and disable the grounded neutral transformer 114 and todetermine whether the OPAl_out signal includes high frequency signals when the grounded neutral transformer 114 is enabled and when it is disabled. In various embodiments, a controller 200 may disable the grounded neutral transformer 114 by closing a switch (130, FIG. 1) to shunt the differential transformer 112. The switch may be controlled by a pin of the controller 200. In various embodiments, a controller 200 may enable the grounded neutral transformer 114 by opening the switch and disengaging the shunt. In the simplest case, the switch may be a transistor, such as a MOSFET, which persons skilled in the art will recognize. In various embodiments, the controller 200 may enable and disable the grounded neutral transformer 114 by disconnecting the OPA1 output or the resonant circuit output in the positive feedback loop. In various embodiments, the controller 200 may enable and disable the differential transformer 112 based on the timing of a power line frequency, e.g., 60 Hz, such as based on the power line frequency, a multiple of the power line frequency (e.g., 120 Hz), or a fraction of the power line frequency (e.g., 30 Hz). For example, the controller 200 may alternate enabling the differential transformer 112 for one cycle and disabling the differential transformer 112 for one cycle. As another example, the controller 200 may alternate enabling the differential transformer 112 for one half-cycle and disabling the differential transformer 112 for one half-cycle. Further details are described in connection with FIG. 5.

[0078] The various constants for algorithms stored in the GFCI device can be calibrated during manufacturing. The constants can be stored within the controller 200, such as, for example, within flash memory or an EEPROM of the controller 200, and / or may be stored within non-volatile memory (not shown) outside the controller 200. The constants can be used to compensate for example, for differences in permeability of the magnetic core and / or number of turns of one or both of the transformers 1 12, 1 14, as well as variations in passive components. It is contemplatedthat calibration is performed for different temperatures and the corresponding constants for various temperatures in a particular temperature range stored in the GFCI device.

[0079] The GFCI device may be tested via a manually initiated test or an automatically initiated self-test. When performing a self-test, the test routine control module 228 controls a test circuit to generate a simulated ground fault. Persons skilled in the art will understand a test circuit, and an example is described in U.S. Patent No. 9,276,393. If the simulated ground fault is sensed, the GFCI device continues normal operation. However, if the simulated ground fault is not sensed, the GFCI device remains in a tripped condition or triggers a tripped condition so that power will not be provided to the load 106, and / or triggers an alarm. For a manual test, test button is actuated and a BUTTON signal is transmitted. Test routine control module 228 receives the BUTTON signal and transmits a control signal to activate test circuit for generating a simulated ground fault.

[0080] FIG. 2 is merely illustrative and variations are contemplated to be within the scope of the present disclosure.

[0081] FIG. 3 and FIG. 4 show examples of a voltage reference circuit and will now be described. In various embodiments, the voltage reference circuit of FIG. 3 and FIG. 4 implements the voltage reference circuit 118 of FIG. 1. In various embodiments, the voltage reference circuit may be an internal module of the controller of FIG. 1 or FIG. 2 or may be implemented by a field- programmable gate array (FPGA).

[0082] Referring now to FIG. 3, there is shown an example of a voltage reference circuit that is implemented using a low-dropout (LDO) regulator 310. The example of FIG. 3 may be used for the voltage reference circuit 118 of FIG. 1. In various embodiments, the LDO regulator 310 may be a component from Texas Instruments, Inc. or may be a component from other integrated circuit (IC) providers. The voltage reference circuit of FIG. 3 may provide a stable 1 ,2V reference voltage,as shown in FIG. 3. In various embodiments, the voltage reference circuit of FIG. 3 may provide other reference voltages, such as 1.35V, for example. A voltage reference produced by a LDO regulator is more stable and is less susceptible to power source disturbances.

[0083] Referring now to FIG. 4, there is shown an example of a voltage reference circuit that is implemented using a resistor divider with some degree of protection for higher frequency power source disturbances. In comparison to the LDO regulator of FIG. 3, the resistor divider is cheaper to implement but is more susceptible to power source disturbances. The capacitor C22 has an impedance that is lower for higher frequencies and serves as a shunt to ground for higher frequency disturbances in the power source voltage Vdd. The voltage reference circuit of FIG. 4 may be susceptible to power source disturbances at certain frequencies. Accordingly, if the resistor divider is used to provide a reference voltage, the GFCI device would need to account for such power source disturbances. For example, if power source disturbances introduce an undesirable frequency signal into the reference voltage, the undesirable frequency signal could also affect the OPAl out signal and could be misinterpreted as a grounded neutral fault. In accordance with aspects of the present disclosure, to address this disturbance, an ADC may sample the Vref signal of FIG. 4 at the same time and the same timing (e.g., same sampling rate) that OPAl out is sampled, and may compensate the OPAl out samples by subtracting (or otherwise compensating for) the Vref samples. Similarly, for any other signals that may be affected by variations in Vref due to power source disturbances, Vref may be sampled at the same time and the same timing that such other signals are sampled, and the Vref sample values may be used to compensate the other signal samples.

[0084] The voltage reference circuits of FIGS. 3 and 4 are merely examples. Other voltage reference circuits are contemplated to be within the scope of the present disclosure.

[0085] Accordingly, example components and circuitry for a GFCI device have been described above. As described above, a controller may distinguish an actual grounded neutral fault from high frequency signals generated by loads.

[0086] FIG. 5 shows a flow diagram of example operations of a GFCI device. The operations of FIG. 5 may be performed by the controller 200 of FIG. 2.

[0087] At block 510, the operation involves causing a grounded neutral (GN) fault detector to be enabled, where the GN fault detector is configured to provide a first signal in response to a (GN) fault on a neutral conductor, and where the first signal has a frequency above a power line frequency (e.g., 60 Hz). For example, the grounded neutral fault detector may be the grounded neutral transformer 114 of FIG. 1, and the first signal provided by the grounded neutral fault detector may be the resonant signal in the windings of the grounded neutral transformer 114. The resonant signal may have a frequency in the range of 3-10 kHz, for example, or in another frequency range above the power line frequency. The grounded neutral fault detector (e.g., grounded neutral transformer) may be enabled in the manner described above herein, e g., opening the switch 130, FIG. 1.

[0088] At block 520, the operation involves detecting a second signal while the GN fault detector is enabled, where the second signal has a frequency above the power line frequency. For example, the OPAl out signal (the second signal) may have a frequency above the power line frequency, such as in the 3-10 kHz range, or in another frequency range above the power line frequency.

[0089] At block 530, the operation involves causing the GN fault detector to be disabled. The grounded neutral fault detector (e.g., grounded neutral transformer) may be disabled in the manner described above herein, e.g., closing the switch 130, FIG. 1 .

[0090] At block 540, the operation involves, based on detecting no frequency above the power line frequency while the GN fault detector is disabled, causing a load to be disconnected. As described above herein, if the OPAl out signal has a frequency in the first frequency range (above the power line frequency) while the grounded neutral fault detector is enabled and while the grounded neutral fault detector is disabled, then it can be determined that the amplified signal is caused by high frequency noise from a load. But if the OPAl out signal has a frequency in the first frequency range (above the power line frequency) while the grounded neutral fault detector is enabled but not while the grounded neutral fault detector is disabled, then it can be determined that the amplified signal is caused by an actual grounded neutral fault. The grounded neutral fault detector (e.g., grounded neutral transformer) may be enabled and disabled in the manner described above herein, e.g., opening or closing the switch 130, FIG. 1.

[0091] FIG. 5 is illustrative, and variations are contemplated to be within the scope of the present disclosure. For example, in various embodiments, the operations may include operations other than those shown in FIG. 5. In various embodiments, the operations may not include every operation shown in FIG. 5. In various embodiments, the operations may have a different order than those shown in FIG. 5. Such and other embodiments are contemplated to be within the scope of the present disclosure.

[0092] FIG. 6 shows a flow diagram of another example of operations of a GFCI device. The operations of FIG. 6 may be performed by the controller 200 of FIG. 2.

[0093] At block 610, the operation involves obtaining an amplified signal in a positive feedback loop, where the feedback loop includes (i) a grounded neutral fault detector configured to provide a first signal in response to a grounded neutral fault on a neutral conductor where the first signal has a first frequency range, and (ii) an amplifier configured to amplify a second signalin the positive feedback loop to provide the amplified signal. The feedback loop may be the feedback loop described in connection with FIG. 1. For example, the grounded neutral fault detector may be the grounded neutral transformer 114 of FIG. 1, and the first signal provided by the grounded neutral fault detector may be the resonant signal in the windings of the grounded neutral transformer 114. The resonant signal may have a frequency in the range of 3-10 kHz, for example, or in another frequency range. The frequency range of the resonant signal would be the first frequency range. The amplifier may be the op-amp OPA1 of FIG. 1, and the amplified signal may be OPA1 out. The feedback loop is not limited to the example of FIG. 1, however, and other implementations are within the scope of the present disclosure.

[0094] At block 620, the operation involves determining whether the amplified signal has an amplified-signal frequency in the first frequency range while the grounded neutral fault detector is enabled and while the grounded neutral fault detector is disabled. For example, the OPAl out signal may have a frequency in the first frequency range, such as 3-10 kHz, or another frequency range. As described above herein, if the OPAl out signal has a frequency in the first frequency range while the grounded neutral fault detector is enabled and while the grounded neutral fault detector is disabled, then it can be determined that the amplified signal is caused by high frequency noise from a load. But if the OPAl out signal has a frequency in the first frequency range while the grounded neutral fault detector is enabled but not while the grounded neutral fault detector is disabled, then it can be determined that the amplified signal is caused by an actual grounded neutral fault. The grounded neutral fault detector (e.g., grounded neutral transformer) may be enabled and disabled in the manner described above herein, e.g., opening or closing the switch 130, FIG. 1.

[0095] At block 630, the operation involves, based on determining that the amplified signal has an amplified-signal frequency in the first frequency range while the GN fault detector isenabled but not while the GN fault detector is disabled, causing an interrupter to interrupt current flow through the neutral conductor.

[0096] FIG. 6 is illustrative, and variations are contemplated to be within the scope of the present disclosure. For example, in various embodiments, the operations may include operations other than those shown in FIG. 6. In various embodiments, the operations may not include every operation shown in FIG. 6. In various embodiments, the operations may have a different order than those that shown in FIG. 6. Such and other embodiments are contemplated to be within the scope of the present disclosure.

[0097] The embodiments disclosed herein are examples of the disclosure and may be embodied in various forms. For instance, although certain embodiments herein are described as separate embodiments, each of the embodiments herein may be combined with one or more of the other embodiments herein. Specific structural and functional details disclosed herein are not to be interpreted as limiting, but as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present disclosure in virtually any appropriately detailed structure. Like reference numerals may refer to similar or identical elements throughout the description of the figures.

[0098] The phrases “in an embodiment,” “in embodiments,” “in various embodiments,” “in some embodiments,” or “in other embodiments” may each refer to one or more of the same or different embodiments in accordance with the present disclosure. A phrase in the form “A or B” means “(A), (B), or (A and B) .” A phrase in the form “at least one of A, B, or C” means “(A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C) ”

[0099] Any of the herein described methods, programs, algorithms, or codes may be converted to, or expressed in, a programming language or computer program. The terms “programminglanguage” and “computer program,” as used herein, each include any language used to specify instructions to a computer, processor, or controller, and include (but is not limited to) the following languages and their derivatives: Assembler, Basic, Batch files, BCPL, C, C+, C++, Delphi, Fortran, Java, JavaScript, machine code, operating system command languages, Pascal, Perl, PL1, scripting languages, Visual Basic, metalanguages which themselves specify programs, and all first, second, third, fourth, fifth, or further generation computer languages. Also included are database and other data schemas, parameters and / or variables, and any other meta-languages. No distinction is made between languages which are interpreted, compiled, or use both compiled and interpreted approaches. No distinction is made between compiled and source versions of a program. Thus, reference to a program, where the programming language could exist in more than one state (such as source, compiled, object, or linked) is a reference to any and all such states. Reference to a program may encompass the actual instructions, variables, and parameters, and / or the intent of those instructions, variables, and parameters.

[0100] The systems described herein may also utilize one or more controllers to receive various information and transform the received information to generate an output. The controller may include any type of computing device, computational circuit, or any type of processor or processing circuit capable of executing a series of instructions that are stored in a memory. The controller may include multiple processors and / or multicore central processing units (CPUs) and may include any type of processor, such as a microprocessor, digital signal processor, microcontroller, programmable logic device (PLD), field programmable gate array (FPGA), or the like. The controller may also include a memory to store data and / or instructions that, when executed by the one or more processors, causes the one or more processors to perform one or more methods and / or algorithms.

[0101] It should be understood that the foregoing description is only illustrative of the present disclosure. Various alternatives and modifications can be devised by those skilled in the art without departing from the disclosure. Accordingly, the present disclosure is intended to embrace all such alternatives, modifications, and variations. The embodiments described with reference to the attached drawing figures are presented only to demonstrate certain examples of the disclosure. Other elements, steps, methods, and techniques that are insubstantially different from those described above and / or in the appended claims are also intended to be within the scope of the disclosure.

Claims

What is Claimed is:

1. A circuit interrupting device comprising: a grounded neutral (GN) fault detector configured to provide a first signal in response to a (GN) fault on a neutral conductor, the first signal having a frequency above a power line frequency; and a controller configured to perform: detecting a second signal while the GN fault detector is enabled, the second signal having a frequency above the power line frequency; causing the GN fault detector to be disabled; and based on detecting no frequency above the power line frequency while the GN fault detector is disabled, causing a load to be disconnected.

2. The circuit interrupting device of claim 1, further comprising: an amplifier arranged to form a positive feedback loop with the GN fault detector, the amplifier configured to amplify a second signal in the positive feedback loop to provide an amplified signal, wherein the controller is further configured to perform: determining whether the amplified signal has an amplified-signal frequency above the power line frequency while the GN fault detector is enabled and while the GN fault detector is disabled.

3. The circuit interrupting device of claim 2, wherein in the determining whether the amplified signal has an amplified-signal frequency above the power line frequency while the GNfault detector is enabled and while the GN fault detector is disabled, the controller is configured to perform: causing the GN fault detector to be enabled; determining a first frequency of the amplified signal while the GN fault detector is enabled; causing the GN fault detector to be disabled; and determining a second frequency of the amplified signal while the GN fault detector is disabled.

4. The circuit interrupting device of claim 3, wherein in the determining whether the amplified signal has an amplified-signal frequency above the power line frequency while the GN fault detector is enabled and while the GN fault detector is disabled, the controller is configured to, at least twice, cause the GN fault detector to be enabled and cause the GN fault detector to be disabled.

5. The circuit interrupting device of any one of the preceding claims, wherein the controller is configured to repeatedly alternate causing the GN fault detector to be enabled for one cycle of the power line frequency and causing the GN fault detector to disabled for one cycle of the power line frequency.

6. The circuit interrupting device of any one of the preceding claims, wherein the controller is configured to repeatedly alternate causing the GN fault detector to be enabled forone half-cycle of the power line frequency and causing the GN fault detector to be disabled for one half-cycle of the power line frequency.

7. The circuit interrupting device of any one of claims 2-6, further comprising: a comparator configured to provide an indication corresponding to each cycle of the amplified signal; and a counter configured to count the indication corresponding to each cycle of the amplified signal, wherein the controller is configured to read and reset the counter to determine the amplified-signal frequency.

8. The circuit interrupting device of any one of claims 2-7, further comprising: a ground fault detector configured to provide a third signal in response to the first signal and in response to detection of a ground fault on a phase conductor and the neutral conductor; a second amplifier configured to amplify a fourth signal to provide a second amplified signal, wherein the fourth signal is based on the third signal; and a high pass filter connected between an output of the second amplifier and an input of the first amplifier.

9. The circuit interrupting device of any one of claims 2-8, further comprising: a voltage reference circuit configured to provide a reference voltage, a first analog-to-digital converter (ADC), and a second ADC,the controller further configured to perform: sampling, by the first ADC, the amplified signal to provide first signal samples, wherein the sampling occurs at a sampling rate, and sampling, by the second ADC, the reference voltage to provide reference voltage samples, wherein the sampling by the second ADC occurs at the sampling rate.

10. The circuit interrupting device of claim 9, wherein the controller is further configured to perform: compensating the first signal samples based on the reference voltage samples.

11. The circuit interrupting device of any one of claims 2-10, wherein the controller is further configured to perform: based on determining that the amplified signal has an amplified-signal frequency above the power line frequency while the GN fault detector is enabled and while the GN fault detector is disabled, repeat, for another iteration, the determining whether the amplified signal has an amplified-signal frequency above the power line frequency while the GN fault detector is enabled and while the GN fault detector is disabled.

12. A method in a circuit interrupting device comprising: causing a grounded neutral (GN) fault detector to be enabled, the GN fault detector configured to provide a first signal in response to a (GN) fault on a neutral conductor, the first signal having a frequency above a power line frequency;detecting a second signal while the GN fault detector is enabled, the second signal having a frequency above the power line frequency; causing the GN fault detector to be disabled; and based on detecting no frequency above the power line frequency while the GN fault detector is disabled, causing a load to be disconnected.

13. The method of claim 12, wherein an amplifier is arranged to form a positive feedback loop with the GN fault detector, the amplifier configured to amplify a second signal in the positive feedback loop to provide an amplified signal, the method further comprising: determining whether the amplified signal has an amplified-signal frequency above the power line frequency while the GN fault detector is enabled and while the GN fault detector is disabled.

14. The method of claim 13, wherein the determining whether the amplified signal has an amplified-signal frequency above the power line frequency while the GN fault detector is enabled and while the GN fault detector is disabled comprises: causing the GN fault detector to be enabled; determining a first frequency of the amplified signal while the GN fault detector is enabled; causing the grounded neutral fault detector to be disabled; and determining a second frequency of the amplified signal while the GN fault detector is disabled.

15. The method of claim 14, where the determining whether the amplified signal has an amplified-signal frequency above the power line frequency while the GN fault detector is enabled and while the GN fault detector is disabled comprises: at least twice, causing the GN fault detector to be enabled and causing the GN fault detector to be disabled.

16. The method of any one of claims 12-15, further comprising: repeatedly alternating causing the GN fault detector to be enabled for one cycle of the power line frequency and causing the GN fault detector to be disabled for one cycle of the power line frequency.

17. The method of any one of claims 12-16, further comprising: repeatedly alternating causing the GN fault detector to be enabled for one half-cycle of the power line frequency and causing the GN fault detector to be disabled for one half-cycle of the power line frequency.

18. The method of any one of claims 13-17, further comprising: providing an indication corresponding to each cycle of the amplified signal; counting the indication corresponding to each cycle of the amplified signal; and reading and resetting the count to determine the amplified-signal frequency.

19. The method of any one of claims 13-18, wherein the positive feedback loop further comprises:a ground fault detector configured to provide a third signal in response to the first signal and in response to detection of a ground fault on a phase conductor and the neutral conductor; a second amplifier configured to amplify a fourth signal to provide a second amplified signal, wherein the fourth signal is based on the third signal; and a high pass filter connected between an output of the second amplifier and an input of the first amplifier.

20. The method of any one of claims 13-19, further comprising: sampling, by a first analog-to-digital converter (ADC), the amplified signal to provide first signal samples, wherein the sampling occurs at a sampling rate, and sampling, by a second ADC, a reference voltage to provide reference voltage samples, wherein the sampling by the second ADC occurs at the sampling rate.

21. The method of claim 20, further comprising: compensating the first signal samples based on the reference voltage samples.

22. The method of any one of claims 13-21, further comprising: based on determining that the amplified signal has an amplified-signal frequency above the power line frequency while the GN fault detector is enabled and while the GN fault detector is disabled, repeating, for another iteration, the determining whether the amplified signal has an amplified-signal frequency above the power line frequency while the GN fault detector is enabled and while the GN fault detector is disabled.

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