Scheduling method, program, network device, and display method

Abstract

A scheduling method for scheduling packet delivery of a network device constituting a network is provided, wherein: gate control information for controlling a gate for delivering a packet of the network device is generated on the basis of the specifications of the network; a merging gate of the network device with which the packet merges is identified on the basis of the specifications of the network; and common gate control information is applied to the identified merging gate to schedule packet delivery of the network device.

Description

Scheduling method, program, network device, and display method

[0001] The present disclosure relates to a scheduling method, a program, a network device, and a display method.

[0002] The introduction of Ethernet (registered trademark)-based Time Sensitive Networking (TSN) is being considered as a technology that ensures real-time communication between FA (Factory Automation) devices such as manufacturing equipment and production lines in factories.

[0003] Patent Document 1 discloses a technique for performing scheduling so as to satisfy end-to-end delay using TAS (Time Aware Shaper), which is one method of TSN.

[0004] Special Publication No. 2023-517143

[0005] However, when trying to solve a schedule that satisfies a large number of constraints using a mixed integer programming problem to guarantee real-time communication for the large amount of traffic between FA devices with various data cycles and sizes, the number of schedule combinations becomes enormous, which can result in cases where the network data stream cannot be scheduled appropriately.

[0006] Non-limiting embodiments of the present disclosure contribute to providing a network device, a scheduling method, a program, and a node graph display method that can appropriately schedule data streams in a network.

[0007] A scheduling method according to one embodiment of the present disclosure is a scheduling method for scheduling packet transmission of network devices that constitute a network, which generates gate control information for controlling a gate that transmits packets of the network device based on the specifications of the network, identifies a junction gate of the network device where packets will merge based on the specifications of the network, and applies common gate control information to the identified junction gate to schedule packet transmission of the network device.

[0008] A program according to one embodiment of the present disclosure is a program for scheduling packet transmission of network devices that constitute a network, and causes a processor to execute the following process: generate gate control information for controlling the gate that transmits packets of the network device based on the specifications of the network; identify a junction gate of the network device where packets will merge based on the specifications of the network; and apply common gate control information to the identified junction gate to schedule packet transmission of the network device.

[0009] A network device according to one embodiment of the present disclosure is a network device that constitutes a network and schedules packet transmission, and includes a generation unit that generates gate control information that controls a gate that transmits packets of the network device based on the specifications of the network, an identification unit that identifies a junction gate of the network device where packets will merge based on the specifications of the network, and a scheduling unit that applies common gate control information to the identified junction gate to schedule packet transmission of the network device.

[0010] A display method according to one embodiment of the present disclosure displays, on a display, gate information of a merging gate where packets of network devices constituting a network merge, and displays, on the display, a time chart showing the timing of sending packets at the merging gate, and the time chart displays the section in which the gate of the merging gate is opened and closed, and the open / closed state of the gate in the section based on the priority of the packets.

[0011] These comprehensive or specific aspects may be realized as a system, an apparatus, a method, an integrated circuit, a computer program, or a recording medium, or may be realized as any combination of a system, an apparatus, a method, an integrated circuit, a computer program, and a recording medium.

[0012] According to an embodiment of the present disclosure, the data stream of the network can be appropriately scheduled.

[0013] Further advantages and effects in an embodiment of the present disclosure will be clarified from the specification and the drawings. Such advantages and / or effects are respectively provided by some embodiments and the features described in the specification and the drawings, but not all of them are necessarily provided in order to obtain one or more identical features.

[0014] Figure showing an example of a network system according to an embodiment of the present disclosure. Figure showing a block configuration example of NW devices constituting the network system of Figure 1. Figure showing a detailed block configuration example of a switch. Figure showing a detailed block configuration example of the gate of a switch. Figure showing an example of a time chart of input packets and output packets. Figure showing a detailed block configuration example of GCL generation. Figure showing a data configuration example of NW traffic specifications. Figure for explaining the generation of a delay model. Figure for explaining the generation of a delay model. Figure for explaining the generation of a GCL frame. Figure for explaining the generation of common GCL. Figure showing an example of a delay evaluation result. Figure showing an example of generated GCL. Flowchart showing an operation example of an NW device. Flowchart showing a detailed operation example of S3 in Figure 13. Figure showing an example of the delay evaluation of common GCL in a time chart. Flowchart showing a detailed operation example of S4 in Figure 13. Figure showing an example of the delay evaluation of common GCL in a time chart. Figure for explaining the time ratio of the gate section and a modification example of the gate state. Figure for explaining an adjustment example of BE packets. Figure showing an example of a GUI. Figure showing an example of a GUI.

[0015] Hereinafter, embodiments of the present disclosure will be described in detail with appropriate reference to the drawings. However, a more detailed description than necessary may be omitted. For example, a detailed description of well-known matters or a redundant description of substantially the same configuration may be omitted. This is to avoid making the following description unnecessarily redundant and to facilitate the understanding of those skilled in the art.

[0016] Note that the attached drawings and the following description are provided for those skilled in the art to fully understand the present disclosure, and it is not intended to limit the subject matter described in the claims thereby.

[0017] <System Configuration Diagram> Fig. 1 is a diagram illustrating an example of a network system 100 according to an embodiment of the present disclosure. The network system 100 is a network system in which TSN is introduced. As shown in Fig. 1, the network system 100 includes switches 1011 and 1012 and devices 1031 to 1034. The switches 1011 and 1012 and the devices 1031 to 1034 are connected via, for example, Ethernet. The network system 100 is constructed, for example, on a production line in a factory.

[0018] The switches 1011 and 1012 are NW (Network) devices that relay data streams (packets). The switch 1011 has a plurality of ports 1021. The switch 1012 has a plurality of ports 1022. The switches 1011 and 1012 relay packets between the ports 1021 and 1022, for example, by executing an application stored in a storage unit. The switches may also be referred to as relay nodes or relay devices.

[0019] Port 1021 of switch 1011 outputs a packet input to a certain port 1021 from the certain port 1021 in accordance with, for example, the packet's destination, priority, and a predetermined schedule. Port 1022 of switch 1012, like port 1021 of switch 1011, also outputs a packet input to a certain port 1022 from the certain port 1022 in accordance with the packet's destination, priority, and a predetermined schedule.

[0020] The devices 1031 to 1034 are network devices that serve as packet senders or receivers (destinations). The devices 1031 to 1034 operate as packet senders and / or packet receivers, for example, by executing an application stored in a storage unit. When operating as a packet sender, this device (or its application) may be called a talker. When operating as a packet receiver, this device (or its application) may be called a listener. The devices 1031 to 1034 may run multiple applications, and may operate as multiple talkers and / or multiple listeners.

[0021] The devices 1031 to 1034 are, for example, devices such as FA (Factory Automation) equipment such as PCs (Personal Computers) and PLCs (Programmable Logic Controllers), sensors, and actuators. The devices 1031 to 1034 may also be referred to as end devices. A device operating as a talker may also be referred to as a transmitting node or transmitting device. A device operating as a listener may also be referred to as a receiving node or receiving device. The devices 1031 to 1034 have at least one port (not shown) and may be connected to other NW devices.

[0022] <Block Diagram> Fig. 2 is a diagram showing an example of a block configuration of a network device 200 constituting the network system 100 of Fig. 1. As shown in Fig. 2, the network device 200 includes a receiving unit 201, a control unit 202, a transmitting unit 203, a UI (User Interface) unit 204, and a storage unit 205.

[0023] The receiving unit 201 performs a receiving process for packets input from the Ethernet connected to the port.

[0024] The control unit 202 controls the entire network device 200. The control unit 202 performs data processing based on the packets received by the receiving unit 201.

[0025] The control unit 202 may be configured by a processor such as a CPU (Central Processing Unit). The control unit 202 may implement the network communication processing functions of the switch and / or end device in accordance with a program (application) stored in the storage unit 205.

[0026] The transmitting unit 203 performs a transmitting process of outputting packets generated based on the data processing in the control unit 202 to the Ethernet connected to the port.

[0027] The UI unit 204 is an input / output device such as a keypad, a touch panel, and / or a display. The UI unit 204 outputs a signal corresponding to a user's operation to the control unit 202. The UI unit 204 displays an image corresponding to the signal output from the control unit 202 on the display.

[0028] The storage unit 205 stores an operating system (OS) program and application programs executed by the control unit 202. The storage unit 205 also stores various data necessary for processing by the control unit 202. The storage unit 205 may be, for example, a solid state drive (SSD), random access memory (RAM), flash memory, read only memory (ROM), and / or a hard disk drive (HDD). There may be one storage unit 205 or multiple storage units 205.

[0029] Depending on the functions of the network device 200, the network device 200 may not include the UI unit 204. The network device 200 may be remotely connected to another device such as a PC, and the other device may provide a user interface for the network device 200.

[0030] 3 is a diagram showing an example of a detailed block configuration of the switch 1011. As shown in Fig. 3, the switch 1011 has an input port 301, a router 302, a gate 303, and an output port 304. The switch 1012 also has a block configuration similar to that of the switch 1011.

[0031] The input port 301 may correspond to, for example, the receiving unit 201 in Fig. 2. The router 302 and gate 303 may correspond to, for example, the control unit 202 in Fig. 2. The output port 304 may correspond to, for example, the transmitting unit 203 in Fig. 2. The above-described correspondence relationships are merely examples, and the present invention is not limited to these. For example, the input port 301 and router 302 may correspond to the receiving unit 201 in Fig. 2. For example, the gate 303 and output port 304 may correspond to the transmitting unit 203 in Fig. 2.

[0032] The input port 301 converts signals from the Ethernet cable into packets (packet data), and outputs the converted packets to the router 302.

[0033] The router 302 analyzes the packet header and determines to which output port 304 the packet should be output. The router 302 determines the output port 304 to which the packet should be output based on the destination written in the packet header and the routing table, and outputs the packet to the gate 303 connected to the determined output port.

[0034] The gate 303 analyzes the headers of packets input from the multiple routers 302 and determines the order in which the packets should be output to the output port 304. The gate 303 schedules the output order and / or timing of the packets based on the priority and GCL (Gate Control List) included in the packet header, and outputs the packets to the output port 304.

[0035] The output port 304 converts the packet output from the gate 303 into an Ethernet signal and outputs it to an Ethernet cable.

[0036] Fig. 4 is a diagram showing a detailed block configuration example of the gate 303 of the switch 1011. As shown in Fig. 4, the gate 303 has a priority filter 402, a queue 403, a selector 404, a scheduler 405, and a GCL unit 406. In addition to the gate 303, Fig. 4 also shows the output port 304 shown in Fig. 3.

[0037] An arrow A4a in Fig. 4 indicates a packet input to the priority filter 402. An arrow A4b in Fig. 4 indicates a packet output from the output port 304. A packet has a destination and a priority, and for example, "30" in the packets indicated by arrows A4a and A4b indicates the destination of the packet, and "7", "6", and "5" indicate the priority.

[0038] Gate 303 outputs a plurality of input packets from output port 304. In the example of Fig. 4, gate 303 outputs four packets {30:7}, {30:6}, {30:5}, {30:7} from output port 304 as one packet sequence {30:7, 30:7, 30:6, 30:5}.

[0039] The priority filter 402 analyzes the packet header and determines the priority of the input packet. The priority filter 402 outputs the input packet whose priority has been determined to a queue 403 corresponding to the priority. The priority may be a priority related to the transmission order of the packets from the output port 304.

[0040] The queue 403 holds packets output from the priority filter 402 on a first-in, first-out (FIFO) basis. A plurality of queues 403 are provided for each priority. For example, the queues 403 range from the highest priority queue "7" to the lowest priority queue "0." Note that the number of queues 403 may be provided according to the number of priorities. For example, if 16 priorities are set, 16 queues 403 may be provided.

[0041] The selector 404 outputs the packet output from the queue 403 to the output port 304 under the control of the scheduler 405 .

[0042] The scheduler 405 controls the selector 404 based on the GCL generated by the GCL unit 406. For example, the scheduler 405 determines, based on the GCL list, when and for how long a packet held in which queue will be output, and controls the selector 404.

[0043] The GCL unit 406 generates a GCL. The GCL includes information for setting whether to open or close the selector 404. For example, the GCL includes information indicating when and for how long packets of which priority (queue) are to be output.

[0044] An example of a GCL is shown on the left side of the GCL unit 406 in Fig. 4. For example, the GCL [[100,7], [100,6], [100,5]] shown in Fig. 4 indicates that packets with priority 7 are output during the first 100 usec period, packets with priority 6 are output during the next 100 usec period, and packets with priority 5 are output during the final 100 usec period, repeating this operation. Based on the example GCL shown in Fig. 4, the four packets {30:7}, {30:6}, {30:5}, and {30:7} input to the priority filter 402 are sorted in the order {30:7, 30:7, 30:6, 30:5} and output from the output port 304.

[0045] <Time Chart> Fig. 5 is a diagram showing an example of a time chart of input packets and output packets. The horizontal axis t in Fig. 5 represents time. Packets 501 to 504 represent packets input to the priority filter 402. Packet 506 represents a packet output from the output port 304.

[0046] In the time chart of FIG. 5, the priority of packets 501 to 504 is indicated by the height of the rectangular packets 501 to 504, and the packet length (data size) of packets 501 to 504 is indicated by the width of the rectangular packets 501 to 504.

[0047] For example, packets 501 and 504 with a priority of 7 have the highest rectangular height. Packet 502 with a priority of 6 has the next highest rectangular height after packets 501 and 504 with a priority of 7. Packet 503 with a priority of 5 has the next highest rectangular height after packet 502 with a priority of 6. Packet 503 with a priority of 5 has the largest rectangular width. Packet 502 with a priority of 6 has the next largest rectangular width after packet 503 with a priority of 5. Packets 501 and 502 with a priority of 7 have the next largest rectangular width after packet 502 with a priority of 6.

[0048] In the drawings described below (for example, FIG. 15, etc.), the priority of a packet is indicated by the height of the rectangular packet, and the packet length of the packet is indicated by the width of the rectangular packet, as described above.

[0049] The GCL 505 indicates the open / closed state of the gate 303 for the input packet. In other words, the GCL 505 indicates the selection state of the queue 403 in the selector 404. In other words, the GCL 505 indicates the selection state based on the priority of the input packet.

[0050] The dotted line divisions in GCL 505 indicate intervals during which the selected state of packets is maintained (the output period of queue 403). In other words, the dotted line divisions in GCL 505 indicate intervals (gate intervals) during which gate 303 is opened and closed. In the example of Figure 5, the gate intervals include gate interval 1 from 0 to 100 usec, gate interval 2 from 100 to 200 usec, and gate interval 3 from 200 to 300 usec.

[0051] The three letters shown in each gate section of GCL 505 indicate the open / closed state of the gate. "o" (open) indicates that the gate is open, and "c" (close) indicates that the gate is closed. The order of the three letters indicates the priority. For example, the leftmost letter corresponds to priority "7," the middle letter corresponds to priority "6," and the rightmost letter corresponds to priority "5."

[0052] For example, as shown in FIG. 5, when the GCL is [[100, 7], [100, 6], [100, 5]], the gate state (selection state of the queue 403 in the selector 404) is "occ" in gate section 1, "coc" in gate section 2, and "cco" in gate section 3, as shown in GCL 505. That is, in gate section 1, the gate for priority 7 is open, and the gates for priorities 6 and 5 are closed. In gate section 2, the gate for priority 6 is open, and the gates for priorities 7 and 5 are closed. In gate section 3, the gate for priority 5 is open, and the gates for priorities 7 and 6 are closed.

[0053] In the drawings described below (for example, FIG. 15, etc.), the gate states are indicated by the letters "o" and "c" and the boundaries of the gate sections are indicated by dotted lines, as in the above.

[0054] In the present disclosure, for example, a store-and-forward method is assumed, so that a packet is input (reception of the packet starts), and after the entire packet is stored (after the square wave rises and falls), processing such as header analysis is performed, and the packet is forwarded.

[0055] When the input of a packet is completed (reception is completed), the gate section of the priority of that packet is open, and if the packet can be transmitted, the packet is transmitted.

[0056] For example, packets 501 and 504 with priority 7 have each been received within gate section 1. The gate state of gate section 1 is "occ," which means that transmission of packets with priority 7 is permitted (the gate is open). Therefore, packets 501 and 504 with priority 7 are output from output port 304 in gate section 1 (after an internal processing delay), as shown by packet 506.

[0057] The reception of the priority 6 packet 502 is completed within gate section 1, but the gate state of gate section 1 is "occ," and transmission of priority 6 packets is not permitted (the gate is closed). Therefore, transmission of the priority 6 packet 502 is delayed until the next gate section 2. In gate section 2, the gate state is "coc," and transmission of priority 6 packets is permitted. Therefore, the priority 6 packet 502 is output from the output port 304 (after an internal processing delay) in gate section 2, as shown by packet 506.

[0058] Packet 503 with priority 5 is received before packet 501 with priority 7, but the gate state of gate section 1 is "occ," and transmission of priority 5 packets is not permitted (the gate is closed). Therefore, transmission of packet 503 with priority 5 is delayed until the next gate section 2. In gate section 2, the gate state is "coc," and transmission of priority 5 packets is not permitted, and transmission of packet 503 with priority 5 is delayed until the next gate section 3. In gate section 3, the gate state is "cco," and transmission of priority 5 packets is permitted. Therefore, packet 503 with priority 5 is output from output port 304 (after an internal processing delay) in gate section 3, as shown by packet 506.

[0059] In this way, gate 303 schedules the output order and / or timing of multiple packets input at approximately the same time based on the priority and GCL written in the packet header, and outputs the packets to output port 304.

[0060] <GCL generation block diagram> In the network system 100, an appropriate GCL is set at the gate 303 where multiple packets with the same destination or passing through the same partial route converge, so as to satisfy communication conditions (constraints) such as delay characteristics and jitter characteristics required for traffic between the talker and the listener.

[0061] FIG. 6 is a diagram illustrating a detailed block configuration example of GCL generation. As illustrated in FIG. 6, the NW device 200 includes a GCL frame generator 602, a common GCL generator 603, an individual GCL adjuster 604, a delay model generator 606, and a delay evaluator 607. The UI unit 204 illustrated in FIG. 2 is also illustrated in FIG. 6. The NW traffic specification 601 input to the GCL frame generator 602 and the delay model generator 606 and the generated GCL 605 output from the individual GCL adjuster 604 are also illustrated in FIG. 6. The traffic specification 601 and the generated GCL 605 may be stored in the storage unit 205 illustrated in FIG. 2. The functions of each unit except the UI unit 204 may be implemented by the control unit 202 illustrated in FIG. 2.

[0062] The NW traffic specification 601 is data that sets the network specification indicating the topology of the network, such as the connection relationship of NW devices, and the traffic specification between the talker and the listener.

[0063] 7 is a diagram showing an example of the data configuration of the NW traffic specification 601. As shown in FIG. 7, the NW traffic specification 601 includes data of a network specification 701 and a traffic specification 702.

[0064] The network specification 701 includes data such as a source device (DevA), a destination device (DevB), a link speed, and a link delay. For example, the first line of the network specification 701 indicates that the network device PLC0 and the network device SW0 are connected at 100 Mbps Ethernet. The first line of the network specification 701 also indicates that the link delay between the network device PLC0 and the network device SW0 is set to 1 nsec. Note that this disclosure assumes full-duplex Ethernet communication, and although links are shown as a source and a destination, independent links may be used in both directions.

[0065] The traffic specification 702 includes data such as a traffic ID (Tid), a source talker (Src), a destination listener (Dst), a transmission period (Period), a transmission data size (Size), a priority (Priority), a permissible delay (Max_Delay), and a permissible jitter (Max_Jitter). For example, the traffic with traffic ID "1" shown in the traffic specification 702 indicates that the source talker is "PLC0" and the destination listener is "I / O0." Furthermore, the traffic with traffic ID "1" shown in the traffic specification 702 indicates that the transmission period is "500 usec," the transmission data size is "500 bytes," the priority is "7," the permissible delay is "250 usec," and the permissible jitter is "10 usec."

[0066] Traffic with a set allowable delay and allowable jitter, such as traffic with traffic ID "1," is sometimes called ST (Scheduled Traffic). In contrast, traffic with traffic ID "33" does not have a set allowable delay or allowable jitter. Traffic with no set allowable delay or allowable jitter is sometimes called BE (Best Effort). BE has no constraints on delay or jitter, and can arrive at the destination at any time (even if the delay and jitter are large).

[0067] Returning to the explanation of Fig. 6, the delay model generation unit 606 extracts the network connection relationships from the NW traffic specifications 601 and determines the route of each traffic. From the determined route, the delay model generation unit 606 determines the connection relationships of the gates through which packets of each traffic pass and the merging gates where packets of each traffic merge, and generates a delay model for calculating packet delay.

[0068] Delay Model Figures 8A and 8B are diagrams for explaining the generation of a delay model 803. Details of the delay model 803 shown in Figure 8A are shown in Figure 8B. Figure 8A shows a simplified version of the network specification 701 and traffic specification 702 shown in Figure 7.

[0069] The delay model generation unit 606 generates a device connection graph 801 indicating the connection relationships between devices from the network specification 701. Next, the delay model generation unit 606 searches for the shortest path 802 between the source talker and the destination listener for each traffic from the traffic specification 702 and the device connection graph 801. Based on the device route (route) of each traffic found, the delay model generation unit 606 generates a delay model 803 indicating the path (path) of the routers 302 and gates 303 through which the traffic passes. In the delay model 803, the delay model generation unit 606 identifies a junction gate where multiple packets with the same destination and passing through the same partial path merge (see the rectangular frame in FIG. 8B ), and sets the identified junction gate as a target gate for setting a common GCL, which will be described later. The delay model generation unit 606 determines the transmission order and delay of packets at each gate based on the set GCL, and accumulates these along the path to calculate the transmission delay of each traffic.

[0070] Returning to the explanation of Fig. 6, the GCL frame generator 602 determines the GCL period and the number of gate sections from the traffic specification 702, and generates a GCL frame.

[0071] GCL Frame Fig. 9 is a diagram for explaining the generation of a GCL frame 901. The GCL frame generator 602 determines the GCL period based on the ST transmission period of the traffic specification 702. For example, assume that the ST transmission periods are set to 500 usec and 1000 usec in the traffic specification 702. In this case, the GCL frame generator 602 sets 500 usec as the minimum period of the GCL frame 901 and 1000 usec as the common period (least common multiple) of the GCL frame 901, as shown in Fig. 10.

[0072] Next, the GCL frame generator 602 obtains the number of priorities used in the entire traffic from the traffic specification 702 and determines the number of gate sections of the GCL. For example, considering that a minimum number of gate sections is provided in the minimum period through which packets of all priorities can pass, the number of gate sections in the minimum period may be set to "number of priorities + α" (α is an integer equal to or greater than 1). For example, if three priorities 7, 6, and 5 are used, the gate sections are set so that at least three packets of priorities 7, 6, and 5 can pass during the minimum period. In the example of FIG. 10 , the number of gate sections in the minimum period of the GCL frame 901 is set to "3 + 1 = 4" (α = 1). By extending this to a common period, the number of gate sections in the GCL frame 901 is set to 8.

[0073] Returning to the explanation of FIG. 6, the common GCL generator 603 generates a common (single) GCL that is initially set for all merging gates. The common GCL is obtained by assigning a gate time ratio and a gate pattern to each gate section of the GCL frame 901 generated by the GCL frame generator 602. The gate time ratio indicates the time ratio of each gate section to the common period. The gate pattern indicates the opening and closing pattern by priority in each gate section.

[0074] Common GCL Figure 10 is a diagram illustrating the generation of a common GCL 1003. The common GCL generation unit 603 selects a combination of gate time ratios 1001 for a GCL frame 901 with a period of 1000 usec and eight gate sections. The gate time ratios 1001 are expressed, for example, as integer ratios. For example, the common GCL generation unit 603 assigns a value selected from integer values ​​of {1, 2, 3, 4} to each gate section to generate the gate time ratios 1001. In Figure 10, the common GCL generation unit 603 generates gate time ratios 1001 by assigning an integer ratio of [1:2:1:3:1:2:1:3] to gate sections 1 to 8.

[0075] The common GCL generating unit 603 may repeatedly assign the gate time ratios assigned to the gate sections 1 to 4, which are the minimum periods, or may assign gate time ratios of different values ​​to all eight gate sections.

[0076] The common GCL generator 603 assigns gate patterns 1002 to gate sections 1 to 8 of the GCL frame 901. The gate pattern 1002 may be, for example, a combination of coded character strings indicating the open / close status for each priority. The gate pattern 1002 may be assigned to gate sections 1 to 8 using a subset of all possible combinations of gate patterns for the number of priorities. For example, when priorities 7, 6, and 5 are used, the number of combinations of gate open / close status is eight. However, the gate state "ccc," which does not allow any of the priorities to pass, may be excluded from the gate pattern 1002. Furthermore, for example, the gate state "occo," in which the highest priority of 7 and the lowest priority of 5 are simultaneously open, among the priorities 7, 6, and 5, may be excluded from the gate pattern 1002. In FIG. 10, the common GCL generating unit 603 generates a gate pattern 1002 in which [ooc, ooc, ooc, ooc, ooo, occ, occ, cco, coo] is assigned to gate sections 1 to 8.

[0077] As described above, the common GCL generation unit 603 assigns a gate time ratio 1001 and a gate pattern 1002 to each gate section of the GCL frame 901 generated by the GCL frame generation unit 602, and generates a common GCL 1003. The common GCL may also be referred to as a candidate GCL.

[0078] The common GCL is set at a merging gate (see the rectangular box in FIG. 8B ) where multiple packets merge. By setting a common GCL with a common gate time ratio 1001 and gate pattern 1002 at all merging gates, the number of combinations of traffic scheduling (packet arrival order and output order) is reduced compared to when individual GCLs are generated and set at each merging gate.

[0079] Furthermore, the number of traffic scheduling combinations is restricted by limiting the number (in the example of FIG. 10, integer values ​​{1, 2, 3, 4}) that forms the basis of the gate time ratio 1001. The number of traffic scheduling combinations is also restricted by assigning gate patterns 1002 to gate sections 1 to 8 using a subset rather than all patterns of gate states.

[0080] Returning to the description of FIG. 6 , the common GCL 1003 is output to the delay evaluation unit 607. The delay evaluation unit 607 sets the common GCL 1003 at the merging gate of the delay model 803 generated by the delay model generation unit 606, and performs delay evaluation of all traffic. The result of the delay evaluation is returned to the common GCL generation unit 603. The common GCL generation unit 603 determines the gate time ratio and the combination of gate patterns based on the returned delay evaluation. The NW device 200 repeats this operation to generate the common GCL 1003 that minimizes the evaluation value of the delay evaluation of all traffic.

[0081] 11 is a diagram showing an example of a delay evaluation result 1101. The delay evaluation result 1101 is generated by the delay model generation unit 606. The delay evaluation result 1101 includes data such as a traffic ID (Tid), a source talker (Src), a destination listener (Dst), a worst delay (Worst Delay), jitter, a delay margin (Delay Margin), a jitter margin (Jitter Margin), and a constraint satisfaction / violation flag (OK / NG).

[0082] The worst delay indicates the maximum transmission delay of a packet. The jitter indicates the variation in the transmission delay of a packet. The delay margin indicates the value obtained by subtracting the worst delay from the allowable delay in the traffic specification 702 in FIG. 7. The jitter margin indicates the value obtained by subtracting the jitter value from the allowable jitter in the traffic specification 702. If the delay evaluation result 1101 satisfies the traffic specification 702 (constraint) (for example, if the allowable delay and / or allowable jitter is satisfied), the constraint satisfaction / violation flag is set to OK.

[0083] It should be noted that for BE packets such as those with traffic ID "33," delay and jitter constraints (allowable delay and allowable jitter) are not set, and therefore delay and jitter margins are not calculated.

[0084] Returning to the explanation of FIG. 6 , the individual GCL adjustment unit 604 extracts traffic for which constraints cannot be satisfied even when using the common GCL 1003 generated by the common GCL generation unit 603. The individual GCL adjustment unit 604 determines which gate section of which merging gate on the path of the extracted traffic is experiencing a large delay, and individually adjusts the GCL of the determined merging gate. For example, the individual GCL adjustment unit 604 adjusts the gate time ratio and / or gate pattern assigned to the gate section of the GCL of the determined merging gate and / or the gate sections before and after it. The individual GCL adjustment unit 604 outputs the adjusted GCL to the delay evaluation unit 607.

[0085] The delay evaluation unit 607 sets the common GCL 1003 to the merging gate of the delay model 803 generated by the delay model generation unit 606, sets the GCL input from the individual GCL adjustment unit 604 to the specified merging gate, and performs delay evaluation of all traffic. The delay evaluation result is returned to the individual GCL adjustment unit 604. The individual GCL adjustment unit 604 determines the gate time ratio and the combination of gate patterns based on the returned evaluation result. The NW device 200 repeats this operation and generates an individual GCL that minimizes the evaluation value of the delay evaluation of all traffic.

[0086] The generated GCL 605 shown in FIG. 6 includes the common GCL 1003 generated by the common GCL generating unit 603 and an individually adjusted GCL for a specific gate generated by the individual GCL adjusting unit 604 .

[0087] 12 is a diagram showing an example of a generated GCL 1201. The generated GCL 1201 is a generated GCL that shows in detail the generated GCL 605 in FIG. 6. The generated GCL 1201 includes the GCLs of all gates in the network system 100.

[0088] The generated GCL 1201 has data of the GCL ID (GCLid), gate name (Gate), and GCL. For example, the GCLids "1" and "2" of the generated GCL 1201 are set to a common GCL. The GCLids "3" and "15" are set to individually adjusted GCLs. The GCLid "31," which is not a merging gate, is set to [9999, 'ooo'], which indicates that the gate is always open.

[0089] The GCL display only needs to show the gate opening time and priority. In Fig. 18, it is displayed as [end time within the period, character string indicating the gate status], but it may also be expressed as [duration of the gate section, set of opening priorities]. Furthermore, the gate status character string may be represented as a bit vector of 1 and 0, for example.

[0090] Returning to the explanation of Fig. 6, the UI unit 204 displays information such as the input NW traffic specification 601, the GCL evaluation result by the delay evaluation unit 607, fine adjustment of the GCL, and the generated GCL 605 to be output, and allows the user to edit and operate the information.

[0091] Note that one of the NW devices 200 constituting the network system 100 may execute the above operation. The NW device 200 executing the above operation may distribute the generated or adjusted GCL to other NW devices constituting the network system 100. Also, an information processing device such as a PC or a server connected to the network system 100 may execute the above operation. The information processing device executing the above operation may distribute the generated or adjusted GCL to the NW devices constituting the network system 100.

[0092] 13 is a flowchart illustrating an example of the operation of the network device 200. The process of the flowchart illustrated in FIG. 13 may be executed, for example, when the network system 100 is constructed or when the network system 100 is changed.

[0093] The NW device 200 generates the shortest path 802 (passing / merging gates) between the source and destination and the delay model 803 from the NW traffic specification 601 (S1).

[0094] The NW device 200 extracts the number of priorities (classes) and the common period of the GCL frame 901 from the NW traffic specification 601. Based on the extracted number of priorities and the common period, the NW device 200 determines the number of gate sections of the GCL frame 901 in the common GCL and the gate states to be assigned to each gate section of the GCL frame 901 (S2). For example, as shown in FIG. 10 , the NW device 200 determines the number of gate sections to be "8" and six gate states, "ooo," "ooc," "occ," "coo," "coc," and "cco."

[0095] The network device 200 searches for a common GCL to be set for all the merging gates (S3). The process of S3 will be described in detail with reference to the flowchart of FIG.

[0096] The network device 200 extracts traffic that cannot satisfy the constraints in the common GCL found in S3, and modifies the gate section of the gate that is the cause of the constraints not being satisfied (S4). The process of S4 will be described in detail with reference to the flowchart of FIG.

[0097] The network device 200 determines whether all necessary GCLs have been generated (S5). If all necessary GCLs have not been generated ("N" in S5), the network device 200 proceeds to S3.

[0098] If all the necessary GCLs have been generated ("Y" in S5), the NW device 200 accepts confirmation and / or adjustment from the user via the UI unit 204 and ends the GCL generation (S6).

[0099] The order of the processes is not limited to the above. After the process of S4, the network device 200 may accept confirmation and / or adjustment from the user via the UI unit 204.

[0100] Fig. 14 is a flowchart showing a detailed operation example of S3 in Fig. 13. The NW device 200 divides the GCL frame 901 into gate sections equal to the number of gate sections determined in S2 in Fig. 13. That is, the NW device 200 divides the GCL frame 901 into gate sections equal to the number of gate sections.

[0101] The NW device 200 selects (S11) one gate time ratio from a plurality of candidate combinations of time ratios to be assigned to each gate section of the GCL frame 901. For example, as shown in FIG. 10 , the NW device 200 selects a gate time ratio 1001 of [1:2:1:3:1:2:1:3] from a plurality of candidate combinations of time ratios {1, 2, 3, 4} that can be assigned to gate sections 1 to 8.

[0102] The NW device 200 selects (S12) one gate pattern from a plurality of combination candidates of gate states (gate states determined in S2 of FIG. 13) to be assigned to each gate section of the GCL frame 901. For example, as shown in FIG. 10, the NW device 200 selects a gate pattern 1002 of [ooc, ooc, ooc, ooc, ooo, occ, occ, cco, coo] from a plurality of combination candidates of gate states {ooo, ooc, occ, coo, coc, cco} that can be assigned to gate sections 1 to 8.

[0103] The NW device 200 generates a common GCL 1003 based on the gate time ratio selected in S11 and the gate pattern selected in S12, and performs delay evaluation of all traffic using the delay model 803 generated in S1 of Fig. 13 (S13). An example of the common GCL 1003 is shown in Fig. 10. An example of a delay evaluation result 1101 of traffic in the delay model 803 is shown in Fig. 11.

[0104] The NW device 200 calculates an evaluation value of the common GCL from the delay evaluation result 1101. For example, the NW device 200 may calculate an evaluation value such that the smaller the value, the better the performance, using various values ​​or statistics such as the number of constraint-violating traffic, the maximum value of the worst delay, and the average value of the positive delay margin. The NW device 200 may weight the various values ​​or statistics of the delay evaluation result 1101, or may use the sum of the weighted values ​​as the evaluation value. Furthermore, the NW device 200 may substitute a value based on the delay evaluation result 1101 into an evaluation function, and use the value of the evaluation function as the evaluation value.

[0105] The NW device 200 determines whether the evaluation value of the delay evaluation of the common GCL based on the gate pattern selected in S12 is minimum or whether the loop process (loop process of S12 to S14) has been executed a predetermined number of times (S14). If the evaluation value is not minimum and the loop process has not been executed a predetermined number of times (N in S14), the NW device 200 returns to S12 and selects another gate pattern.

[0106] If the evaluation value of the delay evaluation in S14 becomes minimum or if the loop processing has been executed a predetermined number of times (Y in S14), the NW device 200 proceeds to S15. The NW device 200 determines whether the evaluation value of the delay evaluation of the common GCL based on the gate time ratio selected in S11 becomes minimum or whether the loop processing (loop processing from S11 to S15) has been executed a predetermined number of times (S15). If the evaluation value is not minimum and the loop processing has not been executed a predetermined number of times (N in S15), the NW device 200 proceeds to S11 and selects another gate time ratio.

[0107] If the evaluation value of the delay evaluation in S15 becomes the minimum or if the loop processing has been executed a predetermined number of times (Y in S15), the NW device 200 proceeds to S16. The NW device 200 generates a common GCL based on the gate time ratio and gating pattern selected when the result of the determination in S15 is "Y." The NW device 200 applies the generated common GCL to the delay model 803 generated in S1 of FIG. 13 and performs delay evaluation of all traffic (S16).

[0108] 13, the processing order of the inner loop (S12 to S14) and the outer loop (S11 to S15) may be interchanged. Also, the gate time allocation and gate pattern selection processes may be executed simultaneously, and one loop process may be executed.

[0109] Time Chart The delay evaluation result of S16 may be generated as a time chart and displayed on the UI unit 204.

[0110] Fig. 15 is a time chart showing an example of delay evaluation of a common GCL. Fig. 15 shows, from top to bottom, a time chart of each gate on the path through which a packet from source "CAM0" to destination "PLC2" passes. The time chart shows how the packet is delayed at each gate.

[0111] The numbers in the rectangles representing each packet in Figure 16 indicate the traffic ID (Tid). In Figure 13, traffic ID "21" is highlighted. A common GCL is set for the merging gates "SW3:SW0," "SW0:SW1," "SW1:SW2," "SW2:SW5," and "SW5:PLC2" (the gate sections and gate patterns indicated by dotted lines are common to each merging gate). The passing gate "CAM0:SW3" ​​is always open (there are no dotted lines separating the gates). In the example of Figure 13, it can be seen that the packet with traffic ID "21" is significantly delayed after the merging gate "SW1:SW2."

[0112] Returning to the explanation of the operation flow, Fig. 16 is a flowchart showing a detailed example of the operation of S4 in Fig. 13. The NW device 200 selects violating traffic in order of the importance of constraint violations, such as delay violations, jitter violations, and the number of lost BE packets (the number of packets that did not reach the destination within the delay evaluation period) (S21). For example, the NW device 200 selects traffic ID "21" which has a large delay margin violation in the delay evaluation result 1101 shown in Fig. 12.

[0113] The NW device 200 identifies the gate and gate section causing the violation (S22). For example, in the time chart shown in Fig. 17, delays occur in the packet with traffic ID "21" in gate section 4 of gate "SW1:SW2" shown in box 1701, gate section 8 of gate "SW2:SW5" shown in box 1702, and gate section 8 of gate "SW5:PLC2" shown in box 1703. The time chart in Fig. 17 is the same as the time chart in Fig. 15.

[0114] The NW device 200 modifies the time ratio and / or gate state of the identified gate section and / or the gate sections before and after the identified gate section, and performs re-evaluation using the delay model 803 (S23).

[0115] Correction of the time ratio of the gate section and the gate state Fig. 18 is a diagram for explaining an example of correction of the time ratio of the gate section and the gate state. Like Fig. 15 and Fig. 17, Fig. 18 shows, from top to bottom, a time chart of each gate on the path through which a packet from the source "CAM0" to the destination "PLC2" passes.

[0116] For example, the NW device 200 extends the time ratio of gate section 3, which is immediately before gate section 4 (see box 1701 in FIG. 17 ) of gate "SW1:SW2" identified in S22, and shortens the time ratio of gate section 4 (see box 1801 in FIG. 18 ). In this case, as shown in boxes 1701 in FIG. 17 and 1801 in FIG. 18 , traffic ID "21," which had been interrupted by low-priority traffic ID "31," is transmitted first, thereby shortening the delay of traffic ID "21." As a result, the packet of traffic ID "21" arrives in time for transmission in gate section 4 of gate "SW2:SW5."

[0117] 18, the NW device 200 extends the time ratio and changes the gate state from "oco" to "COc" so that traffic with traffic ID "21" can be transmitted in gate section 5 of gate "SW5:PLC2." Here, traffic ID "18," which has a high priority, is delayed from gate section 5 to gate section 6. However, since traffic ID "18" has a large delay margin, this margin can be allocated to traffic ID "21." Note that capital letters indicating the gate state indicate that the gate state has been changed.

[0118] Correction of the delay constraint violation for traffic ID "21" causes jitter in traffic ID "18." This jitter occurs due to the difference between the time percentage of gate section 1 and the time percentage of gate section 5 of gate "SW5:PLC2" (see the time percentage in box 1704 in FIG. 17 and the time percentage in box 1802 in FIG. 18). Therefore, the NW device 200 aligns the time percentage of gate section 1 with the time percentage of gate section 5, as shown in boxes 1802 and 1803 in FIG. 18, and changes the gate state from "OOC" to "CoC." This improves the jitter for traffic ID "18."

[0119] Adjustment of BE Packets If all the ST constraints are satisfied, the NW device 200 may perform adjustment to reduce the number of lost BE packets.

[0120] 19 is a diagram illustrating an example of adjusting a BE packet. In FIG. 19, a time chart of each gate on a path through which a packet from source "ED4" to destination "DS" passes is shown from top to bottom.

[0121] The network device 200 may open the gate for BE packets in a gate section where no high-priority packets arrive. For example, in FIG. 19 , the network device 200 changes the gate state of the gate section where no BE packets with priority 5 arrive and no other priority packets arrive (see boxes 1901 and 1902) to enable transmission of packets with priority 5.

[0122] Furthermore, when the time when a high-priority packet arrives is limited, the NW device 200 may adjust the bandwidth allocated to the BE packet so as to increase it. For example, as shown in a box 1903 in FIG. 19 , the NW device 200 may shorten the dead time of the gate section 6 of the gate "SW1:SW2" and extend the gate section 7.

[0123] Returning to the description of the flowchart in FIG. 16 , the NW device 200 determines whether the constraint violation has been improved in the GCL corrected (adjusted) in S23 (S24). For example, when one gate section is adjusted, the arrival order of packets at the downstream gate changes, and the evaluation result changes accordingly. Therefore, the NW device 200 may improve the constraint violation by adjusting the upstream gate and the gate section starting from the earliest gate. Alternatively, the NW device 200 may adjust the constraints to be adjusted in the order of delay, jitter, and number of lost packets. Alternatively, the NW device 200 may adjust the jitter at the final gate of each traffic path. If the constraint violation has not been improved (N in S24), the NW device 200 proceeds to S22. If the constraint violation has been improved (Y in S24), the NW device 200 proceeds to S25.

[0124] The NW device 200 performs a delay evaluation of the GCL in which the constraint violation has been improved, and determines whether the evaluation value is minimized or whether the loop processing has been executed a predetermined number of times (S25). If the evaluation value is not minimized and the loop processing has not been executed a predetermined number of times (N in S25), the NW device 200 proceeds to S21 and selects the violating traffic.

[0125] When the evaluation value of the delay evaluation in S25 becomes the minimum, or when the loop processing has been executed a predetermined number of times (Y in S25), the NW device 200 proceeds to S26. The NW device 200 sets the adjusted GCL with the minimum evaluation value as the individual adjustment GCL for the target gate, and sets the other GCLs as common GCLs and evaluates them using the delay model (S26).

[0126] <GUI> Figures 20 and 21 are diagrams showing an example of a GUI. Note that the chart display section 2003 shown in Figure 21 is a detailed illustration of the chart display section 2003 shown simply in Figure 20.

[0127] 20 may be displayed on, for example, a display included in the network device 200. The GUI screen 2001 may also be displayed on, for example, a display of an information processing device such as a PC connected to the network device 200. The GUI screen 2001 may also be displayed on, for example, a display of an information processing device such as a PC that has implemented thereon a program that simulates the configuration and operation described above.

[0128] As shown in FIG. 20, the GUI screen 2001 has a network traffic specification / result display section 2002, a chart display section 2003, a display traffic selection section 2004, a gate pattern editing section 2005 (see FIG. 21), a gate delimiter marker 2006 (see FIG. 21), a delay / jitter measurement marker 2007 (see FIG. 21), a transmission offset adjustment marker 2008 (see FIG. 21), and a GCL status 2009 (see FIG. 21).

[0129] 20 displays tabular data such as the network specification 701, the traffic specification 702, the delay evaluation result 1101, and the generated GCL 1201. Data displayed in the NW traffic specification and result display section 2002, such as the numerical value of each cell, may be edited by the user.

[0130] The display traffic selection unit 2004 selects data to be displayed in the chart display unit 2003 from the data displayed in the NW traffic specification and result display unit 2002. For example, a traffic ID for which a time chart is desired to be displayed may be selected from the delay evaluation result 1101 displayed in the NW traffic specification and result display unit 2002. The route of the selected traffic may be displayed in the device connection graph 801. The path of the selected traffic may be displayed in the delay model 803.

[0131] The chart display section 2003 displays charts and graphs such as time charts for each traffic (see, for example, FIGS. 5, 115, and 17 to 19), a device connection graph 801, and a delay model 803.

[0132] The gate pattern editing unit 2005 shown in Fig. 21 edits the gate pattern (gate state) for each gate section on the time chart. For example, by clicking on the character string of the gate pattern, the character string becomes editable and the gate pattern can be edited. To perform delay evaluation on the edited gate pattern, for example, the recalculation button shown in Fig. 20 is pressed. To return the gate pattern to its state before editing, for example, the Undo button in Fig. 20 is pressed.

[0133] The gate delimiter marker 2006 shown in Fig. 21 is used to edit the gate time ratio for each GCL gate section on the time chart. Clicking on the gate delimiter marker 2006 and dragging it left or right allows the time of the gate sections before and after it to be adjusted. To perform delay evaluation on the edited gate section, for example, press the recalculate button shown in Fig. 20. To return the gate section to its state before editing, for example, press the Undo button in Fig. 20.

[0134] The delay / jitter measurement marker 2007 shown in FIG. 21 specifies the start time and end time when measuring the delay time and / or jitter time of the target packet. Clicking on the delay / jitter measurement marker 2007 and dragging it left or right displays the time from the start marker to the end marker. Also, if the end marker is adjacent to a packet symbol (rectangle), the delay time of the packet in other periods may be measured in the same way, and the variation (jitter) may be displayed. The start marker may be automatically set to the time when transmission is started by the talker (application) that is the source of the packet symbol (rectangle) that the end marker is adjacent to.

[0135] The transmission offset adjustment marker 2008 shown in FIG. 21 adjusts the transmission offset of the target packet and specifies the transmission start time. The transmission offset adjustment marker 2008 adjusts the time at which transmission starts at the source talker (application) of the packet symbol (rectangle) that the end marker mentioned above is adjacent to. The transmission start time can be adjusted by clicking the transmission offset adjustment marker 2008 and dragging it left or right. To perform delay evaluation on the edited transmission offset, for example, press the recalculate button shown in FIG. 20. To return the transmission offset to the state before editing, for example, press the Undo button shown in FIG. 20.

[0136] The GCL status 2009 shown in Fig. 21 indicates whether the GCL of each gate has been individually adjusted. For example, a mark "-" indicates a gate for which no GCL has been set, and a mark "*" indicates a gate for which an individually adjusted or edited GCL has been set. If there is no mark, it indicates that a common GCL has been set.

[0137] By providing the network device 200 or the simulator with the GUIs shown in FIGS. 20 and 21 , the user can easily recognize how data streams merge and / or branch, which gates are congested, and how much bandwidth is available. The user can also easily recognize situations such as which data streams on which paths are exerting pressure on bandwidth constraints. The user can also easily recognize how much delay margin there is, whether unnecessary waiting time is occurring, and so on. Furthermore, the user can operate each part of the time chart as a handle, which facilitates editing and / or adjusting the GCL.

[0138] As described above, the NW device 200 generates a GCL that controls the gate 303 that transmits packets based on the NW traffic specification 601, identifies a merging gate where the packets will merge based on the NW traffic specification 601, and schedules packet transmission by applying a common GCL to the identified merging gate. This reduces the number of traffic scheduling combinations, enabling appropriate scheduling of network data streams. Furthermore, the scheduling time is reduced.

[0139] The network device 200 also displays gate information of the merging gate (e.g., see "CAM0:SW3", "SW3:SW0", ... in FIG. 21 ) on the display, and displays a time chart showing the timing of packet transmission at the merging gate. The time chart displays the intervals in which the merging gate is opened and closed (e.g., see the dotted lines in FIG. 21 ) and the open / closed state of the gate based on the priority of the packets in the intervals. This allows the user to easily understand the packet (traffic) stream.

[0140] Although the embodiments have been described above with reference to the drawings, the present disclosure is not limited to such examples. It is clear that a person skilled in the art can conceive of various modifications or alterations within the scope of the claims. It is understood that such modifications or alterations also fall within the technical scope of the present disclosure. Furthermore, the components in the embodiments may be combined in any manner without departing from the spirit of the present disclosure.

[0141] In the above-described embodiments, the notation "... part" used for each component may be replaced with other notations such as "... circuit," "... assembly," "... device," "... unit," or "... module."

[0142] The present disclosure can be realized by software, hardware, or software in conjunction with hardware. Each functional block used in the description of the above embodiments may be partially or entirely realized as an LSI, which is an integrated circuit, and each process described in the above embodiments may be partially or entirely controlled by a single LSI or a combination of LSIs. The LSI may be composed of individual chips, or may be composed of a single chip that includes some or all of the functional blocks. The LSI may have data input and output. Depending on the degree of integration, the LSI may also be called an IC, system LSI, super LSI, or ultra LSI.

[0143] The integrated circuit method is not limited to LSI, and may be realized by a dedicated circuit, a general-purpose processor, or a dedicated processor. Also, a field programmable gate array (FPGA) that can be programmed after LSI manufacturing, or a reconfigurable processor that can reconfigure the connections and settings of circuit cells within the LSI, may be used. The present disclosure may be realized as digital processing or analog processing.

[0144] Furthermore, if an integrated circuit technology that can replace LSI emerges due to advances in semiconductor technology or other derivative technologies, it is natural that such technology may be used to integrate functional blocks. The application of biotechnology, etc. is also a possibility.

[0145] The disclosures of the specification, drawings and abstract contained in Japanese Patent Application No. 2023-171390, filed on October 2, 2023, are incorporated herein by reference in their entirety.

[0146] The present disclosure is useful for techniques for adjusting networks in which TSN is introduced.

[0147] 100 Network system 1011, 1012 Switches 1021, 1022 Ports 1031 to 1034 Devices 200 NW device 201 Receiving unit 202 Control unit 203 Transmitting unit 204 UI ​​unit 205 Storage unit 301 Input port 302 Router 303 Gate 304 Output port

Claims

1. A scheduling method for scheduling packet transmission of network devices that make up a network, comprising the steps of: generating gate control information for controlling a gate that transmits packets of the network device based on a specification of the network; identifying a junction gate of the network device where packets will merge based on the specification of the network; and applying common gate control information to the identified junction gate to schedule packet transmission of the network device.

2. The scheduling method according to claim 1, wherein the gate control information includes gate section information indicating the section in which the gate is opened and closed, and gate state information indicating the open / closed state of the gate based on the priority of packets in the section.

3. The scheduling method according to claim 2, further comprising: determining a common packet sending period at the junction gate based on the specifications of the network; and setting the number of sections so that packets of each priority level that join the junction gate are sent within the packet sending period.

4. The scheduling method according to claim 2, further comprising: extracting traffic that does not satisfy traffic constraints based on the network specifications; identifying a gate among the merging gates that is causing the traffic constraints not to be satisfied; and adjusting the section and / or the open / closed state of the identified gate to schedule packet transmission of the network device.

5. The scheduling method according to claim 4, further comprising adjusting the section and / or the open / closed state of the identified gate so as to reduce a delay evaluation of the traffic.

6. The scheduling method according to claim 4, further comprising the step of accepting adjustments of the section and / or the open / closed state of the identified gate from a user.

7. The method of claim 4, wherein the traffic constraints are traffic delay and jitter.

8. A program for scheduling packet transmission of network devices that constitute a network, the program causing a processor to execute the following processes: generate gate control information for controlling a gate that transmits packets of the network device based on the specifications of the network; identify a junction gate of the network device where packets merge based on the specifications of the network; and schedule packet transmission of the network device by applying common gate control information to the identified junction gate.

9. A network device that constitutes a network and schedules packet transmission, comprising: a generation unit that generates gate control information for controlling a gate that transmits packets of the network device based on specifications of the network; an identification unit that identifies a junction gate of the network device where packets merge based on the specifications of the network; and a scheduling unit that applies common gate control information to the identified junction gate to schedule packet transmission of the network device.

10. A display method comprising: displaying on a display gate information of a junction gate where packets of network devices constituting a network join; and displaying on the display a time chart showing the timing of sending packets at the junction gate; and displaying on the time chart the section in which the gate of the junction gate is opened and closed, and the open / closed state of the gate in the section based on the priority of the packets.

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