Pixel circuit and display device

Abstract

A pixel circuit and a display device. The pixel circuit comprises a light-emitting element (E1), a driving circuit (10), a light-emitting control circuit (11), and a driving control circuit (12); under the control of the potential of a control node (Ct), the light-emitting control circuit (11) controls the driving circuit (10) to be connected to the light-emitting element (E1), or controls the driving circuit (10) to be connected to a power supply voltage end (VDD); under the control of the potential of a first node N1, the driving circuit (10) generates a driving current flowing from the power supply voltage end (VDD) to the light-emitting element (E1); and under the control of an initial control signal (RST) and on the basis of a voltage signal provided by a data line (DT), the driving control circuit (12) controls the control node (Ct) to be connected to the light-emitting control end (EM) or a light-emitting control voltage end (HF). When the pixel circuit works, the influence of IR voltage drop of the power supply voltage end (VDD) on display uniformity can be eliminated.

Description

Pixel circuit and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel circuit and a display device. Background Art

[0002] The display market is currently booming, and with increasing consumer demand for a wide range of display products, including laptops, smartphones, TVs, tablets, smartwatches, and fitness bands, more new display products are expected to emerge in the future. Micro LED (micro light-emitting diode) display technology boasts low power consumption, high brightness, ultra-high resolution and color saturation, fast response time, ultra-low power consumption, long lifespan, and high efficiency, making it considered the most competitive next-generation display technology.

[0003] In a micro-LED display, since the driving current of the micro-LED is relatively large, the voltage drop of the power supply in the display panel increases sharply as the current multiple increases, thereby affecting the uniformity of the backplane display.

[0004] Summary of the Invention

[0005] In one aspect, an embodiment of the present disclosure provides a pixel circuit including a light-emitting element, a driving circuit, a light-emitting control circuit, and a driving control circuit;

[0006] The light emitting control circuit is electrically connected to a control node, and is used to control the connection between the driving circuit and the light emitting element, or to control the connection between the driving circuit and a power supply voltage terminal, under the control of the potential of the control node;

[0007] The driving circuit is electrically connected to the first node, and under the control of the potential of the first node, the driving circuit generates a driving current flowing from the power supply voltage terminal to the light emitting element;

[0008] The driving control circuit is electrically connected to the control node, data line, initial control end, light-emitting control end and light-emitting control voltage end, respectively, and is used to control the connection between the control node and the light-emitting control end or the light-emitting control voltage end according to the voltage signal provided by the data line under the control of the initial control signal provided by the initial control end.

[0009] Optionally, the control terminal of the driving circuit is electrically connected to a first node, the first terminal of the driving circuit is electrically connected to a power supply voltage terminal, and the second terminal of the driving circuit is electrically connected to a driving node, and the driving circuit is configured to generate a driving current flowing from the power supply voltage terminal to the driving node under the control of the potential of the first node;

[0010] The light-emitting control circuit is also electrically connected to the driving node and the first pole of the light-emitting element respectively, and is used to control the connection between the driving node and the first pole of the light-emitting element under the control of the potential of the control node; the second pole of the light-emitting element is electrically connected to the first voltage terminal.

[0011] Optionally, the control terminal of the driving circuit is electrically connected to a first node, the first terminal of the driving circuit is electrically connected to a driving node, and the second terminal of the driving circuit is electrically connected to a first voltage terminal, and the driving circuit is configured to generate a driving current flowing from the driving node to the first voltage terminal under the control of the potential of the first node;

[0012] The first electrode of the light emitting element is electrically connected to the power supply voltage terminal;

[0013] The light emitting control circuit is also electrically connected to the second electrode of the light emitting element and the driving node respectively, and is used to control the connection between the second electrode of the light emitting element and the driving node under the control of the potential of the control node.

[0014] Optionally, the pixel circuit described in at least one embodiment of the present disclosure further includes a storage circuit and a voltage control circuit;

[0015] A first end of the energy storage circuit is electrically connected to the first node, a second end of the energy storage circuit is electrically connected to the second node, and the energy storage circuit is used to store electrical energy;

[0016] The voltage control circuit is electrically connected to the light-emitting control terminal, the second voltage terminal and the second node respectively, and is used to control the connection between the second voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control terminal.

[0017] Optionally, the initial control end includes a first initial control end and a second initial control end;

[0018] The drive control circuit includes a first writing circuit, a second writing circuit, a first control circuit, a second control circuit, a first voltage maintaining circuit and a second voltage maintaining circuit;

[0019] The first writing circuit is electrically connected to the third node, the data line and the first initial control terminal respectively, and is used to control the connection between the data line and the third node under the control of a first initial control signal provided by the first initial control terminal;

[0020] The second writing circuit is electrically connected to the fourth node, the data line and the second initial control terminal respectively, and is used to control the connection between the data line and the fourth node under the control of the second initial control signal provided by the second initial control terminal;

[0021] The first control circuit is electrically connected to the third node, the light emitting control terminal and the control node respectively, and is used to control the connection between the light emitting control terminal and the control node under the control of the potential of the third node;

[0022] The second control circuit is electrically connected to the fourth node, the light-emitting control voltage terminal, and the control node, respectively, and is configured to control the connection between the light-emitting control voltage terminal and the control node under the control of the potential of the fourth node;

[0023] The first voltage maintaining circuit is electrically connected to the third node, and is configured to maintain the potential of the third node;

[0024] The second voltage maintaining circuit is electrically connected to the fourth node and is configured to maintain a potential of the fourth node.

[0025] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a first initialization circuit and a second initialization circuit;

[0026] The first initialization circuit is electrically connected to the first initial control terminal, the initial voltage terminal, and the first node, respectively, and is configured to write the initial voltage provided by the initial voltage terminal into the first node under the control of a first initial control signal provided by the first initial control terminal;

[0027] The second initialization circuit is electrically connected to the first initial control terminal, the reference voltage terminal and the second node respectively, and is used to write the reference voltage provided by the reference voltage terminal into the second node under the control of the first initial control signal provided by the first initial control terminal.

[0028] Optionally, the drive control circuit includes a third writing circuit, a third control circuit, a fourth control circuit and a third voltage maintaining circuit;

[0029] The third writing circuit is electrically connected to the fifth node, the data line and the initial control terminal respectively, and is used to control the connection between the data line and the fifth node under the control of the initial control signal provided by the initial control terminal;

[0030] The third control circuit is electrically connected to the fifth node, the light-emitting control terminal, and the control node, respectively, and is configured to control the connection between the control node and the light-emitting control terminal under the control of the potential of the fifth node;

[0031] The fourth control circuit is electrically connected to the fifth node, the light-emitting control voltage terminal, and the control node, respectively, and is configured to control the connection between the control node and the light-emitting control voltage terminal under the control of the potential of the fifth node;

[0032] The third voltage maintaining circuit is electrically connected to the fifth node and is configured to maintain the potential of the fifth node.

[0033] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a first initialization circuit and a second initialization circuit;

[0034] The first initialization circuit is electrically connected to the initial control terminal, the initial voltage terminal, and the first node, respectively, and is configured to write the initial voltage provided by the initial voltage terminal into the first node under the control of the initial control signal provided by the initial control terminal;

[0035] The second initialization circuit is electrically connected to the initial control terminal, the reference voltage terminal and the second node respectively, and is used to write the reference voltage provided by the reference voltage terminal into the second node under the control of the initial control signal provided by the initial control terminal.

[0036] Optionally, the pixel circuit described in at least one embodiment of the present disclosure further includes a data writing circuit and a compensation control circuit;

[0037] The data writing circuit is electrically connected to the write control terminal, the data line and the second node respectively, and is used to control the connection between the data line and the second node under the control of the write control signal provided by the write control terminal;

[0038] The compensation control circuit is electrically connected to the compensation control terminal, the first node and the driving node respectively, and is used to control the communication between the first node and the driving node under the control of the compensation control signal provided by the compensation control terminal.

[0039] Optionally, the first writing circuit includes a first transistor, the second writing circuit includes a second transistor, the first control circuit includes a third transistor, and the second control circuit includes a fourth transistor;

[0040] The gate of the first transistor is electrically connected to the first initial control terminal, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the third node;

[0041] The gate of the second transistor is electrically connected to the second initial control terminal, the first electrode of the second transistor is electrically connected to the data line, and the second electrode of the second transistor is electrically connected to the fourth node;

[0042] The gate of the third transistor is electrically connected to the third node, the first electrode of the third transistor is electrically connected to the light emitting control terminal, and the second electrode of the third transistor is electrically connected to the control node;

[0043] The gate of the fourth transistor is electrically connected to the fourth node, the first electrode of the fourth transistor is electrically connected to the light emitting control voltage terminal, and the second electrode of the fourth transistor is electrically connected to the control node.

[0044] Optionally, the first voltage maintaining circuit includes a first capacitor, and the second voltage maintaining circuit includes a second capacitor;

[0045] A first end of the first capacitor is electrically connected to the third node, and a second end of the first capacitor is electrically connected to a DC voltage terminal;

[0046] A first end of the second capacitor is electrically connected to the fourth node, and a second end of the second capacitor is electrically connected to a DC voltage end.

[0047] Optionally, the first initialization circuit includes a fifth transistor, and the second initialization circuit includes a sixth transistor;

[0048] The gate of the fifth transistor is electrically connected to the first initial control terminal, the first electrode of the fifth transistor is electrically connected to the initial voltage terminal, and the second electrode of the fifth transistor is electrically connected to the first node;

[0049] A gate of the sixth transistor is electrically connected to the first initial control terminal, a first electrode of the sixth transistor is electrically connected to the reference voltage terminal, and a second electrode of the sixth transistor is electrically connected to the second node.

[0050] Optionally, the third writing circuit includes a seventh transistor, the third control circuit includes an eighth transistor, and the fourth control circuit includes a ninth transistor;

[0051] The gate of the seventh transistor is electrically connected to the initial control terminal, the first electrode of the seventh transistor is electrically connected to the data line, and the second electrode of the seventh transistor is electrically connected to the fifth node;

[0052] The gate of the eighth transistor is electrically connected to the fifth node, the first electrode of the eighth transistor is electrically connected to the light emitting control terminal, and the second electrode of the eighth transistor is electrically connected to the control node;

[0053] The gate of the ninth transistor is electrically connected to the fifth node, the first electrode of the ninth transistor is electrically connected to the light emitting control voltage terminal, and the second electrode of the ninth transistor is electrically connected to the control node.

[0054] Optionally, the third voltage maintaining circuit includes a third capacitor;

[0055] A first end of the third capacitor is electrically connected to the fifth node, and a second end of the third capacitor is electrically connected to a DC voltage end.

[0056] Optionally, the first initialization circuit includes a fifth transistor, and the second initialization circuit includes a sixth transistor;

[0057] The gate of the fifth transistor is electrically connected to the initial control terminal, the first electrode of the fifth transistor is electrically connected to the initial voltage terminal, and the second electrode of the fifth transistor is electrically connected to the first node;

[0058] A gate of the sixth transistor is electrically connected to the initial control terminal, a first electrode of the sixth transistor is electrically connected to the reference voltage terminal, and a second electrode of the fifth transistor is electrically connected to the second node.

[0059] Optionally, the driving circuit includes a driving transistor, and the light emitting control circuit includes a tenth transistor;

[0060] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the power supply voltage terminal, and the second electrode of the driving transistor is electrically connected to the driving node;

[0061] The gate of the tenth transistor is electrically connected to the light emitting control terminal, the first electrode of the tenth transistor is electrically connected to the power supply voltage terminal, and the second electrode of the tenth transistor is electrically connected to the first electrode of the light emitting element.

[0062] Optionally, the driving circuit includes a driving transistor, and the light emitting control circuit includes a tenth transistor;

[0063] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the driving node, and the second electrode of the driving transistor is electrically connected to the first voltage terminal;

[0064] The gate of the tenth transistor is electrically connected to the light emitting control terminal, the first electrode of the tenth transistor is electrically connected to the second electrode of the light emitting element, and the second electrode of the tenth transistor is electrically connected to the driving node.

[0065] Optionally, the energy storage circuit includes a storage capacitor, and the voltage control circuit includes an eleventh transistor;

[0066] The first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to the second node;

[0067] The gate of the eleventh transistor is electrically connected to the light emitting control terminal, the first electrode of the eleventh transistor is electrically connected to the second voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the second node.

[0068] Optionally, the data writing circuit includes a twelfth transistor, and the compensation control circuit includes a thirteenth transistor;

[0069] The gate of the twelfth transistor is electrically connected to the write control terminal, the first electrode of the twelfth transistor is electrically connected to the data line, and the second electrode of the twelfth transistor is electrically connected to the second node;

[0070] A gate of the thirteenth transistor is electrically connected to the compensation control terminal, a first electrode of the thirteenth transistor is electrically connected to the first node, and a second electrode of the thirteenth transistor is electrically connected to the driving node.

[0071] In a second aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned pixel circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] FIG1 is a structural diagram of a pixel circuit according to an embodiment of the present disclosure;

[0073] FIG2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0074] FIG3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0075] FIG4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0076] FIG5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0077] FIG6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0078] FIG7 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0079] FIG8 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0080] FIG9 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0081] FIG10 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0082] FIG11 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0083] FIG12 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0084] FIG13 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0085] FIG14 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0086] FIG15 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0087] FIG16 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0088] FIG17 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0089] FIG18 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG17 ;

[0090] FIG19 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0091] FIG20 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG19 ;

[0092] FIG21 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0093] FIG22 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG21 of the present disclosure;

[0094] FIG23 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0095] FIG24 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG23 of the present disclosure;

[0096] FIG25 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0097] FIG26 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0098] FIG. 27 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0099] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0100] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0101] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0102] The pixel circuit described in the embodiment of the present disclosure includes a light-emitting element, a driving circuit, a light-emitting control circuit and a driving control circuit;

[0103] The light emitting control circuit is electrically connected to a control node, and is used to control the connection between the driving circuit and the light emitting element, or to control the connection between the driving circuit and a power supply voltage terminal, under the control of the potential of the control node;

[0104] The driving circuit is electrically connected to the first node, and under the control of the potential of the first node, the driving circuit generates a driving current flowing from the power supply voltage terminal to the light emitting element;

[0105] The driving control circuit is electrically connected to the control node, data line, initial control end, light-emitting control end and light-emitting control voltage end, respectively, and is used to control the connection between the control node and the light-emitting control end or the light-emitting control voltage end according to the voltage signal provided by the data line under the control of the initial control signal provided by the initial control end.

[0106] When the pixel circuit described in the embodiment of the present disclosure is in operation, it can eliminate the influence of IR Drop (IR voltage drop) of the power supply voltage terminal VDD on display uniformity.

[0107] In at least one embodiment of the present disclosure, a control terminal of the driving circuit is electrically connected to a first node, a first terminal of the driving circuit is electrically connected to a power supply voltage terminal, and a second terminal of the driving circuit is electrically connected to a driving node, and the driving circuit is configured to generate a driving current flowing from the power supply voltage terminal to the driving node under the control of the potential of the first node;

[0108] The light-emitting control circuit is also electrically connected to the driving node and the first pole of the light-emitting element respectively, and is used to control the connection between the driving node and the first pole of the light-emitting element under the control of the potential of the control node; the second pole of the light-emitting element is electrically connected to the first voltage terminal.

[0109] As shown in FIG1 , the pixel circuit according to the embodiment of the present disclosure includes a light-emitting element E1 , a driving circuit 10 , a light-emitting control circuit 11 , and a driving control circuit 12 ;

[0110] The control terminal of the driving circuit 10 is electrically connected to the first node N1, the first terminal of the driving circuit 10 is electrically connected to the power supply voltage terminal VDD, and the second terminal of the driving circuit 10 is electrically connected to the driving node N0. The driving circuit 10 is configured to generate a driving current flowing from the power supply voltage terminal VDD to the driving node N0 under the control of the potential of the first node N1;

[0111] The light emitting control circuit 11 is electrically connected to the control node Ct, the driving node N0, and the first electrode of the light emitting element E1, respectively, and is configured to control the connection between the driving node N0 and the first electrode of the light emitting element E1 under the control of the potential of the control node Ct; the second electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1;

[0112] The drive control circuit 12 is electrically connected to the control node Ct, the data line DT, the initial control terminal RST, the light-emitting control terminal EM and the light-emitting control voltage terminal HF, respectively, and is used to control the connection between the control node Ct and the light-emitting control terminal EM or the light-emitting control voltage terminal HF according to the voltage signal provided by the data line DT under the control of the initial control signal provided by the initial control terminal RST.

[0113] In at least one embodiment of the present disclosure, the control terminal of the driving circuit is electrically connected to a first node, the first terminal of the driving circuit is electrically connected to a driving node, and the second terminal of the driving circuit is electrically connected to a first voltage terminal. The driving circuit is configured to generate a driving current flowing from the driving node to the first voltage terminal under the control of the potential of the first node.

[0114] The first electrode of the light emitting element is electrically connected to the power supply voltage terminal;

[0115] The light emitting control circuit is also electrically connected to the second electrode of the light emitting element and the driving node respectively, and is used to control the connection between the second electrode of the light emitting element and the driving node under the control of the potential of the control node.

[0116] Optionally, the first voltage terminal may be a low voltage terminal.

[0117] As shown in FIG2 , the pixel circuit according to the embodiment of the present disclosure includes a light-emitting element E1 , a driving circuit 10 , a light-emitting control circuit 11 , and a driving control circuit 12 ;

[0118] The control terminal of the driving circuit 10 is electrically connected to the first node N1, the first terminal of the driving circuit 10 is electrically connected to the driving node N0, and the second terminal of the driving circuit 10 is electrically connected to the first voltage terminal V1. The driving circuit 10 is configured to generate a driving current flowing from the driving node N0 to the first voltage terminal V1 under the control of the potential of the first node N1;

[0119] The first electrode of the light emitting element E1 is electrically connected to the power supply voltage terminal VDD;

[0120] The light emitting control circuit 11 is electrically connected to the control node Ct, the second electrode of the light emitting element E1, and the driving node N0, respectively, and is configured to control the connection between the second electrode of the light emitting element E1 and the driving node N0 under the control of the potential of the control node Ct;

[0121] The drive control circuit 12 is electrically connected to the control node Ct, the data line DT, the initial control terminal RST, the light-emitting control terminal EM and the light-emitting control voltage terminal HF, respectively, and is used to control the connection between the control node Ct and the light-emitting control terminal EM or the light-emitting control voltage terminal HF according to the voltage signal provided by the data line DT under the control of the initial control signal provided by the initial control terminal RST.

[0122] The pixel circuit according to at least one embodiment of the present disclosure may further include an energy storage circuit and a voltage control circuit;

[0123] A first end of the energy storage circuit is electrically connected to the first node, a second end of the energy storage circuit is electrically connected to the second node, and the energy storage circuit is used to store electrical energy;

[0124] The voltage control circuit is electrically connected to the light-emitting control terminal, the second voltage terminal and the second node respectively, and is used to control the connection between the second voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control terminal.

[0125] As shown in FIG3 , based on at least one embodiment of the pixel circuit shown in FIG1 , the pixel circuit according to at least one embodiment of the present disclosure may further include a voltage control circuit 13 and a tank circuit 14 ;

[0126] A first end of the energy storage circuit 14 is electrically connected to the first node N1, and a second end of the energy storage circuit 14 is electrically connected to the second node N2. The energy storage circuit 14 is used to store electrical energy.

[0127] The voltage control circuit 13 is electrically connected to the light emitting control terminal EM, the second voltage terminal V2 and the second node N2 respectively, and is used to control the connection between the second voltage terminal V2 and the second node N2 under the control of the light emitting control signal provided by the light emitting control terminal EM.

[0128] As shown in FIG4 , based on at least one embodiment of the pixel circuit shown in FIG2 , the pixel circuit according to at least one embodiment of the present disclosure may further include a voltage control circuit 13 and a tank circuit 14 ;

[0129] A first end of the energy storage circuit 14 is electrically connected to the first node N1, and a second end of the energy storage circuit 14 is electrically connected to the second node N2. The energy storage circuit 14 is used to store electrical energy.

[0130] The voltage control circuit 13 is electrically connected to the light emitting control terminal EM, the second voltage terminal V2 and the second node N2 respectively, and is used to control the connection between the second voltage terminal V2 and the second node N2 under the control of the light emitting control signal provided by the light emitting control terminal EM.

[0131] In at least one embodiment of the present disclosure, the initial control terminal includes a first initial control terminal and a second initial control terminal;

[0132] The drive control circuit includes a first writing circuit, a second writing circuit, a first control circuit, a second control circuit, a first voltage maintaining circuit and a second voltage maintaining circuit;

[0133] The first writing circuit is electrically connected to the third node, the data line and the first initial control terminal respectively, and is used to control the connection between the data line and the third node under the control of a first initial control signal provided by the first initial control terminal;

[0134] The second writing circuit is electrically connected to the fourth node, the data line and the second initial control terminal respectively, and is used to control the connection between the data line and the fourth node under the control of the second initial control signal provided by the second initial control terminal;

[0135] The first control circuit is electrically connected to the third node, the light emitting control terminal and the control node respectively, and is used to control the connection between the light emitting control terminal and the control node under the control of the potential of the third node;

[0136] The second control circuit is electrically connected to the fourth node, the light-emitting control voltage terminal, and the control node, respectively, and is configured to control the connection between the light-emitting control voltage terminal and the control node under the control of the potential of the fourth node;

[0137] The first voltage maintaining circuit is electrically connected to the third node, and is configured to maintain the potential of the third node;

[0138] The second voltage maintaining circuit is electrically connected to the fourth node and is configured to maintain a potential of the fourth node.

[0139] In a specific implementation, the initial control end may include a first initial control end and a second initial control end; the drive control circuit may include a first write circuit, a second write circuit, a first control circuit, a second control circuit, a first voltage maintaining circuit and a second voltage maintaining circuit; the first write circuit controls the connection between the data line and the third node under the control of the first initial control signal; the second write circuit controls the connection between the data line and the fourth node under the control of the second initial control signal; the first control circuit controls the connection between the light-emitting control end and the control node under the control of the potential of the third node; the second control circuit controls the connection between the light-emitting control voltage end and the control node under the control of the potential of the fourth node; the first voltage maintaining circuit maintains the potential of the third node; and the second voltage maintaining circuit maintains the potential of the fourth node.

[0140] As shown in FIG5 , based on the embodiment of the pixel circuit shown in FIG3 , the initial control terminal includes a first initial control terminal RSTA and a second initial control terminal RSTB;

[0141] The driving control circuit includes a first writing circuit 21, a second writing circuit 22, a first control circuit 23, a second control circuit 24, a first voltage maintaining circuit 25 and a second voltage maintaining circuit 26;

[0142] The first write circuit 21 is electrically connected to the third node N3, the data line DT and the first initial control terminal RSTA, respectively, and is used to control the connection between the data line DT and the third node N3 under the control of a first initial control signal provided by the first initial control terminal RSTA;

[0143] The second write circuit 22 is electrically connected to the fourth node N4, the data line DT and the second initial control terminal RSTB, and is used to control the connection between the data line DT and the fourth node N4 under the control of the second initial control signal provided by the second initial control terminal RSTB;

[0144] The first control circuit 23 is electrically connected to the third node N3, the light emitting control terminal EM, and the control node Ct, respectively, and is configured to control the light emitting control terminal EM to be connected to the control node Ct under the control of the potential of the third node N3;

[0145] The second control circuit 24 is electrically connected to the fourth node N4, the light-emission control voltage terminal HF, and the control node Ct, respectively, and is configured to control the connection between the light-emission control voltage terminal HF and the control node Ct under the control of the potential of the fourth node N4;

[0146] The first voltage maintaining circuit 25 is electrically connected to the third node N3 and is used to maintain the potential of the third node N3;

[0147] The second voltage maintaining circuit 26 is electrically connected to the fourth node N4 and is configured to maintain the potential of the fourth node N4.

[0148] As shown in FIG6 , based on the embodiment of the pixel circuit shown in FIG4 , the initial control terminal includes a first initial control terminal RSTA and a second initial control terminal RSTB;

[0149] The driving control circuit includes a first writing circuit 21, a second writing circuit 22, a first control circuit 23, a second control circuit 24, a first voltage maintaining circuit 25 and a second voltage maintaining circuit 26;

[0150] The first write circuit 21 is electrically connected to the third node N3, the data line DT and the first initial control terminal RSTA, respectively, and is used to control the connection between the data line DT and the third node N3 under the control of a first initial control signal provided by the first initial control terminal RSTA;

[0151] The second write circuit 22 is electrically connected to the fourth node N4, the data line DT and the second initial control terminal RSTB, and is used to control the connection between the data line DT and the fourth node N4 under the control of the second initial control signal provided by the second initial control terminal RSTB;

[0152] The first control circuit 23 is electrically connected to the third node N3, the light emitting control terminal EM, and the control node Ct, respectively, and is configured to control the light emitting control terminal EM to be connected to the control node Ct under the control of the potential of the third node N3;

[0153] The second control circuit 24 is electrically connected to the fourth node N4, the light-emission control voltage terminal HF, and the control node Ct, respectively, and is configured to control the connection between the light-emission control voltage terminal HF and the control node Ct under the control of the potential of the fourth node N4;

[0154] The first voltage maintaining circuit 25 is electrically connected to the third node N3 and is used to maintain the potential of the third node N3;

[0155] The second voltage maintaining circuit 26 is electrically connected to the fourth node N4 and is configured to maintain the potential of the fourth node N4.

[0156] The pixel circuit according to at least one embodiment of the present disclosure further includes a first initialization circuit and a second initialization circuit;

[0157] The first initialization circuit is electrically connected to the first initial control terminal, the initial voltage terminal, and the first node, respectively, and is configured to write the initial voltage provided by the initial voltage terminal into the first node under the control of a first initial control signal provided by the first initial control terminal;

[0158] The second initialization circuit is electrically connected to the first initial control terminal, the reference voltage terminal and the second node respectively, and is used to write the reference voltage provided by the reference voltage terminal into the second node under the control of the first initial control signal provided by the first initial control terminal.

[0159] In a specific implementation, the pixel circuit may further include a first initialization circuit and a second initialization circuit. The first initialization circuit writes the initial voltage provided by the initial voltage terminal into the first node under the control of a first initial control signal, and the second initialization circuit writes the reference voltage into the second node under the control of the first initial control signal to initialize the potential of the first node and the potential of the second node.

[0160] As shown in FIG7 , based on at least one embodiment of the pixel circuit shown in FIG5 , the pixel circuit according to at least one embodiment of the present disclosure further includes a first initialization circuit 31 and a second initialization circuit 32 ;

[0161] The first initialization circuit 31 is electrically connected to the first initial control terminal RSTA, the initial voltage terminal I1 and the first node N1 respectively, and is configured to write the initial voltage Vint provided by the initial voltage terminal I1 into the first node N1 under the control of the first initial control signal provided by the first initial control terminal RSTA;

[0162] The second initialization circuit 32 is electrically connected to the first initial control terminal RSTA, the reference voltage terminal REF and the second node N2 respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal REF into the second node N2 under the control of the first initial control signal provided by the first initial control terminal RSTA.

[0163] As shown in FIG8 , based on at least one embodiment of the pixel circuit shown in FIG6 , the pixel circuit according to at least one embodiment of the present disclosure further includes a first initialization circuit 31 and a second initialization circuit 32 ;

[0164] The first initialization circuit 31 is electrically connected to the first initial control terminal RSTA, the initial voltage terminal I1 and the first node N1 respectively, and is configured to write the initial voltage Vint provided by the initial voltage terminal I1 into the first node N1 under the control of the first initial control signal provided by the first initial control terminal RSTA;

[0165] The second initialization circuit 32 is electrically connected to the first initial control terminal RSTA, the reference voltage terminal REF and the second node N2 respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal REF into the second node N2 under the control of the first initial control signal provided by the first initial control terminal RSTA.

[0166] In at least one embodiment of the present disclosure, the drive control circuit may include a third writing circuit, a third control circuit, a fourth control circuit, and a third voltage maintaining circuit; the third writing circuit controls the connection between the data line and the fifth node under the control of an initial control signal;

[0167] The third control circuit is electrically connected to the fifth node, the light-emitting control terminal, and the control node, respectively, and is configured to control the connection between the control node and the light-emitting control terminal under the control of the potential of the fifth node;

[0168] The fourth control circuit is electrically connected to the fifth node, the light-emitting control voltage terminal, and the control node, respectively, and is configured to control the connection between the control node and the light-emitting control voltage terminal under the control of the potential of the fifth node;

[0169] The third voltage maintaining circuit is electrically connected to the fifth node and is configured to maintain the potential of the fifth node.

[0170] In a specific implementation, the driving control circuit may include a third writing circuit, a third control circuit, a fourth control circuit and a third voltage maintaining circuit; the third writing circuit controls the connection between the data line and the fifth node under the control of an initial control signal; the third control circuit controls the connection between the control node and the light-emitting control end under the control of the potential of the fifth node; the fourth control circuit controls the connection between the control node and the light-emitting control voltage end under the control of the potential of the fifth node; and the third voltage maintaining circuit maintains the potential of the fifth node.

[0171] As shown in FIG9 , based on the embodiment of the pixel circuit shown in FIG3 , the driving control circuit may include a third writing circuit 41 , a third control circuit 42 , a fourth control circuit 43 and a third voltage maintaining circuit 44 ;

[0172] The third write circuit 41 is electrically connected to the initial control terminal RST, the data line DT and the fifth node N5 respectively, and is used to control the connection between the data line DT and the fifth node N5 under the control of the initial control signal provided by the initial control terminal RST;

[0173] The third control circuit 42 is electrically connected to the fifth node N5, the light emitting control terminal EM, and the control node Ct, respectively, and is configured to control the connection between the control node Ct and the light emitting control terminal EM under the control of the potential of the fifth node N5;

[0174] The fourth control circuit 43 is electrically connected to the fifth node N5, the light-emission control voltage terminal HF, and the control node Ct, respectively, and is configured to control the connection between the control node Ct and the light-emission control voltage terminal HF under the control of the potential of the fifth node N5;

[0175] The third voltage maintaining circuit 44 is electrically connected to the fifth node N5 and is configured to maintain the potential of the fifth node N5.

[0176] As shown in FIG10 , based on the embodiment of the pixel circuit shown in FIG4 , the driving control circuit may include a third writing circuit 41 , a third control circuit 42 , a fourth control circuit 43 and a third voltage maintaining circuit 44 ;

[0177] The third write circuit 41 is electrically connected to the initial control terminal RST, the data line DT and the fifth node N5 respectively, and is used to control the connection between the data line DT and the fifth node N5 under the control of the initial control signal provided by the initial control terminal RST;

[0178] The third control circuit 42 is electrically connected to the fifth node N5, the light emitting control terminal EM, and the control node Ct, respectively, and is configured to control the connection between the control node Ct and the light emitting control terminal EM under the control of the potential of the fifth node N5;

[0179] The fourth control circuit 43 is electrically connected to the fifth node N5, the light-emission control voltage terminal HF, and the control node Ct, respectively, and is configured to control the connection between the control node Ct and the light-emission control voltage terminal HF under the control of the potential of the fifth node N5;

[0180] The third voltage maintaining circuit 44 is electrically connected to the fifth node N5 and is configured to maintain the potential of the fifth node N5.

[0181] The pixel circuit according to at least one embodiment of the present disclosure further includes a first initialization circuit and a second initialization circuit;

[0182] The first initialization circuit is electrically connected to the initial control terminal, the initial voltage terminal, and the first node, respectively, and is configured to write the initial voltage provided by the initial voltage terminal into the first node under the control of the initial control signal provided by the initial control terminal;

[0183] The second initialization circuit is electrically connected to the first initial control terminal, the reference voltage terminal and the second node respectively, and is used to write the reference voltage provided by the reference voltage terminal into the second node under the control of the initial control signal provided by the initial control terminal.

[0184] In a specific implementation, the pixel circuit may further include a first initialization circuit and a second initialization circuit; the first initialization circuit writes an initial voltage to the first node under the control of an initial control signal; the second initialization circuit writes a reference voltage to the second node under the control of an initial control signal.

[0185] As shown in FIG11 , based on at least one embodiment of the pixel circuit shown in FIG9 , the pixel circuit according to at least one embodiment of the present disclosure further includes a first initialization circuit 31 and a second initialization circuit 32 ;

[0186] The first initialization circuit 31 is electrically connected to the initial control terminal RST, the initial voltage terminal I1 and the first node N1 respectively, and is configured to write the initial voltage Vint provided by the initial voltage terminal I1 into the first node N1 under the control of the initial control signal provided by the initial control terminal RST;

[0187] The second initialization circuit 32 is electrically connected to the initial control terminal RST, the reference voltage terminal REF and the second node N2 respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal REF into the second node N2 under the control of the initial control signal provided by the initial control terminal RST.

[0188] As shown in FIG12 , based on at least one embodiment of the pixel circuit shown in FIG10 , the pixel circuit according to at least one embodiment of the present disclosure further includes a first initialization circuit 31 and a second initialization circuit 32 ;

[0189] The first initialization circuit 31 is electrically connected to the initial control terminal RST, the initial voltage terminal I1 and the first node N1 respectively, and is configured to write the initial voltage Vint provided by the initial voltage terminal I1 into the first node N1 under the control of the initial control signal provided by the initial control terminal RST;

[0190] The second initialization circuit 32 is electrically connected to the initial control terminal RST, the reference voltage terminal REF and the second node N2 respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal REF into the second node N2 under the control of the initial control signal provided by the initial control terminal RST.

[0191] The pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit and a compensation control circuit;

[0192] The data writing circuit is electrically connected to the write control terminal, the data line and the second node respectively, and is used to control the connection between the data line and the second node under the control of the write control signal provided by the write control terminal;

[0193] The compensation control circuit is electrically connected to the compensation control terminal, the first node and the driving node respectively, and is used to control the communication between the first node and the driving node under the control of the compensation control signal provided by the compensation control terminal.

[0194] In a specific implementation, the pixel circuit may further include a data writing circuit and a compensation control circuit. The data writing circuit controls the connection between the data line and the second node under the control of a write control signal; the compensation control circuit controls the connection between the first node and the driving node under the control of a compensation control signal.

[0195] As shown in FIG13 , based on at least one embodiment of the pixel circuit shown in FIG7 , the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit 61 and a compensation control circuit 62 ;

[0196] The data writing circuit 61 is electrically connected to the writing control terminal GT1, the data line DT and the second node N2 respectively, and is used to control the connection between the data line DT and the second node N2 under the control of the writing control signal provided by the writing control terminal GT;

[0197] The compensation control circuit 62 is electrically connected to the compensation control terminal GT2, the first node N1 and the driving node N0 respectively, and is used to control the connection between the first node N1 and the driving node N0 under the control of the compensation control signal provided by the compensation control terminal GT2.

[0198] As shown in FIG14 , based on at least one embodiment of the pixel circuit shown in FIG11 , the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit 61 and a compensation control circuit 62 ;

[0199] The data writing circuit 61 is electrically connected to the writing control terminal GT1, the data line DT and the second node N2 respectively, and is used to control the connection between the data line DT and the second node N2 under the control of the writing control signal provided by the writing control terminal GT;

[0200] The compensation control circuit 62 is electrically connected to the compensation control terminal GT2, the first node N1 and the driving node N0 respectively, and is used to control the connection between the first node N1 and the driving node N0 under the control of the compensation control signal provided by the compensation control terminal GT2.

[0201] As shown in FIG15 , based on at least one embodiment of the pixel circuit shown in FIG8 , the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit 61 and a compensation control circuit 62 ;

[0202] The data writing circuit 61 is electrically connected to the writing control terminal GT1, the data line DT and the second node N2 respectively, and is used to control the connection between the data line DT and the second node N2 under the control of the writing control signal provided by the writing control terminal GT;

[0203] The compensation control circuit 62 is electrically connected to the compensation control terminal GT2, the first node N1 and the driving node N0 respectively, and is used to control the connection between the first node N1 and the driving node N0 under the control of the compensation control signal provided by the compensation control terminal GT2.

[0204] As shown in FIG16 , based on at least one embodiment of the pixel circuit shown in FIG12 , the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit 61 and a compensation control circuit 62 ;

[0205] The data writing circuit 61 is electrically connected to the writing control terminal GT1, the data line DT and the second node N2 respectively, and is used to control the connection between the data line DT and the second node N2 under the control of the writing control signal provided by the writing control terminal GT;

[0206] The compensation control circuit 62 is electrically connected to the compensation control terminal GT2, the first node N1 and the driving node N0 respectively, and is used to control the connection between the first node N1 and the driving node N0 under the control of the compensation control signal provided by the compensation control terminal GT2.

[0207] Optionally, the first writing circuit includes a first transistor, the second writing circuit includes a second transistor, the first control circuit includes a third transistor, and the second control circuit includes a fourth transistor;

[0208] The gate of the first transistor is electrically connected to the first initial control terminal, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the third node;

[0209] The gate of the second transistor is electrically connected to the second initial control terminal, the first electrode of the second transistor is electrically connected to the data line, and the second electrode of the second transistor is electrically connected to the fourth node;

[0210] The gate of the third transistor is electrically connected to the third node, the first electrode of the third transistor is electrically connected to the light emitting control terminal, and the second electrode of the third transistor is electrically connected to the control node;

[0211] The gate of the fourth transistor is electrically connected to the fourth node, the first electrode of the fourth transistor is electrically connected to the light emitting control voltage terminal, and the second electrode of the fourth transistor is electrically connected to the control node.

[0212] Optionally, the first voltage maintaining circuit includes a first capacitor, and the second voltage maintaining circuit includes a second capacitor;

[0213] A first end of the first capacitor is electrically connected to the third node, and a second end of the first capacitor is electrically connected to a DC voltage terminal;

[0214] A first end of the second capacitor is electrically connected to the fourth node, and a second end of the second capacitor is electrically connected to a DC voltage end.

[0215] Optionally, the DC voltage terminal may be a ground terminal, a low voltage terminal or a common electrode voltage terminal, but is not limited thereto.

[0216] Optionally, the first initialization circuit includes a fifth transistor, and the second initialization circuit includes a sixth transistor;

[0217] The gate of the fifth transistor is electrically connected to the first initial control terminal, the first electrode of the fifth transistor is electrically connected to the initial voltage terminal, and the second electrode of the fifth transistor is electrically connected to the first node;

[0218] A gate of the sixth transistor is electrically connected to the first initial control terminal, a first electrode of the sixth transistor is electrically connected to the reference voltage terminal, and a second electrode of the sixth transistor is electrically connected to the second node.

[0219] Optionally, the third writing circuit includes a seventh transistor, the third control circuit includes an eighth transistor, and the fourth control circuit includes a ninth transistor;

[0220] The gate of the seventh transistor is electrically connected to the initial control terminal, the first electrode of the seventh transistor is electrically connected to the data line, and the second electrode of the seventh transistor is electrically connected to the fifth node;

[0221] The gate of the eighth transistor is electrically connected to the fifth node, the first electrode of the eighth transistor is electrically connected to the light emitting control terminal, and the second electrode of the eighth transistor is electrically connected to the control node;

[0222] The gate of the ninth transistor is electrically connected to the fifth node, the first electrode of the ninth transistor is electrically connected to the light emitting control voltage terminal, and the second electrode of the ninth transistor is electrically connected to the control node.

[0223] Optionally, the third voltage maintaining circuit includes a third capacitor;

[0224] A first end of the third capacitor is electrically connected to the fifth node, and a second end of the third capacitor is electrically connected to a DC voltage end.

[0225] Optionally, the first initialization circuit includes a fifth transistor, and the second initialization circuit includes a sixth transistor;

[0226] The gate of the fifth transistor is electrically connected to the initial control terminal, the first electrode of the fifth transistor is electrically connected to the initial voltage terminal, and the second electrode of the fifth transistor is electrically connected to the first node;

[0227] A gate of the sixth transistor is electrically connected to the initial control terminal, a first electrode of the sixth transistor is electrically connected to the reference voltage terminal, and a second electrode of the fifth transistor is electrically connected to the second node.

[0228] Optionally, the driving circuit includes a driving transistor, and the light emitting control circuit includes a tenth transistor;

[0229] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the power supply voltage terminal, and the second electrode of the driving transistor is electrically connected to the driving node;

[0230] The gate of the tenth transistor is electrically connected to the light emitting control terminal, the first electrode of the tenth transistor is electrically connected to the power supply voltage terminal, and the second electrode of the tenth transistor is electrically connected to the first electrode of the light emitting element.

[0231] Optionally, the driving circuit includes a driving transistor, and the light emitting control circuit includes a tenth transistor;

[0232] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the driving node, and the second electrode of the driving transistor is electrically connected to the first voltage terminal;

[0233] The gate of the tenth transistor is electrically connected to the light emitting control terminal, the first electrode of the tenth transistor is electrically connected to the second electrode of the light emitting element, and the second electrode of the tenth transistor is electrically connected to the driving node.

[0234] Optionally, the energy storage circuit includes a storage capacitor, and the voltage control circuit includes an eleventh transistor;

[0235] The first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to the second node;

[0236] The gate of the eleventh transistor is electrically connected to the light emitting control terminal, the first electrode of the eleventh transistor is electrically connected to the second voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the second node.

[0237] Optionally, the data writing circuit includes a twelfth transistor, and the compensation control circuit includes a thirteenth transistor;

[0238] The gate of the twelfth transistor is electrically connected to the write control terminal, the first electrode of the twelfth transistor is electrically connected to the data line, and the second electrode of the twelfth transistor is electrically connected to the second node;

[0239] A gate of the thirteenth transistor is electrically connected to the compensation control terminal, a first electrode of the thirteenth transistor is electrically connected to the first node, and a second electrode of the thirteenth transistor is electrically connected to the driving node.

[0240] As shown in FIG17 , based on at least one embodiment of the pixel circuit shown in FIG13 , the light emitting element is a micro light emitting diode M1;

[0241] The first writing circuit includes a first transistor T1, the second writing circuit includes a second transistor T2, the first control circuit includes a third transistor T3, and the second control circuit includes a fourth transistor T4;

[0242] The gate of the first transistor T1 is electrically connected to the first initial control terminal RSTA, the source of the first transistor T1 is electrically connected to the data line DT, and the drain of the first transistor T1 is electrically connected to the third node N3;

[0243] The gate of the second transistor T2 is electrically connected to the second initial control terminal RSTB, the source of the second transistor T2 is electrically connected to the data line DT, and the drain of the second transistor T2 is electrically connected to the fourth node N4;

[0244] The gate of the third transistor T3 is electrically connected to the third node N3, the source of the third transistor T3 is electrically connected to the light emitting control terminal EM, and the drain of the third transistor T3 is electrically connected to the control node Ct;

[0245] The gate of the fourth transistor T4 is electrically connected to the fourth node N4, the source of the fourth transistor T4 is electrically connected to the light emitting control voltage terminal HF, and the drain of the fourth transistor T4 is electrically connected to the control node Ct;

[0246] The first voltage maintaining circuit includes a first capacitor C1, and the second voltage maintaining circuit includes a second capacitor C2;

[0247] A first end of the first capacitor C1 is electrically connected to the third node N3, and a second end of the first capacitor C1 is electrically connected to the ground GND;

[0248] A first end of the second capacitor C2 is electrically connected to the fourth node N4, and a second end of the second capacitor C2 is electrically connected to the ground GND;

[0249] The first initialization circuit includes a fifth transistor T5, and the second initialization circuit includes a sixth transistor T6;

[0250] The gate of the fifth transistor T5 is electrically connected to the first initial control terminal RSTA, the source of the fifth transistor T5 is electrically connected to the initial voltage terminal I1, and the drain of the fifth transistor T5 is electrically connected to the first node N1;

[0251] The gate of the sixth transistor T6 is electrically connected to the first initial control terminal RSTA, the source of the sixth transistor T6 is electrically connected to the reference voltage terminal REF, and the drain of the sixth transistor T6 is electrically connected to the second node N2;

[0252] The driving circuit includes a driving transistor T0, the energy storage circuit includes a storage capacitor Cst, the light emitting control circuit includes a tenth transistor T10, and the voltage control circuit includes an eleventh transistor T11;

[0253] The gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the power supply voltage terminal VDD, and the drain of the driving transistor T0 is electrically connected to the driving node N0;

[0254] A first end of the storage capacitor Cst is electrically connected to the first node N1, and a second end of the storage capacitor Cst is electrically connected to the second node N2;

[0255] The gate of the tenth transistor T10 is electrically connected to the control node Ct, the source of the tenth transistor T10 is electrically connected to the driving node N0, and the drain of the tenth transistor T10 is electrically connected to the anode of the micro light emitting diode M1; the cathode of the micro light emitting diode M1 is electrically connected to the low voltage terminal VSS;

[0256] The gate of the eleventh transistor T11 is electrically connected to the light emitting control terminal EM, the source of the eleventh transistor T11 is electrically connected to the power supply voltage terminal VDD, and the drain of the eleventh transistor T11 is electrically connected to the second node N2;

[0257] The data writing circuit includes a twelfth transistor T12, and the compensation control circuit includes a thirteenth transistor T13; the writing control terminal and the compensation control terminal are both scanning terminals GT;

[0258] The gate of the twelfth transistor T12 is electrically connected to the scanning terminal GT, the source of the twelfth transistor T12 is electrically connected to the data line DT, and the drain of the twelfth transistor T12 is electrically connected to the second node N2;

[0259] A gate of the thirteenth transistor T13 is electrically connected to the scanning terminal GT, a source of the thirteenth transistor T13 is electrically connected to the first node N1, and a drain of the thirteenth transistor T13 is electrically connected to the driving node N0.

[0260] In at least one embodiment of the pixel circuit shown in FIG. 17 , all transistors are p-type transistors, but the present invention is not limited thereto.

[0261] In at least one embodiment of the pixel circuit shown in FIG17 , the second voltage terminal is a power supply voltage terminal VDD.

[0262] In at least one embodiment of the pixel circuit shown in Figure 17, the voltage value of Vref can be greater than or equal to -3V and less than or equal to the voltage value of the power supply voltage provided by VDD, and the voltage value of Vi1 can be greater than or equal to -3V and less than or equal to the power supply voltage value, and the power supply voltage value can be the voltage value of the power supply voltage provided by VDD; for example, the voltage value of Vref can be 0V, and the voltage value of Vi1 can be 0V, but it is not limited to this.

[0263] Optionally, the voltage value of the power supply voltage provided by VDD may be 14.6 V, and the voltage value of the low voltage signal provided by VSS may be 0 V. The voltage value of the power supply voltage may be greater than or equal to 12 V and less than or equal to 18 V, and the voltage value of the low voltage signal provided by VSS may be greater than or equal to -3 V and less than or equal to 1 V, but are not limited thereto.

[0264] When at least one embodiment of the pixel circuit shown in FIG. 17 of the present disclosure is in operation, in the reset stage S1, the selection stage S2, and the data writing and compensation stage S3, the VDD inputs the first power supply voltage VDD1, no current flows through the power supply voltage terminal VDD, and the voltage drop is substantially zero; in the light-emitting stage S4, the driving current required for each pixel circuit flows through the power supply voltage terminal VDD, generating an IR voltage drop, and providing a second power supply voltage VDD2 to the power supply voltage terminal of a circuit of a remote pixel, VDD2 = VDD-Vdrop, where Vdrop is the voltage drop.

[0265] As shown in FIG18 , when at least one embodiment of the pixel circuit shown in FIG17 of the present disclosure is in operation, a display cycle includes a reset phase S1 , a selection phase S2 , a data writing and compensation phase S3 , and a light emitting phase S4 , which are arranged in sequence;

[0266] In the reset phase S1, EM provides a high voltage signal, RSTA provides a low voltage signal, RSTB provides a high voltage signal, GT provides a high voltage signal, HF provides a high voltage signal, and DT provides a first data voltage Vdata_S1; T5 and T6 are turned on to reset the nodes at both ends of Cst. At this time, the potential of N2 is Vref, and the potential of N1 is Vint; at the same time, T1 is turned on, and Vdata_S1 is written to N3 through T1. When displaying medium and high grayscales, Vdata_S1 is a low voltage signal, so T3 is turned on, and the light-emitting control signal provided by EM is written to the gate of T10; when displaying low grayscales, Vdata_S1 is a high voltage signal, and T3 is turned off;

[0267] In the selection phase S2, EM provides a high voltage signal, RSTA provides a high voltage signal, RSTB provides a low voltage signal, GT provides a high voltage signal, HF provides a high voltage signal, and DT provides a second data voltage Vdata_S2; T4 is turned on, Vdata_S2 is written to N4 through T4, and when displaying medium and high grayscales, Vdata_S2 is a high voltage signal, so that T4 is closed; when displaying low grayscales, Vdata_S2 is a low voltage signal, T4 is turned on, and the light-emitting control voltage provided by HF is written to the gate of T10. The light-emitting control voltage provided by HF is a high-frequency pulse signal; when displaying medium and high grayscales, the light-emitting control signal provided by EM is written to the gate of T10, and M1 emits light for a long time; when displaying low grayscales, the light-emitting control voltage provided by HF is written to the gate of T10 to realize PWM (pulse width modulation) modulation. The light-emitting control voltage is a high-frequency PWM signal, which can improve the problem of poor low grayscale uniformity of micro-light-emitting diodes, and at the same time can reduce visual fatigue and improve viewing comfort; the potential of N1 and the potential of N2 maintain the potential at the previous moment;

[0268] In the data writing and compensation phase S3, GT provides a low voltage signal, T12 is turned on, and DT provides the display data voltage Vdata. Vdata charges N1 through T0 and T13, so that the potential of N1 becomes VDD1+Vth, where Vth is the threshold voltage of T0.

[0269] In the light-emitting phase S4, EM provides a low voltage signal, T11 turns on, and VDD2 is written to N2. Through the bootstrap pull-up effect of Cst, the potential of N1 becomes VDD1+Vth+VDD2-Vdata; the gate-source voltage of T0 is VDD1+Vth-Vdata, and the driving current Id flowing through M1 is equal to K(VDD1-Vdata). 2 , in order to eliminate the influence of IR voltage drop; where K is the current coefficient of T0;

[0270] When displaying medium and high grayscale, the gate of T10 is connected to the light-emitting control signal provided by EM, T10 is turned on, and M1 emits light;

[0271] When displaying low grayscale, the gate of T10 is connected to the light-emitting control voltage provided by HF; when HF provides a low voltage signal, T10 is turned on and M1 emits light, realizing PWM display.

[0272] When at least one embodiment of the pixel circuit shown in FIG. 17 of the present disclosure is in operation,

[0273] In the reset phase S1, the potential of N1 is Vint, and the potential of N2 is Vref;

[0274] In the selection stage S2, the potential of N1 is Vint and the potential of N2 is Vref;

[0275] In the data writing and compensation phase S3, the potential of N1 is Vdata, and the potential of N2 is VDD1+Vth; Vth is the threshold voltage of T0;

[0276] In the light emitting stage S4 , the potential of N1 is VDD2 , and the potential of N2 is VDD1 + Vth + VDD2 − Vdata.

[0277] As shown in FIG19 , based on at least one embodiment of the pixel circuit shown in FIG14 , the light emitting element is a micro light emitting diode M1;

[0278] The third writing circuit includes a seventh transistor T7, the third control circuit includes an eighth transistor T8, and the fourth control circuit includes a ninth transistor T9;

[0279] The gate of the seventh transistor T7 is electrically connected to the initial control terminal RST, the source of the seventh transistor T7 is electrically connected to the data line DT, and the drain of the seventh transistor T7 is electrically connected to the fifth node N5;

[0280] The gate of the eighth transistor T8 is electrically connected to the fifth node N5, the source of the eighth transistor T8 is electrically connected to the light emitting control terminal EM, and the drain of the eighth transistor T8 is electrically connected to the control node Ct;

[0281] The gate of the ninth transistor T9 is electrically connected to the fifth node N5, the source of the ninth transistor T9 is electrically connected to the light emitting control voltage terminal HF, and the drain of the ninth transistor T9 is electrically connected to the control node Ct;

[0282] The third voltage maintaining circuit includes a third capacitor C3;

[0283] A first end of the third capacitor C3 is electrically connected to the fifth node N5, and a second end of the third capacitor C3 is electrically connected to the common electrode voltage terminal VCOM;

[0284] The first initialization circuit includes a fifth transistor T5, and the second initialization circuit includes a sixth transistor T6;

[0285] The gate of the fifth transistor T5 is electrically connected to the initial control terminal RST, the source of the fifth transistor T5 is electrically connected to the initial voltage terminal I1, and the drain of the fifth transistor T5 is electrically connected to the first node N1; the initial voltage terminal I1 is used to provide an initial voltage Vint;

[0286] The gate of the sixth transistor T6 is electrically connected to the initial control terminal RST, the source of the sixth transistor T6 is electrically connected to the reference voltage terminal REF, and the drain of the sixth transistor T6 is electrically connected to the second node N2; the reference voltage terminal REF is used to provide a reference voltage Vref;

[0287] The driving circuit includes a driving transistor T0, the energy storage circuit includes a storage capacitor Cst, the light emitting control circuit includes a tenth transistor T10, and the voltage control circuit includes an eleventh transistor T11;

[0288] The gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the power supply voltage terminal VDD, and the drain of the driving transistor T0 is electrically connected to the driving node N0;

[0289] A first end of the storage capacitor Cst is electrically connected to the first node N1, and a second end of the storage capacitor Cst is electrically connected to the second node N2;

[0290] The gate of the tenth transistor T10 is electrically connected to the control node Ct, the source of the tenth transistor T10 is electrically connected to the driving node N0, and the drain of the tenth transistor T10 is electrically connected to the anode of the micro light emitting diode M1; the cathode of M1 is electrically connected to the low voltage terminal VSS;

[0291] The gate of the eleventh transistor T11 is electrically connected to the light emitting control terminal EM, the source of the eleventh transistor T11 is electrically connected to the power supply voltage terminal VDD, and the drain of the eleventh transistor T11 is electrically connected to the second node N2;

[0292] The data writing circuit includes a twelfth transistor T12, and the compensation control circuit includes a thirteenth transistor T13;

[0293] The gate of the twelfth transistor T12 is electrically connected to the write control terminal GT1, the source of the twelfth transistor T12 is electrically connected to the data line DT, and the drain of the twelfth transistor T12 is electrically connected to the second node N2;

[0294] A gate of the thirteenth transistor T13 is electrically connected to the compensation control terminal GT2 , a source of the thirteenth transistor T13 is electrically connected to the first node N1 , and a drain of the thirteenth transistor T13 is electrically connected to the driving node N0 .

[0295] In at least one embodiment of the pixel circuit shown in FIG. 19 of the present disclosure, T0 , T9 , T10 , T11 , and T12 are all p-type transistors, and T6 , T7 , T8 , T5 , and T13 are all n-type transistors.

[0296] In at least one embodiment of the pixel circuit shown in FIG. 19 , the second voltage terminal is a power supply voltage terminal VDD.

[0297] In at least one embodiment of the pixel circuit shown in Figure 19, the voltage value of Vref can be greater than or equal to -3V and less than or equal to the voltage value of the power supply voltage provided by VDD, and the voltage value of Vi1 can be greater than or equal to -3V and less than or equal to the power supply voltage value, and the power supply voltage value can be the voltage value of the power supply voltage provided by VDD; for example, the voltage value of Vref can be 0V, and the voltage value of Vi1 can be 0V, but is not limited to this.

[0298] Optionally, the voltage value of the power supply voltage provided by VDD may be 14.6 V, and the voltage value of the low voltage signal provided by VSS may be 0 V. The voltage value of the power supply voltage may be greater than or equal to 12 V and less than or equal to 18 V, and the voltage value of the low voltage signal provided by VSS may be greater than or equal to -3 V and less than or equal to 1 V, but are not limited thereto.

[0299] As shown in FIG20 , when at least one embodiment of the pixel circuit shown in FIG19 of the present disclosure is in operation, a display cycle may include a reset phase S1 , a data writing and compensation phase S3 , and a light emitting phase S4 , which are arranged in sequence;

[0300] In the reset phase S1, RST provides a high voltage signal, EM provides a high voltage signal, GT2 provides a low voltage signal, GT1 provides a high voltage signal, HF provides a high voltage signal, and DT provides a first data voltage Vdata_S1; T5 and T6 are turned on to reset the potentials of N1 and N2. At this time, the potential of N1 is Vint and the potential of N2 is Vref;

[0301] At the same time, T2 is turned on and Vdata_S1 is written to N5 through T2;

[0302] When displaying medium and high grayscale, Vdata_S1 is a high voltage signal, T1 is closed, T3 is opened, and the light control signal provided by EM is written to the gate of T10;

[0303] When displaying low grayscale, Vdata_S1 is a low voltage signal, T1 is turned on, T3 is turned off, and the light-emitting control terminal voltage provided by HF is written to the gate of T10;

[0304] In the data writing and compensation phase S3, GT1 provides a low voltage signal, GT2 provides a high voltage signal, EM provides a high voltage signal, RST provides a low voltage signal, HF provides a high voltage signal, DT provides the display data voltage Vdata, and VDD charges N1 through T0 and T13 until the potential of N1 reaches VDD1+Vth, where Vth is the threshold voltage of T0;

[0305] In the light-emitting stage S4, EM provides a low voltage signal, T11 is turned on, and VDD2 is written to N2. Through the bootstrap pull-up effect of Cst, the potential of N1 changes to VDD1+Vth+VDD2-Vdata; the gate-source voltage of T0 is VDD1+Vth-Vdata, and the driving current Id flowing through M1 is equal to K(VDD1-Vdata). 2 , in order to eliminate the influence of IR voltage drop; where K is the current coefficient of T0;

[0306] When displaying medium or high grayscale, the gate of T10 is connected to the light-emitting control signal provided by EM, T10 is turned on, and M1 emits light;

[0307] When displaying low grayscale, the gate of T10 is connected to the light-emitting control voltage provided by HF. When HF provides a low voltage signal, T10 is turned on to achieve PWM display.

[0308] When at least one embodiment of the pixel circuit shown in FIG. 19 of the present disclosure is in operation,

[0309] In the reset phase S1, the potential of N1 is Vint, and the potential of N2 is Vref;

[0310] In the data writing and compensation phase S3, the potential of N1 is Vdata, and the potential of N2 is VDD1+Vth; Vth is the threshold voltage of T0;

[0311] In the light emitting stage S4 , the potential of N1 is VDD2 , and the potential of N2 is VDD1 + Vth + VDD2 − Vdata.

[0312] In at least one embodiment of the pixel circuit shown in FIG. 19 of the present disclosure, during operation, in the light-emitting stage S4, the gate-source voltage Vgs at T0 is equal to VDD1+Vth+VDD2-Vdata-VDD2, Vgs is equal to VDD1+Vth-Vdata; and the driving current Id flowing through M1 is equal to K×(VDD1-Vdata). 2 , so as to eliminate the influence of IR drop.

[0313] The difference between at least one embodiment of the pixel circuit shown in FIG. 21 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 19 of the present disclosure is that: T6 and T7 are p-type transistors;

[0314] The gate of T6 and the gate of T7 are both electrically connected to the reset control voltage terminal RST1.

[0315] FIG22 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG21 of the present disclosure, wherein the reset control voltage signal provided by RST1 is inversely proportional to the reset control signal provided by RST in FIG11 .

[0316] In at least one embodiment of the pixel circuit shown in FIG19 of the present disclosure, T1 may be an n-type transistor, and T3 may be a p-type transistor;

[0317] The transistor type of T1 is opposite to that of T3 to realize the inverter voltage writing function. When T1 is an n-type transistor and T3 is a p-type transistor, Vdata is a low voltage signal when displaying medium and high grayscales; when displaying low grayscales, Vdata is a high voltage signal.

[0318] In at least one embodiment of the pixel circuit shown in FIG. 19 of the present disclosure, T12 may also be replaced by a p-type transistor.

[0319] As shown in FIG23, based on at least one embodiment of the pixel circuit shown in FIG15,

[0320] The light emitting element is a micro light emitting diode M1;

[0321] The first writing circuit includes a first transistor T1, the second writing circuit includes a second transistor T2, the first control circuit includes a third transistor T3, and the second control circuit includes a fourth transistor T4;

[0322] The gate of the first transistor T1 is electrically connected to the first initial control terminal RSTA, the source of the first transistor T1 is electrically connected to the data line DT, and the drain of the first transistor T1 is electrically connected to the third node N3;

[0323] The gate of the second transistor T2 is electrically connected to the second initial control terminal RSTB, the source of the second transistor T2 is electrically connected to the data line DT, and the drain of the second transistor T2 is electrically connected to the fourth node N4;

[0324] The gate of the third transistor T3 is electrically connected to the third node N3, the source of the third transistor T3 is electrically connected to the light emitting control terminal EM, and the drain of the third transistor T3 is electrically connected to the control node Ct;

[0325] The gate of the fourth transistor T4 is electrically connected to the fourth node N4, the source of the fourth transistor T4 is electrically connected to the light emitting control voltage terminal HF, and the drain of the fourth transistor T4 is electrically connected to the control node Ct;

[0326] The first voltage maintaining circuit includes a first capacitor C1, and the second voltage maintaining circuit includes a second capacitor C2;

[0327] A first end of the first capacitor C1 is electrically connected to the third node N3, and a second end of the first capacitor C1 is electrically connected to the ground GND;

[0328] A first end of the second capacitor C2 is electrically connected to the fourth node N4, and a second end of the second capacitor C2 is electrically connected to the ground GND;

[0329] The first initialization circuit includes a fifth transistor T5, and the second initialization circuit includes a sixth transistor T6;

[0330] The gate of the fifth transistor T5 is electrically connected to the first initial control terminal RSTA, the source of the fifth transistor T5 is electrically connected to the initial voltage terminal I1, and the drain of the fifth transistor T5 is electrically connected to the first node N1;

[0331] The gate of the sixth transistor T6 is electrically connected to the first initial control terminal RSTA, the source of the sixth transistor T6 is electrically connected to the reference voltage terminal REF, and the drain of the sixth transistor T6 is electrically connected to the second node N2;

[0332] The driving circuit includes a driving transistor T0, the energy storage circuit includes a storage capacitor Cst, the light emitting control circuit includes a tenth transistor T10, and the voltage control circuit includes an eleventh transistor T11;

[0333] The gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the driving node N0, and the drain of the driving transistor T0 is electrically connected to the low voltage terminal VSS;

[0334] A first end of the storage capacitor Cst is electrically connected to the first node N1, and a second end of the storage capacitor Cst is electrically connected to the second node N2;

[0335] The anode of the micro light emitting diode M1 is electrically connected to the power supply voltage terminal VDD;

[0336] The gate of the tenth transistor T10 is electrically connected to the control node Ct, the source of the tenth transistor T10 is electrically connected to the cathode of the micro light emitting diode M1, and the drain of the tenth transistor T10 is electrically connected to the driving node N0; the cathode of the micro light emitting diode M1 is electrically connected to the low voltage terminal VSS;

[0337] The gate of the eleventh transistor T11 is electrically connected to the light emitting control terminal EM, the source of the eleventh transistor T11 is electrically connected to the low voltage terminal VSS, and the drain of the eleventh transistor T11 is electrically connected to the second node N2;

[0338] The data writing circuit includes a twelfth transistor T12, and the compensation control circuit includes a thirteenth transistor T13; the writing control terminal and the compensation control terminal are both scanning terminals GT;

[0339] The gate of the twelfth transistor T12 is electrically connected to the scanning terminal GT, the source of the twelfth transistor T12 is electrically connected to the data line DT, and the drain of the twelfth transistor T12 is electrically connected to the second node N2;

[0340] A gate of the thirteenth transistor T13 is electrically connected to the scanning terminal GT, a source of the thirteenth transistor T13 is electrically connected to the first node N1, and a drain of the thirteenth transistor T13 is electrically connected to the driving node N0.

[0341] In at least one embodiment of the pixel circuit shown in FIG. 23 , all transistors are n-type transistors, but the present invention is not limited thereto.

[0342] In at least one embodiment of the pixel circuit shown in FIG. 23 , T0 needs to be an n-type transistor, and other transistors can be replaced by p-type transistors.

[0343] In at least one embodiment of the pixel circuit shown in FIG. 23 ,

[0344] In at least one embodiment of the pixel circuit shown in FIG. 23 , the second voltage terminal is a low voltage terminal VSS.

[0345] When at least one embodiment of the pixel circuit shown in FIG. 23 of the present disclosure is in operation, in the reset stage S1, the selection stage S2, and the data writing and compensation stage S3, the low voltage terminal VSS provides a first low voltage VSS1, no current flows through the low voltage terminal VSS, and the voltage drop is substantially zero; in the light-emitting stage S4, the driving current required for each pixel circuit flows through the low voltage terminal VSS, generating an IR voltage drop, and providing a second low voltage VSS2 to the low voltage terminal of a circuit of a remote pixel, VSS2 = VDD - Vdrop, where Vdrop is the voltage drop.

[0346] In at least one embodiment of the pixel circuit shown in Figure 23, the voltage value of Vref can be greater than or equal to -3V and less than or equal to the voltage value of the power supply voltage provided by VDD, the voltage value of Vi1 can be the same as the voltage value of the power supply voltage provided by VDD, or, the voltage value of Vi1 is less than the voltage value of the power supply voltage provided by VDD, and the absolute value of the difference between the voltage value of Vi1 and the voltage value of the power supply voltage provided by VDD is less than or equal to 3V.

[0347] Optionally, the voltage value of the power supply voltage provided by VDD may be 14.6 V, and the voltage value of the low voltage signal provided by VSS may be 0 V. The voltage value of the power supply voltage may be greater than or equal to 12 V and less than or equal to 18 V, and the voltage value of the low voltage signal provided by VSS may be greater than or equal to -3 V and less than or equal to 1 V, but are not limited thereto.

[0348] As shown in FIG24 , when at least one embodiment of the pixel circuit shown in FIG23 of the present disclosure is in operation, a display cycle includes a reset phase S1 , a selection phase S2 , a data writing and compensation phase S3 , and a light emitting phase S4 , which are arranged in sequence;

[0349] In the reset phase S1, EM provides a low voltage signal, RSTA provides a high voltage signal, RSTB provides a low voltage signal, GT provides a low voltage signal, HF provides a low voltage signal, and DT provides a first data voltage Vdata_S1; T5 and T6 are turned on to reset the nodes at both ends of Cst. At this time, the potential of N2 is Vref, and the potential of N1 is Vint; at the same time, T1 is turned on, and Vdata_S1 is written to N3 through T1. When displaying medium and high grayscales, Vdata_S1 is a high voltage signal, so T3 is turned on, and the light-emitting control signal provided by EM is written to the gate of T10; when displaying low grayscales, Vdata_S1 is a low voltage signal, and T3 is turned off;

[0350] In the selection phase S2, EM provides a low voltage signal, RSTA provides a low voltage signal, RSTB provides a high voltage signal, GT provides a low voltage signal, HF provides a low voltage signal, and DT provides a second data voltage Vdata_S2; T4 is turned on, Vdata_S2 is written to N4 through T4, and when displaying medium and high grayscales, Vdata_S2 is a low voltage signal, so that T4 is turned off; when displaying low grayscales, Vdata_S2 is a high voltage signal, T4 is turned on, and the light-emitting control voltage provided by HF is written to the gate of T10. The light-emitting control voltage provided by HF is a high-frequency pulse signal; when displaying medium and high grayscales, the light-emitting control signal provided by EM is written to the gate of T10, and M1 emits light for a long time; when displaying low grayscales, the light-emitting control voltage provided by HF is written to the gate of T10 to realize PWM (pulse width modulation) modulation. The light-emitting control voltage is a high-frequency PWM signal, which can improve the problem of poor low grayscale uniformity of micro-light-emitting diodes, and at the same time can reduce visual fatigue and improve viewing comfort; the potential of N1 and the potential of N2 maintain the potential at the previous moment;

[0351] In the data writing and compensation phase S3, GT provides a high voltage signal, T12 is turned on, and DT provides the display data voltage Vdata. Vdata charges N1 through T0 and T13, so that the potential of N1 becomes VSS1+Vth, where Vth is the threshold voltage of T0.

[0352] In the light-emitting stage S4, EM provides a high voltage signal, T11 turns on, and VDD2 is written to N2. Through the bootstrap pull-up effect of Cst, the potential of N1 becomes VSS1+Vth+VSS2-Vdata; the gate-source voltage of T0 is VSS1+Vth-Vdata, and the driving current Id flowing through M1 is equal to K(VSS1-Vdata). 2 , in order to eliminate the influence of IR voltage drop; where K is the current coefficient of T0;

[0353] When displaying medium and high grayscale, the gate of T10 is connected to the light-emitting control signal provided by EM, T10 is turned on, and M1 emits light;

[0354] When displaying low grayscale, the gate of T10 is connected to the light-emitting control voltage provided by HF; when HF provides a low voltage signal, T10 is turned on and M1 emits light, realizing PWM display.

[0355] At least one embodiment of the pixel circuit shown in FIG. 23 of the present disclosure is in operation.

[0356] In the reset phase S1, the potential of N1 is Vint, and the potential of N2 is Vref;

[0357] In the selection stage S2, the potential of N1 is Vint and the potential of N2 is Vref;

[0358] In the data writing and compensation phase S3, the potential of N1 is Vdata, and the potential of N2 is VSS1+Vth; Vth is the threshold voltage of T0;

[0359] In the light emitting stage S4 , the potential of N1 is VDD2 , and the potential of N2 is VSS1 + Vth + VSS2 − Vdata.

[0360] As shown in FIG25 , based on at least one embodiment of the pixel circuit shown in FIG16 , the light emitting element is a micro light emitting diode M1;

[0361] The third writing circuit includes a seventh transistor T7, the third control circuit includes an eighth transistor T8, and the fourth control circuit includes a ninth transistor T9;

[0362] The gate of the seventh transistor T7 is electrically connected to the initial control terminal RST, the source of the seventh transistor T7 is electrically connected to the data line DT, and the drain of the seventh transistor T7 is electrically connected to the fifth node N5;

[0363] The gate of the eighth transistor T8 is electrically connected to the fifth node N5, the source of the eighth transistor T8 is electrically connected to the light emitting control terminal EM, and the drain of the eighth transistor T8 is electrically connected to the control node Ct;

[0364] The gate of the ninth transistor T9 is electrically connected to the fifth node N5, the source of the ninth transistor T9 is electrically connected to the light emitting control voltage terminal HF, and the drain of the ninth transistor T9 is electrically connected to the control node Ct;

[0365] The third voltage maintaining circuit includes a third capacitor C3;

[0366] A first end of the third capacitor C3 is electrically connected to the fifth node N5, and a second end of the third capacitor C3 is electrically connected to the common electrode voltage terminal VCOM;

[0367] The first initialization circuit includes a fifth transistor T5, and the second initialization circuit includes a sixth transistor T6;

[0368] The gate of the fifth transistor T5 is electrically connected to the initial control terminal RST, the source of the fifth transistor T5 is electrically connected to the initial voltage terminal I1, and the drain of the fifth transistor T5 is electrically connected to the first node N1; the initial voltage terminal I1 is used to provide an initial voltage Vint;

[0369] The gate of the sixth transistor T6 is electrically connected to the initial control terminal RST, the source of the sixth transistor T6 is electrically connected to the reference voltage terminal REF, and the drain of the sixth transistor T6 is electrically connected to the second node N2; the reference voltage terminal REF is used to provide a reference voltage Vref;

[0370] The driving circuit includes a driving transistor T0, the energy storage circuit includes a storage capacitor Cst, the light emitting control circuit includes a tenth transistor T10, and the voltage control circuit includes an eleventh transistor T11;

[0371] The gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the driving node N0, and the drain of the driving transistor T0 is electrically connected to the low voltage terminal VSS;

[0372] A first end of the storage capacitor Cst is electrically connected to the first node N1, and a second end of the storage capacitor Cst is electrically connected to the second node N2;

[0373] The anode of the micro light emitting diode M1 is electrically connected to the power supply voltage terminal VDD;

[0374] The gate of the tenth transistor T10 is electrically connected to the control node Ct, the source of the tenth transistor T10 is electrically connected to the cathode of the micro light emitting diode M1, and the drain of the tenth transistor T10 is electrically connected to the driving node N0;

[0375] The gate of the eleventh transistor T11 is electrically connected to the light emitting control terminal EM, the source of the eleventh transistor T11 is electrically connected to the low voltage terminal VSS, and the drain of the eleventh transistor T11 is electrically connected to the second node N2;

[0376] The data writing circuit includes a twelfth transistor T12, and the compensation control circuit includes a thirteenth transistor T13;

[0377] The gate of the twelfth transistor T12 is electrically connected to the write control terminal GT1, the source of the twelfth transistor T12 is electrically connected to the data line DT, and the drain of the twelfth transistor T12 is electrically connected to the second node N2;

[0378] A gate of the thirteenth transistor T13 is electrically connected to the compensation control terminal GT2 , a source of the thirteenth transistor T13 is electrically connected to the first node N1 , and a drain of the thirteenth transistor T13 is electrically connected to the driving node N0 .

[0379] In at least one embodiment of the pixel circuit shown in FIG. 25 , the second voltage terminal is a low voltage terminal VSS.

[0380] In at least one embodiment of the pixel circuit shown in FIG. 25 of the present disclosure, T0 , T5 , T6 , T7 , T8 , and T13 are n-type transistors, and T9 , T10 , T11 , and T12 are p-type transistors.

[0381] The difference between at least one embodiment of the pixel circuit shown in FIG. 26 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 17 of the present disclosure is that the source of T11 is electrically connected to the reference voltage terminal REF, which is used to provide a reference voltage Vref.

[0382] FIG. 18 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 26 of the present disclosure.

[0383] In at least one embodiment of the pixel circuit shown in FIG. 26 of the present disclosure, during operation, in the light-emitting phase, the gate-source voltage at T0 is Vref+Vth-Vdata, and the driving current Id flowing through M1 is equal to K(Vref-Vdata). 2 , so as to eliminate the influence of IR voltage drop; where K is the current coefficient of T0.

[0384] In at least one embodiment of the pixel circuit shown in FIG. 26 , the second voltage terminal is a reference voltage terminal REF.

[0385] The difference between at least one embodiment of the pixel circuit shown in FIG. 27 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 19 of the present disclosure is that the source of T11 is electrically connected to the reference voltage terminal REF, which is used to provide a reference voltage Vref.

[0386] FIG. 20 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 27 of the present disclosure.

[0387] In at least one embodiment of the pixel circuit shown in FIG. 27 of the present disclosure, during operation, in the light-emitting phase, the gate-source voltage at T0 is Vref+Vth-Vdata, and the driving current Id flowing through M1 is equal to K(Vref-Vdata). 2 , so as to eliminate the influence of IR voltage drop; where K is the current coefficient of T0.

[0388] In at least one embodiment of the pixel circuit shown in FIG. 27 , the second voltage terminal is a reference voltage terminal REF.

[0389] The display device described in the embodiment of the present disclosure includes the above-mentioned pixel circuit.

[0390] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A pixel circuit comprising a light-emitting element, a driving circuit, a light-emitting control circuit and a driving control circuit; The light emitting control circuit is electrically connected to a control node, and is used to control the connection between the driving circuit and the light emitting element, or to control the connection between the driving circuit and a power supply voltage terminal, under the control of the potential of the control node; The driving circuit is electrically connected to the first node, and under the control of the potential of the first node, the driving circuit generates a driving current flowing from the power supply voltage terminal to the light emitting element; The driving control circuit is electrically connected to the control node, the data line, the initial control terminal, the light-emitting control terminal and the light-emitting control voltage terminal, respectively, and is used to control the connection between the control node and the light-emitting control terminal or the light-emitting control voltage terminal according to the voltage signal provided by the data line under the control of the initial control signal provided by the initial control terminal.

2. The pixel circuit according to claim 1, wherein: The control end of the driving circuit is electrically connected to the first node, the first end of the driving circuit is electrically connected to the power supply voltage end, the second end of the driving circuit is electrically connected to the driving node, and the driving circuit is used to generate a driving current flowing from the power supply voltage end to the driving node under the control of the potential of the first node; The light-emitting control circuit is also electrically connected to the driving node and the first pole of the light-emitting element respectively, and is used to control the connection between the driving node and the first pole of the light-emitting element under the control of the potential of the control node; the second pole of the light-emitting element is electrically connected to the first voltage terminal.

3. The pixel circuit according to claim 1, wherein: The control end of the driving circuit is electrically connected to the first node, the first end of the driving circuit is electrically connected to the driving node, the second end of the driving circuit is electrically connected to the first voltage end, and the driving circuit is used to generate a driving current flowing from the driving node to the first voltage end under the control of the potential of the first node; The first electrode of the light emitting element is electrically connected to the power supply voltage terminal; The light emitting control circuit is also electrically connected to the second electrode of the light emitting element and the driving node respectively, and is used to control the connection between the second electrode of the light emitting element and the driving node under the control of the potential of the control node.

4. The pixel circuit according to any one of claims 1 to 3, wherein: Also includes a storage circuit and a voltage control circuit; The first end of the energy storage circuit is electrically connected to the first node, the second end of the energy storage circuit is electrically connected to the second node, and the energy storage circuit is used to store electrical energy; The voltage control circuit is electrically connected to the light-emitting control terminal, the second voltage terminal and the second node respectively, and is used to control the connection between the second voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control terminal.

5. The pixel circuit according to claim 4, wherein: The initial control end includes a first initial control end and a second initial control end; The drive control circuit includes a first write circuit, a second write circuit, a first control circuit, a second control circuit, a first voltage maintaining circuit and a second voltage maintaining circuit; The first writing circuit is electrically connected to the third node, the data line and the first initial control terminal respectively, and is used to control the connection between the data line and the third node under the control of the first initial control signal provided by the first initial control terminal; The second writing circuit is electrically connected to the fourth node, the data line and the second initial control terminal respectively, and is used to control the connection between the data line and the fourth node under the control of the second initial control signal provided by the second initial control terminal; The first control circuit is electrically connected to the third node, the light emitting control terminal and the control node respectively, and is used to control the connection between the light emitting control terminal and the control node under the control of the potential of the third node; The second control circuit is electrically connected to the fourth node, the light-emitting control voltage terminal and the control node respectively, and is used to control the connection between the light-emitting control voltage terminal and the control node under the control of the potential of the fourth node; The first voltage maintaining circuit is electrically connected to the third node and is used to maintain the potential of the third node; The second voltage maintaining circuit is electrically connected to the fourth node, and is used to maintain the potential of the fourth node.

6. The pixel circuit according to claim 5, wherein: Also includes a first initialization circuit and a second initialization circuit; The first initialization circuit is electrically connected to the first initial control terminal, the initial voltage terminal and the first node respectively, and is used to write the initial voltage provided by the initial voltage terminal into the first node under the control of the first initial control signal provided by the first initial control terminal; The second initialization circuit is electrically connected to the first initial control terminal, the reference voltage terminal and the second node respectively, and is used to write the reference voltage provided by the reference voltage terminal into the second node under the control of a first initial control signal provided by the first initial control terminal.

7. The pixel circuit according to claim 4, wherein: The driving control circuit includes a third writing circuit, a third control circuit, a fourth control circuit and a third voltage maintaining circuit; The third writing circuit is electrically connected to the fifth node, the data line and the initial control terminal respectively, and is used to control the data line to be connected to the fifth node under the control of the initial control signal provided by the initial control terminal; The third control circuit is electrically connected to the fifth node, the light emitting control terminal and the control node respectively, and is used to control the connection between the control node and the light emitting control terminal under the control of the potential of the fifth node; The fourth control circuit is electrically connected to the fifth node, the light-emitting control voltage terminal and the control node respectively, and is used to control the connection between the control node and the light-emitting control voltage terminal under the control of the potential of the fifth node; The third voltage maintaining circuit is electrically connected to the fifth node, and is used to maintain the potential of the fifth node.

8. The pixel circuit according to claim 7, wherein: Also includes a first initialization circuit and a second initialization circuit; The first initialization circuit is electrically connected to the initial control terminal, the initial voltage terminal and the first node respectively, and is used to write the initial voltage provided by the initial voltage terminal into the first node under the control of the initial control signal provided by the initial control terminal; The second initialization circuit is electrically connected to the initial control terminal, the reference voltage terminal and the second node respectively, and is used to write the reference voltage provided by the reference voltage terminal into the second node under the control of the initial control signal provided by the initial control terminal.

9. The pixel circuit according to claim 4, wherein: Also includes a data writing circuit and a compensation control circuit; The data writing circuit is electrically connected to the writing control terminal, the data line and the second node respectively, and is used to control the connection between the data line and the second node under the control of the writing control signal provided by the writing control terminal; The compensation control circuit is electrically connected to the compensation control terminal, the first node and the driving node respectively, and is used to control the connection between the first node and the driving node under the control of the compensation control signal provided by the compensation control terminal.

10. The pixel circuit according to claim 5, wherein: The first write circuit includes a first transistor, the second write circuit includes a second transistor, the first control circuit includes a third transistor, and the second control circuit includes a fourth transistor; The gate of the first transistor is electrically connected to the first initial control terminal, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the third node; The gate of the second transistor is electrically connected to the second initial control terminal, the first electrode of the second transistor is electrically connected to the data line, and the second electrode of the second transistor is electrically connected to the fourth node; The gate of the third transistor is electrically connected to the third node, the first electrode of the third transistor is electrically connected to the light emitting control terminal, and the second electrode of the third transistor is electrically connected to the control node; The gate of the fourth transistor is electrically connected to the fourth node, the first electrode of the fourth transistor is electrically connected to the light emitting control voltage terminal, and the second electrode of the fourth transistor is electrically connected to the control node.

11. The pixel circuit according to claim 5, wherein: The first voltage maintaining circuit includes a first capacitor, and the second voltage maintaining circuit includes a second capacitor; The first end of the first capacitor is electrically connected to the third node, and the second end of the first capacitor is electrically connected to the DC voltage end; The first end of the second capacitor is electrically connected to the fourth node, and the second end of the second capacitor is electrically connected to the DC voltage end.

12. The pixel circuit according to claim 6, wherein: The first initialization circuit includes a fifth transistor, and the second initialization circuit includes a sixth transistor; The gate of the fifth transistor is electrically connected to the first initial control terminal, the first electrode of the fifth transistor is electrically connected to the initial voltage terminal, and the second electrode of the fifth transistor is electrically connected to the first node; A gate of the sixth transistor is electrically connected to the first initial control terminal, a first electrode of the sixth transistor is electrically connected to the reference voltage terminal, and a second electrode of the sixth transistor is electrically connected to the second node.

13. The pixel circuit according to claim 7, wherein: The third writing circuit includes a seventh transistor, the third control circuit includes an eighth transistor, and the fourth control circuit includes a ninth transistor; The gate of the seventh transistor is electrically connected to the initial control terminal, the first electrode of the seventh transistor is electrically connected to the data line, and the second electrode of the seventh transistor is electrically connected to the fifth node; The gate of the eighth transistor is electrically connected to the fifth node, the first electrode of the eighth transistor is electrically connected to the light emitting control terminal, and the second electrode of the eighth transistor is electrically connected to the control node; The gate of the ninth transistor is electrically connected to the fifth node, and the first electrode of the ninth transistor is electrically connected to the light emitting The control voltage terminal is electrically connected, and the second electrode of the ninth transistor is electrically connected to the control node.

14. The pixel circuit according to claim 7, wherein: The third voltage maintaining circuit includes a third capacitor; A first end of the third capacitor is electrically connected to the fifth node, and a second end of the third capacitor is electrically connected to a DC voltage end.

15. The pixel circuit according to claim 8, wherein: The first initialization circuit includes a fifth transistor, and the second initialization circuit includes a sixth transistor; The gate of the fifth transistor is electrically connected to the initial control terminal, the first electrode of the fifth transistor is electrically connected to the initial voltage terminal, and the second electrode of the fifth transistor is electrically connected to the first node; A gate of the sixth transistor is electrically connected to the initial control terminal, a first electrode of the sixth transistor is electrically connected to the reference voltage terminal, and a second electrode of the fifth transistor is electrically connected to the second node.

16. The pixel circuit according to claim 2, wherein: The driving circuit includes a driving transistor, and the light emitting control circuit includes a tenth transistor; The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the power supply voltage terminal, and the second electrode of the driving transistor is electrically connected to the driving node; The gate of the tenth transistor is electrically connected to the light emitting control terminal, the first electrode of the tenth transistor is electrically connected to the power supply voltage terminal, and the second electrode of the tenth transistor is electrically connected to the first electrode of the light emitting element.

17. The pixel circuit according to claim 3, wherein: The driving circuit includes a driving transistor, and the light emitting control circuit includes a tenth transistor; The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the driving node, and the second electrode of the driving transistor is electrically connected to the first voltage terminal; The gate of the tenth transistor is electrically connected to the light emitting control terminal, the first electrode of the tenth transistor is electrically connected to the second electrode of the light emitting element, and the second electrode of the tenth transistor is electrically connected to the driving node.

18. The pixel circuit according to claim 4, wherein: The energy storage circuit includes a storage capacitor, and the voltage control circuit includes an eleventh transistor; The first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to the second node; A gate of the eleventh transistor is electrically connected to the light emitting control terminal, a first electrode of the eleventh transistor is electrically connected to the second voltage terminal, and a second electrode of the eleventh transistor is electrically connected to the second node.

19. The pixel circuit according to claim 9, wherein: The data writing circuit includes a twelfth transistor, and the compensation control circuit includes a thirteenth transistor; The gate of the twelfth transistor is electrically connected to the write control terminal, the first electrode of the twelfth transistor is electrically connected to the data line, and the second electrode of the twelfth transistor is electrically connected to the second node; A gate of the thirteenth transistor is electrically connected to the compensation control terminal, a first electrode of the thirteenth transistor is electrically connected to the first node, and a second electrode of the thirteenth transistor is electrically connected to the driving node.

20. A display device comprising the pixel circuit according to any one of claims 1 to 19.

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