Display substrate and manufacturing method therefor, and display device

Abstract

A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises a plurality of circuit units; the circuit units each comprise a pixel driving circuit and at least one connecting strip; the pixel driving circuit at least comprises a third transistor; the third transistor at least comprises a third active layer; the third active layer at least comprises a third source region, a third drain region, and a third channel region located between the third source region and the third drain region; the third source region is in the shape of a strip extending in the direction of a unit row, and has at least one active edge extending in the direction of the unit row; the connecting strip is in the shape of a strip extending in the direction of the unit row, and has at least one connecting strip edge extending in the direction of the unit row; and the distance between the at least one active edge and the at least one connecting strip edge is greater than or equal to 0.5 μm.

Description

Display substrate and manufacturing method thereof, and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on October 27, 2023, with application number 202311416209.1 and invention name “Display substrate, preparation method thereof, and display device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to but is not limited to the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] In one aspect, the present disclosure provides a display substrate comprising a plurality of circuit units forming a plurality of cell rows and a plurality of cell columns, at least one circuit unit comprising a pixel driving circuit and at least one connecting strip, the pixel driving circuit comprising at least a second transistor serving as a compensation transistor, a third transistor serving as a driving transistor, and a fourth transistor serving as a data writing transistor; the second transistor comprising at least a second active layer, the third transistor comprising at least a third active layer, and the fourth transistor comprising at least a fourth active layer, the third active layer comprising at least a third source region, a third drain region, and a third channel region located between the third source region and the third drain region, the third source region being connected to the fourth active layer, and the third drain region being connected to the second active layer; the third source region being in the shape of a strip extending along the cell row direction, the third source region having at least one active edge extending along the cell row direction; the connecting strip being in the shape of a strip extending along the cell row direction, the connecting strip having at least one connecting strip edge extending along the cell row direction; the distance between the at least one active edge and the at least one connecting strip edge being greater than or equal to 0.5 μm, where the distance represents the dimension in the cell column direction.

[0007] In an exemplary embodiment, in at least one circuit unit, the pixel driving circuit further includes a blocking electrode, and the orthographic projection of the third channel region on the display substrate plane is located within the range of the orthographic projection of the blocking electrode on the display substrate plane; the at least one connecting strip includes a first blocking connecting strip, which is arranged between the blocking electrodes of two adjacent circuit units in the unit row direction and is respectively connected to the two blocking electrodes.

[0008] In an exemplary embodiment, in at least one circuit unit, an orthographic projection of the third source region on the display substrate plane is located within a range of an orthographic projection of the first blocking connecting bar on the display substrate plane.

[0009] In an exemplary embodiment, in at least one circuit unit, the at least one active edge includes a first active edge and a second active edge respectively located on both sides of the third active region unit column direction, and the at least one connecting strip edge includes a first blocking edge and a second blocking edge respectively located on both sides of the first blocking connecting strip unit column direction; the distance between the first blocking edge and the first active edge is greater than or equal to 0.5 μm, and the distance between the second blocking edge and the second active edge is greater than or equal to 0.5 μm.

[0010] In an exemplary embodiment, in at least one circuit unit, an orthographic projection of the third source region on the display substrate plane does not overlap with an orthographic projection of the first blocking connecting bar on the display substrate plane.

[0011] In an exemplary embodiment, in at least one circuit unit, the at least one active edge includes at least a source region edge of the third source region close to the first blocking connecting strip, and the at least one connecting strip edge includes at least a blocking edge of the first blocking connecting strip close to the third source region; and the distance between the blocking edge and the source region edge is greater than or equal to 0.5 μm.

[0012] In an exemplary embodiment, in at least one circuit unit, the pixel driving circuit further includes a storage capacitor, the storage capacitor including at least a first plate and a second plate, the orthographic projection of the second plate on the display substrate plane at least partially overlaps with the orthographic projection of the first plate on the display substrate plane, and the orthographic projection of the third channel region on the display substrate plane is located within the range of the orthographic projection of the first plate on the display substrate plane; the at least one connecting strip includes a first plate connecting strip, the first plate connecting strip is arranged between the second plates of two adjacent circuit units in the unit row direction, and is respectively connected to the two second plates.

[0013] In an exemplary embodiment, in at least one circuit unit, an orthographic projection of the third source region on the display substrate plane is located within a range of an orthographic projection of the first electrode connecting bar on the display substrate plane.

[0014] In an exemplary embodiment, in at least one circuit unit, the at least one active edge includes a first active edge and a second active edge, respectively located on both sides of the third active region unit column direction, and the at least one connecting strip edge includes a first electrode plate edge and a second electrode plate edge, respectively located on both sides of the first electrode plate connecting strip unit column direction; the distance between the first electrode plate edge and the first active edge is greater than or equal to 0.5 μm, and the distance between the second electrode plate edge and the second active edge is greater than or equal to 0.5 μm.

[0015] In an exemplary embodiment, in at least one circuit unit, an orthographic projection of the third source region on the display substrate plane does not overlap with an orthographic projection of the first electrode connecting bar on the display substrate plane.

[0016] In an exemplary embodiment, in at least one circuit unit, the at least one active edge includes at least a source region edge of the third source region close to the first board-level connecting strip, and the at least one connecting strip edge includes at least a plate edge of the first plate connecting strip close to the third source region; and a distance between the plate edge and the source region edge is greater than or equal to 0.5 μm.

[0017] In an exemplary embodiment, in at least one circuit unit, the gate electrode of the fourth transistor is connected to a first scanning signal line, the first scanning signal line is in the shape of a straight line or a broken line extending along the unit row direction, and the orthographic projection of the second active layer on the plane of the display substrate at least partially overlaps with the orthographic projection of the first scanning signal line on the plane of the display substrate.

[0018] In an exemplary embodiment, in at least one circuit unit, the second active layer includes at least a second source region, a second drain region, a first active segment, and a second active segment, the second source region is connected to the gate electrode of the third transistor, and the second drain region is connected to the third drain region of the third active layer; a first end of the first active segment is connected to the second source region, a second end of the first active segment extends along a cell row direction and is connected to the first end of the second active segment, and a second end of the second active segment extends along a cell column direction and is connected to the second drain region; an orthographic projection of the first active segment on the display substrate plane at least partially overlaps with an orthographic projection of the first scan signal line on the display substrate plane.

[0019] In an exemplary embodiment, the first scan signal line includes a first scan edge and a second scan edge, respectively located on both sides of the first scan signal line unit in a column direction; in at least one circuit unit, in an overlapping area between the first active segment and the first scan signal line, the orthographic projections of the first scan edge and the second scan edge on the display substrate plane are located within a range of the orthographic projection of the first active segment on the display substrate plane.

[0020] In an exemplary embodiment, the first active segment includes a third active edge and a fourth active edge respectively located on both sides of the first active segment unit in a column direction; in at least one circuit unit, in an overlapping region of the first active segment and the first scanning signal line, a distance between the third active edge and the first scanning edge is greater than or equal to 0.5 μm, and a distance between the fourth active edge and the second scanning edge is greater than or equal to 0.5 μm.

[0021] In an exemplary embodiment, the pixel driving circuit further includes a first transistor serving as a first initialization transistor, a fifth transistor serving as a first light-emitting control transistor, a sixth transistor serving as a second light-emitting control transistor, a seventh transistor serving as a second initialization transistor, an eighth transistor serving as a third initialization transistor, at least one connecting electrode, and at least one pad, wherein the at least one connecting electrode is connected to the active layer of the at least one transistor through an active via, and the orthographic projection of the at least one active via on the plane of the display substrate is within the range of the orthographic projection of the at least one pad on the plane of the display substrate.

[0022] In an exemplary embodiment, a distance between an edge of the active via and an edge of the spacer is greater than or equal to 0.5 μm.

[0023] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes at least a blocking layer, a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, and a fourth conductive layer arranged in sequence on a base, the at least one spacer is arranged in the blocking layer, and the at least one connecting electrode is arranged in the fourth conductive layer.

[0024] In an exemplary embodiment, in at least one circuit unit, the shielding layer further includes a shielding electrode, and a distance between an edge of at least one active via hole and an edge of the shielding electrode is greater than or equal to 0.5 μm.

[0025] In an exemplary embodiment, in at least one circuit unit, the shielding layer further includes a second shielding connection strip, which is in the shape of a strip extending along the unit column direction and is respectively connected to the shielding electrode and at least one pad, and the distance between the edge of at least one active via and the second shielding connection strip is greater than or equal to 0.5 μm.

[0026] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0027] In another aspect, the present disclosure further provides a method for preparing a display substrate, wherein the display substrate includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, the method comprising:

[0028] A pixel driving circuit and at least one connecting strip are formed in at least one circuit unit. The pixel driving circuit includes at least a second transistor serving as a compensation transistor, a third transistor serving as a driving transistor, and a fourth transistor serving as a data writing transistor. The second transistor includes at least a second active layer, the third transistor includes at least a third active layer, and the fourth transistor includes at least a fourth active layer. The third active layer includes at least a third source region, a third drain region, and a third channel region located between the third source region and the third drain region. The third source region is connected to the fourth active layer, and the third drain region is connected to the second active layer. The third source region is shaped like a strip extending along a cell row direction, and the third source region has at least one active edge extending along the cell row direction. The connecting strip is shaped like a strip extending along the cell row direction, and has at least one connecting strip edge extending along the cell row direction. The distance between the at least one active edge and the at least one connecting strip edge is greater than or equal to 0.5 μm, where the distance is a dimension in the cell column direction.

[0029] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0031] FIG1 is a schematic structural diagram of a display device;

[0032] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0033] FIG3 is a schematic diagram of a cross-sectional structure of a display substrate;

[0034] FIG4 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0035] FIG5 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0036] FIG6 is a schematic diagram of a third active layer according to an exemplary embodiment of the present disclosure;

[0037] FIG7 is a schematic diagram of the positional relationship between a first shielding connecting strip and a third source electrode according to the present invention;

[0038] FIG8 is a schematic diagram of the positional relationship between a first electrode connecting bar and a third source electrode according to the present disclosure;

[0039] FIG9 is a schematic diagram of an embodiment of the present disclosure after forming a shielding layer pattern;

[0040] 10A and 10B are schematic diagrams of an embodiment of the present disclosure after forming a first semiconductor layer pattern;

[0041] FIG10C is an enlarged view of area A in FIG10A ;

[0042] 11A and 11B are schematic diagrams of an embodiment of the present disclosure after forming a first conductive layer pattern;

[0043] 12A and 12B are schematic diagrams of an embodiment of the present disclosure after forming a second conductive layer pattern;

[0044] FIG12C is an enlarged view of area A in FIG12A ;

[0045] 13A and 13B are schematic diagrams of an embodiment of the present disclosure after forming a second semiconductor layer pattern;

[0046] FIG13C is an enlarged view of area B in FIG13A ;

[0047] 14A and 14B are schematic diagrams of an embodiment of the present disclosure after forming a third conductive layer pattern;

[0048] FIG15A is a schematic diagram of an embodiment of the present disclosure after forming a sixth insulating layer pattern;

[0049] FIG15B is an enlarged view of area C in FIG15A ;

[0050] FIG15C is an enlarged view of area D in FIG15A ;

[0051] FIG15D is an enlarged view of area E in FIG15A ;

[0052] 16A and 16B are schematic diagrams of an embodiment of the present disclosure after forming a fourth conductive layer pattern;

[0053] FIG17 is a schematic diagram of another positional relationship between the first shielding connecting strip and the third source electrode according to the present invention;

[0054] FIG18 is a schematic diagram of another positional relationship between the first electrode connecting strip and the third source electrode according to the present disclosure.

[0055] Explanation of Reference Numerals: 11—first active layer; 12—second active layer; 13—third active layer; 14—fourth active layer; 15—fifth active layer; 16—sixth active layer; 17—seventh active layer; 18—eighth active layer; 21—first scanning signal line; 22—second scanning signal line; 23—third scanning signal line; 24—fourth scanning signal line; 25—light-emitting signal line; 31—first electrode plate; 32—second electrode plate; 33—shielding line; 34—opening; 35—first board-level connecting bar; 36—second board-level connecting bar; 41—first initial signal line; 42—second initial signal line; 43—third initial signal line; 51—first connecting electrode; 52—second connecting electrode; 53—third connecting electrode; 54—fourth connecting electrode; 55—fifth connecting electrode; 56—sixth connecting electrode; 57—seventh connecting electrode; 58—eighth connecting electrode; 59—ninth connecting electrode; 60—shielding electrode; 61—first shielding connecting strip; 62—second shielding connecting strip; 63—third shielding connecting strip; 71—first pad; 72—second pad; 101—substrate; 102—driving circuit layer; 103—light-emitting structure layer; 104—encapsulation structure layer. DETAILED DESCRIPTION

[0056] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0057] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0058] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0059] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0060] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0061] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0062] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0063] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0064] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0065] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0066] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0067] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0068] FIG1 is a schematic diagram of the structure of a display device. As shown in FIG1 , the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is respectively connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a per-pixel basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured as a shift register and may generate emission signals by sequentially transmitting emission stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal. o may be a natural number. In an exemplary embodiment, the pixel array may be provided on a display substrate.

[0069] Figure 2 is a schematic diagram of a planar structure of a display substrate. As shown in Figure 2, the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a third sub-pixel P3 emitting a second color light, a second sub-pixel P2 emitting a third color light, and a fourth sub-pixel P4 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting unit is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0070] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 and the fourth subpixel P4 may be green subpixels (G) that emit green light, and the third subpixel P3 may be a blue subpixel (B) that emits blue light. In an exemplary embodiment, the subpixels may be rectangular, diamond, pentagonal, or hexagonal, and the four subpixels may be arranged in an RGBG pixel arrangement. In other exemplary embodiments, the four subpixels may be arranged horizontally, vertically, or in a square, etc., which is not limited in this disclosure.

[0071] In an exemplary embodiment, a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a triangular arrangement, which is not limited in the present disclosure.

[0072] Figure 3 is a schematic cross-sectional view of a display substrate, illustrating the structure of four sub-pixels. As shown in Figure 3, in a plane perpendicular to the display substrate, the display substrate may include a drive circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the drive circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in this disclosure.

[0073] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include at least an anode, an organic light-emitting layer and a cathode, the anode being connected to the pixel driving circuit, the organic light-emitting layer being connected to the anode, and the cathode being connected to the organic light-emitting layer, and the organic light-emitting layer emitting light of corresponding colors under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material laminated structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0074] Figure 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in Figure 4, the pixel driving circuit may include eight transistors (first transistor T1 to eighth transistor T8), one storage capacitor C, and one holding capacitor Cb. The pixel driving circuit is connected to ten signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, light emitting signal line EM, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, data signal line DATA, and first power line VDD).

[0075] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is respectively connected to the first electrode of the second transistor T2, the gate electrode of the third transistor T3, the first end of the storage capacitor C, and the first end of the holding capacitor Cb; the second node N2 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8; the third node N3 is respectively connected to the second electrode of the first transistor T1, the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6; and the fourth node N4 is respectively connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.

[0076] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1, a second end of the storage capacitor C is connected to the first power line VDD, a first end of the holding capacitor Cb is connected to the first node N1, and a second end of the holding capacitor Cb is connected to the first scan signal line S1.

[0077] In an exemplary embodiment, the first transistor T1 may be referred to as a first initialization transistor, a gate electrode of the first transistor T1 is connected to the third scan signal line S3 , a first electrode of the first transistor T1 is connected to the first initial signal line INIT1 , and a second electrode of the first transistor T1 is connected to the third node N3 .

[0078] In an exemplary embodiment, the second transistor T2 may be referred to as a compensation transistor, a gate electrode of the second transistor T2 is connected to the fourth scan signal line S4 , a first electrode of the second transistor T2 is connected to the first node N1 , and a second electrode of the second transistor T2 is connected to the third node N3 .

[0079] In an exemplary embodiment, the third transistor T3 may be referred to as a driving transistor, a gate electrode of the third transistor T3 is connected to the first node N1 , a first electrode of the third transistor T3 is connected to the second node N2 , and a second electrode of the third transistor T3 is connected to the third node N3 .

[0080] In an exemplary embodiment, the fourth transistor T4 may be referred to as a data writing transistor, a gate electrode of the fourth transistor T4 is connected to the first scan signal line S1 , a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the second node N2 .

[0081] In an exemplary embodiment, the fifth transistor T5 may be referred to as a first light emission control transistor, a gate electrode of the fifth transistor T5 is connected to the light emission signal line EM, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2.

[0082] In an exemplary embodiment, the sixth transistor T6 may be referred to as a second light emission control transistor, a gate electrode of the sixth transistor T6 is connected to the light emission signal line EM, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0083] In an exemplary embodiment, the seventh transistor T7 may be referred to as a second initialization transistor, a gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0084] In an exemplary embodiment, the eighth transistor T8 may be referred to as a third initialization transistor, a gate electrode of the eighth transistor T8 is connected to the second scan signal line S2, a first electrode of the eighth transistor T8 is connected to the third initial signal line INIT3, and a second electrode of the eighth transistor T8 is connected to the second node N2.

[0085] In an exemplary embodiment, the second scan signal line S2 and the third scan signal line S3 may be connected to different signal lines or to the same signal source, that is, the signals of the second scan signal line S2 and the third scan signal line S3 may be the same or different.

[0086] In an exemplary embodiment, a first electrode of the light-emitting device EL is connected to the fourth node N4, and a second electrode of the light-emitting device EL is connected to the second power supply line VSS. The light-emitting device EL may be an OLED including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0087] In an exemplary embodiment, the signal of the first power line VDD is a continuously provided high level signal, and the signal of the second power line VSS is a continuously provided low level signal.

[0088] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 may be a P-type transistor or an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the eighth transistor T8 may include P-type transistors and N-type transistors.

[0089] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 may be low-temperature polysilicon transistors, or oxide transistors, or both. The active layer of the low-temperature polysilicon transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating low-temperature polysilicon transistors and oxide transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can leverage the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0090] The exemplary embodiments of the present disclosure provide a display substrate. In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate may include a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate. On a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one of the circuit units may include a pixel driving circuit, and the pixel driving circuit is configured to output a corresponding current to the connected light-emitting device. The light-emitting structure layer may include a plurality of light-emitting units, at least one of the light-emitting units may include a light-emitting device, the light-emitting device being connected to the pixel driving circuit of the corresponding circuit unit, and the light-emitting device being configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit.

[0091] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In exemplary embodiments, the position and shape of the orthographic projection of the light-emitting unit on the substrate may correspond to the position and shape of the orthographic projection of the circuit unit on the substrate, or the position and shape of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position and shape of the orthographic projection of the circuit unit on the substrate.

[0092] In an exemplary embodiment, the exemplary embodiment of the present disclosure displays a substrate including a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit including a pixel driving circuit and at least one connecting strip, the pixel driving circuit including at least a second transistor as a compensation transistor, a third transistor as a driving transistor, and a fourth transistor as a data writing transistor, the gate electrode of the third transistor being connected to the first electrode of the second transistor, the first electrode of the third transistor being connected to the second electrode of the fourth transistor, the second electrode of the third transistor being connected to the second electrode of the second transistor, and the first electrode of the fourth transistor being connected to the data signal line; the second transistor including at least a second active layer, the fourth transistor to The present invention comprises at least a fourth active layer, the third transistor comprises at least a third active layer, the third active layer comprises at least a third source region, a third drain region and a third channel region located between the third source region and the third drain region, the third source region is connected to the fourth active layer, and the third drain region is connected to the second active layer; the shape of the third source region is a strip shape extending along the unit row direction, and the third source region has at least one active edge extending along the unit row direction; the shape of the connecting bar is a strip shape extending along the unit row direction, and the connecting bar has at least one connecting bar edge extending along the unit row direction; the distance between at least one active edge and at least one connecting bar edge is greater than or equal to 0.5 μm, and the distance is the dimension in the unit column direction.

[0093] In an exemplary embodiment, in at least one circuit unit, the pixel driving circuit further includes a blocking electrode, and the orthographic projection of the third channel region on the display substrate plane is located within the range of the orthographic projection of the blocking electrode on the display substrate plane; the at least one connecting strip includes a first blocking connecting strip, which is arranged between the blocking electrodes of two adjacent circuit units in the unit row direction and is respectively connected to the two blocking electrodes.

[0094] In an exemplary embodiment, in at least one circuit unit, the pixel driving circuit further includes a storage capacitor, the storage capacitor including at least a first plate and a second plate, the orthographic projection of the second plate on the display substrate plane at least partially overlaps with the orthographic projection of the first plate on the display substrate plane, and the orthographic projection of the third channel region on the display substrate plane is located within the range of the orthographic projection of the first plate on the display substrate plane; the at least one connecting strip includes a first plate connecting strip, the first plate connecting strip is arranged between the second plates of two adjacent circuit units in the unit row direction, and is respectively connected to the two second plates.

[0095] In an exemplary embodiment, in at least one circuit unit, the gate electrode of the fourth transistor is connected to a first scanning signal line, the first scanning signal line is in the shape of a straight line or a broken line extending along the unit row direction, and the orthographic projection of the second active layer on the plane of the display substrate at least partially overlaps with the orthographic projection of the first scanning signal line on the plane of the display substrate.

[0096] Figure 5 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of eight circuit units (two unit rows and four unit columns). In this exemplary embodiment, the multiple circuit units can form multiple unit rows and multiple unit columns, with the multiple circuit units in each unit row arranged sequentially along a first direction X, and the multiple unit rows arranged sequentially along a second direction Y, forming an array of circuit units arranged in an array, with the first direction X intersecting the second direction Y.

[0097] In an exemplary embodiment, at least one circuit unit may include at least a pixel driving circuit. The pixel driving circuit may include at least a storage capacitor and a plurality of transistors. The storage capacitor may include a first plate and a second plate, wherein the orthographic projection of the second plate on the display substrate plane at least partially overlaps with the orthographic projection of the first plate on the display substrate plane. The plurality of transistors may include a first transistor T1 as a first initialization transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a drive transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first emission control transistor, a sixth transistor T6 as a second emission control transistor, a seventh transistor T7 as a second initialization transistor, and an eighth transistor T8 as a third initialization transistor.

[0098] In the exemplary embodiment, the gate electrode of the first transistor T1 is connected to the third scan signal line 23, and the first electrode of the first transistor T1 is connected to the first initial signal line 41. The gate electrode of the second transistor T2 is connected to the fourth scan signal line 24, the first electrode of the second transistor T2 is connected to the gate electrode of the third transistor T3, and the second electrode of the second transistor T2 is connected to the second electrode of the first transistor T1, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively. The first electrode of the third transistor T3 is connected to the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8. The gate electrode of the fourth transistor T4 is connected to the first scan signal line 21, and the first electrode of the fourth transistor T4 is connected to the data signal line. The gate electrode of the fifth transistor T5 is connected to the light emission signal line 25, the first electrode of the fifth transistor T5 is connected to the first power supply line, the gate electrode of the sixth transistor T6 is connected to the light emission signal line 25, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7. The gate electrode of the seventh transistor T7 is connected to the second scan signal line 22, and the first electrode of the seventh transistor T7 is connected to the second initial signal line 42. A gate electrode of the eighth transistor T8 is connected to the second scanning signal line 22 , and a first electrode of the eighth transistor T8 is connected to the third initial signal line 43 .

[0099] In an exemplary embodiment, the second transistor T2 may be an oxide transistor, and the first transistor T1 and the third transistor T3 to the eighth transistor T8 may be low-temperature polysilicon transistors.

[0100] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the fourth scan signal line 24, the light-emitting signal line 25, the first initial signal line 41, the second initial signal line 42, and the third initial signal line 43 may be in the shape of a straight line or a broken line, with the main portion extending along the first direction X. In the present disclosure, "A extends along the B direction" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, a line segment, or a strip-shaped body, the main portion extending along the B direction, and the length of the main portion extending along the B direction being greater than the length of the secondary portion extending along other directions. In the following description, "A extends along the B direction" means "the main portion of A extends along the B direction."

[0101] In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate may include at least: a blocking layer arranged on the substrate, a first insulating layer arranged on a side of the blocking layer away from the substrate, a first semiconductor layer arranged on a side of the first insulating layer away from the substrate, a second insulating layer arranged on a side of the first semiconductor layer away from the substrate, a first conductive layer arranged on a side of the second insulating layer away from the substrate, a third insulating layer arranged on a side of the first conductive layer away from the substrate, a second conductive layer arranged on a side of the third insulating layer away from the substrate, a fourth insulating layer arranged on a side of the second conductive layer away from the substrate, a second semiconductor layer arranged on a side of the fourth insulating layer away from the substrate, a fifth insulating layer arranged on a side of the second semiconductor layer away from the substrate, the third conductive layer arranged on a side of the fifth insulating layer away from the substrate, a sixth insulating layer arranged on a side of the third conductive layer away from the substrate, and a fourth conductive layer arranged on a side of the sixth insulating layer away from the substrate.

[0102] In an exemplary embodiment, the blocking layer may include at least a blocking electrode, the first semiconductor layer may include at least a first active layer of the first transistor T1, a third active layer 13 of the third transistor T3 to an eighth active layer of the eighth transistor T8, the first conductive layer may include at least a first scan signal line, a second scan signal line, a third scan signal line, a light-emitting signal line, and a first plate of a storage capacitor, the second conductive layer may include at least a second plate of the storage capacitor, the second semiconductor layer may include at least a second active layer of the second transistor T2, the third conductive layer may include at least a first initial signal line, a second initial signal line, a third initial signal line, and a fourth scan signal line, and the fourth conductive layer may include at least a plurality of connecting electrodes.

[0103] Figure 6 is a schematic diagram of a third active layer according to an exemplary embodiment of the present disclosure. As shown in Figure 6, the second transistor T2 may include at least a second active layer 12, the third transistor T3 may include at least a third active layer 13, and the fourth transistor T4 may include at least a fourth active layer 14. The third active layer 13 and the fourth active layer 14 may be disposed in the first semiconductor layer, and the second active layer 12 may be disposed in the second semiconductor layer.

[0104] In an exemplary embodiment, the third active layer 13 may include at least a third source region 13-1, a third drain region 13-2, and a third channel region 13-3 arranged between the third source region 13-1 and the third drain region 13-2, and the orthographic projection of the third channel region 13-3 on the plane of the display substrate is located within the range of the orthographic projection of the first electrode 31 (i.e., the gate electrode of the third transistor T3) on the plane of the display substrate.

[0105] In an exemplary embodiment, the third source region 13-1 may be in the shape of a strip extending along the first direction X (the cell row direction), with a first end of the third source region 13-1 connected to the third channel region 13-3, and a second end of the third source region 13-1 extending in a direction away from the third channel region 13-3 before being connected to the second region of the fourth active layer 14. In an exemplary embodiment, the fourth active layer 14 may be in the shape of a strip extending along the second direction Y (the cell column direction), with a first region of the fourth active layer 14 configured to be connected to a data signal line.

[0106] In an exemplary embodiment, the third drain region 13-2 may be in the shape of a strip extending along the first direction X (the cell row direction). A first end of the third drain region 13-2 is connected to the third channel region 13-3. A second end of the third drain region 13-2 extends away from the third channel region 13-3 and is then connected to the second region of the second active layer 12 via the second connection electrode 52. In an exemplary embodiment, the first region of the second active layer 12 is configured to be connected to the first electrode 31 via the first connection electrode 51.

[0107] In an exemplary embodiment, during the data writing phase of the pixel driver circuit's operating sequence, after the data signal line writes the data signal into the first region of the fourth active layer 14, the data signal then passes through the second region of the fourth active layer 14, the third source region 13-1, the third channel region 13-3, the third drain region 13-2, the second connection electrode 52, the second region of the second active layer 12, the first region of the second active layer 12, and the first connection electrode 51 before being written into the first electrode plate 31. Before reaching the third channel region 13-3, the data signal first propagates along the second direction Y in the fourth active layer 14 and then propagates along the first direction X in the third source region 13-1. This means that the data signal makes a turn during its transmission from the fourth active layer 14 to the third active layer 13. This region where the data signal makes a turn can be referred to as a semiconductor node. Research has found that the capacitance at a semiconductor node can affect the transmission of the data signal, and thus the current of the light-emitting device. When the capacitance at the semiconductor node varies between different circuit units, it can lead to display defects such as uniformity and horizontal streaks.

[0108] Figure 7 is a schematic diagram of the positional relationship between a first shielding connecting bar and a third source electrode according to the present disclosure. As shown in Figure 7, at least one circuit unit may further include a first shielding connecting bar 61. The first shielding connecting bar 61 may be disposed between shielding electrodes 60 of two adjacent circuit units in the first direction X (unit row direction) and connected to the two shielding electrodes 60, respectively. The first shielding connecting bar 61 may serve as a connecting bar according to the present disclosure.

[0109] In an exemplary embodiment, the shape of the first blocking connecting strip 61 can be a straight line or a broken line extending along the first direction X, and in at least one circuit unit, the positive projection of the third source region 13-1 of the third active layer on the substrate does not overlap with the positive projection of the first blocking connecting strip 61 on the substrate.

[0110] In an exemplary embodiment, in at least one circuit unit, the shape of the third source region 13-1 can be a strip shape extending along the first direction X, and can have at least a source region edge 19-0 close to one side of the first blocking connecting strip 61, and the source region edge 19-0 can serve as the active edge of the present disclosure.

[0111] In an exemplary embodiment, in at least one circuit unit, the first shielding connecting strip 61 may be in the shape of a strip extending along the first direction X, and may have at least a shielding edge 61-0 close to one side of the third source region 13-1, and the shielding edge 61-0 may serve as the connecting strip edge of the present disclosure.

[0112] In an exemplary embodiment, in at least one circuit unit, a separation distance L0 may be provided between the source region edge 19 - 0 and the shielding edge 61 - 0 . The separation distance L0 may be greater than or equal to 0.5 μm.

[0113] In an exemplary embodiment, the separation distance L0 is a dimension in the second direction Y. The separation distance L0 may be an average distance between the source region edge 19 - 0 and the board-level edge 61 - 0 , or may be a minimum distance between the source region edge 19 - 0 and the board-level edge 61 - 0 , or may be a maximum distance between the source region edge 19 - 0 and the board-level edge 61 - 0 .

[0114] The present invention discloses that the third source region and the first shielding connection strip do not overlap, and the distance between the edge of the third source region and the edge of the first shielding connection strip is greater than or equal to 0.5 μm. Even if the position of the shielding layer and the first semiconductor layer changes due to fluctuations in the manufacturing process, the consistency of the capacitance at the semiconductor node position in each circuit unit can be effectively guaranteed, thereby avoiding display uniformity and horizontal stripes caused by capacitance differences, and improving display effect and display quality.

[0115] Figure 8 is a schematic diagram of the positional relationship between a first electrode connecting bar and a third source electrode according to the present disclosure. As shown in Figure 8, at least one circuit unit may further include a first electrode connecting bar 35. The first electrode connecting bar 35 may be disposed between the second electrode plates 32 of two adjacent circuit units in the first direction X (unit row direction) and connected to each of the two second electrode plates 32. The first electrode connecting bar 35 may serve as another connecting bar according to the present disclosure.

[0116] In an exemplary embodiment, the shape of the first board-level connecting bar 35 can be a straight line or a broken line extending along the first direction X, and in at least one circuit unit, the positive projection of the third source region 13-1 of the third active layer on the substrate can be located within the range of the positive projection of the first board-level connecting bar 35 on the substrate.

[0117] In an exemplary embodiment, in at least one circuit unit, the shape of the third source region 13-1 may be a strip shape extending along the first direction X, and may have at least a first active edge 19-1 and a second active edge 19-2. The shapes of the first active edge 19-1 and the second active edge 19-2 may be straight lines or broken lines extending along the first direction X. The first active edge 19-1 may be located on one side of the third source region 13-1 in the opposite direction of the second direction Y, and the second active edge 19-2 may be located on one side of the third source region 13-1 in the second direction Y. The first active edge 19-1 and the second active edge 19-2 may serve as active edges of the present disclosure.

[0118] In an exemplary embodiment, in at least one circuit unit, the shape of the first board-level connecting strip 35 can be a strip extending along the first direction X, and can have at least a first board-level edge 35-1 and a second board-level edge 35-2. The shapes of the first board-level edge 35-1 and the second board-level edge 35-2 can be straight lines or broken lines extending along the first direction X. The first board-level edge 35-1 can be located on the side of the first board-level connecting strip 35 in the opposite direction of the second direction Y, and the second board-level edge 35-2 can be located on the side of the first board-level connecting strip 35 in the second direction Y. The first board-level edge 35-1 and the second board-level edge 35-2 can serve as the connecting strip edges of the present disclosure.

[0119] In an exemplary embodiment, in at least one circuit unit, a first distance L1 is provided between the first active edge 19 - 1 and the first board-level edge 35 - 1 . The first distance L1 may be greater than or equal to 0.5 μm.

[0120] In an exemplary embodiment, the first distance L1 is a dimension in the second direction Y. The first distance L1 may be an average distance between the first active edge 19 - 1 and the first board-level edge 35 - 1, or may be a minimum distance between the first active edge 19 - 1 and the first board-level edge 35 - 1, or may be a maximum distance between the first active edge 19 - 1 and the first board-level edge 35 - 1.

[0121] In an exemplary embodiment, in at least one circuit unit, a second distance L2 is provided between the second active edge 19 - 2 and the second board-level edge 35 - 2 . The second distance L2 may be greater than or equal to 0.5 μm.

[0122] In an exemplary embodiment, the second distance L2 is a dimension in the second direction Y. The second distance L2 may be an average distance between the second active edge 19 - 2 and the second board-level edge 35 - 2 , or may be a minimum distance between the second active edge 19 - 2 and the second board-level edge 35 - 2 , or may be a maximum distance between the second active edge 19 - 2 and the second board-level edge 35 - 2 .

[0123] The present disclosure provides a first board-level connecting strip to completely cover the third source region, and the distance between the edge of the third source region and the edge of the first board-level connecting strip is greater than or equal to 0.5 μm. Even if the position of the first semiconductor layer and the second conductive layer changes due to fluctuations in the manufacturing process, the consistency of the capacitance at the semiconductor node position in each circuit unit can be effectively guaranteed, thereby avoiding display uniformity and horizontal stripes caused by capacitance differences, and improving display effects and display quality.

[0124] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes the deposition of film layers, coating of photoresist on the film layers, mask exposure, development, etching, stripping of photoresist and other processes for metal materials, inorganic materials or transparent conductive materials, and includes the coating of organic materials, mask exposure and development and other processes for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0125] In an exemplary embodiment, taking eight circuit units (Mth unit row and M+1th unit row, Nth unit column, N+1th unit column, N+2th unit column and N+3th unit column) as an example, the preparation process of the display substrate may include the following operations.

[0126] (1) Forming a blocking layer pattern. In an exemplary embodiment, forming the blocking layer pattern may include: depositing a blocking film on a substrate, patterning the blocking film through a patterning process, and forming a blocking layer pattern on the substrate, as shown in FIG9 . In an exemplary embodiment, the blocking layer may be referred to as a bottom metal (LS) layer.

[0127] In an exemplary embodiment, the shielding layer pattern of each circuit unit may include at least a shielding electrode 60 , a first shielding connection bar 61 , a second shielding connection bar 62 , a third shielding connection bar 63 and a first spacer 71 .

[0128] In an exemplary embodiment, the shielding electrode 60 may be rectangular in shape, with chamfers or grooves provided at the corners of the rectangle, and may be disposed in a central region of the circuit unit in the first direction X and the second direction Y.

[0129] In an exemplary embodiment, the first spacer 71 may be block-shaped (eg, rectangular) and may be disposed on one side of the shielding electrode 60 in the second direction Y. The first spacer 71 may serve as the spacer of the present disclosure.

[0130] In an exemplary embodiment, the shape of the first shielding connection strip 61 can be a straight line or a broken line extending along the first direction X. The first shielding connection strip 61 can be arranged on one side of the shielding electrode 60 in the first direction X or on the side opposite to the first direction X of the shielding electrode 60. The first end of the first shielding connection strip 61 is connected to the shielding electrode 60 of the current circuit unit, and the second end of the first shielding connection strip 61 is connected to the shielding electrode 60 of the adjacent circuit unit in the first direction X, so that the first shielding connection strip 61 and the shielding electrode 60 in a unit row are connected into one, forming an interconnected integrated structure.

[0131] In an exemplary embodiment, the shape of the second shielding connection strip 62 can be a straight line or a broken line extending along the second direction Y. The second shielding connection strip 62 can be arranged on one side of the shielding electrode 60 in the second direction Y. The first end of the second shielding connection strip 62 is connected to the shielding electrode 60, and the second end of the second shielding connection strip 62 is connected to the first pad 71.

[0132] In an exemplary embodiment, the shape of the third shielding connection bar 63 can be a straight line or a broken line extending along the second direction Y. The third shielding connection bar 63 can be arranged on the side opposite to the second direction Y of the shielding electrode 60. The first end of the third shielding connection bar 63 is connected to the shielding electrode 60, and the second end of the third shielding connection bar 63 is connected to the first pad 71 in the previous unit row.

[0133] In an exemplary embodiment, in at least one unit column, the shielding electrode 60 , the second shielding connection bar 62 , the third shielding connection bar 63 and the first spacer 71 are connected as a whole to form an interconnected integral structure.

[0134] In an exemplary embodiment, the shielding layers in the unit rows and unit columns are connected as one, which can ensure that the shielding layers in the display substrate have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0135] In an exemplary embodiment, the shielding layers of adjacent cell columns may be mirror-symmetrical with respect to a column boundary, which may be a straight line located between adjacent cell columns and extending along the second direction Y. For example, the shielding layer of the Nth column and the shielding layer of the N+1th column may be mirror-symmetrical with respect to the column boundary, the shielding layer of the N+1th column and the shielding layer of the N+2th column may be mirror-symmetrical with respect to the column boundary, and the shielding layer of the N+2th column and the shielding layer of the N+3th column may be mirror-symmetrical with respect to the column boundary. In an exemplary embodiment, the shapes of the shielding layers in multiple cell rows may be substantially the same.

[0136] (2) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on the substrate on which the aforementioned pattern is formed, patterning the first semiconductor film through a patterning process to form a first insulating layer covering the shielding layer, and a first semiconductor layer pattern disposed on the first insulating layer, as shown in FIG10A and FIG10B , where FIG10B is a plan view schematic diagram of the first semiconductor layer in FIG10A .

[0137] In an exemplary embodiment, the first semiconductor layer pattern of each circuit unit may include at least the first active layer 11 of the first transistor T1, the third active layer 13 of the third transistor T3 to the eighth active layer 18 of the eighth transistor T8, and the third active layer 13 to the seventh active layer 17 are an integrated structure connected to each other, and the first active layer 11 and the eighth active layer 18 are separately provided.

[0138] In an exemplary embodiment, in the pixel driving circuit of the present circuit unit, in the second direction Y, the first active layer 11 and the fourth active layer 14 can be located on the side of the third active layer 13 in the present circuit unit in the opposite direction Y, and the fifth active layer 15, the sixth active layer 16, the seventh active layer 17 and the eighth active layer 18 can be located on the side of the second direction Y of the third active layer 13 in the present circuit unit.

[0139] In an exemplary embodiment, the third active layer 13 may have an inverted "Ω" shape, the fourth active layer 14, the fifth active layer 15, and the sixth active layer 16 may have an "I" shape, and the first active layer 11, the seventh active layer 17, and the eighth active layer 18 may have an "L" shape.

[0140] In an exemplary embodiment, the first active layer 11, the third active layer 13, the third active layer 13, the eighth active layer 18 may each include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the first region 13-1 of the third active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer may be connected to each other, and the first region 13-1 of the third active layer may serve as both the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer. The second region 13-2 of the third active layer is connected to the first region 16-1 of the sixth active layer, and the second region 13-2 of the third active layer may serve as the first region 16-1 of the sixth active layer. The second region 16-2 of the sixth active layer is connected to the second region 17-2 of the seventh active layer, and the second region 16-2 of the sixth active layer may serve as the second region 17-2 of the seventh active layer. The first region 11-1 of the first active layer, the second region 11-2 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, the first region 17-1 of the seventh active layer, the first region 18-1 of the eighth active layer, and the second region 18-2 of the eighth active layer may be separately provided.

[0141] In an exemplary embodiment, the orthographic projection of the third active layer 13 on the substrate at least partially overlaps with the orthographic projection of the shielding electrode 60 on the substrate. The shielding electrode 60 serves as a shielding layer for the third transistor T3, shielding the channel region of the third transistor T3 to ensure the electrical performance of the third transistor T3.

[0142] In an exemplary embodiment, the orthographic projection of the channel region of the third active layer 13 on the substrate is located within the range of the orthographic projection of the shielding electrode 60 on the substrate.

[0143] In an exemplary embodiment, an orthographic projection of the first region 17 - 1 of the seventh active layer on the substrate at least partially overlaps with an orthographic projection of the first spacer 71 on the substrate.

[0144] In an exemplary embodiment, the area of ​​the orthographic projection of the first region 17-1 of the seventh active layer on the substrate may be smaller than the area of ​​the orthographic projection of the first pad 71 on the substrate, and the orthographic projection of the first region 17-1 of the seventh active layer on the substrate is located within the range of the orthographic projection of the first pad 71 on the substrate, so that the orthographic projection of the subsequently formed tenth via hole exposing the first region 17-1 of the seventh active layer on the substrate is located within the range of the orthographic projection of the first pad 71 on the substrate, which can improve the uniformity of the via hole.

[0145] In an exemplary embodiment, the fifth active layers of some two adjacent circuit cells in a cell row may be interconnected as a single unit. For example, the first region 15-1 of the fifth active layer in the N-1th column and the first region 15-1 of the fifth active layer in the Nth column are interconnected, and the fifth active layer 15 in the N-1th column and the fifth active layer 15 in the Nth column are interconnected as a single unit. For another example, the first region 15-1 of the fifth active layer in the N+1th column and the first region 15-1 of the fifth active layer in the N+2th column are interconnected, and the fifth active layer 15 in the N+1th column and the fifth active layer 15 in the N+2th column are interconnected as a single unit. For another example, the first region 15-1 of the fifth active layer in the N+3th column and the first region 15-1 of the fifth active layer in the N+4th column are interconnected, and the fifth active layer 15 in the N+3th column and the fifth active layer 15 in the N+4th column are interconnected as a single unit. Since the first region of the fifth active layer in each circuit unit is configured to be connected to the first power line formed subsequently, by forming the fifth active layers of adjacent circuit units into an integrated structure connected to each other, it can be ensured that the first electrodes of the fifth transistors T5 of adjacent circuit units have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0146] In an exemplary embodiment, within a cell row, the eighth active layers of some two adjacent circuit cells may be interconnected as a single unit. For example, the first region 18-1 of the eighth active layer in the N-1th column and the first region 18-1 of the eighth active layer in the Nth column are interconnected, and the eighth active layer 18 in the N-1th column and the eighth active layer 18 in the Nth column are interconnected as a single unit. For another example, the first region 18-1 of the eighth active layer in the N+1th column and the first region 18-1 of the eighth active layer in the N+2th column are interconnected, and the eighth active layer 18 in the N+1th column and the eighth active layer 18 in the N+2th column are interconnected as a single unit. For another example, the first region 18-1 of the eighth active layer in the N+3th column and the first region 18-1 of the eighth active layer in the N+4th column are interconnected, and the eighth active layer 18 in the N+3th column and the eighth active layer 18 in the N+4th column are interconnected as a single unit. Since the first region of the eighth active layer in each circuit unit is configured to be connected to the third initial signal line formed subsequently, by forming the eighth active layers of adjacent circuit units into an integrated structure connected to each other, it can be ensured that the first electrodes of the eighth transistors of adjacent circuit units have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0147] In an exemplary embodiment, the first active layer 11 may be arranged between two adjacent cell rows, the second region 11-2 of the first active layer may be located in a circuit cell of the current cell row, and the first region 11-1 of the first active layer may be located in a circuit cell of the previous cell row. For example, the second region 11-2 of the first active layer may be located in a circuit cell of the Mth row, and the first region 11-1 of the first active layer may be located in a circuit cell of the M-1th row, where M may be a positive integer greater than or equal to 1.

[0148] In an exemplary embodiment, the first semiconductor layers of adjacent cell columns may be mirror-symmetrical with respect to a column boundary. For example, the first semiconductor layer of the Nth column and the first semiconductor layer of the N+1th column may be mirror-symmetrical with respect to the column boundary, the first semiconductor layer of the N+1th column and the first semiconductor layer of the N+2th column may be mirror-symmetrical with respect to the column boundary, and the first semiconductor layer of the N+2th column and the first semiconductor layer of the N+3th column may be mirror-symmetrical with respect to the column boundary. In an exemplary embodiment, the shapes of the first semiconductor layers in multiple cell rows may be substantially the same.

[0149] In an exemplary embodiment, the first semiconductor layer may be made of polycrystalline silicon (p-Si), meaning the third to seventh transistors are LTPS transistors. In an exemplary embodiment, patterning the first semiconductor film through a patterning process may include: first forming an amorphous silicon (a-Si) film on the first insulating film, performing a dehydrogenation treatment on the amorphous silicon film, and then crystallizing the dehydrogenated amorphous silicon film to form a polycrystalline silicon film. Subsequently, patterning the polycrystalline silicon film to form a first semiconductor layer pattern.

[0150] FIG10C is an enlarged view of region A in FIG10A . As shown in FIG10A , FIG10B , and FIG10C , in an exemplary embodiment, the third active layer 13 may include at least a third source region 13-1. The third source region 13-1 may be in the shape of a strip extending along the first direction X. The third source region 13-1 is connected to the fourth active layer 14 and the fifth active layer 15, respectively.

[0151] In an exemplary embodiment, the first shielding connection bar 61 may be in the shape of a straight line or a broken line extending along the first direction X, and the orthographic projection of the third source region 13 - 1 on the substrate does not overlap with the orthographic projection of the first shielding connection bar 61 on the substrate.

[0152] In an exemplary embodiment, in at least one circuit unit, the first blocking connecting bar 61 may be located on one side of the third source region 13 - 1 in the second direction Y.

[0153] In an exemplary embodiment, the third source region 13-1 may have at least a source region edge 19-0 proximate to the first shielding connection bar 61, and the first shielding connection bar 61 may have at least a shielding edge 61-0 proximate to the third source region 13-1. In at least one circuit unit, a separation distance L0 may be defined between the source region edge 19-0 and the shielding edge 61-0, and the separation distance L0 may be greater than or equal to 0.5 μm.

[0154] In this embodiment, the third source region and the first shielding connection strip are not overlapped, and the distance between the edge of the third source region and the edge of the first shielding connection strip is greater than or equal to 0.5μm. Even if the position of the shielding layer and the first semiconductor layer changes due to fluctuations in the manufacturing process, the consistency of the capacitance at the semiconductor node position in each circuit unit can be effectively guaranteed, thereby avoiding display uniformity and horizontal stripes caused by capacitance differences, and improving the display effect and display quality.

[0155] (3) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a second insulating layer covering the first semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG11A and FIG11B , where FIG11B is a plan view schematic diagram of the first conductive layer in FIG11A . In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0156] In an exemplary embodiment, the first conductive layer pattern of each circuit unit includes at least a first scan signal line 21 , a second scan signal line 22 , a third scan signal line 23 , a light emitting signal line 25 and a first plate 31 of a storage capacitor.

[0157] In an exemplary embodiment, the first electrode plate 31 may be rectangular, with chamfered or grooved corners. The orthographic projection of the first electrode plate 31 on the substrate at least partially overlaps the orthographic projection of the third active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first electrode plate 31 may serve as both a plate of the storage capacitor and a gate electrode of the third transistor T3.

[0158] In an exemplary embodiment, the orthographic projection of the channel region of the third active layer on the substrate is located within the range of the orthographic projection of the first electrode plate 31 on the substrate.

[0159] In an exemplary embodiment, an orthographic projection of the first electrode plate 31 on the substrate at least partially overlaps with an orthographic projection of the shielding electrode 60 on the substrate.

[0160] In an exemplary embodiment, the shape of the first scanning signal line 21 can be a straight line or a broken line with the main portion extending along the first direction X. The first scanning signal line 21 can be located on the side of the first electrode 31 in the opposite direction of the second direction Y. The area where the first scanning signal line 21 overlaps with the fourth active layer can serve as the gate electrode of the fourth transistor T4.

[0161] In an exemplary embodiment, the shape of the second scanning signal line 22 can be a straight line or a broken line with the main portion extending along the first direction X. The second scanning signal line 22 can be located on one side of the first electrode 31 in the second direction Y. The area where the second scanning signal line 22 overlaps with the seventh active layer can serve as the gate electrode of the seventh transistor T7, and the area where the second scanning signal line 22 overlaps with the eighth active layer can serve as the gate electrode of the eighth transistor T8.

[0162] In an exemplary embodiment, the shape of the third scan signal line 23 can be a straight line or a broken line with the main portion extending along the first direction X. The third scan signal line 23 can be located on a side of the first scan signal line 21 away from the first electrode plate 31, and the area where the third scan signal line 23 overlaps with the first active layer can serve as the gate electrode of the first transistor T1.

[0163] In an exemplary embodiment, the shape of the light-emitting signal line 25 can be a straight line or a broken line with the main part extending along the first direction X. The light-emitting signal line 25 can be located between the first electrode 31 and the second scanning signal line 22. The area where the light-emitting signal line 25 overlaps with the fifth active layer can serve as the gate electrode of the fifth transistor T5, and the area where the light-emitting signal line 25 overlaps with the sixth active layer can serve as the gate electrode of the sixth transistor T6.

[0164] In an exemplary embodiment, the first scanning signal line 21, the second scanning signal line 22, the third scanning signal line 23 and the light-emitting signal line 25 can be designed with non-equal widths, and the width is the dimension in the second direction Y, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines. The present disclosure does not limit this.

[0165] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23 and the light emitting signal line 25 may include an overlapping area with the first semiconductor layer and an area not overlapping with the first semiconductor layer, and the width of the signal line in the area overlapping with the first semiconductor layer may be greater than the width of the signal line in the area not overlapping with the first semiconductor layer.

[0166] In an exemplary embodiment, the first conductive layers of adjacent cell columns may be mirror-symmetric with respect to a column boundary. For example, the first conductive layer of the Nth column and the first conductive layer of the N+1th column may be mirror-symmetric with respect to the column boundary, the first conductive layer of the N+1th column and the first conductive layer of the N+2th column may be mirror-symmetric with respect to the column boundary, and the first conductive layer of the N+2th column and the first conductive layer of the N+3th column may be mirror-symmetric with respect to the column boundary. In an exemplary embodiment, the shapes of the first conductive layers in multiple cell rows may be substantially the same.

[0167] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the first semiconductor layer. The first semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 and the third transistor T3 to the eighth transistor T8, and the first semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of ​​the first transistor T1 and the third transistor T3 to the eighth transistor T8 are all conductorized.

[0168] (4) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate having the aforementioned pattern formed thereon, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIG12A and FIG12B , where FIG12B is a plan view schematic diagram of the second conductive layer in FIG12A . In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0169] In an exemplary embodiment, the second conductive layer pattern of each circuit unit includes at least a second electrode 32 of the storage capacitor and a shielding line 33 .

[0170] In an exemplary embodiment, the outline of the second electrode plate 32 can be rectangular, and the corners of the rectangle can be chamfered or grooved. The orthographic projection of the second electrode plate 32 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 31 on the substrate. The second electrode plate 32 can serve as another electrode plate of the storage capacitor, and the first electrode plate 31 and the second electrode plate 32 constitute the storage capacitor of the pixel driving circuit.

[0171] In an exemplary embodiment, an opening 34 is provided on the second electrode plate 32. Opening 34 can be rectangular and located in the middle of the second electrode plate 32, forming a ring-shaped structure. Opening 34 exposes the third insulating layer covering the first electrode plate 31, and the orthographic projection of the first electrode plate 31 on the substrate includes the orthographic projection of opening 34 on the substrate. In an exemplary embodiment, opening 34 is configured to accommodate a thirteenth via hole to be formed later. The thirteenth via hole is located within opening 34 and exposes the first electrode plate 31, allowing a first connecting electrode to be formed later to connect to the first electrode plate 31.

[0172] In an exemplary embodiment, the second electrode plate 32 may be provided with a first plate-level connecting bar 35 and a second plate-level connecting bar 36. The first plate-level connecting bar 35 may be in the shape of a straight line or a zigzag line extending along the first direction X. The first plate-level connecting bar 35 may be disposed on one side of the second electrode plate 32 in the first direction X or on a side opposite to the first direction X. The first end of the first plate-level connecting bar 35 is connected to the second electrode plate 32 in the current circuit unit, and the second end of the first plate-level connecting bar 35 is connected to the first plate-level connecting bar 35 in the adjacent circuit unit in the first direction X. The second plate-level connecting bar 36 may be in the shape of a straight line or a zigzag line extending along the first direction X. The second plate-level connecting bar 36 may be disposed on one side of the second electrode plate 32 in the first direction X or on a side opposite to the first direction X. The first end of the second plate-level connecting bar 36 is connected to the second electrode plate 32 in the current circuit unit, and the second end of the second plate-level connecting bar 36 is connected to the second plate-level connecting bar 36 in the adjacent circuit unit in the first direction X.

[0173] In an exemplary embodiment, the first board-level connecting bar 35 has a first width, and the second board-level connecting bar 36 has a second width. The first width may be greater than the second width. The first width and the second width are dimensions in the second direction Y.

[0174] In an exemplary embodiment, the first board-level connecting bar 35 and the second board-level connecting bar 36 may be staggered in the second direction.

[0175] In an exemplary embodiment, the second plates 32 in two adjacent circuit units in a unit row can be interconnected integral structures. For example, the second plate 32 in the Nth column and the second plate 32 in the N+1th column are interconnected by a second plate-level connecting bar 36 to form an interconnected integral structure. For another example, the second plate 32 in the N+1th column and the second plate 32 in the N+2th column can be interconnected by a first plate-level connecting bar 35 to form an interconnected integral structure. Since the second plate 32 in each circuit unit is connected to the first power line formed subsequently, by forming the second plates 32 of adjacent circuit units into an interconnected integral structure, the second plates of the integral structure can be reused as a power signal line, which can ensure that the multiple second plates in a unit row have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0176] In an exemplary embodiment, the shape of the shielding line 33 can be a straight line or a line shape with the main part extending along the first direction X. The shielding line 33 can be located between the first scanning signal line 21 and the third scanning signal line 23. The shielding line 33 is configured as a shielding layer of the second transistor T2, shielding the channel region of the second transistor T2, ensuring the electrical performance of the oxide second transistor T2, and at the same time being configured as the bottom gate electrode of the second transistor T2.

[0177] In an exemplary embodiment, the shielding lines 33 may be designed as zigzag lines with unequal widths, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines.

[0178] In an exemplary embodiment, the second conductive layers of adjacent cell columns may be mirror-symmetric with respect to a column boundary. For example, the second conductive layer of the Nth column and the second conductive layer of the N+1th column may be mirror-symmetric with respect to the column boundary, the second conductive layer of the N+1th column and the second conductive layer of the N+2th column may be mirror-symmetric with respect to the column boundary, and the second conductive layer of the N+2th column and the second conductive layer of the N+3th column may be mirror-symmetric with respect to the column boundary. In an exemplary embodiment, the shapes of the second conductive layers in multiple cell rows may be substantially the same.

[0179] Figure 12C is an enlarged view of area A in Figure 12A. As shown in Figures 12A, 12B, and 12C, in an exemplary embodiment, the shape of the first board-level connecting bar 35 can be a straight line or a broken line extending along the first direction X, and the orthographic projection of the third source region 13-1 on the substrate can be located within the range of the orthographic projection of the first board-level connecting bar 35 on the substrate.

[0180] In an exemplary embodiment, the third source region 13-1 may have at least a first active edge 19-1 and a second active edge 19-2, and the shapes of the first active edge 19-1 and the second active edge 19-2 may be straight lines or broken lines extending along the first direction X. The first active edge 19-1 may be located on a side of the third source region 13-1 in the opposite direction of the second direction Y (i.e., a side close to the first scan line 21), and the second active edge 19-2 may be located on a side of the third source region 13-1 in the second direction Y (i.e., a side away from the first scan line 21).

[0181] In an exemplary embodiment, the first board-level connecting strip 35 may have at least a first board-level edge 35-1 and a second board-level edge 35-2. The shapes of the first board-level edge 35-1 and the second board-level edge 35-2 may be straight lines or broken lines extending along the first direction X. The first board-level edge 35-1 may be located on the side of the first board-level connecting strip 35 in the opposite direction of the second direction Y (i.e., the side close to the first scan line 21), and the second board-level edge 35-2 may be located on the side of the first board-level connecting strip 35 in the second direction Y (i.e., the side away from the first scan line 21).

[0182] In an exemplary embodiment, in at least one circuit unit, a first distance L1 is provided between the first active edge 19 - 1 and the first board-level edge 35 - 1 . The first distance L1 may be greater than or equal to 0.5 μm.

[0183] In an exemplary embodiment, in at least one circuit unit, a second distance L2 is provided between the second active edge 19 - 2 and the second board-level edge 35 - 2 . The second distance L2 may be greater than or equal to 0.5 μm.

[0184] In this embodiment, the first board-level connecting strip is set to completely cover the third source area, and the distance between the edge of the third source area and the edge of the first blocking connecting strip is greater than or equal to 0.5μm. Even if the position of the first semiconductor layer and the second conductive layer changes due to fluctuations in the manufacturing process, the consistency of the capacitance at the semiconductor node position in each circuit unit can be effectively guaranteed, thereby avoiding display uniformity and horizontal stripes caused by capacitance differences, and improving the display effect and display quality.

[0185] (5) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern may include: sequentially depositing a fourth insulating film and a second semiconductor film on the substrate having the aforementioned pattern formed thereon, patterning the second semiconductor film through a patterning process to form a fourth insulating layer covering the substrate, and a second semiconductor layer pattern disposed on the fourth insulating layer, as shown in FIG13A and FIG13B , where FIG13B is a plan view schematic diagram of the second semiconductor layer in FIG13A .

[0186] In an exemplary embodiment, the second semiconductor layer pattern of each circuit unit includes at least a second active layer 12 of a second transistor T2 .

[0187] In an exemplary embodiment, the second active layer 12 may be in an “L” shape, and an orthographic projection of the second active layer 12 on the substrate at least partially overlaps an orthographic projection of the shielding line 33 on the substrate.

[0188] In an exemplary embodiment, the first region 12 - 1 of the second active layer may be located on a side of the shielding line 33 close to the second electrode plate 32 , and the second region 12 - 2 of the second active layer may be located on a side of the shielding line 33 away from the second electrode plate 32 .

[0189] In an exemplary embodiment, an orthographic projection of the second active layer 12 on the substrate at least partially overlaps an orthographic projection of the first scan signal line 21 on the substrate.

[0190] In an exemplary embodiment, the second semiconductor layers of adjacent cell columns may be mirror-symmetrical with respect to a column boundary. For example, the second semiconductor layer of the Nth column and the second semiconductor layer of the N+1th column may be mirror-symmetrical with respect to the column boundary, the second semiconductor layer of the N+1th column and the second semiconductor layer of the N+2th column may be mirror-symmetrical with respect to the column boundary, and the second semiconductor layer of the N+2th column and the second semiconductor layer of the N+3th column may be mirror-symmetrical with respect to the column boundary. In an exemplary embodiment, the shapes of the second semiconductor layers in multiple cell rows may be substantially the same.

[0191] Figure 13C is an enlarged view of region B in Figure 13A. As shown in Figures 13A, 13B, and 13C, the second active layer 12 may include a first active segment 12A, a second source region (i.e., the first region of the second active layer) 12-1, a second active segment 12B, and a second drain region (i.e., the second region of the second active layer) 12-2. The first active segment 12A may be in the shape of a strip extending along the first direction X, and the second source region 12-1 may be in the shape of a block (e.g., a rectangle). The first active segment 12A and the second source region 12-1 may be located on the side of the shielding line 33 close to the second electrode 32.

[0192] The second active segment 12B may be in the shape of a strip extending along the second direction Y, and the second drain region 12-2 may be in the shape of a block (e.g., a rectangle). The second drain region 12-2 may be located on the side of the shielding line 33 away from the second electrode plate 32. The first end of the first active segment 12A is connected to the second source region 12-1, and the second end of the first active segment 12A extends along the first direction X or the direction opposite to the first direction X and is connected to the first end of the second active segment 12B. The first end of the second active segment 12B is connected to the second end of the first active segment 12A, and the second end of the second active segment 12B extends along the direction opposite to the second direction Y and is connected to the second drain region 12-2.

[0193] In an exemplary embodiment, the second source region 12 - 1 is configured to be connected to the first electrode 31 through a first connection electrode formed subsequently, and the second drain region 12 - 2 is configured to be connected to the third drain region of the third active layer 13 through a second connection electrode formed subsequently.

[0194] In an exemplary embodiment, in at least one circuit unit, an orthographic projection of the first active segment 12A of the second active layer 12 on the substrate at least partially overlaps with an orthographic projection of the first scan signal line 21 on the substrate.

[0195] In an exemplary embodiment, in at least one circuit unit, the width of the first active section 12A may be greater than the width of the first scan signal line 21 , and the width is the dimension in the second direction Y.

[0196] In an exemplary embodiment, the first active segment 12A may have at least a third active edge 19-3 and a fourth active edge 19-4. The shapes of the third active edge 19-3 and the fourth active edge 19-4 may be a straight line or a broken line with the main body extending along the first direction X. The third active edge 19-3 may be located on the side of the first active segment 12A in the opposite direction of the second direction Y (i.e., the side close to the blocking line 33), and the fourth active edge 19-4 may be located on the side of the first active segment 12A in the second direction Y (i.e., the side away from the blocking line 33).

[0197] In an exemplary embodiment, the first scanning signal line 21 may have at least a first scanning edge 21-1 and a second scanning edge 21-2. The shapes of the first scanning edge 21-1 and the second scanning edge 21-2 may be straight lines or broken lines with the main body extending along the first direction X. The first scanning edge 21-1 may be located on the side of the first scanning signal line 21 in the opposite direction of the second direction Y (i.e., the side close to the shielding line 33), and the second scanning edge 21-2 may be located on the side of the first scanning signal line 21 in the second direction Y (i.e., the side away from the shielding line 33).

[0198] In an exemplary embodiment, in at least one circuit unit, in the overlapping area of ​​the first active segment 12A and the first scanning signal line 21, the orthographic projections of the first scanning edge 21-1 and the second scanning edge 21-2 on the substrate are located within the range of the orthographic projection of the first active segment 12A on the substrate, and the orthographic projection of the first active segment 12A on the substrate includes the orthographic projections of the first scanning edge 21-1 and the second scanning edge 21-2 on the substrate, that is, the first active segment 12A overlays the first scanning edge 21-1 and the second scanning edge 21-2 of the first scanning signal line 21.

[0199] In an exemplary embodiment, in at least one circuit unit, a third distance L3 is provided between the third active edge 19 - 3 and the first scanning edge 21 - 1 in the overlapping region between the first active segment 12A and the first scanning signal line 21 . The third distance L3 may be greater than or equal to 0.5 μm.

[0200] In an exemplary embodiment, in at least one circuit unit, a fourth distance L4 is provided between the fourth active edge 19 - 4 and the second scanning edge 21 - 2 in the overlapping region between the first active segment 12A and the first scanning signal line 21 . The fourth distance L4 may be greater than or equal to 0.5 μm.

[0201] In the exemplary embodiment, because the second source region 12-1 is connected to the first electrode plate 31 via a subsequently formed first connection electrode, forming the first node N1 of the pixel driving circuit, the first active segment 12A has a potential of the first node N1, and the first active segment 12A forms a holding capacitor Cb with the first scan signal line 21. By setting the distance between the edge of the first active segment and the edge of the first scan signal line 21 to be greater than or equal to 0.5 μm, the present disclosure effectively ensures consistency of the holding capacitor Cb across all circuit units, even if the positions of the first conductive layer and the second semiconductor layer vary due to manufacturing process fluctuations. This avoids display uniformity and streaks caused by capacitance variations, thereby improving display quality and performance.

[0202] In an exemplary embodiment, in at least one circuit unit, a second spacer 72 is disposed on the first scan signal line 21 . The second spacer 72 may be block-shaped (eg, rectangular) and connected to the first scan signal line 21 .

[0203] In an exemplary embodiment, the first scan signal line 21 and the second spacer 72 may be an integral structure connected to each other.

[0204] In an exemplary embodiment, the orthographic projection of the second pad 72 on the substrate at least partially overlaps with the orthographic projection of the second drain region 12-2 of the second active layer on the substrate, so that the orthographic projection of the third via hole that subsequently exposes the second drain region 12-2 of the second active layer on the substrate is within the range of the orthographic projection of the second pad 72 on the substrate, which can improve the uniformity of the via hole.

[0205] In an exemplary embodiment, the second semiconductor layer may be made of oxide, that is, the eighth transistor T8 is an oxide transistor. In an exemplary embodiment, the second semiconductor thin film may be made of indium gallium zinc oxide (IGZO), which has higher electron mobility than amorphous silicon.

[0206] (6) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: sequentially depositing a fifth insulating film and a third conductive film on the substrate having the aforementioned pattern formed thereon, patterning the third conductive film using a patterning process to form a fifth insulating layer covering the second semiconductor layer, and a third conductive layer pattern disposed on the fifth insulating layer, as shown in FIG14A and FIG14B , where FIG14B is a plan view schematic diagram of the third conductive layer in FIG14A . In an exemplary embodiment, the second conductive layer may be referred to as a third gate metal (GATE3) layer.

[0207] In an exemplary embodiment, the third conductive layer pattern of each circuit unit includes at least a fourth scan signal line 24 , a first preliminary signal line 41 , a second preliminary signal line 42 , and a third preliminary signal line 43 .

[0208] In an exemplary embodiment, the shape of the fourth scan signal line 24 can be a straight line or a line shape with the main portion extending along the first direction X. The fourth scan signal line 24 can be located between the first scan signal line 21 and the third scan signal line 23. The area where the fourth scan signal line 24 overlaps with the second active layer can serve as the gate electrode of the second transistor T2.

[0209] In an exemplary embodiment, the orthographic projection of the fourth scan signal line 24 on the substrate at least partially overlaps with the orthographic projection of the shielding line 33 on the substrate, and the fourth scan signal line 24 and the shielding line 33 can be connected to the same signal source, so that the shielding line 33 can serve as the bottom gate electrode of the second transistor T2, and the fourth scan signal line 24 can serve as the top gate electrode of the second transistor T2, forming a second transistor T2 with a top-gate and bottom-gate structure.

[0210] In an exemplary embodiment, the shape of the first initial signal line 41 can be a straight line or a broken line with the main portion extending along the first direction X. The first initial signal line 41 can be located on the side of the light-emitting signal line 25 away from the second electrode 32. The first initial signal line 41 is configured to be connected to the first region of the first active layer through a seventh connecting electrode formed subsequently.

[0211] In an exemplary embodiment, the orthographic projection of the first initial signal line 41 on the substrate at least partially overlaps with the orthographic projection of the second scanning signal line 22 on the substrate, and the first initial signal line 41 with a constant voltage can act as a shield to reduce the impact of the second scanning signal line 22 on the pixel driving circuit.

[0212] In an exemplary embodiment, the shape of the second initial signal line 42 can be a straight line or a broken line with the main portion extending along the first direction X. The second initial signal line 42 can be located on the side of the first initial signal line 41 away from the second electrode 32. The second initial signal line 42 is configured to be connected to the first region of the seventh active layer through the subsequently formed eighth connecting electrode.

[0213] In an exemplary embodiment, the orthographic projection of the second initial signal line 42 on the substrate at least partially overlaps with the orthographic projection of the third scanning signal line 23 on the substrate, and the second initial signal line 42 with a constant voltage can act as a shield, reducing the impact of the third scanning signal line 23 on the pixel driving circuit.

[0214] In an exemplary embodiment, the shape of the third initial signal line 43 can be a straight line or a broken line with the main portion extending along the first direction X. The third initial signal line 43 can be located on the side of the first initial signal line 41 close to the second electrode 32. The third initial signal line 43 is configured to be connected to the first region of the eighth active layer through a ninth connecting electrode formed subsequently.

[0215] In an exemplary embodiment, the orthographic projection of the third initial signal line 43 on the substrate at least partially overlaps with the orthographic projection of the luminous signal line 25 on the substrate. The third initial signal line 43 with a constant voltage can play a shielding role, reducing the impact of the luminous signal line 25 on the pixel driving circuit.

[0216] In an exemplary embodiment, the third conductive layers of adjacent cell columns may be mirror-symmetric with respect to a column boundary. For example, the third conductive layer of the Nth column and the third conductive layer of the N+1th column may be mirror-symmetric with respect to the column boundary, the third conductive layer of the N+1th column and the third conductive layer of the N+2th column may be mirror-symmetric with respect to the column boundary, and the third conductive layer of the N+2th column and the third conductive layer of the N+3th column may be mirror-symmetric with respect to the column boundary. In an exemplary embodiment, the shapes of the third conductive layers in multiple cell rows may be substantially the same.

[0217] (7) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming the sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the fifth insulating film using a patterning process to form a sixth insulating layer covering the third conductive layer, wherein the sixth insulating layer is provided with a plurality of vias, as shown in FIG. 15A .

[0218] In an exemplary embodiment, the multiple vias of each circuit unit include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16 and a seventeenth via V17.

[0219] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the first via hole V1 are etched away to expose the surface of the first region of the first active layer, and the first via hole V1 is configured to connect a subsequently formed seventh connecting electrode to the first region of the first active layer through the via hole.

[0220] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second region of the first active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the second via hole V2 are etched away to expose the surface of the second region of the first active layer, and the second via hole V2 is configured to connect a subsequently formed second connecting electrode to the second region of the first active layer through the via hole.

[0221] In an exemplary embodiment, since the first active layer 11 spans between two adjacent cell rows, the first via V1 can be located in a circuit cell of the previous cell row, and the second via V2 can be located in a circuit cell of the current cell row. For example, the first via V1 can be located in a circuit cell of the M-1th cell row, and the second via V2 can be located in a circuit cell of the Mth cell row.

[0222] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first region of the second active layer on the substrate, the sixth insulating layer and the fifth insulating layer in the third via hole V3 are etched away to expose the surface of the first region of the second active layer, and the third via hole V3 is configured to connect a subsequently formed first connecting electrode to the first region of the second active layer through the via hole.

[0223] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second region of the second active layer on the substrate, the sixth insulating layer and the fifth insulating layer in the fourth via hole V4 are etched away to expose the surface of the second region of the second active layer, and the fourth via hole V4 is configured to connect a subsequently formed second connecting electrode to the second region of the second active layer through the via hole.

[0224] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the second area of ​​the third active layer (also the first area of ​​the sixth active layer) on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the second area of ​​the third active layer (also the first area of ​​the sixth active layer), and the fifth via hole V5 is configured to connect the subsequently formed second connecting electrode to the second area of ​​the third active layer (also the first area of ​​the sixth active layer) through the via hole.

[0225] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the first area of ​​the fourth active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via hole V6 are etched away to expose the surface of the first area of ​​the fourth active layer. The sixth via hole V6 is configured to connect a subsequently formed third connecting electrode to the first area of ​​the fourth active layer through the via hole.

[0226] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is located within the orthographic projection of the first region of the fifth active layer on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the seventh via V7 are etched away, exposing the surface of the first region of the fifth active layer. The seventh via V7 is configured to connect a subsequently formed fourth connection electrode to the first region of the fifth active layer through the via. In an exemplary embodiment, because the first regions of the fifth active layers of some adjacent circuit cells in a cell row are interconnected, some of the adjacent circuit cells can share one seventh via V7.

[0227] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the second area of ​​the fifth active layer (also the first area of ​​the third active layer and the second area of ​​the fourth active layer) on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the eighth via V8 are etched away to expose the surface of the second area of ​​the fifth active layer (also the first area of ​​the third active layer and the second area of ​​the fourth active layer), and the eighth via V8 is configured to connect the subsequently formed fifth connecting electrode to the second area of ​​the fifth active layer (also the first area of ​​the third active layer and the second area of ​​the fourth active layer) through the via hole.

[0228] In an exemplary embodiment, the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the ninth via hole V9 are etched away to expose the surface of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer), and the ninth via hole V9 is configured to connect the subsequently formed sixth connecting electrode to the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) through the via hole.

[0229] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the tenth via hole V10 are etched away to expose the surface of the first region of the seventh active layer, and the tenth via hole V10 is configured to connect the subsequently formed eighth connecting electrode to the first region of the seventh active layer through the via hole.

[0230] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the orthographic projection of the first region of the eighth active layer on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the eleventh via hole V11 are etched away, exposing the surface of the first region of the eighth active layer. The eleventh via hole V11 is configured to connect a subsequently formed ninth connecting electrode to the first region of the eighth active layer through the via hole. In an exemplary embodiment, since the first regions of the eighth active layer of some adjacent circuit cells in a cell row are interconnected, some of the adjacent circuit cells can share the same eleventh via hole V11.

[0231] In an exemplary embodiment, the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the second region of the eighth active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the twelfth via hole V12 are etched away to expose the surface of the second region of the eighth active layer. The twelfth via hole V12 is configured to connect the subsequently formed fifth connecting electrode to the second region of the eighth active layer through the via hole.

[0232] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the opening 34 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer in the thirteenth via hole V13 are etched away to expose the surface of the first electrode 31. The thirteenth via hole V13 is configured to connect the subsequently formed first connecting electrode to the first electrode 31 through the via hole.

[0233] In the exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is located within the range of the orthographic projection of the first board-level connecting bar 35 of the second electrode plate 32 on the substrate. The sixth insulating layer, the fifth insulating layer, and the fourth insulating layer within the fourteenth via V14 are etched away, exposing the surface of the first board-level connecting bar 35. The fourteenth via V14 is configured to connect a subsequently formed fourth connecting electrode to the second electrode plate 32 through this via. In the exemplary embodiment, because the second electrodes 32 of adjacent circuit cells in a cell row are interconnected via the first board-level connecting bar 35, some adjacent circuit cells in a cell row can share a single fourteenth via V14.

[0234] In an exemplary embodiment, the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the first initial signal line 41 on the substrate, the sixth insulating layer in the fifteenth via hole V15 is etched away to expose the surface of the first initial signal line 41, and the fifteenth via hole V15 is configured to connect the subsequently formed seventh connecting electrode to the first initial signal line 41 through the via hole.

[0235] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate can be located within the range of the orthographic projection of the second scan signal line 22 on the substrate. At the location where the fourth conductive layer (SD1) and the third conductive layer (GATE3) overlap through the fifteenth via V15, the present disclosure provides the second scan signal line 22 as a spacer in the first conductive layer (GATE1) below the via. This effectively ensures the uniformity of the via even if the first conductive layer, the third conductive layer, or the via position shifts due to manufacturing process fluctuations, thus avoiding defects such as watermarks caused by poor via uniformity.

[0236] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the substrate is located within the range of the orthographic projection of the second initial signal line 42 on the substrate, the sixth insulating layer in the sixteenth via V16 is etched away to expose the surface of the second initial signal line 42, and the sixteenth via V16 is configured to connect the subsequently formed eighth connecting electrode to the second initial signal line 42 through the via.

[0237] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the substrate can be located within the range of the orthographic projection of the third scan signal line 23 on the substrate. At the location where the fourth conductive layer (SD1) and the third conductive layer (GATE3) overlap through the sixteenth via V16, the present disclosure provides the third scan signal line 23 as a spacer in the first conductive layer (GATE1) below the via. This effectively ensures the uniformity of the via even if the first conductive layer, the third conductive layer, or the via position shifts due to manufacturing process fluctuations, thus avoiding defects such as watermarks caused by poor via uniformity.

[0238] In an exemplary embodiment, the orthographic projection of the seventeenth via hole V17 on the substrate is located within the range of the orthographic projection of the third initial signal line 43 on the substrate, the sixth insulating layer in the seventeenth via hole V17 is etched away to expose the surface of the third initial signal line 43, and the seventeenth via hole V17 is configured to connect the subsequently formed ninth connecting electrode to the third initial signal line 43 through the via hole.

[0239] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 on the substrate can be located within the range of the orthographic projection of the luminescent signal line 25 on the substrate. At the location where the fourth conductive layer (SD1) and the third conductive layer (GATE3) overlap through the seventeenth via V17, the present disclosure provides the luminescent signal line 25 as a spacer in the first conductive layer (GATE1) below the via. This effectively ensures the uniformity of the via even if the first conductive layer, the third conductive layer, or the via position shifts due to manufacturing process fluctuations, thus avoiding defects such as watermarks caused by poor via uniformity.

[0240] In an exemplary embodiment, the plurality of via holes in adjacent cell columns may be mirror-symmetrical with respect to a column boundary line, and the shapes of the plurality of via holes in the plurality of cell rows may be substantially the same.

[0241] Figure 15B is an enlarged view of area C in Figure 15A, illustrating the positional relationship between the shielding layer, the first semiconductor layer and the via in this area. As shown in Figures 15A and 15B, in an exemplary embodiment, the shielding layer may include at least a shielding electrode 60, and the shape of the shielding electrode 60 may be a block shape (such as a rectangle). The first semiconductor layer may include at least a fifth active layer 15, and the shape of the second area 15-2 of the fifth active layer may be a block shape (such as a rectangle). An eighth via V8 is provided in the area where the second area 15-2 of the fifth active layer is located, and the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the second area 15-2 of the fifth active layer on the substrate, and the eighth via V8 exposes the surface of the second area 15-2 of the fifth active layer.

[0242] In an exemplary embodiment, the orthographic projection of the second region 15 - 2 of the fifth active layer on the substrate does not overlap with the orthographic projection of the blocking electrode 60 on the substrate, and the orthographic projection of the eighth via hole V8 on the substrate does not overlap with the orthographic projection of the blocking electrode 60 on the substrate.

[0243] In an exemplary embodiment, a fifth distance L5 is provided between the eighth via hole V8 and the shielding electrode 60. The fifth distance L5 may be greater than or equal to 0.5 μm. In an exemplary embodiment, the fifth distance L5 may be the minimum distance between an edge of the eighth via hole V8 on a side close to the shielding electrode 60 and an edge of the shielding electrode 60 on a side close to the eighth via hole V8.

[0244] The present invention provides that the second region 15-2 of the fifth active layer does not overlap with the shielding electrode 60, and the distance between the eighth via V8 and the shielding electrode 60 is greater than or equal to 0.5 μm. Even if the position of the shielding layer, the first semiconductor layer or the via changes due to fluctuations in the manufacturing process, the uniformity of the via can be effectively guaranteed, thereby avoiding defects such as watermarks caused by poor uniformity of the via.

[0245] Figure 15C is an enlarged view of the D area in Figure 15A, illustrating the positional relationship between the shielding layer, the first semiconductor layer and the via in this area. As shown in Figures 15A and 15C, in an exemplary embodiment, the shielding layer may include at least a second shielding connecting strip 62, and the shape of the second shielding connecting strip 62 may be a straight line or a broken line extending along the second direction Y. The first semiconductor layer may include at least an eighth active layer 18, and the shape of the second area 18-2 of the eighth active layer may be a block shape (such as a rectangle). A twelfth via V12 is provided in the area where the second area 18-2 of the eighth active layer is located. The orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the second area 18-2 of the eighth active layer on the substrate, and the twelfth via V12 exposes the surface of the second area 18-2 of the eighth active layer.

[0246] In an exemplary embodiment, the orthographic projection of the second region 18 - 2 of the eighth active layer on the substrate does not overlap with the orthographic projection of the second blocking connecting bar 62 on the substrate, and the orthographic projection of the twelfth via hole V12 on the substrate does not overlap with the orthographic projection of the second blocking connecting bar 62 on the substrate.

[0247] In an exemplary embodiment, a sixth distance L6 is provided between the twelfth via hole V12 and the second blocking connection bar 62. The sixth distance L6 may be greater than or equal to 0.5 μm. In an exemplary embodiment, the sixth distance L6 may be the minimum distance between an edge of the twelfth via hole V12 on a side close to the second blocking connection bar 62 and an edge of the second blocking connection bar 62 on a side close to the twelfth via hole V12.

[0248] The present disclosure arranges that the second region 18-2 of the eighth active layer does not overlap with the second shielding connecting strip 62, and the distance between the twelfth via V12 and the second shielding connecting strip 62 is greater than or equal to 0.5 μm. Even if the position of the shielding layer, the first semiconductor layer or the via changes due to fluctuations in the manufacturing process, the uniformity of the via can be effectively guaranteed, thereby avoiding defects such as watermarks caused by poor uniformity of the via.

[0249] Figure 15D is an enlarged view of area E in Figure 15A, illustrating the positional relationship between the shielding layer, the first semiconductor layer, and the via in this area. As shown in Figures 15A and 15D, in an exemplary embodiment, the shielding layer includes at least a first spacer 71, which can be shaped like a block (e.g., a rectangle). The first semiconductor layer includes at least a seventh active layer 17, and the first region 17-1 of the seventh active layer can be shaped like a block (e.g., a rectangle). The orthographic projection of the first region 17-1 of the seventh active layer on the substrate is within the range of the orthographic projection of the first spacer 71 on the substrate, and the orthographic projection area of ​​the first region 17-1 of the seventh active layer on the substrate is smaller than the orthographic projection area of ​​the first spacer 71 on the substrate. A tenth via V10 is provided in the area where the first region 17-1 of the seventh active layer is located. The orthographic projection of the tenth via V10 on the substrate is within the range of the orthographic projection of the first region 17-1 of the seventh active layer on the substrate, and the tenth via V10 exposes the surface of the first region 17-1 of the seventh active layer.

[0250] In an exemplary embodiment, a seventh distance L7 is defined between an edge of the tenth via hole V10 and an edge of the first spacer 71. The seventh distance L7 may be greater than or equal to 0.5 μm. In an exemplary embodiment, the seventh distance L7 may be the minimum distance between the edge of the tenth via hole V10 and the edge of the first spacer 71, that is, the minimum distance between any point on the edge of the twelfth via hole V12 and any point on the edge of the first spacer 71.

[0251] The present disclosure arranges a first pad 71 below the first area of ​​the seventh active layer, the area of ​​the first pad 71 is larger than the area of ​​the first area of ​​the seventh active layer, and the orthographic projection of the first area of ​​the seventh active layer on the substrate is located within the range of the orthographic projection of the first pad 71 on the substrate, so that the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the first pad 71 on the substrate, and the distance between the edge of the tenth via hole V10 and the edge of the first pad 71 is greater than or equal to 0.5 μm. Even if the blocking layer, the first semiconductor layer or the via hole position changes due to fluctuations in the preparation process, the uniformity of the via hole can be effectively guaranteed, thereby avoiding defects such as watermarks caused by poor via hole uniformity.

[0252] (8) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the sixth insulating layer, as shown in FIG16A and FIG16B , where FIG16B is a plan view schematic diagram of the fourth conductive layer in FIG16A . In an exemplary embodiment, the fourth conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0253] In an exemplary embodiment, the fourth conductive layer of each circuit unit includes at least: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a seventh connection electrode 57, an eighth connection electrode 58 and a ninth connection electrode 59.

[0254] In an exemplary embodiment, the first connection electrode 51 may be shaped like a zigzag line with a main portion extending along the second direction Y. The first end of the first connection electrode 51 is connected to the first region of the second active layer via a third via hole V3. The second end of the first connection electrode 51 extends along the second direction Y and is connected to the first electrode plate 31 via a thirteenth via hole V13. In an exemplary embodiment, because the first electrode plate 31 also serves as the gate electrode of the third transistor T3, the first connection electrode 51 causes the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 31 to have the same potential, forming a first node N1 of the pixel driving circuit.

[0255] In an exemplary embodiment, since the orthographic projection of the first active segment 12A of the second active layer 12 on the substrate at least partially overlaps with the orthographic projection of the first scan signal line 21 on the substrate, the first connecting electrode 51 causes the first active segment 12A to have the potential of the first node N1, and the first active segment 12A and the first scan signal line 21 form a holding capacitor Cb.

[0256] In an exemplary embodiment, the second connection electrode 52 may be in an "L" shape. A first end of the second connection electrode 52 is connected to the second region of the first active layer via a second via hole V2. A second end of the second connection electrode 52 is connected to the second region of the third active layer (also the first region of the sixth active layer) via a fifth via hole V5. The portion between the first and second ends of the second connection electrode 52 is connected to the second region of the second active layer via a fourth via hole V4. In an exemplary embodiment, the second connection electrode 52 causes the second electrodes of the first transistor T1, the second transistor T2, the third transistor T3, and the first electrode of the sixth transistor T6 to have the same potential, forming a third node N3 of the pixel driving circuit.

[0257] In an exemplary embodiment, the third connection electrode 53 may be in a block shape (e.g., a rectangular shape) and is connected to the first region of the fourth active layer through a sixth via hole V6. In an exemplary embodiment, the third connection electrode 53 may serve as a first electrode of the fourth transistor T4 and is configured to be connected to a subsequently formed data signal line.

[0258] In an exemplary embodiment, the shape of the fourth connection electrode 54 can be a broken line with the main portion extending along the second direction Y. The first end of the fourth connection electrode 54 is connected to the first area of ​​the fifth active layer through the seventh via V7. The second end of the fourth connection electrode 54 extends in the opposite direction of the second direction Y and is connected to the second electrode plate 32 through the fourteenth via V14, thereby achieving the same potential for the first electrode of the fifth transistor T5 in the circuit unit and the second electrode plate 32 of the storage capacitor.

[0259] In an exemplary embodiment, a power connection block 54 - 1 is provided on the fourth connection electrode 54 . The power connection block 54 - 1 is provided on a side of the second end of the fourth connection electrode 54 away from the first end. The power connection block 54 - 1 is configured to be connected to a first power line formed subsequently.

[0260] In an exemplary embodiment, in at least one circuit unit, the fourth connection electrode 54 and the power connection block 54 - 1 may be connected to each other in an integral structure.

[0261] In an exemplary embodiment, the fourth connection electrodes 54 in some adjacent circuit cells in a cell row can be interconnected and integrated. This ensures that the first electrode of the fifth transistor T5 and the second plate 32 of the storage capacitor in the adjacent circuit cells have the same potential, which helps improve the uniformity of the panel, avoid display defects on the display substrate, and ensure the display quality of the display substrate. For example, the fourth connection electrode 54 in the N-1 column is interconnected with the fourth connection electrode 54 in the N column, the fourth connection electrode 54 in the N+1 column is interconnected with the fourth connection electrode 54 in the N+2 column, and the fourth connection electrode 54 in the N+3 column is interconnected with the fourth connection electrode 54 in the N+4 column. In an exemplary embodiment, the integrated fourth connection electrodes 54 and power connection blocks 54-1 in adjacent circuit cells can form a "Y" shape, with the fourth connection electrode 54 disposed between adjacent circuit cells and two power connection blocks 54-1 disposed in each of the two circuit cells.

[0262] In an exemplary embodiment, the fifth connection electrode 55 may be shaped like a zigzag line with a main portion extending along the second direction Y. A first end of the fifth connection electrode 55 is connected to the second region of the fifth active layer via an eighth via hole V8, and a second end of the fifth connection electrode 55 is connected to the second region of the eighth active layer via a twelfth via hole V12. In an exemplary embodiment, because the second region of the fifth active layer serves as both the first region of the third active layer and the second region of the fourth active layer, the fifth connection electrode 55 causes the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8 to have the same potential, thereby forming a second node N2 of the pixel driving circuit.

[0263] In an exemplary embodiment, the sixth connection electrode 56 may be in a block shape (e.g., a rectangle) and is connected to the second region of the sixth active layer (also the second region of the seventh active layer) via a ninth via hole V9. In an exemplary embodiment, the sixth connection electrode 56 may simultaneously serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. The sixth connection electrode 56 is configured to be connected to an anode connection electrode formed subsequently.

[0264] In an exemplary embodiment, the shape of the seventh connection electrode 57 can be a strip shape with the main portion extending along the second direction Y, the first end of the seventh connection electrode 57 is connected to the first region of the first active layer through the first via hole V1, and the second end of the seventh connection electrode 57 is connected to the first initial signal line 41 through the fifteenth via hole V15, thereby enabling the first initial signal line 41 to write the first initial signal into the first electrode of the first transistor T1.

[0265] In an exemplary embodiment, the shape of the eighth connection electrode 58 can be a strip shape with a main portion extending along the first direction X, the first end of the eighth connection electrode 58 is connected to the first region of the seventh active layer through the tenth via V10, and the second end of the eighth connection electrode 58 is connected to the second initial signal line 42 through the sixteenth via V16, thereby enabling the second initial signal line 42 to write the second initial signal into the first electrode of the seventh transistor T7.

[0266] In an exemplary embodiment, the shape of the ninth connection electrode 59 can be an "L" shape, the first end of the ninth connection electrode 59 is connected to the first region of the eighth active layer through the eleventh via V11, and the second end of the ninth connection electrode 59 is connected to the third initial signal line 43 through the seventeenth via V17, thereby enabling the third initial signal line 43 to write the third initial signal into the first electrode of the eighth transistor T8.

[0267] In an exemplary embodiment, the ninth connecting electrodes 59 in some adjacent circuit units within a unit row may be interconnected as an integrated structure. This ensures that the first electrodes of the eighth transistors T8 in adjacent circuit units have the same potential, which helps improve the uniformity of the panel, avoids display defects on the display substrate, and ensures the display quality of the display substrate. For example, the ninth connecting electrode 59 in the N-1th column is interconnected with the ninth connecting electrode 59 in the Nth column, the ninth connecting electrode 59 in the N+1th column is interconnected with the ninth connecting electrode 59 in the N+2th column, and the ninth connecting electrode 59 in the N+3th column is interconnected with the ninth connecting electrode 59 in the N+4th column. In an exemplary embodiment, the integrated ninth connecting electrodes 59 in adjacent circuit units may be U-shaped.

[0268] In an exemplary embodiment, the fourth conductive layers of adjacent cell columns may be mirror-symmetric with respect to the column boundary. For example, the fourth conductive layer of the Nth column and the fourth conductive layer of the N+1th column may be mirror-symmetric with respect to the column boundary, the fourth conductive layer of the N+1th column and the fourth conductive layer of the N+2th column may be mirror-symmetric with respect to the column boundary, and the fourth conductive layer of the N+2th column and the fourth conductive layer of the N+3th column may be mirror-symmetric with respect to the column boundary. In an exemplary embodiment, the shapes of the fourth conductive layers in multiple cell rows may be substantially the same.

[0269] Subsequent processes may include forming a first power line and a data signal line. In one exemplary embodiment, the process of forming the first power line and the data signal line may include sequentially forming a first planar layer, a fifth conductive layer (SD2), and a second planar layer, wherein the fifth conductive layer includes at least a first power line and a data signal line, the first power line being connected to the power connection block 54-1 of the fourth connection electrode 54 through a via, and the data signal line being connected to the third connection electrode 53 through a via, so that the first power line writes the first power signal to the fifth transistor T5 and the second electrode plate 32 of the storage capacitor, and the data signal line 72 is connected to the first electrode of the fourth transistor T4, so that the data signal line 72 can write the data signal to the first electrode of the fourth transistor T4. In another exemplary embodiment, the process of forming the first power line and the data signal line may include: sequentially forming a first flat layer, a fifth conductive layer (SD2), a second flat layer, a sixth conductive layer (SD3) and a third flat layer, the fifth conductive layer includes at least an eleventh connecting electrode and a twelfth connecting electrode, the sixth conductive layer includes at least a first power line and a data signal line, the first power line is connected to the power connection block 54-1 of the fourth connecting electrode 54 through the eleventh connecting electrode, and the data signal line is connected to the third connecting electrode 53 through the twelfth connecting electrode, which will not be repeated here.

[0270] At this point, the driving circuit layer is prepared on the substrate. In a plane parallel to the display substrate, the driving circuit layer may include multiple circuit units, each circuit unit may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, a third scanning signal line, a fourth scanning signal line, a light-emitting signal line, a first initial signal line, a second initial signal line, a third initial signal line, a first power line, and a data signal line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving circuit layer may include at least a shielding layer, a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a sixth insulating layer, and a fourth conductive layer sequentially arranged on the substrate. The blocking layer may include at least a blocking electrode, the first semiconductor layer may include at least the active layers of the first transistor and the third to eighth transistors, the first conductive layer may include at least the first scanning signal line, the second scanning signal line, the third scanning signal line, the light-emitting signal line and the first plate of the storage capacitor, the second conductive layer may include at least the blocking line and the second plate of the storage capacitor, the second semiconductor layer may include at least the active layer of the second transistor, the third conductive layer may include at least the first initial signal line, the second initial signal line, the third initial signal line and the fourth scanning signal line, and the fourth conductive layer may include at least multiple connecting electrodes.

[0271] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-Si).

[0272] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may have a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may have a single layer, multiple layers, or a composite layer.

[0273] In an exemplary embodiment, the pixel driving circuits in two adjacent circuit units in a unit row may be substantially mirror-symmetrical with respect to a column boundary. For example, the pixel driving circuit in the Nth column and the pixel driving circuit in the N+1th column may be mirror-symmetrical with respect to the column boundary. For another example, the pixel driving circuit in the N+1th column and the pixel driving circuit in the N+2th column may be mirror-symmetrical with respect to the column boundary.

[0274] In an exemplary embodiment, the pixel driving circuits in two adjacent circuit units can be substantially mirror-symmetrical with respect to the column dividing line and can include any one or more of the following: the shielding layer in two adjacent circuit units in a unit row can be mirror-symmetrical with respect to the column dividing line, the first semiconductor layer in two adjacent circuit units in a unit row can be mirror-symmetrical with respect to the column dividing line, the first conductive layer in two adjacent circuit units in a unit row can be mirror-symmetrical with respect to the column dividing line, the second conductive layer in two adjacent circuit units in a unit row can be mirror-symmetrical with respect to the column dividing line, the second semiconductor layer in two adjacent circuit units in a unit row can be mirror-symmetrical with respect to the column dividing line, the third conductive layer in two adjacent circuit units in a unit row can be mirror-symmetrical with respect to the column dividing line, and the fourth conductive layer in two adjacent circuit units in a unit row can be mirror-symmetrical with respect to the column dividing line.

[0275] In an exemplary embodiment, after the driving circuit layer is prepared, the process may further include first preparing a light emitting structure layer on the driving circuit layer, and then preparing an encapsulation structure layer on the light emitting structure layer, which will not be described in detail here.

[0276] Figure 17 is a schematic diagram illustrating another embodiment of the present disclosure showing the positional relationship between the first blocking connecting strip and the third source electrode. As shown in Figure 17 , in at least one circuit unit, the orthographic projection of the third source region 13-1 of the third active layer on the substrate can be within the orthographic projection of the first blocking connecting strip 61 on the substrate. The first blocking connecting strip 61 can serve as a connecting strip in the present disclosure.

[0277] In an exemplary embodiment, in at least one circuit unit, the shape of the third source region 13-1 may be a strip shape extending along the first direction X, and may have at least a first active edge 19-1 and a second active edge 19-2. The shapes of the first active edge 19-1 and the second active edge 19-2 may be straight lines or broken lines extending along the first direction X. The first active edge 19-1 may be located on one side of the third source region 13-1 in the opposite direction of the second direction Y, and the second active edge 19-2 may be located on one side of the third source region 13-1 in the second direction Y. The first active edge 19-1 and the second active edge 19-2 may serve as active edges of the present disclosure.

[0278] In an exemplary embodiment, in at least one circuit unit, the shape of the first shielding connecting strip 61 can be a strip shape extending along the first direction X, and can have at least a first shielding edge 61-1 and a second shielding edge 61-2. The shapes of the first shielding edge 61-1 and the second shielding edge 61-2 can be straight lines or broken lines extending along the first direction X. The first shielding edge 61-1 can be located on the side of the first shielding connecting strip 61 in the opposite direction of the second direction Y, and the second shielding edge 61-2 can be located on the side of the first shielding connecting strip 61 in the second direction Y. The first shielding edge 61-1 and the second shielding edge 61-2 can serve as the connecting strip edges of the present disclosure.

[0279] In an exemplary embodiment, in at least one circuit unit, a first distance L1 is provided between the first active edge 19 - 1 and the first blocking edge 61 - 1 . The first distance L1 may be greater than or equal to 0.5 μm.

[0280] In an exemplary embodiment, the first distance L1 is a dimension in the second direction Y. The first distance L1 may be an average distance between the first active edge 19 - 1 and the first blocking edge 61 - 1 , or may be a minimum distance between the first active edge 19 - 1 and the first blocking edge 61 - 1 , or may be a maximum distance between the first active edge 19 - 1 and the first blocking edge 61 - 1 .

[0281] In an exemplary embodiment, in at least one circuit unit, a second distance L2 is provided between the second active edge 19 - 2 and the second blocking edge 61 - 2 . The second distance L2 may be greater than or equal to 0.5 μm.

[0282] In an exemplary embodiment, the second distance L2 is a dimension in the second direction Y. The second distance L2 may be an average distance between the second active edge 19 - 2 and the second blocking edge 61 - 2 , or may be a minimum distance between the second active edge 19 - 2 and the second blocking edge 61 - 2 , or may be a maximum distance between the second active edge 19 - 2 and the second blocking edge 61 - 2 .

[0283] The present invention discloses that the first blocking connecting strip is set to completely include the third source region, and the distance between the edge of the third source region and the edge of the first blocking connecting strip is greater than or equal to 0.5μm. Even if the position of the blocking layer and the first semiconductor layer changes due to fluctuations in the manufacturing process, the consistency of the capacitance at the semiconductor node position in each circuit unit can be effectively guaranteed, thereby avoiding display uniformity and horizontal stripes caused by capacitance differences, and improving the display effect and display quality.

[0284] Figure 18 is a schematic diagram illustrating another embodiment of the present disclosure showing the positional relationship between the first plate connecting bar and the third source electrode. As shown in Figure 18 , in at least one circuit unit, the orthographic projection of the third source region 13-1 of the third active layer on the substrate does not overlap with the orthographic projection of the first plate connecting bar 35 on the substrate. Therefore, the first plate connecting bar 35 can serve as a connecting bar in the present disclosure.

[0285] In an exemplary embodiment, in at least one circuit unit, the third source region 13 - 1 may be in the shape of a strip extending along the first direction X, and may have at least a source region edge 19 - 0 on one side close to the first electrode connecting bar 35 , and the source region edge 19 - 0 may serve as an active edge of the present disclosure.

[0286] In an exemplary embodiment, in at least one circuit unit, the first plate connecting bar 35 may be in the shape of a bar extending along the first direction X, and may have at least a plate edge 35-0 close to one side of the third source region 13-1. The plate edge 35-0 may serve as the connecting bar edge of the present disclosure.

[0287] In an exemplary embodiment, in at least one circuit unit, a separation distance L0 may be provided between the source region edge 19 - 0 and the plate edge 35 - 0 . The separation distance L0 may be greater than or equal to 0.5 μm.

[0288] In an exemplary embodiment, the separation distance L0 is a dimension in the second direction Y. The separation distance L0 may be an average distance between the source region edge 19 - 0 and the plate edge 35 - 0 , or may be a minimum distance between the source region edge 19 - 0 and the plate edge 35 - 0 , or may be a maximum distance between the source region edge 19 - 0 and the plate edge 35 - 0 .

[0289] The present disclosure arranges that the third source region and the first electrode connecting strip do not overlap, and the distance between the edge of the third source region and the edge of the first electrode connecting strip is greater than or equal to 0.5 μm. Even if the position of the first semiconductor layer and the second conductive layer changes due to fluctuations in the manufacturing process, the consistency of the capacitance at the semiconductor node position in each circuit unit can be effectively guaranteed, thereby avoiding display uniformity and horizontal stripes caused by capacitance differences, and improving display effect and display quality.

[0290] In an exemplary embodiment, the structures of Figures 7, 8, 17, and 18 can be arranged in a display substrate in any combination. For example, in one display substrate, the orthographic projection of the third source region on the substrate is within the range of the orthographic projection of the first blocking connecting strip on the substrate, and the orthographic projection of the third source region on the substrate is within the range of the orthographic projection of the first board-level connecting strip on the substrate. For another example, in another display substrate, the orthographic projection of the third source region on the substrate does not overlap with the orthographic projection of the first blocking connecting strip on the substrate, and the orthographic projection of the third source region on the substrate does not overlap with the orthographic projection of the first board-level connecting strip on the substrate. This disclosure is not limited here.

[0291] The display substrate provided by the exemplary embodiment of the present disclosure, by setting the positional relationship between the third active layer and the first blocking connecting strip, and the third active layer and the first board-level connecting strip, can effectively ensure the consistency of the capacitance at the semiconductor node position in each circuit unit even if the film layer position changes due to fluctuations in the preparation process, thereby avoiding display uniformity and horizontal stripes caused by capacitance differences, and improving the display effect and display quality.

[0292] The disclosed display substrate, by setting the positional relationship between the second active layer and the first scanning signal line, can effectively ensure the consistency of capacitance in each circuit unit even if the film layer position changes due to fluctuations in the manufacturing process, thereby avoiding display uniformity and horizontal stripes caused by capacitance differences, and improving display effects and display quality.

[0293] The present disclosure shows that a corresponding pad is arranged below the position where the fourth conductive layer of the substrate overlaps the third conductive layer through a via, so that the orthographic projection of the via on the substrate is within the range of the orthographic projection of the pad on the substrate. Even if the position of the conductive layer or the via changes due to fluctuations in the preparation process, the uniformity of the via can be effectively guaranteed, avoiding watermarks and other defects caused by poor uniformity of the via.

[0294] The preparation process disclosed in the present invention is well compatible with existing preparation processes, is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield rate.

[0295] The structure and preparation process shown above in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0296] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0297] The present disclosure also provides a method for preparing a display substrate to produce the display substrate provided in the above embodiment. In an exemplary embodiment, the display substrate includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns. The preparation method may include:

[0298] A pixel driving circuit and at least one connecting strip are formed in at least one circuit unit. The pixel driving circuit includes at least a second transistor serving as a compensation transistor, a third transistor serving as a driving transistor, and a fourth transistor serving as a data writing transistor. The second transistor includes at least a second active layer, the third transistor includes at least a third active layer, and the fourth transistor includes at least a fourth active layer. The third active layer includes at least a third source region, a third drain region, and a third channel region located between the third source region and the third drain region. The third source region is connected to the fourth active layer, and the third drain region is connected to the second active layer. The third source region is shaped like a strip extending along a cell row direction, and the third source region has at least one active edge extending along the cell row direction. The connecting strip is shaped like a strip extending along the cell row direction, and has at least one connecting strip edge extending along the cell row direction. The distance between the at least one active edge and the at least one connecting strip edge is greater than or equal to 0.5 μm, where the distance is a dimension in the cell column direction.

[0299] The present disclosure further provides a display device including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the embodiments of the present invention are not limited thereto.

[0300] While the embodiments disclosed herein are as described above, it should be noted that the above embodiments are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns. At least one circuit unit includes a pixel driving circuit and at least one connection bar. The pixel driving circuit includes at least a second transistor as a compensation transistor, a third transistor as a driving transistor, and a fourth transistor as a data writing transistor; The second transistor at least includes a second active layer, the third transistor at least includes a third active layer, the fourth transistor at least includes a fourth active layer. The third active layer at least includes a third source region, a third drain region, and a third channel region located between the third source region and the third drain region. The third source region is connected to the fourth active layer, and the third drain region is connected to the second active layer; The shape of the third source region is strip-shaped extending along the unit row direction, and the third source region has at least one active edge extending along the unit row direction; the shape of the connection bar is strip-shaped extending along the unit row direction, and the connection bar has at least one connection bar edge extending along the unit row direction; the distance between at least one active edge and at least one connection bar edge is greater than or equal to 0.5 μm, and the distance is the dimension in the unit column direction.

2. The display substrate according to claim 1, wherein, In at least one circuit unit, the pixel driving circuit further includes a shielding electrode, and the positive projection of the third channel region on the display substrate plane is within the range of the positive projection of the shielding electrode on the display substrate plane; the at least one connection bar includes a first shielding connection bar, and the first shielding connection bar is disposed between the shielding electrodes of two adjacent circuit units in the unit row direction and is respectively connected to the two shielding electrodes.

3. The display substrate according to claim 2, wherein, In at least one circuit unit, the positive projection of the third source region on the display substrate plane is within the range of the positive projection of the first shielding connection bar on the display substrate plane.

4. The display substrate according to claim 3, wherein, In at least one circuit unit, the at least one active edge includes a first active edge and a second active edge respectively located on two sides of the third source region in the unit column direction, and the at least one connection bar edge includes a first shielding edge and a second shielding edge respectively located on two sides of the first shielding connection bar in the unit column direction; the distance between the first shielding edge and the first active edge is greater than or equal to 0.5 μm, and the distance between the second shielding edge and the second active edge is greater than or equal to 0.5 μm.

5. The display substrate according to claim 2, wherein, In at least one circuit unit, the positive projection of the third source region on the display substrate plane and the positive projection of the first shielding connection bar on the display substrate plane do not overlap.

6. The display substrate according to claim 5, wherein, In at least one circuit unit, the at least one active edge at least includes the source region edge of the third source region on the side close to the first shielding connection bar, and the at least one connection bar edge at least includes the shielding edge of the first shielding connection bar on the side close to the third source region; the distance between the shielding edge and the source region edge is greater than or equal to 0.5 μm.

7. The display substrate according to claim 1, wherein, In at least one circuit unit, the pixel driving circuit further includes a storage capacitor. The storage capacitor includes at least a first electrode plate and a second electrode plate. The orthographic projection of the second electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the first electrode plate on the display substrate plane. The orthographic projection of the third channel region on the display substrate plane is within the range of the orthographic projection of the first electrode plate on the display substrate plane. The at least one connection strip includes a first electrode plate connection strip. The first electrode plate connection strip is disposed between the second electrode plates of two adjacent circuit units in the unit row direction and is respectively connected to the two second electrode plates.

8. The display substrate according to claim 7, wherein, In at least one circuit unit, the orthographic projection of the third source region on the display substrate plane is within the range of the orthographic projection of the first electrode plate connection strip on the display substrate plane.

9. The display substrate according to claim 8, wherein, In at least one circuit unit, the at least one active edge includes a first active edge and a second active edge respectively located on two sides of the third source region in the unit column direction. The at least one connection strip edge includes a first electrode plate edge and a second electrode plate edge respectively located on two sides of the first electrode plate connection strip in the unit column direction. The distance between the first electrode plate edge and the first active edge is greater than or equal to 0.5 μm, and the distance between the second electrode plate edge and the second active edge is greater than or equal to 0.5 μm.

10. The display substrate according to claim 7, wherein, In at least one circuit unit, the orthographic projection of the third source region on the display substrate plane does not overlap with the orthographic projection of the first electrode plate connection strip on the display substrate plane.

11. The display substrate according to claim 10, wherein, In at least one circuit unit, the at least one active edge at least includes the source region edge of the third source region close to the first electrode plate connection strip. The at least one connection strip edge at least includes the electrode plate edge of the first electrode plate connection strip close to the third source region. The distance between the electrode plate edge and the source region edge is greater than or equal to 0.5 μm.

12. The display substrate according to any one of claims 1 to 11, wherein, In at least one circuit unit, the gate electrode of the fourth transistor is connected to the first scan signal line. The shape of the first scan signal line is a straight line or a broken line extending along the unit row direction. The orthographic projection of the second active layer on the display substrate plane at least partially overlaps with the orthographic projection of the first scan signal line on the display substrate plane.

13. The display substrate according to claim 12, wherein, In at least one circuit unit, the second active layer at least includes a second source region, a second drain region, a first active segment, and a second active segment. The second source region is connected to the gate electrode of the third transistor. The second drain region is connected to the third drain region of the third active layer. The first end of the first active segment is connected to the second source region. After the second end of the first active segment extends along the unit row direction, it is connected to the first end of the second active segment. After the second end of the second active segment extends along the unit column direction, it is connected to the second drain region. The orthographic projection of the first active segment on the display substrate plane at least partially overlaps with the orthographic projection of the first scan signal line on the display substrate plane.

14. The display substrate according to claim 13, wherein, The first scan signal line includes a first scan edge and a second scan edge respectively located on both sides of the first scan signal line unit in the column direction; in at least one circuit unit, in the overlapping region of the first active segment and the first scan signal line, the orthographic projections of the first scan edge and the second scan edge on the display substrate plane are within the range of the orthographic projection of the first active segment on the display substrate plane.

15. The display substrate according to claim 14, wherein, The first active segment includes a third active edge and a fourth active edge respectively located on both sides of the first active segment unit in the column direction; in at least one circuit unit, in the overlapping region of the first active segment and the first scan signal line, the distance between the third active edge and the first scan edge is greater than or equal to 0.5 μm, and the distance between the fourth active edge and the second scan edge is greater than or equal to 0.5 μm.

16. The display substrate according to any one of claims 1 to 11, wherein, The pixel driving circuit further includes a first transistor as a first initialization transistor, a fifth transistor as a first light-emitting control transistor, a sixth transistor as a second light-emitting control transistor, a seventh transistor as a second initialization transistor, an eighth transistor as a third initialization transistor, at least one connection electrode, and at least one spacer. At least one connection electrode is connected to the active layer of at least one transistor through an active via, and the orthographic projection of at least one active via on the display substrate plane is within the range of the orthographic projection of at least one spacer on the display substrate plane.

17. The display substrate according to claim 16, wherein, The distance between the edge of the active via and the edge of the spacer is greater than or equal to 0.5 μm.

18. The display substrate according to claim 16, wherein, In a direction perpendicular to the display substrate, the display substrate at least includes an occlusion layer, a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, and a fourth conductive layer sequentially arranged on a substrate. The at least one spacer is disposed in the occlusion layer, and the at least one connection electrode is disposed in the fourth conductive layer.

19. The display substrate according to claim 18, wherein, In at least one circuit unit, the occlusion layer further includes an occlusion electrode, and the distance between the edge of at least one active via and the edge of the occlusion electrode is greater than or equal to 0.5 μm.

20. The display substrate according to claim 19, wherein In at least one circuit unit, the occlusion layer further includes a second occlusion connection bar. The shape of the second occlusion connection bar is a strip shape extending along the unit column direction, and is respectively connected to the occlusion electrode and at least one spacer. The distance between the edge of at least one active via and the second occlusion connection bar is greater than or equal to 0.5 μm.

21. A display device, including the display substrate according to any one of claims 1 to 20.

22. A method for manufacturing a display substrate, the display substrate including a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, the manufacturing method including: Forming a pixel driving circuit and at least one connection bar in at least one circuit unit, the pixel driving circuit at least including a second transistor as a compensation transistor, a third transistor as a driving transistor, and a fourth transistor as a data writing transistor; The second transistor includes at least a second active layer, the third transistor includes at least a third active layer, the fourth transistor includes at least a fourth active layer, the third active layer includes at least a third source region, a third drain region, and a third channel region located between the third source region and the third drain region, the third source region is connected to the fourth active layer, and the third drain region is connected to the second active layer; The shape of the third source region is a strip shape extending along the unit row direction, and the third source region has at least one active edge extending along the unit row direction; the shape of the connection bar is a strip shape extending along the unit row direction, and the connection bar has at least one connection bar edge extending along the unit row direction; the distance between at least one active edge and at least one connection bar edge is greater than or equal to 0.5 μm, and the distance is the dimension in the unit column direction.

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