Display substrate and manufacturing method therefor, and display device

Abstract

A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises multiple sub-pixels, at least one sub-pixel comprises a pixel driving circuit and a data signal line connected to the pixel driving circuit, the pixel driving circuit at least comprises a storage capacitor and a first transistor, the storage capacitor at least comprises a first electrode plate and a second electrode plate, and the first transistor is connected to the data signal line. In a direction perpendicular to the display substrate, the display substrate comprises a first conductive layer arranged on a base and a semiconductor layer arranged on the side of the first conductive layer away from the base, the first conductive layer at least comprises data signal lines, and the semiconductor layer at least comprises first active layers of first transistors. In at least one sub-pixel, the first active layer is connected to the data signal line by means of a via hole.

Description

Display substrate and manufacturing method thereof, and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on October 25, 2023, with application number 202311393797.1 and invention name “Display substrate, preparation method thereof, and display device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, display devices using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] On the one hand, the present disclosure provides a display substrate, comprising multiple repeating units, at least one repeating unit comprising multiple sub-pixels, at least one sub-pixel comprising a pixel driving circuit and a data signal line connected to the pixel driving circuit, the pixel driving circuit comprising at least a storage capacitor and a first transistor, the storage capacitor comprising at least a first electrode plate and a second electrode plate, the orthographic projection of the first electrode plate on the plane of the display substrate and the orthographic projection of the second electrode plate on the plane of the display substrate at least partially overlapping; in a direction perpendicular to the display substrate, the display substrate comprises a first conductive layer arranged on a base and a semiconductor layer arranged on a side of the first conductive layer away from the base, the first conductive layer comprising at least the data signal line, the semiconductor layer comprising at least the second electrode plate and the first active layer of the first transistor; in at least one sub-pixel, the first active layer is connected to the data signal line through a via.

[0007] In an exemplary embodiment, in at least one sub-pixel, the first active layer and the second electrode plate are connected to each other as an integral structure.

[0008] In an exemplary embodiment, the pixel driving circuit further includes a second transistor, which is connected to the first power line through a power connection line; the first conductive layer further includes the first power line, and the semiconductor layer further includes the power connection line and a second active layer of the second transistor; in at least one sub-pixel, the second active layer is connected to the power connection line, and the power connection line is connected to the first power line through a via.

[0009] In an exemplary embodiment, in at least one sub-pixel, the second active layer and the power connection line are connected to each other as an integral structure.

[0010] In an exemplary embodiment, the first power line is in the shape of a straight line or a broken line extending along the second direction, and the power connection line is in the shape of a straight line or a broken line extending along the first direction, and the first direction and the second direction intersect; two adjacent first power lines in the first direction are connected to the same power connection line to form a mesh structure.

[0011] In an exemplary embodiment, the first power line is in the shape of a straight line or a broken line extending along the second direction, the power connection line is in the shape of a straight line or a broken line extending along the first direction, the first direction and the second direction intersect; two adjacent first power lines in the first direction are connected to different power connection lines.

[0012] In an exemplary embodiment, the display substrate further includes a second conductive layer disposed on a side of the semiconductor layer away from the base, the second conductive layer at least including a second gate electrode of the second transistor, and the second gate electrode is connected to the second plate via a gate connecting electrode.

[0013] In an exemplary embodiment, the display substrate further includes a third conductive layer disposed on a side of the second conductive layer away from the substrate, the third conductive layer including at least the gate connecting electrode; the gate connecting electrode is respectively connected to the second gate electrode and the second electrode plate through the same via hole, or the gate connecting electrode is connected to the second gate electrode through one via hole and to the second electrode plate through another via hole.

[0014] In an exemplary embodiment, the third conductive layer further includes a first electrode and an active connection electrode, the first electrode and the active connection electrode are connected to each other as an integral structure, and the active connection electrode is connected to the second active layer through an active via.

[0015] In an exemplary embodiment, the second active layer is connected to the first electrode plate through a plate-level via, or the second active layer is connected to a transparent connecting electrode through a plate-level via, and the transparent connecting electrode and the first electrode plate are an integrated structure connected to each other.

[0016] In an exemplary embodiment, in at least one sub-pixel, an orthographic projection of the active via on the substrate at least partially overlaps with an orthographic projection of the board-level via on the substrate.

[0017] In an exemplary embodiment, the pixel driving circuit further includes a third transistor, the third transistor including at least a third active layer, the first conductive layer further includes a compensation signal line, and the compensation signal line is connected to the third active layer of multiple sub-pixels in the repeating unit through the semiconductor layer.

[0018] In an exemplary embodiment, the semiconductor layer further includes a compensation connection line, the compensation signal line is connected to the compensation connection line through a via hole, and the compensation connection line is connected to the third active layer of a plurality of sub-pixels in a repeating unit.

[0019] In an exemplary embodiment, in at least one repeating unit, the compensation connection line and the third active layers of a plurality of sub-pixels are connected to each other as an integral structure.

[0020] In an exemplary embodiment, in at least one repeating unit, the compensation signal line is in a straight line or a broken line shape extending along the second direction, and the compensation signal line is arranged in the middle position of the repeating unit in the first direction, and the first direction and the second direction intersect.

[0021] In an exemplary embodiment, in at least one repeating unit, the plurality of sub-pixels include at least a red sub-pixel, a white sub-pixel, a green sub-pixel, and a blue sub-pixel arranged in sequence along the first direction, the red sub-pixel includes a red data signal line, the green sub-pixel includes a green data signal line, the blue sub-pixel includes a blue data signal line, the red data signal line is arranged on one side of the compensation signal line in the first direction, and the green data signal line and the blue data signal line are arranged on the other side of the compensation signal line in the first direction.

[0022] In an exemplary embodiment, in at least one repeating unit, a first gap is provided between the pixel driving circuit of the red sub-pixel and the pixel driving circuit of the white sub-pixel, a second gap is provided between the pixel driving circuit of the green sub-pixel and the pixel driving circuit of the blue sub-pixel, the red data signal line is provided in the first gap, and the green data signal line and the blue data signal line are provided in the second gap.

[0023] In an exemplary embodiment, the first electrode plate is disposed in the first conductive layer.

[0024] In an exemplary embodiment, the display substrate further includes a transparent conductive layer disposed between the base and the first conductive layer, and the first electrode is disposed in the transparent conductive layer.

[0025] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0026] In yet another aspect, the present disclosure further provides a manufacturing method, wherein the display substrate includes a plurality of repeating units, at least one repeating unit includes a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and a data signal line connected to the pixel driving circuit, the pixel driving circuit includes at least a storage capacitor and a first transistor, the storage capacitor includes at least a first electrode plate and a second electrode plate, an orthographic projection of the first electrode plate on a plane of the display substrate at least partially overlaps with an orthographic projection of the second electrode plate on the plane of the display substrate; the manufacturing method comprises:

[0027] forming a first conductive layer on a substrate, wherein the first conductive layer at least includes the data signal line;

[0028] A semiconductor layer is formed on the first conductive layer, the semiconductor layer including at least the second electrode and the first active layer of the first transistor; in at least one sub-pixel, the first active layer is connected to the data signal line through a via hole.

[0029] Other aspects will become apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0031] FIG1 is a schematic structural diagram of a display device;

[0032] FIG2 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0033] FIG3 is an equivalent circuit diagram of a pixel driving circuit in a repeating unit according to an exemplary embodiment of the present disclosure;

[0034] FIG4 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0035] FIG5A is a cross-sectional view taken along line AA in FIG4 ;

[0036] FIG5B is a cross-sectional view taken along line BB in FIG4 ;

[0037] FIG6 is a schematic diagram of a display substrate after forming a first conductive layer pattern according to the present disclosure;

[0038] FIG7 is a schematic diagram of a display substrate after forming a first insulating layer pattern according to the present disclosure;

[0039] 8A and 8B are schematic diagrams of a display substrate after a semiconductor layer pattern is formed according to the present disclosure;

[0040] 9A and 9B are schematic diagrams of a display substrate after forming a second conductive layer pattern according to the present disclosure;

[0041] FIG10 is a schematic diagram of a display substrate after forming a third insulating layer and a planar layer pattern according to the present disclosure;

[0042] 11A and 11B are schematic diagrams of a display substrate after a third conductive layer pattern is formed thereon according to the present disclosure;

[0043] FIG12 is a schematic diagram of a display substrate after forming a pixel definition layer pattern according to the present disclosure;

[0044] FIG13 is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure;

[0045] FIG14 is a schematic diagram of another display substrate according to the present disclosure after a transparent conductive layer and a first conductive layer pattern are formed;

[0046] FIG15 is a schematic diagram of another display substrate after forming a first insulating layer pattern according to the present disclosure;

[0047] 16A and 16B are schematic diagrams of another display substrate after semiconductor layer patterns are formed according to the present disclosure;

[0048] 17A and 17B are schematic diagrams of another display substrate after forming a second conductive layer pattern according to the present disclosure;

[0049] FIG18 is a schematic diagram of another display substrate after forming a third insulating layer and a planar layer pattern according to the present disclosure;

[0050] 19A and 19B are schematic diagrams of another display substrate after forming a third conductive layer pattern according to the present disclosure;

[0051] FIG. 20 is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure.

[0052] Explanation of the accompanying drawings: 10—substrate; 11—first electrode; 12—second electrode; 13—transparent connecting electrode; 14—shielding electrode; 21—first power line; 22—data signal line; 23—compensation signal line; 31—first active layer; 32—second active layer; 33—third active layer; 34—power connection line; 35—compensation connection line; 40—scanning signal line; 41—first gate electrode; 42—second gate electrode; 43—third gate electrode; 50—first electrode; 51—eleventh connecting electrode; 52—twelfth connecting electrode; 61—first insulating layer; 62—second insulating layer; 63—third insulating layer; 64—flat layer. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other in any way.

[0054] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0055] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0056] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0057] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0058] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0059] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0060] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0061] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0062] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0063] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0064] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0065] Figure 1 is a schematic diagram of the structure of a display device. As shown in Figure 1, the OLED display device may include a timing controller, a data driver, a scan driver, and a pixel array. The timing controller is respectively connected to the data driver and the scan driver. The data driver is respectively connected to multiple data signal lines (D1 to Dn). The scan driver is respectively connected to multiple scan signal lines (S1 to Sm). The pixel array may include multiple sub-pixels Pxij. Each sub-pixel Pxij may be connected to a corresponding data signal line and a corresponding scan signal line. i and j may be natural numbers. At least one sub-pixel Pxij may include at least a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to the scan signal line and the data signal line. The light-emitting unit may include at least a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the circuit unit. Sub-pixel Pxij may refer to a sub-pixel whose pixel driving circuit is connected to the i-th scan signal line and the j-th data signal line. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, and may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver. The data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn in units of pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured in the form of a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next level circuit under the control of a clock signal, where m can be a natural number. In an exemplary embodiment, the pixel array can be provided on a display substrate.

[0066] An exemplary embodiment of the present disclosure provides a display substrate, comprising a plurality of repeating units, at least one repeating unit comprising a plurality of sub-pixels, at least one sub-pixel comprising a pixel driving circuit and a data signal line connected to the pixel driving circuit, the pixel driving circuit comprising at least a storage capacitor and a first transistor, the storage capacitor comprising at least a first electrode plate and a second electrode plate, the orthographic projection of the first electrode plate on the plane of the display substrate at least partially overlapping the orthographic projection of the second electrode plate on the plane of the display substrate; in a direction perpendicular to the display substrate, the display substrate comprises a first conductive layer disposed on a base and a semiconductor layer disposed on a side of the first conductive layer away from the base, the first conductive layer comprising at least the data signal line, the semiconductor layer comprising at least the second electrode plate and the first active layer of the first transistor; in at least one sub-pixel, the first active layer is connected to the data signal line through a via.

[0067] In an exemplary embodiment, the pixel driving circuit further includes a second transistor, which is connected to the first power line through a power connection line; the first conductive layer further includes the first power line, and the semiconductor layer further includes the power connection line and a second active layer of the second transistor; in at least one sub-pixel, the second active layer is connected to the power connection line, and the power connection line is connected to the first power line through a via.

[0068] In an exemplary embodiment, the pixel driving circuit further includes a third transistor, the third transistor including at least a third active layer, the first conductive layer further includes a compensation signal line, and the compensation signal line is connected to the third active layer of multiple sub-pixels in the repeating unit through the semiconductor layer.

[0069] In an exemplary embodiment, the semiconductor layer further includes a compensation connection line, the compensation signal line is connected to the compensation connection line through a via hole, and the compensation connection line is connected to the third active layer of a plurality of sub-pixels in a repeating unit.

[0070] The display substrate of the present disclosure is described below by way of some exemplary embodiments.

[0071] Figure 2 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure. As shown in Figure 2, in an exemplary embodiment, the display substrate may include multiple repeating units 100 in a direction parallel to the display substrate. At least one repeating unit 100 may include multiple sub-pixels arranged sequentially along a first direction X. In an exemplary embodiment, a repeating unit is a basic unit that constitutes the display substrate. The display substrate is formed by repeatedly and continuously arranging the repeating units along at least one direction. In other words, the display substrate is composed of multiple repeating units.

[0072] In an exemplary embodiment, one repeating unit 100 may include four sub-pixels, and the four sub-pixels may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, a third sub-pixel P3 emitting a third color light, and a fourth sub-pixel P4 emitting a fourth color light.

[0073] In an exemplary embodiment, in at least one repeating unit 100, the second subpixel P2 may be arranged on one side of the first subpixel P1 in the first direction X, the third subpixel P3 may be arranged on one side of the second subpixel P2 in the first direction X, and the fourth subpixel P4 may be arranged on one side of the third subpixel P3 in the first direction X. The plurality of subpixels arranged sequentially along the first direction X may be referred to as pixel rows, and the plurality of subpixels arranged sequentially along the second direction Y may be referred to as pixel columns. The plurality of pixel rows and the plurality of pixel columns constitute an array-arranged pixel array, and the first direction X intersects the second direction Y.

[0074] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a white sub-pixel (W) that emits white light, the third sub-pixel P3 may be a green sub-pixel (G) that emits green light, and the fourth sub-pixel P4 may be a blue sub-pixel (B) that emits blue light. In some possible embodiments, the arrangement of RWGB can be adjusted according to actual needs and is not specifically limited in this disclosure.

[0075] In one exemplary embodiment, the display substrate may include at least a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate, in a direction perpendicular to the display substrate. In at least one repeating unit, the driving circuit layer may include multiple circuit units, each of which may include at least a pixel driving circuit. The pixel driving circuits are connected to scan signal lines and data signal lines, respectively. The pixel driving circuits are configured to receive data voltages transmitted by the data signal lines under the control of the scan signal lines and output a corresponding current to the light-emitting device. The light-emitting structure layer may include multiple light-emitting units, each of which may include at least a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the circuit unit for the sub-pixel in which it is located. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0076] In another exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least a driving circuit layer disposed on a base, a color filter structure layer disposed on a side of the driving circuit layer remote from the base, and a light-emitting structure layer disposed on a side of the color filter structure layer remote from the base. In at least one repeating unit, the color filter structure layer may include multiple color filter units, each of which may include at least a color filter layer configured to cause corresponding sub-pixels to emit light of a desired color.

[0077] In exemplary embodiments, the circuit unit referred to in this disclosure refers to an area divided by pixel driver circuits. The color filter unit referred to in this disclosure refers to an area divided by color filter layers. The light-emitting unit referred to in this disclosure refers to an area divided by light-emitting devices. The orthographic projections of the circuit unit, the color filter layer, and the light-emitting unit on the substrate may correspond or may not correspond.

[0078] In the exemplary embodiment of the present disclosure, the positions of the circuit unit's orthographic projection on the substrate, the color filter layer's orthographic projection on the substrate, and the light-emitting unit's orthographic projection on the substrate are one-to-one corresponding, and the circuit unit, the color filter unit, and the light-emitting unit constitute sub-pixels. Therefore, in the following content, sub-pixels are uniformly used to refer to the circuit unit, the color filter unit, and the light-emitting unit.

[0079] In an exemplary embodiment, a plurality of sub-pixels sequentially arranged along a first direction X may be referred to as pixel rows, and a plurality of sub-pixels sequentially arranged along a second direction Y may be referred to as pixel columns. The plurality of pixel rows and the plurality of pixel columns constitute an array-arranged pixel array, and the first direction X and the second direction Y intersect.

[0080] In an exemplary embodiment, the first direction X may be a horizontal direction, the second direction Y may be a vertical direction, and the first direction X and the second direction Y may be perpendicular to each other.

[0081] Figure 3 is an equivalent circuit diagram of a pixel driving circuit in a repeating unit according to an exemplary embodiment of the present disclosure. As shown in Figure 3, at least one repeating unit may include four pixel driving circuits, which may be arranged in a square and may have a 3T1C structure.

[0082] In an exemplary embodiment, at least one pixel driving circuit may include three transistors (a first transistor T1, a second transistor T2, and a third transistor T3) and a storage capacitor C, and the pixel driving circuit is respectively connected to the scanning signal line 40, the first power line 21, the data signal line 22, and the compensation signal line 23.

[0083] In an exemplary embodiment, each pixel driving circuit may include a first node N1 and a second node N2. The first node N1 is connected to the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the first end of the storage capacitor C, respectively. The second node N2 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the second end of the storage capacitor C, respectively.

[0084] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1 , a second end of the storage capacitor C is connected to the second node N2 , and the storage capacitor C is used to store the potential of the gate electrode of the second transistor T2 .

[0085] In an exemplary embodiment, the first transistor T1 is a switching transistor, the second transistor T2 is a driving transistor, and the third transistor T3 is a compensation transistor.

[0086] In the exemplary embodiment, a gate electrode of the first transistor T1 is connected to the scan signal line 40, a first electrode of the first transistor T1 is connected to the data signal line 22, and a second electrode of the first transistor T1 is connected to the first node N1. When a turn-on signal is applied to the scan signal line 40, the first transistor T1 inputs a data signal of the data signal line 22 to the gate electrode of the second transistor T2.

[0087] In an exemplary embodiment, a gate electrode of the second transistor T2 is connected to the first node N1, a first electrode of the second transistor T2 is connected to the first power line 21, and a second electrode of the second transistor T2 is connected to the second node N2. The second transistor T2 generates a corresponding current at its second electrode under the control of the data signal received at its gate electrode.

[0088] In an exemplary embodiment, a gate electrode of the third transistor T3 is connected to the scan signal line 40, a first electrode of the third transistor T3 is connected to the compensation signal line 23, and a second electrode of the third transistor T3 is connected to the second node N2. When a turn-on signal is applied to the scan signal line 40, the third transistor T3 extracts the threshold voltage Vth and mobility of the second transistor T2 in response to the compensation timing to compensate for the threshold voltage Vth.

[0089] In an exemplary embodiment, in the pixel driving circuit of at least one sub-pixel, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected to the same scan signal line 40 .

[0090] In an exemplary embodiment, in the plurality of pixel driving circuits of at least one pixel row, the gate electrodes of the plurality of first transistors T1 and the gate electrodes of the plurality of third transistors T3 are connected to the same scan signal line 40 .

[0091] In an exemplary embodiment, in the four pixel driving circuits of at least one repeating unit, the gate electrodes of the four first transistors T1 and the gate electrodes of the four third transistors T3 are connected to the same scan signal line 40 .

[0092] In an exemplary embodiment, the light-emitting device EL may be an OLED, including a stacked first electrode, an organic light-emitting layer, and a second electrode, or a QLED, including a stacked first electrode, a quantum dot light-emitting layer, and a second electrode. The first electrode of the light-emitting device EL is connected to the second node N2, and the second electrode of the light-emitting device EL is connected to the second power supply line VSS. The light-emitting device EL emits light of corresponding brightness in response to the current flowing through the second electrode of the second transistor T2. In an exemplary embodiment, the first electrode may be an anode, and the second electrode may be a cathode; alternatively, the first electrode may be a cathode, and the second electrode may be an anode.

[0093] In an exemplary embodiment, the signal of the first power line 21 is a continuously provided high-level signal, and the signal of the second power line VSS is a continuously provided low-level signal.

[0094] In an exemplary embodiment, the first to third transistors T1 to T3 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first to third transistors T1 to T3 may include P-type transistors and N-type transistors.

[0095] In an exemplary embodiment, the first transistor T1 to the third transistor T3 may be low-temperature polysilicon transistors, or oxide transistors, or both. The active layer of the low-temperature polysilicon transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating low-temperature polysilicon transistors and oxide transistors on a display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, can leverage the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0096] Figure 4 is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a repeating unit (four subpixels) of a bottom-emission display substrate. As shown in Figure 4 , at least one repeating unit may include a first subpixel P1, a second subpixel P2, a third subpixel P3, and a fourth subpixel P4 arranged along a first direction X, parallel to the display substrate. Each subpixel includes a pixel driver circuit.

[0097] In an exemplary embodiment, the first subpixel P1 may be a red subpixel, the second subpixel P2 may be a white subpixel, the third subpixel P3 may be a green subpixel, and the fourth subpixel P4 may be a blue subpixel.

[0098] In an exemplary embodiment, at least one repeating unit may include two first power lines 21 , four data signal lines 22 , one compensation signal line 23 , and one scan signal line 40 , all of which are connected to pixel driving circuits in four sub-pixels.

[0099] In an exemplary embodiment, the shape of the scan signal line 40 can be a straight line or a broken line extending along the first direction X, the shape of the first power line 21, the data signal line 22 and the compensation signal line 23 can be a straight line or a broken line extending along the second direction Y, the compensation signal line 23 can be arranged in the middle position of the repeating unit in the first direction X, the two first power lines 21 can be respectively arranged on both sides of the repeating unit in the first direction X, the four data signal lines 22 and the one compensation signal line 23 can be arranged between the two first power lines 21, two of the four data signal lines 22 can be located between the compensation signal line 23 and one first power line 21, and the other two of the four data signal lines 22 can be located between the compensation signal line 23 and another first power line 21.

[0100] In an exemplary embodiment, the four data signal lines 22 may include at least a red data signal line located at a red sub-pixel, a green data signal line located at a green sub-pixel, and a blue data signal line located at a blue sub-pixel. The red data signal line may be arranged on one side of the compensation signal line 23 in the first direction X, and the green data signal line and the blue data signal line may be arranged on the other side of the compensation signal line 23 in the first direction X.

[0101] In an exemplary embodiment, a first sub-pixel P1 is formed between one first power line 21 and one data signal line 22 adjacent to the first direction X, a second sub-pixel P2 is formed between the compensation signal line 23 and one data signal line 22 adjacent to the direction opposite to the first direction X, a third sub-pixel P3 is formed between the compensation signal line 23 and one data signal line 22 adjacent to the first direction X, and a fourth sub-pixel P4 is formed between another first power line 21 and one data signal line 22 adjacent to the direction opposite to the first direction X.

[0102] In an exemplary embodiment, in at least one repeating unit, a first gap is provided between the pixel driving circuit of the red sub-pixel and the pixel driving circuit of the white sub-pixel, a second gap is provided between the pixel driving circuit of the green sub-pixel and the pixel driving circuit of the blue sub-pixel, a red data signal line is provided in the first gap, and a green data signal line and a blue data signal line are provided in the second gap.

[0103] In an exemplary embodiment, the pixel driving circuit of at least one of the four sub-pixels in the repeating unit may include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor. The first transistor T1, the second transistor T2, and the third transistor T3 may each include an active layer, a gate electrode, a first electrode, and a second electrode. The storage capacitor may include at least a first electrode plate 11 and a second electrode plate 12, wherein the orthographic projection of the first electrode plate 11 on the display substrate plane at least partially overlaps the orthographic projection of the second electrode plate 12 on the display substrate plane.

[0104] In an exemplary embodiment, in at least one repeating unit, the scan signal line 40 is respectively connected to the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 in each sub-pixel, the data signal line 22 is connected to the first electrode of the first transistor T1 in each sub-pixel, the compensation signal line 23 is connected to the first electrode of the third transistor T3 in each sub-pixel, the first power line 21 is connected to the first electrode of the second transistor T2 in each sub-pixel, the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the second plate 12 of the storage capacitor in each sub-pixel are interconnected, and the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first plate 11 of the storage capacitor in each sub-pixel are interconnected.

[0105] In an exemplary embodiment, at least one repeating unit may further include a power connection line 34, through which the first power line 21 is connected to the first electrode of the second transistor T2 in each sub-pixel. The power connection line 34 may be in the shape of a straight line or a broken line extending along the first direction X. The power connection line 34 is connected to two adjacent first power lines 21 in the first direction X. Thus, the power connection lines 34 extending along the first direction X and the first power lines 21 extending along the second direction Y form a mesh structure within the repeating unit.

[0106] In an exemplary embodiment, a power connection line 34 may be provided across the first to fourth subpixels P1 to P4. The first end of the power connection line 34 is connected to the first power line 21 in the first subpixel P1, and the second end of the power connection line 34 is connected to the first power line 21 in the fourth subpixel P4. The region between the first and second ends is connected to the first electrodes of the second transistors T2 in each of the four subpixels. In this way, one first power line 21 can provide power signals to the pixel drive circuits of four subpixels via one power connection line 34, forming a two-to-four first power line structure.

[0107] In an exemplary embodiment, at least one repeating unit may further include a compensation connection line 35, through which the compensation signal line 23 is connected to the first electrode of the third transistor T3 in each sub-pixel. The compensation connection line 35 may be in the shape of a straight line or a broken line extending along the first direction X. The compensation connection line 35 is connected to the compensation signal line 23 on one hand, and is connected to the first electrodes of the third transistors T3 in each of the four sub-pixels on the other hand.

[0108] In an exemplary embodiment, the compensation connection line 35 may be arranged across the first to fourth sub-pixels P1 to P4. The middle portion of the compensation connection line 35 in the first direction X is connected to the compensation signal line 23, and both sides of the compensation connection line 35 in the first direction X are connected to the first electrodes of the third transistors T3 in the four sub-pixels. In this way, one compensation signal line 23 can provide compensation signals to the pixel drive circuits of the four sub-pixels, forming a one-to-four compensation signal line structure.

[0109] FIG5A is a cross-sectional view taken along line AA in FIG4 , and FIG5B is a cross-sectional view taken along line BB in FIG4 . As shown in FIG4 , FIG5A and FIG5B , in a direction perpendicular to the display substrate, the display substrate may include at least a driving circuit layer disposed on a substrate 10 and a light emitting structure layer disposed on a side of the driving circuit layer away from the substrate. In an exemplary embodiment,

[0110] The driving circuit layer may include a first conductive layer arranged on the substrate 10, a first insulating layer 61 arranged on the side of the first conductive layer away from the substrate, a semiconductor layer arranged on the side of the first insulating layer 61 away from the substrate, a second insulating layer 62 arranged on the side of the semiconductor layer away from the substrate, a second conductive layer arranged on the side of the second insulating layer 62 away from the substrate, and a third insulating layer 63 and a flat layer 64 arranged on the side of the second conductive layer away from the substrate. The light-emitting structure layer may include at least a third conductive layer arranged on the side of the driving circuit layer away from the substrate.

[0111] In an exemplary embodiment, the first conductive layer may include at least a first electrode plate 11 and a data signal line 22, and the semiconductor layer may include at least a second electrode plate 12 and a first active layer 31 of the first transistor T1. In at least one sub-pixel, the first region of the first active layer 31 is connected to the data signal line 22 through a via.

[0112] In an exemplary embodiment, in at least one sub-pixel, the first active layer 31 and the second electrode plate 12 may be an integral structure connected to each other.

[0113] In an exemplary embodiment, the first conductive layer may further include a first power line 21, and the semiconductor layer may further include a power connection line 34 and a second active layer 32 of the second transistor T2. In at least one sub-pixel, the first region of the second active layer 32 is connected to the power connection line 34, which is connected to the first power line 21 through a via.

[0114] In an exemplary embodiment, in at least one sub-pixel, the second active layer 32 and the power connection line 34 may be an integral structure connected to each other.

[0115] In an exemplary embodiment, the first conductive layer may further include a compensation connection line 35 , the semiconductor layer may further include a third active layer 33 of the third transistor T3 , and the compensation signal line 35 may be connected to the third active layer 33 of the plurality of sub-pixels in the repeating unit through the semiconductor layer.

[0116] In an exemplary embodiment, the semiconductor layer may further include a compensation connection line 35. In at least one repeating unit, the compensation connection line 35 is connected to the first region of the third active layer 33 of the plurality of sub-pixels in the repeating unit and is connected to the compensation signal line 23 through a via.

[0117] In an exemplary embodiment, in at least one repeating unit, the compensation connection line 35 and the third active layers 33 of the plurality of sub-pixels may be connected to each other in an integral structure.

[0118] In an exemplary embodiment, the second conductive layer may include at least a second gate electrode 42 of the second transistor. The second gate electrode 42 is connected to the second electrode plate 12 via a twelfth connecting electrode 52 . The twelfth connecting electrode 52 may serve as a gate connecting electrode of the present disclosure.

[0119] In an exemplary embodiment, the third conductive layer may include at least a twelfth connecting electrode 52. In one embodiment, the twelfth connecting electrode 52 may be connected to the second gate electrode 42 located in the second conductive layer through a via hole, and connected to the second electrode plate 12 located in the semiconductor layer through another via hole. In another embodiment, the twelfth connecting electrode 52 may be connected to the second gate electrode 42 located in the second conductive layer and the second electrode plate 12 located in the semiconductor layer through the same via hole.

[0120] In an exemplary embodiment, the third conductive layer may further include a first electrode 50 and an eleventh connecting electrode 51. The first electrode 50 and the eleventh connecting electrode 51 may be an integral structure connected to each other. The eleventh connecting electrode 51 is connected to the second region of the second active layer 32 through the eleventh via V11. The eleventh connecting electrode 51 may serve as an active connecting electrode of the present disclosure, and the eleventh via V11 may serve as an active via of the present disclosure.

[0121] In an exemplary embodiment, the second region of the second active layer 32 is connected to the first electrode plate 11 through a second via hole V2 , and the second via hole V2 may serve as a board-level via hole of the present disclosure.

[0122] In an exemplary embodiment, in at least one sub-pixel, an orthographic projection of the eleventh via hole V11 (active via hole) on the substrate at least partially overlaps with an orthographic projection of the second via hole V2 (board-level via hole) on the substrate.

[0123] In an exemplary embodiment, the orthographic projection area of ​​the eleventh via hole V11 on the substrate may be larger than the orthographic projection area of ​​the second via hole V2 on the substrate, which may improve connection reliability.

[0124] In exemplary embodiments, the first electrode may be an anode of the light emitting structure layer, or the first electrode may be a cathode of the light emitting structure layer.

[0125] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes the deposition of film layers, coating of photoresist on the film layers, mask exposure, development, etching, stripping of photoresist and other processes for metal materials, inorganic materials or transparent conductive materials, and includes the coating of organic materials, mask exposure and development and other processes for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0126] In an exemplary embodiment, taking an example in which a repeating unit includes four sub-pixels (a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4), the preparation process of the display substrate in this exemplary embodiment may include the following operations.

[0127] (11) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first conductive film on a substrate, patterning the first conductive film through a patterning process, and forming the first conductive layer pattern on the substrate, as shown in FIG6 . In an exemplary embodiment, the first conductive layer may be referred to as a shielding metal (SHL) layer.

[0128] In an exemplary embodiment, the first conductive layer pattern in each sub-pixel in the repeating unit may include at least the first plate 11 of the storage capacitor.

[0129] In an exemplary embodiment, the shape of the first electrode plate 11 can be rectangular, the corners of the rectangle can be chamfered, the edges of the rectangle can be broken lines, the first electrode plate 11 can be set in the middle area of ​​the sub-pixel in the second direction Y, the first electrode plate 11 can serve as a electrode plate of the storage capacitor, and the first electrode plate 11 is configured to form a storage capacitor with the second electrode plate formed subsequently.

[0130] In an exemplary embodiment, the areas of the first plates 11 in the sub-pixels in the repeating unit may be substantially the same, so that the capacities of the storage capacitors in the sub-pixels are substantially the same.

[0131] In an exemplary embodiment, the first conductive layer of the repeating unit may further include two first power lines 21 , four data signal lines 22 , and one compensation signal line 23 .

[0132] In an exemplary embodiment, the first power line 21, the data signal line 22, and the compensation signal line 23 may be in the shape of a straight line or a zigzag line, with the main portion extending along the second direction Y. The compensation signal line 23 may be located in the middle of the repeating unit in the first direction X and may be disposed between the second subpixel P2 and the third subpixel P3. Two first power lines 21 may be located on either side of the compensation signal line 23 in the first direction X, one for the first subpixel P1 and the other for the fourth subpixel P4. Four data signal lines 22 may be provided in each subpixel, two of the four data signal lines 22 may be located between one first power line 21 and the compensation signal line 23, and the other two of the four data signal lines 22 may be located between another first power line 21 and the compensation signal line 23.

[0133] In an exemplary embodiment, the two first power lines 21 may include a first first power line 21-1 and a second first power line 21-2 sequentially arranged along the first direction X, and the four data signal lines 22 may include a first data signal line 22-1, a third data signal line 22-3, and a fourth data signal line 22-4 sequentially arranged along the first direction X. The first first power line 21-1 and the first data signal line 22-1 may define a first pixel column, the second data signal line 22-2 and the compensation signal line 23 may define a second pixel column, the compensation signal line 23 and the third data signal line 22-3 may define a third pixel column, and the fourth data signal line 22-4 and the second first power line 21-2 may define a fourth pixel column.

[0134] In an exemplary embodiment, the first power line 21 , the data signal line 22 and the compensation signal line 23 may be zigzag lines of unequal widths. Using zigzag lines of varying widths not only facilitates the layout of the pixel structure but also reduces parasitic capacitance.

[0135] In an exemplary embodiment, the orthographic projection of the compensation signal line 23 on the substrate at least partially overlaps with the orthographic projection of the vertical reference line on the substrate, the positions and shapes of the two first power lines 21 can be substantially mirror-symmetrical with respect to the vertical reference line, the positions and shapes of the two data signal lines 22 located on the side opposite to the first direction X of the compensation signal line 23 and the positions and shapes of the two data signal lines 22 located on the side of the compensation signal line 23 in the first direction X can be substantially mirror-symmetrical with respect to the vertical reference line, and the positions and shapes of the four first electrodes 11 in the repeating unit can be substantially mirror-symmetrical with respect to the vertical reference line, which can be a straight line extending along the second direction Y and bisecting the repeating unit in the first direction X.

[0136] (12) Forming a first insulating layer pattern. In an exemplary embodiment, forming the first insulating layer pattern may include: depositing a first insulating film on the substrate on which the aforementioned pattern is formed, patterning the first insulating film through a patterning process to form a first insulating layer pattern covering the first conductive layer, wherein a plurality of vias are provided on the first insulating layer, as shown in FIG. 7 .

[0137] In an exemplary embodiment, the plurality of via holes of each sub-pixel in the repeating unit includes at least a first via hole V1 , a second via hole V2 , and a third via hole V3 .

[0138] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate at least partially overlaps with the orthographic projection of the data signal line 22 on the substrate. The first insulating layer within the first via hole V1 is etched away, exposing the surface of the data signal line 22. The first via hole V1 is configured to connect the first region of the subsequently formed first active layer to the data signal line 22 through the via hole. In an exemplary embodiment, the second via hole V2 can serve as a board-level via of the present disclosure.

[0139] In an exemplary embodiment, the orthographic projections of the second via V2 and the third via V3 on the substrate at least partially overlap with the orthographic projection of the first electrode plate 11 on the substrate, the first insulating layer within the second via V2 and the third via V3 is etched away to expose the surface of the first electrode plate 11, the second via V2 is configured to connect the second region of the subsequently formed second active layer to the first electrode plate 11 through the via, and the third via V3 is configured to connect the second region of the subsequently formed third active layer to the first electrode plate 11 through the via.

[0140] In an exemplary embodiment, the first insulating layer in the repeating unit may further include a fourth via hole V4 and a fifth via hole V5 .

[0141] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate at least partially overlaps with the orthographic projection of the first power line 21 on the substrate. The first insulating layer within the fourth via hole V4 is etched away, exposing the surface of the first power line 21. The fourth via hole V4 is configured to connect a subsequently formed power connection line to the first power line 21 through the via hole. In an exemplary embodiment, the fourth via hole V4 may be provided in each of the first subpixel P1 and the fourth subpixel P4.

[0142] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate at least partially overlaps with the orthographic projection of the compensation signal line 23 on the substrate. The first insulating layer within the fifth via hole V5 is etched away, exposing the surface of the compensation signal line 23. The fifth via hole V5 is configured to allow a subsequently formed compensation connection line to be connected to the compensation signal line 23 through the via hole. In an exemplary embodiment, the fifth via hole V5 may be provided between the second subpixel P2 and the third subpixel P3.

[0143] In an exemplary embodiment, the plurality of via holes on the first insulating layer within the repeating unit may be substantially mirror-symmetrical with respect to a vertical reference line.

[0144] (13) Forming a semiconductor layer pattern. In an exemplary embodiment, forming the semiconductor layer pattern may include: depositing a semiconductor thin film on the substrate on which the aforementioned pattern is formed, and patterning the semiconductor thin film through a patterning process to form a semiconductor layer pattern disposed on the first insulating layer, as shown in FIG8A and FIG8B , where FIG8B is a plan view schematic diagram of the semiconductor layer in FIG8A .

[0145] In an exemplary embodiment, the semiconductor layer pattern in each sub-pixel in the repeating unit may include at least a first active layer 31 , a second active layer 32 , a third active layer 33 , a power connection line 34 , a compensation connection line 35 , and a second plate 12 .

[0146] In an exemplary embodiment, the shape of the second electrode plate 12 can be rectangular, and the orthographic projection of the second electrode plate 12 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 11 on the substrate. The second electrode plate 12 is configured to form another electrode plate of the storage capacitor, and the first electrode plate 11 and the second electrode plate 12 constitute the storage capacitor of the pixel driving circuit.

[0147] In an exemplary embodiment, in one repeating unit, the overlapping area of ​​the orthographic projection of the second electrode 12 on the substrate and the orthographic projection of the first electrode 11 on the substrate in each sub-pixel may be substantially the same, so that the capacity of the storage capacitor in each sub-pixel is substantially the same.

[0148] In an exemplary embodiment, the shape of the power connection line 34 can be a straight line or a broken line with the main part extending along the first direction X. The power connection line 34 can be arranged on the side of the second electrode 12 in the opposite direction of the second direction Y, and the power connection line 34 is connected to the first power line 21 through the fourth via V4.

[0149] In an exemplary embodiment, in one repeating unit, the orthographic projection of the power connection line 34 on the substrate at least partially overlaps with the orthographic projection of the four data signal lines 22 on the substrate, and the orthographic projection of the power connection line 34 on the substrate at least partially overlaps with the orthographic projection of the compensation signal line 23 on the substrate.

[0150] In an exemplary embodiment, the power connection line 34 can serve as a horizontal connection line, and the two first power lines 21 in a repeating unit are both connected to the power connection line 34, so that the power connection line 34 extending along the first direction X and the first power line 21 extending along the second direction Y form a mesh structure on the display substrate for transmitting the first power signal. This can not only effectively reduce the resistance of the first power line and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0151] In an exemplary embodiment, the shape of the compensation connection line 35 can be a straight line or a broken line with the main part extending along the first direction X. The compensation connection line 35 can be arranged on one side of the second electrode plate 12 in the second direction Y, and the compensation connection line 35 is connected to the compensation signal line 23 through the fifth via V5.

[0152] In an exemplary embodiment, in one repeating unit, the orthographic projection of the compensation connection line 35 on the substrate at least partially overlaps with the orthographic projection of the four data signal lines 22 on the substrate, and the orthographic projection of the compensation connection line 35 on the substrate does not overlap with the orthographic projection of the first power line 21 on the substrate.

[0153] In an exemplary embodiment, the first active layer 31 can serve as the active layer of the first transistor T1, the second active layer 32 can serve as the active layer of the second transistor T2, and the third active layer 33 can serve as the active layer of the third transistor T3. The first active layer 31 and the third active layer 33 can be arranged between the compensation connection line 35 and the second electrode plate 12, and the second active layer 32 can be arranged between the power connection line 34 and the second electrode plate 12.

[0154] In example embodiments, each of the first active layer 31 , the second active layer 32 , and the third active layer 33 may include a channel region and first and second regions located at both sides of the channel region.

[0155] In an exemplary embodiment, the first active layer 31 may be in the shape of a strip extending along the second direction Y and may be disposed on one side of the second electrode plate 12 in the second direction Y. The first region of the first active layer 31 is connected to the data signal line 22 via a first via V1, and the second region of the first active layer 31 is connected to the second electrode plate 12, thereby enabling the data signal line 22 to write a data signal into the first electrode of the first transistor T1. In an exemplary embodiment, the first region of the first active layer 31 in each sub-pixel may be connected to one data signal line 22 via the first via V1, thereby enabling four data signal lines 22 to write data signals into the first electrodes of the four first transistors T1 in a repeating unit.

[0156] In an exemplary embodiment, the four data signal lines 22 may include a first data signal line, a second data signal line, a third data signal line, and a fourth data signal line sequentially arranged along the first direction X. The first data signal line may be located on one side of the first pixel column in the first direction X and connected to the first region of the first active layer in the first subpixel P1. The second data signal line may be located on one side of the second pixel column in the opposite direction of the first direction X and on one side of the first data signal line in the first direction X and connected to the first region of the first active layer in the second subpixel P2. The third data signal line may be located on one side of the third pixel column in the first direction X and connected to the first region of the first active layer in the third subpixel P3. The fourth data signal line may be located on one side of the fourth pixel column in the opposite direction of the first direction X and on one side of the third data signal line in the first direction X and connected to the first region of the first active layer in the fourth subpixel P4.

[0157] In an exemplary embodiment, in one sub-pixel, the first active layer 31 and the second electrode plate 12 may be an integral structure connected to each other.

[0158] In an exemplary embodiment, the second active layer 32 may be in the shape of a strip extending along the second direction Y. The orthographic projection of the second active layer 32 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 11 on the substrate. The orthographic projection of the channel region of the second active layer 32 on the substrate may be located within the orthographic projection of the first electrode plate 11 on the substrate. The first electrode plate 11 may shield the channel region of the second active layer 32, preventing light from affecting the channel and reducing leakage current, thereby preventing the influence of light on transistor characteristics and ensuring the electrical performance of the second transistor T2.

[0159] In the exemplary embodiment, the first region of the second active layer 32 is connected to the power connection line 34, and the second region of the second active layer 32 is connected to the first electrode plate 11 through the second via V2. Since the power connection line 34 is connected to the first power line, the first power line 21 writes the first power signal to the first electrode of the second transistor T2, and the second electrode of the second transistor T2 and the first electrode plate 11 have the same potential.

[0160] In an exemplary embodiment, the two first power lines 21 may include a first first power line and a second first power line. The first first power line may be located on a side of the first pixel column opposite to the first direction X, and the second first power line may be located on a side of the fourth pixel column in the first direction X. Because the first first power line of the first pixel column can simultaneously provide a first power signal to the pixel driving circuits in the first to fourth sub-pixels P1 to P4 via the power connection line 34, and the second first power line of the fourth pixel column can simultaneously provide a first power signal to the pixel driving circuits in the first to fourth sub-pixels P1 to P4 via the power connection line 34, the first power lines 21 in a repeating unit form a two-to-four structure. By designing the first power lines as a two-to-four structure, the display substrate of the present disclosure reduces the number of signal lines and the space occupied, resulting in a simple structure and a reasonable layout, fully utilizing the layout space, improving space utilization, and facilitating improved resolution.

[0161] In an exemplary embodiment, the two first power lines 21 in a repeating unit are substantially mirror-symmetrical with respect to a vertical reference line, and the four second transistors T2 in a repeating unit are substantially mirror-symmetrical with respect to the vertical reference line. This symmetrical structure of the present disclosure can ensure that the voltage drops written by the first power line to the second transistors T2 are substantially the same, thereby ensuring display uniformity.

[0162] In an exemplary embodiment, in one repeating unit, the power connection line 34 and the second active layers 32 in four sub-pixels may be connected to each other in an integral structure.

[0163] In an exemplary embodiment, the shape of the third active layer 33 can be a strip shape extending along the second direction Y, the first area of ​​the third active layer 33 is connected to the compensation connection line 35, and the second area of ​​the third active layer 33 is connected to the first electrode 11 through the third via V3, thereby enabling the compensation signal line 23 to write the compensation signal into the first electrode of the third transistor T3, and at the same time enabling the second electrode of the third transistor T3 to have the same potential as the first electrode 11.

[0164] In an exemplary embodiment, compensation signal line 23 can be located between the second and third pixel columns. Compensation signal line 23 can simultaneously provide compensation signals to the pixel driver circuits in four sub-pixels via compensation connection line 35. Therefore, the four pixel driver circuits in a repeating unit can share a single compensation signal line 23, i.e., the compensation signal lines 23 in a repeating unit form a one-to-four structure. By designing the display substrate as a one-to-four structure, the disclosed display substrate reduces the number of signal lines and space requirements, resulting in a simple structure and a rational layout. This fully utilizes the layout space, improves space efficiency, and facilitates improved resolution.

[0165] In an exemplary embodiment, the compensation connection line 35 may be mirror-symmetrical with respect to the compensation signal line 23 . This symmetrical structure of the present disclosure can ensure that the RC delay of the third transistors T3 in the four sub-pixels when the compensation signal is written is substantially the same, thereby ensuring display uniformity.

[0166] In an exemplary embodiment, in one repeating unit, the compensation connection line 35 and the third active layers 33 in four sub-pixels may be an integrated structure connected to each other.

[0167] In example embodiments, positions of respective patterns in the semiconductor layer within the repeating unit may be substantially mirror-symmetrical with respect to a vertical reference line.

[0168] In an exemplary embodiment, the positions of the respective patterns of the semiconductor layer in the first sub-pixel P1 and the second sub-pixel P2 can be substantially mirror-symmetrical with respect to a pixel reference line, the positions of the respective patterns of the semiconductor layer in the third sub-pixel P3 and the fourth sub-pixel P4 can be substantially mirror-symmetrical with respect to the pixel reference line, the positions of the respective patterns of the semiconductor layer in the first sub-pixel P1 and the fourth sub-pixel P4 can be substantially mirror-symmetrical with respect to the pixel reference line, the positions of the respective patterns of the semiconductor layer in the second sub-pixel P2 and the third sub-pixel P3 can be substantially mirror-symmetrical with respect to the pixel reference line, and the pixel reference line can be a straight line located between adjacent sub-pixels and extending along the second direction Y.

[0169] In exemplary embodiments, the semiconductor layer may be formed of a metal oxide, such as an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, an oxide containing indium, gallium, and zinc, etc. The semiconductor layer may be a single layer, a double layer, or a multilayer.

[0170] (14) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a second insulating film and a second conductive film on the substrate having the aforementioned pattern formed thereon, patterning the second insulating film and the second conductive film through a patterning process to form a second insulating layer disposed on the semiconductor layer, and a second conductive layer pattern disposed on the second insulating layer, as shown in FIG9A and FIG9B , where FIG9B is a plan view schematic diagram of the second conductive layer in FIG9A . In an exemplary embodiment, the second conductive layer may be referred to as a gate metal (GT) layer.

[0171] In an exemplary embodiment, the second conductive layer pattern of each sub-pixel in the repeating unit may include at least the scan signal line 40 and the second gate electrode 42 .

[0172] In an exemplary embodiment, the shape of the scanning signal line 40 can be a straight line or a broken line with the main portion extending along the first direction X. The scanning signal line 40 can be located on one side of the second electrode plate 12 in the second direction Y. The scanning signal line 40 is configured to simultaneously control the conduction or disconnection of all the first transistors T1 and all the third transistors T3 in the four sub-pixels of the repeating unit.

[0173] In an exemplary embodiment, the orthographic projection of the scan signal line 40 on the substrate at least partially overlaps with the orthographic projection of the first active layer in each subpixel on the substrate, and the scan signal line 40 in the overlapping area can serve as the gate electrode of the first transistor T1.

[0174] In an exemplary embodiment, the orthographic projection of the scan signal line 40 on the substrate at least partially overlaps with the orthographic projection of the third active layer in each subpixel on the substrate, and the scan signal line 40 in the overlapping area can serve as the gate electrode of the third transistor T3.

[0175] In an exemplary embodiment, in one sub-pixel, one scan signal line 40 may serve as both the first gate electrode and the third gate electrode, so that the scan signal line 40 may control the on / off switching of the first transistor T1 and the third transistor T3 in one sub-pixel.

[0176] In an exemplary embodiment, in one repeating unit, one scan signal line 40 simultaneously serves as four first gate electrodes and four third transistors in four sub-pixels, so that the scan signal line 40 can control the on / off switching of the four first transistors T1 and the four third transistors T3 in one repeating unit.

[0177] In an exemplary embodiment, in one pixel row, one scan signal line 40 simultaneously serves as all first gate electrodes and all third transistors in a plurality of sub-pixels, so that the scan signal line 40 can control the on or off of all first transistors T1 and all third transistors T3 in one pixel row.

[0178] In an exemplary embodiment, the second gate electrode 42 may be in the shape of a strip with a main portion extending along the first direction X. The second gate electrode 42 may serve as the gate electrode of the second transistor T2. On one hand, the orthographic projection of the second gate electrode 42 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate. On the other hand, the orthographic projection of the second gate electrode 42 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 12 on the substrate.

[0179] In example embodiments, positions of respective patterns in the second conductive layer within the repeating unit may be substantially mirror-symmetrical with respect to a vertical reference line.

[0180] In an exemplary embodiment, the positions of the respective patterns of the second conductive layer in the first subpixel P1 and the second subpixel P2 can be substantially mirror-symmetrical with respect to the pixel reference line, the positions of the respective patterns of the second conductive layer in the third subpixel P3 and the fourth subpixel P4 can be substantially mirror-symmetrical with respect to the pixel reference line, the positions of the respective patterns of the second conductive layer in the first subpixel P1 and the fourth subpixel P4 can be substantially mirror-symmetrical with respect to the pixel reference line, and the positions of the respective patterns of the second conductive layer in the second subpixel P2 and the third subpixel P3 can be substantially mirror-symmetrical with respect to the pixel reference line.

[0181] In an exemplary embodiment, after the second insulating film and the second conductive film are patterned, the second insulating layer pattern and the second conductive layer pattern are substantially the same, and the second insulating layer is disposed on a side of the second conductive layer close to the substrate.

[0182] In an exemplary embodiment, this process also includes a conductive treatment. After forming the second conductive layer pattern, the conductive treatment is performed using the second conductive layer as a shield for plasma treatment. The semiconductor layer shielded by the second conductive layer serves as the channel region of the transistor, while the semiconductor layer not shielded by the second conductive layer is processed into a conductive layer, forming a conductive second plate and a conductive source and drain region.

[0183] (15) Forming a third insulating layer and a planar layer pattern. In an exemplary embodiment, forming the third insulating layer and the planar layer pattern may include: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, then coating a planar film, patterning the planar film and the third insulating film through a patterning process to form a third insulating layer covering the second conductive layer and a planar layer pattern disposed on the third insulating layer, wherein a plurality of vias are disposed on the planar layer, as shown in FIG. 10 .

[0184] In an exemplary embodiment, the plurality of via holes in each sub-pixel in the repeating unit includes at least an eleventh via hole V11 and a twelfth via hole V12 .

[0185] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the second region of the second active layer on the substrate. The planar layer and the third insulating layer within the eleventh via hole V11 are etched away, exposing the surface of the second region of the second active layer. The eleventh via hole V11 is configured to connect a subsequently formed second connection electrode to the second region of the second active layer through the via hole. In an exemplary embodiment, the eleventh via hole V11 can serve as the active via hole of the present disclosure.

[0186] In an exemplary embodiment, in at least one sub-pixel, an orthographic projection of the eleventh via hole V11 on the substrate at least partially overlaps with an orthographic projection of the second via hole V2 on the substrate.

[0187] In an exemplary embodiment, the orthographic projection area of ​​the eleventh via hole V11 on the substrate may be larger than the orthographic projection area of ​​the second via hole V2 on the substrate, which may improve connection reliability.

[0188] In an exemplary embodiment, the twelfth via hole V12 may include two sub-holes, one sub-hole having an orthographic projection on the substrate at least partially overlapping with an orthographic projection of the second gate electrode 42 on the substrate, and exposing the surface of the second gate electrode 42, and the other sub-hole having an orthographic projection on the substrate at least partially overlapping with an orthographic projection of the second electrode plate 12 on the substrate, and exposing the surface of the second electrode plate 12. The twelfth via hole V12 is configured to allow a subsequently formed first connection electrode to be simultaneously connected to the second gate electrode 42 and the second electrode plate 12 through the via hole.

[0189] In some possible embodiments, the twelfth via V12 can be a via of a transition structure, including two half holes, one half hole exposing the surface of the second gate electrode 42, and the other half hole exposing the surface of the second electrode plate 12, so that the twelfth via V12 of the transition structure composed of the two half holes simultaneously exposes the second gate electrode 42 and the second electrode plate 12.

[0190] In an exemplary embodiment, this process can use a single patterning process to simultaneously form vias on the third insulating layer and the flat layer. The third insulating layer and the flat layer share a halftone or gray tone mask (MASK) process, effectively reducing the number of patterning processes.

[0191] In an exemplary embodiment, the plurality of via holes on the third insulating layer within the repeating unit may be substantially mirror-symmetrical with respect to a vertical reference line.

[0192] (16) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on the flat layer, as shown in FIG11A and FIG11B , where FIG11B is a planar schematic diagram of the third conductive layer in FIG11A .

[0193] In an exemplary embodiment, the third conductive layer of each sub-pixel in the repeating unit may include at least the first connection electrode 51 , the second connection electrode 52 , and the first electrode 50 .

[0194] In an exemplary embodiment, the first connection electrode 51 may be in the shape of a bar with a main portion extending along the second direction Y. A first end of the first connection electrode 51 is connected to the second region of the second active layer through an eleventh via hole V11, and a second end of the first connection electrode 51 is connected to the first electrode 50. In an exemplary embodiment, the first connection electrode 51 may serve as an active connection electrode of the present disclosure.

[0195] In an exemplary embodiment, the second connection electrode 52 may be in a block shape (e.g., a rectangle). The second connection electrode 52 is connected to both the second gate electrode 42 and the second plate 12 via a twelfth via hole V12. In an exemplary embodiment, because the second plate 12 is connected to the second region of the first active layer, the second connection electrode 52 ensures that the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the second plate 12 of the storage capacitor have the same potential, forming a first node N1 in the pixel driving circuit. In an exemplary embodiment, the second connection electrode 52 may serve as the gate connection electrode of the present disclosure.

[0196] In an exemplary embodiment, the first electrode 50 may be rectangular in shape, and the corners of the rectangle may be chamfered, grooved, or protruded. The edge of the first electrode 50 on the side closest to the second electrode plate 12 is connected to the second end of the first connection electrode 51. Because the second region of the second active layer is connected to the first electrode plate 11 through a via, and the second region of the third active layer is connected to the first electrode plate 11 through a via, the first connection electrode 51 ensures that the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode plate 11 of the storage capacitor have the same potential, forming a second node N2 in the pixel driving circuit.

[0197] In an exemplary embodiment, the first plate 11 has the potential of the second node N2 in the pixel driving circuit, the second plate 12 has the potential of the first node N1 in the pixel driving circuit, and the first plate 11 and the second plate 12 constitute a storage capacitor of the pixel driving circuit.

[0198] In an exemplary embodiment, the first connection electrode 51 and the first electrode 50 may be an integral structure connected to each other.

[0199] In exemplary embodiments, the first electrode 50 may be an anode of the light emitting device, or the first electrode 50 may be a cathode of the light emitting device.

[0200] In an exemplary embodiment, at least one sub-pixel may include a circuit area and a light-transmitting area, the first transistor T1, the second transistor T2, the third transistor T3 and the storage capacitor may be arranged in the circuit area, the first electrode 50 may be arranged in the light-transmitting area, and the orthographic projection of the first electrode 50 on the substrate does not overlap with the orthographic projection of the second electrode plate 12 on the substrate.

[0201] In an exemplary embodiment, the four first electrodes 50 in a repeating unit may be sequentially arranged along the first direction X and respectively connected to the pixel driving circuits of the first subpixel P1, the second subpixel P2, the third subpixel P3, and the fourth subpixel P4. In some possible implementations, the arrangement of the anodes may be adjusted according to actual needs and is not specifically limited in this disclosure.

[0202] In an exemplary embodiment, the third conductive layer may be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0203] In example embodiments, positions of respective patterns in the third conductive layer within the repeating unit may be substantially mirror-symmetrical with respect to a vertical reference line.

[0204] (17) Forming a pixel definition layer. In an exemplary embodiment, forming a pixel definition layer pattern may include: coating a pixel definition film on the substrate having the aforementioned pattern formed thereon, and patterning the pixel definition film through a patterning process to form a pixel definition layer covering the fourth conductive layer, as shown in FIG. 12 .

[0205] In an exemplary embodiment, a pixel opening K is opened on the pixel definition layer of each sub-pixel in the repeating unit, the pixel definition film in the pixel opening K is removed to expose the surface of the first electrode 50, and the orthographic projection of the pixel opening K on the substrate is within the range of the orthographic projection of the first electrode 50 on the substrate.

[0206] In an exemplary embodiment, the shape of the pixel opening K in a plane parallel to the substrate may be similar to that of the first electrode 50 , and the cross-sectional shape of the pixel opening K in a plane perpendicular to the substrate may be rectangular or trapezoidal.

[0207] In exemplary embodiments, the shape of the pixel opening may include any one or more of a triangle, a rectangle, a trapezoid, a parallelogram, a five-frame shape, a six-frame shape, a circle, and an ellipse.

[0208] In an exemplary embodiment, the shapes of the pixel openings of the four sub-pixels may be the same or different, and the areas of the pixel openings of the four sub-pixels may be the same or different.

[0209] In an exemplary embodiment, the shapes and areas of the pixel openings of the four sub-pixels may be different to accommodate the transmittance of different sub-pixel filters, so that the light-emitting devices of the four sub-pixels can emit the same brightness at different currents, thereby maximizing the lifespan of the four sub-pixel light-emitting devices and ensuring the product lifespan.

[0210] In an exemplary embodiment, the pixel definition layer may be made of polyimide, acryl, polyethylene terephthalate, or the like.

[0211] (18) Forming an organic light-emitting layer and a cathode pattern. In an exemplary embodiment, forming the organic light-emitting layer and the cathode pattern may include: first forming an organic light-emitting layer pattern, wherein the organic light-emitting layer is connected to the first electrode 50 through the pixel opening K. Then, forming a second electrode, wherein the second electrode is connected to the organic light-emitting layer.

[0212] In an exemplary embodiment, the organic light-emitting layer may include an emission layer (EML), and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the organic light-emitting layer may be formed using a fine metal mask (FMM) or open mask evaporation, or using an inkjet process.

[0213] (19) Forming a packaging structure layer pattern. In an exemplary embodiment, forming a packaging structure layer pattern may include: first using an open mask to deposit a first inorganic thin film to form a first packaging layer. Subsequently, using an inkjet printing process to inkjet print an organic material on the first packaging layer, and after curing into a film, forming a second packaging layer. Subsequently, using an open mask to deposit a second inorganic thin film to form a third packaging layer, the first packaging layer, the second packaging layer and the third packaging layer constitute a packaging structure layer. The first packaging layer and the third packaging layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiC), silicon carbonitride (SiCN) and silicon oxynitride (SiON), and can be a single layer, a multilayer or a composite layer. The second packaging layer can be made of a resin material to form a laminated structure of inorganic material / organic material / inorganic material. The organic material layer is arranged between the two inorganic material layers to ensure that external water vapor cannot enter the light-emitting structure layer.

[0214] At this point, a drive circuit layer, a light-emitting structure layer disposed on the drive circuit layer, and an encapsulation structure layer disposed on the light-emitting structure layer are prepared on the substrate. In a plane perpendicular to the display substrate, the drive circuit layer may include at least a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, and a planar layer stacked sequentially on the substrate. The light-emitting structure layer may include at least a first electrode, a pixel definition layer, an organic light-emitting layer, and a second electrode. The encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer.

[0215] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si).

[0216] In an exemplary embodiment, the first conductive layer and the second conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The third conductive layer can be made of a transparent conductive material, such as indium tin oxide ITO or indium zinc oxide IZO. The first insulating layer, the second insulating layer and the third insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, a multilayer or a composite layer. The planar layer can be made of an organic material, such as a resin.

[0217] In an exemplary embodiment, the display substrate of this embodiment may include a color filter structure layer, which may be disposed between a third insulating layer and a planar layer. In at least one repeating unit, the color filter structure layer may include multiple color filter units, and at least one color filter unit may include a color filter layer configured to cause the corresponding sub-pixel to emit light of a desired color. In an exemplary embodiment, the display substrate preparation process may include: depositing a third insulating layer on a substrate having the aforementioned pattern formed thereon, then coating a first color filter layer on the third insulating layer, and patterning the first color filter layer using a patterning process to form a first color filter unit. Then, coating a second color filter layer, and patterning the second color filter layer using a patterning process to form a second color filter unit. Then, coating a third color filter layer, and patterning the third color filter layer using a patterning process to form a third color filter unit. Then, coating a planar thin film, and using a patterning process to form an eleventh and twelfth via holes. The planar layer, color filter structure layer, and third insulating layer within the via holes are removed.

[0218] Currently, existing display substrates face complex production processes and high production costs. For example, the manufacturing process for the driver circuit layer in one display substrate requires seven masking steps, resulting in low production efficiency and high production costs, while also impacting product yield.

[0219] The embodiment of the present disclosure provides a display substrate with a bottom emission structure. By arranging structures such as a first power line, a data signal line, and a compensation signal line in a first conductive layer, the first active layer, the second active layer, and the third active layer in the semiconductor layer are connected to the first power line, the data signal line, and the compensation signal line through vias, respectively. This not only reduces the number of conductive layers, but also reduces the patterning process of switching vias and the patterning process of switching conductive layers. As a result, the preparation process of the driving circuit layer only requires five patterning processes, which reduces the number of patterning processes, effectively improves production efficiency, effectively reduces production costs, and maximizes product yield.

[0220] In a display substrate, to reduce the number of patterning processes, a gate metal layer and a semiconductor layer are connected using a transfer via structure consisting of deep and shallow half-holes. This requires the semiconductor layer to be conductively bonded twice, which not only damages the semiconductor layer but also complicates the process and reduces the process yield. The display substrate disclosed herein does not require the use of a transfer via structure or the double conductive bonding of the semiconductor layer. This not only reduces etching damage to the semiconductor layer, but also reduces the number and size of vias, reduces process complexity, and improves process yield.

[0221] The display substrate disclosed herein provides power connection lines on the semiconductor layer. The power connection lines and the first power lines form a mesh structure for transmitting the first power signal. This can not only effectively reduce the resistance of the first power line and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality.

[0222] The disclosed display substrate has a 3T1C one-gate structure, employing a single scan signal line to drive the pixel drive circuit. This scan signal line is connected to the first and third transistors in the pixel drive circuit. By reducing the number of scan signal lines, not only can the structure of the pixel drive circuit be simplified and its footprint reduced, facilitating high-resolution display, but it can also effectively increase the light-transmitting area of ​​the light-transmitting region, improving the spatial proportion of the light-transmitting region and facilitating high-transparency display. Furthermore, because a repeating unit requires only one scan signal line to drive, the number of corresponding gate drive circuits (GOA) and clock signal lines (CLK) can be reduced exponentially, effectively reducing the footprint of the gate drive circuits and clock signal lines, facilitating a narrow bezel and enhancing product advantages.

[0223] The preparation process disclosed in the present invention is well compatible with existing preparation processes, is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield rate.

[0224] Figure 13 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a pixel driver circuit within a repeating unit (four sub-pixels) in a bottom-emission display substrate. As shown in Figure 13 , the main structure of the display substrate of this embodiment is substantially the same as that shown in Figure 5 , except that the storage capacitors in this embodiment are transparent.

[0225] In an exemplary embodiment, the display substrate of this embodiment may further include a transparent conductive layer disposed between the base and the first conductive layer. The first electrode of the storage capacitor may be disposed in the transparent conductive layer, and the second electrode may be disposed in the semiconductor layer.

[0226] In an exemplary embodiment, the transparent conductive layer may further include a transparent connecting electrode, and the transparent connecting electrode and the first electrode plate may be an integrated structure connected to each other.

[0227] In an exemplary embodiment, the second region of the second active layer is connected to the transparent connection electrode through a via hole.

[0228] In an exemplary embodiment, a process of preparing a display substrate according to the exemplary embodiment may include the following operations.

[0229] (21) Forming a transparent conductive layer and a first conductive layer pattern. In an exemplary embodiment, forming the transparent conductive layer and the first conductive layer pattern may include: sequentially depositing a first conductive film and a second conductive film on a substrate, patterning the first conductive film and the second conductive film through a patterning process, and forming the transparent conductive layer and the first conductive layer pattern on the substrate, as shown in FIG14 . In an exemplary embodiment, the transparent conductive layer may be referred to as a first transparent (1ITO) layer, and the first conductive layer may be referred to as a shielding metal (SHL) layer.

[0230] In an exemplary embodiment, the transparent conductive layer pattern in each sub-pixel in the repeating unit may include at least the first plate 11 of the storage capacitor and the transparent connecting electrode 13 , and the first conductive layer of each sub-pixel in the repeating unit may include at least the shielding electrode 14 .

[0231] In an exemplary embodiment, the shape of the first electrode 11 can be rectangular, the corners of the rectangle can be chamfered, the edges of the rectangle can be broken lines, the first electrode 11 can be set in the middle area of ​​the sub-pixel in the second direction Y, the first electrode 11 can serve as a transparent electrode of a transparent storage capacitor, and the first electrode 11 is configured to form a transparent storage capacitor with the second electrode formed subsequently.

[0232] In an exemplary embodiment, the transparent connecting electrode 13 may be in the shape of a strip having a main portion extending along the second direction Y, and may be disposed on a side of the first electrode plate 11 in the opposite direction of the second direction Y. The first end of the transparent connecting electrode 13 is connected to the first electrode plate 11, and the second end of the transparent connecting electrode 13 extends in a direction away from the first electrode plate 11. The second end of the transparent connecting electrode 13 is configured to be connected to the second region of the third active layer formed subsequently.

[0233] In an exemplary embodiment, the first electrode plate 11 and the transparent connecting electrode 13 of each sub-pixel may be an integrated structure connected to each other.

[0234] In an exemplary embodiment, the shape of the blocking electrode 14 can be a strip shape with the main part extending along the second direction Y, and can be arranged on the side of the first electrode 11 in the opposite direction of the second direction Y. The blocking electrode 14 overlaps the extended section of the first electrode 11. On the one hand, the blocking electrode 14 is configured to be connected to the second area of ​​the second active layer formed subsequently, and on the other hand, it is configured to shield the second transistor, reduce the intensity of light irradiated on the second transistor, reduce the leakage current of the second transistor, and thus reduce the impact of light on the characteristics of the second transistor.

[0235] In an exemplary embodiment, the first conductive layer of the repeating unit may further include two first power lines 21, four data signal lines 22, and one compensation signal line 23. The shapes and positions of the first power lines 21, the data signal lines 22, and the compensation signal line 23 are substantially the same as those in the previous embodiment.

[0236] In an exemplary embodiment, patterning the first conductive film and the second conductive film through a patterning process may include: after sequentially depositing the first conductive film and the second conductive film, coating a layer of photoresist on the second conductive film, exposing the photoresist using a half-tone mask, and developing the photoresist to form fully exposed areas, partially exposed areas, and unexposed areas. The photoresist in the fully exposed areas is removed, exposing the surface of the second conductive film in the fully exposed areas, and the photoresist in the partially exposed areas is partially removed. The photoresist in the partially exposed areas has a first thickness, while the photoresist in the unexposed areas remains unchanged. The photoresist in the unexposed areas has a second thickness, wherein the first thickness is less than the second thickness. The unexposed areas are the areas where the shielding electrode 14, the first power line 21, the data signal line 22, and the compensation signal line 23 are located, and the partially exposed areas are the areas where the first plate 11 and the transparent connecting electrode 13 are located. Subsequently, a first etching process is performed to etch away the first and second conductive films in the fully exposed areas, forming patterns of the first power line 21, the data signal line 22, and the compensation signal line 23. Subsequently, an ashing process is used to remove the photoresist from the partially exposed areas, exposing the surface of the second conductive film in the partially exposed areas while leaving the unexposed areas covered with photoresist. Subsequently, a second etching process is performed to etch away the second conductive film in the partially exposed areas, exposing the first conductive film and forming the patterns of the first electrode 11, the transparent connecting electrode 13, and the shielding electrode 14. Finally, the remaining photoresist is stripped off.

[0237] In an exemplary embodiment, the shielding electrode 14, the first power line 21, the data signal line 22 and the compensation signal line 23 are all double-layer structures of a first conductive film and a second conductive film. A first transparent layer is arranged between the shielding metal layer and the substrate. The first transparent layer and the first electrode plate 11 are an integrated structure interconnected, thereby achieving electrical connection between the shielding electrode 14 and the first electrode plate 11.

[0238] In an exemplary embodiment, the double-layer structure of the first power line 21 , the data signal line 22 , and the compensation signal line 23 can effectively reduce the resistance of the signal lines, lower the voltage drop of the signal, and improve the display performance.

[0239] In an exemplary embodiment, the transparent conductive layer may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0240] (22) Forming a first insulating layer pattern. In an exemplary embodiment, forming the first insulating layer pattern may include: depositing a first insulating film on the substrate on which the aforementioned pattern is formed, patterning the first insulating film through a patterning process to form a first insulating layer pattern covering the transparent conductive layer and the first conductive layer, wherein a plurality of via holes are provided on the first insulating layer, as shown in FIG. 15 .

[0241] In an exemplary embodiment, the plurality of via holes of each sub-pixel in the repeating unit includes at least a first via hole V1 , a second via hole V2 , and a third via hole V3 .

[0242] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate at least partially overlaps with the orthographic projection of the data signal line 22 on the substrate, the first insulating layer within the first via hole V1 is etched away to expose the surface of the data signal line 22, and the first via hole V1 is configured to connect the first region of the subsequently formed first active layer to the data signal line 22 through the via hole.

[0243] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate at least partially overlaps with the orthographic projection of the blocking electrode 14 on the substrate, the first insulating layer in the second via hole V2 is etched away to expose the surface of the blocking electrode 14, and the second via hole V2 is configured to connect the second region of the second active layer formed subsequently to the first electrode plate 11 through the via hole.

[0244] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate at least partially overlaps with the orthographic projection of the second end of the transparent connecting electrode 13 on the substrate, the first insulating layer within the third via hole V3 is etched away, exposing the surface of the second end of the transparent connecting electrode 13, and the third via hole V3 is configured to connect the second region of the subsequently formed third active layer to the second end of the transparent connecting electrode 13 through the via hole.

[0245] In an exemplary embodiment, the first insulating layer in the repeating unit may further include a fourth via hole V4 and a fifth via hole V5 .

[0246] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate at least partially overlaps with the orthographic projection of the first power line 21 on the substrate. The first insulating layer within the fourth via hole V4 is etched away, exposing the surface of the first power line 21. The fourth via hole V4 is configured to connect a subsequently formed power connection line to the first power line 21 through the via hole. In an exemplary embodiment, the fourth via hole V4 may be provided in each of the first subpixel P1 and the fourth subpixel P4.

[0247] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate at least partially overlaps with the orthographic projection of the compensation signal line 23 on the substrate. The first insulating layer within the fifth via hole V5 is etched away, exposing the surface of the compensation signal line 23. The fifth via hole V5 is configured to allow a subsequently formed compensation connection line to be connected to the compensation signal line 23 through the via hole. In an exemplary embodiment, the fifth via hole V5 may be provided between the second subpixel P2 and the third subpixel P3.

[0248] (23) Forming a semiconductor layer pattern. In an exemplary embodiment, forming the semiconductor layer pattern may include: depositing a semiconductor thin film on the substrate on which the aforementioned pattern is formed, and patterning the semiconductor thin film through a patterning process to form a semiconductor layer pattern disposed on the first insulating layer, as shown in FIG16A and FIG16B , where FIG16B is a plan view schematic diagram of the semiconductor layer in FIG16A .

[0249] In an exemplary embodiment, the semiconductor layer pattern in each sub-pixel in the repeating unit may include at least a first active layer 31 , a second active layer 32 , a third active layer 33 , a power connection line 34 , a compensation connection line 35 , and a second plate 12 .

[0250] In an exemplary embodiment, the shape of the second electrode plate 12 can be rectangular, and the orthographic projection of the second electrode plate 12 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 11 on the substrate. The second electrode plate 12 can serve as another transparent electrode plate of the transparent storage capacitor, and the first electrode plate 11 and the second electrode plate 12 constitute a transparent storage capacitor of the pixel driving circuit.

[0251] In an exemplary embodiment, in one repeating unit, the overlapping area of ​​the orthographic projection of the second electrode 12 on the substrate and the orthographic projection of the first electrode 11 on the substrate in each sub-pixel may be substantially the same, so that the capacity of the storage capacitor in each sub-pixel is substantially the same.

[0252] In an exemplary embodiment, a plate connection block 12-1 may be provided on the second electrode plate 12. The plate connection block 12-1 may be in a block shape and may be provided on one side of the second electrode plate 12 in the second direction Y. A first end of the plate connection block 12-1 is connected to the second electrode plate 12, and a second end of the plate connection block 12-1 extends away from the second electrode plate 12. The second end of the plate connection block 12-1 is configured to be connected to a twelfth connection electrode formed subsequently.

[0253] In an exemplary embodiment, the shape of the power connection line 34 can be a straight line or a broken line with the main part extending along the first direction X. The power connection line 34 can be arranged on one side of the second electrode plate 12 in the second direction Y, and the power connection line 34 is connected to the first power line 21 through the fourth via V4.

[0254] In an exemplary embodiment, in one repeating unit, the orthographic projection of the power connection line 34 on the substrate at least partially overlaps with the orthographic projection of the four data signal lines 22 on the substrate, and the orthographic projection of the power connection line 34 on the substrate at least partially overlaps with the orthographic projection of the compensation signal line 23 on the substrate.

[0255] In an exemplary embodiment, the power connection line 34 can serve as a horizontal connection line, and the two first power lines 21 in a repeating unit are both connected to the power connection line 34, so that the power connection line 34 extending along the first direction X and the first power line 21 extending along the second direction Y form a mesh structure on the display substrate for transmitting the first power signal. This can not only effectively reduce the resistance of the first power line and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0256] In an exemplary embodiment, the shape of the compensation connection line 35 can be a straight line or a broken line with the main part extending along the first direction X. The compensation connection line 35 can be arranged on the side of the second electrode 12 in the opposite direction of the second direction Y. The compensation connection line 35 is connected to the compensation signal line 23 through the fifth via V5.

[0257] In an exemplary embodiment, in one repeating unit, the orthographic projection of the compensation connection line 35 on the substrate at least partially overlaps with the orthographic projection of the four data signal lines 22 on the substrate, and the orthographic projection of the compensation connection line 35 on the substrate does not overlap with the orthographic projection of the first power line 21 on the substrate.

[0258] In an exemplary embodiment, the first active layer 31 can serve as the active layer of the first transistor T1, the second active layer 32 can serve as the active layer of the second transistor T2, and the third active layer 33 can serve as the active layer of the third transistor T3. The first active layer 31 and the third active layer 33 can be arranged between the compensation connection line 35 and the second electrode plate 12, and the second active layer 32 can be arranged between the power connection line 34 and the second electrode plate 12.

[0259] In example embodiments, each of the first active layer 31 , the second active layer 32 , and the third active layer 33 may include a channel region and first and second regions located at both sides of the channel region.

[0260] In an exemplary embodiment, the first active layer 31 may be L-shaped and may be disposed on the side of the second electrode plate 12 opposite the second direction Y. The first region of the first active layer 31 is connected to the data signal line 22 via a first via V1, and the second region of the first active layer 31 is connected to the second electrode plate 12, thereby enabling the data signal line 22 to write the data signal into the first electrode of the first transistor T1. In an exemplary embodiment, the first region of the first active layer 31 in each sub-pixel may be connected to one data signal line 22 via the first via V1, thereby enabling four data signal lines 22 to write data signals into the first electrodes of the four first transistors T1 in a repeating unit.

[0261] In an exemplary embodiment, in one sub-pixel, the first active layer 31 and the second electrode plate 12 may be an integral structure connected to each other.

[0262] In an exemplary embodiment, the second active layer 32 may be in the shape of a strip extending along the second direction Y. The orthographic projection of the second active layer 32 on the substrate at least partially overlaps with the orthographic projection of the shielding electrode 14 on the substrate. The orthographic projection of the channel region of the second active layer 32 on the substrate may be located within the orthographic projection of the shielding electrode 14 on the substrate. The shielding electrode 14 may shield the channel region of the second active layer 32, preventing light from affecting the channel and reducing leakage current, thereby preventing the influence of light on transistor characteristics and ensuring the electrical performance of the second transistor T2.

[0263] In this exemplary embodiment, the first region of the second active layer 32 is connected to the power connection line 34, and the second region of the second active layer 32 is connected to the shielding electrode 14 via the second via V2. Since the power connection line 34 is connected to the first power line, the first power line 21 writes the first power signal to the first electrode of the second transistor T2. Since the shielding electrode 14 is connected to the first electrode plate 11, the second electrode of the second transistor T2 and the first electrode plate 11 have the same potential.

[0264] In an exemplary embodiment, the two first power lines 21 may include a first first power line and a second first power line. The first first power line may be located on a side of the first pixel column opposite to the first direction X, and the second first power line may be located on a side of the fourth pixel column in the first direction X. Because the first first power line of the first pixel column can simultaneously provide a first power signal to the pixel driving circuits in the first to fourth sub-pixels P1 to P4 via the power connection line 34, and the second first power line of the fourth pixel column can simultaneously provide a first power signal to the pixel driving circuits in the first to fourth sub-pixels P1 to P4 via the power connection line 34, the first power lines 21 in a repeating unit form a two-to-four structure. By designing the first power lines as a two-to-four structure, the display substrate of the present disclosure reduces the number of signal lines and the space occupied, resulting in a simple structure and a reasonable layout, fully utilizing the layout space, improving space utilization, and facilitating improved resolution.

[0265] In an exemplary embodiment, the two first power lines 21 in a repeating unit are substantially mirror-symmetrical with respect to a vertical reference line, and the four second transistors T2 in a repeating unit are substantially mirror-symmetrical with respect to the vertical reference line. This symmetrical structure of the present disclosure can ensure that the voltage drops written by the first power line to the second transistors T2 are substantially the same, thereby ensuring display uniformity.

[0266] In an exemplary embodiment, in one repeating unit, the power connection line 34 and the second active layers 32 in four sub-pixels may be connected to each other in an integral structure.

[0267] In an exemplary embodiment, the third active layer 33 may be in the shape of a strip extending along the first direction X. The first region of the third active layer 33 is connected to the compensation connection line 35, and the second region of the third active layer 33 is connected to the second end of the transparent connection electrode 13 via the third via V3. This enables the compensation signal line 23 to write the compensation signal to the first electrode of the third transistor T3. Since the transparent connection electrode 13 is connected to the first electrode plate 11, the second electrode of the third transistor T3 and the first electrode plate 11 have the same potential.

[0268] In an exemplary embodiment, compensation signal line 23 can be located between the second and third pixel columns. Compensation signal line 23 can simultaneously provide compensation signals to the pixel driver circuits in four sub-pixels via compensation connection line 35. Therefore, the four pixel driver circuits in a repeating unit can share a single compensation signal line 23, i.e., the compensation signal lines 23 in a repeating unit form a one-to-four structure. By designing the display substrate as a one-to-four structure, the disclosed display substrate reduces the number of signal lines and space requirements, resulting in a simple structure and a rational layout. This fully utilizes the layout space, improves space efficiency, and facilitates improved resolution.

[0269] In an exemplary embodiment, the compensation connection line 35 may be mirror-symmetrical with respect to the compensation signal line 23 . This symmetrical structure of the present disclosure can ensure that the RC delay of the third transistors T3 in the four sub-pixels when the compensation signal is written is substantially the same, thereby ensuring display uniformity.

[0270] In an exemplary embodiment, in one repeating unit, the compensation connection line 35 and the third active layers 33 in four sub-pixels may be an integrated structure connected to each other.

[0271] In exemplary embodiments, the semiconductor layer may be formed of a metal oxide, such as an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, an oxide containing indium, gallium, and zinc, etc. The semiconductor layer may be a single layer, a double layer, or a multilayer.

[0272] (24) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second insulating film and the second conductive film through a patterning process to form a second insulating layer disposed on the semiconductor layer, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG17A and FIG17B , where FIG17B is a plan view schematic diagram of the first conductive layer in FIG17A .

[0273] In an exemplary embodiment, the first conductive layer pattern of each sub-pixel in a repeating unit may include at least a scan signal line 40 , a first gate electrode 41 , a second gate electrode 42 , and a third gate electrode 43 .

[0274] In an exemplary embodiment, the shape of the scanning signal line 40 can be a straight line or a broken line with the main portion extending along the first direction X. The scanning signal line 40 can be located on the side of the second electrode plate 12 in the opposite direction of the second direction Y. The scanning signal line 40 is configured to simultaneously control the conduction or disconnection of all the first transistors T1 and all the third transistors T3 in the four sub-pixels of the repeating unit.

[0275] In an exemplary embodiment, the first gate electrode 31 may be in the shape of a strip extending along the second direction Y and may be disposed on a side of the scan signal line 40 close to the first active layer 21. A first end of the first gate electrode 31 is connected to the scan signal line 40, and a second end of the first gate electrode 31 extends toward the first active layer 21. The orthographic projection of the first gate electrode 31 on the substrate at least partially overlaps with the orthographic projection of the first active layer 21 on the substrate. In an exemplary embodiment, the first gate electrode 31 may serve as the gate electrode of the first transistor T1 and may control whether the first transistor T1 is turned on or off.

[0276] In an exemplary embodiment, the first gate electrode 31 and the scan signal line 40 may be an integral structure connected to each other.

[0277] In an exemplary embodiment, the third gate electrode 33 may be in the shape of a strip extending along the second direction Y and may be disposed on a side of the scan signal line 40 close to the third active layer 23. A first end of the third gate electrode 33 is connected to the scan signal line 40, and a second end of the third gate electrode 33 extends toward the third active layer 23. The orthographic projection of the third gate electrode 33 on the substrate at least partially overlaps with the orthographic projection of the third active layer 23 on the substrate. In an exemplary embodiment, the third gate electrode 33 may serve as the gate electrode of the third transistor T3 and may control whether the third transistor T3 is turned on or off.

[0278] In an exemplary embodiment, the third gate electrode 33 and the scan signal line 40 may be an integral structure connected to each other.

[0279] In an exemplary embodiment, in one repeating unit, the scan signal line 40 and the first gate electrode 31 and the third gate electrode 33 in four sub-pixels may be an integrated structure connected to each other.

[0280] In an exemplary embodiment, the first gate electrode 31 and the third gate electrode 33 in one sub-pixel are connected to the same scan signal line 40 , and one scan signal line 40 can simultaneously control the on / off states of the first transistor T1 and the third transistor T3 .

[0281] In an exemplary embodiment, the first gate electrodes 31 and the third gate electrodes 33 in four sub-pixels in one repeating unit are connected to the same scan signal line 40 , and one scan signal line 40 simultaneously controls the on / off switching of four first transistors T1 and four third transistors T3 in one repeating unit.

[0282] In an exemplary embodiment, the first gate electrodes 31 and the third gate electrodes 33 in a plurality of sub-pixels in one pixel row are connected to the same scan signal line 40 , and one scan signal line 40 simultaneously controls the on or off of all first transistors T1 and all third transistors T3 in one pixel row.

[0283] In an exemplary embodiment, the second gate electrode 42 may be L-shaped and may serve as the gate electrode of the second transistor T2. On one hand, the orthographic projection of the second gate electrode 42 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate. On the other hand, the orthographic projection of the second gate electrode 42 on the substrate at least partially overlaps with the orthographic projection of the plate connecting block 12-1 of the second plate 12 on the substrate.

[0284] In an exemplary embodiment, after the second insulating film and the second conductive film are patterned, the second insulating layer pattern is substantially the same as the first conductive layer pattern, and the second insulating layer is disposed on a side of the first conductive layer close to the substrate.

[0285] In an exemplary embodiment, this process also includes a conductive treatment. After forming a first conductive layer pattern, the conductive treatment is performed using the first conductive layer as a shield for plasma treatment. The semiconductor layer shielded by the first conductive layer serves as the channel region of the transistor, while the semiconductor layer not shielded by the first conductive layer is processed into a conductive layer, forming a conductive second plate and a conductive source and drain region.

[0286] (25) Forming a third insulating layer and a planar layer pattern. In an exemplary embodiment, forming the third insulating layer and the planar layer pattern may include: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, then coating a planar film, patterning the planar film and the third insulating film through a patterning process to form a third insulating layer covering the first conductive layer and a planar layer pattern disposed on the third insulating layer, wherein a plurality of vias are disposed on the planar layer, as shown in FIG. 18 .

[0287] In an exemplary embodiment, the plurality of via holes in each sub-pixel in the repeating unit includes at least an eleventh via hole V11 and a twelfth via hole V12 .

[0288] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the second region of the second active layer on the substrate, the flat layer and the third insulating layer within the eleventh via hole V11 are etched away to expose the surface of the second region of the second active layer, and the eleventh via hole V11 is configured to connect a subsequently formed second connecting electrode to the second region of the second active layer through the via hole.

[0289] In an exemplary embodiment, the twelfth via hole V12 may include two sub-holes, one sub-hole having an orthographic projection on the substrate at least partially overlapping with an orthographic projection of the second gate electrode 42 on the substrate, and exposing the surface of the second gate electrode 42, and the other sub-hole having an orthographic projection on the substrate at least partially overlapping with an orthographic projection of the second electrode plate 12 on the substrate, and exposing the surface of the second electrode plate 12. The twelfth via hole V12 is configured to allow a subsequently formed first connection electrode to be simultaneously connected to the second gate electrode 42 and the second electrode plate 12 through the via hole.

[0290] In some possible embodiments, the twelfth via V12 can be a via of a transition structure, including two half holes, one half hole exposing the surface of the second gate electrode 42, and the other half hole exposing the surface of the second electrode plate 12, so that the twelfth via V12 of the transition structure composed of the two half holes simultaneously exposes the second gate electrode 42 and the second electrode plate 12.

[0291] In an exemplary embodiment, this process can use a single patterning process to simultaneously form vias on the third insulating layer and the flat layer. The third insulating layer and the flat layer share a halftone or gray tone mask (MASK) process, effectively reducing the number of patterning processes.

[0292] (26) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on the flat layer, as shown in FIG19A and FIG19B , where FIG19B is a planar schematic diagram of the third conductive layer in FIG19A . In an exemplary embodiment, the third conductive layer may be referred to as a second transparent (2ITO) layer.

[0293] In an exemplary embodiment, the third conductive layer of each sub-pixel in the repeating unit may include at least the first connection electrode 51 , the second connection electrode 52 , and the first electrode 50 .

[0294] In an exemplary embodiment, the shape of the first connection electrode 51 can be a strip shape with a main portion extending along the second direction Y, the first end of the first connection electrode 51 is connected to the second region of the second active layer through the eleventh via hole V11, and the second end of the first connection electrode 51 is connected to the first electrode 50.

[0295] In an exemplary embodiment, the second connection electrode 52 may be in a block shape (e.g., a rectangle). The second connection electrode 52 is connected to both the second gate electrode 42 and the plate connection block 12-1 through a twelfth via V12. In an exemplary embodiment, because the plate connection block 12-1 is connected to the second plate 12, and the second plate 12 is connected to the second region of the first active layer, the second connection electrode 52 ensures that the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the second plate 12 of the storage capacitor have the same potential, forming a first node N1 in the pixel driving circuit.

[0296] In an exemplary embodiment, the first electrode 50 may be rectangular in shape, and the corners of the rectangle may be chamfered, grooved, or protruding. One side of the first electrode 50 is connected to the second end of the first connection electrode 51. Since the second region of the second active layer is connected to the shielding electrode 14 via a via, the shielding electrode 14 is connected to the first electrode plate 11, and the second region of the third active layer is connected to the transparent connection electrode 13 via a via, and the transparent connection electrode 13 is connected to the first electrode plate 11, the first connection electrode 51 ensures that the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode plate 11 of the storage capacitor have the same potential, forming a second node N2 in the pixel driving circuit.

[0297] In an exemplary embodiment, the first plate 11 has the potential of the second node N2 in the pixel driving circuit, the second plate 12 has the potential of the first node N1 in the pixel driving circuit, and the first plate 11 and the second plate 12 constitute a storage capacitor of the pixel driving circuit.

[0298] In an exemplary embodiment, the first connection electrode 51 and the first electrode 50 may be an integral structure connected to each other.

[0299] In exemplary embodiments, the first electrode 50 may be an anode of the light emitting device, or the first electrode 50 may be a cathode of the light emitting device.

[0300] In an exemplary embodiment, the first electrode 50 can also serve as an auxiliary capacitor for the storage capacitor. Because the first electrode 50 is connected to the first connection electrode 51, and the first connection electrode 51 has the potential of the second node N2 in the pixel driving circuit, the first electrode 50 having the potential of the second node N2 and the second electrode plate 12 having the potential of the first node N1 form an auxiliary capacitor, and the auxiliary capacitor and the storage capacitor are connected in parallel. The present disclosure uses the first electrode to form an auxiliary capacitor, and the auxiliary capacitor and the storage capacitor are connected in parallel. On the one hand, it can effectively increase the capacitance value of the storage capacitor. On the other hand, it can reduce the electrode plate area while maintaining the capacitance value of the storage capacitor, effectively reducing the occupied area.

[0301] In an exemplary embodiment, the four first electrodes 50 in a repeating unit may be sequentially arranged along the first direction X and respectively connected to the pixel driving circuits of the first subpixel P1, the second subpixel P2, the third subpixel P3, and the fourth subpixel P4. In some possible implementations, the arrangement of the anodes may be adjusted according to actual needs and is not specifically limited in this disclosure.

[0302] In an exemplary embodiment, the third conductive layer may be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0303] (27) The pixel definition layer, the organic light-emitting layer, the cathode and the encapsulation structure layer patterns are formed. The preparation process is basically the same as that of the above embodiment and will not be repeated here.

[0304] At this point, a drive circuit layer, a light-emitting structure layer disposed on the drive circuit layer, and an encapsulation structure layer disposed on the light-emitting structure layer are prepared on the substrate. In a plane perpendicular to the display substrate, the drive circuit layer may include at least a transparent conductive layer, a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, and a planar layer stacked sequentially on the substrate. The light-emitting structure layer may include at least a first electrode, a pixel definition layer, an organic light-emitting layer, and a second electrode. The encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer.

[0305] In an exemplary embodiment, the display substrate of this embodiment may include a color filter structure layer, and the color filter structure layer may be disposed between the third insulating layer and the planar layer, which will not be described in detail here.

[0306] The display substrate of the embodiment of the present disclosure can not only achieve the technical effect of the display substrate shown in Figure 5, but also, by forming a transparent storage capacitor composed of a transparent conductive layer and a transparent semiconductor layer, light can be emitted through the transparent storage capacitor. Therefore, the storage capacitor can be set in the pixel opening, which can not only effectively increase the capacitance of the storage capacitor, but also effectively increase the pixel aperture ratio.

[0307] Figure 20 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a pixel driver circuit in a repeating unit (four sub-pixels) of a bottom-emission display substrate. The main structure of the display substrate of this embodiment is substantially the same as that shown in Figure 5 , except that the display substrate of this embodiment employs a non-mesh structure for the first power line, with two adjacent first power lines 21 in the first direction X connected to different power connection lines 34.

[0308] The structures of the first electrode plate 11, the second electrode plate 12, the first power line 21, the data signal line 22, the compensation signal line 23, the compensation connection line 35, the first transistor T1, the second transistor T2, the third transistor T3 and the first anode 60 of the display substrate of this embodiment are basically the same as those shown in Figure 5 and are not repeated here.

[0309] As shown in FIG20 , the two power connection lines 34 of this embodiment can be in the shape of a straight line or a broken line, with the main portion extending along the first direction X. The first power connection line 34 can be arranged in the first pixel column and the second pixel column, with one end of the first power connection line 34 connected to the first first power line 21 through the fourth via V4, and the other end of the first power connection line 34 connected to the first region of the second active layer 32 in the first pixel column and the second pixel column, respectively. The second power connection line 34 can be arranged in the third pixel column and the fourth pixel column, with one end of the second power connection line 34 connected to the second first power line 21 through the fourth via V4, and the other end of the second power connection line 34 connected to the first region of the second active layer 32 in the third pixel column and the fourth pixel column, respectively.

[0310] In an exemplary embodiment, in one repeating unit, the orthographic projection of the power connection line 34 on the substrate at least partially overlaps with the orthographic projection of the four data signal lines 22 on the substrate, and the orthographic projection of the power connection line 34 on the substrate does not overlap with the orthographic projection of the compensation signal line 23 on the substrate.

[0311] In an exemplary embodiment, the first first power line in the first pixel column can simultaneously provide a first power signal to the pixel driving circuits in the first sub-pixel P1 and the second sub-pixel P2 via power connection line 34. The second first power line in the fourth pixel column can simultaneously provide a first power signal to the pixel driving circuits in the third sub-pixel P3 and the fourth sub-pixel P4 via power connection line 34. Thus, the first power lines 21 in a repeating unit form a one-to-two structure. By designing the first power lines as a one-to-two structure, the display substrate of the present disclosure reduces the number of signal lines and the occupied space. The structure is simple, the layout is rational, and the layout space is fully utilized, improving space utilization and facilitating higher resolution.

[0312] The display substrate of the embodiment of the present disclosure can not only achieve the technical effect of the display substrate shown in Figure 5, but also effectively increase the pixel aperture ratio and improve the display effect by adopting a first power line structure with a non-mesh structure, making it more suitable for display type display.

[0313] The structure and preparation process shown in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit them.

[0314] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0315] The exemplary embodiments of the present disclosure also provide a method for preparing a display substrate, for preparing the display substrate of the aforementioned embodiment. In the exemplary embodiment, the display substrate includes a plurality of repeating units, at least one repeating unit includes a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and a data signal line connected to the pixel driving circuit, the pixel driving circuit includes at least a storage capacitor and a first transistor, the storage capacitor includes at least a first electrode plate and a second electrode plate, the orthographic projection of the first electrode plate on the display substrate plane at least partially overlapping the orthographic projection of the second electrode plate on the display substrate plane; the preparation method may include:

[0316] forming a first conductive layer on a substrate, wherein the first conductive layer at least includes the data signal line;

[0317] A semiconductor layer is formed on the first conductive layer, the semiconductor layer including at least the second electrode and the first active layer of the first transistor; in at least one sub-pixel, the first active layer is connected to the data signal line through a via hole.

[0318] The present disclosure also provides a display device comprising the display substrate of the aforementioned embodiment. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system.

[0319] While the embodiments disclosed herein are as described above, it should be noted that the above embodiments are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate includes a plurality of repeating units. At least one repeating unit includes a plurality of sub-pixels. At least one sub-pixel includes a pixel driving circuit and a data signal line connected to the pixel driving circuit. The pixel driving circuit includes at least a storage capacitor and a first transistor. The storage capacitor includes at least a first electrode plate and a second electrode plate. The orthographic projection of the first electrode plate on the plane of the display substrate at least partially overlaps with the orthographic projection of the second electrode plate on the plane of the display substrate; In a direction perpendicular to the display substrate, the display substrate includes a first conductive layer disposed on a substrate and a semiconductor layer disposed on a side of the first conductive layer away from the substrate. The first conductive layer at least includes the data signal lines, and the semiconductor layer at least includes the second electrode plate and the first active layer of the first transistor; In at least one sub-pixel, the first active layer is connected to the data signal line through a via.

2. The display substrate according to claim 1, wherein In at least one sub-pixel, the first active layer and the second electrode plate are an integrally connected structure.

3. The display substrate according to claim 1, wherein The pixel driving circuit further includes a second transistor, and the second transistor is connected to a first power supply line through a power supply connection line; the first conductive layer further includes the first power supply line, and the semiconductor layer further includes the power supply connection line and the second active layer of the second transistor; in at least one sub-pixel, the second active layer is connected to the power supply connection line, and the power supply connection line is connected to the first power supply line through a via.

4. The display substrate according to claim 3, wherein, In at least one sub-pixel, the second active layer and the power supply connection line are an integrally connected structure.

5. The display substrate according to claim 3, wherein, The shape of the first power supply line is a straight line or a broken line extending along a second direction, and the shape of the power supply connection line is a straight line or a broken line extending along a first direction, and the first direction and the second direction intersect; two adjacent first power supply lines in the first direction are connected to the same power supply connection line to form a mesh structure.

6. The display substrate according to claim 3, wherein, The shape of the first power supply line is a straight line or a broken line extending along a second direction, and the shape of the power supply connection line is a straight line or a broken line extending along a first direction, and the first direction and the second direction intersect; two adjacent first power supply lines in the first direction are connected to different power supply connection lines.

7. The display substrate according to claim 3, wherein, The display substrate further includes a second conductive layer disposed on a side of the semiconductor layer away from the substrate. The second conductive layer at least includes the second gate electrode of the second transistor, and the second gate electrode is connected to the second electrode plate through a gate connection electrode.

8. The display substrate according to claim 7, wherein, The display substrate further includes a third conductive layer disposed on a side of the second conductive layer away from the substrate. The third conductive layer at least includes the gate connection electrode; the gate connection electrode is connected to the second gate electrode and the second electrode plate through the same via, or the gate connection electrode is connected to the second gate electrode through one via and connected to the second electrode plate through another via.

9. The display substrate according to claim 8, wherein, The third conductive layer further includes a first electrode and an active connection electrode, the first electrode and the active connection electrode are an integrally connected structure, and the active connection electrode is connected to the second active layer through an active via.

10. The display substrate according to claim 9, wherein, The second active layer is connected to the first electrode plate through a board-level via, or the second active layer is connected to a transparent connection electrode through a board-level via, and the transparent connection electrode and the first electrode plate are an integrally connected structure.

11. The display substrate according to claim 10, wherein, In at least one sub-pixel, a positive projection of the active via on the substrate at least partially overlaps a positive projection of the board-level via on the substrate.

12. The display substrate according to claim 1, wherein, The pixel driving circuit further includes a third transistor, the third transistor at least includes a third active layer, the first conductive layer further includes a compensation signal line, and the compensation signal line is connected to the third active layers of a plurality of sub-pixels in the repeating unit through a semiconductor layer.

13. The display substrate according to claim 12, wherein, The semiconductor layer further includes a compensation connection line, the compensation signal line is connected to the compensation connection line through a via hole, and the compensation connection line is connected to the third active layers of a plurality of sub-pixels in the repeating unit.

14. The display substrate according to claim 13, wherein, In at least one repeating unit, the compensation connection line and the third active layers of the plurality of sub-pixels are an integrally connected structure.

15. The display substrate according to claim 12, wherein, In at least one repeating unit, the shape of the compensation signal line is a straight line or a broken line extending along a second direction, the compensation signal line is disposed at an intermediate position in a first direction of the repeating unit, and the first direction and the second direction intersect.

16. The display substrate according to claim 15, wherein, In at least one repeating unit, the plurality of sub-pixels at least include a red sub-pixel, a white sub-pixel, a green sub-pixel, and a blue sub-pixel sequentially disposed along the first direction. The red sub-pixel includes a red data signal line, the green sub-pixel includes a green data signal line, the blue sub-pixel includes a blue data signal line. The red data signal line is disposed on one side of the compensation signal line in the first direction, and the green data signal line and the blue data signal line are disposed on the other side of the compensation signal line in the first direction.

17. The display substrate according to claim 16, wherein, In at least one repeating unit, a first gap is provided between the pixel driving circuit of the red sub-pixel and the pixel driving circuit of the white sub-pixel, and a second gap is provided between the pixel driving circuit of the green sub-pixel and the pixel driving circuit of the blue sub-pixel. The red data signal line is disposed in the first gap, and the green data signal line and the blue data signal line are disposed in the second gap.

18. The display substrate according to any one of claims 1 to 17, wherein The first electrode plate is disposed in the first conductive layer.

19. The display substrate according to any one of claims 1 to 17, wherein, The display substrate further includes a transparent conductive layer disposed between the substrate and the first conductive layer, and the first electrode plate is disposed in the transparent conductive layer.

20. A display device, comprising the display substrate according to any one of claims 1 to 19.

21. A method for manufacturing a display substrate, the display substrate includes a plurality of repeating units, at least one repeating unit includes a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and a data signal line connected to the pixel driving circuit, the pixel driving circuit at least includes a storage capacitor and a first transistor, the storage capacitor at least includes a first electrode plate and a second electrode plate, and at least a part of the orthographic projection of the first electrode plate on the display substrate plane overlaps with the orthographic projection of the second electrode plate on the display substrate plane; the manufacturing method includes: Forming a first conductive layer on a substrate, the first conductive layer at least includes the data signal line; Forming a semiconductor layer on the first conductive layer, the semiconductor layer at least includes the second electrode plate and the first active layer of the first transistor; In at least one sub-pixel, the first active layer is connected to the data signal line through a via hole.

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