Display panel and display device

Abstract

A display panel and a display device. The display panel comprises a display region and a peripheral region surrounding the display region. The display panel comprises a common power line located in the peripheral region and a metal grid structure located in the peripheral region. The metal grid structure is located on the side of the common power line close to the display region, the metal grid structure is connected to the common power line, and part of the wiring of the metal grid structure extends to the display region. The common power line comprises a first line segment having a first line width and a second line segment having a second line width. The first line width is different from the second line width, and the first line segment is directly connected to the second line segment. The metal grid structure comprises a functional grid portion and a main grid portion. The functional grid portion is closer to the connection position of the first line segment and the second line segment than the main grid portion, and the resistance of the functional grid portion per unit area is smaller than that of the main grid portion per unit area. Therefore, the current at the connection position can be dispersed, reducing the current density at the connection position, solving the problem of local region heating.

Description

Display panel and display device Technical Field

[0001] Embodiments of the present disclosure relate to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) display devices have a series of advantages such as self-luminescence, high contrast, high clarity, wide viewing angle, low power consumption, fast response speed, and low manufacturing cost. They have become one of the key development directions of the new generation of display devices and are therefore receiving increasing attention.

[0003] Summary of the Invention

[0004] The embodiments of the present disclosure provide a display panel and a display device. By making the resistance per unit area of ​​the functional grid portion smaller than the resistance per unit area of ​​the main grid portion, the current at the connected positions can be dispersed, the current density at the connected positions can be reduced, and the problem of heating in local areas can be solved.

[0005] At least one embodiment of the present disclosure provides a display panel, comprising a display area and a peripheral area surrounding the display area, the display panel comprising a common power line located in the peripheral area and a metal grid structure located in the peripheral area, the metal grid structure being located on a side of the common power line close to the display area, the metal grid structure being connected to the common power line and part of the routing of the metal grid structure extending to the display area, the common power line comprising a first line segment having a first line width and a second line segment having a second line width, the first line width and the second line width being different, the first line segment and the second line segment being directly connected, the metal grid structure comprising a functional grid portion and a main grid portion, the functional grid portion being closer to the connection position between the first line segment and the second line segment than the main grid portion, and the resistance per unit area of ​​the functional grid portion being smaller than the resistance per unit area of ​​the main grid portion.

[0006] For example, in a display panel provided by an embodiment of the present disclosure, an extending direction of the first line segment is different from an extending direction of the second line segment.

[0007] For example, in a display panel provided by an embodiment of the present disclosure, the first line segment includes an arc segment, and the arc segment is directly connected to the second line segment.

[0008] For example, in a display panel provided in an embodiment of the present disclosure, the main grid portion includes a first grid portion and a second grid portion, the first grid portion and the second grid portion are located on both sides of the functional grid portion, the first grid portion is connected to the first line segment, the second grid portion is connected to the second line segment, and the functional grid portion is connected to the first line segment and the second line segment at the same time.

[0009] For example, in a display panel provided by an embodiment of the present disclosure, all grid lines in the first grid portion are connected to the first line segment, and all grid lines in the second grid portion are connected to the second line segment.

[0010] For example, in a display panel provided by an embodiment of the present disclosure, a ratio of the first line width to the second line width is greater than or equal to 2.

[0011] For example, in the display panel provided in an embodiment of the present disclosure, the peripheral area includes a binding area, the second line width is smaller than the first line width, and the second line segment is located on a side of the display area close to the binding area.

[0012] For example, in the display panel provided in an embodiment of the present disclosure, the functional grid portion and the main grid portion are arranged in the same layer, and the number of grid lines per unit area of ​​the functional grid portion is greater than the number of grid lines per unit area of ​​the main grid portion.

[0013] For example, in the display panel provided in an embodiment of the present disclosure, the functional grid portion and the main body grid portion are provided in the same layer, and the line width of the grid lines of the functional grid portion is greater than the line width of the grid lines of the main body grid portion.

[0014] For example, in the display panel provided in an embodiment of the present disclosure, the functional grid portion and the main grid portion are arranged in the same layer, and the number of grid lines per unit area of ​​the functional grid portion decreases successively in the direction from the functional grid portion to the main grid portion.

[0015] For example, in the display panel provided in one embodiment of the present disclosure, the functional grid portion and the main grid portion are arranged in the same layer, the main grid portion has a first grid pattern, and the functional grid portion has a second grid pattern, the second grid pattern includes the first grid pattern and a plurality of straight line segments, and the plurality of straight line segments extend divergently from a side of the functional grid portion close to the display area to the common power line.

[0016] For example, in the display panel provided in one embodiment of the present disclosure, the functional grid portion includes a first grid layer and a second grid layer electrically connected to each other, the first grid layer and the main grid portion are arranged in the same layer, and the first grid layer and the second grid layer are arranged in different layers.

[0017] For example, in a display panel provided in an embodiment of the present disclosure, in a direction perpendicular to the display panel, the first grid layer and the second grid layer have substantially the same grid pattern.

[0018] For example, a display panel provided in an embodiment of the present disclosure also includes: a base substrate and a pixel circuit driving layer formed on the base substrate, the pixel circuit driving layer includes a plurality of conductive patterns arranged in sequence along a direction perpendicular to the base substrate, the plurality of conductive patterns include a first conductive pattern and a second conductive pattern, the first grid layer and the main grid portion are located on the same conductive layer as the first conductive pattern, and the second grid layer and the second conductive pattern are located on the same conductive layer.

[0019] For example, in the display panel provided in one embodiment of the present disclosure, the first grid layer is located on the side of the second grid layer away from the base substrate, and along the direction perpendicular to the base substrate, the orthographic projection of the grid lines of the first grid layer on the base substrate falls within the orthographic projection of the grid lines of the second grid layer on the base substrate.

[0020] For example, a display panel provided in an embodiment of the present disclosure also includes: a base substrate, a pixel circuit driving layer formed on the base substrate, and a shielding metal layer located between the base substrate and the pixel circuit driving layer, the pixel circuit driving layer includes a plurality of conductive patterns arranged in sequence along a direction perpendicular to the base substrate, the plurality of conductive patterns include a first conductive pattern, the first grid layer and the main grid portion are located on the same conductive layer as the first conductive pattern, and the second grid layer and the shielding metal layer are located on the same conductive layer.

[0021] For example, in the display panel provided in one embodiment of the present disclosure, the functional grid portion also includes a third grid layer located between the first grid layer and the second grid layer, the multiple conductive patterns also include a second conductive pattern, and the third grid layer and the second conductive pattern are located in the same conductive layer.

[0022] For example, a display panel provided in an embodiment of the present disclosure also includes: a base substrate, a pixel circuit driving layer formed on the base substrate, and a first electrode layer formed on a side of the pixel circuit driving layer away from the base substrate, the pixel circuit driving layer includes a plurality of conductive patterns arranged in sequence along a direction perpendicular to the base substrate, the plurality of conductive patterns include a first conductive pattern, the first grid layer and the main grid portion are located on the same conductive layer as the first conductive pattern, and the second grid layer and the first electrode layer are located on the same conductive layer.

[0023] For example, the display panel provided in one embodiment of the present disclosure also includes: a base substrate, the metal grid structure is located on the base substrate; a plurality of insulating layers, located on a side of the metal grid structure away from the base substrate, and along a direction perpendicular to the base substrate, the thickness of the region where the plurality of insulating layers overlap with the functional grid portion is less than the thickness of other regions of the plurality of insulating layers.

[0024] For example, the display panel provided in an embodiment of the present disclosure also includes: a first transfer line, extending along the first direction; a second transfer line, extending along the second direction, and being arranged in a different layer from the first transfer line; a first dummy line, extending along the first direction; a second dummy line, extending along the second direction, and being arranged in a different layer from the first dummy line; a data line, extending along the second direction, one end of the first transfer line is connected to the data line through a first via, and the other end of the first transfer line is connected to the second transfer line through a second via, the first via and the second via form a first transfer area, the peripheral area includes a binding area, the first transfer area is located on a side of the display area close to the binding area, the display panel also includes a light-emitting element, the first dummy line and the second dummy line are connected to the cathode of the light-emitting element and are configured to transmit a power supply voltage, the first dummy line and the second dummy line are connected through a third via, and the third via forms a plurality of second transfer areas.

[0025] For example, in the display panel provided in an embodiment of the present disclosure, the portion of the wiring of the metal grid structure extending into the display area includes the first dummy line, or the portion of the wiring of the metal grid structure extending into the display area includes the second dummy line.

[0026] For example, a display panel provided in an embodiment of the present disclosure also includes: a base substrate and a pixel circuit driving layer formed on the base substrate, the pixel circuit driving layer includes a plurality of conductive patterns arranged in sequence along a direction perpendicular to the base substrate, the plurality of conductive patterns include a first conductive pattern and a second conductive pattern, the first transfer line and the first dummy line are located in the same conductive layer as the first conductive pattern, and the second transfer line and the second dummy line are located in the same conductive layer as the second conductive pattern.

[0027] For example, the display panel provided in one embodiment of the present disclosure further includes: a third transfer line extending along the first direction; a fourth transfer line extending along the second direction and arranged in a different layer from the third transfer line; a third dummy line extending along the first direction; a fourth dummy line extending along the second direction and arranged in a different layer from the third dummy line; a data line extending along the second direction, one end of the third transfer line being connected to the data line through a fourth via hole, the other end of the third transfer line being connected to the fourth transfer line through a fifth via hole, the fourth via hole and the fifth via hole forming a plurality of third transfer areas, the plurality of third The transfer areas are arranged at intervals along the first direction, the display panel has a display area and a peripheral area surrounding the display area, the peripheral area includes a binding area, the multiple third transfer areas are located on a side of the display area close to the binding area, the display panel also includes a light-emitting element, the third dummy line and the fourth dummy line are connected to the cathode of the light-emitting element and are configured to transmit a power supply voltage, the third dummy line and the fourth dummy line are connected through a sixth via, the sixth via forms a plurality of fourth transfer areas, and along the first direction, at least one of the fourth transfer areas is located between the multiple third transfer areas.

[0028] For example, the display panel provided in one embodiment of the present disclosure also includes: a lead, located between the display area and the binding area, the binding area includes a common power terminal, the common power terminal is configured to transmit a common power signal, one end of the lead is connected to the common power terminal, the multiple fourth transfer areas include a first sub-area, along the first direction, the first sub-area is located between the multiple third transfer areas, and the fourth virtual line of the first sub-area is connected to the other end of the lead.

[0029] For example, a display panel provided in an embodiment of the present disclosure also includes: a base substrate; a pixel circuit driving layer located on the base substrate; and a common power grid layer located on a side of the pixel circuit driving layer away from the base substrate, the pixel circuit driving layer includes a plurality of conductive patterns arranged in sequence along a direction perpendicular to the base substrate, the metal grid structure and the common power line are located on the same conductive layer as the conductive patterns, the common power grid layer includes grid traces located in the display area and peripheral common power lines located in the peripheral area, the peripheral area includes a binding area, the display panel also includes a lead, the lead is located between the display area and the binding area, the binding area includes a common power terminal, the common power terminal is configured to transmit a common power signal, one end of the lead is connected to the common power terminal, and the other end of the lead is connected to the grid trace of the common power grid layer.

[0030] For example, the display panel provided in an embodiment of the present disclosure further includes a light-emitting device layer located on a side of the common power grid layer away from the base substrate.

[0031] For example, the display panel provided in one embodiment of the present disclosure also includes a plurality of pixels, each of the pixels includes an effective light-emitting area and a non-display area surrounding the effective light-emitting area, and the grid lines of the common power grid layer on the base substrate are within the orthographic projection of the non-display area on the base substrate.

[0032] At least one embodiment of the present disclosure provides a display panel, comprising: a third transfer line extending along a first direction; a fourth transfer line extending along a second direction and being arranged in a different layer from the third transfer line; a third dummy line extending along the first direction; a fourth dummy line extending along the second direction and being arranged in a different layer from the third dummy line; a data line extending along the second direction, one end of the third transfer line being connected to the data line through a fourth via hole, the other end of the third transfer line being connected to the fourth transfer line through a fifth via hole, the fourth via hole and the fifth via hole forming a plurality of third transfer areas, the plurality of third transfer areas The transfer areas are arranged at intervals along the first direction, the display panel has a display area and a peripheral area surrounding the display area, the peripheral area includes a binding area, the multiple third transfer areas are located on a side of the display area close to the binding area, the display panel also includes a light-emitting element, the third dummy line and the fourth dummy line are connected to the cathode of the light-emitting element and are configured to transmit a power supply voltage, the third dummy line and the fourth dummy line are connected through a sixth via, the sixth via forms a plurality of fourth transfer areas, and along the first direction, at least one of the fourth transfer areas is located between the multiple third transfer areas.

[0033] For example, the display panel provided in one embodiment of the present disclosure also includes: a lead, located between the display area and the binding area, the binding area includes a common power terminal, the common power terminal is configured to transmit a common power signal, one end of the lead is connected to the common power terminal, the multiple fourth transfer areas include a first sub-area, along the first direction, the first sub-area is located between the multiple third transfer areas, and the fourth virtual line of the first sub-area is connected to the other end of the lead.

[0034] For example, in the display panel provided in an embodiment of the present disclosure, the third transfer line and the third dummy line are provided in the same layer.

[0035] For example, in the display panel provided in an embodiment of the present disclosure, the fourth transfer line and the fourth dummy line are provided in the same layer.

[0036] For example, a display panel provided in an embodiment of the present disclosure also includes: a base substrate and a pixel circuit driving layer formed on the base substrate, the pixel circuit driving layer includes a plurality of conductive patterns arranged in sequence along a direction perpendicular to the base substrate, the plurality of conductive patterns include a first conductive pattern and a second conductive pattern, the third transfer line and the third dummy line are located in the first conductive pattern, and the fourth transfer line and the fourth dummy line are located in the second conductive pattern.

[0037] At least one embodiment of the present disclosure provides a display panel, comprising: a base substrate; a pixel circuit driving layer located on the base substrate; and a common power grid layer located on a side of the pixel circuit driving layer away from the base substrate, wherein the display panel has a display area and a peripheral area surrounding the display area, the common power grid layer comprises grid traces located in the display area and peripheral common power lines located in the peripheral area, the peripheral area comprises a binding area, the display panel further comprises a lead, the lead is located between the display area and the binding area, the binding area comprises a common power terminal, the common power terminal is configured to transmit a common power signal, one end of the lead is connected to the common power terminal, and the other end of the lead is connected to the grid traces of the common power grid layer.

[0038] For example, in a display panel provided in an embodiment of the present disclosure, the peripheral common power line includes a third line segment having a third line width and a fourth line segment having a fourth line width, the third line width and the fourth line width are different, and the third line segment and the fourth line segment are directly connected.

[0039] For example, the display panel provided in an embodiment of the present disclosure further includes: a light-emitting device layer located on a side of the common power grid layer away from the base substrate.

[0040] For example, the display panel provided in one embodiment of the present disclosure also includes: a plurality of pixels, each of the pixels including an effective light-emitting area and a non-display area surrounding the effective light-emitting area, and the grid lines of the common power grid layer on the base substrate are within the orthographic projection of the non-display area on the base substrate.

[0041] For example, the display panel provided in one embodiment of the present disclosure also includes: a common power line, located in the peripheral area; and a metal grid structure, located in the peripheral area and on the side of the common power line close to the display area, the metal grid structure is connected to the common power line and part of the lines of the metal grid structure extend to the display area, the pixel circuit driving layer includes a plurality of conductive patterns arranged in sequence along a direction perpendicular to the base substrate, the plurality of conductive patterns include a first conductive pattern, the common power line and the metal grid structure are located in the same conductive layer as the first conductive pattern.

[0042] At least one embodiment of the present disclosure provides a display device, comprising any of the above-mentioned display panels. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0044] FIG1 is a diagram showing the alignment of a local frame of a display panel;

[0045] FIG2 is a schematic cross-sectional view shown in FIG1 ;

[0046] FIG3 is a current density simulation diagram shown in FIG1 ;

[0047] FIG4 is a schematic plan view of a display panel provided in one embodiment of the present disclosure;

[0048] FIG5 is a partial wiring diagram of the display panel shown in FIG4 ;

[0049] FIG6 is a partial enlarged view of FIG5;

[0050] FIG7 is a schematic cross-sectional view of FIG6 ;

[0051] FIG8 is a partially enlarged wiring diagram of a display panel provided by an embodiment of the present disclosure;

[0052] FIG9 is a schematic cross-sectional view of FIG8 ;

[0053] FIG10 is a partially enlarged wiring diagram of a metal mesh structure of a display panel provided by an embodiment of the present disclosure;

[0054] FIG11 is a partially enlarged wiring diagram of a display panel provided by an embodiment of the present disclosure;

[0055] FIG12 is a cross-sectional schematic diagram of FIG11;

[0056] FIG13 is a partial enlarged view of a first grid layer of a display panel provided by an embodiment of the present disclosure;

[0057] FIG14 is a partial enlarged view of a second grid layer of the display panel shown in FIG13 ;

[0058] FIG15 is a partial cross-sectional schematic diagram of the display panel shown in FIG13;

[0059] FIG16 is a partial enlarged view of another second conductive layer of the display panel shown in FIG13;

[0060] FIG17 is a partial cross-sectional schematic diagram of the display panel shown in FIG13;

[0061] FIG18 is a partial wiring diagram of the display panel shown in FIG13 ;

[0062] FIG19 is a partial cross-sectional schematic diagram of the display panel shown in FIG18 ;

[0063] FIG20 is a partial wiring diagram of a display panel provided by an embodiment of the present disclosure;

[0064] FIG21 is a partial wiring diagram of the second grid layer of the display panel shown in FIG20 ;

[0065] FIG22 is a partial cross-sectional schematic diagram of the display panel shown in FIG20 ;

[0066] FIG23 is a schematic diagram of partial wiring of a display panel provided by an embodiment of the present disclosure;

[0067] FIG24 is a partial cross-sectional schematic diagram of FIG23;

[0068] FIG25 is a schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0069] FIG26 is a partial enlarged schematic diagram of FIG25;

[0070] FIG27 is another schematic diagram of a display panel provided in one embodiment of the present disclosure;

[0071] FIG28 is a partial enlarged schematic diagram of FIG27;

[0072] FIG29 is a plan view of a common power grid layer of a display panel provided by an embodiment of the present disclosure;

[0073] FIG30 is a partial schematic diagram of the common power grid layer shown in FIG29;

[0074] FIG31 is a schematic cross-sectional view of FIG29;

[0075] FIG32 is another schematic cross-sectional view of the display panel shown in FIG29 ;

[0076] FIG33 is a plan view of the metal mesh structure of FIG32; and

[0077] FIG34 is a schematic diagram of a display device provided according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0078] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0079] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0080] Unless otherwise defined, the features such as "parallel", "perpendicular" and "same" used in the embodiments of the present disclosure include the cases of "parallel", "perpendicular", "same" in a strict sense, as well as the cases of "approximately parallel", "approximately perpendicular", "approximately the same" and the like which contain certain errors. For example, the above-mentioned "approximately" may mean that the difference between the compared objects is 10% of the average value of the compared objects, or within 5%. When the number of a component or element is not specifically indicated below in the embodiments of the present disclosure, it means that the component or element may be one or more, or may be understood as at least one. "At least one" refers to one or more, and "multiple" refers to at least two. The "same-layer arrangement" in the embodiments of the present disclosure refers to the relationship between multiple film layers formed by the same material after the same step (for example, a one-step patterning process). The "same layer" here does not always mean that the thickness of multiple film layers is the same or the height of multiple film layers in the cross-sectional view is the same.

[0081] High Brightness Mode (HMD) is a display mode of the display panel. Under strong light, such as in strong outdoor light environments, the low brightness contrast is insufficient, and HBM mode display is required to maintain sufficient contrast. In addition, fingerprint or facial recognition under strong light is easily affected by external light, which affects the corresponding speed and signal-to-noise ratio. Improving the HBM brightness can improve the fingerprint or facial recognition performance under strong light. Therefore, the brightness demand of HBM is getting higher and higher. For example, the HBM brightness demand of some products has exceeded 2000nit. However, the higher the brightness demand, the corresponding current demand will also become higher. When the common power supply (VSS) line passes through the corner of the display panel frame, the narrow position at the corner can easily lead to excessive current density, causing the display panel to heat up, resulting in a decrease in luminous efficiency and even wiring burns. Although the display panel can emit higher brightness at the same current by improving the luminous efficiency of the light-emitting element, it is still difficult to meet the brightness demand by simply improving the luminous efficiency of the light-emitting element.

[0082] The demand for narrow borders of display panels is increasing. For example, some products require the distance from the display area to the bottom border to be narrower and narrower, reaching 500μm, which results in the compression of signal routing space. For the same current, the current density of the narrow border increases, which will also cause the display panel to overheat.

[0083] Figure 1 is a wiring diagram of a local frame position of a display panel; Figure 2 is a cross-sectional schematic diagram of the display panel; and Figure 3 is a current density simulation diagram of the display panel. As shown in Figures 1 and 2, at the corner of the frame of the display panel, the metal grid 10 is connected to the common power line 11 to disperse the current of the common power line 11 and reduce the current density. However, as shown in Figure 3, at the position where the width and direction of the common power line 11 change (the position indicated by the arrow in the figure), the current density is the largest, reaching 1.56*10 9 A / m 2 , causing the display panel to overheat, resulting in reduced luminous efficiency and even wiring burns.

[0084] In this regard, an embodiment of the present disclosure provides a display panel and a display device. The display panel has a display area and a peripheral area surrounding the display area, the display panel includes a common power line located in the peripheral area and a metal grid structure located in the peripheral area, the metal grid structure is located on the side of the common power line close to the display area, the metal grid structure is connected to the common power line and part of the metal grid structure extends to the display area. The common power line includes a first line segment having a first line width and a second line segment having a second line width, the first line width and the second line width are different, and the first line segment and the second line segment are directly connected. The metal grid structure includes a functional grid portion and a main grid portion, the functional grid portion is closer to the connection position of the first line segment and the second line segment than the main grid portion. The resistance per unit area of ​​the functional grid portion is smaller than the resistance per unit area of ​​the main grid portion.

[0085] In the display panel provided by the embodiment of the present disclosure, the metal grid structure is connected to the common power line to disperse the current and reduce the current density. At the connecting position of the first line segment and the second line segment of the common power line, due to the different line widths of the first line segment and the second line segment, the line width of the common power line changes, and the current density at the connecting position of the first line segment and the second line segment will be greater than that at other positions. By making the resistance per unit area of ​​the functional grid portion smaller than the resistance per unit area of ​​the main grid portion, the current at the connecting position can be dispersed, the current density at the connecting position can be reduced, and the current at the position with the maximum current density can be accurately and effectively reduced, thereby solving the problem of heating in the local area. In addition, by making the resistance per unit area of ​​the functional grid portion smaller than the resistance per unit area of ​​the main grid portion, the structure of the heating position is improved and optimized in a targeted manner, and the problem of heating in the local area can be better solved without changing the structural design of other areas.

[0086] The display panel and the display device provided by the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0087] An embodiment of the present disclosure provides a display panel. FIG4 is a planar schematic diagram of a display panel provided by an embodiment of the present disclosure; FIG5 is a partial wiring diagram of the display panel shown in FIG4; FIG6 is a partial enlarged diagram of FIG5; and FIG7 is a cross-sectional schematic diagram of FIG6. As shown in FIG4 to FIG7, the display panel 100 has a display area AA and a peripheral area BB surrounding the display area AA. The display panel 100 includes a common power line 110 located in the peripheral area BB and a metal grid structure 120 located in the peripheral area BB. The metal grid structure 120 is located on a side of the common power line 110 close to the display area AA. The metal grid structure 120 is connected to the common power line 110 and part of the wiring of the metal grid structure 120 extends to the display area AA. The common power line 110 includes a first line segment 111 having a first line width and a second line segment 112 having a second line width. The first line width and the second line width are different. The first line segment 111 and the second line segment 112 are directly connected. The metal mesh structure 120 includes a functional mesh portion 121 and a main mesh portion 122. The functional mesh portion 121 is closer to the connecting position P of the first line segment 111 and the second line segment 112 than the main mesh portion 122. The resistance per unit area of ​​the functional mesh portion 121 is lower than the resistance per unit area of ​​the main mesh portion 122.

[0088] In the display panel 100 provided in the embodiment of the present disclosure, the metal mesh structure 120 is connected to the common power line 110 to disperse the current and reduce the current density. At the connection position P of the first line segment 111 and the second line segment 112 of the common power line 110, due to the different line widths of the first line segment 111 and the second line segment 112, the line width of the common power line 110 changes, and the current density at the connection position P of the first line segment 111 and the second line segment 112 is greater than that at other positions. By making the resistance per unit area of ​​the functional grid portion 121 smaller than the resistance per unit area of ​​the main grid portion 122, the current at the connection position P can be dispersed, reducing the current density at the connection position P. The current at the position with the maximum current density can be accurately and effectively reduced, solving the problem of localized heating. In addition, by making the resistance per unit area of ​​the functional grid portion 121 smaller than the resistance per unit area of ​​the main grid portion 122, the structure of the heat-generating position is improved and optimized in a targeted manner, and the problem of localized heating can be better solved without changing the structural design of other areas. For example, the common power line 110 is used to transmit the first common power supply voltage (VSS).

[0089] In some examples, as shown in Figures 5 and 6 , the second line width of the second line segment 112 is smaller than the first line width of the first line segment 111. Due to the smaller line width, the current density at the connecting position P of the second line segment 112 and the first line segment 111 is too high, and the local area is prone to heating. By optimizing the metal mesh structure 120 in this area, the current at the location with the maximum current density can be accurately and effectively reduced, thus solving the problem of local heating.

[0090] In some examples, as shown in Figures 5 and 6, the extension direction of the first line segment 111 is different from the extension direction of the second line segment 112. For example, the extension direction of the first line segment 111 is at an angle to the extension direction of the second line segment 112. For example, as shown in Figure 4, the intersection position P of the first line segment 111 and the second line segment 112 is located in a corner region of the display panel 100. For example, as shown in Figure 4, the first line segment 111 and the second line segment 112 are located at the intersection region of two adjacent sides of the display panel 100.

[0091] In some examples, as shown in Figures 5 and 6, the first line segment 111 includes an arc segment, which is directly connected to the second line segment 112. For example, the arc segment is located at a corner of the display panel 100. For example, the arc segment is located at the intersection of two adjacent sides of the display panel 100.

[0092] In some examples, as shown in Figures 5 to 7, the main grid portion 122 includes a first grid portion 122a and a second grid portion 122b, the first grid portion 122a and the second grid portion 122b are located on both sides of the functional grid portion 121, the first grid portion 122a is connected to the first line segment 111, the second grid portion 122b is connected to the second line segment 112, and the functional grid portion 121 is connected to the first line segment 111 and the second line segment 112 at the same time.

[0093] In some examples, as shown in FIG. 5 and FIG. 6 , the grid lines in the first grid portion 122 a are all connected to the first line segment 111 , and the grid lines in the second grid portion 122 b are all connected to the second line segment.

[0094] In some examples, as shown in FIG5 , the ratio of the first line width to the second line width is greater than or equal to 2. By reducing the second line width of the second line segment 112, the border on the side where the second line segment 112 is located can be narrowed, thereby achieving a narrow border. The embodiment of the present disclosure does not limit the ratio of the first line width to the second line width, and can be designed according to the requirements of the display panel 100. For example, the ratio can also be greater than or equal to 2.5, or greater than or equal to 3.

[0095] For example, the peripheral area BB includes a binding area, and the second line segment 112 is located on a side of the display area AA that is close to the binding area. By reducing the second line width of the second line segment 112, the border of the display area AA on the side close to the binding area can be narrowed. For example, as shown in FIG4 , the border on the side where the second line segment is located can be the bottom border of the display panel 100.

[0096] In some examples, as shown in Figures 5 to 7, the functional grid portion 121 and the main grid portion 122 are arranged in the same layer, and the number of grid lines per unit area of ​​the functional grid portion 121 is greater than the number of grid lines per unit area of ​​the main grid portion 122. As a result, not only can the resistance per unit area of ​​the functional grid portion 121 be smaller than the resistance per unit area of ​​the main grid portion 122, the current density at the connection position P can be accurately and effectively reduced, and the problem of heating in the local area can be better solved without adding a film layer or changing the structural design of other areas. The embodiment of the present disclosure does not limit the thickness, direction or pattern of the grid lines of the functional grid portion 121 and the main grid portion 122. It should be noted that Figure 7 only schematically shows the metal grid structure, and other conductive layers are no longer described one by one.

[0097] For example, as shown in FIG7 , the display panel 100 further includes a base substrate 130 and a pixel driving circuit layer 140 formed on the base substrate. The pixel driving circuit layer 140 includes a plurality of conductive patterns, and the metal grid structure 120 may be located in the same conductive layer as one of the conductive patterns. For example, as shown in FIG7 , from bottom to top, the layers are the base substrate 130, the isolation buffer layer, the gate insulating layer, the interlayer insulating layer, the passivation layer, the first planarization layer, the second planarization layer, the metal grid structure 120, and the third planarization layer. For example, the base substrate 130 may include a flexible insulating material such as polyimide (PI) or a rigid insulating material such as a glass substrate. For example, the metal grid structure 120 may be a multi-layer composite film, for example, a TIALTi film. For example, the metal grid structure 120 may also be a single-layer film. The embodiments of the present disclosure do not limit the conductive layer, etc., where the metal grid structure 120 is located.

[0098] Figure 8 is a partially enlarged wiring diagram of a display panel provided by an embodiment of the present disclosure; Figure 9 is a cross-sectional schematic diagram of Figure 8. As shown in Figures 8 and 9, the functional grid portion 121 and the main grid portion 122 are arranged in the same layer, and the line width of the grid lines of the functional grid portion 121 is greater than the line width of the grid lines of the main grid portion 122. As a result, not only can the resistance per unit area of ​​the functional grid portion 121 be made smaller than the resistance per unit area of ​​the main grid portion 122, the current density at the connection position P can be accurately and effectively reduced, and the problem of heating in the local area can be better solved without adding a film layer or changing the structural design of other areas. The embodiment of the present disclosure does not limit the direction or pattern of the grid lines of the functional grid portion 121 and the main grid portion 122. It should be noted that Figure 9 only schematically shows the metal grid structure, and other conductive layers are no longer described one by one.

[0099] In some examples, as shown in Figures 6 to 9, the mesh density of the metal mesh structure 120 ranges from 40% to 85%, and correspondingly, the hole density of the metal mesh structure 120 ranges from 15% to 60%. Setting the maximum mesh density of the functional mesh portion 121 of the metal mesh structure 120 to 85% can reduce the current density without causing excessive load due to excessive wiring density, nor can it affect the exhaust of the insulating layer below the metal mesh structure 120 due to excessive wiring density. Setting the minimum mesh density of the main mesh portion 122 of the metal mesh structure 120 to 40% can avoid the situation where the mesh density is too small and the effect of reducing the current density is not obvious.

[0100] It should be noted that the grid density is the ratio of the area of ​​the grid lines per unit area, the hole density is the ratio of the area of ​​the holes per unit area, and the sum of the grid density and the hole density is 100%. For example, under the premise that the line widths of the grid lines of the metal grid structure 120 are equal, the grid density can be equivalent to the density of the grid lines per unit area, and the change in grid density can be equivalent to the change in the density of the grid lines or the number of grids.

[0101] For example, a mesh density of 40% corresponds to a hole density of 60%. For example, a mesh density of 85% corresponds to a hole density of 15%. For example, a mesh density of 65% corresponds to a hole density of 40%. The present disclosure does not impose any restrictions on mesh density and hole density, and can be designed based on the actual product.

[0102] For example, the pore density of the functional mesh portion 121 of the metal mesh structure 120 can be 15%, and the pore density of the main mesh portion 122 can be 20%. For example, the pore density of the functional mesh portion 121 can be 20%, and the pore density of the main mesh portion 122 can be 40%. For example, the pore density of the functional mesh portion 121 can be 15%, and the pore density of the main mesh portion 122 can be 60%. The embodiments of the present disclosure do not impose any restrictions on the pore density of the functional mesh portion 121 and the main mesh portion 122, and can be designed based on the current density distribution analyzed by simulation.

[0103] Figure 10 is a partially enlarged wiring diagram of a metal grid structure of a display panel provided by an embodiment of the present disclosure. As shown in Figure 10, the functional grid portion 121 and the main grid portion 122 are arranged in the same layer, and the number of grid lines per unit area of ​​the functional grid portion 121 decreases successively in the direction from the functional grid portion 121 to the main grid portion 122. Thus, the metal grid structure can be improved and optimized in a targeted manner for local heating areas, so as to achieve better improvement effects. The embodiment of the present disclosure does not limit the thickness, direction or pattern of the grid lines of the functional grid portion 121 and the main grid portion 122. For example, the distribution of the grid lines of the metal grid structure 120 can be designed based on the current density distribution analyzed by simulation and taking into account process factors such as the exhaust of the insulating layer to better reduce the current density.

[0104] Figure 10 schematically illustrates that the number of grid lines per unit area of ​​the functional grid portion 121 decreases along the horizontal direction in the figure, but is not limited to this. For example, the number of grid lines per unit area of ​​the functional grid portion 121 decreases along any direction from the functional grid portion 121 toward the main grid portion 122. For example, this can be along the vertical direction in the figure, or any other direction between the horizontal and vertical directions.

[0105] In some examples, the number of grid lines per unit area of ​​the functional grid portion 121 decreases in a certain pattern along the direction from the functional grid portion 121 to the main grid portion 122. For example, the number of grid lines may decrease in an arithmetic progression.

[0106] In some examples, as shown in Figure 10, the mesh density of the main grid portion 122 can be 40%, and the mesh density of the functional grid portion 121 can be 80% at the position where the current density is maximum. In the direction from the functional grid portion 121 to the main grid portion 122, the mesh density of the functional grid portion 121 decreases from 80% to 40%.

[0107] For example, as shown in Figure 10, the mesh density of the functional grid portion 121 in area A1 is 80%, the length of area A1 is 40μm, and in the next 40μm area A2 in the direction from the functional grid portion 121 to the main grid portion 122, the mesh density of the functional grid portion 121 is 60%, and the mesh density of the main grid portion 122 adjacent to the area A2 with a mesh density of 60% is 40%. The figure schematically shows that the length of each area in the horizontal direction is 40μm, and the embodiment of the present disclosure is not limited to this. The length in other directions can be determined according to the shape of the metal grid structure at the location of the display panel. The present disclosure does not limit the size or area of ​​area A1 and area A2. It can be other values. The values ​​of area A1 and area A2 can also be different. It can be designed according to the size or area of ​​the heating area.

[0108] For example, the grid density of the functional grid portion 121 may vary in a gradient of 80%, 70%, 60%, 50%, or 40%. For example, within an area of ​​a set size at the connecting position P of the first line segment 111 and the second line segment 112, the grid density of the functional grid portion 121 may be 80%, and within an area of ​​the next set size in the direction from the functional grid portion 121 to the main grid portion 122, the grid density of the functional grid portion 121 is 70%. Similarly, within an area of ​​the next set size, the grid density of the functional grid portion 121 is 60%, 50%, and the grid density of the main grid portion 122 is 40%. The disclosed embodiment does not limit the set size of each area. The set size of each grid density area may be the same or different. The grid density of adjacent areas may vary in a certain pattern to better solve the problem of heating in local areas.

[0109] FIG11 is a partially enlarged wiring diagram of a display panel provided by an embodiment of the present disclosure; FIG12 is a cross-sectional schematic diagram of FIG11. As shown in FIG11 and FIG12, the functional grid portion 121 and the main grid portion 122 are arranged on the same layer, the main grid portion 122 has a first grid pattern, and the functional grid portion 121 has a second grid pattern. The second grid pattern includes a first grid pattern and a plurality of straight line segments 1210, and the plurality of straight line segments extend in a divergent manner from the side of the functional grid portion 121 close to the display area AA to the common power line 110. The direction of the plurality of straight line segments 1210 is roughly the same as the direction of the current. Therefore, in the area with the highest current density, the pattern and routing of the grid lines of the functional grid portion 121 are designed according to the direction of the current, which can effectively reduce the current density in the area with the highest current density, better reduce the current density, and solve the problem of local heating. It should be noted that FIG12 only schematically shows the metal grid structure, and the other conductive layers are not described one by one.

[0110] Figure 13 is a partial enlarged view of a first grid layer of a display panel provided by an embodiment of the present disclosure; Figure 14 is a partial enlarged view of a second grid layer of the display panel shown in Figure 13; and Figure 15 is a partial cross-sectional schematic diagram of the display panel shown in Figure 13. As shown in Figures 13 to 15, the functional grid portion 121 includes a first grid layer 121a and a second grid layer 121b that are electrically connected to each other. The first grid layer 121a is arranged on the same layer as the main grid portion 122, and the first grid layer 121a and the second grid layer 121b are arranged on different layers. The parallel connection of the first grid layer 121a and the second grid layer 121b can make the resistance per unit area of ​​the functional grid portion 121 lower than the resistance per unit area of ​​the main grid portion 122, thereby reducing the current density at the connection position P and solving the problem of localized heating. In order to clearly show the first grid layer 121a and the second grid layer 121b, the first grid layer 121a and the second grid layer 121b are shown in Figures 13 and 14 respectively. FIG14 not only shows the second mesh layer 121 b , but also shows the partial structures of other conductive layers, which will not be described one by one here.

[0111] In some examples, as shown in FIG13 , the mesh pattern of the first mesh layer 121a is the same as the mesh pattern of the main mesh portion 122. In this case, along a direction perpendicular to the display panel 100, the first mesh layer 121a and the second mesh layer 121b have substantially the same coverage area. For example, the mesh patterns of the first mesh layer 121a and the main mesh portion 122 may also be different. The embodiments of the present disclosure do not limit the mesh patterns of the first mesh layer 121a and the second mesh layer 121b.

[0112] For example, the grid pattern of the first grid layer 121a may include the grid pattern of any of the embodiments described above, and the second grid layer 121b may include the grid pattern of any of the embodiments described above, which will not be described in detail here.

[0113] In some examples, as shown in Figures 13 to 15 , the first mesh layer 121a and the second mesh layer 121b have substantially the same mesh pattern in a direction perpendicular to the display panel 100, and the first mesh layer 121a and the second mesh layer 121b are substantially overlapped. This can reduce the capacitance difference between the first mesh layer 121a and the second mesh layer 121b.

[0114] In some examples, as shown in Figures 13 and 14, the conductive layer where the first grid layer 121a is located includes a common power line 110a, and the conductive layer where the second grid layer 121b is located includes a common power line 110b. The grid lines of the first grid layer 121a are connected to the common power line 110a, and the grid lines of the second grid layer 121b are connected to the common power line 110b. The common power line 110a and the common power line 110b are connected so that the first grid layer 121a and the second grid layer 121b are electrically connected to each other. The embodiments of the present disclosure do not limit the manner in which the first grid layer 121a and the second grid layer 121b are electrically connected to each other.

[0115] In some examples, as shown in Figures 13 to 15, the display panel 100 also includes a base substrate 130 and a pixel circuit driving layer 140 formed on the base substrate 130. The pixel circuit driving layer 140 includes a plurality of conductive patterns arranged in sequence along a direction perpendicular to the base substrate 130, and the plurality of conductive patterns include a first conductive pattern and a second conductive pattern. The first grid layer 121a and the main grid portion 122 are located on the same conductive layer 141 as the first conductive pattern, and the second grid layer 121b is located on the same conductive layer 142 as the second conductive pattern. The second grid layer 121b is located on the same conductive layer 142 as the second conductive pattern, so that the problem of heating in the local area can be solved without adding an additional film layer. For example, the conductive layer 141 and the conductive layer 142 are also referred to as source and drain metal layers.

[0116] For example, as shown in Figure 15, the metal mesh structure 120 of the embodiment of the present disclosure can be a multi-layered composite film, for example, a TIALTi film. Of course, the embodiment of the present disclosure is not limited to this, and can also be a single-layer film.

[0117] In some examples, as shown in Figures 13 to 15, the first grid layer 121a is located on a side of the second grid layer 121b away from the base substrate 130. In a direction perpendicular to the base substrate 130, the orthographic projection of the grid lines of the first grid layer 121a on the base substrate 130 falls within the orthographic projection of the grid lines of the second grid layer 121b on the base substrate 130. This prevents the grid lines of the first grid layer 121a from falling to the side or on the slope of the grid lines of the second grid layer 121b, thereby preventing the etching of the first grid layer 121a from being affected.

[0118] For example, in a direction perpendicular to the base substrate 130, the width of the grid lines of the second grid layer 121b is greater than or equal to 2 μm greater than the width of the grid lines of the first grid layer 121a, and the single-side boundary of the grid lines of the second grid layer 121b exceeds the corresponding single-side boundary of the grid lines of the first grid layer 121a by 1 μm. This can absorb process fluctuations or deviations and prevent the grid lines of the first grid layer 121a from falling on the sides or climbing up the grid lines of the second grid layer 121b.

[0119] In some examples, as shown in FIG. 14 , the second mesh layer 121 b is insulated from the second conductive pattern located in the display area, and the mesh lines of the second mesh layer 121 b are disconnected from the second conductive pattern.

[0120] FIG16 is a partial enlarged view of another second conductive layer of the display panel shown in FIG13 ; FIG17 is a partial cross-sectional schematic diagram of the display panel shown in FIG13 . As shown in FIG13 , FIG16 and FIG17 , the display panel 100 further includes a base substrate 130 , a pixel circuit driving layer 140 formed on the base substrate 130 , and a shielding metal layer located between the base substrate 130 and the pixel circuit driving layer 140 . The pixel circuit driving layer 140 includes a plurality of conductive patterns sequentially arranged in a direction perpendicular to the base substrate 130 , the plurality of conductive patterns including a first conductive pattern. The first mesh layer 121 a and the main mesh portion 122 are located on the same conductive layer 141 as the first conductive pattern, and the second mesh layer 121 b and the shielding metal layer are located on the same conductive layer 143. The shielding metal layer is located between the base substrate 130 and the pixel circuit driving layer 140. Compared with other conductive layers, the shielding metal layer is closer to the base substrate 130. Therefore, the second grid layer 121b and the shielding metal layer are located on the same conductive layer 143, which can not only reduce the current density, but also shunt the current downward, so that the heat at the higher-heating position is dissipated downward and outward faster. In addition, the second grid layer 121b and the shielding metal layer are located on the same conductive layer 143, so that the heating problem in the local area can be solved without adding an additional film layer. It should be noted that Figure 16 not only shows the second grid layer 121b, but also shows the local structure of other conductive layers, which will not be explained one by one here. Figure 17 only schematically shows the first grid layer 121a and the second grid layer 121b, and the other conductive layers will not be explained one by one.

[0121] In some examples, as shown in Figures 16 and 17, the shielding metal layer 150 includes a shielding pattern to shield charges in the base substrate 130, eliminating the adverse effects of the charges in the base substrate 130 on the transistors in the pixel circuit driving layer 140. The second mesh layer 121b is insulated from the shielding pattern, and the grid lines of the second mesh layer 121b are not connected to the shielding pattern. For example, the second mesh layer 121b is configured to receive a first power supply voltage (VSS), and the shielding pattern is configured to receive a second power supply voltage (VDD).

[0122] In some examples, as shown in Figures 13 and 16, the conductive layer 143 further includes a connecting structure 143a and a connecting via 143b. The grid lines of the second mesh layer 121b are connected to the connecting structure 143a. The connecting via 143b connects the connecting structure 143a to the common power line 110. The first mesh layer 121a is connected to the common power line 110. Thus, the second mesh layer 121b can be electrically connected to the first mesh layer 121a via the connecting structure 143a, the connecting via 143b, and the common power line 110. Of course, the embodiments of the present disclosure do not limit the connection method between the first mesh layer 121a and the second mesh layer 121b.

[0123] Figure 18 is a partial wiring diagram of the display panel shown in Figure 13; Figure 19 is a partial cross-sectional schematic diagram of the display panel shown in Figure 18. As shown in Figures 13, 18, and 19, the functional grid portion 121 also includes a third grid layer 121c located between the first grid layer 121a and the second grid layer 121b. The multiple conductive patterns also include a second conductive pattern, and the third grid layer 121c and the second conductive pattern are located in the same conductive layer 142. By connecting the first grid layer 121a, the second grid layer 121b, and the third grid layer 121c in parallel, the resistance per unit area of ​​the functional grid portion 121 can be further reduced, thereby further reducing the current density at the connection position P. In addition, the third grid layer 121c and the second conductive pattern are located in the same conductive layer 142, thereby solving the problem of localized heating without the need for additional film layers. Figure 19 only schematically illustrates the first grid layer 121a, the second grid layer 121b, and the third grid layer 121c; the other conductive layers are not described one by one.

[0124] For example, the plurality of conductive patterns further include a third conductive pattern, the peripheral area BB further includes a gate driving circuit formed on the base substrate 130, and the connection line between the gate driving circuit and the display area AA is located in the same conductive layer as the third conductive pattern. Of course, the present disclosure does not limit this.

[0125] In some examples, as shown in FIG19 , the mesh pattern of the third mesh layer 121 c is substantially the same as the mesh pattern of the first mesh layer 121 a. For example, the orthographic projection of the mesh lines of the first mesh layer 121 a on the base substrate 130 falls within the orthographic projection of the mesh lines of the third mesh layer 121 c on the base substrate 130. For example, the mesh lines of the third mesh layer 121 c are disconnected from the second conductive pattern.

[0126] Figure 20 is a partial wiring diagram of a display panel provided in accordance with an embodiment of the present disclosure; Figure 21 is a partial wiring diagram of the second mesh layer of the display panel shown in Figure 20; and Figure 22 is a partial cross-sectional schematic diagram of the display panel shown in Figure 20. As shown in Figures 20 and 22, the display panel 100 further includes a base substrate 130, a pixel circuit driving layer 140 formed on the base substrate 130, and a first electrode layer 144a formed on a side of the pixel circuit driving layer 140 facing away from the base substrate 130. The pixel circuit driving layer 140 includes a plurality of conductive patterns arranged in a direction perpendicular to the base substrate 130, including a first conductive pattern. The first mesh layer 121a and the main mesh portion 122 are located on the same conductive layer 141 as the first conductive pattern, while the second mesh layer 121b and the first electrode layer 144a are located on the same conductive layer 144. The second mesh layer 121b and the first electrode layer 144a are located on the same conductive layer 144, thereby resolving the problem of localized heating without the need for additional film layers. In addition, the second mesh layer 121b is located above the first mesh layer 121a, so that current can be diverted upward, which facilitates heat dissipation. For example, the first electrode layer 144a can be an anode, but this is not limited to this embodiment of the present disclosure. Figure 22 only schematically illustrates the first mesh layer 121a and the second mesh layer 121b, and other conductive layers are not described one by one.

[0127] In some examples, as shown in Figures 20 to 22, the mesh pattern of the second mesh layer 121b roughly overlaps with the mesh pattern of the first mesh layer 121a in a direction perpendicular to the base substrate 130, thereby reducing the capacitance difference between the first mesh layer 121a and the second mesh layer 121b.

[0128] In some examples, as shown in FIG. 20 , the grid lines of the second grid layer 121 b are not connected to the patterns of the first electrode layer 144 a located in the display area.

[0129] In some examples, as shown in Figures 20 to 22, the conductive layer 144 further includes a connecting structure 144b, and the second mesh layer 121b is connected to the connecting structure 144b. The conductive layer 141 includes a first mesh layer 121a and a common power line 110a. The common power line 110a at least partially overlaps with the connecting structure 144b in a direction perpendicular to the base substrate 130. The connection between the common power line 110a and the connecting structure 144b electrically connects the first mesh layer 121a and the second mesh layer 121b. Of course, the embodiments of the present disclosure do not limit the manner in which the first mesh layer 121a and the second mesh layer 121b are electrically connected.

[0130] For example, as shown in FIG22 , the second grid layer 121b may further include a pixel defining layer PDL on the side away from the base substrate 130. For example, the pixel defining layer PDL may further include a touch insulating layer TLD and a touch protection layer TOC on the side away from the base substrate 130, which are not described here one by one.

[0131] FIG23 is a schematic diagram of a partial wiring of a display panel provided in accordance with an embodiment of the present disclosure; FIG24 is a schematic diagram of a partial cross-section of FIG23 . As shown in FIG23 and FIG24 , the display panel 100 further includes a base substrate 130 and a plurality of insulating layers 150 . The metal grid structure 120 is located on the base substrate 130 , and the plurality of insulating layers 150 are located on a side of the metal grid structure 120 away from the base substrate 130 . In a direction perpendicular to the base substrate 130 , the thickness of the region where the plurality of insulating layers 150 overlap with the functional grid portion 121 is less than the thickness of other regions of the plurality of insulating layers 150 . By thinning the plurality of insulating layers 150 located on the functional grid portion 121 , heat at locations where heat is generated can be dissipated upward and outward more quickly.

[0132] The figure schematically shows that the functional grid portion 121 includes a first grid layer 121a and a second grid layer 121b, which is not limited in the present embodiment. For example, the metal grid structure 120 can also be any of the structures described above, which will not be described in detail here.

[0133] It should be noted that in order to clearly show the positional relationship between the thinning area A3 of the insulating layer 150 and the functional grid portion 121 in Figure 23, the figure schematically shows the thinning area A3 of the insulating layer 150. The thinning area A3 does not indicate that the insulating layer 150 is disconnected, but is the area where the thinning area A3 is located. The thinning area A3 overlaps with the functional grid portion 121, so the heat at the position where the heat is higher can be dissipated upward and outward faster.

[0134] For example, the regions where the thickness of the plurality of insulating layers 150 is reduced cover the functional grid portion 121 , thereby better dissipating heat.

[0135] 23 and 24 , the plurality of insulating layers 150 include a pixel defining layer PDL, a touch insulating layer TLD, and a touch protection layer TOC sequentially formed on the planarization layer PLN.

[0136] FIG25 is a schematic diagram of a display panel provided in one embodiment of the present disclosure; FIG26 is a partially enlarged schematic diagram of FIG25 . As shown in FIG25 and FIG26 , the display panel 100 further includes a first adapter line 161, a second adapter line 162, a first dummy line 171, and a second dummy line 172. The first adapter line 161 extends along a first direction X, and the second adapter line 162 extends along a second direction Y, and is disposed in a different layer from the first adapter line 161. The first dummy line 171 extends along the first direction X, and the second dummy line 172 extends along the second direction Y, and is disposed in a different layer from the first dummy line 171. The display panel 100 further includes a data line DT extending along the second direction Y. One end of the first transfer line 161 is connected to the data line DT via a first via V1, and the other end of the first transfer line 161 is connected to the second transfer line 162 via a second via V2. The first via V1 and the second via V2 form a first transfer area C1. The display panel 100 includes a display area AA and a peripheral area BB surrounding the display area AA. The peripheral area BB includes a bonding area CC. The first transfer area C1 is located on a side of the display area AA near the bonding area CC. The display panel 100 also includes a light-emitting element. The first and second dummy lines 171 and 172 are connected to the cathodes of the light-emitting elements and are configured to transmit a power supply voltage. The first and second dummy lines 171 and 172 are connected via a third via V3, which forms a plurality of second transfer areas C2.

[0137] It should be noted that the first transfer area C1 and the second transfer area C2 are functional partitions for ease of understanding during the description process. In order to clearly illustrate the direction of the first transfer line 161 and the second transfer line 162, the first transfer area C1 only schematically shows two data lines DT, two first transfer lines 161, and two second transfer lines 162. The V-shaped line in the first transfer area C1 is the connection line between the first via V1 and the second via V2, and is not a line in the display panel 100. In order to clearly illustrate the direction of the first dummy line 171 and the second dummy line 172, the second transfer area C2 only schematically shows two first dummy lines 171 and four second dummy lines 172. For example, the first dummy lines 171 and the second dummy lines 172 of the second transfer area C2 are both provided with third vias V3 at the overlapping position, so that the third vias V3 are arranged in a matrix along the first direction X and the second direction Y in the second transfer area C2. For example, the first dummy line 171 and the second dummy line 172 are only provided with the third via V3 at a partially overlapping position, and the third via V3 is arranged in a V shape in the second transfer area C2, that is, the V-shaped line in the second transfer area C2 is the connection line of the third via V3, and is not a routing line in the display panel 100.

[0138] In the display panel 100 provided in the embodiment of the present disclosure, by providing first and second adapter lines 161 and 162, the data lines DT can be connected to a region near the center of the display panel and then led to the binding region CC via leads. This reduces the width of the frame occupied by the leads, further reducing the frame size of the display panel 100. Disposing first and second dummy lines 171 and 172, connected to the cathodes of the light-emitting elements, in regions where the first and second adapter lines 161 and 162 are not provided not only reduces the voltage drop of the power supply voltage (VSS), thus lowering the power consumption of the display panel 100, but also improves display uniformity.

[0139] In some examples, as shown in Figures 25 and 26 , the display panel 100 further includes a common power line 110 located in the peripheral area BB, and the first dummy line 171 extends along the first direction X and is connected to the common power line 110. For example, the second dummy line 172 extends along the second direction Y and is connected to the common power line 110.

[0140] In some examples, as shown in Figures 4, 5, 25, and 26, the portion of the metal mesh structure 120 extending into the display area AA includes the second dummy line 172. The present disclosure is not limited to this. For example, the portion of the metal mesh structure 120 extending into the display area AA includes the first dummy line 171.

[0141] In some examples, the first jumper line 161 and the first dummy line 171 are disposed on the same layer, and the first jumper line 161 and the first dummy line 171 disposed on the same layer are insulated from each other.

[0142] In some examples, the second jumper line 162 and the second dummy line 172 are disposed on the same layer, and the second jumper line 162 and the second dummy line 172 disposed on the same layer are insulated from each other.

[0143] In some examples, the display panel 100 further includes a base substrate and a pixel circuit driving layer formed on the base substrate. The pixel circuit driving layer includes a plurality of conductive patterns arranged in sequence along a direction perpendicular to the base substrate, the plurality of conductive patterns including a first conductive pattern and a second conductive pattern. The first patch line 161 and the first dummy line 171 are located in the same conductive layer as the first conductive pattern, and the second patch line 162 and the second dummy line 172 are located in the same conductive layer as the second conductive pattern. For example, the conductive layer in which the conductive patterns are located is also referred to as a source / drain metal layer.

[0144] In some examples, as shown in Figures 25 and 26, the lines connecting the multiple first vias V1 and the multiple second vias V2 in the first transition area C1 are in a set shape, and the lines connecting the multiple third vias V3 in the second transition area C2 are approximately in a set shape. For example, the first transition area C1 includes a line with a set shape. For example, the second transition area C2 includes multiple lines with a set shape. For example, the multiple lines with a set shape in the second transition area C2 are arranged along the second direction Y. For example, the set shape can be a V-shape as shown in the figure. The embodiments of the present disclosure do not limit the set shape.

[0145] FIG27 is another schematic diagram of a display panel provided in accordance with an embodiment of the present disclosure; FIG28 is a partially enlarged schematic diagram of FIG27 . As shown in FIG27 and FIG28 , the display panel 100 includes a third adapter line 163, a fourth adapter line 164, a third dummy line 173, and a fourth dummy line 174. The display panel 100 also includes a data line DT. The third adapter line 163 extends along a first direction X, and the fourth adapter line 164 extends along a second direction Y and is disposed in a different layer from the third adapter line 163. The third dummy line 173 extends along the first direction X, and the fourth dummy line 174 extends along the second direction Y and is disposed in a different layer from the third dummy line 173. The data line DT extends along the second direction Y. One end of the third transfer line 163 is connected to the data line DT through a fourth via V4. The other end of the third transfer line 163 is connected to the fourth transfer line 164 through a fifth via V5. The fourth via V4 and the fifth via V5 form a plurality of third transfer areas C3. The plurality of third transfer areas C3 are arranged at intervals along the first direction X. The display panel 100 has a display area AA and a peripheral area BB surrounding the display area AA. The peripheral area BB includes a binding area CC. The plurality of third transfer areas C3 are located on a side of the display area AA close to the binding area CC.

[0146] The display panel 100 further includes a light-emitting element. A third dummy line 173 and a fourth dummy line 174 are connected to the cathode of the light-emitting element and are configured to transmit a power supply voltage. The third dummy line 173 and the fourth dummy line 174 are connected via a sixth via V6, which forms a plurality of fourth transfer areas C4. Along the first direction X, at least one fourth transfer area C4 is located between the plurality of third transfer areas C3.

[0147] It should be noted that the third transfer area C3 and the fourth transfer area C4 are functional areas for ease of understanding during the description. To clearly illustrate the orientation of the third transfer lines 163 and the fourth transfer lines 164, the third transfer area C3 only schematically illustrates two data lines DT, two third transfer lines 163, and two fourth transfer lines 164. The V-shaped lines in the third transfer area C3 are the lines connecting the fourth vias V4 and the fifth vias V5 and do not represent the wiring in the display panel 100. To clearly illustrate the orientation of the third dummy lines 173 and the fourth dummy lines 174, the fourth transfer area C4 only schematically illustrates two third dummy lines 173 and four fourth dummy lines 174. For example, the third dummy lines 173 and the fourth dummy lines 174 of the fourth transfer area C4 are both provided with sixth vias V6 at their overlapping positions, so that the sixth vias V6 are arranged in a matrix along the first direction X and the second direction Y within the fourth transfer area C4. For example, the third dummy line 173 and the fourth dummy line 174 are only provided with the sixth via V6 at the partially overlapping position, and the sixth via V6 is arranged in a V-row in the fourth transfer area C4, that is, the V-shaped line in the fourth transfer area C4 is the connection line of the sixth via V6, and is not a routing line in the display panel 100.

[0148] In the display panel 100 provided in the embodiment of the present disclosure, the data line DT can be transferred to a region near the center of the display panel 100 via the third transfer line 163 and the fourth transfer line 164 in the third transfer area C3, and then led to the binding area CC via leads. This reduces the width of the frame occupied by the leads, further reducing the frame size of the display panel 100. Disposing a first dummy line 171 and a second dummy line 172 connected to the cathode of the light-emitting element in an area where the third transfer line 163 and the fourth transfer line 164 are not provided not only reduces the voltage drop of the power supply voltage (VSS), thus reducing the power consumption of the display panel 100, but also improves display uniformity.

[0149] Along the first direction X, at least one fourth transfer area C4 is located between multiple third transfer areas C3, so that the fourth virtual line 174 of the fourth transfer area C4 located between the multiple third transfer areas C3 can be led to the binding area CC through the lead L, and then, the current of the common power line 110 located in the peripheral area BB can be dispersed, and the current density of the common power line 110 located in the peripheral area BB can be reduced, so that the current density of the common power line 110 located in the peripheral area BB will not be too large when passing through the corner position of the display panel 100, and the current density of the common power line 110 located in the peripheral area BB at the position where the width changes will not be too large, thereby solving the heating problem in local areas such as the corner position or the position where the width changes.

[0150] For example, as shown in Figures 5, 27 and 28, the fourth dummy line 174 of the fourth transfer area C4 located between multiple third transfer areas C3 is led to the binding area CC through the lead L, which can reduce the current of the common power line 110 located in the peripheral area BB in Figure 5, reduce the current density at the connection position P, and solve the problem of heating in the local area.

[0151] 27 and 28 , the plurality of fourth transition areas C4 are located between the plurality of third transition areas C3 along the first direction X. For example, along the first direction X, the plurality of fourth transition areas C4 and the plurality of third transition areas C3 are alternately distributed.

[0152] In some examples, as shown in Figures 27 and 28, the display panel 100 further includes a lead L. The lead L is located between the display area AA and the binding area CC. The binding area CC includes a common power terminal, which is configured to transmit a common power signal, and one end of the lead L is connected to the common power terminal. The plurality of fourth transfer areas C4 include a first sub-area C41. Along the first direction X, the first sub-area C41 is located between the plurality of third transfer areas C3, and the fourth dummy line 174 of the first sub-area C41 is connected to the other end of the lead L. The fourth dummy line 174 of the first sub-area C41 located between the plurality of third transfer areas C3 can be led out from the display area AA and connected to the common power terminal of the binding area CC through the lead L, thereby dispersing the current of the common power line 110 located in the peripheral area BB, thereby solving the heating problem in local areas such as corner positions or width change positions.

[0153] 28 , the third routing line 163 and the third dummy line 173 are disposed on the same layer. The third routing line 163 and the third dummy line 173 disposed on the same layer are insulated from each other.

[0154] 28 , the fourth jumper line 164 and the fourth dummy line 174 are disposed on the same layer. The fourth jumper line 164 and the fourth dummy line 174 disposed on the same layer are insulated from each other.

[0155] In some examples, the display panel 100 further includes a base substrate 130 and a pixel circuit driving layer 140 formed on the base substrate 130. The pixel circuit driving layer 140 includes a plurality of conductive patterns sequentially arranged in a direction perpendicular to the base substrate 130, the plurality of conductive patterns including a first conductive pattern 141 and a second conductive pattern 142. The third connecting line 163 and the third dummy line 173 are located on the first conductive pattern 141, and the fourth connecting line 164 and the fourth dummy line 174 are located on the second conductive pattern 142.

[0156] In some examples, as shown in Figures 27 and 28, the lines connecting the plurality of fourth vias V4 and the plurality of fifth vias V5 in the third transition area C3 are in a set shape, and the lines connecting the plurality of sixth vias V6 in the fourth transition area C4 are approximately in a set shape. For example, the third transition area C3 includes a line of a set shape. For example, the fourth transition area C4 includes a plurality of lines of a set shape. For example, the plurality of lines of a set shape in the fourth transition area C4 are arranged along the second direction Y. For example, the set shape can be a V-shape as shown in the figure. The embodiments of the present disclosure do not limit the set shape.

[0157] In some examples, as shown in Figures 4, 5, 27, and 28, the portion of the metal mesh structure 120 extending into the display area AA includes a fourth dummy line 174. The present disclosure is not limited to this. For example, the portion of the metal mesh structure 120 extending into the display area AA includes a third dummy line 173.

[0158] Figure 29 is a plan view of a common power grid layer of a display panel provided in accordance with an embodiment of the present disclosure; Figure 30 is a partial schematic view of the common power grid layer shown in Figure 29; and Figure 31 is a cross-sectional view of Figure 29. As shown in Figures 29 to 31, the display panel 100 includes a base substrate 130, a pixel circuit driver layer 140, and a common power grid layer 180. The pixel circuit driver layer 140 is located on the base substrate 130, and the common power grid layer 180 is located on a side of the pixel circuit driver layer 140 away from the base substrate 130. The display panel 100 includes a display area AA and a peripheral area BB surrounding the display area AA. The common power grid layer includes grid traces 181 located in the display area AA and peripheral common power lines 182 located in the peripheral area BB. The peripheral area BB includes a bonding area CC. The display panel 100 also includes leads L located between the display area AA and the bonding area CC. Binding region CC includes a common power terminal configured to transmit a common power signal. One end of lead L is connected to the common power terminal, and the other end of lead L is connected to a grid trace 181 of a common power grid layer 180. It should be noted that FIG29 schematically illustrates only a portion of the grid lines of the common power grid layer 180, and FIG31 schematically illustrates only the common power grid layer 180. Other conductive layers are not described in detail.

[0159] In the display panel 100 provided in the embodiment of the present disclosure, a common power grid layer 180 is provided, and the grid traces 181 of the common power grid layer 180 are connected to the common power terminals of the bonding area CC via leads L. This disperses the current of the peripheral common power lines 182 located in the peripheral area BB, reducing the current density of the peripheral common power lines 182 located in the peripheral area BB. This prevents the current density of the peripheral common power lines 182 located in the peripheral area BB from being excessive when passing through the corners of the display panel 100, and also prevents the current density of the peripheral common power lines 182 located in the peripheral area BB from being excessive at locations where the width changes. This solves the problem of heating in localized areas such as corners or locations where the width changes.

[0160] In some examples, as shown in FIG. 29 and FIG. 30 , the grid traces 181 located in the display area are connected to the peripheral common power lines 182 located in the peripheral area.

[0161] In some examples, as shown in Figures 29 and 30, the peripheral common power line 182 includes a third line segment 182a having a third line width and a fourth line segment 182b having a fourth line width. The third line width and the fourth line width are different, and the third line segment 182a and the fourth line segment 182b are directly connected. Due to the different line widths of the third line segment 182a and the fourth line segment 182b, the line width of the peripheral common power line 182 changes at the connection point Q between the third line segment 182a and the fourth line segment 182b. The current density at the connection point Q between the third line segment 182a and the fourth line segment 182b is greater than at other locations, which can easily cause localized heating. By connecting the grid traces 181 of the common power grid layer 180 to the common power terminals of the bonding area CC, the current in the peripheral common power line 182 located in the peripheral area BB can be dispersed, reducing the current density of the peripheral common power line 182 located in the peripheral area BB and solving the problem of localized heating. In some examples, as shown in Figure 30, the fourth line width of fourth line segment 182b is smaller than the third line width of third line segment 182a. Due to the smaller line width, the current density at the connection point Q between fourth line segment 182b and third line segment 182a is too high, which can easily cause localized heating. By connecting the grid traces 181 of the common power grid layer 180 to the common power terminals of the bonding area CC, the current of the surrounding common power lines 182 in the peripheral area BB can be dispersed, solving the problem of localized heating.

[0162] In some examples, as shown in Figures 29 and 30, the extension direction of third line segment 182a is different from the extension direction of fourth line segment 182b. For example, the intersection Q of third line segment 182a and fourth line segment 182b is located at a corner region of the display panel. For example, as shown in Figure 4, first line segment 111 and second line segment 112 are located at the intersection region of two adjacent sides of display panel 100.

[0163] In some examples, as shown in Figures 29 and 30, the third line segment 182a includes an arc segment that is directly connected to the fourth line segment 182b. For example, the arc segment is located at a corner region of the display panel. For example, the arc segment is located at the intersection region of two adjacent sides of the display panel.

[0164] In some examples, as shown in Figures 29 and 30, the ratio of the third line width to the fourth line width is greater than or equal to 2. By reducing the fourth line width of fourth line segment 182b, the border on the side where fourth line segment 182b is located can be narrowed, thereby achieving a narrow border. The present disclosure does not limit the ratio of the third line width to the fourth line width and can be designed according to the requirements of the display panel. For example, the ratio can also be greater than or equal to 2.5, or greater than or equal to 3.

[0165] For example, the peripheral area BB includes a binding area, and the fourth line segment 182b is located on a side of the display area AA that is close to the binding area. By reducing the fourth line width of the fourth line segment 182b, the border of the display area AA on the side close to the binding area can be narrowed. For example, as shown in Figures 29 and 30, the border on the side where the fourth line segment is located can be the bottom border of the display panel.

[0166] In some examples, as shown in FIG. 31 , the display panel further includes a light emitting device layer EL, which is located on a side of the common power grid layer 180 away from the base substrate 130 .

[0167] For example, as shown in FIG31 , a planarization layer PLN may be further included between the common power grid layer 180 and the light emitting device layer EL.

[0168] In some examples, the display panel 100 further includes a plurality of pixels, each pixel including an active light-emitting area and a non-display area AA surrounding the active light-emitting area. The orthographic projection of the grid lines of the common power grid layer 180 on the base substrate 130 is within the orthographic projection of the non-display area AA on the base substrate 130. The grid lines of the common power grid layer are arranged in the non-display area AA of the active light-emitting area to avoid affecting the active light-emitting area.

[0169] FIG32 is another cross-sectional schematic diagram of the display panel shown in FIG29 ; FIG33 is a plan schematic diagram of the metal grid structure of FIG32 . As shown in FIG29 , FIG30 , FIG32 , and FIG33 , the display panel 100 further includes a common power supply line 110 and a metal grid structure 120. The common power supply line 110 is located in the peripheral area BB. The metal grid structure 120 is located in the peripheral area BB and on the side of the common power supply line 110 that is closer to the display area AA. The metal grid structure 120 is connected to the common power supply line 110, and a portion of the metal grid structure 120 extends into the display area AA. The pixel circuit driving layer 140 includes a plurality of conductive patterns sequentially arranged in a direction perpendicular to the base substrate 130. The plurality of conductive patterns include a first conductive pattern. The common power supply line and the metal grid structure are located on the same conductive layer as the first conductive pattern. By connecting the grid trace 181 of the common power grid layer 180 to the common power terminal of the binding area CC, the current of the common power line 110 located in the peripheral area BB can also be dispersed, reducing the current density of the common power line 110 located in the peripheral area BB, thereby solving the problem of local area heating.

[0170] In some examples, as shown in FIG33 , common power line 110 includes line segment 111 and line segment 112. Line segment 111 has a different line width than line segment 112, and line segment 111 and line segment 112 are directly connected. Metal grid structure 120 is located at location P where line segment 111 and line segment 112 are connected. Due to the different line widths of line segment 111 and line segment 112, the line width of common power line 110 changes, and the current density at location P where line segment 111 and line segment 112 are connected is greater than at other locations. By connecting grid trace 181 of common power grid layer 180 to the common power terminal of binding area CC, the current of common power line 110 located in peripheral area BB can also be dispersed, reducing the current density of common power line 110 located in peripheral area BB and solving the problem of heating in local areas.

[0171] In some examples, as shown in FIGS. 30 , 32 , and 33 , the metal mesh structure 120 has substantially the same mesh pattern as the common power mesh layer 180 .

[0172] For example, along a direction perpendicular to the base substrate 130, the line segment 111 corresponds to the third line segment 182a, the line segment 112 corresponds to the fourth line segment 182b, and the connection position P corresponds to the connection position Q. For example, along a direction perpendicular to the base substrate 130, the line segment 111 overlaps with the third line segment 182a, the line segment 112 overlaps with the fourth line segment 182b, and the connection position P overlaps with the connection position Q.

[0173] In some examples, as shown in FIG. 33 , the metal mesh structure 120 may be the metal mesh structure 120 of any of the embodiments described above, which will not be described in detail here.

[0174] An embodiment of the present disclosure provides a display device. FIG34 is a schematic diagram of a display device provided by an embodiment of the present disclosure. As shown in FIG34 , the display device 200 includes any of the display panels 100 described above.

[0175] For example, the display device 200 may be a display device 200 having a display function, such as a television, a computer monitor, a laptop computer, a tablet computer, a smart phone, a navigation system, an electronic picture frame, or a car display.

[0176] There are a few points to note:

[0177] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to conventional designs.

[0178] (2) Unless there is any conflict, the features of the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0179] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel having a display area and a peripheral area surrounding the display area. The display panel includes a common power supply line located in the peripheral area and a metal mesh structure located in the peripheral area. The metal mesh structure is located on a side of the common power supply line closer to the display area. The metal mesh structure is connected to the common power supply line and a part of the trace of the metal mesh structure extends into the display area. The common power supply line includes a first segment having a first line width and a second segment having a second line width. The first line width and the second line width are different, and the first segment and the second segment are directly connected. The metal mesh structure includes a functional mesh portion and a main body mesh portion. The functional mesh portion is closer to the connection position of the first segment and the second segment than the main body mesh portion. The resistance per unit area of the functional mesh portion is less than the resistance per unit area of the main body mesh portion.

2. The display panel according to claim 1, wherein, The extending direction of the first segment is different from the extending direction of the second segment.

3. The display panel according to claim 1, wherein, The first segment includes an arc segment, and the arc segment is directly connected to the second segment.

4. The display panel according to claim 1, wherein, The main body mesh portion includes a first mesh portion and a second mesh portion. The first mesh portion and the second mesh portion are located on both sides of the functional mesh portion. The first mesh portion is connected to the first segment, the second mesh portion is connected to the second segment, and the functional mesh portion is connected to both the first segment and the second segment.

5. The display panel according to claim 4, wherein, All the grid lines in the first mesh portion are connected to the first segment, and all the grid lines in the second mesh portion are connected to the second segment.

6. The display panel according to claim 1, wherein, The ratio of the first line width to the second line width is greater than or equal to 2.

7. The display panel according to claim 1, wherein, The peripheral area includes a bonding area. Wherein, the second line width is less than the first line width, and the second segment is located on a side of the display area closer to the bonding area.

8. The display panel according to any one of claims 1-7, wherein, The functional mesh portion and the main body mesh portion are arranged on the same layer. The number of grid lines per unit area of the functional mesh portion is greater than the number of grid lines per unit area of the main body mesh portion.

9. The display panel according to any one of claims 1-8, wherein, The functional mesh portion and the main body mesh portion are arranged on the same layer. The line width of the grid lines of the functional mesh portion is greater than the line width of the grid lines of the main body mesh portion.

10. The display panel according to any one of claims 1-9, wherein, The functional mesh portion and the main body mesh portion are arranged on the same layer. Along the direction from the functional mesh portion to the main body mesh portion, the number of grid lines per unit area of the functional mesh portion decreases in sequence.

11. The display panel according to any one of claims 1-10, wherein, The functional mesh portion and the main body mesh portion are arranged on the same layer. The main body mesh portion has a first mesh pattern, and the functional mesh portion has a second mesh pattern. The second mesh pattern includes the first mesh pattern and a plurality of straight line segments. The plurality of straight line segments extend divergently from a side of the functional mesh portion closer to the display area to the common power supply line.

12. The display panel according to any one of claims 1-7, wherein, The functional mesh portion includes a first mesh layer and a second mesh layer that are electrically connected to each other. The first mesh layer is arranged on the same layer as the main body mesh portion, and the first mesh layer and the second mesh layer are arranged on different layers.

13. The display panel according to claim 12, wherein, In a direction perpendicular to the display panel, the first mesh layer and the second mesh layer have substantially the same mesh pattern.

14. The display panel according to claim 12 further includes: a substrate substrate and a pixel circuit driving layer formed on the substrate substrate, wherein the pixel circuit driving layer includes a plurality of conductive patterns sequentially arranged in a direction perpendicular to the substrate substrate, and the plurality of conductive patterns include a first conductive pattern and a second conductive pattern, the first grid layer and the main grid portion are in the same conductive layer as the first conductive pattern, and the second grid layer is in the same conductive layer as the second conductive pattern.

15. The display panel according to claim 14, wherein, The first grid layer is located on a side of the second grid layer away from the substrate substrate, in a direction perpendicular to the substrate substrate, a positive projection of grid lines of the first grid layer on the substrate substrate falls within a positive projection of grid lines of the second grid layer on the substrate substrate.

16. The display panel according to claim 12 further includes: a substrate substrate, a pixel circuit driving layer formed on the substrate substrate, and a shielding metal layer located between the substrate substrate and the pixel circuit driving layer, wherein the pixel circuit driving layer includes a plurality of conductive patterns sequentially arranged in a direction perpendicular to the substrate substrate, and the plurality of conductive patterns include a first conductive pattern, the first grid layer and the main grid portion are in the same conductive layer as the first conductive pattern, and the second grid layer is in the same conductive layer as the shielding metal layer.

17. The display panel according to claim 16, wherein, The functional grid portion further includes a third grid layer located between the first grid layer and the second grid layer, the plurality of conductive patterns further include a second conductive pattern, and the third grid layer is in the same conductive layer as the second conductive pattern.

18. The display panel according to claim 12 further includes: a substrate substrate, a pixel circuit driving layer formed on the substrate substrate, and a first electrode layer formed on a side of the pixel circuit driving layer away from the substrate substrate, wherein the pixel circuit driving layer includes a plurality of conductive patterns sequentially arranged in a direction perpendicular to the substrate substrate, and the plurality of conductive patterns include a first conductive pattern, the first grid layer and the main grid portion are in the same conductive layer as the first conductive pattern, and the second grid layer is in the same conductive layer as the first electrode layer.

19. The display panel according to any one of claims 1-18 further includes: a substrate substrate, and the metal grid structure is located on the substrate substrate; a plurality of insulating layers located on a side of the metal grid structure away from the substrate substrate, wherein, in a direction perpendicular to the substrate substrate, a thickness of a region where the plurality of insulating layers overlap with the functional grid portion is less than a thickness of other regions of the plurality of insulating layers.

20. The display panel according to any one of claims 1-19 further includes: a first jumper wire extending in a first direction; a second jumper wire extending in a second direction and arranged in a different layer from the first jumper wire; a first dummy wire extending in the first direction; a second dummy wire extending in the second direction and arranged in a different layer from the first dummy wire; a data line extending in the second direction, One end of the first jumper wire is connected to the data line through a first via hole, and the other end of the first jumper wire is connected to the second jumper wire through a second via hole. The first via hole and the second via hole form a first transfer area. The peripheral area includes a bonding area. The first transfer area is located on a side of the display area close to the bonding area. The display panel further includes a light-emitting element. The first dummy wire and the second dummy wire are connected to a cathode of the light-emitting element and are configured to transmit a power supply voltage. The first dummy wire and the second dummy wire are connected through a third via hole. The third via hole forms a plurality of second transfer areas.

21. The display panel according to claim 20, wherein, The partial trace of the metal mesh structure extending into the display area includes the first dummy wire, or the partial trace of the metal mesh structure extending into the display area includes the second dummy wire.

22. The display panel according to claim 20, further comprising: a substrate and a pixel circuit driving layer formed on the substrate, wherein the pixel circuit driving layer includes a plurality of conductive patterns sequentially arranged in a direction perpendicular to the substrate. The plurality of conductive patterns include a first conductive pattern and a second conductive pattern. The first jumper wire and the first dummy wire are located in the same conductive layer as the first conductive pattern, and the second jumper wire and the second dummy wire are located in the same conductive layer as the second conductive pattern.

23. The display panel according to any one of claims 1-19, further comprising: a third jumper wire extending in a first direction; a fourth jumper wire extending in a second direction and arranged in a different layer from the third jumper wire; a third dummy wire extending in the first direction; a fourth dummy wire extending in the second direction and arranged in a different layer from the third dummy wire; a data line extending in the second direction, wherein one end of the third jumper wire is connected to the data line through a fourth via hole, and the other end of the third jumper wire is connected to the fourth jumper wire through a fifth via hole. The fourth via hole and the fifth via hole form a plurality of third transfer areas. The plurality of third transfer areas are arranged at intervals in the first direction. The display panel has a display area and a peripheral area surrounding the display area. The peripheral area includes a bonding area. The plurality of third transfer areas are located on a side of the display area close to the bonding area. The display panel further includes a light-emitting element. The third dummy wire and the fourth dummy wire are connected to a cathode of the light-emitting element and are configured to transmit a power supply voltage. The third dummy wire and the fourth dummy wire are connected through a sixth via hole. The sixth via hole forms a plurality of fourth transfer areas. In the first direction, at least one of the fourth transfer areas is located between the plurality of third transfer areas.

24. The display panel according to claim 23, further comprising: a lead located between the display area and the bonding area, wherein the bonding area includes a common power supply terminal configured to transmit a common power supply signal. One end of the lead is connected to the common power supply terminal. The plurality of fourth transfer areas include a first sub-area. In the first direction, the first sub-area is located Between the multiple third transfer regions, the fourth dummy line of the first sub-region is connected to the other end of the lead.

25. The display panel according to any one of claims 1-24, further comprising: A substrate; A pixel circuit driving layer located on the substrate; And A common power grid layer located on a side of the pixel circuit driving layer away from the substrate, wherein the pixel circuit driving layer includes a plurality of conductive patterns sequentially arranged in a direction perpendicular to the substrate, and the metal grid structure and the common power line are located in the same conductive layer as the conductive patterns, The common power grid layer includes grid traces located in the display region and peripheral common power lines located in the peripheral region, The peripheral region includes a bonding region, the display panel further includes a lead, the lead is located between the display region and the bonding region, the bonding region includes a common power terminal configured to transmit a common power signal, one end of the lead is connected to the common power terminal, and the other end of the lead is connected to the grid trace of the common power grid layer.

26. The display panel according to claim 25, further comprising: A light-emitting device layer located on a side of the common power grid layer away from the substrate.

27. The display panel according to claim 25, further comprising: A plurality of pixels, each pixel including an effective light-emitting region and a non-display region surrounding the effective light-emitting region, wherein a positive projection of the grid line of the common power grid layer on the substrate is within a positive projection of the non-display region on the substrate.

28. A display panel, comprising: A third transfer line extending in a first direction; A fourth transfer line extending in a second direction and disposed in a different layer from the third transfer line; A third dummy line extending in the first direction; A fourth dummy line extending in the second direction and disposed in a different layer from the third dummy line; A data line extending in the second direction, wherein one end of the third transfer line is connected to the data line through a fourth via, the other end of the third transfer line is connected to the fourth transfer line through a fifth via, the fourth via and the fifth via form a plurality of third transfer regions, and the plurality of third transfer regions are arranged at intervals along the first direction The display panel has a display region and a peripheral region surrounding the display region, the peripheral region includes a bonding region, and the plurality of third transfer regions are located on a side of the display region close to the bonding region, The display panel further includes a light-emitting element, the third dummy line and the fourth dummy line are connected to a cathode of the light-emitting element and configured to transmit a power supply voltage, and the third dummy line and the fourth dummy line are connected through a sixth via, and the sixth via forms a plurality of fourth transfer regions, Along the first direction, at least one of the fourth transfer regions is located between the plurality of third transfer regions.

29. The display panel according to claim 28, further comprising: A lead located between the display region and the bonding region Among them, the bonding area includes a common power terminal configured to transmit a common power signal, and one end of the lead is connected to the common power terminal. The plurality of fourth transfer areas include a first sub-area. Along the first direction, the first sub-area is located between the plurality of third transfer areas, and the fourth dummy line of the first sub-area is connected to the other end of the lead.

30. The display panel according to claim 28, wherein The third transfer wire is disposed on the same layer as the third dummy line.

31. The display panel according to claim 28, wherein, The fourth transfer wire is disposed on the same layer as the fourth dummy line.

32. The display panel according to any one of claims 28-31, further comprising: a substrate substrate and a pixel circuit driving layer formed on the substrate substrate. Among them, the pixel circuit driving layer includes a plurality of conductive patterns sequentially disposed in a direction perpendicular to the substrate substrate. The plurality of conductive patterns include a first conductive pattern and a second conductive pattern. The third transfer wire and the third dummy line are located in the first conductive pattern, and the fourth transfer wire and the fourth dummy line are located in the second conductive pattern.

33. A display panel, comprising: a substrate substrate; a pixel circuit driving layer located on the substrate substrate; and a common power grid layer located on a side of the pixel circuit driving layer away from the substrate substrate. Among them, the display panel has a display area and a peripheral area surrounding the display area. The common power grid layer includes grid traces located in the display area and peripheral common power lines located in the peripheral area. The peripheral area includes a bonding area. The display panel further includes a lead located between the display area and the bonding area. The bonding area includes a common power terminal configured to transmit a common power signal. One end of the lead is connected to the common power terminal, and the other end of the lead is connected to the grid traces of the common power grid layer.

34. The display panel according to claim 33, wherein, The peripheral common power lines include a third line segment having a third line width and a fourth line segment having a fourth line width. The third line width and the fourth line width are different, and the third line segment and the fourth line segment are directly connected.

35. The display panel according to claim 33, further comprising: a light-emitting device layer located on a side of the common power grid layer away from the substrate substrate.

36. The display panel according to claim 33, further comprising: a plurality of pixels, each pixel including an effective light-emitting area and a non-display area surrounding the effective light-emitting area. Among them, the orthographic projection of the grid lines of the common power grid layer on the substrate substrate is within the orthographic projection of the non-display area on the substrate substrate.

37. The display panel according to claim 33, further comprising: common power traces located in the peripheral area; and a metal grid structure located in the peripheral area and on a side of the common power line close to the display area. Among them, the metal grid structure is connected to the common power line, and part of the traces of the metal grid structure extends into the display area. The pixel circuit driving layer includes a plurality of conductive patterns sequentially arranged in a direction perpendicular to the substrate, and the plurality of conductive patterns include a first conductive pattern. The common power supply trace and the metal mesh structure are located in the same conductive layer as the first conductive pattern.

38. A display device, comprising the display panel according to any one of claims 1-27, or the display panel according to any one of claims 28-32, or the display panel according to any one of claims 33-37.

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