Detection substrate and flat panel detector

Abstract

Disclosed in the embodiments of the present disclosure are a detection substrate and a flat panel detector. The detection substrate comprises: a base substrate, and a gate metal layer, a source-drain metal layer, a photoelectric conversion device and a bias voltage electrode layer which are sequentially stacked on the base substrate. The gate metal layer comprises a gate electrode and a scanning line electrically connected to the gate electrode. The source-drain metal layer comprises a first electrode, a second electrode and a first connecting part electrically connected to the second electrode. The photoelectric conversion layer comprises a bottom electrode, a photoelectric conversion layer and a top electrode which are sequentially stacked, wherein the bottom electrode is close to the base substrate, and the bottom electrode is electrically connected to the first electrode. The bias voltage electrode layer comprises a bias voltage line and a first reading line which extend in the same direction and are spaced apart. The detection substrate further comprises a second connecting part arranged on the same layer as the bottom electrode, wherein the first reading line is electrically connected to the second connecting part, and the second connecting part is electrically connected to the first connecting part.

Description

Detection substrate and flat panel detector Technical Field

[0001] The present disclosure relates to the field of photoelectric detection technology, and in particular to a detection substrate and a flat panel detector. Background Art

[0002] Flat X-ray Panel Detector (FPXD) based on Thin Film Transistor (TFT) technology is a crucial component in digital imaging technology. Due to its advantages such as fast imaging speed, good spatial and density resolution, high signal-to-noise ratio, and direct digital output, it is widely used in medical imaging (such as chest X-ray), industrial inspection (such as metal flaw detection), security inspection, air transportation and other fields.

[0003] X-ray flat panel detectors primarily consist of thin-film transistors (TFTs) and photoelectric converters. Under X-ray irradiation, the scintillator or phosphor layer of an indirect conversion X-ray flat panel detector converts X-ray photons into visible light. The photoelectric converter then converts the visible light into an electrical signal, which is then read by the TFTs and output to display the image.

[0004] Summary of the Invention

[0005] The present disclosure provides a detection substrate and a flat panel detector, and the specific solutions are as follows:

[0006] The present disclosure provides a detection substrate, comprising: a base substrate, and a gate metal layer, a source / drain metal layer, a photoelectric conversion device, and a bias voltage electrode layer arranged on the base substrate; wherein,

[0007] The gate metal layer includes a gate and a scan line electrically connected to the gate;

[0008] The source-drain metal layer includes a first electrode, a second electrode, and a first connecting portion electrically connected to the second electrode;

[0009] The photoelectric conversion device comprises a bottom electrode, a photoelectric conversion layer and a top electrode stacked in sequence, wherein the bottom electrode is close to the substrate and is electrically connected to the first electrode;

[0010] The bias voltage electrode layer includes bias voltage lines and first read lines extending in the same direction and spaced apart from each other;

[0011] The detection substrate further includes a second connection portion provided in the same layer as the bottom electrode, the first readout line is electrically connected to the second connection portion, and the second connection portion is electrically connected to the first connection portion.

[0012] In a possible implementation, the detection substrate provided in the embodiment of the present disclosure further includes: a first insulating layer located between the source / drain metal layer and the bottom electrode, and a planar layer located between the top electrode and the bias voltage electrode layer; wherein,

[0013] The first connection portion is electrically connected to the second connection portion through a first via hole penetrating the first insulating layer, and the second connection portion is electrically connected to the first readout line through a first outer hole penetrating the planar layer.

[0014] In a possible implementation, the detection substrate provided in the embodiment of the present disclosure further includes: a first buffer layer located between the top electrode and the flat layer, and a second buffer layer located between the flat layer and the bias voltage electrode layer; wherein,

[0015] The second connecting portion is also electrically connected to the first reading line through a first inner hole that passes through the first buffer layer and the second buffer layer. The first inner hole and the first outer hole are arranged to form a second via hole. The orthographic projection of the first inner hole on the base substrate is located within the orthographic projection range of the first outer hole on the base substrate. The inner wall of the first inner hole covers the inner wall of the first outer hole.

[0016] In a possible implementation, in the detection substrate provided in an embodiment of the present disclosure, an orthographic projection of the first outer hole on the base substrate does not overlap with an orthographic projection of the first via hole on the base substrate.

[0017] In one possible implementation, in the above-mentioned detection substrate provided in an embodiment of the present disclosure, the difference between the radius of the first outer hole and the radius of the first inner hole is at least greater than or equal to a first distance, the distance between the adjacent side walls of the first outer hole and the first via hole is greater than or equal to a second distance, and the ratio of the first distance to the second distance is 3:1 to 1:2.

[0018] In a possible implementation, in the detection substrate provided in an embodiment of the present disclosure, the first distance is 2 μm to 7 μm, and the second distance is 1 μm to 5 μm.

[0019] In a possible implementation, in the above-mentioned detection substrate provided by an embodiment of the present disclosure, the bias voltage electrode layer further includes a third connection portion electrically connected to the first read line, and the third connection portion is electrically connected to the second connection portion through the second via hole; wherein,

[0020] Orthographic projections of the first connecting portion, the second connecting portion, and the third connecting portion on the base substrate overlap with each other.

[0021] In a possible implementation, in the detection substrate provided in an embodiment of the present disclosure, the first readout line and the third connection portion are an integrated structure.

[0022] In a possible implementation, in the detection substrate provided in an embodiment of the present disclosure, outer contours of the first connection portion, the second connection portion, and the third connection portion are the same.

[0023] In a possible implementation, in the above-mentioned detection substrate provided in an embodiment of the present disclosure, the orthographic projections of the first via hole and the second via hole on the base substrate are both located within the orthographic projection range of the first connecting portion, the second connecting portion and the third connecting portion on the base substrate.

[0024] In a possible implementation, in the above-mentioned detection substrate provided in an embodiment of the present disclosure, the source-drain metal layer also includes a second read line electrically connected to the first connection portion, the second read line has the same extension direction as the first read line, and the orthographic projection of the second read line on the base substrate overlaps with the orthographic projection of the first read line on the base substrate.

[0025] In a possible implementation, in the detection substrate provided in an embodiment of the present disclosure, the second read line and the first connecting portion are an integrated structure.

[0026] In a possible implementation, in the above-mentioned detection substrate provided in an embodiment of the present disclosure, the detection substrate also includes a third read line arranged in the same layer as the bottom electrode, the third read line is electrically connected to the second connection portion, the third read line has the same extension direction as the first read line, and the orthographic projection of the third read line on the base substrate overlaps with the orthographic projection of the first read line on the base substrate.

[0027] In a possible implementation, in the detection substrate provided in an embodiment of the present disclosure, the third read line and the second connecting portion are an integrated structure.

[0028] In a possible implementation, in the detection substrate provided in an embodiment of the present disclosure, the first readout line and the scan line are arranged to cross each other, and the first via hole and the second via hole are arranged along an extension direction of the first readout line.

[0029] In a possible implementation, in the detection substrate provided in an embodiment of the present disclosure, the first via hole is close to the scan line adjacent to the first connection portion, or the second via hole is close to the scan line adjacent to the first connection portion.

[0030] In a possible implementation, in the detection substrate provided in the embodiment of the present disclosure, the orthographic projections of the center of the first via hole and the center of the second via hole on the base substrate do not overlap with the orthographic projection of the first reading line on the base substrate.

[0031] In a possible implementation, in the detection substrate provided in an embodiment of the present disclosure, the orthographic projections of the center of the first via hole and the center of the second via hole on the base substrate are located on the same side of the first reading line.

[0032] In a possible implementation, in the detection substrate provided by an embodiment of the present disclosure, the orthographic projections of the center of the first via hole and the center of the second via hole on the base substrate are located on the side of the first reading line away from the second pole to which it is electrically connected.

[0033] In a possible implementation, in the detection substrate provided in the embodiment of the present disclosure, the orthographic projections of the center of the first via hole and the center of the second via hole on the base substrate are located on the side of the first reading line close to the second pole to which it is electrically connected.

[0034] In a possible implementation, in the detection substrate provided in an embodiment of the present disclosure, the first readout line and the scan line are arranged to cross each other, and the first via hole and the second via hole are arranged along an extension direction of the scan line.

[0035] In a possible implementation, in the above-mentioned detection substrate provided in an embodiment of the present disclosure, the orthographic projection of the center of the second via on the base substrate is located on the side of the first reading line away from the second pole electrically connected to it, and the first via is located on the side of the second via away from the first reading line.

[0036] In a possible implementation, in the above-mentioned detection substrate provided in an embodiment of the present disclosure, the first connecting portion is divided into a first area and a second area connected to each other along the extension direction of the first reading line or along the extension direction of the scanning line, the area of ​​the first area is smaller than the area of ​​the second area, the first via hole is located in the first area, and the second via hole is located in the second area; the outer contour shape of the first connecting portion and the adjacent photoelectric conversion device is complementary.

[0037] In a possible implementation, in the above-mentioned detection substrate provided in an embodiment of the present disclosure, the bias voltage line is electrically connected to the top electrode through a third via hole penetrating the second buffer layer, the planar layer, and the first buffer layer, the third via hole including a second outer hole and a second inner hole, the second outer hole penetrating the planar layer, the second inner hole penetrating the first buffer layer and the second buffer layer, and the inner wall of the second inner hole covers the inner wall of the second outer hole; wherein,

[0038] The radius of the first inner hole is greater than or equal to the radius of the second inner hole, and the radius of the first outer hole is greater than or equal to the radius of the second outer hole.

[0039] In a possible implementation, in the detection substrate provided in the embodiment of the present disclosure, the radius of the first inner hole is 1 μm to 7 μm larger than the radius of the second inner hole, and the radius of the first outer hole is 1 μm to 7 μm larger than the radius of the second outer hole.

[0040] In a possible implementation, the detection substrate provided in the embodiment of the present disclosure further includes: a second insulating layer located on a side of the bias voltage electrode layer facing away from the base substrate, and a shielding layer located on a side of the second insulating layer facing away from the base substrate;

[0041] The orthographic projection of the shielding layer on the base substrate covers the orthographic projection of the side wall of the photoelectric conversion device on the base substrate.

[0042] In one possible implementation, in the detection substrate provided in an embodiment of the present disclosure, the base substrate includes a photosensitive area and a peripheral area surrounding the photosensitive area, the peripheral area includes a bias voltage electrode ring electrically connected to the bias voltage line, the bias voltage electrode ring includes a plurality of conductive structures surrounding the peripheral area and arranged at intervals, and adjacent conductive structures are electrically connected via a plurality of fourth connecting portions located on the bias voltage electrode layer;

[0043] The first reading line is located in the photosensitive area and extends between the bias voltage electrode ring and the photosensitive area. The peripheral area also includes a reading lead located in the gate metal layer and overlapping with the fourth connection portion. One end of the first reading line extends between the bias voltage electrode ring and the photosensitive area and is electrically connected to the first end of the reading lead through a fifth connection portion arranged in the same layer as the bottom electrode. The second end of the reading lead is electrically connected to a fan-out lead, and the fan-out lead is arranged in the same layer as the bottom electrode.

[0044] In a possible implementation, the detection substrate provided in the embodiment of the present disclosure further includes: a gate insulating layer located between the gate metal layer and the source / drain metal layer, and an active layer located between the gate insulating layer and the source / drain metal layer; the active layer is in direct contact with the source / drain and the second electrode; wherein,

[0045] One end of the first readout line extending between the bias voltage electrode ring and the photosensitive area is electrically connected to the fifth connection portion via a fourth via hole penetrating the second buffer layer, the planar layer, and the first buffer layer, and the fifth connection portion is electrically connected to the first end of the readout lead via a fifth via hole penetrating the first insulating layer and the gate insulating layer;

[0046] The second end of the readout lead is electrically connected to the fan-out lead through a sixth via hole penetrating the first insulating layer and the gate insulating layer.

[0047] In a possible implementation, in the above-mentioned detection substrate provided in an embodiment of the present disclosure, the conductive structures located on both sides of the extension direction of the first reading line are located between adjacent reading leads, and the conductive structures located on both sides of the extension direction of the scanning line are located between adjacent scanning lines.

[0048] In a possible implementation, in the detection substrate provided in the embodiment of the present disclosure, the material of the active layer includes amorphous silicon.

[0049] Correspondingly, an embodiment of the present disclosure further provides a flat panel detector, comprising any of the above-mentioned detection substrates provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] FIG1 is a schematic diagram of the equivalent circuit structure of a pixel in a flat panel detector;

[0051] FIG2 is a schematic diagram of the planar structure of a pixel in a conventional flat panel detector;

[0052] FIG3 is a schematic cross-sectional view along the AA' and BB' directions in FIG2 ;

[0053] FIG4 is a schematic cross-sectional view taken along the CC' direction in FIG2;

[0054] FIG5 is a schematic plan view of a detection substrate provided by the present disclosure;

[0055] FIG6 is a plan view schematically illustrating a pixel in FIG5 ;

[0056] FIG7 is a partially enlarged schematic plan view of FIG6 ;

[0057] FIG8 is a schematic cross-sectional view along the AA' and BB' directions in FIG7;

[0058] FIG9 is a schematic cross-sectional view along the CC' direction in FIG7;

[0059] FIG10 is another cross-sectional schematic diagram along the CC' direction in FIG7;

[0060] FIG11 is a schematic diagram of the coupling capacitance Cds / Cds′ corresponding to FIG10 ;

[0061] FIG12 is another cross-sectional schematic diagram along the CC' direction in FIG7;

[0062] FIG13 is a schematic diagram of the coupling capacitance Cds / Cds′ corresponding to FIG12 ;

[0063] FIG14 is another cross-sectional schematic diagram along the CC' direction in FIG7;

[0064] FIG15 is a schematic diagram of the coupling capacitance Cds / Cds′ corresponding to FIG14 ;

[0065] FIG16A shows the changes in noise components and total noise corresponding to FIG9 , FIG10 , FIG12 , and FIG14 of the embodiment and FIG4 of the conventional solution;

[0066] FIG16B shows the change of the signal-to-noise ratio of FIG9, FIG10, FIG12 and FIG14 of the comparative embodiment;

[0067] 17A to 17C are schematic planar structural diagrams of the first connecting portion, the second connecting portion, the first readout line, and the third connecting portion corresponding to FIG. 9 ;

[0068] 18A to 18C are schematic planar structural diagrams of the second readout line and the first connection portion, the second connection portion, and the first readout line and the third connection portion corresponding to FIG. 10 ;

[0069] 19A to 19C are schematic planar structural diagrams of the first connection portion, the third readout line and the second connection portion, and the first readout line and the third connection portion corresponding to FIG. 12 ;

[0070] 20A to 20C are schematic planar structural diagrams of the second readout line and the first connection portion, the third readout line and the second connection portion, and the first readout line and the third connection portion corresponding to FIG. 14 ;

[0071] FIG21A is another partially enlarged schematic plan view of a pixel in FIG5 ;

[0072] FIG21B is another partially enlarged schematic plan view of a pixel in FIG5 ;

[0073] FIG21C is another partially enlarged schematic plan view of a pixel in FIG5 ;

[0074] FIG22 is a schematic diagram showing the planar structure of the shielding layer;

[0075] FIG23 is a schematic plan view of a portion of the photosensitive area and a portion of the peripheral area;

[0076] FIG24 is a schematic plan view of a portion of the peripheral area;

[0077] FIG25 is a schematic cross-sectional view along the EE' direction in FIG23 and FIG24;

[0078] FIG26 is a schematic structural diagram of another detection substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0079] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0080] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words “include” or “comprise” and the like used in this disclosure mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. The words “connect” or “connected” and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Inside”, “outside”, “upper”, “lower”, etc. are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0081] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0082] X-ray flat-panel detectors are widely used in current medical image acquisition, with static general radiography (DR) accounting for nearly half of the market demand. In recent years, advancements in medical technology have also led to higher technical requirements for medical imaging, with the most pressing demand being for dynamic image acquisition, with common equipment and scenarios including DRF, CBCT, and DSA. Furthermore, with the advancement of imaging technology, the application of X-ray flat-panel detectors has expanded beyond medicine, such as industrial inspection in automotive manufacturing, lithium battery testing, and semiconductor testing. These industrial inspection fields also place high demands on dynamic image acquisition.

[0083] Dynamic images correspond to higher acquisition frame rates, that is, shorter single-frame acquisition time, which corresponds to less cumulative X-ray exposure. For medical scenarios, this obviously reduces damage to the patient's body. However, from the technical principle of the photoelectric image acquisition panel, the shortening of the single-frame acquisition time and the reduction of the cumulative exposure dose mean a decrease in the image signal, while the image noise usually fluctuates slightly with the acquisition time, resulting in an overall decrease in the signal-to-noise ratio (SNR) of dynamic images compared to the SNR of static images. This is obviously contrary to the requirement of "obtaining images of the highest possible quality with the least possible radiation damage." Therefore, it is necessary to explore better flat-panel detector technology to reduce pixel noise in order to obtain dynamic images with higher SNR and better quality.

[0084] A flat panel detector generally includes multiple scan lines and multiple read lines arranged in an insulated cross-section. The multiple scan lines and multiple read lines define multiple pixels, as shown in Figures 1 and 2. Figure 1 is a schematic diagram of the equivalent circuit structure of a pixel in a flat panel detector, and Figure 2 is a schematic diagram of the planar structure of a pixel in a conventional flat panel detector. Each pixel includes a thin film transistor 2 and a photoelectric conversion device 3 arranged on a substrate 1. The gate G of the thin film transistor 2 is electrically connected to the scan line 4, which is used to control the opening and closing of the thin film transistor 2; the second electrode D (e.g., the drain) of the thin film transistor 2 is electrically connected to the read line 5 for reading the photogenerated carriers generated in the pixel, and the read line 5 is arranged in the same layer as the drain; the first electrode S (e.g., the source) of the thin film transistor 2 is electrically connected to the bottom electrode 31 of the photoelectric conversion device 3; the bias voltage line 6 (Vbias) is electrically connected to the top electrode 32 of the photoelectric conversion device 3 and provides a negative bias voltage to enable the photoelectric conversion device 3 to operate in a reverse bias state where photoelectric conversion can occur; the thin film transistor 2 acts as a switch to control the entire pixel. When the thin film transistor 2 is turned on, the carriers generated by the photoelectric effect accumulated in the photoelectric conversion device 3 in the pixel are detected and read through the read line 5; when the thin film transistor 2 is turned off, the photoelectric conversion device 3 is exposed to light, and the photoelectric conversion effect continues to occur, and the photogenerated carriers are accumulated through the capacitor C formed between the top electrode 32 and the bottom electrode 31 of the photoelectric conversion device 3, waiting to be released through the read line 5 when the thin film transistor 2 is turned on.

[0085] As shown in Figures 3 and 4, Figure 3 is a schematic cross-sectional view along the AA' and BB' directions in Figure 2, and Figure 4 is a schematic cross-sectional view along the CC' direction in Figure 2. The flat-panel detector further includes: an active layer Act located between the gate G and the first electrode S and the second electrode D, a gate insulating layer 7 located between the gate G and the active layer Act, a first insulating layer 8 located between the first electrode S, the second electrode D and the bottom electrode 31, a first buffer layer 9 located between the top electrode 32 and the bias voltage line 6, a planarizing layer 10 located between the first buffer layer 9 and the bias voltage line 6, a second buffer layer 11 located between the planarizing layer 10 and the bias voltage line 6, a second insulating layer 12 located on the side of the bias voltage line 6 facing away from the second buffer layer 11, and a shielding layer 13 located on the side of the second insulating layer 12 facing away from the bias voltage line 6.

[0086] In the flat-panel detector structures shown in Figures 2-4, there are several locations with large overlap / coupling capacitances:

[0087] (1) Cgd in FIG4: Cgd is the overlap capacitance formed at the intersection of the scan line 4 and the read line 5. There is only one gate insulating layer 7 between the two metal lines, so the capacitance of Cgd is relatively large.

[0088] (2) Cds in Figures 2 and 3: Cds is the coupling capacitance formed between the readout line 5 and the bottom electrode 31 in the pixel to which it belongs. Since the readout line 5 and the bottom electrode 31 are separated by only one first insulating layer 8 in the cross-sectional structure and the lateral spacing in the planar structure is relatively small, typically 2μm to 8μm, the capacitance value of Cds is relatively large.

[0089] (3) Cds' in FIG2 : the coupling capacitance formed between the readout line 5 and the bottom electrode 31 in the adjacent right pixel (shown only in the plan view shown in FIG2 , not shown in the cross-sectional view in FIG3 ). Since the readout line 5 and the bottom electrode 31 are separated by only one first insulating layer 8 in the cross-sectional structure, and the lateral spacing in the planar structure is relatively small, typically 2 μm to 8 μm, the capacitance value of Cds' is relatively large.

[0090] The three capacitors Cgd, Cds, and Cds' are the primary components of the total capacitance of read line 5, collectively accounting for 40% to 60% of the total capacitance. Therefore, the values ​​of Cgd, Cds, and Cds' significantly affect the total capacitance of read line 5, which in turn affects pixel noise and, ultimately, the flat-panel detector's signal-to-noise ratio. Furthermore, the resistance of read line 5 also affects pixel noise and, ultimately, the flat-panel detector's signal-to-noise ratio.

[0091] In view of this, in order to reduce the pixel noise of the flat-panel detector to obtain a dynamic image with higher SNR and better quality, the present disclosure provides a detection substrate, as shown in FIG5 , including a base substrate 1, the base substrate 1 having a photosensitive area AA and a peripheral area BB surrounding the photosensitive area AA, the photosensitive area AA including a plurality of pixels P distributed in an array; as shown in FIG6 to FIG9 , FIG6 is a planar schematic diagram of a pixel P in FIG5 , FIG7 is a partially enlarged planar schematic diagram of FIG6 , FIG8 is a cross-sectional schematic diagram along the AA' and BB' directions in FIG7 , and FIG9 is a cross-sectional schematic diagram along the CC' direction in FIG7 , the detection substrate further includes a gate metal layer 40, a source-drain metal layer 50, a photoelectric conversion device 3 and a bias voltage electrode layer 60 arranged on the base substrate 1; wherein,

[0092] The gate metal layer 40 includes a gate G and a scan line 4 electrically connected to the gate G;

[0093] The source-drain metal layer 50 includes a first electrode S, a second electrode D, and a first connecting portion 5' electrically connected to the second electrode D;

[0094] The photoelectric conversion device 3 includes a bottom electrode 31, a photoelectric conversion layer 33 and a top electrode 32 stacked in sequence. The bottom electrode 31 is close to the substrate 1 and is electrically connected to the first electrode S.

[0095] The bias voltage electrode layer 60 includes bias voltage lines 6 and first readout lines 6' extending in the same direction and spaced apart from each other. Thus, the patterns of the first readout lines 6' and the bias voltage lines 6 can be formed in a single patterning process simply by changing the original pattern when forming the bias voltage lines 6. This eliminates the need for a separate process for preparing the first readout lines 6', thereby simplifying the manufacturing process, saving production costs, and improving production efficiency.

[0096] The detection substrate further includes a second connection portion 3 ′ provided in the same layer as the bottom electrode 31 . The first readout line 6 ′ is electrically connected to the second connection portion 3 ′, and the second connection portion 3 ′ is electrically connected to the first connection portion 5 ′.

[0097] The above-mentioned detection substrate provided by the embodiment of the present disclosure jumps the readout line originally set in the source and drain metal layer in the related technical Figures 2 to 4 to the bias voltage electrode layer through a second connection portion set in the same layer as the bottom electrode, that is, the readout line is formed in the upper layer of the film layer stack structure through the second connection portion; it can be clearly seen from the cross-sectional structure of Figures 8 and 9 that whether it is the overlapping capacitor Cgd or the coupling capacitor Cds / Cds', the distance between the two poles of the capacitor is significantly enlarged, so the capacitance of Cgd, Cds and Cds' is significantly reduced. Therefore, the embodiment of the present disclosure achieves a significant reduction in the capacitance on the readout line, which can significantly reduce pixel noise and improve the signal-to-noise ratio of the pixel, which is conducive to the application of products and technologies in dynamic image acquisition scenarios, thereby obtaining higher quality dynamic images.

[0098] It should be noted that the second connecting portion 3' mentioned above is arranged on the same layer as the bottom electrode 31. The same layer arrangement here means that the bottom electrode 31 and the second connecting portion 3' are located on the same layer, the bottom electrode 31 and the second connecting portion 3' are prepared in the same process, and the main parts of the bottom electrode 31 and the second connecting portion 3' are located on the same plane in terms of structure.

[0099] It should be noted that the first electrode of the source-drain metal layer can be the source electrode, and the second electrode can be the drain electrode; of course, the first electrode can also be the drain electrode, and the second electrode can be the source electrode; this disclosure takes the first electrode being the source electrode and the second electrode being the drain electrode as an example.

[0100] In a specific implementation, the above-mentioned detection substrate provided in the embodiment of the present disclosure, as shown in FIG6 to FIG9, further includes: a first insulating layer 8 located between the source / drain metal layer 50 and the bottom electrode 31, and a flat layer 10 located between the top electrode 32 and the bias voltage electrode layer 60; wherein,

[0101] The first connection portion 5' is electrically connected to the second connection portion 3' via a first via V1 that penetrates the first insulating layer 8. The second connection portion 3' is electrically connected to the first readout line 6' via a first external via V21 that penetrates the planar layer 10. The present disclosure jumpers the readout line originally provided in the source / drain metal layer 50 to the bias voltage electrode layer 60 through the first via V1 and the first external via V21. This reduces the capacitance of the first readout line 6' and also reduces the resistance of the first readout line 6' by electrically connecting the metal at the vias, thereby further reducing pixel noise.

[0102] In a specific implementation, in order to improve the adhesion between the flat layer and the top electrode and between the bias voltage electrode layer and the flat layer, the above-mentioned detection substrate provided in the embodiment of the present disclosure, as shown in Figures 6 to 9, further includes: a first buffer layer 9 located between the top electrode 32 and the flat layer 10, and a second buffer layer 11 located between the flat layer 10 and the bias voltage electrode layer 60; wherein,

[0103] The second connection portion 3' is also electrically connected to the first readout line 6' via a first inner hole V22 that penetrates the first buffer layer 9 and the second buffer layer 11. The first inner hole V22 and the first outer hole V21 are nested to form a second via V2. The orthographic projection of the first inner hole V22 on the substrate 1 is within the orthographic projection of the first outer hole V21 on the substrate 1, and the inner wall of the first inner hole V22 overlaps the inner wall of the first outer hole V21. Thus, when forming the second via V2, the planar layer 10 uses a single-layer patterning process to form the first outer hole V21, and the first buffer layer 9 and the second buffer layer 11 use a single-layer patterning process to form the first inner hole V22. Moreover, since the material of the flat layer 10 is generally organic resin, it contains a certain proportion of volatile substances and has a high thermal weight loss ratio. If part of the flat layer is exposed on the inner wall of the first outer hole V21, the volatile substances in the flat layer 10 will evaporate and condense in the subsequent high-temperature process (150°C to 250°C) of sputtering deposition of the metal layer (first reading line 6'), affecting the metal deposition morphology; therefore, the embodiment of the present disclosure uses the inner wall of the first inner hole V22 to cover the inner wall of the first outer hole V21, thereby avoiding the adverse effects of volatilization caused by the exposure of the flat layer 10.

[0104] In a specific implementation, the above-mentioned detection substrate provided in the embodiment of the present disclosure, as shown in Figures 5 to 9, also includes: a gate insulating layer 7 located between the gate metal layer 40 and the source-drain metal layer 50, and an active layer Act located between the gate insulating layer 7 and the source-drain metal layer 50; the active layer Act is in direct contact with the first electrode S and the second electrode D; wherein the gate G, the first electrode S, the second electrode D and the active layer Act constitute a thin film transistor 2, and of course the structure of the thin film transistor 2 is not limited to the structure provided in the present disclosure; the first reading line 6' and the scanning line 4 are generally arranged to cross to define a plurality of pixels P, each pixel P includes a thin film transistor 2 and a photoelectric conversion device 3, the gate G of the thin film transistor 2 is electrically connected to the scanning line 4, the first electrode S of the thin film transistor 2 is electrically connected to the bottom electrode 31 of the photoelectric conversion device 3, the second electrode D of the thin film transistor 2 is electrically connected to the first reading line 6', and the bottom electrode 32 of the photoelectric conversion device 3 is electrically connected to the bias voltage line 6.

[0105] Specifically, the photoelectric conversion layer 33 converts light signals into electrical signals, while the bottom electrode 31 conducts the electrical signals generated by the photoelectric conversion layer 33 after being illuminated by light. There is a facing area between the bottom electrode 31 and the top electrode 32, forming a storage capacitor between them. When the detection substrate is operating, for example, a voltage of -5 to -10V is applied to the top electrode 32 via the bias voltage line 6, causing the photoelectric conversion layer 33 to operate under a negative bias. This generates a distinct electrical signal, which is stored in the bottom electrode 31. This signal is then transmitted to an external IC via the thin-film transistor 2 to store image data.

[0106] Optionally, as shown in Figures 8 and 9, the thickness of the gate insulating layer 7 is 300nm to 600nm, the thickness of the first insulating layer 8 is 400nm to 600nm, the thickness of the first buffer layer 9 is 50nm to 300nm, the thickness of the flat layer 10 is 1500nm to 2500nm, and the thickness of the second buffer layer 11 is 100nm to 300nm. Therefore, Cgd can be reduced by more than 90%, Cds / Cds' can be reduced by 20% to 40%, and therefore the total capacitance of the first read line 6' in Figure 9 of the embodiment of the present disclosure can be reduced by 10% to 20%.

[0107] In specific implementations, in the above-mentioned detection substrate provided in the embodiments of the present disclosure, as shown in Figures 7 and 9 , the orthographic projection of the first outer hole V21 on the base substrate 1 does not overlap with the orthographic projection of the first via hole V1 on the base substrate 1. This reduces the risk of line breakage caused by deep hole dry etching to form a chamfered corner on the first readout line 6', thereby avoiding image defects caused by line breakage. If the orthographic projection of the second via hole V2 in the present disclosure on the substrate 1 overlaps with the orthographic projection of the first via hole V1 on the substrate 1, assuming that the first reading line 6' is directly electrically connected to the first connecting portion 5' through a deep hole penetrating the second buffer layer 11, the flat layer 10, the first buffer layer 9 and the first insulating layer 8, a chamfered angle will be formed at the bottom of the first insulating layer 8 (generally SiO / SiN material). This is because the dry etching process of SiO / SiN (such as reactive ion beam etching) is blocked by the first connecting portion 5' when etching to the bottom of the hole, and the ion beam will diverge to the surroundings, thereby damaging the morphology of the first insulating layer 8 around the bottom of the hole; this chamfered angle is not conducive to the subsequent metal deposition climbing during the production of the first reading line 6', and ultimately causes the first reading line 6' to break at the bottom of the hole. If the present disclosure adopts the method in which the orthographic projection of the second via hole V2 on the base substrate 1 overlaps with the orthographic projection of the first via hole V1 on the base substrate 1, and the first reading line 6' is electrically connected to the first connecting portion 5' through the second connecting portion 3', the bottom of the first insulating layer 8 will still form a chamfer at the position of the first via hole V1, which will also cause the first reading line 6' to break at the bottom of the hole.

[0108] In a specific implementation, in the above-mentioned detection substrate provided in the embodiment of the present disclosure, as shown in FIG9 , the difference between the radius of the first outer hole V21 and the radius of the first inner hole V22 is at least greater than or equal to the first distance a; the distance between the first outer hole V21 and the adjacent sidewall of the first via hole V1 is greater than or equal to the second distance b, where b is intended to ensure that the first outer hole V21 and the adjacent sidewall of the first via hole V1 are not tangent or intersecting, taking into account the comprehensive deviation limits of processes such as exposure and etching. Otherwise, there will be the aforementioned risk of chamfered corners, resulting in the first reading line 6' being disconnected within the via hole; optionally, the ratio of the first distance a to the second distance b can be 3:1 to 1:2. Furthermore, the first distance a can be 2μm to 7μm; the second distance b can be 1μm to 5μm.

[0109] In a specific implementation, in the above-mentioned detection substrate provided by the embodiment of the present disclosure, as shown in FIG9 , the bias voltage electrode layer 60 further includes a third connection portion 61 electrically connected to the first read line 6 ′, and the third connection portion 61 is electrically connected to the second connection portion 3 ′ through the second via V2; wherein,

[0110] The orthographic projections of the first connecting portion 5', the second connecting portion 3' and the third connecting portion 61 on the substrate 1 overlap with each other. Optionally, the outer contours of the first connecting portion 5', the second connecting portion 3' and the third connecting portion 61 may be the same, for example, the orthographic projections of the three completely overlap, although there may be some error.

[0111] In specific implementations, in the detection substrate provided in the embodiment of the present disclosure, as shown in FIG9 , the first readout line 6' and the third connecting portion 61 can be an integral structure. This allows the patterns of the first readout line 6' and the third connecting portion 61 to be formed in a single patterning process, simplifying the manufacturing process, saving production costs, and improving production efficiency.

[0112] In a specific implementation, in the above-mentioned detection substrate provided in the embodiment of the present disclosure, as shown in Figures 7 and 10, Figure 10 is another cross-sectional schematic diagram along the CC' direction in Figure 7, and the source-drain metal layer 50 also includes a second read line 5 electrically connected to the first connecting portion 5', and the second read line 5 has the same extension direction as the first read line 6', and the orthographic projection of the second read line 5 on the base substrate 1 overlaps with the orthographic projection of the first read line 6' on the base substrate 1. In this embodiment, the read line originally set in the source-drain metal layer 50 in the related technical Figures 2 to 4 is changed to a parallel structure of a second read line 5 set in the source-drain metal layer 50 and a first read line 6' set in the bias voltage electrode layer 60, that is, the second read line 5 set in the source-drain metal layer 50 and the first read line 6' set in the bias voltage electrode layer 60 are connected in parallel in a double layer through the first via hole and the second via hole to form a total read line; it can be clearly seen from the cross-sectional structure of Figure 10 that the overlapping capacitance Cgd is not reduced compared with Figure 4; as shown in Figure 11, Figure 11 is a schematic diagram of the coupling capacitance Cds / Cds' corresponding to schematic diagram 10. Compared with Figure 4, in addition to the original coupling part between the bottom electrode 31 and the second read line 5 remaining unchanged, this embodiment even adds a coupling part between the bottom electrode 31 and the first read line 6', so this embodiment does not reduce the capacitance of the read line. However, it is clear that the resistance of the read line is significantly reduced due to the double-layer parallel wiring of the second read line and the first read line. If the resistivity of the second read line and the first read line is approximately equal, the total resistance of the read line in the disclosed embodiment can be reduced by nearly 50% compared to the conventional solution shown in Figure 4. Although the total capacitance of the read line increases in this embodiment, the reduction in the total resistance of the read line is greater, thus achieving an overall reduction in noise on the read line.

[0113] In specific implementations, in the above-mentioned detection substrate provided in the embodiments of the present disclosure, as shown in Figures 7 and 10, the second readout line 5 and the first connecting portion 5' can be an integral structure. This allows the second readout line 5 and the first connecting portion 5' to be formed in a single patterning process, which can simplify the manufacturing process, reduce production costs, and improve production efficiency.

[0114] In a specific implementation, in the above-mentioned detection substrate provided in the embodiment of the present disclosure, as shown in Figures 7 and 12, Figure 12 is another cross-sectional schematic diagram along the CC' direction in Figure 7, and the detection substrate also includes a third read line 30 arranged in the same layer as the bottom electrode 31, and the third read line 30 is electrically connected to the second connecting portion 3'. The third read line 30 has the same extension direction as the first read line 6', and the orthographic projection of the third read line 30 on the base substrate 1 overlaps with the orthographic projection of the first read line 6' on the base substrate 1. In this embodiment, the read line originally set in the source-drain metal layer 50 in the related technical Figures 2 to 4 is changed to a parallel structure of a third read line 30 set in the same layer as the bottom electrode 31 and a first read line 6' set in the bias voltage electrode layer 60, that is, the read line originally set in the source-drain metal layer 50 is changed to a double-layer parallel connection of the third read line 30 and the first read line 6' through the first via and the second via to constitute the total read line; it can be clearly seen from the cross-sectional structure of Figure 12 that compared with Figure 4, the overlapping capacitance Cgd has a first insulating layer 8 added between the two poles of Cgd, so the capacitance of Cgd is reduced; as shown in Figure 13, Figure 13 is a schematic diagram of the coupling capacitance Cds / Cds' corresponding to schematic diagram 12, and the coupling capacitance Cds / Cds' is compared with Figure 4, and Figure 13 is similar to Figure 11, so the capacitance of Cds / Cds' is increased; overall, Figure 12 has a slight increase in the total capacitance of the read line compared with the conventional solution. However, it is clear that the resistance of the read line is significantly reduced due to the double-layer parallel wiring of the third read line 30 and the first read line 6'. If the resistivity of the third read line 30 and the first read line 6' is approximately equal, the total resistance of the read line of the present disclosure can be reduced by nearly 50% compared to the conventional solution shown in Figure 4. Although the total capacitance of the read line is increased in this embodiment, the reduction in the total resistance of the read line is greater, so the overall noise on the read line is reduced.

[0115] In a specific implementation, in the above-mentioned detection substrate provided by the embodiment of the present disclosure, as shown in Figures 7 and 14, Figure 14 is another cross-sectional schematic diagram along the CC' direction in Figure 7, the source-drain metal layer 50 also includes a second read line 5 electrically connected to the first connecting portion 5', the second read line 5 has the same extension direction as the first read line 6', and the orthographic projection of the second read line 5 on the base substrate 1 overlaps with the orthographic projection of the first read line 6' on the base substrate 1; the detection substrate also includes a third read line 30 arranged in the same layer as the bottom electrode 31, the third read line 30 is electrically connected to the second connecting portion 3', the third read line 30 has the same extension direction as the first read line 6', and the orthographic projection of the third read line 30 on the base substrate 1 overlaps with the orthographic projection of the first read line 6' on the base substrate 1. In this embodiment, the read line originally set in the source-drain metal layer 50 in the related technical Figures 2 to 4 is changed to a parallel structure of a second read line 5 set in the source-drain metal layer 50, a third read line 30 set in the same layer as the bottom electrode 31, and a first read line 6' set in the bias voltage electrode layer 60. That is, the read line originally set in the source-drain metal layer 50 is changed to a second read line 5, a third read line 30 and a first read line 6' in parallel through the first via hole and the second via hole to form a total read line; it can be clearly seen from the cross-sectional structure of Figure 14 that the overlap capacitance Cgd is not reduced compared with that in Figure 4; as shown in Figure 15, Figure 15 is a schematic diagram of the coupling capacitance Cds / Cds' corresponding to schematic diagram 14. Compared with Figure 4, the coupling capacitance Cds / Cds', in addition to the original coupling part between layer 6 and layer 4, even adds the coupling part between the bottom electrode 31 and the first read line 6', and the coupling part between the bottom electrode 31 and the third read line 30. Therefore, the read line capacitance of this embodiment is not reduced, and even increases significantly. However, it is clear that the resistance of the read line is significantly reduced due to the three-layer parallel wiring of the second read line 5, the third read line 30, and the first read line 6'. If the resistivity of the second read line 5, the third read line 30, and the first read line 6' are approximately equal, the total resistance of the read line of the present disclosure can be reduced by approximately 60% to 70% compared to the conventional solution shown in Figure 4. Although the total capacitance of the read line is increased in this embodiment, the reduction in the total resistance of the read line is greater, so the overall noise on the read line is reduced.

[0116] In specific implementations, in the detection substrate provided in the embodiments of the present disclosure, as shown in Figures 12 and 14 , the third readout line 30 and the second connection portion 3' can be an integral structure. This allows the patterning of the third readout line 30 and the second connection portion 3' to be formed in a single patterning process, simplifying the manufacturing process, saving production costs, and improving production efficiency.

[0117] In a specific implementation, in the above-mentioned detection substrate provided in the embodiment of the present disclosure, as shown in Figures 6 to 15 , the orthographic projections of the first via hole V1 and the second via hole V2 on the base substrate 1 are both located within the orthographic projections of the first connecting portion 5', the second connecting portion 3', and the third connecting portion 61 on the base substrate 1. This ensures electrical connection between each of the first connecting portion 5', the second connecting portion 3', and the third connecting portion 61.

[0118] The following describes the optimization effects achieved in terms of noise and SNR of the above embodiments, Figures 9, 10, 12, and 14, compared with the conventional solution Figure 4, using simulation data based on the noise calculation model and signal-to-noise ratio (SNR) formula of the detection substrate.

[0119] The signal-to-noise ratio (SNR) formula for detecting the substrate is as follows:

[0120] The noise formula is shown in the denominator. The first four terms They are: shot noise of thin film transistors, defect noise of thin film transistors, shot noise of photoelectric converters, and thermal noise of photoelectric converters. The above four items have nothing to do with the capacitance C and resistance R of the read line, and are collectively referred to as pixel noise. Therefore, the above formula can be transformed into

[0121] The last two terms in the noise formula They are: (1) Line noise Positively correlated with C and R; (2) read-out IC read noise, positively correlated with C. The design optimizations made in the embodiment Figures 9, 10, 12 and 14 are exactly the above two The effect of noise components.

[0122] Take a detection substrate with a resolution of 2048 rows × 2048 columns and a pixel size of about 200μm × 200μm as an example:

[0123] FIG16A shows the changes in each noise component and the total noise compared with FIG9, FIG10, FIG12 and FIG14 of the embodiment and FIG4 of the conventional solution. As mentioned above, since it is not related to C and R, there is no change between the embodiments; read noise Positively correlated with C, since C in Figure 9 is reduced and R is basically unchanged, Figure 9 is compared with Figure 4 of the conventional solution. In Figures 10, 12, and 14, C increases, so Figures 10, 12, and 14 are compared with Figure 4 of the conventional solution. All of them have increased, which is completely consistent with the C changes described in the embodiments of Figures 9, 10, 12 and 14 above; line noise It is positively correlated with C and R. In Figure 9, C decreases while R remains almost unchanged, so the line noise Reduced; In Figures 10, 12, and 14, although C has increased, R has decreased more, so the overall line noise To sum up, in the embodiment FIG9 and are all reduced, so the noise is reduced; for the embodiments Figures 10, 12 and 14, according to the noise formula Although Rising, but The overall effect is to reduce the noise.

[0124] To sum up, the total noise is compared 9 , 10 , 12 and 14 are all significantly reduced, and the reduction ratio is shown in FIG16B . The overall noise of the embodiments FIG9 , 10 , 12 and 14 can be reduced by more than 10%.

[0125] As shown in Figure 16B, comparing the SNR changes in Example Figures 9, 10, 12, and 14, none of the readout line designs in Example Figures 9, 10, 12, and 14 act on the photodiode. Therefore, the signal intensity remains unchanged compared to the conventional solution in Figure 4. Therefore, the change in SNR is entirely due to noise reduction. Using the grayscale of a 16-bit readout IC half-saturation dose image (30,000 to 35,000 grayscale) as the signal, the SNR in Example Figures 9, 10, 12, and 14 all improves by more than 4%, with a maximum improvement of 6.5%.

[0126] In order to clearly illustrate the structure of the second reading line 5 and the first connection part 5', the third reading line 30 and the second connection part 3', the first reading line 6' and the third connection part 61, as shown in Figures 17A to 17C, Figures 18A to 18C, Figures 19A to 19C, and Figures 20A to 20C, Figures 17A to 17C are respectively schematic diagrams of the planar structure of the first connection part 5', the second connection part 3', the first reading line 6' and the third connection part 61 corresponding to Figure 9, and Figures 18A to 18C are respectively schematic diagrams of the second reading line 5 and the first connection part 5', the second connection part 3', 19A to 19C are schematic diagrams of the planar structure of the first connection part 5', the third read line 30 and the second connection part 3', and the first read line 6' and the third connection part 61 corresponding to FIG12 , respectively. FIG20A to 20C are schematic diagrams of the planar structure of the second read line 5 and the first connection part 5', the third read line 30 and the second connection part 3', and the first read line 6' and the third connection part 61 corresponding to FIG14 , respectively. It can be seen that the outer contours of the first connection part 5', the second connection part 3' and the third connection part 61 are the same.

[0127] In a specific implementation, in the above-mentioned detection substrate provided in the embodiment of the present disclosure, as shown in Figures 7, 21A, and 21B, the first readout line 6' and the scan line 4 are arranged to intersect, and the first via hole V1 and the second via hole V2 can be arranged along the extension direction of the first readout line 6'. Optionally, as shown in Figure 21A, the first via hole V1 is close to the scan line 4 adjacent to the first connection portion 5'; and as shown in Figures 7 and 21B, the second via hole V2 is close to the scan line 4 adjacent to the first connection portion 5'.

[0128] In a specific implementation, in the above-mentioned detection substrate provided in the embodiment of the present disclosure, as shown in Figures 7, 21A and 21B, the orthographic projections of the center of the first via hole V1 and the center of the second via hole V2 on the base substrate 1 may not overlap with the orthographic projection of the first reading line 6' on the base substrate 1, but of course, this is not limited to this.

[0129] In a specific implementation, in the above-mentioned detection substrate provided in the embodiment of the present disclosure, as shown in Figures 7, 21A, and 21B, the orthographic projections of the center of the first via V1 and the center of the second via V2 on the base substrate 1 can be located on the same side of the first read line 6'. Optionally, as shown in Figures 7 and 21A, the orthographic projections of the center of the first via V1 and the center of the second via V2 on the base substrate 1 are located on the side of the first read line 6' away from the second pole D to which it is electrically connected; as shown in Figure 21B, the orthographic projections of the center of the first via V1 and the center of the second via V2 on the base substrate 1 are located on the side of the first read line 6' close to the second pole D to which it is electrically connected.

[0130] In a specific implementation, in the above-mentioned detection substrate provided in the embodiment of the present disclosure, as shown in FIG21C , the first readout line 6' and the scan line 4 are arranged crosswise, and the first via V1 and the second via V2 are arranged along the extension direction of the scan line 4. Optionally, the orthographic projection of the center of the second via V2 on the base substrate 1 is located on the side of the first readout line 6' away from the second pole D electrically connected thereto, and the first via V1 is located on the side of the second via V2 away from the first readout line 6'. Of course, it is also possible that the center of the first via V1 is located on the side of the first readout line 6' away from the second pole D electrically connected thereto, and the second via V2 is located on the side of the first via V1 away from the first readout line 6'.

[0131] In a specific implementation, in the above-mentioned detection substrate provided in the embodiment of the present disclosure, as shown in Figures 7, 21A, and 21B, the first connection portion 5' can be divided into a first region S1 and a second region S2 that are interconnected along the extension direction of the first readout line 6'. As shown in Figure 21C, the first connection portion 5' can be divided into a first region S1 and a second region S2 that are interconnected along the extension direction of the scan line 4. The area of ​​the first region S1 is smaller than that of the second region S2. The first via V1 is located within the first region S1, and the second via V2 is located within the second region S2. The outer contours of the first connection portion 5' and the adjacent photoelectric conversion device 3 complement each other. This can minimize the loss of pixel fill rate, thereby ensuring the sensitivity of the detection substrate and improving the signal-to-noise ratio.

[0132] It should be noted that Figures 7 and 21A-21C show the relative positions of several first vias V1 and second vias V2 in the pixel. It can be seen that the present disclosure has no specific restrictions on the placement positions of the first vias V1 and the second vias V2. On the basis of ensuring that the jump connection method remains unchanged, in addition to the four examples shown in Figures 7 and 21A-21C, there may also be other similar examples, which will not affect the optimization effect of noise and signal-to-noise ratio achieved by the present disclosure.

[0133] In a specific implementation, in the above-mentioned detection substrate provided in an embodiment of the present disclosure, as shown in FIG8 , the bias voltage line 6 is electrically connected to the top electrode 32 through a third via hole V3 penetrating the second buffer layer 11, the flat layer 10, and the first buffer layer 9. The third via hole V3 includes a second outer hole V31 and a second inner hole V32 that are sleeved. The second outer hole V31 penetrates the flat layer 10, and the second inner hole V32 penetrates the first buffer layer 9 and the second buffer layer 11. The inner wall of the second inner hole V32 covers the inner wall of the second outer hole V31; wherein,

[0134] The radius of the first inner hole V22 is greater than or equal to the radius of the second inner hole V32, and the radius of the first outer hole V21 is greater than or equal to the radius of the second outer hole V31. This is because the thin-film transistor 2 and the photoelectric conversion device 3 are horizontal structures. The etching depth of the first inner hole V22 is greater than the etching depth of the second inner hole V32, and the etching depth of the first outer hole V21 is greater than the etching depth of the second outer hole V31. Therefore, sufficient exposure area must be reserved to ensure that the photoresist in the first inner hole V22 and the first outer hole V21 is fully exposed without any residual photoresist. This avoids insufficient exposure that may cause the first inner hole V22 and the first outer hole V21 to fail to penetrate, resulting in the ineffective electrical connection between the first readout line 6' and the second connecting portion 3', and thus causing image defective lines. Optionally, to ensure the pixel fill rate, the second outer hole V31 and the second inner hole V32 will select the minimum value corresponding to the process capability limit of the exposure machine. For example, the radius of the first inner hole V22 is 1μm to 7μm larger than the radius of the third via hole V3, and the radius of the first outer hole V21 is 1μm to 7μm larger than the radius of the second outer hole V31.

[0135] In a specific implementation, in order to shield the photoelectric conversion device from damage by external signals, the detection substrate provided in the embodiment of the present disclosure, as shown in Figures 6 to 8, further includes: a second insulating layer 12 located on the side of the bias voltage electrode layer 60 facing away from the base substrate 1, and a shielding layer 13 located on the side of the second insulating layer 12 facing away from the base substrate 1;

[0136] To clearly illustrate the structure of the shielding layer 13, as shown in FIG22 , the orthographic projection of the shielding layer 13 on the base substrate 1 covers the orthographic projection of the sidewalls of the photoelectric conversion device 3 on the base substrate 1. Specifically, to prevent the shielding layer 13 from affecting the transmittance, the material of the shielding layer 13 is generally a transparent conductive material, such as indium tin oxide (ITO), boron-doped zinc oxide (BZO), aluminum-doped zinc oxide (AZO), etc.

[0137] In a specific implementation, in the above-mentioned detection substrate provided by the embodiment of the present disclosure, as shown in Figures 23 to 25, Figure 23 is a plan view schematically showing a portion of the photosensitive area AA and a portion of the peripheral area BB, Figure 24 is a plan view schematically showing a portion of the peripheral area BB, and Figure 25 is a cross-sectional view schematically shown along the EE' direction in Figures 23 and 24. The peripheral area BB includes a bias voltage electrode ring 70 electrically connected to the bias voltage line 6. The bias voltage electrode ring 70 includes a plurality of conductive structures 71 surrounding the peripheral area BB and arranged at intervals. Adjacent conductive structures 71 are electrically connected via a plurality of fourth connecting portions 62 located on the bias voltage electrode layer 60.

[0138] The first reading line 6' is located in the photosensitive area AA and extends between the bias voltage electrode ring 70 and the photosensitive area AA. The peripheral area BB also includes a reading lead 41 located in the gate metal layer 40 and overlapping with the fourth connecting portion 62. One end of the first reading line 6' extends between the bias voltage electrode ring 70 and the photosensitive area AA and is electrically connected to the first end of the reading lead 41 through the fifth connecting portion 34 arranged in the same layer as the bottom electrode 31. The second end of the reading lead 41 is electrically connected to the fan-out lead 35, and the fan-out lead 35 is arranged in the same layer as the bottom electrode 31.

[0139] Optionally, the first read line 6' extends to one end between the bias voltage electrode ring 70 and the photosensitive area AA and the fan-out lead 35, and is not limited to being electrically connected to the read lead 41 located in the gate metal layer 40, but can also be located in other non-bias voltage electrode layers 60 such as the source and drain metal layer 50; of course, the read lead 41 can also use a double or triple layer of metal such as the gate metal layer 40 and the source and drain metal layer 50 in parallel to reduce the resistance of the read lead 41.

[0140] Optionally, as shown in Figures 23 and 24, the conductive structure 71 can adopt a three-layer parallel electrically connected structure, including a sub-conductive structure located in the bias voltage electrode layer 60, a sub-conductive structure arranged on the same layer as the bottom electrode 31, and a sub-conductive structure arranged on the same layer as the shielding layer 13. Of course, one or two layers of the structure can also be adopted as the parallel electrically connected structure, and the present disclosure does not limit this.

[0141] In a specific implementation, in the above-mentioned detection substrate provided by the embodiment of the present disclosure, as shown in Figures 23 and 24, one end of the first readout line 6' extending between the bias voltage electrode ring 70 and the photosensitive area AA is electrically connected to the fifth connection portion 34 via a fourth via hole V4 penetrating the second buffer layer 11, the planar layer 10, and the first buffer layer 9. The fifth connection portion 34 is electrically connected to the first end of the readout lead 41 via a fifth via hole V5 penetrating the first insulating layer 8 and the gate insulating layer 7. Optionally, the number of the fourth via hole V4 and the fifth via hole V5 can be set to multiple, thereby reducing the contact resistance between the first readout line 6', the fifth connection portion 34, and the readout lead 41.

[0142] The second end of the read lead 41 is electrically connected to the fan-out lead 35 through a sixth via V6 that passes through the first insulating layer 8 and the gate insulating layer 7; optionally, the number of sixth vias V6 can be set to multiple, thereby reducing the contact resistance between the read lead 41 and the fan-out lead 35.

[0143] In a specific implementation, in the above-mentioned detection substrate provided in the embodiment of the present disclosure, as shown in Figures 23 and 24, each conductive structure 71 located on both sides of the extension direction of the first reading line 6' is located between adjacent reading leads 41, and each conductive structure 71 located on both sides of the extension direction of the scanning line 4 is located between adjacent scanning lines 4, so as to realize jumper connection between adjacent conductive structures 71 to avoid short circuit.

[0144] Alternatively, as shown in FIG8 , the photoelectric conversion layer 33 in the present disclosure may have a PN structure or a PIN structure. Specifically, the PIN structure includes an N-type doped N-type semiconductor layer, an undoped intrinsic semiconductor layer I, and a P-type doped P-type semiconductor layer. The thickness of the intrinsic semiconductor layer I may be greater than that of the P-type semiconductor layer and the N-type semiconductor layer.

[0145] In addition, the orthographic projection of the top electrode 32 on the base substrate 1 is located within the orthographic projection of the photoelectric conversion layer 33 on the base substrate 1, that is, the area of ​​the top electrode 32 is slightly smaller than the area of ​​the photoelectric conversion layer 33, which can reduce the leakage current caused by damage to the side wall of the photoelectric conversion layer 33 during etching.

[0146] Optionally, the bottom electrode 31 can be formed of molybdenum, aluminum, silver, copper, titanium, platinum, tungsten, tantalum, tantalum nitride, alloys thereof, combinations thereof, or other suitable materials; and the top electrode 32 can be formed of indium tin oxide (ITO) or indium zinc oxide (IZO) or other suitable transparent materials to improve light transmission efficiency.

[0147] Optionally, the gate insulating layer 7 , the first insulating layer 8 , the first buffer layer 9 , the second buffer layer 11 and the second insulating layer 12 may be made of inorganic materials, such as silicon nitride, silicon oxide, silicon oxynitride and the like.

[0148] In specific implementation, in the above-mentioned detection substrate provided in the embodiment of the present disclosure, as shown in Figure 26, the detection substrate also includes: a scintillator layer 14 located on the side of the shielding layer 13 away from the base substrate 1. The material of the scintillator layer 14 is a material that can convert X-rays into visible light, which is mainly composed of scintillators. The scintillator itself is a type of material that can emit light after absorbing high-energy particles or rays. It is usually processed into crystals in applications, which are called scintillator crystals. The embodiment of the present disclosure does not limit the specific material of the scintillator crystals of the scintillator layer 14, which can be cesium iodide (CsI), cadmium tungstate, barium fluoride, gadolinium oxysulfide (GOS), etc.

[0149] Specifically, the working process of the detection substrate shown in Figure 26 provided by the embodiment of the present disclosure is: when the high-energy particles of X-rays are impacted, the scintillator layer 14 converts the kinetic energy of the high-energy particles into light energy and emits a flash (visible light signal), and the light signal can be converted into an electrical signal through the photoelectric conversion device 3, and read out through the thin film transistor 2, so as to obtain an X-ray image through subsequent signal processing (including amplification, conversion, etc.).

[0150] Currently, the most widely used technologies for capturing dynamic images using thin-film transistor-based flat-panel detectors are IGZO thin-film transistor (TFT) and CMOS. However, both technologies still have significant drawbacks, such as IGZO's poor material stability, easy conductivity, and low product yield, while CMOS's high cost and difficulty in large-scale production are significant.

[0151] Although a-Si thin-film transistor technology is inferior to IGZO and CMOS in terms of performance, it is still sufficient to match some dynamic acquisition demand scenarios through some design optimizations. In addition, a-Si technology has absolute advantages over the above two technologies in terms of cost, yield, stability, and large area. Therefore, a-Si thin-film transistor technology still has high application and promotion potential in the field of dynamic image acquisition panels.

[0152] Therefore, in the detection substrate provided in the embodiment of the present disclosure, the material of the active layer includes amorphous silicon, that is, the present disclosure proposes a detection substrate design based on the a-Si thin film transistor process. Based on the basic structure of the detection substrate based on the a-Si thin film transistor process, the metal wiring layer used for the signal readout line connected to the second electrode in the pixel is adjusted and optimized through jumper holes with special definition requirements, and on this basis, several multi-layer wiring structures of the readout line are derived to reduce pixel noise. In addition, all embodiments involved in the present disclosure are fully compatible with the mass production process of the detection substrate based on the a-Si thin film transistor process. Compared with conventional solutions, the present disclosure does not require additional photolithography processes, has no additional development costs, and has high promotion potential.

[0153] Based on the same inventive concept, the present disclosure also provides a flat-panel detector, including the aforementioned detection substrate provided in the present disclosure. Because the principles of this flat-panel detector are similar to those of the aforementioned detection substrate, the implementation of this flat-panel detector can be referenced to the aforementioned detection substrate, and any repetitions will not be repeated.

[0154] The embodiments of the present disclosure provide a detection substrate and a flat-panel detector, in which the readout line originally provided in the source-drain metal layer in the related art is jumped to the bias voltage electrode layer through a second connection portion provided in the same layer as the bottom electrode, that is, the readout line is formed in the upper layer of the film layer stack structure through the second connection portion; it can be clearly seen from the cross-sectional structures of Figures 8 and 9 that, whether it is the overlapping capacitor Cgd or the coupling capacitor Cds / Cds', the distance between the two poles of the capacitor is significantly enlarged, so the capacitance values ​​of Cgd, Cds and Cds' are significantly reduced. Therefore, the embodiments of the present disclosure achieve a significant reduction in the capacitance on the readout line, which can significantly reduce pixel noise and improve the signal-to-noise ratio of the pixel, which is conducive to the application of the product and technology in dynamic image acquisition scenarios, thereby obtaining higher-quality dynamic images.

[0155] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0156] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. A detection substrate, wherein, Comprising: A substrate, and a gate metal layer, a source-drain metal layer, a photoelectric conversion device, and a bias voltage electrode layer disposed on the substrate; wherein, The gate metal layer includes a gate and a scan line electrically connected to the gate; The source-drain metal layer includes a first electrode, a second electrode, and a first connection portion electrically connected to the second electrode; The photoelectric conversion device includes a bottom electrode, a photoelectric conversion layer, and a top electrode stacked in sequence, the bottom electrode is close to the substrate, and the bottom electrode is electrically connected to the first electrode; The bias voltage electrode layer includes bias voltage lines and first read lines that are arranged at intervals and have the same extending direction; The detection substrate further includes a second connection portion disposed on the same layer as the bottom electrode, the first read line is electrically connected to the second connection portion, and the second connection portion is electrically connected to the first connection portion.

2. The detection substrate according to claim 1, wherein, Further comprising: A first insulating layer located between the source-drain metal layer and the bottom electrode, and a planarization layer located between the top electrode and the bias voltage electrode layer; wherein, The first connection portion is electrically connected to the second connection portion through a first via hole penetrating through the first insulating layer, and the second connection portion is electrically connected to the first read line through a first external hole penetrating through the planarization layer.

3. The detection substrate according to claim 2, wherein, Further comprising: A first buffer layer located between the top electrode and the planarization layer, and a second buffer layer located between the planarization layer and the bias voltage electrode layer; wherein, The second connection portion is further electrically connected to the first read line through a first internal hole penetrating through the first buffer layer and the second buffer layer, the first internal hole and the first external hole are sleeved to form a second via hole, the orthographic projection of the first internal hole on the substrate is located within the orthographic projection range of the first external hole on the substrate, and the inner wall of the first internal hole covers the inner wall of the first external hole.

4. The detection substrate according to claim 3, wherein, The orthographic projection of the first external hole on the substrate does not overlap with the orthographic projection of the first via hole on the substrate.

5. The detection substrate according to claim 4, wherein, The difference between the radius of the first external hole and the radius of the first internal hole is at least greater than or equal to a first distance, the distance between adjacent side walls of the first external hole and the first via hole is greater than or equal to a second distance, and the ratio of the first distance to the second distance is 3:1 to 1:

2.

6. The detection substrate according to claim 5, wherein, The first distance is 2 μm to 7 μm, and the second distance is 1 μm to 5 μm.

7. The detection substrate according to any one of claims 3-6, wherein, The bias voltage electrode layer further includes a third connection portion electrically connected to the first read line, and the third connection portion is electrically connected to the second connection portion through the second via hole; wherein, The orthographic projections of the first connection portion, the second connection portion, and the third connection portion on the substrate overlap each other.

8. The detection substrate according to claim 7, wherein, The first read line and the third connection portion are of an integral structure.

9. The detection substrate according to claim 8, wherein, The outer contours of the first connection portion, the second connection portion, and the third connection portion are the same.

10. The detection substrate according to claim 9, wherein, The orthographic projections of the first via hole and the second via hole on the substrate are both located within the orthographic projection ranges of the first connection portion, the second connection portion, and the third connection portion on the substrate.

11. The detection substrate according to any one of claims 3-10, wherein, The source-drain metal layer further includes a second read line electrically connected to the first connection portion. The second read line has the same extending direction as the first read line, and a positive projection of the second read line on the substrate overlaps a positive projection of the first read line on the substrate.

12. The detection substrate according to claim 11, wherein, The second read line and the first connection portion are of an integral structure.

13. The detection substrate according to any one of claims 3-12, wherein, The detection substrate further includes a third read line disposed in the same layer as the bottom electrode. The third read line is electrically connected to the second connection portion. The third read line has the same extending direction as the first read line, and a positive projection of the third read line on the substrate overlaps a positive projection of the first read line on the substrate.

14. The detection substrate according to claim 13, wherein, The third read line and the second connection portion are of an integral structure.

15. The detection substrate according to any one of claims 3-14, wherein, The first read line and the scan line are cross - arranged, and the first via hole and the second via hole are arranged along the extending direction of the first read line.

16. The detection substrate according to claim 15, wherein, The first via hole is close to the scan line adjacent to the first connection portion, or the second via hole is close to the scan line adjacent to the first connection portion.

17. The detection substrate according to claim 16, wherein, Positive projections of the center of the first via hole and the center of the second via hole on the substrate do not overlap a positive projection of the first read line on the substrate respectively.

18. The detection substrate according to claim 17, wherein, Positive projections of the center of the first via hole and the center of the second via hole on the substrate are located on the same side of the first read line.

19. The detection substrate according to claim 18, wherein, Positive projections of the center of the first via hole and the center of the second via hole on the substrate are located on a side of the first read line far from the second electrode to which it is electrically connected.

20. The detection substrate according to claim 18, wherein, Positive projections of the center of the first via hole and the center of the second via hole on the substrate are located on a side of the first read line close to the second electrode to which it is electrically connected.

21. The detection substrate according to any one of claims 3-14, wherein, The first read line and the scan line are cross - arranged, and the first via hole and the second via hole are arranged along the extending direction of the scan line.

22. The detection substrate according to claim 21, wherein, A positive projection of the center of the second via hole on the substrate is located on a side of the first read line far from the second electrode to which it is electrically connected, and the first via hole is located on a side away from the first read line with respect to the second via hole.

23. The detection substrate according to claim 19 or 22, wherein, The first connection portion is divided into a first region and a second region that are connected to each other along the extending direction of the first read line or along the extending direction of the scan line. The area of the first region is smaller than the area of the second region. The first via hole is located in the first region, and the second via hole is located in the second region; the outer contour shapes of the first connection portion and the adjacent optoelectronic conversion device are complementary.

24. The detection substrate according to any one of claims 3-23, wherein, The bias voltage line is electrically connected to the top electrode through a third via hole penetrating the second buffer layer, the planarization layer, and the first buffer layer. The third via hole includes a sleeved second outer hole and a second inner hole. The second outer hole penetrates the planarization layer, and the second inner hole penetrates the first buffer layer and the second buffer layer. The inner wall of the second inner hole covers the inner wall of the second outer hole; wherein The radius of the first inner hole is greater than or equal to the radius of the second inner hole, and the radius of the first outer hole is greater than or equal to the radius of the second outer hole.

25. The detection substrate according to claim 24, wherein, The radius of the first inner hole is 1 μm to 7 μm larger than the radius of the second inner hole, and the radius of the first outer hole is 1 μm to 7 μm larger than the radius of the second outer hole.

26. The detection substrate according to any one of claims 1-25, wherein, Further included are: a second insulating layer on the side of the bias voltage electrode layer facing away from the substrate, and a shielding layer on the side of the second insulating layer facing away from the substrate; The orthographic projection of the shielding layer on the substrate covers the orthographic projection of the side wall of the photoelectric conversion device on the substrate.

27. The detection substrate according to any one of claims 1-26, wherein, The substrate includes a photosensitive region and a peripheral region surrounding the photosensitive region. The peripheral region includes a bias voltage electrode ring electrically connected to the bias voltage line. The bias voltage electrode ring includes a plurality of conductive structures surrounding the peripheral region and arranged at intervals, and adjacent conductive structures are electrically connected through a plurality of fourth connection portions located in the bias voltage electrode layer; The first read line is located in the photosensitive region and extends between the bias voltage electrode ring and the photosensitive region. The peripheral region further includes a read lead located in the gate metal layer and overlapping with the fourth connection portion. One end of the first read line extending between the bias voltage electrode ring and the photosensitive region is electrically connected to the first end of the read lead through a fifth connection portion arranged in the same layer as the bottom electrode. The second end of the read lead is electrically connected to a fan-out lead, and the fan-out lead is arranged in the same layer as the bottom electrode.

28. The detection substrate according to claim 27, wherein, Further included are: a gate insulating layer between the gate metal layer and the source-drain metal layer, and an active layer between the gate insulating layer and the source-drain metal layer; The active layer is in direct contact with the source-drain and the second electrode; wherein, One end of the first read line extending between the bias voltage electrode ring and the photosensitive region is electrically connected to the fifth connection portion through a fourth via hole penetrating through the second buffer layer, the planarization layer, and the first buffer layer. The fifth connection portion is electrically connected to the first end of the read lead through a fifth via hole penetrating through the first insulating layer and the gate insulating layer; The second end of the read lead is electrically connected to the fan-out lead through a sixth via hole penetrating through the first insulating layer and the gate insulating layer.

29. The detection substrate according to claim 28, wherein, Each of the conductive structures on both sides of the extending direction of the first read line is located between adjacent read leads, and each of the conductive structures on both sides of the extending direction of the scan line is located between adjacent scan lines.

30. A flat panel detector, wherein, Including the detection substrate according to any one of claims 1-29.

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