Communication method based on LDPC code, and communication apparatus

Abstract

A communication method based on an LDPC code, and a communication apparatus. Encoding or decoding can be performed on the basis of a storage matrix and indication information, the indication information may comprise first information, each row pair among a plurality of row pairs indicated by the first information comprises two rows, and a set composed of column numbers of columns where non-zero elements in the first X elements of a first row in the two rows are located is a proper subset of a set composed of column numbers of columns where non-zero elements in the first X elements of a second row in the two rows are located, so that splitting extension is realized in the low bit rate extension process, that is, the first row can be subjected to elimination on the basis of increasing the second row so as to increase the orthogonality between rows. Moreover, a plurality of first rows indicated by the first information can form one or more row groups, and first rows comprised in each row group have an association relationship, so that the orthogonality can be further increased on the basis of the association relationship. Therefore, it is helpful to increase the orthogonality between rows, thereby improving decoding performance.

Description

A communication method and communication device based on LDPC code

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on October 30, 2023, with application number 202311433976.3, and priority to the Chinese patent application entitled “A communication method and communication device based on LDPC code”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of coding, and more particularly, to a communication method and a communication device based on LDPC codes. Background Art

[0003] In the field of channel coding, low-density parity check (LDPC) codes are one of the most mature and widely used channel coding schemes. Current LDPC codes suffer from low orthogonality between rows in the LDPC basis matrix, which impacts decoding efficiency and performance. For example, new radio (NR) LDPC codes have high edge density in the high-rate portion, resulting in a lack of orthogonality between rows and supporting only parallel decoding of quasi-cyclic (QC) blocks.

[0004] Summary of the Invention

[0005] The embodiments of the present application provide a communication method and a communication device based on LDPC codes, which help to improve decoding performance.

[0006] In a first aspect, a communication method based on LDPC codes is provided, which can be executed by a transmitting device or a module or unit in the transmitting device (e.g., a chip). The transmitting device can be a terminal device or a network device.

[0007] The method includes: obtaining an information bit sequence; performing LDPC encoding on the information bit sequence according to a first LDPC base matrix and indication information to obtain an LDPC codeword sequence; wherein the indication information includes first information, the first information being used to indicate a plurality of row pairs, each of the plurality of row pairs including a first row and a second row, a set consisting of column numbers of columns where non-zero elements among the first x elements of the first row of the row pair are located is a proper subset of a set consisting of column numbers of columns where non-zero elements among the first x elements of the second row of the row pair are located, and x is a positive integer; the plurality of first rows indicated by the first information form one or more row groups, each of the one or more row groups including at least two first rows, a column weight of each column of a matrix region formed by the second rows corresponding to the at least two first rows being less than or equal to 2, and the at least two first rows being associated with each other; and sending the LDPC codeword sequence.

[0008] Exemplarily, x is the total number of information columns and core check columns.

[0009] In the above method, each of the multiple row pairs indicated by the first information includes two rows, and the set consisting of the column numbers of the columns containing the non-zero elements in the first x elements of the first row of the two rows is a proper subset of the set consisting of the column numbers of the columns containing the non-zero elements in the first x elements of the second row of the two rows. This supports splitting expansion during low-rate scaling, i.e., eliminating the first row while adding the second row to improve orthogonality between rows. Furthermore, the multiple first rows indicated by the first information can be organized into one or more row groups, and at least two first rows included in each row group are associated with each other. This association can further enhance orthogonality. For example, based on this association, the rows in the second LDPC base matrix corresponding to the first row of a row group and the rows in the second LDPC base matrix corresponding to the second row of the first row of the row group can be regrouped to ensure that the rows within each newly obtained group are completely orthogonal. Therefore, the above method can improve orthogonality between rows, facilitate row-parallel decoding at the receiving end device, and thus improve decoding performance.

[0010] In combination with the first aspect, in some implementations, the performing LDPC encoding on the information bit sequence according to the first LDPC base matrix and the indication information to obtain an LDPC codeword sequence includes: obtaining a second LDPC base matrix according to the first LDPC base matrix and the indication information; performing LDPC encoding on the information bit sequence according to the second LDPC base matrix to obtain an LDPC codeword sequence, wherein the row of the second LDPC base matrix corresponding to the first row is obtained by eliminating the second row in the same row pair by the first row.

[0011] In the above implementation, when obtaining the second LDPC basis matrix used for encoding, the row corresponding to the first row of the second LDPC basis matrix is ​​obtained by eliminating the second row in the same row pair by the first row. This can improve the orthogonality between rows, help to achieve row-parallel decoding of the receiving device, and thus improve decoding performance.

[0012] In combination with the first aspect or any implementation manner thereof, in other implementation manners, the association relationship includes a first association relationship and / or a second association relationship. The two first rows having the first association relationship are mutually orthogonal, and the union of the column numbers of the columns containing the non-zero elements of the two first rows includes the intersection of the column numbers of the columns containing the non-zero elements of the two second rows corresponding to the two first rows; and the two first rows having the second association relationship have the same connecting edge at the first position, and the column number at the first position belongs to the intersection of the column numbers of the columns containing the non-zero elements of the two second rows corresponding to the two first rows.

[0013] In the above implementation, possible implementations for an association relationship between at least two first rows included in a row group are provided. Based on these possible implementations, the rows in the second LDPC base matrix corresponding to the first row in a row group and the rows in the second LDPC base matrix corresponding to the second row in the row group can be regrouped so that the rows in each newly obtained group are completely orthogonal.

[0014] Exemplarily, the rows in the second LDPC base matrix corresponding to the first row in a row group and the rows in the second LDPC base matrix corresponding to the second row corresponding to the first row in the row group can be divided into two groups, referred to as the first row set and the second row set, respectively, wherein the union of the first row set and the second row set includes the rows in the second LDPC base matrix corresponding to the first row in a row group and the rows in the second LDPC base matrix corresponding to the second row corresponding to the first row in the row group.

[0015] The first row set is composed of rows in the second LDPC base matrix corresponding to rows in the first subset and / or rows in the second LDPC base matrix corresponding to rows in the second subset, wherein the rows in the first subset are all first rows, and each first row in the first subset has a first association relationship, and the rows in the second subset are all second rows, and the first row corresponding to the second row in the second subset has a second association relationship with the first row in the first subset.

[0016] The second row set is composed of rows in the second LDPC base matrix corresponding to rows in the third subset and / or rows in the second LDPC base matrix corresponding to rows in the fourth subset. The third subset is composed of the second row corresponding to the first row in the first subset, the fourth subset is composed of the first row corresponding to the second row in the second subset, and each pair of first rows in the fourth subset has a first association relationship.

[0017] It should be noted that when there is only one row in the first row set, the first subset, the second subset, the second row set, the third subset or the fourth subset, the definition of these sets may not involve the description of the first association relationship and / or the second association relationship.

[0018] In combination with the first aspect or any implementation thereof, in some other implementations, in any combination of the at least two first rows, the number of combinations having the first association relationship and the number of combinations having the second association relationship are related to the number of the first rows included in the at least two first rows.

[0019] In combination with the first aspect or any implementation thereof, in other implementations, in any combination of the at least two first rows, The combination has the first association relationship, combinations have the second association relationship, wherein k is the number of the first rows included in the at least two first rows, represents the number of combinations of selecting two rows from ki rows, represents the number of combinations of any two rows from k rows, It represents the number of combinations of selecting two rows from i rows. Indicates rounding down.

[0020] Based on the quantitative relationship between the combinations with the first association relationship and the combinations with the second association relationship provided in the above embodiments, the rows corresponding to the first row in a row group in the second LDPC base matrix and the rows corresponding to the second row in the first row in the row group in the second LDPC base matrix can be regrouped so that the rows in each newly obtained group are completely orthogonal.

[0021] In combination with the first aspect or any implementation thereof, in other implementations, for a row group including k first rows, the number of combinations with the first association relationship and the number of combinations with the second association relationship are distributed in a total of In this case, in the combination of the first two rows in the row group, The combination has a first association relationship, The combination has a second relationship, represents the number of combinations of selecting two rows from ki rows, represents the number of combinations of any two rows from k rows, It represents the number of combinations of selecting two rows from i rows. Indicates rounding up.

[0022] Based on the quantitative relationship between the combinations with the first association relationship and the combinations with the second association relationship provided in the above embodiments, the rows corresponding to the first row in a row group in the second LDPC base matrix and the rows corresponding to the second row in the first row in the row group in the second LDPC base matrix can be regrouped so that the rows in each newly obtained group are completely orthogonal.

[0023] In combination with the first aspect or any implementation thereof, in some other implementations, each row pair of the multiple row pairs corresponds to two rows of the first LDPC basis matrix; the indication information is in the form of a sequence, and the first information is a sequence consisting of the row number of the second row of each row pair in the one or more row pairs; in one of the row pairs, the position of the row number of the second row in the sequence corresponding to the indication information is the row number of the first row, and the position of the row number of the second row in the sequence corresponding to the indication information is greater than the row number of the first row.

[0024] In combination with the first aspect or any implementation thereof, in some other implementations, the sequence corresponding to the first information includes one or more segments, and the row number in the t-th segment of the one or more segments is {1, 2, ..., 2 t-1 M-1,2 t-1 M}, where t and M are positive integers.

[0025] Exemplarily, M may be the number of core rows.

[0026] In the above implementation, each row number appears only once in a round of splitting, so multiple splits included in each round can be executed in parallel, which helps to improve splitting efficiency.

[0027] In combination with the first aspect or any implementation thereof, in some other implementations, the indication information further includes second information, where the second information is used to indicate one or more third rows, wherein the one or more third rows of the second LDPC base matrix are the same as the one or more third rows of the first LDPC base matrix.

[0028] The second information may correspond to a traditional extension or a normal extension.

[0029] In the above implementation, the indication information includes two types of information: one type of information is used to indicate one or more row pairs, corresponding to split expansion, and the other type of information is used to indicate one or more rows, corresponding to traditional expansion. This allows the indication information to indicate two different low-rate expansion methods using these two types of information. In other words, during the low-rate expansion process, there are two expansion methods, and the indication information can determine which of the two methods a particular expansion is performed. This makes low-rate expansion more flexible than using only one expansion method, helping to obtain an LDPC base matrix with better performance.

[0030] In combination with the first aspect or any implementation thereof, in some other implementations, the second information includes one or more first characters, and the positions of the one or more first characters in the sequence corresponding to the indication information correspond to the row numbers of the one or more third rows.

[0031] In combination with the first aspect or any implementation thereof, in some other implementations, the indication information further includes third information, where the third information is used to indicate one or more fourth rows. The one or more fourth rows of the second LDPC base matrix are the same as the one or more fourth rows of the first LDPC base matrix. The rows indicated by the fourth information may be core rows of the second LDPC base matrix.

[0032] In combination with the first aspect or any implementation thereof, in some other implementations, the third information includes M second characters or M row numbers, and the M row numbers are 1, 2, ..., M-1, M in sequence, where M is a positive integer.

[0033] Exemplarily, M may be the number of core rows.

[0034] In combination with the first aspect or any implementation manner thereof, in some other implementation manners, the first character and / or the second character is a value other than a row number of the first LDPC basis matrix.

[0035] By setting the first character or the second character to a value other than the row number of the first LDPC base matrix, the first character or the second character can be well distinguished from the row number in the first information.

[0036] In combination with the first aspect or any implementation thereof, in some other implementations, the sequence corresponding to the indication information includes a first segment, a second segment, a third segment, a fourth segment and a fifth segment in sequence, wherein the first segment is composed of the third information, the second segment is composed of the first part of the second information, the third segment is composed of the first part of the first information, the fourth segment is composed of the second part of the first information and the second part of the second information, and the fifth segment is composed of the third part of the second information.

[0037] Based on the above sequence, it helps to ensure that each expansion maintains the optimal edge density.

[0038] In combination with the first aspect or any implementation thereof, in some other implementations, the third segment includes one or more sub-segments, and the row number in the r-th segment of the one or more sub-segments is {1, 2, ..., 2 r-1 (M+T)-1,2 r-1 (M+T)}, wherein r is a positive integer and T is the number of characters in the first part of the second information.

[0039] Exemplarily, M may be the number of core rows.

[0040] In the above implementation, each row number appears only once in a round of splitting, so multiple splits included in each round can be executed in parallel, which helps to improve splitting efficiency.

[0041] In a second aspect, a communication method based on LDPC codes is provided. The method can be executed by a receiving device or by a module or unit in the receiving device (e.g., a chip). The receiving device can be a terminal device or a network device. The terms or features in the second aspect or its implementation that are the same or corresponding to those in the first aspect or its implementation can refer to the first aspect or its implementation, and the technical effects thereof can refer to the technical effects in the first aspect or its implementation, and will not be repeated in the second aspect.

[0042] The method includes: receiving an LDPC codeword sequence; decoding the LDPC codeword sequence according to a first LDPC base matrix and indication information; wherein the indication information includes first information, the first information being used to indicate a plurality of row pairs, each row pair in the plurality of row pairs including a first row and a second row, a set consisting of column numbers of columns where non-zero elements among the first x elements of the first row in the row pair are located is a proper subset of a set consisting of column numbers of columns where non-zero elements among the first x elements of the second row in the row pair are located, and x is a positive integer; the plurality of first rows indicated by the first information form one or more row groups, each row group in the one or more row groups includes at least two first rows, a column weight of each column of a matrix region formed by the second rows corresponding to the at least two first rows is less than or equal to 2, and the at least two first rows are associated with each other.

[0043] In combination with the second aspect, in some implementations, decoding the LDPC codeword sequence according to the first LDPC base matrix and the indication information includes: obtaining a second LDPC base matrix according to the first LDPC base matrix and the indication information; decoding the LDPC codeword sequence according to the second LDPC base matrix, wherein the row of the second LDPC base matrix corresponding to the first row is obtained by eliminating the second row in the same row pair by the first row.

[0044] In combination with the second aspect or any implementation manner thereof, in other implementation manners, the association relationship includes a first association relationship and / or a second association relationship. The two first rows having the first association relationship are mutually orthogonal, and the union of the column numbers of the columns containing the non-zero elements of the two first rows includes the intersection of the column numbers of the columns containing the non-zero elements of the two second rows corresponding to the two first rows; and the two first rows having the second association relationship have the same connecting edge at the first position, and the column number at the first position belongs to the intersection of the column numbers of the columns containing the non-zero elements of the two second rows corresponding to the two first rows.

[0045] In combination with the second aspect or any implementation thereof, in other implementations, decoding the LDPC codeword sequence according to the second LDPC base matrix includes: performing row-parallel decoding on the portion of the LDPC codeword sequence corresponding to rows in a first row set, and performing row-parallel decoding on the portion of the LDPC codeword sequence corresponding to rows in a second row set. The union of the first row set and the second row set includes rows in the second LDPC base matrix corresponding to the at least two first rows, and rows in the second LDPC base matrix corresponding to the second rows corresponding to the at least two first rows. The first row set consists of rows in the second LDPC base matrix corresponding to rows in a first subset and / or rows in the second LDPC base matrix corresponding to rows in a second subset, wherein all rows in the first subset are the first rows and the first rows in the first subset have the first association relationship with each other, and all rows in the second subset are the second rows and the first rows corresponding to the second rows in the second subset have the second association relationship with the first rows in the first subset. The second row set is composed of rows in the second LDPC base matrix corresponding to rows in the third subset and / or rows in the second LDPC base matrix corresponding to rows in the fourth subset, the third subset is composed of the second rows corresponding to the first rows in the first subset, the fourth subset is composed of the first rows corresponding to the second rows in the second subset, and the first rows in the fourth subset have the first association relationship in pairs.

[0046] In combination with the second aspect or any implementation thereof, in some other implementations, in any combination of the at least two first rows, the number of combinations having the first association relationship and the number of combinations having the second association relationship are related to the number of the first rows included in the at least two first rows.

[0047] In combination with the second aspect or any implementation thereof, in some other implementations, in any combination of the at least two first rows, The combination has the first association relationship, combinations have the second association relationship, wherein k is the number of the first rows included in the at least two first rows, represents the number of combinations of selecting two rows from ki rows, represents the number of combinations of any two rows from k rows, It represents the number of combinations of selecting two rows from i rows. Indicates rounding down.

[0048] In combination with the second aspect or any implementation thereof, in other implementations, for a row group including k first rows, the number of combinations with the first association relationship and the number of combinations with the second association relationship are distributed in a total of In this case, in the combination of the first two rows in the row group, The combination has a first association relationship, The combination has a second association relationship, represents the number of combinations of selecting two rows from ki rows, represents the number of combinations of any two rows from k rows, It represents the number of combinations of selecting two rows from i rows. Indicates rounding up.

[0049] In combination with the second aspect or any implementation thereof, in some other implementations, each row pair of the multiple row pairs corresponds to two rows of the first LDPC basis matrix; the indication information is in the form of a sequence, and the first information is a sequence consisting of the row number of the second row of each row pair in the one or more row pairs; in one of the row pairs, the position of the row number of the second row in the sequence corresponding to the indication information is the row number of the first row, and the position of the row number of the second row in the sequence corresponding to the indication information is greater than the row number of the first row.

[0050] In combination with the second aspect or any implementation thereof, in some other implementations, the sequence corresponding to the first information includes one or more segments, and the row number in the t-th segment of the one or more segments is {1, 2, ..., 2t-1 M-1,2 t-1 M}, where t and M are positive integers.

[0051] In combination with the second aspect or any implementation manner thereof, in some other implementation manners, the indication information further includes second information, and the second information is used to indicate one or more third rows.

[0052] In combination with the second aspect or any implementation thereof, in some other implementations, the second information includes one or more first characters, and positions of the one or more first characters in the sequence corresponding to the indication information correspond to row numbers of the one or more third rows.

[0053] In combination with the second aspect or any implementation manner thereof, in some other implementation manners, the indication information further includes third information, and the third information is used to indicate one or more fourth rows.

[0054] In combination with the second aspect or any implementation thereof, in some other implementations, the third information includes M second characters or M row numbers, and the M row numbers are 1, 2, ..., M-1, M in sequence, where M is a positive integer.

[0055] In combination with the second aspect or any implementation thereof, in some other implementations, the first character and / or the second character is a value other than a row number of the first LDPC basis matrix.

[0056] In combination with the second aspect or any implementation thereof, in some other implementations, the sequence corresponding to the indication information includes a first segment, a second segment, a third segment, a fourth segment and a fifth segment in sequence, wherein the first segment is composed of the third information, the second segment is composed of the first part of the second information, the third segment is composed of the first part of the first information, the fourth segment is composed of the second part of the first information and the second part of the second information, and the fifth segment is composed of the third part of the second information.

[0057] In combination with the second aspect or any implementation thereof, in some other implementations, the third segment includes one or more sub-segments, and the row number in the r-th segment of the one or more sub-segments is {1, 2, ..., 2 r-1 (M+T)-1,2 r-1 (M+T)}, wherein r is a positive integer and T is the number of characters in the first part of the second information.

[0058] In a third aspect, a communication device is provided, configured to execute the method provided by any of the above aspects or implementations thereof. Specifically, the device may include units and / or modules, such as a processing unit and / or a transceiver unit, configured to execute the method provided by any of the above aspects or implementations thereof.

[0059] In one implementation, the apparatus is a transmitting device or a receiving device. When the apparatus is a transmitting device or a receiving device, the transceiver unit may be a transceiver, an input / output interface, or a communication interface; and the processing unit may be at least one processor. Optionally, the transceiver is a transceiver circuit. Optionally, the input / output interface is an input / output circuit.

[0060] In another implementation, the apparatus is a chip, chip system, or circuit used in a transmitting device or a receiving device. When the apparatus is a chip, chip system, or circuit used in a transmitting device or a receiving device, the transceiver unit may be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit; and the processing unit may be at least one processor, processing circuit, or logic circuit.

[0061] In a fourth aspect, a communication device is provided, comprising: a memory for storing programs; and at least one processor for executing computer programs or instructions stored in the memory to perform the method provided by any one of the above aspects or its implementation.

[0062] In one implementation, the apparatus is a transmitting end device or a receiving end device.

[0063] In another implementation, the apparatus is a chip, a chip system, or a circuit used in a transmitting device or a receiving device.

[0064] In a fifth aspect, a communication device is provided, comprising: at least one processor and a communication interface, wherein the at least one processor is configured to retrieve a computer program or instruction stored in a memory through the communication interface to execute the method provided by any of the above aspects or implementations thereof. The communication interface may be implemented in hardware or software.

[0065] In one implementation, the device further includes the memory.

[0066] In a sixth aspect, a processor is provided for executing the methods provided in the above aspects.

[0067] For the operations such as sending and acquiring / receiving involved in the processor, unless otherwise specified, or if they do not conflict with their actual functions or internal logic in the relevant descriptions, they can be understood as operations such as processor output, reception, and input, or as sending and receiving operations performed by the radio frequency circuit and antenna. This application does not limit this.

[0068] In a seventh aspect, a computer-readable storage medium is provided, which stores a program code for execution by a device, wherein the program code includes a method for executing any one of the above aspects or its implementation.

[0069] In an eighth aspect, a computer program product comprising instructions is provided, which, when run on a computer, enables the computer to execute the method provided by any one of the above aspects or its implementation.

[0070] In a ninth aspect, a chip is provided, comprising a processor and a communication interface, wherein the processor reads instructions stored in a memory through the communication interface and executes the method provided by any one of the above aspects or implementations thereof. The communication interface may be implemented in hardware or software.

[0071] Optionally, as an implementation method, the chip also includes a memory, in which a computer program or instruction is stored, and the processor is used to execute the computer program or instruction stored in the memory. When the computer program or instruction is executed, the processor is used to execute the method provided by any of the above aspects or its implementation methods.

[0072] When the method provided in this application is executed by a chip, this application does not limit the number of chips that implement the method. For example, the method can be executed by one chip or by two or more chips. Furthermore, when the number of chips implementing the method of this application is two or more, the chip manufacturers are not limited and can be the same manufacturer or different manufacturers.

[0073] In a tenth aspect, a communication system is provided, comprising at least one of the transmitting device or the receiving device described above.

[0074] In an eleventh aspect, a computer program is provided, which, when executed on a computer, enables the method provided by any one of the above aspects or its implementation to be executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] FIG1 is a schematic diagram of a network architecture to which embodiments of the present application can be applied.

[0076] FIG2 is a schematic diagram of an LDPC check matrix H.

[0077] FIG3 is a Tanner graph of an LDPC check matrix H.

[0078] FIG4 is a schematic diagram of the structure of a check matrix.

[0079] FIG. 5 shows an example of a non-column-regularized grouping structure and a column-regularized grouping structure.

[0080] Figure 6 is an example of traditional expansion and split expansion.

[0081] FIG7 is a schematic flowchart of a communication method 700 based on LDPC codes provided in this application.

[0082] FIG8 is a schematic diagram of the first association relationship.

[0083] FIG9 is a schematic diagram of the second association relationship.

[0084] FIG10 is an example of a technical solution of an embodiment of the present application.

[0085] FIG11 is another example of the technical solution of an embodiment of the present application.

[0086] FIG12 is another example of the technical solution of an embodiment of the present application.

[0087] FIG13 is another example of the technical solution of an embodiment of the present application.

[0088] FIG14 is a simulation result 1 of the difference in signal-to-noise ratio (SNR) between the NR LDPC code and the LDPC code of the present application at different code rates.

[0089] FIG15 is a second simulation result of the difference between the SNR of the NR LDPC code and the LDPC code of the present application at different code rates.

[0090] FIG16 is a schematic structural diagram of a device provided in an embodiment of the present application.

[0091] FIG17 is another schematic structural diagram of the device provided in an embodiment of the present application.

[0092] FIG18 is a schematic diagram of a chip system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0093] To facilitate understanding of the embodiments of the present application, the following explanations are made before introducing the embodiments of the present application.

[0094] "For indicating" or "indicating" can include direct indication and indirect indication, or "for indicating" or "indicating" can be explicitly and / or implicitly indicated. The various numerical numbers such as first, second, etc. are only used for the convenience of description and are not used to limit the scope of the embodiments of the present application, such as distinguishing different messages, different information, etc. "Pre-definition" can be implemented by pre-saving corresponding codes, tables or other methods that can be used to indicate relevant information in the device. This application does not limit its specific implementation method. The "protocol" involved may refer to a standard protocol in the communication field, for example, it may include the Long Term Evolution (LTE) protocol, the NR protocol and related protocols used in future communication systems. This application does not limit this. Words such as "exemplary", "for example", "exemplarily", "as (another) example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as an "example" in this application should not be construed as being preferred or advantageous over other embodiments or design schemes. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized. "At least one" means one or more, and "a plurality" means two or more. "At most one" means one or zero. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can mean: a, or b, or c, or a and b, or a and c, or b and c, or a, b and c. Where a, b and c can be single or multiple, respectively. Descriptions of network element A sending a message, information, or data to network element B, or network element B receiving a message, information, or data from network element A, are intended to clarify the network element to which the message, information, or data is sent, and do not limit whether the messages, information, or data are sent directly or indirectly through other network elements. Phrases such as "when," "under the circumstances," "if," and "if" all imply that the device will take appropriate action under certain objective circumstances. They do not specify a time limit, do not require the device to perform a judgment action, and do not imply any other limitations.

[0095] In addition, the network architecture and business scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field can know that with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0096] A communication system to which the embodiments of the present application can be applied is described below.

[0097] The embodiments of the present application can be applied to various communication systems, including but not limited to: fifth generation (5G) system or NR system, LTE system, long term evolution-advanced (LTE-A) system, LTE frequency division duplex (FDD) system, LTE time division duplex (TDD) system, etc. It can also be applied to future communication systems, such as the sixth generation mobile communication system. In addition, it can also be applied to device to device (D2D) communication, vehicle-to-everything (V2X) communication, machine to machine (M2M) communication, machine type communication (MTC), Internet of Things (IoT) communication system, narrowband Internet of Things (NB-IoT) system or other communication systems. In addition, the present invention can also be extended to similar wireless communication systems, such as wireless-fidelity (WiFi), worldwide interoperability for microwave access (WIMAX), and communication systems related to the 3rd Generation Partnership Project (3GPP), without limitation.

[0098] A communication system applicable to embodiments of the present application may include one or more transmitting devices and one or more receiving devices. Optionally, one of the transmitting device and the receiving device may be a terminal device, and the other may be a network device. Optionally, both the transmitting device and the receiving device may be terminal devices. Optionally, both the transmitting device and the receiving device may be network devices.

[0099] Exemplarily, FIG1 shows a schematic diagram of a network architecture to which an embodiment of the present application may be applied.

[0100] As shown in Figure 1, the embodiments of the present application can be applied to both uplink data transmission and downlink data transmission. Figure 1 only takes uplink data transmission or downlink data transmission between a network device and two terminal devices (such as terminal device 1 and terminal device 2) as an example. In uplink data transmission, the transmitting device in this article is a terminal device, and the receiving device is a network device; conversely, in downlink data transmission, the transmitting device is a network device, and the receiving device is a terminal device. In addition, the applicability of the embodiments of the present application in other communication scenarios is not limited. For example, it can also be applied to sidelink communications.

[0101] The terminal device of the present application may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, drone, wireless communication device, user agent or user device, etc. The terminal device in the embodiments of the present application may refer to a device that provides voice and / or data connectivity to a user and can be used to connect people, objects and machines, such as a handheld device with wireless connection function, a vehicle-mounted device, etc. The terminal device in the embodiments of the present application can be a mobile phone, a tablet computer, a laptop computer, a PDA, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, etc.

[0102] The network device of the present application may be a device with wireless transceiver functions, and the network device may be a device that provides wireless communication function services, usually located on the network side, including but not limited to the next-generation base station (gNodeB, gNB) in the 5G system, the base station in the sixth-generation mobile communication system, the base station in the future mobile communication system, or the access node in the wireless fidelity (WiFi) system, the evolved node B (eNB) in the long-term evolution (LTE) system, the radio network controller (RNC), the node B (NB), the base station controller (BSC), the home base station (for example, home evolved NodeB or home Node B, HNB), the base band unit (BBU), the transmission reception point (TRP), the transmitting point (TP), the base transceiver station (BTS), the satellite, the drone, etc. In a network structure, the network device may include a centralized unit (CU) node, or a distributed unit (DU) node, or a RAN device including a CU node and a DU node, or a RAN device including a control plane CU node and a user plane CU node, and a DU node, or the network device may also be a wireless controller, relay station, vehicle-mounted device, and wearable device in a cloud radio access network (CRAN) scenario. In addition, the base station may be a macro base station, a micro base station, a relay node, a donor node, or a combination thereof. The base station may also refer to a communication module, a modem, or a chip for being set in the aforementioned device or apparatus. The base station may also be a mobile switching center and a device that performs the base station function in D2D, V2X, and M2M communications, a network-side device in a 6G network, or a device that performs the base station function in future communication systems. The base station can support networks with the same or different access technologies without limitation.

[0103] Unless otherwise specified, the device used to implement the function of a terminal device or network device in this application may refer to the terminal device or network device itself, or may refer to a device that can support the terminal device or network device to implement the function, such as a chip system or chip, specifically, a system on a chip (SoC) or a modem. The device can be installed in the terminal device or network device. In the embodiments of the present application, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0104] It should also be noted that some embodiments herein use the 5G system as an example to describe specific solution details. It is understood that when this solution is applied to other communication systems, such as the LTE system or future communication systems, the messages, channels, or information in the solution can be replaced with messages, channels, or information in other communication systems that can implement corresponding functions, and this application does not limit this.

[0105] In addition, the embodiments of the present application can be applied to various application scenarios, such as high-throughput scenarios, high-reliability scenarios, low-latency scenarios, high-reliability and low-latency scenarios, or low-power scenarios. Among them, the high-throughput scenario can be, for example, an enhanced mobile broadband (eMBB) scenario, the high-reliability and low-latency scenario can be, for example, an URLLC (Ultra Reliable Low Latency Communication) scenario, and the low-power scenario can be, for example, an M2M scenario, an MTC scenario, or an IoT scenario.

[0106] To facilitate understanding of the embodiments of the present application, several concepts or terms involved in the embodiments of the present application are briefly explained. The concepts or terms introduced below are explained based on the concepts or terms specified in the reference protocol, but this does not mean that the embodiments of the present application can only be applied to existing systems. The concepts or terms involved in the embodiments of the present application can be applied to future systems. The specific names of the concepts or terms (for example, concepts or terms involving functional descriptions) can be adjusted as future systems develop.

[0107] 1. LDPC Code

[0108] LDPC codes are linear block codes whose parity check matrices are sparse. The number of zero elements in an LDPC parity check matrix far outnumbers the number of nonzero elements. In other words, the row and column weights of the parity check matrix are very small compared to the LDPC code length. An LDPC code with an information bit sequence length equal to q and a code length equal to n can be uniquely identified by its parity check matrix.

[0109] In 1981, Tanner represented LDPC codewords using a graph, now called a Tanner graph. There is a one-to-one correspondence between a Tanner graph and a parity check matrix. A Tanner graph consists of two types of vertices: one type represents codeword bits, called variable nodes, and the other type is called check nodes, representing check constraints. Each check node represents a check constraint. This is explained below with reference to Figures 2 and 3.

[0110] FIG2 is a schematic diagram of an LDPC check matrix H.

[0111] In Figure 2, {V i} represents the variable node (VN) set, {C i} represents the set of check nodes (CN). Each row of the check matrix H represents a check equation, each check equation corresponds to a check node, and each column represents a codeword bit, each codeword bit corresponds to a variable node. In Figure 2, there are eight variable nodes and four check nodes. If a codeword bit is included in the corresponding check equation, a line is connected between the variable node and the check node involved, resulting in a Tanner graph.

[0112] FIG3 is a Tanner graph of an LDPC check matrix H.

[0113] As shown in Figure 3, the Tanner graph represents the LDPC parity check matrix. For example, for a parity check matrix H with m rows and n columns, the Tanner graph contains two types of nodes: n variable nodes and m check nodes. The n variable nodes correspond to the n columns of the parity check matrix H, and the m check nodes correspond to the m rows of the parity check matrix H. A cycle in a Tanner graph consists of interconnected vertices. The cycle has one vertex in this group as both its starting and ending point, and passes through each node only once. The length of a cycle is defined as the number of edges it contains, while the girth of the graph, also known as its size, is defined as the minimum cycle length in the graph. In Figure 3, the girth is 4, as indicated by the black lines. The variable nodes in the Tanner graph correspond to each column of the parity check matrix H, which in turn corresponds to each codeword bit of the LDPC codeword. The check nodes in the Tanner graph correspond to each row of the parity check matrix H, which in turn corresponds to each parity bit of the LDPC codeword. The connections between the two types of nodes correspond to the values ​​of the elements in the H matrix. If there is a connection between the i-th check node and the j-th variable node, the element (i, j) in the H matrix is ​​1. If there is no connection, the corresponding element is 0. The connection between a variable node and a check node can also be called an edge. A connection between a check node and a variable node can also be described as having a connection or edge between the check node and the variable node. The edge relationship between a check node and a variable node can include either the presence of an edge or the absence of an edge.

[0114] In addition, in the Tanner graph, a cycle refers to a closed loop consisting of variable nodes, check nodes, and edges connected end to end.

[0115] As mentioned above, LDPC is a linear block code. It divides the information sequence to be encoded into groups of q bits. The encoder then performs linear operations on these q information bits to obtain m parity bits. These q information bits are then combined with the m parity bits to form a codeword of length n = q + m. The mapping from q information bits to a codeword of length n is typically represented by a corresponding parity check matrix H. Based on the parity check matrix H, a codeword sequence is generated to complete the encoding process. After the codeword sequence is transmitted over the channel, the receiving device decodes the received signal and determines the original information bits.

[0116] 2. QC-LDPC code

[0117] Quasi-cyclic low density parity check (QC-LDPC) codes are a type of structured LDPC codes. Due to the unique structure of its parity check matrix, encoding can be implemented using a simple feedback shift register, reducing the coding complexity of LDPC codes. When the code length is long, the parity check matrix H of the LDPC code will be very large. Therefore, H is usually represented in blocks: the complete parity check matrix H is considered to be composed of multiple Z c ×Z c Specifically, the complete check matrix H can be generated by a base matrix H b Indicates that H b Each element in corresponds to a Z c ×Z c Each submatrix can be represented by the number of cyclic shift bits, thus greatly reducing the storage space required for the complete check matrix H. b The elements in can also be called QC blocks.

[0118] Based on the basis matrix H b And the improvement value Z c (lifting size), the basis matrix H b Expanded to a complete check matrix for encoding or decoding. c It may also be called expansion factor, lifting factor, expansion value, expansion coefficient, or lifting size, etc.

[0119] For example, the basis matrix H of the QC-LDPC code b As shown below:

[0120] It can be seen that the basis matrix H b The size of the matrix is ​​4 rows and 24 columns, and the basis matrix H b Each element in represents a Z c square matrix of order, element represents the cyclic permutation matrix, i represents the cyclic shift value, and i is an integer. In addition, the basis matrix H b The "-1" in represents an all-zero matrix, and "0" represents an identity matrix.

[0121] For example, As shown below:

[0122] Optionally, the basis matrix H b In addition to "-1", the zero elements in can also have other representations, such as using "-" or null values ​​to represent an all-zero matrix.

[0123] It should be noted that the above-mentioned base matrix can also be called a base graph (BG), and the base matrix will be used below to describe the embodiments of the present application.

[0124] 3. Non-zero elements and zero elements

[0125] In the check matrix, a zero element indicates that there is no connection between the variable node and the check node, and a non-zero element indicates that there is a connection between the variable node and the check node.

[0126] In the LDPC basis matrix, the zero element represents Z c An all-zero square matrix of order, with non-zero elements representing Z c The identity matrix of order or based on Z c The circulant permutation matrix of the identity matrix of order , where the values ​​of the non-zero elements represent the circulant shift values ​​or offset values ​​(shifting value) relative to the identity matrix.

[0127] This application does not limit the specific representation of zero elements and non-zero elements. For example, in the check matrix H shown in Figure 2, "0" is used to represent zero elements and "1" is used to represent non-zero elements. For another example, as described above, the base matrix H b In the , "-1" is used to represent zero elements, and "non-negative values" are used to represent non-zero elements.

[0128] For the convenience of description, "0" is used below to represent a zero element and "1" is used to represent a non-zero element.

[0129] 4. Column weight and row weight

[0130] For a column of a matrix, the column weight can refer to the number of non-zero elements contained in the column. For a row of a matrix, the row weight can refer to the number of non-zero elements contained in the row. For example, as shown in Figure 2, the column weight of the first column of the check matrix H is 2, and the row weight of the first row is 4. For another example, as described above, the base matrix H b The first column has a column weight of 4 and the first row has a row weight of 20.

[0131] 5. Structure of the check matrix

[0132] FIG4 is a schematic diagram of the structure of a check matrix.

[0133] As shown in Figure 4(a), the check matrix may include a high rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high rate region may include part A and part B as shown in Figure 4(b), where part A corresponds to information bits (or information bits, systematic bits, etc.), and part B is a square matrix corresponding to core check bits (or core check bits). The all-zero region may correspond to part C of Figure 4(b), which is an all-zero matrix. The incremental redundancy region may correspond to part D of Figure 4(b). The raptor-like region may correspond to part E of Figure 4(b), which may be a unit matrix corresponding to the check bits of the low rate extension.

[0134] The parity check matrix of the LDPC code shown in Figure 4 employs a "raptor-like" structure, allowing it to be gradually extended to lower code rates using a high-rate core matrix. In practice, as shown in Figure 4(a), the first X rows and Y columns of the parity check matrix can be truncated. As the code rate decreases, X and Y gradually increase, and the area of ​​the matrix used also gradually expands.

[0135] It should be noted that the check matrix can be represented by the LDPC base matrix, so the structure of the LDPC base matrix is ​​similar to that of the check matrix, which will not be described in detail here.

[0136] 6. Information column and check column

[0137] The columns of the LDPC basis matrix consist of information columns and check columns.

[0138] Information column: corresponds to the information bit (also called information bit, system bit, etc.), which is the column corresponding to part A.

[0139] Parity column: Corresponds to the parity bit (or check digit). It can include a core parity column and an extended parity column. The core parity column corresponds to part B, and the extended parity column corresponds to part C or part E. The extended parity column is also called a raptor-like column. The extended parity column corresponds to the extended node.

[0140] 7. Core rows, core columns, and core matrices

[0141] Core rows: The core rows of the LDPC matrix are the rows corresponding to the core parity bits. In other words, the core rows are the rows corresponding to the high-rate region, or the rows corresponding to Part A, Part B, or Part C.

[0142] Core columns: This includes all information columns and all core check columns. In other words, core columns are the columns corresponding to the high bitrate area, or the columns corresponding to part A + part B.

[0143] Kernel Matrix: This is the matrix region consisting of all core rows and all core columns of the LDPC base matrix. In other words, the core matrix is ​​the high-rate region of the LDPC base matrix, or the portion consisting of Part A and Part B.

[0144] 8. Information transmission process

[0145] Figure 5 is a schematic diagram of the information transmission process. As shown in Figure 5, information is sent by the source, undergoes source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, source recovery and other processing, and arrives at the destination, completing the transmission of information from the source to the destination. Among them, the processing shown in the upper layer of Figure 5 (including source coding, channel coding and modulation, etc.) is performed at the transmitting end device, and the processing shown in the lower layer (including demodulation, channel decoding, source recovery, etc.) is performed at the receiving end device. The embodiments of the present application mainly relate to source coding, channel coding, channel decoding and source recovery shown in Figure 5.

[0146] 9. Traditional expansion and split expansion

[0147] Traditional expansion: also known as normal expansion, refers to a low-code rate expansion method based on the traditional method. In this method, the rows of the storage matrix are read as the rows of the LDPC basis matrix.

[0148] Split-and-expand: Unlike traditional expansion, this method uses a row of the storage matrix as a new row in the LDPC base matrix. The new row is then used to eliminate the row preceding it. The eliminated and newly added rows are orthogonal, except for the expansion node. Alternatively, the eliminated row is split into the newly added row and the eliminated row. The eliminated row can correspond to the parent node, and the newly added row, or the eliminated row, can correspond to the child node.

[0149] Figure 6 is an example of traditional expansion and split expansion.

[0150] FIG6 takes the splitting and expansion of the second row as an example.

[0151] Figure 6(a) is the matrix before expansion. Figure 6(b) is the matrix after adding a row. The process from Figure 6(a) to Figure 6(b) is a traditional expansion. Figure 6(c) is the matrix after eliminating row 2 using the added row. The process from Figure 6(a) to Figure 6(b) and then to Figure 6(c) is a splitting expansion. The eliminated row and the newly added row are orthogonal, except for the last column.

[0152] In current LDPC codes, the orthogonality between rows of the LDPC base matrix is ​​low, affecting decoding efficiency and performance. For example, the high-rate portion of an NR LDPC code has a high edge density, supporting only parallel decoding of QC blocks. For another example, in the split-and-extended LDPC code shown in Figure 6, the eliminated rows and the newly added rows are orthogonal except for the extended nodes. However, there are overlapping elements at the extended nodes, requiring staggered decoding or changes in message passing methods to achieve parallel decoding between rows, which affects decoding efficiency and performance.

[0153] In response to the above problems, the present application provides a communication method and a communication device based on LDPC codes, in order to improve decoding efficiency and performance.

[0154] The following describes the method embodiments of the present application.

[0155] FIG7 is a schematic flowchart of a communication method 700 based on LDPC codes provided in this application.

[0156] Method 700 can be performed by a transmitting device and a receiving device. Unless otherwise specified, "transmitting device" or "receiving device" can refer to the transmitting device or receiving device itself, or can refer to a device that supports the transmitting device or receiving device to implement the function. For convenience of description, the following description uniformly uses the transmitting device and receiving device. The transmitting device can be a terminal device or a network device, and the receiving device can be a terminal device or a network device.

[0157] Method 700 may include at least part of the following.

[0158] Step 701: The transmitting device obtains an information bit sequence.

[0159] That is, if the transmitting device needs to communicate with the receiving device, that is, the transmitting device needs to send a signal to the receiving device, the transmitting device needs to first obtain the information bit sequence corresponding to the signal to be sent to the receiving device.

[0160] The transmitting end device obtaining the information bit sequence may refer to: the transmitting end device performing source coding on source symbols to generate the information bit sequence. The transmitting end device obtaining the information bit sequence may also refer to: the transmitting end device receiving the information bit sequence from other communication devices.

[0161] In step 702, the transmitting end device performs LDPC encoding on the information bit sequence according to the first LDPC base matrix and the indication information to obtain an LDPC codeword sequence.

[0162] The first LDPC base matrix may refer to a matrix stored in the transmitting device or a matrix predefined by a protocol. The indication information may indicate the correlation between rows in the first LDPC base matrix.

[0163] The transmitting end device can determine the second LDPC base matrix based on the first LDPC base matrix and the indication information, and use the second LDPC base matrix to perform LDPC encoding on the information bit sequence to obtain an LDPC codeword sequence. The second LDPC base matrix is ​​the matrix actually used by the transmitting end for encoding. In the process of obtaining the second LDPC base matrix, the low code rate expansion method can be a split expansion method, or a mixed method of split expansion and traditional expansion. In the low code rate expansion process, whether each expansion is a traditional expansion or a split expansion can be determined by the indication information. The description of split expansion and traditional expansion can be referred to above and will not be described in detail here.

[0164] In one possible implementation, the indication information may include first information corresponding to splitting and spreading. Optionally, the indication information may also include second information corresponding to traditional spreading. When the indication information does not include the first information, the low-rate spreading method used in the process of obtaining the second LDPC base matrix is ​​splitting and spreading. When the indication information includes both the first information and the second information, the low-rate spreading method used in the process of obtaining the second LDPC base matrix is ​​a hybrid of splitting and spreading and traditional spreading.

[0165] The first information and the second information are described below.

[0166] The first information indicates multiple row pairs, each of which includes a first row and a second row. The set consisting of the column numbers of the columns containing the non-zero elements in the first x elements of the first row of a row pair is a proper subset of the set consisting of the column numbers of the columns containing the non-zero elements in the first x elements of the second row of the row pair, where x is a positive integer. Exemplarily, x is equal to the number of core columns of the first LDPC basis matrix. That is, in a row pair, within the core column portion, the set consisting of the column numbers of the columns containing the non-zero elements in the first row is a proper subset of the set consisting of the column numbers of the columns containing the non-zero elements in the second row. The set consisting of the column numbers of the columns containing the non-zero elements in the first row is a proper subset of the set consisting of the column numbers of the columns containing the non-zero elements in the second row. Alternatively, this can be described as follows: connections, edges, or non-zero elements in the first row, excluding extended nodes, are truly contained in connections, edges, or non-zero elements in the second row, excluding extended nodes. The offset value of the non-zero elements in the first row can be the same as the offset value of the corresponding non-zero elements in the second row, or can differ by a fixed value, without limitation.

[0167] For example, in a row pair, the first row is {1, 0, 0, 3, 0, 5, 0, 0, 1, 0}, and the second row is {1, 0, 2, 3, 4, 5, 0, 1, 0, 0}, where the first seven columns are core columns and the last three columns correspond to expansion nodes. 0 represents a zero element. In the first seven columns, the set composed of the column numbers of the columns where the non-zero elements of the first row are located is {1, 4, 6}, and the set composed of the column numbers of the columns where the non-zero elements of the second row are located is {1, 3, 4, 5, 6}. {1, 4, 6} is a proper subset of {1, 3, 4, 5, 6}, which can also be described as {1, 0, 0, 3, 0, 5, 0} is truly contained in {1, 0, 2, 3, 4, 5, 0}.

[0168] The embodiments of the present application do not limit the storage method of the first row and the second row in a row pair. In one possible implementation, each row pair in the multiple row pairs corresponds to two rows in the first LDPC base matrix or two rows in the first LDPC base matrix, that is, the second row can correspond to a row in the first LDPC base matrix or a row in the first LDPC base matrix, and the first row can correspond to a row in the first LDPC base matrix or a row in the first LDPC base matrix. In this case, each row pair in the multiple row pairs is two rows in the same base matrix. In another possible implementation, the second row can correspond to a row in the first LDPC base matrix or a row in the first LDPC base matrix, and the first row can correspond to a row in a matrix other than the first LDPC base matrix or a row in a matrix other than the first LDPC base matrix, that is, the first row and the second row in each row pair in the multiple row pairs are stored in different base matrices respectively. The following describes the embodiments of the present application by taking each row pair in the multiple row pairs as an example corresponding to two rows in the first LDPC base matrix or two rows in the first LDPC base matrix.

[0169] In the process of obtaining the second LDPC base matrix, for the first and second rows in a row pair, the row of the second LDPC base matrix corresponding to the first row is identical to the first row. In other words, the row of the second LDPC base matrix corresponding to the first row of the first LDPC base matrix is ​​obtained by directly reading the first row of the first LDPC base matrix. The row of the second LDPC base matrix corresponding to the second row is obtained by eliminating the corresponding second row using the first row of the first LDPC base matrix. In this way, the row of the second LDPC base matrix corresponding to the first row and the corresponding row corresponding to the second row are orthogonal except for the expanded node. It should be noted that the row of the second LDPC base matrix corresponding to the first row is identical to the first row. This should be understood as follows: when the row of the second LDPC base matrix corresponding to the first row is initially obtained, the row of the second LDPC base matrix corresponding to the first row is identical to the first row. If the row of the second LDPC base matrix corresponding to the first row is subsequently split and expanded as a parent node, the row is no longer identical to the first row of the first LDPC base matrix.

[0170] The second information is used to indicate one or more third rows. One or more third rows are rows used for traditional expansion. In the process of obtaining the second LDPC base matrix, the rows of the second LDPC base matrix corresponding to the one or more third rows are the same as the one or more third rows of the first LDPC base matrix. In other words, the rows of the second LDPC base matrix corresponding to the third row of the first LDPC base matrix are obtained by directly reading the third row of the first LDPC base matrix. Similarly, the rows of the second LDPC base matrix corresponding to the third row are the same as the third row of the first LDPC base matrix. It should be understood that when the rows corresponding to the third row of the second LDPC base matrix are initially obtained, the rows corresponding to the third row of the second LDPC base matrix are the same as the third row of the first LDPC base matrix. If there is a situation in which the rows corresponding to the third row of the second LDPC base matrix are split and expanded as the parent node, the rows are no longer the same as the third row of the first LDPC base matrix.

[0171] The embodiments of the present application do not limit the specific form of the indication information. For example, the form adopted by the indication information may include: at least one of a sequence, a mapping table, or a mapping pair.

[0172] The following takes the case where the indication information is in the form of a sequence as an example to illustrate the indication information in two cases: including the second information and not including the second information.

[0173] Case 1: The indication information does not include the second information

[0174] The indication information does not include the second information, that is, the second LDPC base matrix is ​​obtained by splitting and expanding. In this case, the sequence corresponding to the indication information can be called a split sequence (split sequence), and the split sequence can be composed of the row number of the core row and the row number of the second row of each row pair in the one or more row pairs mentioned above. The length of the split sequence is equal to the number of rows of the second LDPC base matrix. In a row pair, the position of the row number of the second row in the split sequence is the row number of the first row, and the position of the row number of the second row in the split sequence is greater than the row number of the first row. For example, if the value of the 8th position of the split sequence is 3, it means that the row pair is the 8th row and the 3rd row, and the 8th row corresponds to the first row and the 3rd row corresponds to the second row. During the split expansion, the transmitting device uses the 8th row to eliminate the 3rd row.

[0175] In a possible implementation, the sequence corresponding to the first information may include one or more segments, and the row number in the t-th segment of the one or more segments is {1, 2, ..., 2 t-1 M-1,2 t-1 M}, where t and M are positive integers. Each of the one or more segments corresponds to a round of splitting. For example, the splitting sequence can be {1, 2, 3, 4, 3, 4, 1, 2, 5, 2, 6, 8, 4, 7, 1, 3}, where M is 4, and the sequence corresponding to the first information is from the fifth element, that is, the sequence corresponding to the first information is {3, 4, 1, 2, 5, 2, 6, 8, 4, 7, 1, 3}, where t is 2, {3, 4, 1, 2} is the first segment, {5, 2, 6, 8, 4, 7, 1, 3} is the second segment, and the first segment {3, 4, 1, 2} is {1, 2, ..., 2 1-1 ×4-1,2 1-1 ×4}={1,2,3,4}, the second segment {5,2,6,8,4,7,1,3} is {1,2,…,,2 2-1 ×4-1,2 2-1 ×4}=a permutation of {1, 2, 3, 4, 5, 6, 7, 8}.

[0176] For example, M is the number of core rows of the first LDPC basis matrix. In other words, the core rows of the first LDPC basis matrix can be split. This is because the edge density of the core region is relatively dense, and the corresponding core check equation is usually not orthogonal. Splitting and expansion can be used to increase the orthogonality of the core region of the second LDPC basis matrix. In this case, the specific characteristics of the splitting sequence can be as follows:

[0177] 1) If row i is generated by splitting row j, then j = f(i), row j is called the parent node of row i, and row i is the child node of row j;

[0178] 2) If there exists a row i=i0,i1,i2,…,i l =j, so that i k =f(i k-1 ), holds true for k=1,…,l, then i~j,l are called positive integers;

[0179] 3) For the i-th element in the split sequence, define the set S i ={j≤i|i~j};

[0180] 4) Let the core row set of the core matrix be C0, then row i∈S j , where row j∈C0;

[0181] 5) Each round of splitting is a complete split, that is, C0 and all the current child nodes are split.

[0182] Each round of splitting is a complete splitting, which means that the splitting sequence includes one or more segments, each segment corresponds to a round of splitting, and the row number in the segment corresponding to the t-th round of splitting is {1,…,2 t-1 |C0|}, t is a positive integer, |C0| is the number of elements in set C0, that is, the number of core rows, which can correspond to M above.

[0183] In the above method, each row number appears only once in a round of splitting, so multiple splits included in each round can be executed in parallel, which helps to improve splitting efficiency.

[0184] Case 2: The indication information includes the first information and the second information

[0185] The indication information includes first information and second information, that is, the second LDPC base matrix is ​​obtained by a mixture of split expansion and traditional expansion. In this case, the indication information may also include third information, and the third information is used to indicate one or more fourth rows. The one or more fourth rows of the second LDPC base matrix are the same as the one or more fourth rows of the first LDPC base matrix. Similarly, the row corresponding to the fourth row of the second LDPC base matrix is ​​the same as the fourth row of the first LDPC base matrix. It should be understood that when the row corresponding to the fourth row of the second LDPC base matrix is ​​initially obtained, the row corresponding to the fourth row of the second LDPC base matrix is ​​the same as the fourth row of the first LDPC base matrix. If there is a situation in which the row corresponding to the fourth row of the second LDPC base matrix is ​​split and expanded as the parent node, the row is no longer the same as the fourth row of the first LDPC base matrix.

[0186] In this case, the length of the sequence corresponding to the indication information is equal to the number of rows of the second LDPC base matrix. Hereinafter, the sequence corresponding to the indication information is referred to as the indication sequence.

[0187] The first information may include the row number of the second row of each of the one or more row pairs described above. In a row pair, the row number of the second row is located at the same position as the row number of the first row in the indicator sequence, and the row number of the second row is located at a higher position in the indicator sequence than the row number of the first row. For example, the value of the eighth position in the indicator sequence is 3, which indicates that the row pair is the eighth row and the third row, and the eighth row corresponds to the first row and the third row corresponds to the second row. During the split expansion, the transmitting device uses the eighth row to eliminate the third row.

[0188] The second information includes one or more first characters. The position of the one or more first characters in the indicator sequence corresponds to the row number of one or more third rows. For example, the 7th position of the indicator sequence is the first character, which means that based on the traditional expansion, the row of the second LDPC base matrix corresponds to the 7th row of the first LDPC base matrix, that is, the row of the second LDPC base matrix corresponding to the 7th row of the first LDPC base matrix is ​​the same as the 7th row of the first LDPC base matrix.

[0189] Exemplarily, the first character is a value other than a row number of the first LDPC base matrix.

[0190] The third information includes M second characters or M row numbers, where the M row numbers are 1, 2, ..., M, respectively, and M is a positive integer. For example, M is the number of core rows of the first LDPC base matrix. The positions of the M second characters in the indicator sequence correspond to the row numbers of one or more fourth rows. For example, the second position of the indicator sequence is the second character, which indicates that the row of the second LDPC base matrix corresponding to the second row of the first LDPC base matrix is ​​the same as the second row of the first LDPC base matrix.

[0191] Exemplarily, the second character is a value other than the row number of the first LDPC basis matrix. The second character may be the same as or different from the first character, without limitation.

[0192] In one possible implementation, the indication sequence may have a segmented structure. As an example, the indication sequence may sequentially include a first segment, a second segment, a third segment, a fourth segment, and a fifth segment, wherein the first segment consists of the third information, the second segment consists of the first part of the second information, the third segment consists of the first part of the first information, the fourth segment consists of the second part of the first information and the second part of the second information, and the fifth segment consists of the third part of the second information. As another example, the indication sequence may sequentially include a first segment, a second segment, a third segment, and a fourth segment, wherein the first segment consists of the third information, the second segment consists of the first part of the second information, the third segment consists of the first part of the first information, and the fourth segment consists of the second part of the first information and the second part of the second information.

[0193] Optionally, the third segment included in the indication sequence may include one or more sub - segments, and the line number in the r - th segment of the one or more sub - segments is {1, 2, …, 2 r-1 (M + T)-1, 2 r-1 (M + T)}, in permuted form, where r is a positive integer and T is the number of characters in the first part of the second information. For a detailed description, reference may be made to the sequence corresponding to the first information.

[0194] Taking the indication sequence including the first segment, the second segment, the third segment, the fourth segment, and the fifth segment in sequence as an example, the generalized form of the indication sequence is given below.

[0195] Denote the first character as 0, the number of core rows of the core matrix as M, and the indication sequence θ can be expressed as:

[0196] It can be seen that the indication sequence is a five - segment piece - wise function. Among them, the first segment 1, …, M is the core segment, corresponding to the core matrix (or core check equation) of the first LDPC base matrix; the second segment 0 1×T is the traditional extension segment, corresponding to the traditional extension (or traditional extension check equation), and the second segment consists entirely of the first character 0; the third segment p1(1, …, M + T), p2(1, …, 2M + 2T)… is the split extension segment, corresponding to the split extension, and consists entirely of line numbers (this segment will definitely contain the line numbers of the core matrix); the fourth segment γ(0, p x ) is a mixed segment of split extension and traditional extension. The fourth segment represents the interleaving of the first character 0 and the line numbers that have appeared before; the fifth segment also corresponds to the traditional extension, and the fifth segment consists entirely of the first character 0. Among them, T is the length of the second segment, that is, the number of characters. T’ is the length of the fifth segment, that is, the number of characters.

[0197] In a possible implementation, each segment of the indication sequence can be based on the code rate or the line number. Exemplarily, if the indication sequence includes the first segment, the second segment, the third segment, the fourth segment, and the fifth segment, there exists a sequence position j i , such that for 1 ≤ j < j1, it corresponds to the first segment, j1 ≤ j < j2 corresponds to the second segment, …, until the last segment is j4 ≤ j.

[0198] In a possible implementation, j i is related to the code rate corresponding to the sequence (the number of rows of the check equation), that is, there exists a threshold R for the code rate i , such that is the segmentation position described above, where P is the number of punctured columns and K is the number of information columns.

[0199] The above describes the low-bitrate expansion implemented in this application, combined with the indication information. As can be seen, during the split expansion process, the eliminated rows and the newly added rows are only partially orthogonal, and there are still overlapping elements in the expanded nodes. To further improve the orthogonality between rows, the implementation of this application can design associations between subnodes, which is described in detail below.

[0200] As explained above, the first information can be used to indicate one or more row pairs. In a row pair, the set consisting of the column numbers of the columns where the non-zero elements in the first x elements of the first row are located is a proper subset of the set consisting of the column numbers of the columns where the non-zero elements in the first x elements of the second row are located, where x is a positive integer.

[0201] Furthermore, in an embodiment of the present application, the multiple first rows indicated by the first information may form one or more row groups. Each row group in the one or more row groups includes at least two first rows, and the column weight of each column of the matrix region, subgraph, or matrix formed by the second rows corresponding to the at least two first rows is less than or equal to 2, and at least two first rows are associated with each other.

[0202] For example, the row pairs indicated by the first information include {6, 1)(7, 4)(8, 3)(9, 2)(10, 5)}, and the first row indicated by the first information includes rows 6, 7, 8, 9 and 10, wherein rows 6, 7 and 8 are a row group, and rows 9 and 10 are a row group. The column weight of each column of the matrix area, subgraph or matrix composed of rows 1, 4 and 3 corresponding to rows 6, 7 and 8 is less than or equal to 2, and there is an association relationship between rows 6, 7 and 8. The column weight of each column of the matrix area, subgraph or matrix composed of rows 2 and 5 corresponding to rows 9 and 10 is less than or equal to 2, and there is an association relationship between rows 9 and 10.

[0203] The above-mentioned association relationship may include a first association relationship and / or a second association relationship. The first association relationship and the second association relationship are the relationship between the two first rows. The two first rows with the first association relationship are orthogonal to each other, and the union of the column numbers of the columns where the non-zero elements of the two first rows are located contains the intersection of the column numbers of the columns where the non-zero elements of the two second rows corresponding to the two first rows are located. The two first rows with the first association relationship mentioned here can be any two first rows with the first association relationship in a row group. The two first rows with the second association relationship have the same connecting edge at the first position, and the column number at the first position belongs to the intersection of the column numbers of the columns where the non-zero elements of the two second rows corresponding to the two first rows are located. The two first rows with the second association relationship mentioned here can be any two first rows with the second association relationship in a row group.

[0204] FIG8 is a schematic diagram of the first association relationship.

[0205] The first and second rows in Figure 8 correspond to the second row, the column weight of each column of the matrix area (or matrix or subgraph) formed by the first and second rows is no more than 2, the third and fourth rows correspond to the first row, and the first and third rows are a row pair, the second and fourth rows are a row pair, and the tenth and eleventh columns of each row correspond to the expansion nodes.

[0206] As shown in FIG8( a ), the third row and the fourth row are orthogonal to each other, that is, the column weight of each column of the matrix region formed by the third row and the fourth row is less than or equal to 1.

[0207] As shown in Figure 8(b), the set of column numbers of the columns where the non-zero elements in the first row excluding the expanded nodes are located is {1, 2, 3, 4, 5, 6}, and the set of column numbers of the columns where the non-zero elements in the third row excluding the expanded nodes are located is {2, 4, 6}. {1, 2, 3, 4, 5, 6} truly contains {2, 4, 6}, or in other words, {2, 4, 6} is a true subset of {1, 2, 3, 4, 5, 6}.

[0208] As shown in Figure 8(c), the set of column numbers of the columns where the non-zero elements of the second row excluding the expanded nodes are located is {4, 5, 6, 7, 8, 9}, and the set of column numbers of the columns where the non-zero elements of the fourth row excluding the expanded nodes are located is {5, 7}. {4, 5, 6, 7, 8, 9} truly contains {5, 7}, or in other words, {5, 7} is a true subset of {4, 5, 6, 7, 8, 9}.

[0209] As shown in Figure 8(d), the intersection of the set {1, 2, 3, 4, 5, 6} of the column numbers of the columns where the non-zero elements in the first row are located and the set {4, 5, 6, 7, 8, 9} of the column numbers of the columns where the non-zero elements in the second row are located is {4, 5, 6}, and the union of the set {2, 4, 6, 10} of the column numbers of the columns where the non-zero elements in the third row are located and the set {5, 7, 11} of the column numbers of the columns where the non-zero elements in the fourth row are located is {2, 4, 5, 6, 7, 10, 11}. {2, 4, 5, 6, 7, 10, 11} contains {4, 5, 6}. In this way, the third row and the fourth row have a first association relationship.

[0210] FIG9 is a schematic diagram of the second association relationship.

[0211] The first and second rows in Figure 9 correspond to the second row, the column weight of each column of the matrix area (or matrix or subgraph) formed by the first and second rows is not greater than 2, the third and fourth rows correspond to the first row, and the first and third rows are a row pair, the second and fourth rows are a row pair, and the tenth and eleventh columns of each row correspond to the expansion nodes.

[0212] As shown in Figure 9(b), the set of column numbers of the columns where the non-zero elements in the first row excluding the expanded nodes are located is {1, 2, 3, 4, 5, 6}, and the set of column numbers of the columns where the non-zero elements in the third row excluding the expanded nodes are located is {2, 4, 6}. {1, 2, 3, 4, 5, 6} truly contains {2, 4, 6}, or in other words, {2, 4, 6} is a true subset of {1, 2, 3, 4, 5, 6}.

[0213] As shown in Figure 9(c), the set of column numbers of the columns where the non-zero elements in the second row excluding the expanded nodes are located is {4, 5, 6, 7, 8, 9}, and the set of column numbers of the columns where the non-zero elements in the fourth row excluding the expanded nodes are located is {5, 7}. {4, 5, 6, 7, 8, 9} truly contains {5, 7}, or in other words, {5, 7} is a true subset of {4, 5, 6, 7, 8, 9}.

[0214] As shown in Figure 9(d), the intersection of the set {1, 2, 3, 4, 5, 6} of the column numbers of the columns where the non-zero elements in the first row are located and the set {4, 5, 6, 7, 8, 9} of the column numbers of the columns where the non-zero elements in the second row are located is {4, 5, 6}, that is, the first position is the 4th column, the 5th column and the 6th column, the 4th column, the 5th column and the 6th column of the 3rd row are the same as the 4th column, the 5th column and the 6th column of the 4th row, so that the 3rd row and the 4th row have a second association relationship.

[0215] The generalized forms of the first association relationship and the second association relationship are given below in conjunction with the sequence θ corresponding to the indication information.

[0216] Suppose for i ≥ 1, if θ(i) > 0, then there exists j ≥ 1, satisfying the condition θ(j) > 0, θ(i) ≠ θ(j), where i and j represent the row numbers of the child nodes, and θ(i) and θ(j) represent the row numbers of the parent node.

[0217] For the first relationship: and

[0218] For the second association relationship: [N(θ(j))∩N(θ(i))]∩N(i)=[N(θ(j))∩N(θ(i))]∩N(j). [N(θ(j))∩N(θ(i))]∩N(i)=[N(θ(j))∩N(θ(i))]∩N(j) can be simplified to N(θ(j))∩N(i)=N(θ(i))∩N(j).

[0219] Among them, N(i) represents the set consisting of the column numbers of the columns where the non-zero elements of the row with row number i are located, N(j) represents the set consisting of the column numbers of the columns where the non-zero elements of the row with row number j are located, N(θ(i)) represents the set consisting of the column numbers of the columns where the non-zero elements of the row with row number θ(i) are located, and N(θ(j)) represents the set consisting of the column numbers of the columns where the non-zero elements of the row with row number θ(j) are located.

[0220] The above describes the concepts of parent nodes and child nodes based on the sequence θ. In this description, θ(i) and θ(j) are parent nodes grouped together, and their relevance is reflected in their child nodes i and j. Alternatively, we can describe this from the perspective of parent node grouping: nodes whose child nodes have the first or second relevance are grouped together.

[0221] In an embodiment of the present application, in a row group consisting of at least two first rows, the first rows in the row group can be combined in pairs, wherein each combination can have the first association relationship, or each combination can have the second association relationship, or some combinations can have the first association relationship and some combinations can have the second association relationship, without limitation.

[0222] In a possible implementation, in the pairwise combinations of the first rows of a row group, the number of combinations having the first association relationship and the number of combinations having the second association relationship are related to the number of first rows included in the row group.

[0223] As an example, for a row group including k first rows, the number of combinations with the first association relationship and the number of combinations with the second association relationship are distributed in a total of In this case, in the combination of the first two rows in the row group, The combination has a first association relationship, The combination has a second relationship, represents the number of combinations of selecting two rows from ki rows, represents the number of combinations of any two rows from k rows, It represents the number of combinations of selecting two rows from i rows. Specifically, the number of combinations with the first association relationship and the number of combinations with the second association relationship may be allocated in the following manner: combinations have the first relationship and 0 combinations have the second relationship, The combination has a first association relationship, The combination has a second relationship, The combination has a first association relationship, The combinations have the second relationship, ..., The combination has a first association relationship, The combinations have a second association relationship.

[0224] For example, when k=2, the number of combinations with the first association relationship and the number of combinations with the second association relationship are distributed in a total of In this case, either the two first rows have the first association relationship, or the two rows have the second association relationship.

[0225] For another example, when k=3, the number of combinations with the first association relationship and the number of combinations with the second association relationship are distributed in a total of Situations including The combination has a first association relationship and The combinations have a second association, and The combination has a first association relationship and The combinations have a second association relationship.

[0226] As another example, for a row group including k first rows, the number of combinations with the first association relationship and the number of combinations with the second association relationship are distributed in a total of In this case, in the combination of the first two rows in the row group, The combination has a first association relationship, The combination has a second association relationship, represents the number of combinations of selecting two rows from ki rows, represents the number of combinations of any two rows from k rows, It represents the number of combinations of selecting two rows from i rows. Indicates rounding up.

[0227] In this way, for each row group in the above-mentioned one or more row groups, since the first row in the row group has the above-mentioned first association relationship and / or second association relationship, after splitting and expansion, the rows corresponding to the first row in a row group in the second LDPC base matrix and the rows corresponding to the second row in the second LDPC base matrix corresponding to the first row in the row group are re-divided and grouped, so that complete orthogonality between rows in the same group can be achieved.

[0228] In step 703, the transmitting device sends the LDPC codeword sequence to the receiving device, or in other words, the receiving device receives the LDPC codeword sequence from the transmitting device.

[0229] It should be noted that since the LDPC codeword sequence may introduce channel noise signals during the transmission process, the LDPC codeword sequence output or sent by the transmitting device may be different from the LDPC codeword sequence received by the receiving device.

[0230] Step 704: The receiving end device decodes the LDPC codeword sequence according to the first LDPC base matrix and the indication information.

[0231] The first LDCP base matrix and indication information used by the receiving device for decoding are the same as the first LDCP base matrix and indication information used by the transmitting device for encoding. Please refer to the description on the transmitting device side and will not be described in detail here.

[0232] In one possible implementation, the receiving device can obtain a second LDPC base matrix based on the first LDPC base matrix and the indication information, and decode the LDPC codeword sequence based on the second LDPC base matrix, wherein the row corresponding to the first row of the second LDPC base matrix is ​​obtained by eliminating the second row in the same row pair by the first row.

[0233] It should be noted that the decoding matrix actually used by the receiving device and the encoding matrix actually used by the transmitting device can be the same or different. For example, the transmitting device can only read the corresponding rows from the first LDPC base matrix according to the indication information without splitting and expanding. The receiving device can read the corresponding rows from the first LDPC base matrix according to the indication information and split and expand to obtain the second LDPC base matrix. In this case, the LDPC base matrices used by the transmitting device and the receiving device are different. For another example, the transmitting device obtains the second LDPC base matrix based on the first LDPC base matrix and the indication information and uses the second LDPC base matrix for encoding. The receiving device also obtains the second LDPC base matrix in the same way and uses the second LDPC base matrix for decoding. In this case, the decoding matrix actually used by the receiving device is the same as the encoding matrix actually used by the transmitting device.

[0234] It should be noted that, for each of the one or more row groups mentioned above, the receiving device can perform row-parallel decoding on the rows in the second LDPC base matrix corresponding to the first row in a row group and the rows in the second LDPC base matrix corresponding to the second row in the row group that are divided into the same group.

[0235] In one possible implementation, the receiving device may perform row-parallel decoding on the portion of the codeword sequence corresponding to rows in the first row set, and row-parallel decoding on the portion of the codeword sequence corresponding to rows in the second row set. The union of the first row set and the second row set includes rows in the second LDPC base matrix corresponding to the first row in a row group, and rows in the second LDPC base matrix corresponding to the second row corresponding to the first row in the row group. The first row set consists of rows in the second LDPC base matrix corresponding to rows in the first subset and / or rows in the second LDPC base matrix corresponding to rows in the second subset. The rows in the first subset are all first rows, and each pair of first rows in the first subset has a first association relationship. The rows in the second subset are all second rows, and the first row corresponding to the second row in the second subset has a second association relationship with the first row in the first subset. The second row set consists of rows in the second LDPC base matrix corresponding to rows in the third subset and / or rows in the second LDPC base matrix corresponding to rows in the fourth subset. The third subset consists of the second rows corresponding to the first rows in the first subset, the fourth subset consists of the first rows corresponding to the second rows in the second subset, and the first rows in the fourth subset have a first association relationship with each other.

[0236] For example, a row group includes row C and row D, the second row corresponding to row C is row A, and the second row corresponding to row D is row B. Row C and row D have a first association relationship. Row A and row B can be divided into one group, and row C and row D can be divided into one group. In this case, the first subset includes row C and row D, the second subset is an empty set (that is, the first row set does not include the second subset), the third subset includes row A and row B, and the fourth subset is an empty set (that is, the second row set does not include the fourth subset). The receiving device can perform row-parallel decoding on the part of the LDPC codeword sequence corresponding to the rows corresponding to row A and row B in the second LDPC base matrix, and perform row-parallel decoding on the part of the LDPC codeword sequence corresponding to the rows corresponding to row C and row D in the second LDPC base matrix.

[0237] For example, a row group includes row C and row D, the second row corresponding to row C is row A, and the second row corresponding to row D is row B. Row C and row D have a second association relationship. Row A and row C can be divided into a group, and row B and row D can be divided into a group. In this case, the first subset includes row C, the second subset is row A, the third subset includes row D, and the fourth subset includes row B. The receiving device can perform row-parallel decoding on the part of the LDPC codeword sequence corresponding to the rows corresponding to row A and row C in the second LDPC base matrix, and perform row-parallel decoding on the part of the LDPC codeword sequence corresponding to the rows corresponding to row B and row D in the second LDPC base matrix.

[0238] For example, a row group includes row D, row E, and row F, the second row corresponding to row D is row A, the row corresponding to row E is row B, and the row corresponding to row F is row C. Row D and row F have a first association relationship, row D and row E have a second association relationship, and row E and row F have a second association relationship. Row D, row F, and row B can be divided into a group, and row A, row C, and row E can be divided into a group. In this case, the first subset includes row D and row F, the second subset includes row B, the third subset includes row A and row C, and the fourth subset includes row E. The receiving device can perform row-parallel decoding on the part of the LDPC codeword sequence corresponding to the rows corresponding to row D, row F, and row B in the second LDPC base matrix, and perform row-parallel decoding on the part of the LDPC codeword sequence corresponding to the rows corresponding to row A, row C, and row E in the second LDPC base matrix.

[0239] It should be noted that the groups involved in the above-mentioned row-parallel decoding may be stored in the receiving device or may be predefined, without limitation.

[0240] The technical solutions of the embodiments of the present application are described in detail below with reference to several specific examples.

[0241] Example 1

[0242] Fig. 10 is an example of a technical solution of an embodiment of the present application. In this example, k=2.

[0243] As shown in FIG10 , the child node of node 1 is node 3 , and the child node of node 2 is node 4 .

[0244] If there is no correlation between node 3 and node 4, then node 1 and node 3 can only be divided into one group, and node 2 and node 4 can only be divided into one group. Both groups are quasi-orthogonal, that is, the expanded node part still has overlapping elements.

[0245] If a first association relationship is introduced between nodes 3 and 4, that is, node 3 includes an extended node, and in addition to the extended node, the edges or non-zero elements contained in node 3 are a proper subset of node 1, and node 4 includes an extended node, in addition to the extended node, the edges or non-zero elements contained in node 4 are a proper subset of node 2, nodes 3 and 4 are mutually orthogonal, and the union of the non-zero elements of nodes 3 and 4 contains the intersection of the non-zero elements of nodes 1 and 2, then a new grouping method can be generated, such as dividing nodes 1 and 2 into one group, and dividing nodes 3 and 4 into another group, so that the two resulting groups are completely orthogonal. For details of the first association relationship, please refer to Figure 8.

[0246] In this example, multiple parent nodes (e.g., node 1 and node 2) are grouped together, and multiple child nodes (e.g., node 3 and node 4) are grouped together. The child nodes of the parent nodes in the same group have a first association relationship with each other. The transmitting device can perform row-parallel decoding on the multiple parent nodes (e.g., node 1 and node 2) and row-parallel decoding on the multiple child nodes (e.g., node 3 and node 4).

[0247] Example 2

[0248] Fig. 11 is another example of the technical solution of the embodiment of the present application. In this example, k=2.

[0249] As shown in FIG11 , the child node of node 1 is node 3, and the child node of node 2 is node 4.

[0250] If there is no correlation between node 3 and node 4, then node 1 and node 3 can only be divided into one group, and node 2 and node 4 can only be divided into one group. Both groups are quasi-orthogonal, that is, the expanded node part still has overlapping elements.

[0251] If a second association relationship is introduced between nodes 3 and 4, that is, node 3 includes an extended node, and in addition to the extended node, the edges or non-zero elements contained in node 3 are a proper subset of node 1, and node 4 includes an extended node, in addition to the extended node, the edges or non-zero elements contained in node 4 are a proper subset of node 2, and nodes 3 and 4 have exactly the same edges at the intersection of nodes 1 and 2, then a new grouping method can be generated, such as grouping nodes 1 and 4 into one group, and node 2 and 3 into another group, so that the two resulting groups are completely orthogonal. For details of the second association relationship, please refer to Figure 9.

[0252] In this example, nodes 1 and 4 are grouped together, and nodes 2 and 3 are grouped together. Child nodes of parent nodes in the same group have a first association relationship with each other. The transmitting device can perform row-parallel decoding on nodes 1 and 4, and row-parallel decoding on nodes 2 and 3.

[0253] Fig. 12 is another example of the technical solution of the embodiment of the present application. In this example, k=3.

[0254] As shown in FIG12 , the child node of node 1 is node 4, the child node of node 2 is node 5, and the child node of node 3 is node 6.

[0255] If there is no correlation between nodes 4, 5 and 6, then we can only group node 1 and node 4 into one group, node 2 and node 5 into one group, and node 3 and node 6 into one group. These three groups are quasi-orthogonal, that is, the expanded node part still has overlapping elements.

[0256] If the first association relationship is introduced between nodes 4, 5 and 6, that is, node 4 includes an extended node, the edges or non-zero elements contained in node 4 except the extended node are a true subset of node 1, node 5 includes an extended node, the edges or non-zero elements contained in node 5 except the extended node are a true subset of node 2, node 6 includes an extended node, the edges or non-zero elements contained in node 6 except the extended node are a true subset of node 3, nodes 4 and 5 are orthogonal to each other, and the union of the non-zero elements of nodes 4 and 5 contains the intersection of the non-zero elements of nodes 1 and 2. Set, nodes 4 and 6 are mutually orthogonal, the union of the non-zero elements of nodes 4 and 6 contains the intersection of the non-zero elements of nodes 1 and 3, nodes 5 and 6 are mutually orthogonal, the union of the non-zero elements of nodes 5 and 6 contains the intersection of the non-zero elements of nodes 2 and 3, and the column weight of each column of the matrix region composed of nodes 1, 2, and 3 is at most 2. Then, a new grouping method can be generated, such as dividing nodes 1, 2, and 3 into one group, and dividing nodes 4, 5, and 6 into another group, so that the two groups obtained are completely orthogonal. For details of the first association relationship, please refer to Figure 8.

[0257] In this example, multiple parent nodes (e.g., node 1, node 2, and node 3) are grouped together, and multiple child nodes (e.g., node 4, node 5, and node 6) are grouped together. The child nodes of the parent nodes in the same group have a first association relationship with each other. The transmitting device can perform row-parallel decoding on the multiple parent nodes (e.g., node 1, node 2, and node 3) and row-parallel decoding on the multiple child nodes (e.g., node 4, node 5, and node 6).

[0258] Fig. 13 is another example of the technical solution of the embodiment of the present application. In this example, k=3.

[0259] As shown in FIG13 , the child node of node 1 is node 4, the child node of node 2 is node 5, and the child node of node 3 is node 6.

[0260] If there is no correlation between nodes 4, 5 and 6, then we can only group node 1 and node 4 into one group, node 2 and node 5 into one group, and node 3 and node 6 into one group. These three groups are quasi-orthogonal, that is, the expanded node part still has overlapping elements.

[0261] If the first association relationship and the second association relationship are introduced between nodes 4, 5 and 6, such as node 4 includes an extended node, the edges or non-zero elements contained in node 4 except the extended node are a true subset of node 1, node 5 includes an extended node, the edges or non-zero elements contained in node 5 except the extended node are a true subset of node 2, node 6 includes an extended node, the edges or non-zero elements contained in node 6 except the extended node are a true subset of node 3, node 4 and node 6 are mutually orthogonal, the union of the non-zero elements of node 4 and node 6 contains the intersection of the non-zero elements of node 1 and node 3, the edges between node 4 and node 5 at the intersection of node 1 and node 2 are exactly the same, the edges between node 5 and node 6 at the intersection of node 2 and node 3 are exactly the same, and the column weight of each column of the matrix area formed by node 1, node 2 and node 3 is at most 2, then a new grouping method can be generated, such as dividing node 1, node 3 and node 5 into one group, and dividing node 2, node 4 and node 6 into one group, so that the two groups obtained are completely orthogonal. For details of the first association relationship, please refer to FIG8 , and for details of the second association relationship, please refer to FIG9 .

[0262] In this example, nodes 1, 3, and 5 are grouped together, and nodes 2, 4, and 6 are grouped together. The transmitting device can perform row-parallel decoding on nodes 1, 3, and 5, and row-parallel decoding on multiple nodes 2, 4, and 6.

[0263] The performance of the LDPC code of the embodiment of the present application is described below in conjunction with simulation results.

[0264] FIG14 is a simulation result 1 of the difference between the SNR of the NR LDPC code and the LDPC code of the present application at different code rates.

[0265] Figure 14 shows the simulation results of the difference in SNR between the NR LDPC code and the LDPC code of this application at a block error rate (BLER) @ 1e-2. The ordinate is the SNR difference between the NR LDPC code and the LDPC code of this application at BLER @ 1e-2, and the abscissa is the code rate. An SNR difference greater than 0 indicates good performance of the LDPC code of this application, and an SNR difference less than 0 indicates good performance of the NR LDPC code. As shown in Figure 14, compared to the BG1 of the NR LDPC code, the LDPC code of this application has a gain in the code rate range of 0.4 and above. At the same time, the row orthogonality of the LDPC code of this application is better than that of the BG1 of the NR LDPC code.

[0266] FIG15 is a second simulation result of the difference between the SNR of the NR LDPC code and the LDPC code of the present application at different code rates.

[0267] Figure 15 shows the simulation results of the SNR difference between the NR LDPC code and the LDPC code of this application at BLER@1e-3. The ordinate represents the SNR difference between the NR LDPC code and the LDPC code of this application at BLER@1e-2, and the abscissa represents the code rate. An SNR difference greater than 0 indicates good performance of the LDPC code of this application, while an SNR difference less than 0 indicates good performance of the NR LDPC code. As shown in Figure 15, compared to BG1 of the NR LDPC code, the LDPC code of this application has a gain in almost all code rate ranges. At the same time, the LDPC code of this application has a BLER-SNR slope gain, with the gain at BLER1e-3 being greater than that at BLER1e-2.

[0268] The above describes in detail the method embodiment provided by the present application in conjunction with Figures 7 to 15 , and the following will describe the device embodiment of the present application in conjunction with Figures 16 to 18 .

[0269] It is understood that, in order to implement the functions in the above embodiments, the apparatuses in Figures 16 to 18 include hardware structures and / or software modules corresponding to the respective functions. It should be readily apparent to those skilled in the art that, in conjunction with the various exemplary units and method steps described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software.

[0270] Figures 16 and 17 are schematic diagrams of possible apparatuses provided in embodiments of the present application. These apparatuses can be used to implement the functions of the transmitting device or the receiving device in the above method embodiments, thereby also achieving the beneficial effects of the above method embodiments.

[0271] As shown in FIG. 16 , the device 10 includes a transceiver unit 11 and a processing unit 12 .

[0272] When apparatus 10 is used to implement the functions of a transmitting device in each of the above method embodiments, transceiver unit 11 is used to execute the transmitting and receiving steps of the transmitting device, such as step 703, and processing unit 12 is used to execute the processing steps of the transmitting device, such as steps 701 to 702. When apparatus 10 is used to implement the functions of a receiving device in each of the above method embodiments, transceiver unit 11 is used to execute the transmitting and receiving steps of the receiving device, such as step 703, and processing unit 12 is used to execute the processing steps of the receiving device, such as step 704.

[0273] For a more detailed description of the transceiver unit 11 and the processing unit 12 , please refer to the relevant description in the above method embodiment, which will not be described again here.

[0274] As shown in FIG17 , apparatus 20 includes processing circuitry 21. Processing circuitry 21 is coupled to memory 23, which is configured to store instructions. When apparatus 20 is used to implement the method described above, processing circuitry 21 is configured to execute instructions stored in memory 23 to implement the functions of processing unit 12 described above.

[0275] Optionally, the device 20 further includes a memory 23 .

[0276] Optionally, the apparatus 20 further includes a transceiver circuit 22. The transceiver circuit can be referred to as a communication interface. The processing circuit 21 and the transceiver circuit 22 are coupled to each other. It will be appreciated that the transceiver circuit 22 can be a transceiver or an input / output interface. When the apparatus 20 is used to implement the method described above, the processing circuit 21 is used to execute instructions to implement the functions of the processing unit 12, and the transceiver circuit 22 is used to implement the functions of the transceiver unit 11.

[0277] Optionally, the apparatus 20 may be a transmitting end device or a receiving end device, and correspondingly, the transceiver circuit may be a transceiver.

[0278] Optionally, the apparatus 20 may be a chip applied to a transmitting end device or a receiving end device, and accordingly, the transceiver circuit may be an input / output interface.

[0279] Exemplarily, when apparatus 20 is a chip applied to a transmitting device or a receiving device, the chip implements the functions of the transmitting device or the receiving device in the above-described method embodiments. The chip receives information from other modules (such as a radio frequency module or an antenna) in the transmitting device or the receiving device, where the information is sent to the transmitting device or the receiving device by other devices; or the chip sends information to other modules (such as a radio frequency module or an antenna) in the transmitting device or the receiving device, where the information is sent to other devices by the transmitting device or the receiving device.

[0280] 18 is a schematic diagram of a chip system 30 provided in an embodiment of the present application. The chip system 30 (or also referred to as a processing system) includes a logic circuit 31 and an input / output interface 32.

[0281] The logic circuit 31 may be a processing circuit in the chip system 30. The logic circuit 31 may be coupled to a storage unit and call instructions in the storage unit so that the chip system 30 can implement the methods and functions of the various embodiments of the present application. The input / output interface 32 may be an input / output circuit in the chip system 30, outputting information processed by the chip system 30 or inputting data or signaling information to be processed into the chip system 30 for processing.

[0282] As a solution, the chip system 30 is used to implement the operations performed by the transmitting end device or the receiving end device in each of the above method embodiments.

[0283] For example, the logic circuit 31 is used to implement the processing-related operations performed by the sending device or the receiving device in the above method embodiment; the input / output interface 32 is used to implement the sending and / or receiving-related operations performed by the sending device or the receiving device in the above method embodiment.

[0284] The present application also provides a communication device, comprising a processing circuit coupled to a memory, the memory being used to store computer programs or instructions and / or data, and the processing circuit being used to execute the computer programs or instructions stored in the memory, or to read data stored in the memory, to perform the methods described in the above method embodiments. Optionally, there are one or more processing circuits. Optionally, the communication device includes a memory. Optionally, there are one or more memories. Optionally, the memory is integrated with the processing circuit or provided separately.

[0285] The present application also provides a chip including a processing circuit coupled to a memory, the memory being configured to store computer programs or instructions, and the processing circuit being configured to execute the computer programs or instructions stored in the memory to implement the methods performed by the transmitting or receiving device in each of the above method embodiments. The memory may be located within the chip or independently of the chip, external to the chip, without limitation herein.

[0286] The present application also provides a computer-readable storage medium storing computer instructions for implementing the methods executed by a transmitting device or a receiving device in the above-mentioned method embodiments.

[0287] The present application also provides a computer program product comprising instructions, which, when executed by a computer, implement the methods performed by a transmitting device or a receiving device in the above-mentioned method embodiments.

[0288] The present application also provides a communication system, which includes at least one of the transmitting end device or the receiving end device in the above embodiments.

[0289] The explanation of the relevant contents and beneficial effects of any of the above-mentioned devices can be referred to the corresponding method embodiments provided above, which will not be repeated here.

[0290] It is understood that the processing circuit in the embodiments of the present application can be a processor or a circuit in a processor for performing processing operations. The processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The general-purpose processor can be a microprocessor or any conventional processor.

[0291] The method steps in the embodiments of the present application can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, and the software modules can be stored in random access memory, flash memory, read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, hard disks, mobile hard disks, compact disc read-only memory (CD-ROM) or any other form of storage medium well known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and storage medium can be located in an ASIC. In addition, the ASIC can be located in a transmitting device or a receiving device. Of course, the processor and storage medium can also be present in a transmitting device or a receiving device as discrete components.

[0292] In the above embodiments, all or part of the embodiments may be implemented using software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are performed in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user device, or other programmable device. The computer program or instructions may be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions may be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; an optical medium, such as a digital video disk; or a semiconductor medium, such as a solid-state drive.

[0293] In the various embodiments of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced by each other. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

[0294] Unless otherwise indicated, all technical and scientific terms used in the embodiments of the present application have the same meaning as those generally understood by those skilled in the art of the technical field of the application. The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the application. It should be understood that the above are for illustration, and the examples above are only for helping those skilled in the art to understand the embodiments of the present application, rather than limiting the application embodiments to the specific numerical values ​​or specific scenarios illustrated. Those skilled in the art can obviously carry out various equivalent modifications or changes based on the examples given above, and such modifications and changes also fall within the scope of the embodiments of the present application.

Claims

1. A communication method based on low-density parity check (LDPC) codes, characterized in that: The method comprises: Obtaining an information bit sequence; According to the first LDPC base matrix and the indication information, the information bit sequence is LDPC encoded to obtain an LDPC codeword sequence; wherein the indication information includes first information, the first information is used to indicate a plurality of row pairs, each row pair in the plurality of row pairs includes a first row and a second row, a set consisting of column numbers of columns where non-zero elements in the first x elements of the first row in the row pair are located is a proper subset of a set consisting of column numbers of columns where non-zero elements in the first x elements of the second row in the row pair are located, and x is a positive integer; the plurality of first rows indicated by the first information form one or more row groups, each row group in the one or more row groups includes at least two first rows, the column weight of each column of a matrix region formed by the second rows corresponding to the at least two first rows is less than or equal to 2, and the at least two first rows are associated with each other; The LDPC codeword sequence is sent.

2. The method according to claim 1, characterized in that The step of performing LDPC encoding on the information bit sequence according to the first LDPC base matrix and the indication information to obtain an LDPC codeword sequence includes: Obtaining a second LDPC base matrix according to the first LDPC base matrix and the indication information; According to the second LDPC base matrix, LDPC encoding is performed on the information bit sequence to obtain an LDPC codeword sequence, wherein the row of the second LDPC base matrix corresponding to the first row is obtained by eliminating the second row in the same row pair by the first row.

3. The method according to claim 1 or 2, characterized in that: The association relationship includes a first association relationship and / or a second association relationship, wherein: The two first rows having the first association relationship are orthogonal to each other, and the union of the column numbers of the columns where the non-zero elements of the two first rows are located includes the intersection of the column numbers of the columns where the non-zero elements of the two second rows corresponding to the two first rows are located; The two first rows having the second association relationship have the same connecting edge at the first position, and the column number at the first position belongs to the intersection of the column numbers of the columns where the non-zero elements of the two second rows corresponding to the two first rows are located.

4. A communication method based on low-density parity check LDPC code, characterized in that: The method comprises: Receive an LDPC codeword sequence; The LDPC codeword sequence is decoded according to a first LDPC base matrix and indication information; wherein the indication information includes first information, the first information is used to indicate a plurality of row pairs, each row pair in the plurality of row pairs includes a first row and a second row, a set consisting of column numbers of columns where non-zero elements among the first x elements of the first row in the row pair are located is a proper subset of a set consisting of column numbers of columns where non-zero elements among the first x elements of the second row in the row pair are located, and x is a positive integer; the plurality of first rows indicated by the first information form one or more row groups, each row group in the one or more row groups includes at least two first rows, a column weight of each column of a matrix region formed by the second rows corresponding to the at least two first rows is less than or equal to 2, and the at least two first rows are associated with each other.

5. The method according to claim 4, characterized in that The step of decoding the LDPC codeword sequence according to the first LDPC base matrix and the indication information includes: Obtaining a second LDPC base matrix according to the first LDPC base matrix and the indication information; The LDPC codeword sequence is decoded according to the second LDPC base matrix, wherein the row of the second LDPC base matrix corresponding to the first row is obtained by eliminating the second row in the same row pair by the first row.

6. The method according to claim 4 or 5, characterized in that: The association relationship includes a first association relationship and / or a second association relationship, wherein: The two first rows having the first association relationship are orthogonal to each other, and the union of the column numbers of the columns where the non-zero elements of the two first rows are located includes the intersection of the column numbers of the columns where the non-zero elements of the two second rows corresponding to the two first rows are located; The two first rows having the second association relationship have the same connecting edge at the first position, and the column number at the first position belongs to the intersection of the column numbers of the columns where the non-zero elements of the two second rows corresponding to the two first rows are located.

7. The method according to claim 6, characterized in that The step of decoding the LDPC codeword sequence according to the second LDPC base matrix includes: Performing row-parallel decoding on the portion of the LDPC codeword sequence corresponding to the rows in the first row set, and decoding the LDPC codeword The portion of the sequence corresponding to the rows in the second set of rows is decoded row-parallel, where: The union of the first row set and the second row set includes rows in the second LDPC base matrix corresponding to the at least two first rows, and rows in the second LDPC base matrix corresponding to the second rows corresponding to the at least two first rows; The first row set is composed of rows in the second LDPC base matrix corresponding to rows in the first subset and / or rows in the second LDPC base matrix corresponding to rows in the second subset, the rows in the first subset are all the first rows and the first rows in the first subset have the first association relationship in pairs, the rows in the second subset are all the second rows and the first row corresponding to the second row in the second subset has the second association relationship with the first row in the first subset; The second row set consists of rows in the second LDPC base matrix corresponding to rows in the third subset and / or rows in the second LDPC base matrix corresponding to rows in the fourth subset, the third subset consists of the second rows corresponding to the first rows in the first subset, the fourth subset consists of the first rows corresponding to the second rows in the second subset, and the first rows in the fourth subset have the first association relationship in pairs.

8. The method according to claim 3, 6 or 7, characterized in that: In any two combinations of the at least two first rows, the number of combinations having the first association relationship and the number of combinations having the second association relationship are related to the number of the first rows included in the at least two first rows.

9. The method according to claim 8, characterized in that In any combination of at least two of the first rows, The combination has the first association relationship, combinations have the second association relationship, wherein k is the number of the first rows included in the at least two first rows, represents the number of combinations of any two rows selected from ki rows, represents the number of combinations of selecting two rows from k rows, represents the number of combinations of any two rows selected from the i rows, Indicates rounding down.

10. The method according to any one of claims 1 to 9, characterized in that Each row pair of the plurality of row pairs corresponds to two rows of the first LDPC base matrix; The indication information is in the form of a sequence, wherein the first information is a sequence consisting of the row number of the second row of each row pair in the one or more row pairs; In one of the row pairs, the row number of the second row is located at the same position as the row number of the first row in the sequence corresponding to the indication information, and the row number of the second row is located at a greater position than the row number of the first row in the sequence corresponding to the indication information.

11. The method according to claim 10, characterized in that The sequence corresponding to the first information includes one or more segments, and the row number in the t-th segment of the one or more segments is {1, 2, ..., 2 t-1 M-1,2 t-1 M}, where t and M are positive integers.

12. The method according to claim 10, characterized in that The indication information further includes second information, where the second information is used to indicate one or more third rows.

13. The method according to claim 12, characterized in that The second information includes one or more first characters, and positions of the one or more first characters in the sequence corresponding to the indication information correspond to row numbers of the one or more third rows.

14. The method according to claim 12 or 13, characterized in that The indication information further includes third information, and the third information is used to indicate one or more fourth rows.

15. The method according to claim 14, characterized in that The third information includes M second characters or M row numbers, and the M row numbers are 1, 2, ..., M-1, M in sequence, where M is a positive integer.

16. The method according to claim 15, characterized in that The first character and / or the second character is a value other than a row number of the first LDPC base matrix.

17. The method according to claim 15 or 16, characterized in that The sequence corresponding to the indication information includes a first segment, a second segment, a third segment, a fourth segment and a fifth segment in sequence, wherein the first segment is composed of the third information, the second segment is composed of the first part of the second information, the third segment is composed of the first part of the first information, the fourth segment is composed of the second part of the first information and the second part of the second information, and the fifth segment is composed of the third part of the second information.

18. The method according to claim 17, characterized in that The third segment includes one or more sub-segments, and the row number in the rth segment of the one or more sub-segments is {1,2,…,2 r-1 (M+T)-1,2 r-1 (M+T)}, wherein r is a positive integer and T is the number of characters in the first part of the second information.

19. A communication device, characterized in that: The method comprises a module or a unit for executing the method as claimed in any one of claims 1 to 18.

20. A communication device, characterized in that: It includes a processor and an interface circuit, wherein the interface circuit is used to receive signals from other communication devices outside the communication device and transmit them to the processor or send signals from the processor to other communication devices outside the communication device, and the processor is used to implement the method as described in any one of claims 1 to 18 through a logic circuit or executing code instructions.

21. The communication device according to claim 20, characterized in that: The communication device is a chip or a chip system.

22. A computer-readable storage medium, characterized in that: The storage medium stores a computer program or an instruction. When the computer program or the instruction is executed by the communication device, the method according to any one of claims 1 to 18 is implemented.

23. A computer program product, characterized in that The invention comprises a computer program which, when being executed, implements the method according to any one of claims 1 to 18.

24. A communication system, characterized in that: include: A sending end device for executing the method as claimed in any one of claims 1 to 3 and 8 to 18; A receiving device for executing the method as claimed in any one of claims 4 to 18.

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