Data transmission method and apparatus, processing chip and storage medium

Abstract

A data transmission method and apparatus, a processing chip, and a storage medium. The data transmission method comprises: acquiring remaining space information of a first-in first-out memory, and, on the basis of the remaining space information, determining a cache position of data to be transmitted (S110); controlling an arbiter to determine, on the basis of the remaining space information of the first-in first-out memory, a transmission policy of said data (S120); and transmitting said data at the cache position to a target chip according to the transmission policy (S130).

Description

Data transmission method, device, processing chip and storage medium

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on November 17, 2023, with application number 202311544169.9, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of data transmission technology, for example, to a data transmission method, device, processing chip and storage medium. Background Art

[0003] With the rapid development of information technology and the integration of data and industry, the amount of data has grown explosively, and the computing power required for data processing has also exploded.

[0004] To achieve greater computing power, supercomputing platforms commonly use multi-chip computing power sharing. When computing power is shared by at least three chips, inter-chip transmission paths exist between each chip. Because the speed of data consumption within a chip and the speed of data transmission between chips are not fixed, the amount of data transmitted between chips may be excessive at certain times, causing multiple chips to wait for each other, leading to congestion in the loop transmission path. Therefore, preventing congestion in the inter-chip transmission path has become a pressing issue.

[0005] Summary of the Invention

[0006] The present application provides a data transmission method, device, processing chip and storage medium to achieve caching of data to be transmitted when the amount of data transmitted between chips is too large, thereby preventing congestion in the transmission path between chips.

[0007] According to one aspect of the present application, a data transmission method is provided, the method comprising:

[0008] Obtaining remaining space information of a first-in-first-out memory, and determining a cache location of the data to be transmitted based on the remaining space information;

[0009] The control arbiter determines a transmission strategy for the data to be transmitted according to the remaining space information of the first-in-first-out memory;

[0010] The data to be transmitted in the cache location is transmitted to the target chip according to the transmission strategy.

[0011] According to another aspect of the present application, a data transmission device is provided, the device comprising:

[0012] a position determination module configured to obtain remaining space information of a first-in-first-out memory and determine a cache position of the data to be transmitted according to the remaining space information;

[0013] A strategy determination module is configured to control the arbitrator to determine a transmission strategy for data to be transmitted according to remaining space information of the first-in-first-out memory;

[0014] The data sending module is configured to transmit the data to be transmitted in the cache location to the target chip according to the transmission strategy.

[0015] According to another aspect of the present application, a processing chip is provided, wherein the processing chip includes:

[0016] at least one processing unit;

[0017] and a storage unit communicatively coupled to the at least one processing unit;

[0018] The storage unit stores a computer program that can be executed by at least one processing unit, and the computer program is executed by at least one processing unit so that the at least one processing unit can execute the data transmission method of any embodiment of the present application.

[0019] According to another aspect of the present application, a computer-readable storage medium is provided, characterized in that the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processing unit to implement the data transmission method of any embodiment of the present application when executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] FIG1 is a flow chart of a data transmission method provided according to Embodiment 1 of the present application;

[0021] FIG2 is a flow chart of a data transmission method provided according to Embodiment 2 of the present application;

[0022] FIG3 is a schematic diagram of the structure of an inter-chip transmission path proposed in Example 3 of the present application;

[0023] FIG4 is a schematic structural diagram of a data transmission device provided according to a fourth embodiment of the present application;

[0024] FIG5 is a schematic diagram of the structure of a processing chip for implementing a data transmission method according to an embodiment of the present application. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application.

[0026] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0027] Example 1

[0028] Figure 1 is a flow chart of a data transmission method according to the first embodiment of the present application. This embodiment is applicable to inter-chip data transmission. The method can be performed by a data transmission device, which can be implemented in the form of hardware and / or software and can be configured in a processing chip. As shown in Figure 1, the method includes:

[0029] S110 , obtaining remaining space information of a first-in-first-out memory, and determining a cache location of data to be transmitted according to the remaining space information.

[0030] A first-in-first-out (FIFO) memory is a first-in-first-out (FIFO) data buffer that can sequentially write data to be transmitted and sequentially read data to be transmitted. A FIFO memory can cache continuous data streams to prevent the loss of data to be transmitted during chip processing. The data to be transmitted can be data that the processing chip needs to transmit. In one embodiment, the data to be transmitted can include but is not limited to a clock signal. In actual operation, the data to be transmitted can be data that needs to be forwarded by an external chip; or it can be data that needs to be sent by the processing chip. The cache location can refer to the location where the processing chip stores the data to be processed after receiving the data to be processed. The cache location can include a first-in-first-out memory, a double-rate synchronous dynamic random access memory, and the like.

[0031] In one embodiment, the cache location includes at least one of the following: a first-in-first-out memory, and a double data rate synchronous dynamic random access memory.

[0032] Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) can transfer data twice in one clock cycle.

[0033] In an embodiment of the present application, the processing chip can obtain the remaining space information of the first-in-first-out memory in real time, and determine the cache location of the information to be transmitted according to the remaining space information of the first-in-first-out memory. In the actual operation process, the first-in-first-out memory can actively report the remaining space information; or, the processing chip actively pulls the remaining space information of the first-in-first-out memory, which is not limited to this. The cache location may include a first-in-first-out memory and a double-rate synchronous dynamic random access memory. In one embodiment, a first threshold remaining space information can be pre-set. When the remaining space information is greater than the first threshold remaining space information, the cache location of the data to be transmitted is determined to be the first-in-first-out memory; when the remaining space information is less than or equal to the first threshold remaining space information, the cache location of the data to be transmitted is determined to be the double-rate synchronous dynamic random access memory.

[0034] S120 , the control arbiter determines a transmission strategy for the data to be transmitted according to the remaining space information of the FIFO memory.

[0035] An arbiter is a device that determines which module receives priority control when multiple modules compete for transmission control. In actual operation, arbiters may include, but are not limited to, 2-choose-1 arbiters and round-robin arbiters. A transmission strategy is a strategy for transmitting data to be transmitted, which can be determined based on the remaining space in the first-in-first-out memory. In one embodiment, a transmission strategy can include transmitting data to be transmitted from the first-in-first-out memory and transmitting data to be transmitted from the double-bit-rate synchronous dynamic random access memory.

[0036] In an embodiment of the present application, the processing chip can control the arbiter to obtain the remaining space information of the first-in-first-out memory, and the arbiter can determine the transmission strategy of the data to be transmitted based on the remaining space information of the first-in-first-out memory. In the actual operation process, the second threshold remaining space information can be set in advance. When the remaining space information is greater than the second threshold remaining space information, the transmission strategy is determined to be the transmission of the data to be transmitted of the double-rate synchronous dynamic random access memory; when the remaining space information is less than or equal to the second threshold remaining space information, the transmission strategy is determined to be the transmission of the data to be transmitted of the first-in-first-out memory. In other words, when the remaining space information of the first-in-first-out memory is small, the arbitrator gives authority to the first-in-first-out memory, and when the remaining space information of the first-in-first-out memory is large, the arbitrator gives authority to the double-rate synchronous dynamic random access memory, so as to give priority to the transmission of the data to be transmitted of the first-in-first-out memory as much as possible.

[0037] S130 , transmitting the data to be transmitted in the cache location to the target chip according to the transmission strategy.

[0038] The target chip may be a target sending chip for data to be transmitted, and the data transmission path between the target chip and the initial chip may be pre-set. The target chip may be determined according to the data transmission path of the processing chip.

[0039] In an embodiment of the present application, after determining a transmission strategy, a target chip can be determined, and the data to be transmitted in the cache location can be transmitted to the target chip according to the transmission strategy. In actual operation, if the transmission strategy is to transmit data to be transmitted in a first-in-first-out memory, the data to be transmitted in the first-in-first-out memory can be transmitted to the target chip according to the transmission strategy; if the transmission strategy is to transmit data to be transmitted in a double-bit rate synchronous dynamic random access memory, the data to be transmitted in the double-bit rate synchronous dynamic random access memory can be transmitted to the target chip according to the transmission strategy.

[0040] In an embodiment of the present application, by obtaining the remaining space information of the first-in-first-out memory, determining the cache location of the data to be transmitted according to the remaining space information, controlling the arbitrator to determine the transmission strategy of the data to be transmitted according to the remaining space information of the first-in-first-out memory, and transmitting the data to be transmitted at the cache location to the target chip according to the transmission strategy, the cache location and transmission strategy of the data to be transmitted are determined according to the remaining space information of the first-in-first-out memory. When the amount of data transmission between chips is too large, the data to be transmitted is cached to prevent the transmission path between chips from being blocked, avoid the deadlock of the transmission loop between chips, and improve the stability of the system.

[0041] In one embodiment, when the cache location of the data to be transmitted is a double data rate synchronous dynamic random access memory, the data transmission method further includes:

[0042] Determine the delay transmission time of the data to be transmitted in the double rate synchronous dynamic random access memory;

[0043] When the delayed transmission time is greater than the preset delay time, the delayed transmission time is determined to be timed out, and the number of timeouts is recorded;

[0044] When the number of times is greater than the preset number of times, the transmission strategy is adjusted to transmit the data to be transmitted in the double rate synchronous dynamic random access memory;

[0045] When the number of times is less than or equal to the preset number of times, the transmission strategy is adjusted to transmit the data to be transmitted in the first-in-first-out memory.

[0046] The delayed transmission time may refer to the increased transmission time due to the data to be transmitted being cached in the double-speed synchronous dynamic random access memory. The delayed transmission time may be determined based on the time it takes for the data to be transmitted to exit the double-speed synchronous dynamic random access memory minus the time it takes for the data to enter the double-speed synchronous dynamic random access memory. The preset delay time may be a preset maximum value of the delayed transmission time. If the delayed transmission time exceeds the preset delay time, the delayed transmission time may be considered to have timed out. The preset number of times may be a preset maximum number of timeouts. If the number of times is greater than the preset number, the transmission strategy may be adjusted. In one embodiment, the preset delay time and the preset number of times may be set according to user needs. For example, the preset delay time may include, but is not limited to, 215 clock cycles or 216 clock cycles, and the preset number of times may include, but is not limited to, 215 times or 216 times.

[0047] In an embodiment of the present application, the time when data to be transmitted enters and leaves the double-speed synchronous dynamic random access memory can be determined, and the time when the data to be transmitted leaves the double-speed synchronous dynamic random access memory minus the time when the data enters the double-speed synchronous dynamic random access memory is used as the delayed transmission time. If the delayed transmission time is greater than a preset delay time, the delayed transmission time is determined to be a timeout. The number of timeouts can be counted using a counter. If the number of timeouts is greater than a preset number, the transmission strategy is adjusted to transmit the data to be transmitted from the double-speed synchronous dynamic random access memory; if the number of timeouts is less than or equal to the preset number, the transmission strategy is adjusted to transmit the data to be transmitted from the first-in-first-out memory.

[0048] In an embodiment of the present application, by determining the delayed transmission time of the data to be transmitted in the double-speed synchronous dynamic random access memory, when the delayed transmission time is greater than the preset delay time, the delayed transmission time is determined to be a timeout, and the number of timeouts is recorded. When the number is greater than the preset number, the transmission strategy is adjusted to transmit the data to be transmitted in the double-speed synchronous dynamic random access memory; when the number is less than or equal to the preset number, the transmission strategy is adjusted to transmit the data to be transmitted in the first-in-first-out memory, so that when the delayed transmission time of the data to be transmitted in the double-speed synchronous dynamic random access memory is too high, the data to be synchronized in the double-speed synchronous dynamic random access memory is transmitted, the additional transmission time of the data to be transmitted in the double-speed synchronous dynamic random access memory is reduced, and the data to be transmitted is prevented from being cached in the processing chip for a long time.

[0049] In one embodiment, determining a transmission delay time of data to be transmitted in a double data rate synchronous dynamic random access memory includes:

[0050] Determine a first timestamp of buffering the data to be transmitted into the double rate synchronous dynamic random access memory;

[0051] determining a second timestamp of transmitting the data to be transmitted to the arbitrator;

[0052] The delayed transmission time is obtained by subtracting the first timestamp from the second timestamp.

[0053] The first timestamp may be used to identify the time when the data to be transmitted enters the double data rate synchronous dynamic random access memory; the second timestamp may be used to indicate the time when the data to be transmitted is transmitted to the arbitrator, that is, the time when it leaves the double data rate synchronous dynamic random access memory.

[0054] In an embodiment of the present application, when the data to be transmitted is cached in a double data rate synchronous dynamic random access memory, the timestamp can be recorded as the first timestamp. When the data to be transmitted is read again from the double data rate synchronous dynamic random access memory and sent to the arbitrator, the real time can be recorded as the second timestamp, and the first timestamp is subtracted from the second timestamp to obtain the delayed transmission time.

[0055] Example 2

[0056] FIG2 is a flow chart of a data transmission method according to the second embodiment of the present application. This embodiment is an explanation of a data transmission method based on the above embodiment. As shown in FIG2, the method includes:

[0057] S210: Receive remaining space information of a first-in-first-out memory, and extract first threshold remaining space information.

[0058] The first threshold remaining space information may be a critical value for determining the amount of remaining space information in the FIFO memory and may be set according to user needs. In one embodiment, if the remaining space information is greater than the first threshold remaining space information, the FIFO memory remaining space information may be considered to be large; if the remaining space information is less than or equal to the first threshold remaining space information, the FIFO memory remaining space information may be considered to be small.

[0059] In an embodiment of the present application, the FIFO memory can proactively report remaining space information, and the processing chip receives the remaining space information reported by the FIFO memory. Simultaneously, the processing chip can retrieve pre-stored remaining space information based on a first threshold. In actual operation, a reporting period for the FIFO processor can be pre-set, and the FIFO memory can report remaining space information based on the reporting period. In one embodiment, the reporting period can include, but is not limited to, one clock cycle, two clock cycles, and the like, and is not limited to this.

[0060] S220: When the remaining space information is greater than the first threshold remaining space information, determine that the cache location of the data to be transmitted is a first-in-first-out memory.

[0061] In an embodiment of the present application, after obtaining the remaining space information, the relationship between the remaining space information and the first threshold remaining space information can be determined. If the remaining space information is greater than the first threshold remaining space information, it can be determined that the remaining space information of the first-in-first-out memory is larger, and the cache location of the data to be transmitted is determined to be the first-in-first-out memory.

[0062] S230: When the remaining space information is less than or equal to the first threshold remaining space information, determine that the cache location of the data to be transmitted is a double data rate synchronous dynamic random access memory.

[0063] In an embodiment of the present application, when the remaining space information is less than or equal to the first threshold remaining space information, it can be determined that the remaining space information of the first-in-first-out memory is small, and the cache location of the data to be transmitted is determined to be the double rate synchronous dynamic random access memory.

[0064] S240: Control the arbitrator to receive remaining space information of the first-in-first-out memory.

[0065] In the embodiment of the present application, the FIFO memory can proactively report remaining space information, and the processing chip can control the arbitrator to receive the remaining space information reported by the FIFO memory. In actual operation, the remaining space information of the FIFO memory received by the processing chip is the same as the remaining space information of the FIFO memory received by the arbitrator.

[0066] S250: When the remaining space information is greater than the second threshold remaining space information, determine the transmission strategy as transmitting the data to be transmitted in the double data rate synchronous dynamic random access memory.

[0067] The second threshold remaining space information can be understood as a critical value for updating the transmission strategy and can be set by the user as needed. In one embodiment, if the remaining space information is greater than the second threshold remaining space information, the FIFO memory remaining space information can be considered to be greater; if the remaining space information is less than or equal to the first threshold remaining space information, the FIFO memory remaining space information can be considered to be less. The first threshold remaining space information and the second threshold remaining space information can be the same or different, and this is not limited to this.

[0068] In an embodiment of the present application, after the control arbiter obtains the remaining space information, the arbiter can determine the relationship between the remaining space information and the second threshold remaining space information. If the remaining space information is greater than the second threshold remaining space information, it can be determined that the remaining space information of the first-in-first-out memory is large, and the transmission strategy is determined to be to transmit the data to be transmitted from the double data rate synchronous dynamic random access memory.

[0069] S260: When the remaining space information is less than or equal to the second threshold remaining space information, determine the transmission strategy as transmitting the data to be transmitted in the first-in-first-out memory.

[0070] In the embodiment of the present application, when the remaining space information is less than or equal to the second threshold remaining space information, it can be determined that the remaining space information of the FIFO memory is small, and the transmission strategy is determined to transmit the data to be transmitted in the FIFO memory.

[0071] S270: Determine a target chip that receives the data to be transmitted.

[0072] In the embodiment of the present application, the data transmission path of the processing chip can be extracted, and the chip corresponding to the transmission path is determined as the target chip to receive the data to be transmitted. In actual operation, the target chip can be a pre-set receiving chip.

[0073] S280 . When the transmission strategy is to transmit the data to be transmitted in the first-in-first-out memory, the data to be transmitted cached in the first-in-first-out memory is sent to the target chip.

[0074] In an embodiment of the present application, after the transmission strategy and the target chip are determined, the data to be transmitted can be transmitted to the target chip according to the transmission strategy. In the case where the transmission strategy is to transmit the data to be transmitted in the first-in-first-out memory, the data to be transmitted cached in the first-in-first-out memory can be sent to the target chip according to the transmission strategy.

[0075] S290: When the transmission strategy is to transmit the data to be transmitted in the double data rate synchronous dynamic random access memory, send the data to be transmitted cached in the double data rate synchronous dynamic random access memory to the target chip.

[0076] In an embodiment of the present application, when the transmission strategy is to transmit the data to be transmitted in the double data rate synchronous dynamic random access memory, the data to be transmitted cached in the double data rate synchronous dynamic random access memory can be sent to the target chip according to the transmission strategy.

[0077] In an embodiment of the present application, by receiving the remaining space information of the first-in-first-out memory and extracting the first threshold remaining space information, when the remaining space information is greater than the first threshold remaining space information, the cache location of the data to be transmitted is determined to be the first-in-first-out memory; when the remaining space information is less than or equal to the first threshold remaining space information, the cache location of the data to be transmitted is determined to be the double-rate synchronous dynamic random access memory, thereby realizing the determination of the cache location of the data to be transmitted according to the remaining space information of the first-in-first-out memory. By controlling the arbiter to receive the remaining space information of the first-in-first-out memory, when the remaining space information is greater than the second threshold remaining space information, determining the transmission strategy to transmit the data to be transmitted of the double-rate synchronous dynamic random access memory; when the remaining space information is less than or equal to the second threshold remaining space information, determining the transmission strategy to transmit the data to be transmitted of the first-in-first-out memory, determining the target chip to receive the data to be transmitted, when the transmission strategy is to transmit the data to be transmitted of the first-in-first-out memory, sending the data to be transmitted cached in the first-in-first-out memory to the target chip; when the transmission strategy is to transmit the data to be transmitted of the double-rate synchronous dynamic random access memory, sending the data to be transmitted cached in the double-rate synchronous dynamic random access memory to the target chip, realizing determining the transmission strategy through the remaining space information of the first-in-first-out memory, updating the transmission strategy when the remaining space information is small, reducing the additional transmission time of the data to be transmitted in the double-rate synchronous dynamic random access memory, preventing the data to be transmitted from being cached in the processing chip for a long time, and avoiding congestion in the transmission path between chips.

[0078] Example 3

[0079] FIG3 is a schematic diagram of the structure of the inter-chip transmission path proposed in Example 3 of the present application. This embodiment is based on the above embodiment and takes the example of a processing chip consisting of a data distribution module, a first-in-first-out memory, a double-rate synchronous dynamic random access memory, and an arbiter. The data distribution module is configured to receive the remaining space information of the first-in-first-out memory to determine the cache location of the data to be transmitted. The arbiter is a 2-to-1 arbiter as an example to illustrate a data transmission method. As shown in FIG3:

[0080] The processing chip preferentially uses a first-in-first-out memory (FIFO) to cache data to be transmitted that is to be sent to other chips. The data to be transmitted can be generated inside the processing chip, or it can be data from an external chip that needs to be forwarded to the target chip. The data distribution module can detect the remaining space information in the FIFO in real time. When the remaining space information is small, the data sent to the target chip can be temporarily stored in a double data rate synchronous dynamic random access memory (DDR). In one embodiment, by extracting the first threshold remaining space information, when the remaining space information is greater than the first threshold remaining space information, the cache location of the data to be transmitted can be determined to be a first-in-first-out memory; when the remaining space information is less than or equal to the first threshold remaining space information, the cache location of the data to be transmitted can be determined to be a double data rate synchronous dynamic random access memory.

[0081] After the data to be transmitted in the DDR cache location is read, it can be sent to the target chip after passing through a 2-to-1 arbiter together with the data in the original FIFO. The 2-to-1 arbiter can detect the remaining space information in the FIFO in real time. When there is more free storage, the authority is given to the DDR path. When there is less free storage, the authority is given to the FIFO, and the data stored in the FIFO is sent as much as possible. In one embodiment, the second threshold remaining space information can be extracted. When the remaining space information is greater than the second threshold remaining space information, the transmission strategy is determined to be the transmission of the data to be transmitted from the double-rate synchronous dynamic random access memory; when the remaining space information is less than or equal to the second threshold remaining space information, the transmission strategy is determined to be the transmission of the data to be transmitted from the first-in-first-out memory.

[0082] In one embodiment, when the cache location is DDR, a timestamp (first timestamp) of the data to be transmitted being cached in the DDR can be recorded and written to the DDR. When the data to be transmitted is read back from the DDR and sent to the target chip via an arbitrator, a real-time timestamp (second timestamp) can be determined. The timestamp information carried in the data is subtracted from the real-time timestamp to obtain the additional transmission time of the data due to being cached in the DDR, i.e., the delayed transmission time. A counter is used to count the number of times the delayed transmission time exceeds a preset delay time, and the transmission strategy is adjusted. In one embodiment, if the number of times exceeds the preset number, the transmission strategy is adjusted to transmit the data to be transmitted from the double data rate synchronous dynamic random access memory; if the number of times is less than or equal to the preset number, the transmission strategy is adjusted to transmit the data to be transmitted from the first-in-first-out memory.

[0083] Example 4

[0084] FIG4 is a schematic diagram of the structure of a data transmission device according to a fourth embodiment of the present application. As shown in FIG4 , the device includes: a location determination module 41 , a strategy determination module 42 and a data sending module 43 .

[0085] The location determination module 41 is configured to obtain remaining space information of the first-in-first-out memory and determine a cache location of the data to be transmitted according to the remaining space information.

[0086] The strategy determination module 42 is configured to control the arbitrator to determine a transmission strategy for the data to be transmitted according to the remaining space information of the first-in-first-out memory.

[0087] The data sending module 43 is configured to transmit the data to be transmitted in the cache location to the target chip according to the transmission strategy.

[0088] In an embodiment of the present application, the remaining space information of the first-in-first-out memory is obtained through a position determination module, and the cache position of the data to be transmitted is determined according to the remaining space information. The strategy determination module controls the arbitrator to determine the transmission strategy of the data to be transmitted according to the remaining space information of the first-in-first-out memory. The data sending module transmits the data to be transmitted at the cache position to the target chip according to the transmission strategy, thereby realizing the determination of the cache position and transmission strategy of the data to be transmitted according to the remaining space information of the first-in-first-out memory. When the data transmission volume between chips is too large, the data to be transmitted is cached to prevent the transmission path between chips from being blocked and to avoid deadlock of the transmission loop between chips.

[0089] In one embodiment, the cache location in the location determination module 41 includes at least one of the following: a first-in-first-out memory, and a double data rate synchronous dynamic random access memory.

[0090] In one embodiment, the data transmission device further includes:

[0091] A delay time determination module is configured to determine a delay transmission time of data to be transmitted in a double rate synchronous dynamic random access memory;

[0092] A timeout number recording module is configured to determine that the delayed transmission time is a timeout when the delayed transmission time is greater than a preset delay time, and record the number of timeouts;

[0093] A first transmission strategy adjustment module is configured to adjust the transmission strategy to transmit the data to be transmitted in the double data rate synchronous dynamic random access memory when the number of times is greater than a preset number of times;

[0094] The second transmission strategy adjustment module is configured to adjust the transmission strategy to transmit the data to be transmitted in the first-in-first-out memory when the number of times is less than or equal to the preset number of times.

[0095] In one embodiment, the delay time determination module includes:

[0096] A first timestamp determining unit, configured to determine a first timestamp of data to be transmitted cached in the double rate synchronous dynamic random access memory;

[0097] a second timestamp determining unit, configured to determine a second timestamp of the data to be transmitted when it is transmitted to the arbitrator;

[0098] The delay time determining unit is configured to subtract the first timestamp from the second timestamp as the delayed transmission time.

[0099] In one embodiment, the location determination module 41 includes:

[0100] a space information receiving unit configured to receive remaining space information from the first-in-first-out memory and extract first threshold remaining space information;

[0101] a first position determining unit configured to determine that the cache location of the data to be transmitted is a first-in-first-out memory when the remaining space information is greater than the first threshold remaining space information;

[0102] The second position determining unit is configured to determine that the cache location of the data to be transmitted is the double rate synchronous dynamic random access memory when the remaining space information is less than or equal to the first threshold remaining space information.

[0103] In one embodiment, the policy determination module 42 includes:

[0104] a remaining information receiving unit, configured to control the arbitrator to receive remaining space information of the first-in-first-out memory;

[0105] a first transmission strategy determining module configured to determine, when the remaining space information is greater than the second threshold remaining space information, that the transmission strategy is to transmit the data to be transmitted in the double data rate synchronous dynamic random access memory;

[0106] The second transmission strategy determining module is configured to determine the transmission strategy as transmitting the data to be transmitted in the first-in-first-out memory when the remaining space information is less than or equal to the second threshold remaining space information.

[0107] In one embodiment, the data sending module 43 includes:

[0108] A target chip determination module is configured to determine a target chip that receives data to be transmitted;

[0109] a first data transmission unit configured to send the data to be transmitted cached in the first-in-first-out memory to the target chip when the transmission strategy is to transmit the data to be transmitted in the first-in-first-out memory;

[0110] The second data transmission unit is configured to send the data to be transmitted cached in the double data rate synchronous dynamic random access memory to the target chip when the transmission strategy is to transmit the data to be transmitted in the double data rate synchronous dynamic random access memory.

[0111] The data transmission device provided in the embodiments of the present application can execute the data transmission method provided in any embodiment of the present application, and has the corresponding functional modules and effects of the execution method.

[0112] Example 5

[0113] Figure 5 is a schematic diagram of the structure of a processing chip 10 that implements a data transmission method according to an embodiment of the present application. The components, their connections and relationships, and their functions shown herein are merely examples and are not intended to limit the implementation of the present application as described and / or claimed herein.

[0114] As shown in FIG5 , the processing chip 10 includes at least one processing unit 11 and a storage unit, such as a read-only memory (ROM) 12 and a random access memory (RAM) 13, which are communicatively connected to the at least one processing unit 11. The storage unit stores a computer program that can be executed by the at least one processing unit. The processing unit 11 can perform a variety of appropriate actions and processes according to the computer program stored in the ROM 12 or the computer program loaded from the storage unit 18 to the RAM 13. In the RAM 13, a variety of programs and data required for the operation of the processing chip 10 can also be stored. The processing unit 11, ROM 12, and RAM 13 are connected to each other via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0115] Various components in processing chip 10 are connected to I / O interface 15, including: an input unit 16, such as a keyboard, mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a magnetic disk, optical disk, etc.; and a communication unit 19, such as a network card, modem, wireless communication transceiver, etc. Communication unit 19 allows processing chip 10 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0116] The processing unit 11 can be a variety of general-purpose and / or specialized processing components with processing and computing capabilities. Some examples of the processing unit 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The processing unit 11 performs the methods and processes described above, such as the data transmission method.

[0117] In some embodiments, the data transmission method may be implemented as a computer program tangibly embodied in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed onto processing chip 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processing unit 11, one or more steps of the data transmission method described above may be performed. Alternatively, in other embodiments, processing unit 11 may be configured to perform the data transmission method in any other suitable manner (e.g., via firmware).

[0118] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard parts (ASSPs), system on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0119] Computer programs for implementing the methods of the present application may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the computer program is executed by the processor, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The computer program may be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0120] In the context of the present application, computer-readable storage medium can be a tangible medium that can contain or store a computer program for use by an instruction execution system, device or equipment or used in combination with an instruction execution system, device or equipment. Computer-readable storage medium can include but is not limited to electronic, magnetic, optical, electromagnetic, infrared or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, computer-readable storage medium can be a machine-readable signal medium. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory RAM, a read-only memory ROM, an erasable programmable read-only memory (EPROM) or a flash memory, an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device or any suitable combination of the foregoing.

[0121] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a cathode ray tube (CRT) or a liquid crystal display (LCD) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0122] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with embodiments of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0123] A computing system may include a client and a server. The client and server are generally remote from each other and typically interact via a communication network. The client-server relationship arises through computer programs running on the respective computers and establishing a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, a host product within a cloud computing service ecosystem that addresses the management difficulties and limited scalability of traditional physical hosts and virtual private server (VPS) services.

[0124] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the multiple steps described in this application can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of this application can be achieved. This is not limited herein.

[0125] The above specific implementation methods do not constitute a limitation on the scope of protection of this application.

Claims

1. A data transmission method, include: Acquire remaining space information of a first-in-first-out memory, and determine a cache location of the data to be transmitted according to the remaining space information; The control arbitrator determines a transmission strategy for the data to be transmitted according to the remaining space information of the first-in-first-out memory; The data to be transmitted in the cache location is transmitted to a target chip according to the transmission strategy.

2. The method according to claim 1, in, The cache location includes at least one of the following: the first-in-first-out memory, a double rate synchronous dynamic random access memory.

3. The method according to claim 1, wherein when the cache location of the data to be transmitted is a double rate synchronous dynamic random access memory, the method further comprises: include: Determining a delayed transmission time of the data to be transmitted in the double rate synchronous dynamic random access memory; When the delayed transmission time is greater than the preset delay time, determining that the delayed transmission time is timed out, and recording the number of timeouts; When the number is greater than the preset number, adjusting the transmission strategy to transmit the data to be transmitted of the double rate synchronous dynamic random access memory; When the number is less than or equal to the preset number, the transmission strategy is adjusted to transmit the data to be transmitted in the first-in-first-out memory.

4. The method according to claim 3, in, The step of determining the delayed transmission time of the data to be transmitted in the double rate synchronous dynamic random access memory comprises: Determine a first timestamp of caching the data to be transmitted into the double rate synchronous dynamic random access memory; Determine a second timestamp when the data to be transmitted is transmitted to the arbitrator; The delayed transmission time is obtained by subtracting the first timestamp from the second timestamp.

5. The method according to claim 1, in, The obtaining of remaining space information of the first-in-first-out memory and determining the cache location of the data to be transmitted according to the remaining space information includes: receiving the remaining space information of the first-in-first-out memory, and extracting first threshold remaining space information; When the remaining space information is greater than the first threshold remaining space information, determining that the cache location of the data to be transmitted is the first-in-first-out memory; When the remaining space information is less than or equal to the first threshold remaining space information, it is determined that the cache location of the data to be transmitted is a double rate synchronous dynamic random access memory.

6. The method according to claim 1, in, The control arbiter determines the transmission strategy of the data to be transmitted according to the remaining space information of the first-in-first-out memory, including: Controlling the arbitrator to receive the remaining space information of the first-in-first-out memory; In the case where the remaining space information is greater than the second threshold remaining space information, determining that the transmission strategy is to transmit the data to be transmitted of the double rate synchronous dynamic random access memory; When the remaining space information is less than or equal to the second threshold remaining space information, the transmission strategy is determined to be transmitting the data to be transmitted in the first-in-first-out memory.

7. The method according to claim 1, in, The transmitting the data to be transmitted in the cache location to the target chip according to the transmission strategy includes: Determine the target chip to receive the data to be transmitted; When the transmission strategy is to transmit the data to be transmitted in the first-in-first-out memory, sending the data to be transmitted cached in the first-in-first-out memory to the target chip; In the case where the transmission strategy is to transmit the data to be transmitted of the double rate synchronous dynamic random access memory The data to be transmitted cached in the double rate synchronous dynamic random access memory is sent to the target chip.

8. A data transmission device, include: A location determination module, configured to obtain remaining space information of a first-in-first-out memory, and determine a cache location of data to be transmitted according to the remaining space information; A strategy determination module, configured to control the arbitrator to determine a transmission strategy for the data to be transmitted according to the remaining space information of the first-in-first-out memory; The data sending module is configured to transmit the data to be transmitted in the cache location to a target chip according to the transmission strategy.

9. A processing chip, the processing chip include: at least one processing unit; and a storage unit communicatively connected to the at least one processing unit; The storage unit stores a computer program that can be executed by the at least one processing unit, and the computer program is executed by the at least one processing unit so that the at least one processing unit can execute the data transmission method described in any one of claims 1-7.

10. A computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable a processing unit to implement the data transmission method according to any one of claims 1 to 7 when the processing unit executes the computer instructions.

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