Buffer circuit, linear regulator, display panel, and near-eye display device

Abstract

A buffer circuit, a linear regulator, a display panel, and a head-mounted display device. The buffer circuit (20) comprises an error amplification module (11), a voltage clamping module (12), and an output module (13); an input end of the voltage clamping module (12) is connected to an output end of the error amplification module (11), an output end of the voltage clamping module (12) is connected to a first input end (O1) of the output module (13), and the voltage clamping module (12) is configured to clamp, when a load current changes, the voltage of the output end of the error amplification module (11) and then transmit the clamped voltage to the first input end (O1) of the output module (13); and a second input end (O2) of the output module (13) is connected to an input end of the buffer circuit (20).

Description

Buffer circuit, linear regulator, display panel, and near-eye display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on November 17, 2023, with application number 202311543663.3, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of display technology, for example, to a buffer circuit, a linear regulator, a display panel, and a near-eye display device. Background Art

[0003] As an important circuit module in a power management unit (PMU), a low voltage linear regulator (Low Dropout Regulator, LDO) is widely used in display panels.

[0004] The relevant low-voltage linear regulator mainly consists of a voltage reference source, an error amplification module, a buffer circuit, a power transistor, and a voltage divider output module. When the load of the low-voltage linear regulator is large, the direct way to reduce the impedance of the buffer circuit is to increase its quiescent current or increase the size of the buffer circuit. However, this approach will increase the static power consumption of the entire circuit or make the area larger, and the loop response speed will be too slow. In addition, the larger buffer circuit is combined with the larger power transistor, resulting in excessive overshoot voltage in the low-voltage linear regulator when the load current changes, causing the power transistor to enter a temporary pinch-off region. When the power transistor enters the pinch-off region, the low-voltage linear regulator will temporarily enter an uncontrollable state. In display devices, the above problems will cause the visual effect of the display device to deteriorate, resulting in screen flickering or screen rolling.

[0005] Summary of the Invention

[0006] The present application provides a buffer circuit, a linear voltage regulator, a display panel, and a head-mounted display device. When the load current changes, the buffer circuit has a small overshoot voltage, the power tube does not enter the pinch-off region, the loop response speed can be improved, the dynamic current can be reduced, and thus the static power consumption of the circuit can be reduced.

[0007] In a first aspect, an embodiment of the present application provides a buffer circuit, comprising an error amplification module, a voltage clamping module, and an output module, wherein the output module includes a clamping signal receiving module, an amplified signal receiving module, and a feedback module; a first input end of the error amplification module is connected to the feedback module, a second input end of the error amplification module is connected to a first reference voltage, an output end of the error amplification module is connected to an input end of the voltage clamping module, and an output end of the voltage clamping module is connected to the clamping signal receiving module; the clamping signal receiving module and the amplified signal receiving module are jointly connected to an output end of the output module; the amplified signal receiving module is configured to receive a first amplified signal and operate under the control of the first amplified signal; the error amplification module is configured to compare the feedback voltage of the feedback module with the first reference voltage and generate a second amplified signal, and the voltage clamping module is configured to generate a clamping signal under the action of the second amplified signal; the clamping signal receiving module is configured to operate under the control of the clamping signal; and the amplified signal receiving module and the clamping signal receiving module jointly control the voltage at the output end of the output module.

[0008] In a second aspect, an embodiment of the present application provides a linear regulator, comprising the buffer circuit provided by any embodiment of the present application; the linear regulator also includes an operational amplifier module and a power tube; the first input end of the operational amplifier module is connected to the output end of the linear regulator, the second input end of the operational amplifier module is connected to the second reference voltage, the output end of the operational amplifier module is connected to the amplified signal receiving module of the buffer circuit, and is configured to provide the first amplified signal; the gate of the power tube is connected to the output end of the buffer circuit, the first pole of the power tube serves as the output end of the linear regulator, and the second pole of the power tube is connected to a power supply.

[0009] In a third aspect, an embodiment of the present application provides a display panel, comprising the linear regulator provided by any embodiment of the present application.

[0010] In a fourth aspect, an embodiment of the present application provides a head-mounted display device, comprising a silicon-based organic light emitting diode (OLED) display panel provided in any embodiment of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG1 is a schematic structural diagram of a buffer circuit provided in an embodiment of the present application;

[0012] FIG2 is a voltage-current curve diagram of a low-voltage linear regulator including a voltage clamping module provided in an embodiment of the present application under a load current variation condition;

[0013] FIG3 is a schematic diagram of another dynamic current and voltage limiting buffer circuit provided in an embodiment of the present application;

[0014] FIG4 is a schematic diagram of a dynamic current and voltage limiting buffer circuit that does not include a voltage clamping module;

[0015] FIG5 is a schematic structural diagram of another buffer circuit provided in an embodiment of the present application;

[0016] FIG6 is a schematic structural diagram of another buffer circuit provided in an embodiment of the present application;

[0017] FIG7 is a schematic structural diagram of a display panel provided in an embodiment of the present application;

[0018] FIG8 is a schematic structural diagram of a near-eye display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application.

[0020] The terms "first," "second," and the like in the specification and claims of this application and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the application described herein can be implemented in sequences other than those illustrated or described herein. In addition, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions.

[0021] Figure 1 is a schematic diagram of the structure of a buffer circuit provided in an embodiment of the present application. This embodiment of the present application also provides a low-voltage linear regulator including the buffer circuit shown in Figure 1. The buffer circuit in this embodiment of the present application is a dynamic current-limiting and voltage-limiting buffer circuit, which is suitable for providing a dynamic control voltage to the gate of a power transistor in a low-voltage linear regulator.

[0022] Continuing to refer to FIG. 1 , the dynamic current and voltage limiting buffer circuit 20 includes an error amplification module 11 , a voltage clamping module 12 and an output module 13 .

[0023] The output module 13 includes a clamping signal receiving module 131, an amplified signal receiving module 132, and a feedback module 133. The clamping signal receiving module 131 is configured to receive the clamping signal provided by the voltage clamping module 12 and operate under the control of this clamping signal. The amplified signal receiving module 132 is configured to receive an external first amplified signal and operate under the control of this first amplified signal. The feedback module 133 is configured to convert the current changes flowing through the amplified signal receiving module 132 into voltage changes and feed them back to the first input terminal of the error amplification module 11. The output module 13 also includes a first input terminal O1, a second input terminal O2, an output terminal PG, and a feedback terminal FB.

[0024] The first input of the error amplification module 11 is connected to the feedback terminal FB of the feedback module 133, and the second input of the error amplification module 11 is connected to the first reference voltage Vref1. The error amplification module 11 compares the feedback voltage at the feedback terminal FB of the output module 13 with the first reference voltage Vref1 to generate a second amplified signal for controlling the voltage clamping module 12. A reference voltage source can be used to provide the error amplification module 11 with a high-precision first reference voltage Vref1. Figure 1 schematically illustrates a case where the first input of the error amplification module 11 is a non-inverting input, and the second input of the error amplification module 11 is an inverting input.

[0025] The input of the voltage clamping module 12 is connected to the output of the error amplification module 11. The output of the voltage clamping module 12 is connected to the first input O1 of the output module 13. The first input O1 is connected to the control terminal of the clamping signal receiving module 131. The voltage clamping module 12 is configured to provide a clamping signal to the clamping signal receiving module 131 to control the output module 13 to output a set of dynamic voltages when the load current changes. This prevents the low-voltage linear regulator from outputting excessive current and limits the current range of the low-voltage linear regulator.

[0026] The second input terminal O2 of the output module 13 serves as the input terminal of the dynamic current limiting and voltage limiting buffer circuit 20 and is connected to the control terminal of the amplified signal receiving module 132. The output terminal PG of the output module 13 serves as the output terminal of the dynamic current limiting and voltage limiting buffer circuit 20. The output module 13 is configured to control the output terminal PG to follow the first input terminal O1 and the second input terminal O2 to output voltage.

[0027] FIG1 also schematically illustrates the connection structure between the dynamic current-limiting and voltage-limiting buffer circuit 20 and other modules of the low-voltage linear regulator 30. The low-voltage linear regulator 30 also includes an operational amplifier module 10 and a power transistor MP. The second input terminal O2 of the dynamic current-limiting and voltage-limiting buffer circuit 20 is connected to the output terminal of the operational amplifier module 10, providing a first amplified signal to the amplified signal receiving module 132. The output terminal PG of the dynamic current-limiting and voltage-limiting buffer circuit 20 is connected to the gate of the power transistor MP of the low-voltage linear regulator 30. The first input terminal of the operational amplifier module 10 is connected to the output terminal (OUT) of the low-voltage linear regulator 30, and the second input terminal of the operational amplifier module 10 is connected to a second reference voltage Vref2. For example, in the structure shown in FIG1, the power transistor MP is a P-type metal oxide semiconductor (PMOS) field-effect transistor. The first input terminal of the operational amplifier module 10 is a non-inverting input terminal, and the second input terminal is an inverting input terminal.

[0028] The power transistor MP, also known as the pass transistor, primarily functions as a channel for supplying high current to the load. The first terminal of the power transistor MP is connected to the power supply VP+, and the second terminal is connected to the output of the linear regulator. Power transistors MP include, but are not limited to, NPN transistors, PNP transistors, PMOS transistors, or N-type metal oxide semiconductor (NMOS) transistors. Figure 1 schematically illustrates a PMOS power transistor MP.

[0029] When the load current of the low-voltage linear regulator 30 changes, the voltage at the output terminal OUT changes. The output terminal OUT feeds back its own voltage change to the first input terminal of the operational amplifier module 10. The output terminal of the operational amplifier module 10 generates a first amplified signal based on the signal at the first input terminal, and provides it to the amplified signal receiving module 132 to control the operating state of the amplified signal receiving module 132. The feedback module 133 converts the current change flowing through the amplified signal receiving module 132 into a voltage change and feeds it back to the first input terminal of the error amplifier module 11. The error amplifier module 11 outputs a second amplified signal to the voltage clamping module 12 based on the voltage change. The voltage clamping module 12 outputs a clamping signal to the clamping signal receiving module 131 based on the second amplified signal and controls the operating state of the clamping signal receiving module 131. The clamping signal receiving module 131 and the amplified signal receiving module 132 jointly control the potential of the output terminal PG.

[0030] Optionally, the change in the load current of the low-voltage linear regulator 30 may refer to a change from light load to heavy load, such as when an external high-power power circuit suddenly starts working; or it may refer to a change from heavy load to light load, such as when an external high-power power circuit suddenly stops working.

[0031] When the load current changes from a light load to a heavy load, the clamping signal receiving module 131 and the amplifying signal receiving module 132 first jointly control the potential of the output terminal PG to enhance the driving capability of the power tube MP, so that the power tube MP can output a larger current to meet the operation of the external circuit; then, the clamping signal receiving module 131 and the amplifying signal receiving module 132 jointly control the potential of the output terminal PG to suppress the trend of enhancing the driving capability of the power tube MP, so that the power tube MP quickly enters a stable heavy-load operating state.

[0032] When the load current changes from a heavy load to a light load, the clamping signal receiving module 131 and the amplifying signal receiving module 132 first jointly control the potential of the output terminal PG to weaken the driving capability of the power tube MP, so that the power tube MP can reduce the output current to correspond to the light load state. Then, the clamping signal receiving module 131 and the amplifying signal receiving module 132 jointly control the potential of the output terminal PG again to suppress the trend of weakening the driving capability of the power tube MP, so that the power tube MP quickly enters a stable light load operating state.

[0033] During the above-mentioned change process, the voltage clamping module 12 provides a clamping signal, so that the clamping signal receiving module 131 and the amplified signal receiving module 132 jointly and quickly control the potential of the output terminal PG, so that the low-voltage linear regulator 30 can quickly change the operating current and quickly enter a stable working state.

[0034] Optionally, the power tube MP is a PMOS tube. When the potential of the output terminal PG decreases, the driving capability of the power tube MP is enhanced, and the power tube MP can provide a larger current; when the potential of the output terminal PG increases, the driving capability of the power tube MP is weakened, and the output current of the power tube MP decreases.

[0035] Optionally, the output module 13 can be a PMOS source follower. The clamping signal receiving module 131 includes an eleventh transistor MB1, and the amplified signal receiving module 132 includes a twelfth transistor MB2. Both the eleventh transistor MB1 and the twelfth transistor MB2 are PMOS transistors. Optionally, the output module 13 has a relatively small input capacitance and a relatively low output impedance. For example, the input capacitance of the output module 13 can be between 100 fF and 1 pF, and the output impedance of the output module 13 can be between 10Ω and 200Ω.

[0036] Optionally, the feedback module 133 includes a feedback resistor RF. The clamped signal receiving module 131 is connected between the power supply VP+ and the output terminal PG, and the amplified signal receiving module 132 is connected between the output terminal PG and the feedback resistor RF. The feedback resistor RF is also grounded. However, the present application is not limited to this embodiment. In other embodiments, the structure of the output module 13 can also be other forms. Optionally, the feedback module 133 provides a lower feedback voltage, and the feedback voltage range can be set to be less than the first reference voltage Vref1.

[0037] In FIG1 , the gate of the eleventh transistor MB1 is the control terminal of the clamping signal receiving module 131 and is connected to the first input terminal O1 of the output module 13. The second electrode of the eleventh transistor MB1 is connected to the output terminal PG, and the first electrode of the eleventh transistor MB1 is connected to the power supply VP+. The gate of the twelfth transistor MB2 is the control terminal of the amplified signal receiving module 132 and is connected to the second input terminal O2 of the output module 13. The first electrode of the twelfth transistor MB2 is connected to the output terminal PG, and the second electrode of the twelfth transistor MB2 is connected to the first end of the feedback resistor RF. The second end of the feedback resistor RF is grounded, and the first end of the feedback resistor RF serves as the feedback terminal FB of the output module 13.

[0038] FIG2 is a voltage-current curve diagram of a low-voltage linear regulator including a voltage clamping module provided in an embodiment of the present application under a condition where the load current varies. Referring to FIG1 and FIG2 , the working process of the dynamic current-limiting and voltage-limiting buffer circuit and the low-voltage linear regulator provided in an embodiment of the present application is as follows:

[0039] When the load current IL of the low-voltage linear regulator 30 changes from light load to heavy load, in the first time period T1 shown in FIG2 , the output current IL of the output terminal OUT of the low-voltage linear regulator 30 increases instantaneously, and accordingly, the output voltage V OUT The voltage V at the second input terminal O2 of the dynamic current and voltage limiting buffer circuit 20 is instantaneously reduced and fed back to the first input terminal of the operational amplifier module 10 (the non-inverting input terminal in FIG1 ). The operational amplifier module 10 outputs a first amplified signal. At this time, the first amplified signal is a low voltage signal, that is, the voltage V at the second input terminal O2 of the dynamic current and voltage limiting buffer circuit 20. O2 Decrease, control the twelfth transistor MB2 to turn on and pull down the potential V of the output terminal PG PG , thereby increasing the ability of the power tube MP to supply large current. The output terminal PG is discharged through the twelfth transistor MB2, and the current I d increases, the feedback resistor RF will d The increase in the change is converted into an increase in the voltage V FBAnd it is fed back to the first input terminal of the error amplifier 11 (the non-inverting input terminal in Figure 1); the error amplifier 11 outputs a high voltage second amplified signal to the voltage clamping module 12; the voltage clamping module 12 provides a first clamping signal to the first input terminal O1 according to the second amplified signal.

[0040] The first clamping signal provided by the voltage clamping module 12 is a small voltage change signal, which controls the voltage of the first input terminal O1 to change slightly, thereby controlling the disconnection of the eleventh transistor MB1. In the structure shown in Figure 1, the eleventh transistor MB1 is a PMOS transistor, and the first clamping signal is a small voltage increase signal to control the disconnection of the eleventh transistor MB1. However, the present application is not limited to this. If the eleventh transistor is an NMOS transistor, the first clamping signal is a small voltage drop signal to control the disconnection of the eleventh transistor.

[0041] The voltage V at the first input terminal O1 O1 The slight increase controls the eleventh transistor MB1 to be disconnected. At this time, in the output module 13, the eleventh transistor MB1 is disconnected and no longer charges the output terminal PG. The twelfth transistor MB2 is in the on state and continuously pulls down the potential V of the output terminal PG. PG That is, the eleventh transistor MB1 and the twelfth transistor MB2 jointly control the potential of the output terminal PG to decrease rapidly, thereby enhancing the ability of the power transistor MP to provide a large current.

[0042] As the output terminal potential VPG gradually decreases, the current I flowing through the twelfth transistor MB2 d The feedback voltage V FB The voltage is reduced and fed back to the non-inverting input of the error amplifier 11. The error amplifier 11 outputs a low-voltage second amplified signal, which is transmitted to the voltage clamping module 12. Based on this second amplified signal, the voltage clamping module 12 provides a second clamping signal to the first input terminal O1, controlling the rapid opening of the eleventh transistor MB1. The second clamping signal also has a small voltage change, and the voltage change of the second clamping signal is opposite to that of the first clamping signal. In the structure shown in Figure 1, the second clamping signal is a small voltage drop signal.

[0043] During the aforementioned phase, the voltage clamping module 12 controls the voltage at the first input terminal O1 to increase slightly, preventing it from increasing too high. At this point, the small voltage drop signal provided by the voltage clamping module 12 can quickly pull down the voltage at the first input terminal O1, controlling the eleventh transistor MB1 to quickly turn on to charge the output terminal PG, thereby quickly pulling up the potential of the output terminal PG. At this point, both the eleventh transistor MB1 and the twelfth transistor MB2 are in an on state, jointly controlling the potential of the output terminal PG and suppressing its tendency to increase the driving capability of the power transistor MP. This prevents the output current from continuously increasing and instead allows it to quickly stabilize. This allows the low-voltage linear regulator 30 to quickly return to a normal, stable operating state after a sudden change in load from light to heavy.

[0044] During the aforementioned change from light load to heavy load, the voltage clamping module 12 first provides a first clamping signal with a slight voltage increase, thereby raising the gate voltage of the eleventh transistor MB1 to disconnect it. However, the gate voltage of the eleventh transistor MB1 is not further increased. This is sufficient as long as the difference between the source voltage Vs and the gate voltage Vg of the eleventh transistor MB1 is less than the critical value of its threshold voltage Vth. Then, when the eleventh transistor MB1 needs to be turned on to charge the output terminal PG, only a second clamping signal with a slight voltage drop is required to quickly turn on the eleventh transistor MB1, thereby accelerating the control speed of the output terminal PG over the power transistor MP.

[0045] 1 and 2, in the embodiment of the present application, when the load current IL of the low-voltage linear regulator 30 changes from heavy load to light load, such as in the second time period T2, the heavy load is suddenly released, the output current IL decreases instantaneously, and the output voltage V OUT The voltage V O2 As the current I flowing through the twelfth transistor MB2 increases, the twelfth transistor MB2 is turned off and no longer pulls down the potential of the output terminal PG. The eleventh transistor MB1 is in the on state to charge the output terminal PG. d Decrease, feedback voltage V FBThe voltage is reduced and fed back to the non-inverting input of the error amplifier 11. The error amplifier 11 outputs a low-voltage second amplified signal, which is transmitted to the voltage clamping module 12. Based on this second amplified signal, the voltage clamping module 12 provides a third clamping signal to the first input terminal O1, controlling the eleventh transistor MB1 to remain on, continuously charging the output terminal PG and raising the potential of the output terminal PG. At this point, the twelfth transistor MB2 turns off, stopping the pull-down of the output terminal PG, while the eleventh transistor MB1 rapidly charges the output terminal PG. Together, the eleventh and twelfth transistors MB1 and MB2 control the rapid increase in the potential of the output terminal PG, weakening the driving capability of the power transistor MP, allowing the power transistor MP to reduce its output current in response to a light load. The third clamping signal is a voltage signal that keeps the eleventh transistor MB1 on. When the load current IL of the low-voltage linear regulator 30 is in a stable state before changing from a heavy load to a light load, the eleventh transistor MB1 is on. The third clamping signal can be a voltage signal that keeps the eleventh transistor MB1 on.

[0046] Subsequently, the potential of the output terminal PG increases, and the source potential of the twelfth transistor MB2 also increases. When the source voltage Vs of the twelfth transistor MB2 increases to a threshold voltage Vth different from its gate voltage Vg, the twelfth transistor MB2 turns on to discharge the output terminal PG, pulling down the potential of the output terminal PG, so that the output terminal PG enhances the output current capability of the power tube MP, so that the output current no longer continues to decrease but quickly enters a stable state, and at the same time, the output voltage V OUT The rising trend slows down, as the voltage V OUT The voltage level gradually levels off, and the circuit resumes stable operation, providing a stable low current to meet light-load operation requirements. At this point, the eleventh transistor MB1 and the twelfth transistor MB2 are both on, jointly controlling the potential of the output terminal PG and suppressing its tendency to weaken the driving capability of the power transistor MP. This allows the output current to quickly stabilize, preventing it from decreasing. This allows the low-voltage linear regulator 30 to quickly return to normal, stable operation after a sudden change from heavy to light load.

[0047] Optionally, the first reference voltage Vref1 at the second input terminal of the error amplification module 11 is a lower reference voltage. Exemplarily, the first reference voltage Vref1 is set in a range of 50 mV to 300 mV. The first input terminal of the error amplification module 11 is connected to the feedback terminal FB of the output module 13. Therefore, the voltage at the feedback terminal FB of the output module 13 is locked within the lower reference voltage range. In other words, the resistance of the feedback resistor RF can also be set to a smaller value to ensure that when the low-voltage linear regulator is overloaded, the increased dynamic current does not cause the twelfth transistor MB2 to enter the linear region, thereby avoiding circuit instability.

[0048] Optionally, the error amplification module 11 may be a single-sided PMOS differential pair folded operational amplifier, a complete folded operational amplifier, or a single-sided NMOS differential pair folded operational amplifier.

[0049] FIG3 is a schematic diagram of the structure of another dynamic current-limiting and voltage-limiting buffer circuit provided in an embodiment of the present application. The embodiment of the present application also provides a low-voltage linear regulator including the dynamic current-limiting and voltage-limiting buffer circuit shown in FIG3. Referring to FIG3, the error amplification module 11 utilizes a single-sided PMOS differential pair folded operational amplifier structure. Optionally, the error amplification module 11 includes a tail current source IS, a differential pair unit 110, a resistor unit 111, a first current source 112, a bias voltage providing module 113, and further includes a fifth transistor M5 and a sixth transistor M6.

[0050] A first terminal of the tail current source IS is connected to the power supply VP+, and a second terminal of the tail current source IS is connected to the first terminal of the differential pair unit 110, configured to provide a tail current to the differential pair unit 110. A second terminal of the differential pair unit 110 serves as the first input terminal of the error amplification module 11 and is connected to the feedback terminal FB. A third terminal of the differential pair unit 110 serves as the second input terminal of the error amplification module 11 and is connected to the first reference voltage Vref1. A fourth terminal of the differential pair unit 110 is connected to the first current source 112, and a resistor unit 111 is connected between the fifth terminal of the differential pair unit 110 and ground. The differential pair unit 110 is configured to amplify the input differential signal.

[0051] In the structure shown in FIG3 , the voltage clamping module 12 includes a first transistor M1. The differential pair unit 110 includes a second transistor M2 and a third transistor M3. The resistor unit 111 includes a first resistor R1. The first current source 112 includes a fourth transistor M4. The fourth transistor M4, the fifth transistor M5, the first transistor M1, and the sixth transistor M6 are sequentially connected in series between ground and the power supply VP+. The bias voltage providing module 113 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. The seventh transistor M7, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 are sequentially connected in series between the power supply VP+ and ground.

[0052] Optionally, the gate of the second transistor M2 serves as the second terminal of the differential pair unit 110, the first electrode of the second transistor M2 serves as the first terminal of the differential pair unit 110, and the second electrode of the second transistor M2 serves as the fifth terminal of the differential pair unit 110. The gate of the third transistor M3 serves as the third terminal of the differential pair unit 110, the first electrode of the third transistor M3 is connected to the first electrode of the second transistor M2, and the second electrode of the third transistor M3 serves as the fourth terminal of the differential pair unit 110. The first resistor R1 is connected between the second electrode of the second transistor M2 and ground.

[0053] The gate of the fourth transistor M4 is connected to a fixed first bias voltage Vb1. The gate of the fourth transistor M4 serves as the control terminal of the first current source 112. The first electrode of the fourth transistor M4 is connected to the second electrode of the fifth transistor M5, and the second electrode of the fourth transistor M4 is grounded. The gate of the fifth transistor M5 is connected to a fixed second bias voltage Vb2. The first electrode of the fifth transistor M5 is connected to the second electrode of the first transistor M1. The second electrode of the first transistor M1 serves as the input terminal of the voltage clamping module 12. The first electrode of the first transistor M1 serves as the output terminal of the voltage clamping module 12 and is connected to the first input terminal O1 of the output module 13. The gate of the first transistor M1 serves as the control terminal of the voltage clamping module 12. The second electrode of the sixth transistor M6 is connected to the first electrode of the first transistor M1, and the first electrode of the sixth transistor M6 is connected to the power supply VP+.

[0054] The bias voltage providing module 113 is connected to the control terminal of the first current source 112 , namely the gate of the fourth transistor M4 , the gate of the first transistor M1 and the gate of the sixth transistor M6 , and is used to provide bias voltage for the first transistor M1 and the sixth transistor M6 .

[0055] The gate of the seventh transistor M7 of the bias voltage providing module 113 is connected to the gate of the sixth transistor M6 and the second electrode of the seventh transistor M7, respectively. The first electrode of the seventh transistor M7 is connected to the power supply VP+, and the second electrode of the seventh transistor M7 is connected to the first electrode of the eighth transistor M8. The gate of the eighth transistor M8 is connected to the second electrode of the eighth transistor M8. The gate of the ninth transistor M9 is connected to the gate of the first transistor M1 and the second electrode of the ninth transistor M9, respectively. The first electrode of the ninth transistor M9 is connected to the second electrode of the eighth transistor M8, and the second electrode of the ninth transistor M9 is connected to the first electrode of the tenth transistor M10. The gate of the tenth transistor M10 is connected to the gate of the fourth transistor M4, and the second electrode of the tenth transistor M10 is connected to ground.

[0056] For example, in the circuit structure shown in FIG3 , the first transistor M1, the second transistor M2, the third transistor M3, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 are all PMOS transistors, and the fourth transistor M4, the fifth transistor M5, and the tenth transistor M10 are NMOS transistors. The first electrode of the first transistor M1, the second transistor M2, the third transistor M3, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 are source electrodes and drain electrodes, respectively. The first electrode of the fourth transistor M4, the fifth transistor M5, and the tenth transistor M10 are drain electrodes and source electrodes, respectively.

[0057] In the circuit shown in Figure 3, the fourth transistor M4 and the fifth transistor M5 have a cascode structure. The fourth transistor M4 is a common-source transistor, whose second electrode, i.e., source, is grounded at a constant voltage, and its gate is connected to a fixed first bias voltage Vb1. The fifth transistor M5 is a common-gate transistor, whose gate is connected to a fixed second bias voltage Vb2. Neither the source voltage nor the gate voltage of the fourth transistor M4 changes, and the current I flowing through the fourth transistor M4 remains constant. The fourth transistor M4 acts as a stable first current source 112. The current flowing from the power supply VP+ through the fourth transistor M4 to ground is divided into two branches. The first branch is composed of the sixth transistor M6, the first transistor M1, and the fifth transistor M5, and the current in the first branch is I1. The second branch is composed of the third transistor M3, and the current in the second branch is I2.

[0058] The tenth transistor M10 and the fourth transistor M4 form a current mirror circuit. The current of the tenth transistor M10 matches the current of the fourth transistor M4. Current matching means that the channel of the tenth transistor M10 and the channel of the fourth transistor M4 can be set to have a proportional relationship. The current flowing through the tenth transistor M10 can be a proportionally amplified or reduced current of the fourth transistor M4, or the current flowing through the tenth transistor M10 can be set to be consistent with the current of the fourth transistor M4. When the current of the fourth transistor M4 remains unchanged, the current of the tenth transistor M10 is also stable.

[0059] The seventh transistor M7, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 of the bias voltage providing module 113 are sequentially connected in series between the power supply VP+ and the ground. The current flowing through the bias voltage providing module 113 is stable and constant, providing a fixed voltage to the gate of the first transistor M1, that is, the gate voltage Vg of the first transistor M1 remains unchanged. During the operation of the low-voltage linear regulator 30, the bias voltage providing module 113 controls the first transistor M1 to be always turned on and operate stably. Optionally, in the circuit shown in Figure 3, the first transistor M1 is a PMOS transistor. According to the condition for the PMOS transistor to be turned on, Vs-Vg≥Vth, that is, the source voltage Vs of the first transistor M1 is higher than the gate voltage Vg, and is at least higher than the threshold voltage value of the first transistor M1. When the voltage at the first input terminal O1, i.e., the source of the first transistor M1, changes, the gate voltage of the first transistor M1 remains unchanged at Vg, and the source voltage Vs1 of the first transistor M1 increases or decreases to Vs2. The absolute value of the increased or decreased source voltage Vs2 is still greater than the threshold voltage Vth, so the value of the voltage change ΔV is very small and generally does not exceed the threshold voltage of the first transistor M1, resulting in a voltage change with a small amplitude.

[0060] In the structure shown in FIG3 , the clamping signal receiving module of the output module 13 includes an eleventh transistor MB1, the amplified signal receiving module includes a twelfth transistor MB2, and the feedback module includes a feedback resistor RF. Both the eleventh transistor MB1 and the twelfth transistor MB2 are PMOS transistors. A first input terminal O1 is connected to the gate of the eleventh transistor MB1, a second input terminal O2 is connected to the gate of the twelfth transistor MB2, and a feedback terminal FB of the feedback resistor RF is connected to the gate of the second transistor M2.

[0061] In conjunction with FIG1 , FIG2 and FIG3 , the working process of the dynamic current and voltage limiting buffer circuit and the low-voltage linear regulator provided by the embodiment shown in FIG3 is as follows:

[0062] When the load current IL of the low-voltage linear regulator 30 changes from light load to heavy load, in the first time period T1 shown in FIG2 , the voltage of the output terminal OUT drops rapidly and is fed back to the first input terminal of the operational amplifier module 10. The voltage of the second input terminal O2 of the dynamic current and voltage limiting buffer circuit 20 decreases accordingly. The twelfth transistor MB2 is in the on state and pulls down the potential of the output terminal PG, thereby increasing the ability of the power transistor MP to supply output current. The dynamic current I flowing through the twelfth transistor MB2 is d The current I2 flowing through the third transistor M3 increases instantaneously, that is, the current I2 on the second branch increases; correspondingly, the current I1 on the first branch decreases instantaneously.

[0063] On the first branch, at this time, the fifth transistor M5 operates in the saturation region, and the magnitude of the current flowing through the first branch is determined by the fifth transistor M5, and the source voltage Vs of the fifth transistor M5 increases; the first transistor M1 and the sixth transistor M6 operate in the linear region, and the source voltage Vs of the first transistor M1, that is, the voltage of the first output terminal O1, increases slightly, controlling the eleventh transistor MB1 to be temporarily turned off. This slightly increased voltage signal serves as the first clamping signal.

[0064] The voltage rise at the source of the first transistor M1 is small, so the eleventh transistor MB1 can be controlled to be turned off. When the eleventh transistor MB1 needs to be turned on again, the first output terminal O1 does not need to be discharged for a long time to lower the potential to reach the turn-on voltage of the eleventh transistor MB1.

[0065] After the eleventh transistor MB1 is turned off, the output terminal PG is no longer charged. Only the twelfth transistor MB2 discharges the output terminal PG. The potential of the output terminal PG can be rapidly reduced, and the ability of the driving transistor MP to provide a large current is quickly enhanced.

[0066] As the potential of the output terminal PG gradually decreases, the current flowing through the twelfth transistor MB2 decreases, the feedback voltage of the feedback terminal FB decreases and is fed back to the non-inverting input terminal of the error amplifier 11, controlling the second transistor M2 to be turned on, and the second branch current I2 where the third transistor M3 is located decreases instantaneously; correspondingly, the first branch current I1 where the sixth transistor M6, the first transistor M1, and the fifth transistor M5 are located increases.

[0067] At this point, in the first branch, the fifth transistor M5 operates in the saturation region, with its gate voltage unchanged and its source voltage Vs decreasing. The first and sixth transistors M1 and M6 operate in the linear region, and the source voltage Vs of the first transistor M1, and therefore the voltage at the first output terminal O1, decreases slightly, controlling the eleventh transistor MB1 to resume conduction. This slightly decreased voltage signal serves as the second clamping signal. The eleventh transistor MB1 pulls up the potential of the output terminal PG, preventing it from further decreasing and gradually returning to a stable operating state. Because the voltage increase at the first output terminal O1 was minimal during the previous period, the first output terminal O1 can quickly drop to the turn-on voltage of the eleventh transistor MB1, controlling the eleventh transistor MB1 to turn on and charge the output terminal PG, thereby pulling up the potential of the output terminal PG. This weakens the ability of the output terminal PG to control the power transistor MP to output high current, clamping the increasing current at the output terminal of the power transistor MP and quickly restoring the circuit to a stable operating state.

[0068] That is, after the first time period T1 , the low voltage linear regulator 30 recovers from the sudden change of the load from light to heavy to a normal and stable working state.

[0069] When the load current IL of the low voltage linear regulator 30 changes from heavy load to light load, such as in the second time period T2, the heavy load is suddenly released, the output current IL becomes low instantly, and the output voltage V OUT The voltage V at the second input terminal O2 increases instantaneously and is fed back to the non-inverting input terminal of the operational amplifier module 10. The voltage V at the second input terminal O2 also increases instantaneously, turning off the twelfth transistor MB2 and no longer pulling down the potential of the output terminal PG. At this time, the eleventh transistor MB1 is still on, charging the output terminal PG and pulling up the potential of the output terminal PG, reducing the ability of the output terminal PG to drive the power transistor MP to provide high current. As the current flowing through the twelfth transistor MB2 decreases, the voltage at the feedback terminal FB drops and is fed back to the gate of the second transistor M2, keeping it on. The second branch current I2 remains unchanged, and correspondingly, the first branch current I1 remains unchanged. The voltage at the first input terminal O1 remains unchanged, maintaining the charging state of the output terminal PG by the eleventh transistor MB1. That is, at this time, the third clamping signal provided by the first transistor M1 to the first input terminal O1 is a signal that keeps the eleventh transistor MB1 on.

[0070] As the eleventh transistor MB1 charges the output terminal PG, until the difference between the output terminal PG, that is, the source potential of the twelfth transistor MB2, and its gate potential, that is, the potential of the second input terminal O2, is greater than the threshold voltage of the twelfth transistor MB2, the twelfth transistor MB2 is turned on, and the eleventh transistor MB1 and the twelfth transistor MB2 are both in the on state, and the circuit quickly returns to a stable working state.

[0071] That is, after the second time period T2, the potential of the output terminal PG gradually recovers, and the low-voltage linear regulator 30 can quickly recover to a normal and stable working state after the sudden change of the load from heavy load to light load, and smoothly perform the light load working state.

[0072] In a stable operating state, the eleventh transistor MB1 and the twelfth transistor MB2 are both in the on state, the current flowing through the twelfth transistor MB2 is a stable operating current, and the voltage at the feedback terminal FB keeps the second transistor M2 in the on state; only when the external load suddenly changes and the current flowing through the twelfth transistor MB2 suddenly increases, the feedback voltage will control the second transistor MB2 to be turned off.

[0073] Please refer to Figure 4, which is a schematic diagram of a buffer circuit that does not include a voltage clamping module. In the first branch circuit where the first input terminal O1 is located, there is no control measure for the voltage change at the first input terminal O1, that is, the gate voltage of the eleventh transistor MB1. Therefore, the eleventh transistor MB1 turns on very slowly. For example, when the voltage at the output terminal OUT drops momentarily, the second input terminal O2 controls the twelfth transistor MB2 to turn on, discharging the output terminal PG. The current flowing through the twelfth transistor MB2 increases, and the increased voltage at the feedback terminal turns off the second transistor M2. The current in the third transistor M3 increases momentarily, and the first input terminal O1 is connected to the output terminal of the third transistor M3. The first input terminal O1 also increases momentarily, controlling the eleventh transistor MB1 to turn off. At this time, the potential of the first input terminal O1 is very high, close to the power supply voltage. As the twelfth transistor MB2 discharges the output terminal PG, the potential of the output terminal PG gradually decreases, the voltage at the feedback terminal FB decreases, and the second transistor M2 is controlled to be turned on, thereby reducing the instantaneous current flowing through the third transistor M3. The potential of the first input terminal O1 gradually decreases due to the pull-down of the fourth transistor M4. When the potential of the first input terminal O1 drops to a level that controls the turn-on of the eleventh transistor MB1, the eleventh transistor MB1 begins to pull up the potential of the output terminal PG. However, because the potential of the first input terminal O1 begins to drop from a very high state, it takes a long time for the eleventh transistor MB1 to complete charging of the output terminal PG. Therefore, during the long charging time, the output terminal PG still controls the power transistor MP to output a large current, and the circuit takes a long time to stabilize.

[0074] By comparison, referring to FIG3 , in an embodiment of the present application, the buffer circuit includes a voltage clamping module 12. When the potential of the first input terminal O1 increases to control the disconnection of the eleventh transistor MB1, the voltage increase amplitude is controlled not to exceed the threshold voltage value of the first transistor M1. When it is necessary to lower the potential of the first input terminal O1 to control the conduction of the eleventh transistor MB1, the potential of the first input terminal O1 can be quickly reduced to the turn-on voltage of the eleventh transistor MB1, thereby quickly raising the potential of the output terminal PG and controlling the output current of the power tube MP to quickly return to a stable state, thereby significantly shortening the circuit stabilization time.

[0075] FIG5 is a schematic diagram of the structure of another dynamic current and voltage limiting buffer circuit provided in an embodiment of the present application. Referring to FIG5 , the error amplification module 11 adopts a fully folded operational amplifier structure. The error amplification module 11 includes a differential pair unit 110, a first current source 122, a fifth transistor M5, a sixth transistor M6, and a bias voltage providing module 113; a first end of the tail current source IS is connected to the power supply voltage VP+, and a second end of the tail current source IS is connected to the first end of the differential pair unit 110, configured to provide a tail current to the differential pair unit 110; a second end of the differential pair unit 110 serves as the first input end (non-inverting input end) of the error amplification module 11, a third end of the differential pair unit 110 serves as the second input end (inverting input end) of the error amplification module 11, a fourth end of the differential pair unit 110 is connected to the first current source 112, and a fifth end of the differential pair unit 110 is connected to the bias voltage providing module 113.

[0076] The first current source 112, the fifth transistor M5, the voltage clamping module 12, and the sixth transistor M6 are sequentially connected in series between ground and the power supply VP+. The bias voltage providing module 113 is respectively connected to the control terminal of the first current source 112, the control terminal of the fifth transistor M5, the control terminal of the voltage clamping module 12, and the control terminal of the sixth transistor M6. The bias voltage providing module 113 is configured to provide a fixed bias voltage.

[0077] The differential pair unit 110 includes a second transistor M2 and a third transistor M3, the first current source 112 includes a fourth transistor M4, and the voltage clamping module 12 includes a first transistor M1. The similarities between the structure shown in FIG5 and FIG3 are not repeated here, and the differences are described below.

[0078] Optionally, the second electrode of the second transistor M2 serves as the fifth terminal of the differential pair unit 110 and is connected to the bias voltage providing module 113. When the output voltage decreases and the second output terminal O2 is controlled to turn on the twelfth transistor MB2 to discharge the output terminal PG, the voltage at the feedback terminal FB increases, controlling the second transistor M2 to turn off. The current flowing through the second transistor M2 decreases and is transmitted to the bias voltage providing module 113 including the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9. Because the bias voltage providing module 113 outputs a fixed bias voltage, a change in the current of the second transistor M2 does not affect a change in the voltage or current of the bias voltage providing module 113. Similarly, when the output voltage decreases or increases and the second output terminal O2 is controlled to turn off the twelfth transistor MB2, the voltage at the feedback terminal FB decreases, controlling the second transistor M2 to turn on, and the current flowing through the second transistor M2 increases, a change in the current of the second transistor M2 also does not affect the fixed bias voltage output by the bias voltage providing module 113. In FIG3 , the second electrode of the second transistor M2 is grounded to eliminate the influence of the current change of the second transistor M2 on the circuit. In FIG5 , the second electrode of the second transistor M2 is connected to the bias voltage providing module 113 , and the effect is basically the same.

[0079] Optionally, the gate of the fifth transistor M5 is connected to the gate of the ninth transistor M9 to provide a voltage for the gate of the fifth transistor M5 . No additional bias voltage providing circuit is needed to provide a bias voltage for the fifth transistor M5 , thereby simplifying the circuit structure.

[0080] FIG6 is a schematic diagram of the structure of another dynamic current-limiting and voltage-limiting buffer circuit provided in an embodiment of the present application. This circuit differs from FIG5 in that the control terminal of the voltage clamping module 12 in FIG6 is connected to a third bias voltage Vb3. This third bias voltage Vb3 is provided by a newly added bias voltage supply circuit and can be set to any value as required.

[0081] The present application also provides a display panel. FIG7 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application. Referring to FIG7 , the display panel 1 includes a dynamic current-limiting and voltage-limiting buffer circuit and a low-voltage linear regulator according to any of the above embodiments. The display panel 1 is a silicon-based OLED microdisplay panel.

[0082] An embodiment of the present application further provides a near-eye display device. FIG8 is a structural schematic diagram of a near-eye display device provided in an embodiment of the present application. Referring to FIG8 , the near-eye display device 2 includes the above-mentioned silicon-based display panel.

Claims

1. A buffer circuit, comprising: An error amplification module, a voltage clamping module and an output module, wherein the output module includes a clamping signal receiving module, an amplified signal receiving module and a feedback module; The first input end of the error amplification module is connected to the feedback module, the second input end of the error amplification module is connected to the first reference voltage, the output end of the error amplification module is connected to the input end of the voltage clamping module, and the output end of the voltage clamping module is connected to the clamping signal receiving module; the clamping signal receiving module and the amplified signal receiving module are commonly connected to the output end of the output module; The amplified signal receiving module is configured to receive a first amplified signal and operate under the control of the first amplified signal; The error amplification module is configured to compare the feedback voltage of the feedback module with the first reference voltage and generate a second amplified signal, and the voltage clamping module is configured to generate a clamping signal under the action of the second amplified signal; The clamping signal receiving module is configured to operate under the control of the clamping signal; The amplified signal receiving module and the clamped signal receiving module jointly control the voltage of the output end of the output module.

2. The buffer circuit according to claim 1, wherein: The voltage clamping module comprises a first transistor, the gate voltage of the first transistor is fixed, and the first electrode of the first transistor serves as the output end of the voltage clamping module and is connected to the control end of the clamping signal receiving module.

3. The buffer circuit according to claim 1, wherein: The error amplification module includes a single-side differential pair folded operational amplifier or a complete folded operational amplifier.

4. The buffer circuit according to claim 1, wherein: The error amplification module includes a differential pair unit, a first current source, a bias voltage providing module, a fifth transistor and a sixth transistor; The first end of the differential pair unit is connected to a power supply or ground, and the second end of the differential pair unit is connected to a power supply or ground. The first input terminal of the error amplification module is used as the third terminal of the differential pair unit as the second input terminal of the error amplification module, the fourth terminal of the differential pair unit is connected to the first current source, the fifth terminal of the differential pair unit is connected to the fixed potential terminal, and the differential pair unit is configured to amplify the input differential signal; The first current source, the fifth transistor, the voltage clamping module, and the sixth transistor are sequentially connected in series between the ground and the power supply, the gate voltage of the fifth transistor is fixed, and the gate voltage of the sixth transistor is fixed; The bias voltage providing module is connected to the control end of the first current source; the bias voltage providing module is also connected to at least one of the control end of the voltage clamping module, the gate of the fifth transistor, and the gate of the sixth transistor.

5. The buffer circuit according to claim 4, wherein: The differential pair unit includes a second transistor and a third transistor, and the first current source includes a fourth transistor; The gate of the second transistor serves as the first input terminal of the error amplification module, the first electrode of the second transistor is connected to the power supply or grounded, and the second electrode of the second transistor is connected to the fixed potential terminal; The gate of the third transistor serves as the second input terminal of the error amplification module, the first electrode of the third transistor is connected to the first electrode of the second transistor, and the second electrode of the third transistor is connected to the first current source. The gate of the fourth transistor is connected to the first bias voltage, the gate of the fourth transistor serves as the control end of the first current source, the first electrode of the fourth transistor is connected to the second electrode of the third transistor and the second electrode of the fifth transistor, and the second electrode of the fourth transistor is grounded or connected to the power supply.

6. The buffer circuit according to claim 4, wherein: The fifth terminal of the differential pair unit is grounded or connected to the bias voltage providing module.

7. The buffer circuit according to claim 4, wherein: The error amplification module further includes a tail current source and a resistance unit; the tail current source is connected to the first end of the differential pair unit, and the resistance unit is connected to the fifth end of the differential pair unit.

8. The buffer circuit according to claim 5, wherein: The feedback voltage change controls the opening or closing of the second transistor to affect the second current change flowing through the third transistor. The second current change affects the first current change flowing through the fifth transistor, the voltage clamping module, and the sixth transistor. The first current change corresponds to the output terminal voltage of the voltage clamping module. The output terminal voltage of the voltage clamping module is the clamping signal.

9. The buffer circuit according to claim 5, wherein: The bias voltage providing module includes a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor, wherein the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistor are sequentially connected between the power supply and the ground; the gate of the tenth transistor is connected to the first bias voltage, and the second electrode of the tenth transistor is connected to the second electrode of the fourth transistor; or, The bias voltage providing module includes a seventh transistor, a ninth transistor and a tenth transistor, and the seventh transistor, the ninth transistor and the tenth transistor are connected between the power supply and the ground in sequence; the gate of the tenth transistor is connected to the first bias voltage, and the second electrode of the tenth transistor is connected to the second electrode of the fourth transistor.

10. The buffer circuit according to claim 1, wherein: The clamping signal receiving module includes an eleventh transistor, the amplified signal receiving module includes a twelfth transistor, and the feedback module includes a feedback resistor; The gate of the eleventh transistor is configured to receive the clamping signal, and the gate of the twelfth transistor is configured to receive the first amplified signal; the second electrode of the eleventh transistor and the first electrode of the twelfth transistor serve as output terminals of the output module; The feedback resistor is connected to the second electrode of the twelfth transistor and the first input terminal of the error amplification module.

11. A linear regulator, comprising the buffer circuit according to any one of claims 1 to 10; The linear voltage regulator also includes an operational amplifier module and a power tube; The first input end of the operational amplifier module is connected to the output end of the linear regulator, the second input end of the operational amplifier module is connected to the second reference voltage, the output end of the operational amplifier module is connected to the amplified signal receiving module of the buffer circuit, and is configured to provide the first amplified signal; The gate of the power tube is connected to the output end of the buffer circuit, the first pole of the power tube serves as the output end of the linear regulator, and the second pole of the power tube is connected to a power supply.

12. The linear regulator according to claim 11, wherein: The voltage clamping module is configured to provide the clamping signal when the load current changes, control the output module to output a set of dynamic voltages, and clamp the current range output by the linear regulator.

13. The linear regulator according to claim 11, wherein: When the load current of the linear regulator changes, the output voltage of the linear regulator changes and the voltage change is fed back to the first input terminal of the operational amplifier module, and the operational amplifier module generates the first amplified signal and provides it to the amplified signal receiving module to control the current of the amplified signal receiving module; The feedback module converts the current change of the amplified signal receiving module into a voltage change and feeds back the voltage change to the first input terminal of the error amplification module, and the error amplification module outputs the second amplified signal to the voltage clamping module according to the voltage change; The voltage clamping module outputs the clamping signal to the clamping signal receiving module according to the second amplified signal and controls the working state of the clamping signal receiving module; The clamping signal receiving module and the amplified signal receiving module jointly control the gate of the power tube. Pole potential.

14. The linear regulator according to claim 11, wherein: The load current changes include changes from light load to heavy load, and changes from heavy load to light load.

15. The linear regulator according to claim 14, wherein: When the load current changes from light load to heavy load, the clamping signal receiving module and the amplifying signal receiving module jointly control the gate potential of the power tube to enhance the driving capability of the power tube, so that the power tube outputs a larger current to meet the operation of the external circuit; The clamping signal receiving module and the amplified signal receiving module then jointly control the gate potential of the power tube, suppressing the trend of the driving capability of the power tube to increase, so that the power tube quickly enters a stable heavy-load working state.

16. The linear regulator according to claim 14, wherein: When the load current changes from heavy load to light load, the clamping signal receiving module and the amplifying signal receiving module jointly control the gate potential of the power tube to weaken the driving capability of the power tube, so that the power tube reduces the output current corresponding to the light load state; The clamping signal receiving module and the amplified signal receiving module then jointly control the gate potential of the power tube, suppressing the trend of weakening driving capability of the power tube, so that the power tube quickly enters a stable light-load working state.

17. A display panel comprising the linear regulator according to any one of claims 11 to 16.

18. The display panel according to claim 17, wherein: The display panel is a silicon-based organic light-emitting diode (OLED) micro display panel.

19. A near-eye display device, comprising the silicon-based OLED micro display panel according to claim 18.

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