Array substrate, display panel and display apparatus

Abstract

Provided are an array substrate, a display panel and a display apparatus. The array substrate comprises a base substrate (101), the base substrate (101) comprising a display area (AA) and a non-display area (BB) on at least one side of the display area; a gate driving circuit (GOA) arranged in the non-display area (BB) and comprising a plurality of cascaded shift registers; a gate driving circuit signal line (102), the gate driving circuit signal line (102) being coupled to at least one stage of shift register, and the gate driving circuit signal line (102) comprising a first main line part (1021) and a first winding part (1022) which are integrally arranged; and a constant-voltage signal line (103), the constant-voltage signal line (103) comprising a second main line part (1031) and a second winding part (1032), the second main line part (1031) and the first main line part (1021) at least partially overlapping in a direction (Z) perpendicular to the base substrate (101) to form a first capacitor (C1), the second winding part (1032) and the first winding part (1022) forming at least one second capacitor (C2), the area of the orthographic projection of the second capacitor (C2) on the base substrate (101) being less than the area of the orthographic projection of the first capacitor (C1) on the base substrate (101), and at least part of the first winding part (1022) and / or at least part of the second winding part (1032) extending from an area where the first capacitor (C1) is located to an area where the second capacitor (C2) is located.

Description

Array substrate, display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] Thin Film Transistor Liquid Crystal Displays (TFT-LCDs) feature compact size, low power consumption, high image quality, zero radiation, and portability. They have experienced rapid development in recent years, gradually replacing traditional cathode ray tube (CRT) displays and dominating the current flat-panel display market. Currently, TFT-LCDs are widely used in a variety of large, medium, and small-sized products, encompassing nearly every major electronic product in today's information society, including LCD TVs, high-definition digital TVs, computers (desktop and laptop), mobile phones, tablets, navigation systems, in-car displays, projection displays, camcorders, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays.

[0003] Summary of the Invention

[0004] The present disclosure provides an array substrate, a display panel, and a display device. The specific solutions are as follows:

[0005] In one aspect, an embodiment of the present disclosure provides an array substrate, comprising:

[0006] a base substrate, the base substrate comprising a display area and a non-display area located on at least one side of the display area;

[0007] a gate driving circuit, located in the non-display area, the gate driving circuit comprising a plurality of shift registers arranged in cascade;

[0008] a gate drive circuit signal line located in the non-display area, the gate drive circuit signal line being electrically connected to at least one stage of the shift register, the gate drive circuit signal line comprising an integrally arranged first main line portion and a first winding portion;

[0009] A constant voltage signal line is located in the non-display area, and the constant voltage signal line includes a second main line portion and a second winding portion, wherein the second main line portion and the first main line portion at least partially overlap in a direction perpendicular to the base substrate to form a first capacitor, and the second winding portion and the first winding portion form at least one second capacitor, the orthographic projection area of ​​the second capacitor on the base substrate is smaller than the orthographic projection area of ​​the first capacitor on the base substrate, and at least a portion of the first winding portion and / or at least a portion of the second winding portion extends from the area where the first capacitor is located to the area where the second capacitor is located.

[0010] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the first winding portion and the second winding portion overlap with each other in a direction perpendicular to the base substrate to form the second capacitor.

[0011] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, one of the first winding portion and the second winding portion includes a plurality of protrusions, and the plurality of protrusions overlap with the other of the first winding portion and the second winding portion in a direction perpendicular to the base substrate to form a plurality of second capacitors.

[0012] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the winding lengths of the first winding portion on both sides of the area where the second capacitor is located are approximately the same, and the winding lengths of the second winding portion on both sides of the area where the second capacitor is located are approximately the same.

[0013] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the first winding portion includes a first winding repeating unit, the second winding portion includes a second winding repeating unit, and the first winding repeating unit and the second winding repeating unit are alternately arranged on both sides of the area where the second capacitor is located.

[0014] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the gate drive circuit signal line further includes a first connecting portion located on one side of the first winding portion, the first connecting portion being connected to the first main line portion and connected to both ends of the first winding portion;

[0015] The constant voltage signal line also includes a second connecting portion, which is connected to the second main line portion and to both ends of the second winding portion respectively, and the orthographic projection of the second connecting portion on the base substrate is located on a side away from the orthographic projection of the first winding portion on the base substrate.

[0016] In some embodiments, in the array substrate provided by an embodiment of the present disclosure, the gate drive circuit signal line further includes a first overlapping portion connected between the first connecting portion and an end of the first winding portion close to the first main line portion;

[0017] The constant voltage signal line also includes a second overlapping portion, which is connected between the second connecting portion and the end of the second winding portion close to the second main line portion, and the second overlapping portion and the first overlapping portion overlap with each other in a direction perpendicular to the base substrate to form a third capacitor, and the orthographic projection area of ​​the third capacitor on the base substrate is larger than the orthographic projection area of ​​the second capacitor on the base substrate.

[0018] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the line width of the first overlapping portion is greater than the line width of the first winding portion, and the line width of the second overlapping portion is greater than the line width of the second winding portion outside the second capacitor.

[0019] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the first winding portion includes a plurality of first sub-winding portions and at least one straight portion, the first sub-winding portion has a notch on a side facing the first main portion, the plurality of first sub-winding portions are sequentially arranged around an end of the first winding portion, and the straight portion is connected to at least two of the first sub-winding portions adjacent to the end of the first winding portion;

[0020] The second winding portion includes a plurality of second sub-winding portions, each of which has a notch on a side facing the second main line portion. The plurality of second sub-winding portions are arranged in sequence around the end of the second winding portion, and the orthographic projections of the second sub-winding portions on the substrate and the orthographic projections of the first sub-winding portions on the substrate are alternately arranged. At least part of the second sub-winding portions overlaps with the straight line portion in a direction perpendicular to the substrate to form the second capacitor.

[0021] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, the first winding portion includes a plurality of first protrusions, and the second winding portion includes a plurality of second protrusions, and the first protrusions and the second protrusions overlap in a direction perpendicular to the base substrate to form the second capacitor.

[0022] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the second main line portion and the second winding portion are integrally provided.

[0023] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the shift register includes a transistor, and the constant voltage signal line is provided in the same layer as the gate of the transistor.

[0024] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, the first winding portion and the second winding portion are arranged on the same layer, the first winding portion includes a plurality of first protrusions, the second winding portion includes a plurality of second protrusions, and the first protrusions and the second protrusions are arranged opposite to each other to form the second capacitor.

[0025] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the second winding portion is grounded.

[0026] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, a distance between the first protrusion and the second protrusion that are opposite to each other is greater than or equal to 8 μm and less than or equal to 15 μm.

[0027] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the size of the first protrusion is greater than or equal to 4 μm and less than or equal to 7 μm, and the size of the second protrusion is substantially the same as that of the first protrusion.

[0028] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, in addition to the multiple second capacitors, the orthographic projection of the first winding portion on the base substrate and the orthographic projection of the second winding portion on the base substrate are symmetrically arranged with respect to the arrangement direction of the multiple second capacitors.

[0029] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a common electrode located in the display area, and the second main line portion is provided in the same layer as the common electrode.

[0030] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the second main line portion carries a common electrode signal.

[0031] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the shift register includes a transistor, and the gate drive circuit signal line is provided on the same layer as the source / drain of the transistor.

[0032] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the gate drive circuit signal line includes an initial trigger signal line.

[0033] On the other hand, an embodiment of the present disclosure provides a display panel, including an array substrate and an opposite substrate arranged opposite to each other, wherein the array substrate is the above-mentioned array substrate provided in the embodiment of the present disclosure.

[0034] On the other hand, an embodiment of the present disclosure provides a display device, including the above-mentioned display panel provided by an embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] FIG1 is a diagram showing a reset relationship of a gate drive circuit provided by an embodiment of the present disclosure;

[0036] FIG2 is a schematic structural diagram of an array substrate provided in an embodiment of the present disclosure;

[0037] FIG3 is a schematic diagram of an enlarged structure of the M0 region in FIG2 ;

[0038] FIG4 is a schematic diagram of an enlarged structure of the M2 region in FIG3 ;

[0039] FIG5 is another enlarged structural diagram of the M0 region in FIG2 ;

[0040] FIG6 is another enlarged structural diagram of the M0 region in FIG2 ;

[0041] FIG7 is another enlarged structural diagram of the M0 region in FIG2 ;

[0042] FIG8 is another enlarged structural diagram of the M0 region in FIG2 ;

[0043] FIG9 is another enlarged structural diagram of the M2 region in FIG3 ;

[0044] FIG10 is another enlarged structural diagram of the M2 region in FIG3 ;

[0045] FIG11 is a schematic diagram of the cross-sectional structure along line I-II in FIG10 ;

[0046] FIG12 is another enlarged structural diagram of the M2 region in FIG3 ;

[0047] FIG13 is a schematic diagram of the cross-sectional structure along line III-IV in FIG12;

[0048] FIG14 is a schematic diagram of an enlarged structure of the M1 region in FIG2 ;

[0049] FIG15 is an enlarged structural diagram of the M3 region in FIG14 ;

[0050] FIG16 is another enlarged structural diagram of the M1 region in FIG2 ;

[0051] FIG17 is an enlarged structural diagram of the M4 region in FIG16 ;

[0052] FIG18 is an enlarged structural diagram of the M5 region in FIG17 ;

[0053] FIG19 is another enlarged structural diagram of the M1 region in FIG2 ;

[0054] FIG20 is an enlarged structural diagram of the M6 ​​region in FIG19 ;

[0055] FIG21 is a schematic diagram showing the feedback-compensation principle of the common electrode signal;

[0056] FIG22 is a schematic structural diagram of a display panel provided in an embodiment of the present disclosure;

[0057] FIG23 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0058] To further clarify the objectives, technical solutions, and advantages of the embodiments of the present disclosure, the technical solutions of the embodiments of the present disclosure will be described below in conjunction with the accompanying drawings. It should be noted that, to further clarify the objectives, technical solutions, and advantages of the embodiments of the present disclosure, the technical solutions of the embodiments of the present disclosure will be described below in conjunction with the accompanying drawings. It should be noted that in the accompanying drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. Example embodiments are described in this disclosure with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures as a result of, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shapes of the regions shown in this disclosure, but rather include deviations in shape resulting from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features; sharp corners illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their sizes and shapes are not intended to depict the precise shapes of the regions or reflect true scale. They are intended solely to illustrate the present disclosure. The same or similar reference numerals throughout the text represent the same or similar elements or elements having the same or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0059] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar terms used in the present disclosure and the claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0060] In the following description, when an element or layer is referred to as being “on” or “connected to” another element or layer, the element or layer may be directly on, directly connected to, the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as being “disposed on one side of” another element or layer, the element or layer may be directly on, directly connected to, the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as being “directly on” or “directly connected to” another element or layer, there are no intermediate elements or intermediate layers. The term “and / or” includes any and all combinations of one or more of the associated listed items.

[0061] TFT-LCDs are currently the mainstream display device, and their aesthetics directly impact the user experience. As the name suggests, the gate driver on array (GOA) integrates some of the functions of the gate driver IC (Gate IC) in TFT-LCDs onto the array substrate, thereby eliminating the gate driver IC. Thanks to GOA technology, TFT-LCDs achieve high levels of integration, narrow bezels, and low costs.

[0062] GOA signals can be mainly divided into STV (start signal), CLK (clock signal), VDD (DC signal), etc. Through the combination and division of labor of each signal, the gate lines in TFT-LCD are turned on row by row. Among them, STV, as the start signal, often has a large current surge at the beginning of the frame, which can easily cause electrostatic discharge (ESD) of the first few shift registers in GOA.

[0063] Taking the GOA controlled by 8CLK+2STV as an example, as shown in Figure 1, at the beginning of the frame, STV1 serves as the start signal input for the first-stage shift register GOA1 to the fourth-stage shift register GOA4, and GOA starts scanning row by row starting from the first row. When the first-stage shift register GOA1 outputs a signal, it also serves as the start signal input for the fifth-stage shift register GOA5 (the nth row carries the n+4th row, where n is a positive integer). When GOA scans to the 6th row, the output signal of the sixth-stage shift register GOA6 not only carries the tenth-stage shift register GOA10, but also resets the first-stage shift register GOA1 (the mth row resets the m-5th row, where m is an integer greater than or equal to 6). At this point, the operation of the first-stage shift register GOA1 is completed. STV0 resets the shift register between frames (Total Reset, Tr). Therefore, if there is a large instantaneous current in STV, it is easy to cause the first few stages of shift registers to be broken down by static electricity at the beginning of the frame, which in turn leads to accumulation of defects line by line, resulting in abnormal display images.

[0064] To reduce the impact of high currents and prevent electrostatic breakdown of the shift register, an STV signal jumper can be used (for example, the STV signal jumps from the gate layer to the data layer, then back to the gate layer, Gate→SD→Gate) to enter the GOA. However, since these two jumpers require two vias to connect, they can easily cause the vias to burn, corrode, or break down after a period of operation, seriously affecting display quality.

[0065] In order to at least improve the above technical problems existing in the related art, an embodiment of the present disclosure provides an array substrate, as shown in FIG. 2 to FIG. 4 , comprising:

[0066] The base substrate 101 includes a display area AA and a non-display area BB located on at least one side of the display area AA. FIG2 specifically shows that the non-display area BB is arranged around the display area AA. Optionally, the base substrate 101 is a substrate that allows visible light to pass through, such as glass, quartz, plastic, or the like.

[0067] The gate drive circuit GOA is located in the non-display area BB. The gate drive circuit GOA includes a plurality of shift registers arranged in cascade (for example, a first-stage shift register GOA1, a second-stage shift register GOA2, a third-stage shift register GOA3, etc.); in some embodiments, the shift register includes transistors, capacitors, etc., wherein the transistors can be bottom-gate transistors, top-gate transistors, or dual-gate transistors, the transistors can be P-type transistors or N-type transistors, and the active layer material of the transistors can be amorphous silicon (a-Si), polycrystalline silicon (PCS), or silicon monoxide. Silicon (poly), oxide (Oxide, such as indium gallium zinc oxide IGZO), etc.; optionally, a gate insulating layer 104 can be provided between the layer where the gate of the transistor is located and the active layer. The material of the gate insulating layer 104 can be silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), etc. The gate insulating layer 104 can be a single-layer or multi-layer structure. For example, the gate insulating layer 104 includes a stacked silicon nitride layer and a silicon oxide layer.

[0068] The gate drive circuit signal line 102 is located in the non-display area BB. The gate drive circuit signal line 102 is electrically connected to at least one level of shift register. The gate drive circuit signal line 102 includes an integrally arranged first main line portion 1021 and a first winding portion 1022. Optionally, the gate drive circuit signal line 102 includes an initial trigger signal line STV, a frame reset signal line STV0, a ​​first DC signal line VDD (pull-down module power supply signal), a second DC signal line VSS, a first clock signal line CK1, a second clock signal line CK2, etc. The present disclosure uses the gate drive circuit signal line 102 as an example of the initial trigger signal line STV. The gate drive circuit signal line 102 can be set in the same layer and the same material as the source / drain of the transistor. In the present disclosure, "same layer" refers to a layer structure formed by using the same film forming process to form a film layer for making a specific pattern, and then using the same mask template through a single patterning process. That is, one patterning process corresponds to a mask (also called a photomask); depending on the specific pattern, one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may be at the same height or have the same thickness, or at different heights or have different thicknesses.

[0069] The constant voltage signal line 103 is located in the non-display area BB. The constant voltage signal line 103 includes a second main line portion 1031 and a second winding portion 1032, wherein the second main line portion 1031 and the first main line portion 1021 at least partially overlap in a direction Z perpendicular to the base substrate 101 to form a first capacitor C1. The second main line portion 1031 and the first main line portion 1021 are insulated from each other. The second winding portion 1032 and the first winding portion 1022 form at least one second capacitor C2. The orthographic projection area of ​​the second capacitor C2 on the base substrate 101 is smaller than the orthographic projection area of ​​the first capacitor C1 on the base substrate 101, and at least a portion of the first winding portion 1022 and / or at least a portion of the second winding portion 1032 extends from the area where the first capacitor C1 is located to the area where the second capacitor C2 is located.

[0070] In the above-mentioned array substrate provided by the embodiment of the present disclosure, when the STV signal on the gate drive circuit signal line 102 is turned on, the coupling effect of the larger first capacitor C1 can prevent a large instantaneous current impact on the gate drive circuit signal line 102, thereby achieving the purpose of protecting the first few stages of shift registers in the gate drive circuit GOA. Optionally, the present disclosure provides a first winding portion 1022 and a second winding portion 1032 outside the area where the first capacitor C1 is located, and the first winding portion 1022 and the second winding portion 1032 form a smaller second capacitor C2. When the instantaneous current on the gate drive circuit signal line 102 is too large to be pulled down by the first capacitor C1, the large current will flow through the winding between the second capacitor C2 and the first capacitor C1 and break down and discharge at the second capacitor C2, thereby protecting the first few stages of shift registers in the gate drive circuit GOA, thereby ensuring the normal operation of the gate drive circuit GOA.

[0071] Furthermore, since the present disclosure provides that at least a portion of the first winding portion 1022 and / or at least a portion of the second winding portion 1032 extends from the area where the first capacitor C1 is located to the area where the second capacitor C2 is located, it ensures that the smaller second capacitor C2 is farther away from the larger first capacitor C1, and the winding resistance between the second capacitor C2 and the first capacitor C1 is larger. After the second capacitor C2 is broken down, when the signal is working normally, the current will select the normal working circuit with small resistance, and will not flow into the winding area with large resistance to cause the signal on the gate drive circuit signal line 102 and the signal on the constant voltage signal line 103 to interfere with each other. In this way, it is ensured that the normal operation of the product is still not affected after the breakdown.

[0072] From the above, it can be seen that the present disclosure can solve the problem of excessive instantaneous current in the gate drive circuit signal line 102 without jumper processing, effectively avoiding the adverse effects on display image quality caused by via burning / corrosion / breakdown caused by jumper processing.

[0073] 3 and 4 , it can be seen that the anti-static structure composed of the first main line portion 1021, the first winding portion 1022, the second main line portion 1031 and the second winding portion 1032 in the M2 region can be arranged on the same side as the fan-out line FL, so as to be suitable for the case where the shift register GOA scans successively from the first-stage shift register unit GOA1 (i.e., forward scanning); in other embodiments, as shown in FIG5 , the anti-static structure composed of the first main line portion 1021, the first winding portion 1022, the second main line portion 1031 and the second winding portion 1032 in the M2 region can also be arranged on the opposite side of the fan-out line FL. It is set to be suitable for the situation where the shift register GOA is scanned one by one (i.e., reverse scanning) starting from the last-stage shift register unit GOAn; or, as shown in Figure 6, the anti-static structure composed of the first main line portion 1021, the first winding portion 1022, the second main line portion 1031 and the second winding portion 1032 in the M2 area can be set on the same side and different layers of the fan-out line FL at the same time, so as to be suitable for the situation where the shift register GOA is scanned one by one (i.e., forward scanning) starting from the first-stage shift register unit GOA1, and is scanned one by one (i.e., reverse scanning) starting from the last-stage shift register unit GOAn.

[0074] Optionally, as shown in FIG3 , the initial trigger signal line STV, the first DC signal line VDD, the second DC signal line VSS, the first clock signal line CK1, the second clock signal line CK2, and the data line DL can be coupled to the common electrode signal line CL through an electrostatic discharge unit EU, respectively. The anti-static structure formed by the first main line portion 1021, the first winding portion 1022, the second main line portion 1031, and the second winding portion 1032 in the M2 region can be disposed between the initial trigger signal line STV, the first DC signal line VDD, the second DC signal line VSS, the first clock signal line CK1, and the second clock signal line CK2 and the electrostatic discharge unit EU to which they are coupled. Optionally, the common electrode signal line CL in FIG3 is disposed on the same layer and material as the gate of the transistor, and the second main line portion 1031 can be disposed on the same layer and material as the common electrode (com), and the second main line portion 1031 is coupled to the common electrode signal line CL through a via penetrating the insulating layer between the layer where the gate of the transistor is located and the layer where the common electrode (com) is located.

[0075] In some embodiments, as shown in Figures 3, 5 and 6, the anti-static structure in the M2 region can be set on the initial trigger signal line STV; in other embodiments, as shown in Figure 7, the anti-static structure in the M2 region can also be respectively set on the first initial trigger signal line STV1 and the second initial trigger signal line STV2; in other embodiments, as shown in Figure 8, the anti-static structure in the M2 region can also be respectively set on the initial trigger signal line STV and other signal lines (for example, the first DC signal line VDD), which is not limited here.

[0076] In some embodiments, as shown in FIG4 , the first main line portion 1021 and the second main line portion 1031 may be planar structures, and the two overlap to form a first capacitor C1; in other embodiments, as shown in FIG9 , the first main line portion 1021 and the second main line portion 1031 may have mutually overlapping hollow structures HS, and the two overlap outside the hollow structure HS to form the first capacitor C1.

[0077] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, as shown in Figures 4, 9 to 13, the first winding portion 1022 and the second winding portion 1032 can overlap with each other in a direction Z perpendicular to the base substrate 101 to form a second capacitor C2. Optionally, as shown in Figures 4, 9 to 11, the layer where the first winding portion 1022 is located can be located between the layer where the second winding portion 1032 is located (i.e., the layer where the protrusion 1032" is located) and the substrate 101, for example, the first winding portion 1022 is in the same layer and material as the source / drain of the transistor, and the second winding portion 1032 is in the same layer and material as the common electrode (Com) or the pixel electrode; or, as shown in Figures 12 and 13, the layer where the first winding portion 1022 is located can be located on the side of the layer where the second winding portion 1032 is located (i.e., the layer where the protrusion 1032" is located) away from the substrate 101, for example, the first winding portion 1022 is in the same layer and material as the source / drain of the transistor, and the second winding portion 1032 is in the same layer and material as the gate of the transistor. The common electrode (com) or pixel electrode is made of transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), and gallium zinc oxide (GZO). The transistor gate is made of metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni). These metals have lower resistance than the aforementioned transparent conductive materials. Therefore, compared to when the second winding portion 1032 is provided on the same layer and made of the same material as the common electrode (com), the second winding portion 1032 has lower resistance and higher discharge efficiency when provided on the same layer and made of the same material as the transistor gate.

[0078] In some embodiments, the common electrode (com) and the pixel electrode (pixel) can both be arranged on the array substrate, and the layer where the common electrode (com) is located is located on the side of the layer where the pixel electrode (pixel) is located away from the base substrate 101. For example, the pixel electrode (pixel) is located in the first transparent conductive layer on the side of the layer where the source / drain is located away from the base substrate 101, and the common electrode (com) is located in the second transparent conductive layer on the side of the first transparent conductive layer away from the base substrate 101. Optionally, a first insulating layer 105 is provided between the layer where the source / drain is located and the first transparent conductive layer, and a second insulating layer 106 is provided between the first transparent conductive layer and the second transparent conductive layer. The material of the first transparent conductive layer and the second transparent electrode layer can be at least one transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), and gallium zinc oxide (GZO); the material of the first insulating layer 105 can be at least one inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (AlOx), hafnium oxide (HfOx), and tantalum oxide (TaOx); the material of the second insulating layer 106 can be an inorganic insulating material and / or an organic insulating material, wherein the inorganic insulating material includes but is not limited to at least one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (AlOx), hafnium oxide (HfOx), and tantalum oxide (TaOx); the organic insulating material includes but is not limited to at least one of polyacrylic resin, polyepoxy acrylic resin, photosensitive polyimide resin, polyester acrylate, polyurethane acrylate resin, and novolac epoxy acrylic resin.

[0079] It is worth noting that in some embodiments, the thickness of the organic insulating material layer is relatively large, up to This results in a smaller capacitance between the source / drain layer and the second transparent electrode layer and makes breakdown more difficult, making it difficult to achieve the purpose of protection. Therefore, when the second insulating layer 106 includes an organic insulating material layer, in order to ensure that the instantaneous current can smoothly break down and discharge at the second capacitor C2, the present disclosure preferably adopts the solution of setting the second winding portion 1032 at the layer where the gate of the transistor is located as shown in Figures 12 and 13, rather than the solution of setting the second winding portion 1032 at the second transparent electrode layer as shown in Figures 4, 9 to 11.

[0080] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, as shown in Figures 4 and 9, the first winding portion 1022 and the second winding portion 1032 can overlap with each other in a direction Z perpendicular to the base substrate 101 to form a second capacitor C2; or, as shown in Figures 10 and 12, the second winding portion 1032 can be set to include multiple protrusions 1032", and the multiple protrusions 1032" overlap with the first winding portion 1022 in a direction Z perpendicular to the base substrate 101 to form multiple second capacitors C2, so that excessive instantaneous current is broken down and discharged at the multiple second capacitors C2, thereby ensuring high discharge efficiency.

[0081] It should be understood that the present disclosure can also be configured such that the first winding portion 1022 includes a plurality of protrusions, the second winding portion 1032 does not have a plurality of protrusions, and the plurality of protrusions of the first winding portion 1022 overlap with the second winding portion 1032 in a direction Z perpendicular to the base substrate 101 to form a plurality of second capacitors C2. Similarly, excessive instantaneous current can be broken down and discharged at the plurality of second capacitors C2, thereby ensuring a high discharge efficiency.

[0082] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, as shown in Figures 4, 9, 10 and 12, the gate drive circuit signal line 102 may further include a first connecting portion 1023 located on one side of the first winding portion 1022, the first connecting portion 1023 being connected to the first main line portion 1021 and respectively connected to both ends of the first winding portion 1022. Optionally, the first connecting portion 1023, the first main line portion 1021, and the first winding portion 1022 are integrally provided; the constant voltage signal line 1023 is connected to the first main line portion 1021. 3 may further include a second connecting portion 1033, which is connected to the second main line portion 1031 and to both ends of the second winding portion 1032. Optionally, the second connecting portion 1033, the second main line portion 1031, and the second winding portion 1032 are integrally formed, and the orthographic projection of the second connecting portion 1033 on the substrate 101 may be located on a side of the orthographic projection of the first winding portion 1022 on the substrate 101 that is away from the orthographic projection of the first connecting portion 1023 on the substrate 101. This allows a large instantaneous current to be respectively connected to the starting and ending ends of the first winding portion 1022 through the first connecting portion 1023, and to the starting and ending ends of the second winding portion 1032 through the second connecting portion 1033. The current is then transmitted from the starting and ending ends of the first winding portion 1022 and the starting and ending ends of the second winding portion 1032 to the second capacitor C2, thereby increasing the discharge path for the instantaneous current and improving discharge efficiency.

[0083] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in Figures 4, 9, 10, and 12, the first winding portion 1022 can be configured to have substantially the same winding length on both sides of the region where the second capacitor C2 is located, and the second winding portion 1032 can be configured to have substantially the same winding length on both sides of the region where the second capacitor C2 is located. Since a large instantaneous current is transmitted from the beginning and end of the first winding portion 1022 and the beginning and end of the second winding portion 1032 to the second capacitor C2, the present disclosure configures the winding lengths of the first winding portion 1022 on both sides of the second capacitor C2 to be substantially the same, and the winding lengths of the second winding portion 1032 on both sides of the second capacitor C2 to be substantially the same. This allows the second capacitor C2 to be approximately in the middle between the first winding portion 1022 and the second winding portion 1032, ensuring that a large instantaneous current is transmitted to the second capacitor C2 via the longer winding. This reduces the loss of the instantaneous current along the winding path and reduces the impact of the instantaneous current on the first shift register stages in the gate drive circuit GOA, thereby effectively ensuring the normal operation of the gate drive circuit GOA. In addition, after the instantaneous current breaks down at the second capacitor C2, the winding length and resistance on both sides of the area where the second capacitor C2 is located are large, so when the signal is working normally, the current will choose the normal working line with small resistance, and will not flow into the winding area with large resistance, causing the signal on the gate drive circuit signal line 102 and the signal on the constant voltage signal line 103 to interfere with each other. In this way, it is guaranteed to the greatest extent that the normal operation of the product will not be affected after the breakdown.

[0084] It should be noted that in the embodiments provided in the present disclosure, "substantially the same" may be completely identical, or there may be some deviations (for example, a deviation of ±20%). Therefore, as long as the "substantially the same" relationship between related features satisfies the deviation allowance, it falls within the scope of protection of the present disclosure.

[0085] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, as shown in Figures 4, 9, 10 and 12, the first winding portion 1022 includes a first winding repeating unit 1022', the second winding portion 1032 includes a second winding repeating unit 1032', and the first winding repeating unit 1022' and the second winding repeating unit 1032' are alternately arranged on both sides of the area where the second capacitor C2 is located. The first winding portion 1022 and the second winding portion 1032 are both windings arranged in a meandering manner along the first direction X and the second direction Y. The present disclosure ensures that the first winding repeating unit 1022' and the second winding repeating unit 1032' are longer in the first direction X by alternately arranging the first winding repeating unit 1022' and the second winding repeating unit 1032' on both sides of the area where the second capacitor C2 is located, thereby facilitating the realization of longer winding of the first winding portion 1022 and the second winding portion 1032 in a smaller space, ensuring that the resistance of the first winding portion 1022 and the second winding portion 1032 can still be relatively large in a narrow-frame product. Optionally, at least two groups of first winding repeating units 1022' and at least two groups of second winding repeating units 1032' are included on both sides of the second capacitor C2.

[0086] It should be noted that Figures 4, 9, 10 and 12 illustrate that the first winding repeating unit 1022' and the second winding repeating unit 1032' are approximately U-shaped. In other embodiments, the first winding repeating unit 1022' and the second winding repeating unit 1032' may also be other shapes, such as S-shaped, which is not specifically limited here.

[0087] In some embodiments, to ensure that the windings of the first winding portion 1022 and the second winding portion 1032 are longer and have greater resistance within a limited space, thereby minimizing or even eliminating any impact on normal signal transmission, the line widths of the first winding portion 1022 and the second winding portion 1032 can be smaller, and / or the spacing between the two windings in the first winding repeating unit 1022' and the spacing between the two windings in the second winding repeating unit 1032' can be smaller. In some embodiments, the line widths of the first winding portion 1022 and the second winding portion 1032 can be within the process limits of the relevant technology, such as greater than or equal to 4 μm and less than or equal to 5 μm, specifically 4 μm, 4.5 μm, 5 μm, etc.; the spacing between the two windings in the first winding repeating unit 1022' and the spacing between the two windings in the second winding repeating unit 1032' can also be within the process limits, such as greater than or equal to 3 μm and less than or equal to 4 μm, specifically 3 μm, 3.5 μm, 4 μm, etc. It should be understood that with the advancement of process technology, the line width of the first winding portion 1022 and the second winding portion 1032, as well as the spacing between the two windings contained in the first winding repeating unit 1022' and the spacing between the two windings contained in the second winding repeating unit 1032' can be smaller than the above values.

[0088] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in Figures 4, 9, 10 and 12, the gate drive circuit signal line 102 may further include a first overlapping portion 1024, where the first overlapping portion 1024 is connected between the first connecting portion 1023 and the end of the first winding portion 1022 close to the first main line portion 1021 (i.e., the starting end of the first main line portion 1021); the constant voltage signal line 103 may further include a second overlapping portion 1034, where the second overlapping portion 1034 is connected between the second connecting portion 1033 and the end of the second winding portion 1032 close to the second main line portion 1031 (i.e., the starting end of the second main line portion 1031), and the second overlapping portion 1034 and the first overlapping portion 1024 overlap with each other in a direction perpendicular to the base substrate 101 to form a third capacitor C3, and the orthographic projection area of ​​the third capacitor C3 on the base substrate 101 is larger than the orthographic projection area of ​​the second capacitor C2 on the base substrate 101. By setting a larger third capacitor C3 at a position closest to the first capacitor C1, it is possible to avoid the formation of tip discharge at a position close to the signal source (equivalent to the gate drive circuit signal line 102 at the first capacitor C1, and the constant voltage signal line 103), which would cause crosstalk between the signal of the gate drive circuit signal line 102 and the signal of the constant voltage signal line 103.

[0089] Continuing to refer to FIG. 4 , FIG. 9 , FIG. 10 and FIG. 12 , it can be seen that the present disclosure can be implemented by setting the line width of the first overlapping portion 1024 to be greater than the line width of the first winding portion 1022 (equivalent to the line width of the first winding repeating unit 1022 ″), and the line width of the second overlapping portion 1034 to be greater than the line width of the second winding portion 1032 outside the second capacitor C2 (equivalent to the line width of the second winding repeating unit 1032 ″). In other words, the line width of the first overlapping portion 1024 is greater than the line width of the first winding portion 1022 (equivalent to the line width of the first winding repeating unit 1022 ″). The line width of the unit 1022" is increased, and the line width of the second overlapping portion 1034 is increased relative to the line width of the second winding portion 1032 outside the second capacitor C2 (equivalent to the line width of the second winding repeating unit 1032", so that the third capacitor C3 formed by the first overlapping portion 1024 and the second overlapping portion 1034 overlapping in the direction Z perpendicular to the base substrate 101 can be larger than the second capacitor C2 formed by the first winding portion 1022 and the second winding portion 1032 overlapping in the direction Z perpendicular to the base substrate 101.

[0090] In some embodiments, in the above-mentioned array substrate provided in the embodiment of the present disclosure, as shown in Figures 14 and 15, the first winding portion 1022 includes a plurality of first sub-winding portions 221 and at least one straight portion 222, the first sub-winding portion 221 having a notch on the side facing the first main line portion 1021, the plurality of first sub-winding portions 221 being sequentially arranged around the end of the first winding portion 1022, the straight portion 222 being connected to at least two first sub-winding portions 221 adjacent to the end of the first winding portion 1022, and Figure 15 shows that the straight portion 222 is adjacent to the end of the first winding portion 1022. The three first sub-winding portions 221 are connected; the second winding portion 1032 includes multiple second sub-winding portions 321, and the second sub-winding portion 321 has a notch on the side facing the second main line portion 1031. The multiple second sub-winding portions 321 are arranged in sequence around the end of the second winding portion 1032, and the orthographic projections of the second sub-winding portions 321 on the substrate 101 and the orthographic projections of the first sub-winding portions 221 on the substrate 101 are alternately arranged, and at least part of the second sub-winding portions 321 overlap with the straight portion 222 in the direction Z perpendicular to the substrate 101 to form a second capacitor C2.

[0091] In the embodiment shown in Figures 14 and 15, the first winding portion 1022 and the second winding portion 1032 both adopt a circular non-loop design, which can effectively save wiring space. At the same time, a second capacitor C2 for tip discharge is provided at the end of the first winding portion 1022 and the second winding portion 1032 and in the vicinity thereof, which can effectively ensure that tip discharge is formed at a position farther away from the signal source (equivalent to the gate drive circuit signal line 102 at the first capacitor C1 and the constant voltage signal line 103), and the winding resistance between the second capacitor C2 and the first capacitor C1 is large, so that after the second capacitor C2 is broken down by the instantaneous current, when the signal is working normally, the current will select the normal working circuit with small resistance, and will not flow into the winding area with large resistance to cause the signal on the gate drive circuit signal line 102 and the signal on the constant voltage signal line 103 to interfere with each other, thereby ensuring that the normal operation of the product remains unaffected after the breakdown.

[0092] In some embodiments, in the above-mentioned array substrate provided by the embodiment of the present disclosure, as shown in Figures 16 to 20, the first winding portion 1022 includes a plurality of first protrusions 223, and the second winding portion 1032 includes a plurality of second protrusions 322; optionally, in Figures 17 and 18, the first winding portion 1022 and the second winding portion 1032 are arranged in different layers, and the plurality of first protrusions 223 and the plurality of second protrusions 322 overlap in a direction Z perpendicular to the base substrate 101 to form a plurality of The second capacitor C2; in Figures 19 and 20, the first winding portion 1022 and the second winding portion 1032 are arranged in the same layer, and the multiple first protrusions 223 and the multiple second protrusions 322 are opposite to each other to form multiple second capacitors C2. Optionally, the first winding portion 1022 and the source and drain of the transistor are arranged in the same layer and material, the second winding portion 1032 and the pixel electrode or common electrode of the display area are arranged in the same layer and material, or the second winding portion 1032 and the gate of the transistor are arranged in the same layer and material.

[0093] Continuing to refer to Figures 17 and 20, it can be seen that, in addition to the multiple second capacitors C2, the orthographic projection of the first winding portion 1022 on the base substrate 101 and the orthographic projection of the second winding portion 1032 on the base substrate 101 are symmetrically arranged with respect to the arrangement direction of the multiple second capacitors C2 (i.e., the Y direction), so that the multiple second capacitors C2 are located at the end of the first winding portion 1022 and the end of the second winding portion 1032, ensuring that a tip discharge is formed at a position far away from the signal source (equivalent to the gate drive circuit signal line 102 at the first capacitor C1, and the constant voltage signal line 103), and the winding resistance between the second capacitor C2 and the first capacitor C1 is large, so that after the second capacitor C2 is broken down by the instantaneous current, when the signal is working normally, the current will select the normal working circuit with small resistance, and will not flow into the winding area with large resistance to cause the signal on the gate drive circuit signal line 102 and the signal on the constant voltage signal line 103 to interfere with each other, thereby ensuring that the normal operation of the product is still not affected after the breakdown. In addition, the first winding portion 1022 and the second winding portion 1032 adopt a zigzag non-loop design as shown in FIG. 12 and FIG. 15 , which has a simple wiring method and is suitable for products with sufficient wiring space in the X direction and limited wiring space in the Y direction.

[0094] In some embodiments, the present disclosure can adjust different breakdown voltages by adjusting the spacing between the first protrusion 223 and the second protrusion 322 positioned opposite each other in the same layer, so as to be suitable for large-sized products. Since the larger the spacing between the first protrusion 223 and the second protrusion 322, the greater the required breakdown voltage, in order to meet the purpose of breakdown discharge in the present disclosure, as shown in FIG20 , the spacing d between the first protrusion 223 and the second protrusion 322 can be set to be less than or equal to 15 μm; and, since the first protrusion 223 and the second protrusion 322 are arranged in the same layer, in order to avoid short circuiting between the first protrusion 223 and the second protrusion 322, the minimum value of the spacing d between the first protrusion 223 and the second protrusion 322 can be set to the process limit value, for example, 8 μm.

[0095] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, the size of the first protrusion 223 is substantially the same as the size of the second protrusion 322. Optionally, the size of the first protrusion 223 and the second protrusion 322 is greater than or equal to 4 μm and less than or equal to 7 μm, for example, 4 μm, 5 μm, 6 μm, 7 μm, etc. If the size of the first protrusion 223 and the second protrusion 322 is less than 4 μm, the related technology is not yet capable of completing the production. If the size of the first protrusion 223 and the second protrusion 322 is greater than 7 μm, the first protrusion 223 and the second protrusion 322 are too large to achieve tip discharge. Based on this, the present disclosure sets the size of the first protrusion 223 and the second protrusion 322 to 4 μm to 7 μm. In some embodiments, the first protrusion 223 and the second protrusion 322 can be designed as a regular octagon with a single side size of 4μm to 7μm. Due to factors such as manufacturing process accuracy, the shape of the first protrusion 223 and the second protrusion 322 in the actual product is approximately circular.

[0096] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in Figures 4, 9, 10, 12, 15, and 17, the second main line portion 1031 can be integrally provided with the second winding portion 1032 to form the constant voltage signal line 103. Optionally, in Figures 4, 9, 10, 15, and 17, the second main line portion 1031 and the second winding portion 1032 can be integrally provided on the layer where the common electrode (com) is located; in Figure 12, the second main line portion 1031 and the second winding portion 1032 can be integrally provided on the layer where the gate of the transistor is located. Optionally, the constant voltage signal line 103 is coupled to the common electrode signal line CL that is wound around the display area AA within the non-display area BB.

[0097] As shown in Figure 21, to ensure uniformity of the common voltage signal (Vcom) within the display area AA of a product (especially large-size products), signals can be simultaneously applied to the common electrode (com) within the display area AA via the proximal common electrode signal line NCL, the middle common electrode signal line MCL, and the distal common electrode signal line FCL. In some embodiments, fluctuations in the common voltage signal (Vcom) can be monitored via the feedback signal line FL, and the circuit end compensates the common voltage signal (Vcom) based on the fluctuations in the common voltage signal (Vcom) to maintain the common voltage required for normal display. When capacitive coupling occurs at the first capacitor C1 and charge breakdown occurs at the second capacitor C2, causing fluctuations in the common voltage signal (Vcom), the feedback-compensation mechanism can dynamically compensate the common voltage signal (Vcom), ensuring that the stability of the common voltage signal (Vcom) is maintained while preventing static electricity and not affecting normal display.

[0098] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in Figures 19 and 20 , the second main line portion 1031 and the second winding portion 1032 can be two independent lines. For example, the second main line portion 1031 is located in the layer where the common electrode (com) is located, and the second winding portion 1032 is located in the layer where the source / drain of the transistor is located. The second main line portion 1031 can be coupled to the common electrode signal line and grounded at the second winding portion 1032. That is, the second main line portion 1031 carries the common voltage signal (Vcom), and the second winding portion 1032 carries the ground signal (GND). This is equivalent to the constant voltage signal line 103 including two signal lines carrying different signals. Based on the feedback-compensation mechanism of the common voltage signal (Vcom), when capacitive coupling occurs at the first capacitor C1 formed by the overlap of the second main line portion 1031 and the first main line portion 1021, resulting in fluctuations in the common voltage signal (Vcom), dynamic compensation of the common voltage signal (Vcom) can be achieved, ensuring that static electricity is prevented while not affecting normal image display. Furthermore, since the ground signal (GND) itself will not be affected by any signal and fluctuate, the instantaneous current overload of the present disclosure can be discharged through the second capacitor C2 formed by the second winding portion 1032 and the first winding portion 1022 .

[0099] In some embodiments, in the above-mentioned array substrate provided in the embodiment of the present disclosure, a first alignment layer may also be provided on the side of the second transparent conductive layer away from the base substrate 101. Other essential components in the array substrate should be understood by ordinary technicians in this field and will not be elaborated here, nor should they be regarded as limitations of the present disclosure.

[0100] Based on the same inventive concept, an embodiment of the present disclosure provides a display panel, as shown in Figure 22, including the above-mentioned array substrate 001 provided in the embodiment of the present disclosure, an opposing substrate 002 opposite to the array substrate 001, and a liquid crystal layer 003 located between the array substrate 001 and the opposing substrate 002; wherein, the opposing substrate 002 may include multiple red color resists, multiple green color resists and multiple blue color resists, and two adjacent color resists may be separated from each other by a black matrix; wherein, in the direction perpendicular to the base substrate: the size of the blue color resist is larger than the size of the red color resist and the size of the green color resist, and the size of the red color resist is approximately the same as the size of the green color resist.

[0101] In some embodiments, in the display panel provided by the embodiments of the present disclosure, a first polarizer may be provided on a side of the array substrate 001 away from the counter substrate 002, a second alignment layer may be provided on a side of the counter substrate 002 away from the array substrate 001, and a second polarizer may be provided on a side of the counter substrate 002 away from the array substrate 001, with the polarization directions of the first polarizer and the second polarizer being perpendicular to each other. Other essential components of the display panel are well understood by those skilled in the art and are not described here in detail, nor should they be construed as limitations of the present disclosure.

[0102] Based on the same inventive concept, an embodiment of the present disclosure provides a display device, as shown in FIG23 , comprising the above-mentioned display panel PNL provided in an embodiment of the present disclosure, and a backlight module BLU located on the light incident side of the display panel PNL. The backlight module BLU can be a direct-type backlight module or an edge-type backlight module. Optionally, the edge-type backlight module may include a light bar, a stacked reflective sheet, a light guide plate, a diffuser, a prism group, etc., and the light bar is located on one side of the thickness direction of the light guide plate. The direct-type backlight module may include a matrix light source, a reflective sheet, a diffuser, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, and the reflective sheet includes an opening arranged opposite to the position of each lamp bead in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source may be light-emitting devices (LEDs), such as quantum dot light-emitting devices (QLEDs), micro light-emitting devices (such as Mini LEDs, Micro LEDs), etc.

[0103] Among them, submillimeter-scale or even micron-scale micro-light-emitting devices are self-luminous devices, just like organic light-emitting devices (OLEDs). Like organic light-emitting devices, they have a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angles. And because inorganic light-emitting devices emit light based on metal semiconductors with more stable properties and lower resistance, they have the advantages of lower power consumption, greater resistance to high and low temperatures, and longer service life compared to organic light-emitting devices that emit light based on organic matter. And when micro-light-emitting devices are used as backlight sources, they can achieve more precise dynamic backlight effects. While effectively improving the brightness and contrast of the screen, they can also solve the glare phenomenon caused by traditional dynamic backlighting between bright and dark areas of the screen, thereby optimizing the visual experience.

[0104] In some embodiments, the above-mentioned display device provided in the embodiments of the present disclosure may be: a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, or any other product or component with a display function. Optionally, the display device provided in the present disclosure includes, but is not limited to, components such as a camera module, an ambient light sensor, a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip. Optionally, the control chip is a central processing unit, a digital signal processor, a system-on-chip (SoC), etc. For example, the control chip may further include a memory, a power module, etc., and realize power supply and signal input and output functions through additionally provided wires, signal lines, etc. For example, the control chip may further include hardware circuits and computer executable code, etc. The hardware circuit may include conventional very large scale integration (VLSI) circuits or gate arrays and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field programmable gate arrays, programmable array logic, programmable logic devices, etc.

[0105] In addition, those skilled in the art will understand that the above structure does not constitute a limitation on the above display device provided in the embodiment of the present disclosure. In other words, the above display device provided in the embodiment of the present disclosure may include more or fewer of the above components, or a combination of certain components, or different component arrangements.

[0106] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0107] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. An array substrate, wherein, Comprising: A substrate, the substrate including a display area and a non-display area located on at least one side of the display area; A gate driving circuit located in the non-display area, the gate driving circuit including a plurality of cascaded shift registers; A gate driving circuit signal line located in the non-display area, the gate driving circuit signal line being electrically connected to at least one stage of the shift register, the gate driving circuit signal line including a first main line portion and a first winding portion integrally provided; A constant voltage signal line located in the non-display area, the constant voltage signal line including a second main line portion and a second winding portion, wherein the second main line portion and the first main line portion overlap at least partially in a direction perpendicular to the substrate to form a first capacitor, the second winding portion and the first winding portion form at least one second capacitor, the orthographic projection area of the second capacitor on the substrate is smaller than the orthographic projection area of the first capacitor on the substrate, and at least a part of the first winding portion and / or at least a part of the second winding portion extends from the area where the first capacitor is located to the area where the second capacitor is located.

2. The array substrate according to claim 1, wherein, The first winding portion and the second winding portion overlap each other in a direction perpendicular to the substrate to form the second capacitor.

3. The array substrate according to claim 2, wherein, One of the first winding portion and the second winding portion includes a plurality of protruding portions, and the plurality of protruding portions overlap with the other of the first winding portion and the second winding portion in a direction perpendicular to the substrate to form a plurality of the second capacitors.

4. The array substrate according to claim 3, wherein, The winding lengths of the first winding portion on both sides of the area where the second capacitor is located are substantially the same, and the winding lengths of the second winding portion on both sides of the area where the second capacitor is located are substantially the same.

5. The array substrate according to claim 4, wherein, The first winding portion includes a first winding repeating unit, the second winding portion includes a second winding repeating unit, and on both sides of the area where the second capacitor is located, the first winding repeating unit and the second winding repeating unit are alternately arranged.

6. The array substrate according to any one of claims 2 to 5, wherein, The gate driving circuit signal line further includes a first connecting portion located on one side of the first winding portion, the first connecting portion being connected to the first main line portion and respectively connected to both ends of the first winding portion; The constant voltage signal line further includes a second connecting portion, the second connecting portion being connected to the second main line portion and respectively connected to both ends of the second winding portion, and the orthographic projection of the second connecting portion on the substrate is located on a side of the orthographic projection of the first winding portion on the substrate away from the orthographic projection of the first connecting portion on the substrate.

7. The array substrate according to claim 6, wherein, The gate driving circuit signal line further includes a first overlapping portion, the first overlapping portion being connected between the first connecting portion and an end of the first winding portion close to the first main line portion; The constant voltage signal line further includes a second overlapping portion, the second overlapping portion being connected between the second connecting portion and an end of the second winding portion close to the second main line portion, and the second overlapping portion and the first overlapping portion overlap each other in a direction perpendicular to the substrate to form a third capacitor, the orthographic projection area of the third capacitor on the substrate is larger than the orthographic projection area of the second capacitor on the substrate.

8. The array substrate according to claim 7, wherein, The line width of the first overlapping portion is greater than the line width of the first winding portion, and the line width of the second overlapping portion is greater than the line width of the second winding portion outside the second capacitor.

9. The array substrate according to claim 2, wherein, The first winding portion includes a plurality of first sub-winding portions and at least one straight portion. The first sub-winding portions have notches on a side facing the first main line portion. The plurality of first sub-winding portions are sequentially arranged around the end of the first winding portion, and the straight portion is connected to at least two of the first sub-winding portions adjacent to the end of the first winding portion. The second winding portion includes a plurality of second sub-winding portions. The second sub-winding portions have notches on a side facing the second main line portion. The plurality of second sub-winding portions are sequentially arranged around the end of the second winding portion, and the orthographic projection of the second sub-winding portions on the substrate is alternately arranged with the orthographic projection of the first sub-winding portions on the substrate. At least a part of the second sub-winding portions overlaps with the straight portion in a direction perpendicular to the substrate to form the second capacitor.

10. The array substrate according to claim 2, wherein, The first winding portion includes a plurality of first protruding portions, and the second winding portion includes a plurality of second protruding portions. The first protruding portions and the second protruding portions overlap in a direction perpendicular to the substrate to form the second capacitor.

11. The array substrate according to any one of claims 1 to 10, wherein, The second main line portion is integrally provided with the second winding portion.

12. The array substrate according to claim 11, wherein, The shift register includes transistors, and the constant voltage signal line is provided on the same layer as the gates of the transistors.

13. The array substrate according to claim 1, wherein, The first winding portion and the second winding portion are provided on the same layer. The first winding portion includes a plurality of first protruding portions, and the second winding portion includes a plurality of second protruding portions. The first protruding portions and the second protruding portions are arranged opposite to each other to form the second capacitor.

14. The array substrate according to claim 13, wherein, The second winding portion is grounded.

15. The array substrate according to claim 10, 13 or 14, wherein, The distance between the first protruding portion and the second protruding portion arranged opposite to each other is greater than or equal to 8 μm and less than or equal to 15 μm.

16. The array substrate according to any one of claims 10, 13 to 15, wherein, The size of the first protruding portion is greater than or equal to 4 μm and less than or equal to 7 μm, and the size of the second protruding portion is substantially the same as the size of the first protruding portion.

17. The array substrate according to any one of claims 10, 13 to 16, wherein, Outside the plurality of second capacitors, the orthographic projection of the first winding portion on the substrate is symmetrically arranged with the orthographic projection of the second winding portion on the substrate with respect to the arrangement direction of the plurality of second capacitors.

18. The array substrate according to any one of claims 1 to 11 and 13 to 17, wherein, It further includes a common electrode located in the display area, and the second main line portion is provided on the same layer as the common electrode.

19. The array substrate according to any one of claims 1 to 18, wherein, The second main line portion is loaded with a common electrode signal.

20. The array substrate according to any one of claims 1 to 19, wherein, The shift register includes transistors, and the gate driving circuit signal line is provided on the same layer as the source / drain electrodes of the transistors.

21. The array substrate according to any one of claims 1 to 20, wherein, The gate driving circuit signal line includes an initial trigger signal line.

22. A display panel, wherein, It includes an array substrate and an opposing substrate arranged opposite to each other, wherein the array substrate is the array substrate according to any one of claims 1 to 21.

23. A display device, wherein, It includes a display panel according to claim 22.

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