Data driving device and display device comprising same

Abstract

The present invention relates to a data driving device and a display device comprising same, the data driving device comprising: a voltage selection unit, which receives pixel data so as to output a first voltage, a second voltage and an interpolation code of a predetermined number of bits; and an output buffer having a first input terminal to which the first voltage is applied, a second input terminal to which the second voltage is applied, a third input terminal connected to an output terminal through a feedback node, and a control terminal into which the interpolation code is input. The output buffer outputs an interpolation voltage in which voltage changes in response to a current controlled according to the interpolation code.

Description

Data drive device and display device including the same

[0001] The present invention relates to a data driving device and a display device including the same.

[0002] Various flat panel displays are known, including liquid crystal displays (LCDs), organic light emitting diode displays (OLEDs), electroluminescence displays (ELDs), field emission displays (FEDs), plasma display panels (PDPs), and electrophoresis displays (EPDs).

[0003] A display device includes a display panel on which pixels for displaying an input image are arranged, and a display panel driving circuit for writing data into the pixels of the display panel. The display panel driving circuit includes a data driving circuit for supplying data signals of pixel data to data lines of the display panel, and a gate driving circuit for supplying gate signals to gate lines of the display panel.

[0004] To reproduce high-definition images on display devices, various circuit technologies are being applied. For example, increasing the number of bits in pixel data transmitted to the data drive circuit as a digital signal can provide data signals with more detailed gradations to the display panel's pixels, thereby improving gradation expression and color reproducibility.

[0005] The present invention aims to solve the above-mentioned needs and / or problems.

[0006] The present invention provides a data driving device and a display device including the same, which can reduce the circuit area occupied by an interpolation circuit and improve grayscale expression and color reproduction characteristics.

[0007] The tasks of the present invention are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the description below.

[0008] A data driving device according to one embodiment of the present invention includes a voltage selection unit that receives pixel data and outputs a first voltage, a second voltage, and an interpolation code having a predetermined number of bits; and an output buffer having a first input terminal to which the first voltage is applied, a second input terminal to which the second voltage is applied, a third input terminal connected to an output terminal via a feedback node, and a control terminal to which the interpolation code is input. The output buffer outputs an interpolation voltage whose voltage is changed by a current controlled according to the interpolation code.

[0009] The interpolation voltage can be changed while the first voltage and the second voltage are fixed.

[0010] The above pixel data may include j bits (j is a positive integer greater than k). The above interpolation code may be 2 when jk bits are n (n is a positive integer greater than 2). n It may contain bits of dog.

[0011] The voltage selection unit may include a first decoder that receives an image code of upper k bits (k is a positive integer greater than or equal to 2) and p (p is a positive integer greater than or equal to 3) distributed voltages separated from the pixel data and selects the first voltage and the second voltage; and a second decoder that receives lower jk bits separated from the pixel data and outputs the interpolation code.

[0012] The output buffer may include a plurality of input transistors to which the first voltage and the second voltage are applied; a plurality of bias transistors that generate a bias current; and a current control unit connected between the input transistors and the bias transistors and receiving the interpolation code. The current control unit may include a plurality of switch elements that adjust the number of current paths that are conducted between the bias transistors and the input transistors in response to the interpolation code.

[0013] The above output buffer may further include a current amplification and output unit connected to the input transistors to amplify and output current; and a plurality of output transistors connected to the current amplification and output unit.

[0014] According to one embodiment of the present invention, a display device includes a display panel having a plurality of data lines, a plurality of gate lines intersecting the data lines, and a plurality of pixels arranged thereon; a data driver electrically connected to the data lines and supplying a data voltage generated as an interpolation voltage to the data lines; the data driver includes a voltage selector receiving pixel data and outputting a first voltage, a second voltage, and an interpolation code having a predetermined number of bits; and an output buffer having a first input terminal to which the first voltage is applied, a second input terminal to which the second voltage is applied, a third input terminal connected to an output terminal via a feedback node, and a control terminal to which the interpolation code is input. The output buffer outputs an interpolation voltage whose voltage is changed by a current controlled according to the interpolation code.

[0015] The present invention can efficiently utilize the circuit area because the number of large-capacity input transistors to which input voltage is applied can be reduced because interpolation is performed in a current control manner in an interpolation circuit of a data driving device.

[0016] The present invention can reduce interpolation errors by ensuring linearity (gm linearity) according to the current of an input transistor even when the input voltage range of an interpolation circuit is widened, and can improve grayscale expression and color reproduction characteristics.

[0017] The more bits in the interpolation code, the better the resolution of voltage interpolation can be.

[0018] The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

[0019] FIG. 1 is a block diagram showing a display device according to one embodiment of the present invention.

[0020] Figure 2 is a block diagram schematically showing the circuit configuration of the data drive unit.

[0021] Figure 3 is a circuit diagram showing in detail the interpolation circuit illustrated in Figure 2.

[0022] FIG. 4 is a diagram showing an example of input / output signals of the second decoder illustrated in FIG. 2.

[0023] Figure 5 is a diagram showing an example of a voltage interpolated according to a digital signal input to an interpolation circuit.

[0024] Figures 6 and 7 are circuit diagrams showing in detail the output buffer illustrated in Figure 3.

[0025] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. The embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0026] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the details depicted in the drawings. Throughout the specification, the same reference numerals designate substantially the same components. Furthermore, in describing the present invention, detailed descriptions of related known technologies will be omitted if they are deemed to unnecessarily obscure the gist of the present invention.

[0027] In the specification, when “comprises,” “includes,” “has,” and “consists of,” other parts may be added unless “only” is used. When a component is expressed in the singular, it may be interpreted as plural unless otherwise explicitly stated.

[0028] When interpreting a component, it is interpreted as including the error range even if there is no separate explicit description.

[0029] When the positional relationship and interconnectedness between two components are described as ‘on’, ‘above’, ‘below’, ‘next to’, ‘connect, couple’, crossing, intersecting, etc., one or more other components may be interposed between the components unless there is a mention of ‘directly’ or ‘directly’.

[0030] When the temporal order is explained with phrases such as ‘after’, ‘following’, ‘next to’, or ‘before’, it may not be continuous on the time axis unless ‘right away’ or ‘directly’ is used.

[0031] Although first, second, etc. may be used to distinguish components, the function or structure of these components is not limited by the ordinal number or component name attached to the front of the component.

[0032] The following embodiments can be partially or fully combined or combined with one another, enabling various technically feasible interconnections and operations. Each embodiment can be implemented independently of the other, or can be implemented together in a related manner.

[0033] In the following embodiments, the transistor is a three-electrode device including a gate, a source, and a drain. In the case of an n-channel transistor, since the carrier is an electron, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. In the n-channel transistor, the direction of current flows from the drain to the source. In the case of a p-channel transistor, since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In the p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. The source and drain of the transistor are not fixed. In the following description, the source and drain of the transistor will be referred to as the first and second electrodes.

[0034] Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings.

[0035] FIG. 1 is a block diagram showing a display device according to one embodiment of the present invention.

[0036] Referring to FIG. 1, a display device according to an embodiment of the present invention includes a display panel (100) and a display panel driving circuit for writing pixel data into pixels (101) of the display panel (100). Pixel data (Source data) can be interpreted as pixel data (Pixel data).

[0037] The substrate of the display panel (100) may be, but is not limited to, a plastic substrate, a thin glass substrate, or a metal substrate. The display panel (100) may be, but is not limited to, a rectangular panel having a width in a first direction, a length in a second direction, and a thickness in a third direction. In Fig. 1, X, Y, and Z may be, but are not limited to, the first direction, the second direction, and the third direction, respectively.

[0038] In the case of a liquid crystal display (LCD), a backlight unit (BLU) may be placed under the display panel (100). In the case of a self-luminous display such as an electroluminescent display, a light-emitting element is placed in each pixel, so a separate light source such as a backlight unit is not required.

[0039] The display area (AA) of the display panel (100) includes a pixel array that displays an input image. The pixel array includes a plurality of data lines (102), a plurality of gate lines (103) intersecting the data lines (102), and pixels (101) connected to the data lines (102) and the gate lines (103).

[0040] Pixels (101) may be arranged in a matrix form in the display area (AA). Each pixel (101) may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color implementation. Each pixel may further include a white sub-pixel. In a liquid crystal display, pixels include liquid crystal cells. In an electroluminescent display, pixels include light-emitting elements such as OLEDs. Each sub-pixel includes a pixel circuit for driving a liquid crystal cell or a light-emitting element.

[0041] The display panel driving circuit writes pixel data of an input image to pixels of the display panel (100) under the control of a timing controller (130). The display panel driving circuit includes a data driving unit (110) and a gate driving unit (120) that drive pixels (101). The display panel driving circuit may further include a touch sensor driving unit for driving touch sensors. The touch sensor driving unit is omitted in FIG. 1. In a mobile terminal or wearable terminal, the timing controller (130), the data driving unit (110), the touch sensor driving unit, etc. may be integrated into a single drive IC.

[0042] The data driving unit (110) receives pixel data of an input image as a digital signal from a timing controller (130) and outputs a data voltage. The data voltage of the pixel data is supplied to the pixels (101) through data lines (102).

[0043] The circuit of the gate driver (120) may be disposed in a non-display area (NA) outside the display area (AA) of the display panel (100), or at least part of the circuit may be disposed in the display area (AA). The gate driver (120) may be integrated into a separate gate drive IC and electrically connected to the gate lines (103) of the display panel (100). The gate driver (120) sequentially outputs pulses of gate signals to the gate lines under the control of the timing controller (130). The gate driver (120) may sequentially supply pulses of gate signals to the gate lines (103) by shifting the pulses of the gate signals using a shift register.

[0044] The timing controller (130) receives pixel data of an input image and a timing signal synchronized with the data from an external host system (200). The timing signal may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a main clock, etc. Since the vertical period and the horizontal period can be known by counting the data enable signal, the vertical synchronization signal and the horizontal synchronization signal (Hsync) may be omitted. The vertical synchronization signal has a period of one frame period. The horizontal synchronization signal and the data enable signal have periods of one horizontal period. The data enable signal defines a valid pixel data section of the input image.

[0045] The timing controller (130) controls the operation timing of the display panel driving circuit (110, 120) based on the timing signals (Vsync, Hsync, DE) received from the host system (200). The host system (200) can scale a video signal from a video source to match the resolution of the display panel (100) and transmit the scaled signal to the timing controller (130) along with the timing signal.

[0046] Figure 2 is a block diagram schematically showing the circuit configuration of the data drive unit.

[0047] Referring to FIG. 2, the data driving unit (110) may include a receiving unit (111), a logic control unit (112), a shift register (113), a first latch (114), a second latch (115), a grayscale voltage generation unit (116), and an interpolation circuit (117).

[0048] The receiving unit (111) receives a digital signal (DATA) serially received from the timing controller (130), restores a clock from the digital signal (DATA), and samples control data and pixel data of an input image from the digital signal (DATA) using the restored clock, and provides the sampled data to the logic control unit (112). The timing controller (130) can convert the clock and data into a low-voltage differential signal and transmit the same to the data driving unit (110) via a high-speed serial interface.

[0049] The logic control unit (112) rearranges pixel data in sub-pixel units. The logic control unit (112) supplies a start pulse and a clock to the shift register (113) using the restored clock and control data, and can control the output timing of the first and second latch units (114, 115) and the output buffer (118).

[0050] The shift register (113), the first latch (114), and the second latch (115) convert data of a serial system into data of a parallel system. When a start pulse is input, the shift register (113) shifts the clock and outputs it to the channels of the first latch (114). The first latch (114) samples pixel data input from the receiving unit (111) through the logic control unit (112) in response to the clock sequentially input from the shift register (113), and when pixel data is latched in all channels of the first latch (114), the latched data is simultaneously output to the channels of the second latch (115). The second latch (115) latches data simultaneously input from the first latch (114), and outputs the latched data to the interpolation circuit (117) in response to an output enable signal from the logic control unit (112).

[0051] The grayscale voltage generation unit (116) can receive a gamma tap voltage from a gamma voltage generation circuit omitted in the drawing, for example, a programmable gamma circuit. The gamma tap voltage can be interpreted as a gamma reference voltage. The grayscale voltage generation unit (116) can distribute the input voltage using a voltage distribution circuit including a plurality of resistors connected in series.

[0052] The data driving unit (110) may further include a level shifter, which is omitted in the drawing. The level shifter is connected between the second latch (115) and the interpolation circuit (117), and may shift the voltage of pixel data output from the second register (115) to the coin voltage of the interpolation circuit (117) and supply it to the interpolation circuit (117).

[0053] The interpolation circuit (117) selects a voltage in response to pixel data input from the second latch (115), interpolates the voltage, and outputs a data voltage. As illustrated in FIG. 3, the interpolation circuit (117) receives j (j is a positive integer greater than k) bits of pixel data, and receives p (p is a positive integer greater than or equal to 3) number of distribution voltages (VG1 to VGp) from the grayscale voltage generation unit (116). The distribution voltages (VG1 to VGp) have different voltage levels. The interpolation circuit (117) selects two voltages having a potential difference among the p number of distribution voltages (VG1 to VGp) in response to the image code of the upper k (k is a positive integer greater than or equal to 2) bits (hereinafter, referred to as “image code”) separated from the pixel data, and outputs the first and second input voltages (VINH, VINL).

[0054] The interpolation circuit (117) generates an interpolation code (STH) for controlling the current of the output buffer in response to the lower jk bits of the pixel data. The interpolation circuit (117) generates an interpolation voltage (VOUT) between the first and second input voltages (VINH, VINL) with a bias current selected according to the interpolation code (STH). The interpolation voltage (VOUT) is a data voltage of the pixel data. Therefore, the interpolation voltage (VOUT) output from the output buffer (320) is a data voltage that changes according to the grayscale value of the pixel data.

[0055] The interpolation circuit (117) controls the current of the input transistor while the input voltage (VINH, VINL) is fixed. This is due to the transconductance g of the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). m can be explained as follows.

[0056]

[0057] Here, V GS is the gate-source voltage of the transistor and V TH is the threshold voltage. I DS is the current flowing through the channel of the transistor.

[0058] The interpolation circuit (117) is V in the above equation GS - V TH In this fixed state, the current is controlled to output an interpolated voltage. This interpolation circuit (117) can significantly reduce the area occupied by the interpolation circuit because it can reduce the number of large transistors with a large capacity. In addition, the interpolation circuit (117) can reduce the interpolation error because the linearity (gm linearity) according to the current of the input transistor is corrected even if the input voltage range is widened.

[0059] Figure 3 is a circuit diagram showing in detail the interpolation circuit illustrated in Figure 2.

[0060] Referring to FIG. 3, the interpolation circuit (117) includes a voltage selection unit (310) that selects a voltage according to pixel data input as a j-bit digital signal and generates an interpolation code (STH), and an output buffer (320) that generates an interpolation voltage with a current controlled according to the interpolation code (STH) based on the voltage selected by the voltage selection unit (310).

[0061] The voltage selection unit (310) includes a first decoder (312) that selects first and second input voltages (VINH, VINL) in response to an image code obtained from the upper k bits of pixel data, and a second decoder (314) that generates an interpolation code (STH) in response to the lower jk bits of pixel data.

[0062] The first decoder (312) selects two voltages from among p distribution voltages (VG1 to VGp) in response to a k-bit image code. The first decoder (312) may select a higher voltage as the value of the image code increases, but is not limited thereto. For example, depending on the pixel driving method, a relatively lower voltage may be selected from among the distribution voltages (VG1 to VGp) as the value of the image code increases.

[0063] The second decoder (314) decodes the input signal of jk bits to generate an interpolation code (STH) of n bits (n is a positive integer greater than or equal to 2). When jk bits are n (n is a positive integer greater than or equal to 2), the interpolation code (STH) is 2 nIt can be generated as a code of bits, but is not limited thereto. For example, the second decoder (314) can generate an 8-bit interpolation code (STH) as shown in FIG. 4 in response to a 3-bit input signal. As shown in FIG. 4, the second decoder (314) can generate the interpolation code (STH) as 00000000 when the jk bit is 000, and can generate the interpolation code (STH) as 11111111 when the jk bit is 111. The interpolation code (STH) generated from the second decoder (314) interpolates the input voltages (VINH, VINL) by controlling the bias current of the output buffer. The interpolation code (STH) generated from the second decoder (314) can be changed according to the current distribution method of the output buffer (320). As the number of bits of the interpolation code (STH) increases, the intermediate voltages between the first input voltage (VINH) and the second input voltage (VINL) can be distinguished more finely, thereby improving the resolution of voltage interpolation.

[0064] The output buffer (320) receives first and second input voltages (VINH, VINL) selected according to an image code, and an n-bit interpolation code (STH). The output buffer (320) includes a first input terminal (+) to which the first input voltage (VINH) is applied, a second input terminal (+) to which the second input voltage (VINH) is applied, a third input terminal (-) connected to the output terminal via a feedback node, and control terminals to which an n-bit interpolation code (STH) is input. The first input voltage (VINH) may be a voltage higher than the second input voltage (VINL). The output buffer (320) may output an interpolation voltage (VOUT) whose voltage is changed by a bias current controlled according to the interpolation code (STH) in a voltage range between the first and second input voltages (VINH, VINH).

[0065] FIG. 5 is a diagram showing an example of a voltage interpolated according to a digital signal input to an interpolation circuit. In FIG. 5, Ids is a current flowing through a drain-source channel of the bias transistors illustrated in FIG. 6. The voltage of the output buffer (VOUT) may be interpolated according to the digital signal of the jk bit as in the example of FIG. 5, but is not limited thereto. For example, when the jk bit is 000, VINL=8*Ids, and VOUT=VINL. When the jk bit is 011, VINL=5*Ids, VINH=3*Ids, and VOUT=(5*VINL + 3*VINH) / 8. When the jk bit is 100, VINL=4*Ids, VINH=4*Ids, and VOUT=(4*VINL + 4*VINH) / 8. When the jk bit is 111, VINL=1*Ids, VINH=8*Ids, VOUT=(1*VINL + 7*VINH) / 8.

[0066] Figures 6 and 7 are circuit diagrams showing in detail the output buffer illustrated in Figure 3. In Figure 6, AVDDH is a high-potential driving voltage applied to the wiring of the fifth node (55), and VSS is a low-potential reference voltage or ground voltage applied to the wiring of the eighteenth node (68). VBP is a second bias voltage lower than the high-potential driving voltage (AVDDH) and is applied to the sixth node (56). STHB is an inverted code of the interpolation code (STH) through an inverter omitted in the drawing and is applied to the seventh nodes (57). STH is a non-inverted interpolation code and is applied to the sixth nodes (56). VBN is a first bias voltage lower than the second input voltage (VINL) and higher than the low-potential reference voltage (VSS) and is applied to the seventeenth node (67). A first node (51) to which a first input voltage (VINH) is applied may be connected to the first input terminal illustrated in Fig. 6. A second node (52) to which a second input voltage (VINL) is applied may be connected to the second input terminal illustrated in Fig. 6. A thirteenth node (63) may be a feedback node between the output terminal illustrated in Fig. 6 and the third input terminal. Fig. 7 shows the current amplification and output unit illustrated in Fig. 6.

[0067] Referring to FIG. 6, the output buffer (320) includes a plurality of input transistors (M1 to M8), a plurality of bias transistors (PM1 to PMn, NM1 to NMn), a current control unit (40, 42), a current amplification and output unit (70), and an output transistor (PMO, NMO).

[0068] A first input voltage (VINH) and a second input voltage (VINL) are applied to input transistors (M1 to M8). The first to fourth input transistors (M1 to M4) can be implemented as n-channel MOSFETs. The first input transistor (M1) includes a gate electrode connected to a first node (51) to which the first input voltage (VINH) is applied, a first electrode connected to a third node (53), and a second electrode connected to a fourteenth node (64). When the first input transistor (M1) is turned on, the third node (53) can be electrically connected to the fourteenth node (64). The second input transistor (M2) includes a gate electrode connected to a thirteenth node (63), a first electrode connected to a fourth node (54), and a second electrode connected to a fourteenth node (64). When the second input transistor (M2) is turned on, the fourth node (64) can be electrically connected to the fourteenth node (54).

[0069] The third input transistor (M3) includes a gate electrode connected to a second node (52) to which a second input voltage (VINL) is applied, a first electrode connected to a third node (53), and a second electrode connected to a fifteenth node (65). When the third input transistor (M3) is turned on, the third node (53) can be electrically connected to the fifteenth node (65). The fourth input transistor (M4) includes a gate electrode connected to the thirteenth node (63), a first electrode connected to a fourth node (54), and a second electrode connected to the fifteenth node (65). When the fourth input transistor (M4) is turned on, the fourth node (54) can be electrically connected to the fifteenth node (65).

[0070] The fifth to eighth input transistors (M5 to M8) can be implemented as p-channel MOSFETs. The fifth input transistor (M5) includes a gate electrode connected to a first node (51), a first electrode connected to an eighth node (58), and a second electrode connected to an eleventh node (61). When the first input transistor (M1) is turned on, the eighth node (58) can be electrically connected to the eleventh node (61). The sixth input transistor (M6) includes a gate electrode connected to a thirteenth node (63), a first electrode connected to the eighth node (58), and a second electrode connected to a twelfth node (62). When the sixth input transistor (M6) is turned on, the eighth node (58) can be electrically connected to the twelfth node (62).

[0071] The seventh input transistor (M7) includes a gate electrode connected to the second node (52), a first electrode connected to the ninth node (59), and a second electrode connected to the eleventh node (61). When the seventh input transistor (M7) is turned on, the ninth node (59) can be electrically connected to the eleventh node (61). The eighth input transistor (M8) includes a gate electrode connected to the thirteenth node (63), a first electrode connected to the ninth node (59), and a second electrode connected to the twelfth node (62). When the eighth input transistor (M8) is turned on, the ninth node (59) can be electrically connected to the twelfth node (62).

[0072] Bias transistors (NM1 to NMn) generate bias current (Ids). The n-channel bias transistors (NM1 to NMn) can be implemented as n-channel MOSFETs. The n-channel bias transistors (NM1 to NMn) are connected between a corresponding switch element in the first current control unit (42) and an 18th node (68). Each of the n-channel bias transistors (NM1 to NMn) includes a gate electrode connected to a 17th node (67) to which a first bias voltage (VBN) is applied, a first electrode connected to a corresponding switch element in the first current control unit (42), and a second electrode connected to the 18th node (68) to which a low-potential reference voltage (VSS) is applied. Each of the n-channel bias transistors (NM1 to NMn) can be electrically connected to a 14th node (64) or a 15th node (65) through the first current control unit (42).

[0073] The p-channel bias transistors (PM1 to PMn) can be implemented as p-channel MOSFETs. The p-channel bias transistors (PM1 to PMn) are connected between the corresponding switch element and the eighteenth node (68) in the second current control unit (40). Each of the p-channel bias transistors (PM1 to PMn) includes a gate electrode connected to the sixth node (56) to which the second bias voltage (VBP) is applied, a first electrode connected to the fifth node (55) to which the high-potential driving voltage (AVDDH) is applied, and a second electrode connected to the corresponding switch element in the second current control unit (40). Each of the p-channel bias transistors (PM1 to PMn) can be electrically connected to the eighth node (58) or the ninth node (59) through the second current control unit (40).

[0074] The first current control unit (42) connects the corresponding n-channel bias transistors (NM1 to NMn) to the 14th node (64) or the 15th node (65) in response to the interpolation code (STH). The first current control unit (42) includes a plurality of switch elements that switch in response to the voltage of the corresponding bit of the interpolation code (STH). The number of current paths conducted through the first current control unit (42) may vary depending on the interpolation code (STH). As illustrated in FIG. 5, the bias current (Ids) flowing through the n-channel transistor (NM1) may be adjusted according to the current path formed through the first current control unit (42), thereby changing the interpolation voltage (VOUT). For example, when the first bit of the interpolation code (STH) is 0, the first n-channel transistor (NM1) may be connected to the 15th node (65), whereas when the first bit of the interpolation code (STH) is 1, the first n-channel transistor (NM1) may be connected to the 14th node (n64).

[0075] The second current control unit (40) connects the corresponding p-channel bias transistors (PM1 to PMn) to the eighth node (58) or the ninth node (59) in response to the inverted interpolation code (STHB). The second current control unit (40) includes a plurality of switch elements that switch in response to the voltage of the corresponding bit of the inverted interpolation code (STHB). The number of current paths conducted through the first current control unit (42) may vary depending on the inverted interpolation code (STH). The bias current (Ids) flowing through the n-channel transistor (NM1) may be adjusted according to the current path formed through the first current control unit (42), thereby changing the interpolation voltage (VOUT). For example, when the first bit of the inverted interpolation code (STHB) is 0, the first p-channel transistor (PM1) may be connected to the ninth node (59), while when the first bit of the inverted interpolation code (STHB) is 1, the first p-channel transistor (PM1) may be connected to the eighth node (58).

[0076] Referring to FIGS. 6 and 7, the current amplification and output unit (70) can amplify current using a current mirror.

[0077] The current amplification and output unit (70) includes a plurality of transistors (T1 to T12). The current amplification and output unit (70) is connected to output transistors (PMO, NMO). The first to fourth, sixth, and eighth transistors (T1, T2, T3, T4, T6, and T8) and the first output transistor (PMO) may be implemented as p-channel MOSFETs. The fifth, seventh, ninth, and twelfth transistors (T5, T7, T9, T10, T11, and T12) and the second output transistor (NMO) may be implemented as n-channel MOSFETs.

[0078] The first transistor (T1) includes a gate electrode connected to the 21st node (71), a first electrode connected to the 5th node (55), and a second electrode connected to the 3rd node (53). The second transistor (T2) includes a gate electrode connected to the 21st node (71), a first electrode connected to the 5th node (55), and a second electrode connected to the 4th node (54). The third transistor (T3) includes a gate electrode connected to the 22nd node (72), a first electrode connected to the 3rd node (53), and a second electrode connected to the 21st node (71). The fourth transistor (T4) includes a gate electrode connected to the 22nd node (72), a first electrode connected to the 4th node (54), and a second electrode connected to the 23rd node (73). The sixth transistor (T6) includes a gate electrode to which a fourth bias voltage (Vb) is applied, a first electrode connected to the twenty-first node (71), and a second electrode connected to the twenty-fourth node (74). The eighth transistor (T8) includes a gate electrode to which a sixth bias voltage (Vd) is applied, a first electrode connected to the twenty-third node (73), and a second electrode connected to the twenty-sixth node (76). The first output transistor (PMO) includes a gate electrode connected to the twenty-third node (73), a first electrode connected to the fifth node (55), and a second electrode connected to the thirteenth node (63).

[0079] The fifth transistor (T5) includes a gate electrode to which a third bias voltage (Va) is applied, a first electrode connected to the 21st node (71), and a second electrode connected to the 24th node (74). The seventh transistor (T7) includes a gate electrode to which a fifth bias voltage (Vc) is applied, a first electrode connected to the 23rd node (73), and a second electrode connected to the 26th node (76). The ninth transistor (T9) includes a gate electrode connected to the 25th node (75), a first electrode connected to the 24th node (74), and a second electrode connected to the 11th node (61). The tenth transistor (T10) includes a gate electrode connected to the 25th node (75), a first electrode connected to the 26th node (76), and a second electrode connected to the 12th node (62). The eleventh transistor (T11) includes a gate electrode connected to the twenty-fourth node (72), a first electrode connected to the eleventh node (11), and a second electrode connected to the eighteenth node (68). The twelfth transistor (T12) includes a gate electrode connected to the twenty-fourth node (74), a first electrode connected to the twelfth node (62), and a second electrode connected to the eighteenth node (68). The second output transistor (NMO) includes a gate electrode connected to the twenty-sixth node (76), a first electrode connected to the thirteenth node (63), and a second electrode connected to the eighteenth node (68).

[0080] The current amplification and output unit (70) may further include capacitors (C) connected to the 13th node (63). These capacitors (C) can suppress ripple and stabilize the interpolation voltage (VOUT).

[0081] In the interpolation circuit (117) of the present invention, the interpolation voltage (VOUT) can be adjusted from the two input voltages (VINH, VINL) input to the output buffer (720) by adjusting the bias current (Id) while the two input voltages (VINH, VINL) are fixed. Since interpolation is performed using a current control method, the number of large-capacity input transistors to which the input voltage is applied can be reduced. Meanwhile, since the transistors constituting the current control unit (40, 42) are switch elements, they can be implemented in a much smaller size than the input transistors. Therefore, the circuit area of ​​the output buffer (72) can be significantly reduced.

[0082] Since the content of the specification described in the problem to be solved, the means for solving the problem, and the effect described above does not specify the essential features of the claim, the scope of the claim is not limited by the matters described in the content of the specification.

[0083] While the embodiments of the present invention have been described in more detail with reference to the attached drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be implemented without departing from the scope of the technical spirit of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to illustrate, rather than limit, the technical spirit of the present invention, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

Claims

1. A voltage selection unit that inputs pixel data and outputs a first voltage, a second voltage, and an interpolation code of a predetermined number of bits; and An output buffer having a first input terminal to which the first voltage is applied, a second input terminal to which the second voltage is applied, a third input terminal connected to an output terminal through a feedback node, and a control terminal to which the interpolation code is input, The above output buffer is a data-driven device that outputs an interpolated voltage whose voltage is changed by a current controlled according to the above interpolation code.

2. In paragraph 1, A data driving device in which the interpolation voltage is changed while the first voltage and the second voltage are fixed.

3. In paragraph 1, The above pixel data is, Contains j bits (where j is a positive integer greater than k), The above interpolation code is, When jk bit is n (n is a positive integer greater than or equal to 2), 2 n A data-driven device containing a dog's bits.

4. In paragraph 3, The above voltage selection unit, A first decoder that receives an image code of upper k bits (k is a positive integer greater than or equal to 2) separated from the pixel data and p (p is a positive integer greater than or equal to 3) distributed voltages and selects the first voltage and the second voltage; and A data-driven device comprising a second decoder that receives lower jk bits separated from pixel data and outputs the interpolation code.

5. In paragraph 4, The above output buffer is, A plurality of input transistors to which the first voltage and the second voltage are applied; A plurality of bias transistors generating bias current; and A current control unit connected between the input transistors and the bias transistors and receiving the interpolation code, A data drive device, wherein the current control unit includes a plurality of switching elements that adjust the number of current paths conducted between the bias transistors and the input transistors in response to the interpolation code.

6. In paragraph 5, The above output buffer is, A current amplification and output unit connected to the above input transistors to amplify and output current; and A data drive device further comprising a plurality of output transistors connected to the current amplification and output section.

7. A display panel having a plurality of data lines, a plurality of gate lines intersecting the data lines, and a plurality of pixels arranged thereon; A data driving unit electrically connected to the above data lines and supplying a data voltage generated as an interpolation voltage to the above data lines is included. The above data driving unit, A voltage selection unit that inputs pixel data and outputs a first voltage, a second voltage, and an interpolation code of a predetermined number of bits; and An output buffer having a first input terminal to which the first voltage is applied, a second input terminal to which the second voltage is applied, a third input terminal connected to an output terminal through a feedback node, and a control terminal to which the interpolation code is input, A display device, wherein the output buffer includes an output buffer that outputs an interpolated voltage whose voltage is changed by a current controlled according to the interpolation code.

8. In paragraph 7, A display device in which the interpolation voltage is changed while the first voltage and the second voltage are fixed.

9. In paragraph 7, The above pixel data is, Contains j bits (where j is a positive integer greater than k), The above interpolation code is, A data-driven device containing n bits (where n is a positive integer greater than or equal to 2).

10. In paragraph 9, The above voltage selection unit, A first decoder that receives an image code of upper k bits (k is a positive integer greater than or equal to 2) separated from the pixel data and p (p is a positive integer greater than or equal to 3) distributed voltages and selects the first voltage and the second voltage; and A display device comprising a second decoder that receives lower jk bits separated from pixel data and outputs the interpolation code.

11. In Article 10, The above output buffer is, A plurality of input transistors to which the first voltage and the second voltage are applied; A plurality of bias transistors generating bias current; and A current control unit connected between the input transistors and the bias transistors and receiving the interpolation code, A display device, wherein the current control unit includes a plurality of switching elements that adjust the number of current paths conducted between the bias transistors and the input transistors in response to the interpolation code.

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