Data driving unit and display device including same

Abstract

An embodiment discloses a data driving unit and a display device including same. The data driving unit comprises: a first driving circuit including a first DA conversion unit that outputs a first analog data voltage by using a first gamma voltage selected according to a first digital image signal, and a first amplification unit that amplifies the level of the output first analog data voltage and outputs same to a first data line; and a second driving circuit including a second DA conversion unit that outputs a second analog data voltage by using a second gamma voltage selected according to a second digital image signal, and a second amplification unit that amplifies the level of the output second analog data voltage and outputs same to a second data line, wherein, for each pre-determined pixel line, the first DA conversion unit outputs the first analog data voltage by using the second gamma voltage selected by the second DA conversion unit, and the second DA conversion unit outputs the second analog data voltage by using the first gamma voltage selected by the first DA conversion unit.

Description

Data drive unit and display device including the same

[0001] The embodiment relates to a data driving unit and a display device including the same.

[0002] As the information society develops, the demand for display devices for displaying images is increasing in various forms, and recently, various types of display devices such as liquid crystal display devices (LCDs) and organic light emitting display devices (OLEDs) are being utilized.

[0003] A display device includes a display panel including a plurality of pixels, a panel driver for driving the display panel, etc. The panel driver includes a data driver for supplying a data voltage to the display panel, and a gate driver for supplying a gate signal to the display panel.

[0004] When multiple pixels are arranged alternately in RGBG and BGRG formats in units of lines, the data driver must alternately apply data voltages to the R pixels and B pixels through the same data line. For example, the data driver applies the data voltage to the R pixels in odd-numbered pixel lines to the corresponding data line, and applies the data voltage to the B pixels in even-numbered lines to the same data line.

[0005] Using this method of alternating data voltage supply can cause display panel control issues, as the output speed of the data driver differs when a single image pattern is input versus when a different image pattern is input. Therefore, various methods are needed to minimize the difference in the output speed of the data driver depending on the image pattern.

[0006] The embodiment provides a data driving unit capable of minimizing an output speed difference and a display device including the same.

[0007] The tasks of the present invention are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the description below.

[0008] A data driving unit according to an embodiment of the present invention includes a first driving circuit including a first DA conversion unit that outputs a first analog data voltage using a first gamma voltage selected according to a first digital image signal and a first amplifier unit that amplifies the level of the output first analog data voltage and outputs it to a first data line; and a second driving circuit including a second DA conversion unit that outputs a second analog data voltage using a second gamma voltage selected according to a second digital image signal and a second amplifier unit that amplifies the level of the output second analog data voltage and outputs it to a second data line, wherein for each predetermined pixel line, the first DA conversion unit can output the first analog data voltage using the second gamma voltage selected by the second DA conversion unit, and the second DA conversion unit can output the second analog data voltage using the first gamma voltage selected by the first DA conversion unit.

[0009] The first DA conversion unit may include a first a decoder that outputs a first a voltage and a first b voltage using a first gamma voltage selected according to the first digital image signal, and a first b decoder that outputs the first analog data voltage using the outputted first a voltage and first b voltage, and the second DA conversion unit may include a second a decoder that outputs a second a voltage and a second b voltage using a second gamma voltage selected according to the second digital image signal, and a second b decoder that outputs the second analog data voltage using the outputted second a voltage and second b voltage.

[0010] For each of the predetermined pixel lines, the second a decoder can output the first analog data voltage using the first b voltage and the second b voltage, and the second b decoder can output the second analog data voltage using the first a voltage and the second a voltage.

[0011] The first DA conversion unit may include a 1aL switch connected between a first voltage terminal of the 1a decoder that outputs the 1a voltage and a first voltage terminal of the 1b decoder, and a 1aH switch connected between a second voltage terminal of the 1a decoder that outputs the 2a voltage and a second voltage terminal of the 1b decoder, and the second DA conversion unit may include a 1bL switch connected between a first voltage terminal of the 2a decoder that outputs the 1b voltage and a first voltage terminal of the 2b decoder, and a 1bH switch connected between a second voltage terminal of the 2a decoder that outputs the 2b voltage and a second voltage terminal of the 2b decoder.

[0012] The first aL switch, the first aH switch, the first bL switch, and the first bH switch can be turned on for every odd pixel line and turned off for every even pixel line.

[0013] The first DA conversion unit may further include a second aL switch connected between the first voltage terminal of the first a decoder and the second voltage terminal of the second b decoder, and a second aH switch connected between the second voltage terminal of the first a decoder and the second voltage terminal of the second b decoder, and the second DA conversion unit may further include a second bL switch connected between the first voltage terminal of the second a decoder and the first voltage terminal of the first b decoder, and a second bH switch connected between the second voltage terminal of the second a decoder and the second voltage terminal of the first b decoder.

[0014] The second aL switch, the second aH switch, the second bL switch, and the second bH switch can be turned on for every even pixel line and turned off for every odd pixel line.

[0015] A display device according to an embodiment of the present invention comprises: a display panel having a plurality of data lines, a plurality of gate lines intersecting the data lines, and a plurality of pixels arranged thereon; a data driving unit electrically connected to the data lines and supplying a data voltage to the data lines; the data driving unit comprising: a first driving circuit including a first DA converter that outputs a first analog data voltage using a first gamma voltage selected according to a first digital image signal, and a first amplifier that amplifies a level of the outputted first analog data voltage and outputs it to a first data line; And a second driving circuit including a second DA conversion unit that outputs a second analog data voltage using a second gamma voltage selected according to a second digital image signal, and a second amplifier unit that amplifies the level of the output second analog data voltage and outputs it to a second data line, wherein the first DA conversion unit can output the first analog data voltage using the second gamma voltage selected by the second DA conversion unit for each predetermined pixel line, and the second DA conversion unit can output the second analog data voltage using the first gamma voltage selected by the first DA conversion unit.

[0016] According to an embodiment, instead of supplying the analog source voltage output from the existing amplifier in a cross-linked manner to the red sub-pixel and blue sub-pixel that change in pixel line units, by supplying the gamma voltage selected within the DA converter in a cross-linked manner, the difference in output speed of the data drive unit according to the image pattern can be minimized.

[0017] According to an embodiment, manufacturing costs can be reduced because no additional configuration is added to compensate for fast settling times occurring in certain image patterns.

[0018] According to an embodiment, the area efficiency can be increased because the gamma voltages selected within the DA converter are crossed with each other without crossing the eight lines output from the DA converter.

[0019] The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

[0020] FIG. 1 is a drawing showing a display device according to an embodiment of the present invention.

[0021] Figure 2 is a drawing showing the arrangement of pixels illustrated in Figure 1.

[0022] Fig. 3 is a drawing showing the configuration of the data driving unit illustrated in Fig. 1.

[0023] Fig. 4 is a drawing for explaining the operating principle of the DA converter shown in Fig. 3.

[0024] Figures 5a and 5b are drawings showing the connection structure between DA conversion units in the data driving unit.

[0025] Figure 6 is a drawing showing the driving waveforms of the first and second switches illustrated in Figure 5.

[0026] Figures 7 and 8 are drawings for explaining the operating principle of the data driving unit according to Figure 6.

[0027] Figures 9 and 10 are drawings for comparing and explaining simulation results of the data driving unit.

[0028] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. The embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0029] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the details depicted in the drawings. Throughout the specification, the same reference numerals designate substantially the same components. Furthermore, in describing the present invention, detailed descriptions of related known technologies will be omitted if they are deemed to unnecessarily obscure the gist of the present invention.

[0030] In the specification, when “comprises,” “includes,” “has,” and “consists of,” other parts may be added unless “only” is used. When a component is expressed in the singular, it may be interpreted as plural unless otherwise explicitly stated.

[0031] When interpreting a component, it is interpreted as including the error range even if there is no separate explicit description.

[0032] When the positional relationship and interconnectedness between two components are described as ‘on’, ‘above’, ‘below’, ‘next to’, ‘connect, couple’, crossing, intersecting, etc., one or more other components may be interposed between the components unless there is a mention of ‘directly’ or ‘directly’.

[0033] When the temporal order is explained with phrases such as ‘after’, ‘following’, ‘next to’, or ‘before’, it may not be continuous on the time axis unless ‘right away’ or ‘directly’ is used.

[0034] To distinguish components, the ordinal numbers 1, 2, etc. may be used before the names of components; however, these ordinal numbers or names of components do not limit their function or structure. For convenience of explanation, the ordinal numbers preceding the names of the same components may differ across embodiments.

[0035] The following embodiments can be partially or fully combined or combined with one another, enabling various technically feasible interconnections and operations. Each embodiment can be implemented independently of the other, or can be implemented together in a related manner.

[0036] Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings.

[0037] FIG. 1 is a drawing showing a display device according to an embodiment of the present invention, and FIG. 2 is a drawing showing the arrangement of pixels shown in FIG. 1.

[0038] Referring to FIG. 1, a display device (100) according to an embodiment of the present invention may include a display panel (110) and a display driving circuit for driving the display panel. The display driving circuit may include a gate driving unit (120), a data driving unit (130), and a timing controller (140). The display device may further include a host system (150) that supplies various timing signals to the timing controller (140).

[0039] The display panel (110) may include a plurality of gate lines (G1 to Gn) that are arranged crosswise to define a plurality of pixel areas, a plurality of data lines (D1 to Dm), and pixels (P) provided in each of the plurality of pixel areas.

[0040] A pixel (P) may include a red subpixel (R) that emits red light, a green subpixel (G) that emits green light, and a blue subpixel (B) that emits blue light, as shown in FIG. 2. At this time, the positions of the red subpixel (R) and the blue subpixel (B) may vary for each pixel line. For example, in odd-numbered pixel lines (L1, L3), a red subpixel, a green subpixel, a blue subpixel, and a green subpixel may be arranged in that order, and in even-numbered pixel lines (L2, L4), a blue subpixel, a green subpixel, a red subpixel, and a green subpixel may be arranged in that order. Here, red, green, and blue subpixels are described as examples, but the present invention is not limited thereto.

[0041] A red subpixel (R) and a blue subpixel (B) may be connected to the first data line (DL1), and a blue subpixel (B) and a red subpixel (R) may be connected to the third data line (DL3). That is, a red subpixel (R) and a blue subpixel (B) are connected to odd-numbered data lines.

[0042] The gate driver (120) may be arranged on one side of the display panel (110), for example, on the left side, as shown, but may also be arranged on both one side and the other side of the display panel (110), for example, on both the left and right sides, facing each other, as needed. The gate driver (120) may include a plurality of gate driver ICs (Gate Driver Integrated Circuits, not shown).

[0043] The gate driver (120) may be formed in the form of a tape carrier package in which a gate driver IC is mounted, but is not necessarily limited thereto, and the gate driver IC may be mounted directly on the display panel (110).

[0044] The data driving unit (130) converts a digital image signal transmitted from the timing controller (140) into an analog source signal and outputs the signal to the display panel (110). Specifically, the data driving unit (130) outputs an analog source signal to the data lines (D1 to Dm) in response to a data control signal (DCS: Data Control Signal) transmitted from the timing controller (140).

[0045] The data driving unit (130) can alternately supply a data voltage for the red subpixel and a data voltage for the blue subpixel through a data line to which the red subpixel and the blue subpixel are connected, since the red subpixel (R) and the blue subpixel (B) have different positions for each pixel line.

[0046] The data driving unit (130) may be disposed on one side of the display panel (110), for example, on the upper side, but may also be disposed on both one side and the other side of the display panel (110), for example, on both the upper and lower sides, facing each other, depending on the case. In addition, the data driving unit (130) may be formed in the form of a tape carrier package in which a source driver IC is mounted, but is not necessarily limited thereto.

[0047] The timing controller (140) can receive various timing signals including a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable (DE) signal, a clock signal (CLK), etc. from the host system (150) and generate a data control signal (DCS) for controlling the data driver (130) and a gate control signal (GCS) for controlling the gate driver (120). In addition, the timing controller (140) can receive image data (RGB) from the host system (150) and convert it into image data (RGB') in a form that can be processed by the data driver (130) and output it.

[0048] The data control signal (DCS) may include a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE), and the gate control signal (GCS) may include a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (GOE).

[0049] The host system (150) may be implemented as any one of a navigation system, a set-top box, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, a broadcast receiver, and a phone system.

[0050] The host system (150) can include a system on chip (SoC) with a built-in scaler to convert digital image data (RGB) of an input image into a format suitable for display on a display panel (110). The host system (150) can transmit digital image data (RGB) and timing signals to a timing controller (140).

[0051] Fig. 3 is a drawing showing the configuration of the data drive unit shown in Fig. 1, and Fig. 4 is a drawing for explaining the operating principle of the DA conversion unit shown in Fig. 3.

[0052] Referring to FIG. 3, a data driving unit according to an embodiment of the present invention may include a data latch (Source Data Latch; SDL), a level shifter (Level Shifter; LS), a digital analog converter (DAC), and an amplifier (AMP).

[0053] The data latch (SDL) shifts the clock input from the timing controller to generate a sampling clock, samples and stores a digital image signal according to the timing of the generated sampling clock, and can simultaneously output the stored digital image signal.

[0054] The data latch (SDL) can generate control signals to control the digital-to-analog converter (DAC). An example of generating a control signal from the data latch (SDL) is described here, but is not limited thereto. For example, a control signal can be generated in a control logic unit separate from the data latch (SDL) and the generated control signal can be provided to the data latch (SDL).

[0055] A level shifter (LS) can convert the voltage level of an output digital image signal. The level shifter (LS) can convert the voltage level of a digital image signal into a voltage level that can be driven by a digital-to-analog converter (DAC).

[0056] The DA converter (DAC) can select a gamma voltage corresponding to a digital image signal whose voltage level has been converted by a level shifter (LS) and output it as an analog data voltage. The DA converter (DAC) can include a first decoder (DEC1) and a second decoder (DEC2), as shown in Fig. 4.

[0057] The first decoder (DEC1) can select one gamma voltage among the gamma voltages for each grayscale using the video signal. For example, the 8-bit first decoder (DEC1) can select one gamma voltage VR among the gamma voltages for each grayscale using the upper 8 bits of data '1000000000' among the 11-bit pixel data '1000000000'. <1024> , set the selected gamma voltage to the first voltage (VL), and set the gamma voltage VR 8 bits higher than the first voltage (VL) <1032> can be set to the second voltage (VH).

[0058] When the first decoder (DEC1) is set to a first voltage (VL) and a second voltage (VH) based on a video signal, the first decoder (DEC1) can supply the set first voltage (VL) and second voltage (VH) to the second decoder (DEC2).

[0059] The second decoder (DEC2) can select a gamma voltage using the first voltage (VL), the second voltage (VH), and the lower 3 bits of data '000' for interpolation, and output the selected gamma voltage as an analog data voltage.

[0060] At this time, the second decoder (DEC2) generates a gamma voltage VR corresponding to the first voltage (VL) when the data of the lower 3 bits is '000'. <1024> Select to output analog data voltage, and if the data of the lower 3 bits is '001', VR greater than the first voltage (VL) <1025> The analog data voltage is output by selecting the method of outputting the analog data voltage.

[0061] That is, the second decoder (DEC2) generates a gamma voltage VR between the first voltage and the second voltage. <1024> ~ VR <1031> One of the gamma voltages can be selected and output as an analog data voltage.

[0062] The amplifier (AMP) can amplify the level of an analog data voltage and output it to a data line. The amplifier (AMP) receives analog voltage from the second decoder (DEC2) through 8 lines, and amplifies and outputs the average value of the 8 analog voltages supplied.

[0063] In the embodiment, instead of supplying the analog data voltage output from the existing amplifier in a cross-linked manner to the red sub-pixel and blue sub-pixel that are changed in pixel line units, the first voltage and the second voltage selected within the DA converter are supplied in a cross-linked manner.

[0064] In the embodiment, an example of supplying the first voltage and the second voltage alternately for every odd or even pixel line arranged as in Fig. 2 is described as an example, but it is not limited thereto. For example, since it is possible to supply the first voltage and the second voltage alternately for every two pixel lines when arranged alternately in the form of RGBG, RGBG, BGRG, BGRG, it is also possible to supply the first voltage and the second voltage alternately for every n pixel lines.

[0065] FIGS. 5A and 5B are drawings showing a connection structure between DA conversion units within a data driving unit, and FIG. 6 is a drawing showing the driving waveforms of the first and second switches shown in FIG. 5.

[0066] Referring to FIGS. 5A and 5B, the data driving unit may include a first driving circuit including a first data latch (SDL1), a first level shifter (LS1), a first DA conversion unit (DAC1), and a first amplifier unit (AMP1), and a second driving circuit including a second data latch (SDL2), a second level shifter (LS2), a second DA conversion unit (DAC2), and a second amplifier unit (AMP2).

[0067] The first DA conversion unit (DAC1) includes a first a decoder (DEC1a), a second a decoder (DEC2a), a first a switch (SW1a), and a second a switch (SW2a), and the second DA conversion unit (DAC2) includes a first b decoder (DEC1b), a second b decoder (DEC2b), a first b switch (SW1b), and a second b switch (SW2b).

[0068] The 1a switch (SW1a) includes a 1aL switch (SW1aL) and a 1aH switch (SW1aH).

[0069] The first switch (SW1aL) is connected between the first voltage terminal (NL) to which the 1a voltage (VL) of the 1a decoder (DEC1a) is supplied and the first voltage terminal (NL) of the 2a decoder (DEC2a), and the 1aH switch (SW1aH) is connected between the second voltage terminal (NH) to which the 2a voltage (VH) of the 1a decoder (DEC1a) is supplied and the second voltage terminal (NH) of the 2a decoder (DEC2a).

[0070] The 1b switch (SW1b) includes a 1bL switch (SW1bL) and a 1bH switch (SW1bH).

[0071] The first bL switch (SW1bL) is connected between the first voltage terminal (NL) to which the first b voltage (VL) of the first b decoder (DEC1b) is supplied and the first voltage terminal (NL) of the second b decoder (DEC2b), and the first bH switch (SW1bH) is connected between the second voltage terminal (NH) to which the second b voltage (VH) of the first b decoder (DEC1b) is supplied and the second voltage terminal (NH) of the second b decoder (DEC2b).

[0072] The second a switch (SW2a) includes a second aL switch (SW2aL) and a second aH switch (SW2aH).

[0073] The second aL switch (SW2aL) is connected between the first voltage terminal (NL) to which the first a voltage (VL) of the first a decoder (DEC1a) is supplied and the first voltage terminal (NL) of the second b decoder (DEC2b), and the second aH switch (SW2aH) is connected between the second voltage terminal (NH) to which the second a voltage (VH) of the first a decoder (DEC1a) is supplied and the second voltage terminal (NH) of the second b decoder (DEC2b).

[0074] The second b switch (SW2b) includes a second bL switch (SW2bL) and a second bH switch (SW2bH).

[0075] The second bL switch (SW2bL) is connected between the first voltage terminal (NL) to which the first b voltage (VL) of the first b decoder (DEC1b) is supplied and the first voltage terminal (NL) of the second a decoder (DEC2a), and the second bH switch (SW2bH) is connected between the second voltage terminal (NH) to which the second b voltage (VH) of the first b decoder (DEC1b) is supplied and the second voltage terminal (NH) of the second a decoder (DEC2a).

[0076] As shown in Fig. 6, the first a switch (SW1a) and the first b switch (SW1b) are turned on or turned off simultaneously, and the second a switch (SW2a) and the second b switch (SW2b) are turned on or turned off simultaneously, opposite to the first a switch (SW1a) and the first b switch (SW1b).

[0077] For example, when the first switch (SW1a) and the first switch (SW1b) are turned on, the first voltage terminal (NL) and the second voltage terminal (NH) of the first decoder (DEC1a) are connected to the first voltage terminal (NL) and the second voltage terminal (NH) of the second decoder (DEC2a), respectively, and the first voltage terminal (NL) and the second voltage terminal (NH) of the first decoder (DEC1b) are connected to the first voltage terminal (NL) and the second voltage terminal (NH) of the second decoder (DEC2b), respectively.

[0078] As another example, when the 2a switch (SW2a) and the 2b switch (SW2b) are turned on, the first voltage terminal (NL) and the second voltage terminal (NH) of the 1a decoder (DEC1a) are connected to the first voltage terminal (NL) and the second voltage terminal (NH) of the 2b decoder (DEC2b), respectively, and the first voltage terminal (NL) and the second voltage terminal (NH) of the 1b decoder (DEC1b) are connected to the first voltage terminal (NL) and the second voltage terminal (NH) of the 2a decoder (DEC2a), respectively.

[0079] Control signals for controlling the first switch (SW1a), the first switch (SW1b), the second switch (SW2a), and the second switch (SW2b) can be provided from the first data latch or the second data latch.

[0080] The connection structure of the first and second switches described here is only an example and is not limited thereto.

[0081] Figures 7 and 8 are drawings for explaining the operating principle of the data driving unit according to Figure 6.

[0082] Referring to FIG. 7, when a data voltage is applied to the corresponding data line, the first a switch (SW1a) and the first b switch (SW1b) are turned on during the first period (T1), so that the first voltage terminal (NL) and the second voltage terminal (NH) of the first a decoder (DEC1a) are connected to the first voltage terminal (NL) and the second voltage terminal (NH) of the second a decoder (DEC2a), respectively, and the first voltage terminal (NL) and the second voltage terminal (NH) of the first b decoder (DEC1b) are connected to the first voltage terminal (NL) and the second voltage terminal (NH) of the second b decoder (DEC2b), respectively.

[0083] The first voltage and the second voltage selected from the first decoder of the first DA conversion unit (DAC1) are supplied to the second decoder, so that the first data voltage is output to the first data line, and the first voltage and the second voltage selected from the first decoder of the second DA conversion unit (DAC2) are supplied to the second decoder, so that the second data voltage is output to the second data line.

[0084] Referring to FIG. 8, when a data voltage is applied to another data line, when the second switch (SW2a) and the second switch (SW2b) are turned on during the second period (T2), the first voltage terminal (NL) and the second voltage terminal (NH) of the first decoder (DEC1a) are connected to the first voltage terminal (NL) and the second voltage terminal (NH) of the second decoder (DEC2b), respectively, and the first voltage terminal (NL) and the second voltage terminal (NH) of the first decoder (DEC1b) are connected to the first voltage terminal (NL) and the second voltage terminal (NH) of the second decoder (DEC2a), respectively.

[0085] The first voltage and the second voltage selected by the first decoder of the first DA conversion unit (DAC1) are supplied to the second decoder of the first DA conversion unit (DAC2), so that the first data voltage is output to the second data line, and the first voltage and the second voltage selected by the first decoder of the second DA conversion unit (DAC2) are supplied to the second decoder of the first DA conversion unit (DAC1), so that the second data voltage is output to the first data line.

[0086] Figures 9 and 10 are drawings for comparing and explaining simulation results of the data driving unit.

[0087] Referring to FIG. 9, it can be seen that when the data voltages output from the first driving circuit and the second driving circuit in the data drive of the comparative example are supplied to different data lines in a cross manner, the output speed is faster when outputting a single image pattern than when outputting different image patterns.

[0088] For example, in the rising section, the first output voltage is 403 ns and the second output voltage is 729 ns, so the output speed of the first output voltage is fast, and in the falling section, the first output voltage is 390 ns and the second output voltage is 615 ns, so the output speed of the first output voltage is fast.

[0089] This is because in the case of a single image pattern, the output speed is fast because only the data line changes through the MUX and the data voltage does not change.

[0090] Referring to FIG. 10, when the data voltages output from the first driving circuit and the second driving circuit in the data drive of the embodiment are supplied to different data lines in a cross manner, it can be seen that the output speeds between the first output voltage when outputting a single image pattern (red pattern) and the second output voltage when outputting a different image pattern (black / white pattern) are consistent.

[0091] For example, in the rising section, the first output voltage is 730 ns and the second output voltage is 733 ns, which are almost identical, and in the falling section, the first output voltage is 617 ns and the second output voltage is 614 ns, which are almost identical. However, for convenience, the two output voltages are shown side by side.

[0092] In an embodiment, the output speed can be maintained constant without adding any configuration to compensate for the fast settling time that occurs in certain image patterns. Here, the settling time may be the time taken to reach the target voltage.

[0093] As shown in the example, it can be seen that the proposed method of applying gamma voltages in a cross-sectional manner is more effective than the existing method of applying data voltages in a cross-sectional manner at the output of the data drive.

[0094] Additionally, when applying the method according to the embodiment, it can be proven by the difference in output speed for a monochrome image pattern of red and blue and a specific image pattern of black and white.

[0095] Although the embodiments have been described in more detail with reference to the attached drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be implemented without departing from the technical spirit of the present invention. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but rather to illustrate it, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

Claims

1. A first driving circuit including a first DA converter that outputs a first analog data voltage using a first gamma voltage selected according to a first digital image signal and a first amplifier that amplifies the level of the output first analog data voltage and outputs it to a first data line; and A second driving circuit including a second DA converter that outputs a second analog data voltage using a second gamma voltage selected according to a second digital image signal and a second amplifier that amplifies the level of the output second analog data voltage and outputs it to a second data line, A data driving unit, wherein, for each predetermined pixel line, the first DA conversion unit outputs the first analog data voltage using the second gamma voltage selected by the second DA conversion unit, and the second DA conversion unit outputs the second analog data voltage using the first gamma voltage selected by the first DA conversion unit.

2. In paragraph 1, The above first DA converter, It includes a first a decoder that outputs a first a voltage and a first b voltage using a first gamma voltage selected according to the first digital image signal, and a first b decoder that outputs the first analog data voltage using the outputted first a voltage and first b voltage. The above second DA converter is, A data driving unit including a second a decoder that outputs a second a voltage and a second b voltage using a second gamma voltage selected according to the second digital image signal, and a second b decoder that outputs the second analog data voltage using the outputted second a voltage and second b voltage.

3. In paragraph 2, A data driving unit in which, for each of the above predetermined pixel lines, the 2a decoder outputs the first analog data voltage using the 1b voltage and the 2b voltage, and the 2b decoder outputs the second analog data voltage using the 1a voltage and the 2a voltage.

4. In paragraph 2, The above first DA converter, It includes a 1aL switch connected between a first voltage terminal outputting the 1a voltage of the 1a decoder and a first voltage terminal of the 1b decoder, and a 1aH switch connected between a second voltage terminal outputting the 2a voltage of the 1a decoder and a second voltage terminal of the 1b decoder. The above second DA converter is, A data driving unit comprising a 1bL switch connected between a first voltage terminal of the 2a decoder outputting the 1b voltage and a first voltage terminal of the 2b decoder, and a 1bH switch connected between a second voltage terminal of the 2a decoder outputting the 2b voltage and a second voltage terminal of the 2b decoder.

5. In paragraph 4, A data driving unit in which the first aL switch, the first aH switch, the first bL switch, and the first bH switch are turned on for every odd pixel line and turned off for every even pixel line.

6. In paragraph 4, The above first DA converter, Further comprising a 2aL switch connected between the first voltage terminal of the 1a decoder and the second voltage terminal of the 2b decoder, and a 2aH switch connected between the second voltage terminal of the 1a decoder and the second voltage terminal of the 2b decoder, The above second DA converter is, A data driving unit further comprising a 2bL switch connected between the first voltage terminal of the 2a decoder and the first voltage terminal of the 1b decoder, and a 2bH switch connected between the second voltage terminal of the 2a decoder and the second voltage terminal of the 1b decoder.

7. In paragraph 6, A data driving unit in which the second aL switch, the second aH switch, the second bL switch, and the second bH switch are turned on for every even pixel line and turned off for every odd pixel line.

8. A display panel having a plurality of data lines, a plurality of gate lines intersecting the data lines, and a plurality of pixels arranged thereon; A data driving unit electrically connected to the above data lines and supplying a data voltage to the above data lines is included. The above data driving unit, A first driving circuit including a first DA converter that outputs a first analog data voltage using a first gamma voltage selected according to a first digital image signal and a first amplifier that amplifies the level of the output first analog data voltage and outputs it to a first data line; and A second driving circuit including a second DA converter that outputs a second analog data voltage using a second gamma voltage selected according to a second digital image signal and a second amplifier that amplifies the level of the output second analog data voltage and outputs it to a second data line, A display device, wherein, for each predetermined pixel line, the first DA converter outputs the first analog data voltage using the second gamma voltage selected by the second DA converter, and the second DA converter outputs the second analog data voltage using the first gamma voltage selected by the first DA converter.

9. In paragraph 8, The above first DA converter, It includes a first a decoder that outputs a first a voltage and a first b voltage using a first gamma voltage selected according to the first digital image signal, and a first b decoder that outputs the first analog data voltage using the outputted first a voltage and first b voltage. The above second DA converter is, A display device comprising a second a decoder which outputs a second a voltage and a second b voltage using a second gamma voltage selected according to the second digital image signal, and a second b decoder which outputs the second analog data voltage using the outputted second a voltage and second b voltage.

10. In paragraph 9, A display device, wherein, for each of the predetermined pixel lines, the 2a decoder outputs the first analog data voltage using the 1b voltage and the 2b voltage, and the 2b decoder outputs the second analog data voltage using the 1a voltage and the 2a voltage.

11. In paragraph 9, The above first DA converter, It includes a 1aL switch connected between a first voltage terminal outputting the 1a voltage of the 1a decoder and a first voltage terminal of the 1b decoder, and a 1aH switch connected between a second voltage terminal outputting the 2a voltage of the 1a decoder and a second voltage terminal of the 1b decoder. The above second DA converter is, A display device comprising a 1bL switch connected between a first voltage terminal of the 2a decoder outputting the 1b voltage and a first voltage terminal of the 2b decoder, and a 1bH switch connected between a second voltage terminal of the 2a decoder outputting the 2b voltage and a second voltage terminal of the 2b decoder.

12. In paragraph 11, The above first DA converter, Further comprising a 2aL switch connected between the first voltage terminal of the 1a decoder and the second voltage terminal of the 2b decoder, and a 2aH switch connected between the second voltage terminal of the 1a decoder and the second voltage terminal of the 2b decoder, The above second DA converter is, A display device further comprising a 2bL switch connected between the first voltage terminal of the 2a decoder and the first voltage terminal of the 1b decoder, and a 2bH switch connected between the second voltage terminal of the 2a decoder and the second voltage terminal of the 1b decoder.

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