Display substrate and manufacturing method therefor, and display device

Abstract

A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises an active layer (21) provided on one side of a substrate (101); a first gate (11) provided on a first side of the active layer (21); a second gate (12) provided on a second side of the active layer (21), the second gate (12) being electrically connected to the active layer (21); and a third gate (13) provided on the second side of the active layer (21), the third gate (13) and the second gate (12) being insulated from each other, and the third gate (13) being electrically connected to the first gate (11). The first side and the second side are respectively two opposite sides of the active layer (21) in a direction perpendicular to the substrate (101), and the first gate (11), the second gate (12), and the third gate (13) all overlap with the orthographic projection of the active layer (21) on the substrate (101).

Description

Display substrate and manufacturing method thereof, and display device Technical Field

[0001] This article relates to but is not limited to the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] In one aspect, the present disclosure provides a display substrate, comprising:

[0006] an active layer disposed on one side of the substrate;

[0007] a first gate, disposed on a first side of the active layer;

[0008] a second gate, disposed on a second side of the active layer, the second gate being electrically connected to the active layer;

[0009] a third gate, disposed on the second side of the active layer, the third gate and the second gate being insulated from each other and electrically connected to the first gate;

[0010] The first side and the second side are two opposite sides of the active layer in a direction perpendicular to the substrate, and the first gate, the second gate and the third gate overlap with the orthographic projection of the active layer on the substrate.

[0011] In an exemplary embodiment, the orthographic projections of the second gate and the third gate on the substrate do not overlap, and a partition region is provided between the orthographic projections of the second gate and the third gate on the substrate, and the partition region is filled with an insulating material.

[0012] In an exemplary embodiment, the second gate is located on one side of the third gate in the second direction, and the segmentation region is shaped like a line extending along the first direction; or, the second gate is located on one side of the third gate in the first direction, and the segmentation region is shaped like a line extending along the second direction, and the first direction intersects the second direction.

[0013] In an exemplary embodiment, on a plane parallel to the display substrate, a vertical distance between the segmented regions in the second direction is greater than or equal to 0.5 micrometers and less than or equal to 2 micrometers.

[0014] In an exemplary embodiment, the second gate is located on one side of the third gate in a first direction, the segmentation region is shaped like a line extending along a second direction, and the first direction intersects the second direction.

[0015] In an exemplary embodiment, on a plane parallel to the display substrate, a vertical distance between the segmented regions in the first direction is greater than or equal to 0.5 micrometers and less than or equal to 2 micrometers.

[0016] In an exemplary embodiment, the segmentation area is in a broken line shape; or, the segmentation area is in a serpentine line shape.

[0017] In an exemplary embodiment, signal lines are further provided on the substrate, each of the signal lines overlaps with the orthographic projections of the second gate and the third gate on the substrate, and the signal lines include at least one of an initialization signal line, a reference voltage signal line, and a power supply signal line.

[0018] In an exemplary embodiment, an area of ​​an orthographic projection of the second gate on the substrate is greater than or equal to an area of ​​an orthographic projection of the third gate on the substrate.

[0019] In an exemplary embodiment, a ratio of an area of ​​an orthographic projection of the second gate on the substrate to an area of ​​an orthographic projection of the third gate on the substrate is less than or equal to 2 and greater than or equal to 1.

[0020] In an exemplary embodiment, an area of ​​an orthographic projection of the second gate on the substrate is smaller than or equal to an area of ​​an orthographic projection of the third gate on the substrate.

[0021] In an exemplary embodiment, a ratio of an area of ​​an orthographic projection of the second gate on the substrate to an area of ​​an orthographic projection of the third gate on the substrate is less than or equal to 1 and greater than or equal to 0.1.

[0022] In an exemplary embodiment, the second gate includes a high work function conductive material.

[0023] In an exemplary embodiment, the second gate includes a second electrode portion and a second lead portion connected to each other, the second lead portion being electrically connected to the active layer.

[0024] In an exemplary embodiment, the third gate includes a low work function conductive material, and the low work function conductive material includes at least one of aluminum, silver, and zinc.

[0025] In an exemplary embodiment, the third gate includes a third electrode portion and a third lead portion connected to each other, and the third lead portion is electrically connected to the first gate.

[0026] In an exemplary embodiment, the first gate includes a first electrode portion and a first lead portion connected to the first electrode portion, and the first lead portion is electrically connected to the second gate.

[0027] In an exemplary embodiment, a material of the active layer includes metal oxide, the active layer includes a channel region, and the channel region is linear or inverted U-shaped.

[0028] In an exemplary embodiment, a first connecting electrode is further included. The first connecting electrode is disposed on a side of the active layer away from the substrate, and the first connecting electrode is connected to the second gate and the active layer respectively.

[0029] In an exemplary embodiment, a second connecting electrode is further included. The second connecting electrode is disposed on a side of the active layer away from the substrate, and the second connecting electrode is connected to the first gate and the third gate respectively.

[0030] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0031] In another aspect, the present disclosure further provides a method for preparing a display substrate, comprising:

[0032] forming a second gate and a third gate on the substrate;

[0033] forming an active layer on a side of the second gate and the third gate away from the substrate;

[0034] forming a first gate on a side of the active layer away from the substrate, wherein the first gate, the second gate, and the third gate all overlap with an orthographic projection of the active layer on the substrate;

[0035] The second gate is electrically connected to the active layer, and the third gate is electrically connected to the first gate.

[0036] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0038] FIG1 is a schematic structural diagram of a display device;

[0039] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0040] FIG3 is a schematic diagram of a cross-sectional structure of a display substrate;

[0041] FIG4 a is a schematic diagram of a cross-sectional structure of a transistor on a display substrate;

[0042] FIG4 b is a graph showing the startup current of a transistor of a display substrate;

[0043] FIG5 a is an equivalent circuit diagram of a transistor of a display substrate according to an exemplary embodiment of the present disclosure;

[0044] FIG5 b is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to an exemplary embodiment of the present disclosure;

[0045] FIG5 c is an operation timing diagram of a pixel driving circuit of a display substrate according to an exemplary embodiment of the present disclosure;

[0046] FIG6 is a schematic cross-sectional view of a display substrate according to an exemplary embodiment of the present disclosure;

[0047] FIG7 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0048] FIG8 is a schematic diagram of a display substrate after forming second and third gate patterns according to the present disclosure;

[0049] 9a and 9b are schematic diagrams of a display substrate after an active layer pattern is formed according to the present disclosure;

[0050] 10a and 10b are schematic diagrams of a display substrate after forming a first gate pattern according to the present disclosure;

[0051] 11a and 11b are schematic plan views of another display substrate according to the present disclosure;

[0052] 12a and 12b are plan views of another display substrate according to the present disclosure;

[0053] FIG13 is a schematic plan view of another display substrate disclosed herein;

[0054] FIG14 is a schematic plan view of another display substrate disclosed herein;

[0055] FIG15 is a schematic plan view of another display substrate according to the present disclosure. DETAILED DESCRIPTION

[0056] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0057] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0058] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0059] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0060] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0061] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0062] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0063] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0064] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0065] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0066] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0067] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0068] Figure 4a is a schematic diagram of the cross-sectional structure of a transistor on a display substrate. As shown in Figure 4a, the display substrate includes a substrate 101', a first gate 11' disposed on the substrate 101', an active layer 21' disposed on the side of the first gate 11' away from the substrate 101', a second gate 12' disposed on the side of the active layer 21' away from the substrate 101', and a connecting electrode 31' disposed on the side of the second gate 12' away from the substrate 101'. The first gate 11' and the second gate 12' both overlap with the orthographic projection of the active layer 21' on the substrate 101'. The first gate 11', the second gate 12', and the active layer 21' form a transistor with a dual-gate structure. The first gate 11' can serve as the bottom gate of the transistor, and the second gate 12' can serve as the top gate of the transistor. The connecting electrode 31' connects the first gate 11' to the source terminal of the active layer 21' through a via.

[0069] The transistors in this display substrate have a large subthreshold swing (SS) to increase the data range (data range), that is, the voltage amplitude required to change the same level of current, thereby reducing the sensitivity of the display substrate's luminance to voltage fluctuations. If the data range (data range) is too small, that is, the sensitivity is too high, it will lead to poor low-grayscale stability (Mura), affecting the display effect.

[0070] Figure 4b is a graph showing the startup current of a transistor on a display substrate. The abscissa in Figure 4b represents the voltage Vgs between the gate and the active layer, and the ordinate represents the leakage current Ids of the active layer. As shown in Figure 4b, the dual-gate structure of the transistor on the display substrate, which connects the first gate 11' to the source terminal of the active layer 21' via a connecting electrode 31', significantly improves the subthreshold swing (SS) value. However, this reduces the startup current (Ion) of the transistor, affecting the transistor's on / off ratio (the ratio of startup current to off current), and thus impacting the display quality.

[0071] FIG1 is a schematic diagram of the structure of a display device. As shown in FIG1 , the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is respectively connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a per-pixel basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured as a shift register and may generate emission signals by sequentially transmitting emission stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal. o may be a natural number. In an exemplary embodiment, the pixel array may be provided on a display substrate.

[0072] Figure 2 is a schematic diagram of a planar structure of a display substrate. In an exemplary embodiment, the display substrate may include a display area and a frame area located around the display area. As shown in Figure 2, the display area of ​​the display substrate may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, and a third sub-pixel P3 that emits a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting unit may include at least a light-emitting device. The light-emitting device is respectively connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0073] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a blue subpixel (B) that emits blue light, and the third subpixel P3 may be a green subpixel (G) that emits green light. In an exemplary embodiment, the subpixels may be rectangular, diamond-shaped, pentagonal, or hexagonal, and the three subpixels may be arranged horizontally, vertically, or in a triangular pattern, although this disclosure is not limited thereto.

[0074] In an exemplary embodiment, a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, etc., which is not limited in the present disclosure.

[0075] Figure 3 is a schematic cross-sectional view of a display substrate, illustrating the structure of three sub-pixels within the display substrate. As shown in Figure 3, in a plane perpendicular to the display substrate, the display area of ​​the display substrate may include a drive circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the drive circuit layer 102 facing away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 facing away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch-sensitive structure layer, but this disclosure does not limit this.

[0076] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit, and the pixel driving circuit may include a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include at least a light-emitting device, and the light-emitting device may include an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0077] In exemplary embodiments, the organic light-emitting layer may include an emission layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0078] An exemplary embodiment of the present disclosure provides a display substrate, including:

[0079] an active layer disposed on one side of the substrate;

[0080] a first gate, disposed on a first side of the active layer;

[0081] a second gate, disposed on a second side of the active layer, the second gate being electrically connected to the active layer;

[0082] a third gate, disposed on the second side of the active layer, the third gate and the second gate being insulated from each other and electrically connected to the first gate;

[0083] The first side and the second side are two opposite sides of the active layer in a direction perpendicular to the substrate, and the first gate, the second gate and the third gate overlap with the orthographic projection of the active layer on the substrate.

[0084] In an exemplary embodiment, the device further includes signal lines disposed on the substrate, wherein the signal lines overlap with orthographic projections of the second gate and the third gate on the substrate.

[0085] In an exemplary embodiment, orthographic projections of the second gate and the third gate on the substrate do not overlap, and a partition region is provided between the orthographic projection of the second gate and the orthographic projection of the third gate on the substrate.

[0086] In an exemplary embodiment, an area of ​​an orthographic projection of the second gate on the substrate is greater than or equal to an area of ​​an orthographic projection of the third gate on the substrate.

[0087] In an exemplary embodiment, an area of ​​an orthographic projection of the second gate on the substrate is smaller than or equal to an area of ​​an orthographic projection of the third gate on the substrate.

[0088] In an exemplary embodiment, the second gate includes a high work function conductive material.

[0089] In an exemplary embodiment, the third gate includes a low work function conductive material.

[0090] The embodiment of the present disclosure shows that the display substrate can achieve a Bulk Accumulation effect by connecting the second gate to the source terminal (S) of the active layer and the third gate to the first gate, thereby increasing the subthreshold swing (SS) of the transistor of the display substrate, improving the data range, and maintaining the startup current (Ion) of the transistor without decreasing. For example, the on-off ratio (ratio of startup current to off-off current) of the conventional dual-gate structure transistor is 10 8 The disclosed embodiment shows that the on / off ratio (ratio of the start-up current to the off-state current) of the transistor of the substrate can be greater than 10 8 .

[0091] The Bulk Accumulation effect refers to the formation of an accumulation layer of conductive electrons at the interface between the top and bottom gates, creating two channels: one formed by the bottom gate and one by the top gate. Dual-channel drive allows for more effective control of the channel layer potential, as each gate only needs to raise the potential at half the depth of the channel layer. In contrast to single-gate transistors, which require increasing the potential at the gate-insulator interface as the gate bias increases, a single-gate transistor must also raise the potential at the gate-insulator interface. From an energy band structure perspective, the dual-gate structure shifts from the Fermi level (EF) to the conduction band (EC), quickly filling the conduction band and thus conducting.

[0092] The display substrate of the present disclosure is described below by way of some exemplary embodiments.

[0093] Figure 5a is an equivalent circuit diagram of a transistor of a display substrate according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the pixel driving circuit of the display substrate of this embodiment can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C or 9T2C structure, wherein T is a transistor and C is a capacitor. As shown in Figure 5a, the transistor of the pixel driving circuit of the display substrate of the embodiment of the present disclosure is a three-gate structure. The transistor of the embodiment of the present disclosure can be a driving transistor and / or a switching transistor in the pixel driving circuit, preferably as a driving transistor. The transistor of the embodiment of the present disclosure can include an active layer, a first gate, a second gate and a third gate. The first gate can serve as the top gate (TG) of the transistor, the second gate can serve as the first bottom gate (BG-1) of the transistor, the second gate is connected to the source terminal (S) of the active layer, the third gate can serve as the second bottom gate (BG-2) of the transistor, and the third gate can be connected to the first gate.

[0094] The following takes the pixel driving circuit of the display substrate of this embodiment as 4T1C as an example to illustrate the working timing of the pixel driving circuit.

[0095] As shown in FIG5b and FIG5c, the operating timing of the pixel driving circuit of the display substrate of this embodiment includes:

[0096] During the initialization period (initial), the scan signal SCAN(n) has an off-level to turn off the first switch TFT SW1, while the initialization signal INI(n) becomes an on-level to turn on the second and third switch TFTs SW2 and SW3. Therefore, the initialization voltage Vini is applied to the gate node of the driving TFT DT, and the reference voltage Vref is applied to the source node of the driving TFT DT. The initialization period may be one horizontal period of 1H.

[0097] A voltage corresponding to the difference between the initialization voltage Vini and the reference voltage Vref is charged to the storage capacitor Cst, so that the voltage between the gate and source of the driving TFT DT becomes (Vini-Vref). The initialization voltage Vini is higher than the reference voltage Vref by an amount sufficient to turn on the driving TFT DT. For example, the initialization voltage Vini may be 4V, and the reference voltage Vref may be 1V.

[0098] In the front portion of the threshold voltage sensing period (VthSensing), the scan signal SCAN(n) maintains an off-level to turn off the first switch TFT SW1, the initialization signal INI(n) maintains an on-level to turn on the second switch TFT SW2, so that the initialization voltage Vini is continuously applied to the gate node of the driving TFT DT, and the reference signal REF(n) becomes an off-level to float the source node of the driving TFT DT.

[0099] During the initialization period, the driving TFT DT is turned on by the voltage charged in the storage capacitor Cst. During the threshold voltage sensing period, the voltage of the source node of the driving TFT DT rises toward the voltage of the gate node due to the current flowing through the driving TFT DT (source follower). Therefore, if the sensing period is long enough, the voltage of the source electrode of the driving TFT DT rises until the difference between the initialization voltage applied to the gate node of the driving TFT DT and the voltage of the source node corresponds to the threshold voltage Vth of the driving TFT DT.

[0100] At the end of the threshold voltage sensing period (Vth Sensing), as shown in FIG5C , the scan signal SCAN(n) maintains an off-level to turn off the first switch TFT SW1, the initialization signal INI(n) changes to an off-level to turn off the second switch TFT SW2, which floats the gate node of the driving TFT DT, and the reference signal REF(n) maintains an off-level to float the source node of the driving TFT DT.

[0101] The driving TFT DT is maintained in an on state by the voltage charged in the storage capacitor Cst. Therefore, the voltage at the source node of the driving TFT DT increases due to the current flowing through the driving TFT DT, and the voltage at the gate node of the driving TFT DT increases due to the storage capacitor Cst connected to the source node. However, the increase is smaller than the increase in the voltage at the source node. Therefore, as time continues, a voltage corresponding to the threshold voltage of the driving TFT DT can be charged to the storage capacitor Cst.

[0102] In the data writing and mobility sensing period (writing and μ sensing), the scan signal SCAN(n) becomes an on-level to turn on the first switch TFT SW1, and thus the data voltage supplied to the data line is applied to the gate node of the driving TFT DT, and the initialization signal INI(n) maintains an off-level.

[0103] The voltage of the gate node of the driving TFT DT quickly rises to the data voltage, a current corresponding to the voltage difference between the gate and the source electrodes flows through the driving TFT DT, and the voltage of the source node of the driving TFT DT rises toward the data voltage applied to the gate node of the driving TFT DT, so that the voltage difference between the gate and the source electrodes of the driving TFT DT is programmed to a desired grayscale.

[0104] That is, when the current flowing through the driving TFT DT is expressed as I=K*(Vgs-Vth)2, where K is a constant related to electron mobility and is proportional to the electron mobility, in a case where the electron mobility of the driving TFT DT is high (K has a large value), the voltage of the source node of the driving TFT DT rises rapidly and Vgs decreases relatively quickly, while in a case where the electron mobility of the driving TFT DT is small (K has a small value), the voltage of the source node of the driving TFT DT rises slowly and Vgs decreases relatively slowly, so that the current flowing through the driving TFT DT becomes independent of the electron mobility and the electron mobility can be compensated.

[0105] In the light emission period (light emission), the scan signal SCAN(n) becomes an off level to turn off the first switch TFT SW1, and the initialization signal INI(n) and the reference signal REF(n) maintain an off level.

[0106] A current corresponding to the potential difference programmed between the gate and source electrodes of the driving TFT DT during the data writing period (i.e., the potential difference programmed in the storage capacitor Cst) flows. As a result, the voltage of the source node of the driving TFT DT rises, the voltage of the gate node also rises while maintaining the programmed potential difference, and the voltage of the source node becomes higher than the voltage for driving the light emitting diode, which causes the light emitting diode to emit light.

[0107] Figure 6 is a schematic cross-sectional view of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a transistor in the display substrate. In an exemplary embodiment, as shown in Figure 6, the display substrate according to the exemplary embodiment of the present disclosure includes a substrate 101, a second gate electrode 12 and a third gate electrode 13 disposed on the substrate 101, a first insulating layer 51 disposed on the side of the second gate electrode 12 and the third gate electrode 13 facing away from the substrate 101, an active layer 21 disposed on the side of the first insulating layer 51 facing away from the substrate 101, a second insulating layer 52 disposed on the side of the active layer 21 facing away from the substrate 101, a first gate electrode 11 disposed on the side of the second insulating layer 52 facing away from the substrate 101, a third insulating layer 53 disposed on the side of the first gate electrode 11 facing away from the substrate 101, and a first connecting electrode 31 and a second connecting electrode 32 disposed on the side of the third insulating layer 53 facing away from the substrate 101. The first gate electrode 11, the second gate electrode 12, the third gate electrode 13, and the active layer 21 form a transistor in the display substrate. The first gate 11 can serve as the top gate of the transistor; the second gate 12 can serve as the first bottom gate of the transistor, and the second gate 12 is connected to the source terminal of the active layer 21; the third gate 13 can serve as the second bottom gate of the transistor, and the third gate 13 is connected to the first gate 11. The active layer 21 includes a source terminal and a drain terminal, which are located at opposite ends of the active layer 21. The source terminal of the active layer 21 can be used to connect to the source electrode, and the drain terminal of the active layer 21 can be used to connect to the drain electrode.

[0108] In an exemplary embodiment, the first gate 11, the second gate 12, and the third gate 13 all overlap with the orthographic projection of the active layer 21 on the substrate 101. For example, the orthographic projection of the first gate 11 on the substrate 101 is located within the orthographic projection of the active layer 21 on the substrate 101, and at least portions of the second gate 12 and the third gate 13 overlap with the orthographic projection of the active layer 21 on the substrate 101.

[0109] In an exemplary embodiment, the second gate 12 and the third gate 13 may be located in the same film layer, and the orthographic projections of the second gate 12 and the third gate 13 on the substrate do not overlap. In some embodiments, the second gate and the third gate may be located in different film layers. For example, the first gate may be located on the side of the second gate that is away from or close to the substrate.

[0110] In an exemplary embodiment, the second gate 12 and the third gate 13 are located on the side of the active layer 21 close to the substrate, and the first gate 11 is located on the side of the active layer 21 away from the substrate. In some embodiments, the second gate and the third gate may be located on the side of the active layer away from the substrate, and the first gate is located on the side of the active layer close to the substrate.

[0111] In an exemplary embodiment, the second gate 12 and the third gate 13 may be made of conductive materials with different work functions. For example, the second gate 12 may be made of a high-work-function conductive material, such as a high-work-function metal, which may include molybdenum. The third gate 13 may be made of a low-work-function conductive material, such as a low-work-function metal, which may include at least one of aluminum, silver, and zinc.

[0112] The disclosed embodiment shows that the substrate uses a low work function conductive material through the third gate, which can significantly reduce the contact resistance between the second connecting electrode and the third gate, improve the control capability of the third gate, and increase the startup current of the transistor while increasing the subthreshold swing (SS).

[0113] In some embodiments, the second gate and the third gate may be made of a conductive material with the same work function. For example, the second gate and the third gate may be made of the same conductive film layer, including the same conductive material, thereby simplifying the process. The embodiments of the present disclosure are not further described here.

[0114] In an exemplary embodiment, the exemplary embodiment of the present disclosure shows that the substrate further includes a first via 41, a second via 42, a third via 43, and a fourth via 44. The first via 41, the second via 42, the third via 43, and the fourth via 44 all extend in a direction perpendicular to the substrate 101, and the orthographic projections of the first via 41, the second via 42, the third via 43, and the fourth via 44 on the substrate 101 do not overlap. The first via hole 41 extends from the surface of the third insulating layer 53 away from the substrate, penetrates the third insulating layer 53, the second insulating layer 52 and the first insulating layer 51 in sequence, and extends to the second gate 12, exposing at least a portion of the second gate 12. The first connecting electrode 31 is connected to the exposed second gate 12 through the first via hole 41; the second via hole 42 extends from the surface of the third insulating layer 53 away from the substrate, penetrates the third insulating layer 53 and the second insulating layer 52 in sequence, and extends to the source end of the active layer 21, exposing at least a portion of the source end of the active layer 21. The first connecting electrode 31 is connected to the exposed source end of the active layer 21 through the second via hole 42, so that the first connecting electrode 31 connects the second gate 12 to the source end of the active layer 21. The third via 43 extends from the surface of the third insulating layer 53 away from the substrate, penetrates the third insulating layer 53, and extends to the first gate 11, exposing at least a portion of the first gate 11. The second connecting electrode 32 is connected to the exposed first gate 11 through the third via 43; the fourth via 43 extends from the surface of the third insulating layer 53 away from the substrate, penetrates the third insulating layer 53, the second insulating layer 52 and the first insulating layer 51 in sequence, and extends to the third gate 13, exposing at least a portion of the third gate 13. The second connecting electrode 32 is connected to the exposed third gate 13 through the fourth via 44, so that the second connecting electrode 32 connects the first gate 11 and the third gate 13.

[0115] The embodiment of the present disclosure displays a substrate that connects the second gate to the source end (S) of the active layer and the third gate to the first gate, thereby achieving a Bulk Accumulation effect, increasing the subthreshold swing (SS) of the transistor of the display substrate, improving the data range, and maintaining the startup current (Ion) of the transistor from decreasing.

[0116] In an exemplary embodiment, the first insulating layer 51, the second insulating layer 52, and the third insulating layer 53 may be made of an inorganic material, such as an oxygen-silicon compound or a nitrogen-silicon compound. The first insulating layer 51 may be referred to as a first gate insulating layer, isolating the second gate 12 and the third gate 13 from the active layer 21; the second insulating layer 52 may be referred to as a second gate insulating layer, isolating the first gate 11 from the active layer 21.

[0117] Figure 7 is a schematic diagram of the planar structure of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a transistor in the display substrate. In an exemplary embodiment, as shown in Figure 7, the display substrate according to the exemplary embodiment of the present disclosure includes, on a plane parallel to the display substrate, a second gate 12 and a third gate 13 disposed on a substrate, an active layer 21 disposed on a side of the second gate 12 and the third gate 13 away from the substrate, a first gate 11 disposed on a side of the active layer 21 away from the substrate 101, and a first connection electrode 31 and a second connection electrode 32 disposed on a side of the first gate 11 away from the substrate 101.

[0118] In an exemplary embodiment, the exemplary embodiment of the present disclosure further includes a first via 41, a second via 42, a third via 43, and a fourth via 44. The first via 41, the second via 42, the third via 43, and the fourth via 44 all extend in a direction perpendicular to the substrate 101, and the orthographic projections of the first via 41, the second via 42, the third via 43, and the fourth via 44 on the substrate 101 do not overlap. The first connecting electrode 31 is connected to the second gate 12 through the first via 41, and the first connecting electrode 31 is connected to the source terminal of the active layer 21 through the second via 42, thereby connecting the second gate 12 to the source terminal of the active layer 21. The second connecting electrode 32 is connected to the third gate 13 through the third via 43, and the second connecting electrode 32 is connected to the first gate 11 through the fourth via 44, thereby connecting the second connecting electrode 32 to the first gate 11 and the third gate 13.

[0119] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0120] In an exemplary embodiment, the preparation process of the display substrate of this embodiment may include the following operations.

[0121] (11) Forming the second gate and the third gate patterns. In an exemplary embodiment, forming the second gate and the third gate patterns may include: depositing a buffer layer on the substrate at a temperature of 380° C. through a plasma enhanced chemical vapor deposition (PECVD) process; subsequently, depositing a high work function metal film on the buffer layer through a first sputtering process, patterning the high work function metal film through a patterning process, and forming a second gate 12 pattern disposed on the buffer layer; subsequently, depositing a low work function metal film on the buffer layer through a second sputtering process, patterning the low work function metal film through a patterning process, and forming a third gate 13 pattern disposed on the buffer layer; finally, depositing a first insulating film on the second gate 12 and the third gate 13 through a plasma enhanced chemical vapor deposition (PECVD) process at a temperature of 380° C., forming a first insulating layer covering the second gate 12 and the third gate 13, as shown in FIG8 . Among them, the buffer layer can be made of silicon oxide, and the thickness of the buffer layer can be 50 nanometers to 100 nanometers; the first insulating layer can be made of silicon oxide, and the thickness of the first insulating layer can be 100 nanometers to 300 nanometers; the second gate 12 can be made of metal molybdenum; the third gate 13 can be made of at least one of aluminum, silver, and zinc.

[0122] In some embodiments, the third gate pattern may be formed first, and then the second gate pattern may be formed. This embodiment of the present disclosure will not be further described herein.

[0123] In an exemplary embodiment, the second gate 12 may be located on one side of the third gate 13 in the second direction D2 and insulated from the third gate 13. The second gate 12 includes a second electrode portion 121 and a second lead portion 122 that are integrally connected. The second electrode portion 121 may be rectangular, and at least one corner of the second electrode portion 121 may be chamfered. The second lead portion 122 may be linear, with a first end of the second lead portion 122 connected to a side of the second electrode portion 121 opposite the first direction D1. The second end of the second lead portion 122 extends in a direction opposite the first direction D1. The second lead portion 122 may be connected to the first connection electrode via a first via. The first direction D1 and the second direction D2 are both parallel to the plane of the display substrate, intersecting the first direction D1 and the second direction D2. For example, the first direction D1 and the second direction D2 are perpendicular to each other.

[0124] In some embodiments, a shape of an orthographic projection of the second electrode portion on the substrate may include at least one of a triangle, a rhombus, a trapezoid, a circle, an ellipse, a pentagon, and a hexagon.

[0125] In an exemplary embodiment, the third gate 13 may be located on a side of the second gate 12 opposite to the second direction D2 and insulated from the second gate 12. The third gate 13 includes a third electrode portion 131 and a third lead portion 132 that are integrally connected. The third electrode portion 131 may be rectangular in shape, and at least one corner of the third electrode portion 131 may be chamfered. For example, the corner of the third electrode portion 131 facing away from the second gate 12 may be chamfered. The third lead portion 132 may be linear in shape, with a first end connected to a side of the third electrode portion 131 opposite to the second direction D2. The second end of the third lead portion 132 extends in the direction opposite to the second direction D2. The third lead portion 132 may be connected to the second connection electrode via a fourth via.

[0126] In some embodiments, a shape of an orthographic projection of the third electrode portion on the substrate may include at least one of a triangle, a rhombus, a trapezoid, a circle, an ellipse, a pentagon, and a hexagon.

[0127] In an exemplary embodiment, the area of ​​the orthographic projection of the second gate 12 on the substrate is greater than or equal to the area of ​​the orthographic projection of the third gate 13 on the substrate. For example, the area of ​​the orthographic projection of the second electrode portion 121 of the second gate 12 on the substrate is greater than or equal to the area of ​​the orthographic projection of the third electrode portion 131 of the third gate 13 on the substrate.

[0128] In an exemplary embodiment, a ratio of an area of ​​an orthographic projection of the second electrode portion 121 of the second gate 12 on the substrate to an area of ​​an orthographic projection of the third electrode portion 131 of the third gate 13 on the substrate is less than or equal to 2 and greater than or equal to 1. For example, a ratio of an area of ​​an orthographic projection of the second electrode portion 121 of the second gate 12 on the substrate to an area of ​​an orthographic projection of the third electrode portion 131 of the third gate 13 on the substrate is less than or equal to 1.8 and greater than or equal to 1.5.

[0129] The disclosed embodiment shows that the substrate adjusts the compatibility level between the subthreshold swing (SS) of the transistor and the startup current (Ion) of the transistor by adjusting the area ratio of the second gate 12 and the third gate 13 .

[0130] In some embodiments, an area of ​​an orthographic projection of the second electrode portion of the second gate on the substrate may be smaller than an area of ​​an orthographic projection of the third electrode portion of the third gate on the substrate.

[0131] In this exemplary embodiment, a partitioning region 14 is provided between the second gate 12 and the third gate 13. This partitioning region 14 may be filled with a first insulating layer to be formed later. The partitioning region 14 is linear in shape and extends along the first direction D1, separating the second gate 12 from the third gate 13. Opposite sides of the partitioning region 14 in the second direction D2 are the side of the second gate 12 closest to the third gate 13 and the side of the third gate 13 closest to the second gate 12.

[0132] In some embodiments, the segmented regions may be serpentine in shape.

[0133] In an exemplary embodiment, a vertical distance L of the segmentation region 14 in the second direction D2 is greater than or equal to 0.5 microns and less than or equal to 2 microns. For example, the distance L may be greater than or equal to 1 micron and less than or equal to 1.5 microns. The vertical distance L is the vertical distance in the second direction D2 from the edge of the second gate 12 close to the third gate 13 to the edge of the third gate 13 close to the second gate 12.

[0134] In some embodiments, the shape of the segmented area may be a broken line, which will not be further described in detail in the embodiments of the present disclosure.

[0135] (12) Forming an active layer pattern. In an exemplary embodiment, forming the active layer pattern may include: depositing a semiconductor thin film on the first insulating layer at room temperature by a sputtering process on the substrate on which the aforementioned pattern is formed, patterning the semiconductor thin film by a patterning process to form a pattern of the active layer 21 disposed on the first insulating layer; subsequently, depositing a second insulating thin film on the active layer 21 by a plasma enhanced chemical vapor deposition (PECVD) process at a temperature of 380° C. to form a second insulating layer covering the active layer 21, as shown in FIG9a and FIG9b , where FIG9b is a schematic diagram of the active layer in FIG9a .

[0136] In an exemplary embodiment, the active layer 21 includes a channel region 211, and a source terminal 212 and a drain terminal 213 located at opposite ends of the channel region 211 in the first direction D1. The channel region 211 is shaped like an inverted U and protrudes in the direction opposite to the second direction D2. The channel region 211 overlaps with the orthographic projections of the second gate 12 and the third gate 13 on the substrate, respectively. The source terminal 212 is connected to one end of the channel region 211 in the direction opposite to the first direction D1. The source terminal 212 is block-shaped and can be connected to the first connection electrode via a second via. The drain terminal 213 is connected to one end of the channel region 211 in the first direction D1. The drain terminal 213 is block-shaped and can be connected to the source terminal 212 via the channel region 211. The thickness of the active layer 21 may be between 15 and 25 nanometers.

[0137] In an exemplary embodiment, the source terminal 212 of the active layer 21 does not overlap with an orthographic projection of the second lead portion 122 of the second gate 12 on the substrate.

[0138] In an exemplary embodiment, the material of the channel region 211 of the active layer 21 may include polysilicon or a metal oxide. The metal oxide may include indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), or the like. For example, the material of the channel region 211 may be indium gallium oxide, with a weight ratio of indium oxide to gallium oxide in the channel region 211 being 1:1.

[0139] (13) Forming a first gate pattern. In an exemplary embodiment, forming the first gate pattern may include: depositing a first conductive film on the second insulating layer by a sputtering process on the substrate on which the aforementioned pattern is formed, patterning the first conductive film by a patterning process to form a first gate 11 pattern disposed on the second insulating layer; subsequently, depositing a third insulating film on the first gate 11 by a plasma enhanced chemical vapor deposition (PECVD) process at a temperature of 380° C. to form a third insulating layer covering the first gate 11, as shown in FIG10a and FIG10b, where FIG10b is a schematic diagram of the first gate in FIG10a.

[0140] In an exemplary embodiment, the first gate 11 overlaps with the orthographic projection of the active layer 21 on the substrate, and the first gate 11 also overlaps with the orthographic projections of the second gate 12 and the third gate 13 on the substrate. The first gate 11 includes a first electrode portion 111 and a first lead portion 112, which are integrally connected. The first electrode portion 111 can be rectangular in shape and overlap with the orthographic projection of the channel region of the active layer 21 on the substrate. At least one corner of the first electrode portion 111 can be chamfered. For example, all four corners of the first electrode portion 111 are chamfered. The first lead portion 112 can be linear in shape. The first end of the first lead portion 112 is connected to a side of the first electrode portion 111 opposite to the second direction D2. The second end of the first lead portion 112 extends in the direction opposite to the second direction D2. At least a portion of the first lead portion 112 does not overlap with the orthographic projection of the third lead portion of the third gate 13 on the substrate. The first lead portion 112 can be connected to the second connection electrode via a third via.

[0141] In some embodiments, a shape of an orthographic projection of the first electrode portion on the substrate may include at least one of a triangle, a rhombus, a trapezoid, a circle, an ellipse, a pentagon, and a hexagon.

[0142] (14) Forming a first connection electrode and a second connection electrode pattern. In an exemplary embodiment, forming the first connection electrode and the second connection electrode pattern may include: first forming a first via hole 41, a second via hole 42, a third via hole 43, and a fourth via hole 44 on the substrate on which the aforementioned pattern is formed, wherein the first via hole 41, the second via hole 42, the third via hole 43, and the fourth via hole 44 all extend in a direction perpendicular to the substrate 101, and the orthographic projections of the first via hole 41, the second via hole 42, the third via hole 43, and the fourth via hole 44 on the substrate 101 do not overlap. The first via 41 exposes at least a portion of the second gate 12, the second via 42 exposes at least a portion of the source end of the active layer 21, the third via 43 exposes at least a portion of the third gate 13, and the fourth via 44 exposes at least a portion of the first gate 11; subsequently, a second conductive film is deposited on the third insulating layer through a sputtering process, and the second conductive film is patterned through a patterning process to form patterns of the first connecting electrode 31 and the second connecting electrode 32 arranged on the third insulating layer; the first connecting electrode 31 is connected to the second gate 12 through the first via 41, and is connected to the source end of the active layer 21 through the second via 42; the second connecting electrode 32 is connected to the first gate 11 through the third via 43, and is connected to the third gate 13 through the fourth via 44, as shown in Figure 7.

[0143] In an exemplary embodiment, the first connection electrode 31 and the second connection electrode 32 can both be a multi-layer structure. For example, the first connection electrode 31 and the second connection electrode 32 can both include a first conductive layer, a second conductive layer and a third conductive layer stacked along the thickness direction of the substrate. The first conductive layer and the third conductive layer can both be made of metal titanium, and the second conductive layer can be made of metal aluminum.

[0144] In an exemplary embodiment, the first connection electrode 31 and the second connection electrode 32 may both be rectangular in shape. For example, the length of the first connection electrode 31 and the second connection electrode 32 may be 2 to 4 microns, and the width of the first connection electrode 31 and the second connection electrode 32 may be 2 to 4 microns.

[0145] In an exemplary embodiment, the shapes of the first via hole 41 , the second via hole 42 , the third via hole 43 and the fourth via hole 44 may each include at least one of a triangle, a rectangle, a diamond, a trapezoid, a circle, an ellipse, a pentagon and a hexagon.

[0146] Figures 11a and 11b are planar schematic diagrams of another display substrate disclosed herein, with Figure 11b being a schematic diagram of the second and third gate electrodes in Figure 11a. As shown in Figures 11a and 11b, the structure of the display substrate of this exemplary embodiment is substantially the same as that of the display substrate of the embodiment shown in Figure 7, except that the area of ​​the orthographic projection of the second gate electrode 12 of the display substrate of this exemplary embodiment on the substrate is less than or equal to the area of ​​the orthographic projection of the third gate electrode 13 on the substrate. For example, the area of ​​the orthographic projection of the second electrode portion of the second gate electrode 12 on the substrate is less than or equal to the area of ​​the orthographic projection of the third electrode portion of the third gate electrode 13 on the substrate. In an exemplary embodiment, the ratio of the area of ​​the orthographic projection of the second electrode portion of the second gate electrode 12 on the substrate to the area of ​​the orthographic projection of the third electrode portion of the third gate electrode 13 on the substrate is less than or equal to 1 and greater than or equal to 0.1. For example, the ratio of the area of ​​the orthographic projection of the second electrode portion of the second gate electrode 12 on the substrate to the area of ​​the orthographic projection of the third electrode portion of the third gate electrode 13 on the substrate is less than or equal to 0.8 and greater than or equal to 0.5.

[0147] The disclosed embodiment shows that the substrate adjusts the compatibility level between the subthreshold swing (SS) of the transistor and the startup current (Ion) of the transistor by adjusting the area ratio of the second gate 12 and the third gate 13 .

[0148] Figures 12a and 12b are plan views of another display substrate disclosed herein, with Figure 12b being a schematic view of the second and third gates in Figure 12a. As shown in Figures 12a and 12b, the structure of the display substrate of this exemplary embodiment is substantially the same as that of the display substrate of the embodiment shown in Figure 7, with the difference being that the second gate 12 of the display substrate of this exemplary embodiment is located on the side opposite to the third gate 13 in the first direction D1. The segmentation region 14 is linear in shape and extends along the second direction D2, separating the second gate 12 from the third gate 13. The opposing sides of the segmentation region 14 in the first direction D1 are the side of the second gate 12 proximal to the third gate 13, and the side of the third gate 13 proximal to the second gate 12.

[0149] In an exemplary embodiment, a vertical distance L of the segmentation region 14 in the first direction D1 is greater than or equal to 0.5 micrometers and less than or equal to 2 micrometers. For example, the distance L may be greater than or equal to 1 micrometer and less than or equal to 1.5 micrometers.

[0150] Figure 13 is a schematic plan view of another display substrate according to the present disclosure. As shown in Figure 13, the structure of the display substrate of this exemplary embodiment is substantially the same as that of the display substrate of the embodiment shown in Figure 7, with the difference being that the channel region of the active layer 21 of the display substrate of this exemplary embodiment is linear in shape, extends along a first direction D1, and overlaps with the orthographic projections of the first gate 11, the second gate 12, and the third gate 13 on the substrate.

[0151] Figure 14 is a schematic plan view of another display substrate according to the present disclosure. As shown in Figure 14, the structure of the display substrate of this exemplary embodiment is substantially the same as that of the display substrate of the embodiment shown in Figure 12a, with the difference being that the channel region of the active layer 21 of the display substrate of this exemplary embodiment is linear in shape, extends along a first direction D1, and overlaps with the orthographic projections of the first gate 11, the second gate 12, and the third gate 13 on the substrate.

[0152] Figure 15 is a planar schematic diagram of another display substrate disclosed herein. As shown in Figure 15 , the structure of the display substrate of this exemplary embodiment is substantially the same as that of the display substrate of the embodiment shown in Figure 7 , except that the display substrate of this exemplary embodiment further includes a signal line 60. The signal line 60 can be located on the side of the first gate 11 away from the substrate. The main structure of the signal line 60 can be in the shape of a line extending along the second direction D2. The signal line 60 overlaps with the orthographic projection of the segmentation area 14 on the substrate, and the signal line 60 also overlaps with the orthographic projections of the second gate 12 and the third gate 13 on the substrate. Figure 15 only illustrates a portion of the signal line 60. The signal line 60 can be in the shape of a line extending along the second direction D2.

[0153] In an exemplary embodiment, the signal line includes at least one of an initialization signal line, a reference voltage signal line, and a power signal line.

[0154] The disclosed embodiment shows that the substrate overlaps with the orthographic projections of the second gate 12 and the third gate 13 on the substrate through the signal line 60, and a coupling capacitor can be formed with the second gate 12 and the third gate 13 through the signal line 60, thereby regulating the compatibility level of the subthreshold swing (SS) of the transistor and the startup current (Ion) of the transistor.

[0155] The present disclosure also provides a method for preparing a display substrate, comprising:

[0156] forming a second gate and a third gate on the substrate;

[0157] forming an active layer on a side of the second gate and the third gate away from the substrate;

[0158] forming a first gate on a side of the active layer away from the substrate, wherein the first gate, the second gate, and the third gate all overlap with an orthographic projection of the active layer on the substrate;

[0159] The second gate is electrically connected to the active layer, and the third gate is electrically connected to the first gate.

[0160] The present disclosure further provides a display device including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the embodiments of the present invention are not limited thereto.

[0161] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the present invention. Any person skilled in the art may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the present invention shall still be based on the scope defined by the appended claims.

Claims

1. A display substrate, comprising: An active layer disposed on one side of a substrate; A first gate disposed on a first side of the active layer; A second gate disposed on a second side of the active layer, the second gate being electrically connected to the active layer; A third gate disposed on the second side of the active layer, the third gate being insulated from the second gate, and the third gate being electrically connected to the first gate; The first side and the second side are respectively opposite sides of the active layer in a direction perpendicular to the substrate, and the first gate, the second gate and the third gate all overlap the positive projection of the active layer on the substrate.

2. The display substrate according to claim 1, wherein The positive projections of the second gate and the third gate on the substrate do not overlap, and a dividing region is provided between the positive projection of the second gate on the substrate and the positive projection of the third gate on the substrate, and the dividing region is filled with an insulating material.

3. The display substrate according to claim 2, wherein, The second gate is located on one side of the third gate in a second direction, and the shape of the dividing region is linear extending along a first direction; or, the second gate is located on one side of the third gate in a first direction, and the shape of the dividing region is linear extending along a second direction, and the first direction intersects the second direction.

4. The display substrate according to claim 3, wherein, In a plane parallel to the display substrate, the vertical distance of the dividing region in the second direction is greater than or equal to 0.5 micrometers and less than or equal to 2 micrometers.

5. The display substrate according to claim 2, wherein, The second gate is located on one side of the third gate in a first direction, and the shape of the dividing region is linear extending along a second direction, and the first direction intersects the second direction.

6. The display substrate according to claim 5, wherein, In a plane parallel to the display substrate, the vertical distance of the dividing region in the first direction is greater than or equal to 0.5 micrometers and less than or equal to 2 micrometers.

7. The display substrate according to claim 2, wherein, The dividing region is in a polygonal shape; or, the dividing region is in a serpentine trace shape.

8. The display substrate according to any one of claims 1 to 7, further comprising signal lines disposed on the substrate, the signal lines all overlap the positive projections of the second gate and the third gate on the substrate, and the signal lines include at least one of an initialization signal line, a reference voltage signal line, and a power supply signal line.

9. The display substrate according to any one of claims 1 to 7, wherein The area of the positive projection of the second gate on the substrate is greater than or equal to the area of the positive projection of the third gate on the substrate.

10. The display substrate according to claim 9, wherein, The ratio of the area of the positive projection of the second gate on the substrate to the area of the positive projection of the third gate on the substrate is less than or equal to 2 and greater than or equal to 1.

11. The display substrate according to any one of claims 1 to 7, wherein, The area of the positive projection of the second gate on the substrate is less than or equal to the area of the positive projection of the third gate on the substrate.

12. The display substrate as described in claim 11, wherein, The ratio of the area of the positive projection of the second gate on the substrate to the area of the positive projection of the third gate on the substrate is less than or equal to 1 and greater than or equal to 0.

1.

13. The display substrate according to any one of claims 1 to 7, wherein, The second gate includes a high work function conductive material.

14. The display substrate according to any one of claims 1 to 7, wherein, The second gate includes a second electrode portion and a second lead portion connected to each other, and the second lead portion is electrically connected to the active layer.

15. The display substrate according to any one of claims 1 to 7, wherein, The third gate includes a low work function conductive material, and the low work function conductive material includes at least one of aluminum, silver, and zinc.

16. The display substrate according to any one of claims 1 to 7, wherein The third gate includes a third electrode portion and a third lead portion connected to each other, and the third lead portion is electrically connected to the first gate.

17. The display substrate according to any one of claims 1 to 7, wherein, The first gate includes a first electrode portion and a first lead portion connected to the first electrode portion, and the first lead portion is electrically connected to the second gate.

18. The display substrate according to any one of claims 1 to 7, wherein, The material of the active layer includes metal oxide, and the active layer includes a channel region, and the channel region is linear or inverted U-shaped.

19. The display substrate according to any one of claims 1 to 7 further includes a first connection electrode disposed on a side of the active layer away from the substrate, and the first connection electrode is respectively connected to the second gate and the active layer.

20. The display substrate according to any one of claims 1 to 7 further includes a second connection electrode disposed on a side of the active layer away from the substrate, and the second connection electrode is respectively connected to the first gate and the third gate.

21. A display device includes the display substrate according to any one of claims 1 to 20 above.

22. A method for manufacturing a display substrate includes: forming a second gate and a third gate on a substrate; forming an active layer on a side of the second gate and the third gate away from the substrate; forming a first gate on a side of the active layer away from the substrate, and the first gate, the second gate, and the third gate all overlap with a positive projection of the active layer on the substrate; electrically connecting the second gate to the active layer, and electrically connecting the third gate to the first gate.

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