Drive control device and display device

Abstract

The present disclosure pertains to a drive control device and a display device which make it possible to reduce the cost for an LED display. In the present disclosure, a column driver that generates a light emission control signal and that supplies the same to a plurality of LED pixel units, which each comprise a light emitting diode (LED) and an IC driver for controlling light emission of the LED on the basis of the light emission control signal, is connected with the plurality of LED pixel units through one signal wiring in a manner of daisy chain connection, and a wiring layer is formed into a single layer by eliminating crossing of wirings. The present disclosure can be applied to an LED display device of an active drive type.

Description

Drive control device and display device

[0001] The present disclosure relates to a drive control device and an information processing method for a display device, and more particularly to a drive control device and a display device that enable cost reduction of a direct-view LED (Light Emitting Diode) display.

[0002] In recent years, the market for direct-view displays using LEDs (Light Emitting Diodes) has been expanding.

[0003] Several methods have been proposed for driving the LEDs that make up this display, including one called the active method.

[0004] The active method is a method of driving each LED independently, and is characterized by the fact that the LEDs emit light continuously for a long period of time while displaying an image. This makes it possible to produce high brightness with a small current value even when the LED is miniaturized.

[0005] The control circuit that controls the LED light emission using this active driving method is generally mounted on a circuit board as an integrated circuit (IC). The IC controls the LED light emission using the active method based on a light emission control signal supplied via two or three wires.

[0006] For example, a technology has been proposed in which an IC that controls the light emission of each LED arranged in an array controls the light emission of the LEDs using light emission control signals supplied from wiring in the row direction (row line) and wiring in the column direction (column line) (see Patent Document 1).

[0007] International Publication No. 2018 / 056727

[0008] However, when a two-wire or three-wire wiring structure is adopted, the number of substrate layers increases according to the number of wires, which increases the manufacturing costs.

[0009] The present disclosure has been made in view of such circumstances, and in particular aims to reduce the cost of direct-view LED (Light Emitting Diode) displays.

[0010] A drive control device and a display device according to one aspect of the present disclosure include a plurality of LED pixel units each consisting of an LED (Light Emitting Diode) and an emission control unit that controls the emission of the LED based on an emission control signal, and a driver that generates the emission control signal and supplies it to the plurality of LED pixel units, and the plurality of LED pixel units are electrically connected in series to the driver.

[0011] In one aspect of the present disclosure, a light emitting device includes a plurality of LED pixel units each consisting of an LED (Light Emitting Diode) and an emission control unit that controls the emission of the LED based on an emission control signal, and a driver that generates the emission control signal and supplies it to the plurality of LED pixel units, and the plurality of LED pixel units are electrically connected in series to the driver.

[0012] 7 is a diagram illustrating an example of the configuration of an LED display panel in which signal wiring is arranged in a matrix. FIG. 7 illustrates an overview of an LED display panel of the present disclosure in which a plurality of LED pixel units are daisy-chain connected to a single wiring of the present disclosure. FIG. 7 illustrates an example of the configuration of a display system of the present disclosure. FIG. 7 illustrates an example of the configuration of the video wall controller and display unit of FIG. 3. FIG. 7 illustrates an example of the configuration of an LED array panel. FIG. 7 illustrates a first application example of an LED array panel. FIG. 7 illustrates a second application example of an LED array panel. FIG. 7 illustrates an example of the configuration of an LED pixel unit. FIG. 7 illustrates an example of the configuration of signal wiring, power supply wiring, and GND wiring of an LED pixel unit. FIG. 7 illustrates functions realized by an IC provided in an LED pixel unit. FIG. 7 illustrates a communication protocol of the present disclosure. FIG. 7 illustrates a transmission form of a light emission control signal of the present disclosure. FIG. 7 illustrates a light emission timing instruction flag and a read instruction flag. FIG. 7 is a timing chart illustrating the write timing and light emission timing of a light emission control signal. FIG. 7 is a timing chart illustrating the timing of a read operation. FIG. 7 is a flowchart illustrating display processing. FIG. 7 is a flowchart illustrating driver control processing. FIG. 7 is a flowchart illustrating LED drive control processing. FIG. 7 is a flowchart illustrating LED drive control processing. FIG. 7 is a diagram illustrating an arrangement of the LED array panel of FIG. 7 in a second application example. 20 is a diagram showing the LED array panel of FIG. 20 expressed in the wiring layout of FIG. 9. FIG. 21 is a diagram explaining a modified example of the second application example of the LED array panel. FIG. 22 is a diagram showing the LED array panel of FIG. 22 expressed in the wiring layout of FIG. 9. FIG. 23 is a diagram explaining the function realized by the IC of the LED pixel unit of FIG. 23. FIG. 24 is a timing chart explaining the setting operation of the input / output terminals. FIG. 25 is a diagram explaining a state in which the input / output terminals are functioning normally. FIG. 26 is a diagram explaining a deadlock state when the input / output terminals are abnormal. FIG. 27 is a timing chart when resetting the deadlock state of the input / output terminals. FIG. 28 is a flowchart explaining input / output terminal setting processing.

[0013] Preferred embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant description will be omitted.

[0014] Hereinafter, embodiments for implementing the present technology will be described. The description will be made in the following order: 1. Overview of the present disclosure 2. Configuration example of a display system 3. Detailed configuration of a video wall controller and a display unit 4. Configuration example of an LED array panel 5. Configuration example of an LED pixel unit 6. Layout example of an LED pixel unit and signal wiring, power supply wiring, and GND wiring 7. Functions realized by an IC of an LED pixel unit 8. Communication protocol of the present disclosure and operation of a signal detection unit and a signal reproduction unit 9. Transmission form of a light-emitting control signal 10. Light-emitting timing instruction flag and read instruction flag 11. Display processing 12. Driver control processing by a display unit 13. LED drive control processing 14. Modified example of the second application example of an LED array panel 15. Functions realized by the IC of the LED pixel unit in Figures 22 and 23 16. Setting operation of input / output terminals 17. Regarding deadlock and reset 18. Input / output terminal setting processing

[0015] <<1. Overview of the Present Disclosure>> The present disclosure is directed to reducing the cost of direct-view LED (Light Emitting Diode) displays. First, an overview of the present disclosure will be described.

[0016] In recent years, there has been great progress in narrowing the pitch of direct-view displays using LEDs (not organic), and some displays have pixel pitches of less than 1.0 mm.

[0017] Several methods have been proposed for driving the LEDs that make up this display, but in this disclosure, we will use as an example a display device that uses an active method in which small crystal-type LEDs are driven individually and independently as pixels.

[0018] Note that some backlights for LCD (liquid crystal) TVs and the like use a local dimming (partial dimming) method, and even this method includes an active method for driving partial dimming, and similar effects can be achieved by incorporating an IC to which the technology of the present disclosure is applied. However, the explanation will be given using a display device as an example.

[0019] The active method is characterized by the long continuous light emission time of the LED within the display time, which makes it possible to emit high brightness light with a small current value even if the LED is miniaturized (there are currently many LEDs that are 100um x 100um or less).

[0020] The control circuit used for active driving of such LEDs must be mounted on a circuit board as a very small integrated circuit (IC) to drive each pixel individually. The light-emission control signal used to control LED light emission (brightness) is typically a two-wire or three-wire system. An example of a two-wire system is a display device configuration that uses matrix wiring consisting of multiple row wirings and multiple column wirings, as shown in Figure 1.

[0021] The display device 1 in FIG. 1 is composed of an LED pixel unit 2, in which an LED and an IC that controls the LED are integrated, a column control unit (Column Drive) 3, multiple column wirings 4, a row control unit (Row Line Drive) 5, and multiple row wirings 6.

[0022] In the display device 1 of FIG. 1, a plurality of LED pixel units 2 are arranged in an array, and each is connected to a column wiring 4 and a row wiring 6 corresponding to the row and column in which it is arranged, among a plurality of column wirings 4 and a plurality of row wirings 6.

[0023] The column control unit 3 supplies light emission control data to the LED pixel units 2 arranged in an array, with the column wirings 4 as units, while sequentially switching between the LED pixel units 2 row by row.

[0024] The row control unit 5 supplies control signals instructing the writing of light emission control data to the LED pixel units 2 arranged in an array, in units of column wirings 4, while sequentially changing columns.

[0025] As a result, the IC of each LED pixel unit 2 writes the light emission control data supplied from the column control unit 3 via the column wiring 4 at the timing when it receives a control signal instructing writing supplied from the row control unit 5 via the row wiring 6.

[0026] The row control unit 5 supplies control signals by sequentially switching between row wirings 6, and in synchronization with this operation, the column control unit 3 supplies light emission control data by sequentially switching between row wirings 4. In this way, light emission control data is supplied individually to each LED pixel unit 2.

[0027] After all the LED pixel units 2 have written the light emission control data, all the LED pixel units 2 cause their LEDs to emit light based on their respective light emission control data at synchronized timings.

[0028] This configuration reduces the number of wires and enables efficient simultaneous operation of multiple LED pixel unit ICs.

[0029] However, in the display device 1 of FIG. 1, the column wiring 4 and row wiring 6 are necessary, so the substrate wiring has at least a two-layer structure, and further, power supply wiring and GND wiring are also required.

[0030] The layer structure of the substrate associated with such wiring increases costs. Furthermore, with a similar configuration, it may be impossible to achieve a narrow pitch (a pitch of 0.9 mm or less) without increasing the number of layers in the substrate. Furthermore, in the display device 1 shown in Figure 1, the column wiring 4 and row wiring 6 require a column control unit 3 and a row control unit 5, respectively, which increases costs.

[0031] Therefore, in the present disclosure, as shown in FIG. 2, a plurality of LED pixel units are daisy-chained in units of column wiring, thereby forming a single layer of wiring.

[0032] 2, a plurality of LED pixel units 12 are daisy-chained from top to bottom in the figure, with the column wiring 14 of the column control unit 13 as a unit. Power supply wiring 15 and GND wiring 16 are also wired in parallel with the column wiring 14.

[0033] Furthermore, the column control unit 13 generates light emission control data for the adjacent LED pixel unit 12 in sequence from the light emission control data for the LED pixel unit 12 closest to itself, in units of column wiring 14. Each LED pixel unit 12 transmits the light emission control data supplied from the adjacent LED pixel unit 12 closer to the column control unit 13 to the adjacent LED pixel unit 12 farther away, and the light emission control data is transmitted sequentially from the column control unit 13 to the farthest LED pixel unit 12 like a bucket brigade.

[0034] As a result, the column wiring 14, power supply wiring 15, and GND wiring 16 are wired in parallel, eliminating the need for intersecting wiring, making it possible to make the wiring layer including all of them into a single layer, thereby enabling the cost of the substrate to be reduced.

[0035] Furthermore, by adopting a configuration that does not require a row control unit, it is possible to reduce costs.

[0036] <<2. Configuration Example of Display System>> FIG. 3 shows a configuration example of a display system to which the technology of the present disclosure is applied.

[0037] 3 displays video content on a large display configured by arranging multiple display units in a tiled pattern. Note that, although the present disclosure will be described using an example of the display system 21 including multiple display units, the number of display units does not necessarily have to be multiple, and a single display unit may also be used.

[0038] More specifically, the display system 21 comprises a PC (personal computer) 30 , a video server 31 , a video wall controller 32 , and a video wall 33 .

[0039] The PC (personal computer) 30 is a general-purpose computer that accepts operation inputs from a user and supplies commands corresponding to the operation content to the video wall controller 32 .

[0040] The video server 31 is, for example, a server computer, and supplies video signal data such as video content to the video wall controller 32 .

[0041] The video wall controller 32 operates in response to commands supplied from the PC 30, and distributes data consisting of video content image signals to the display units 51-1 to 51-n that make up the video wall 33 for display.

[0042] When there is no need to distinguish between the display units 51-1 to 51-n, they will be simply referred to as display units 51.

[0043] As shown in the upper right corner of Figure 3, the video wall 33 is made up of display units 51-1 to 51-n, each of which has an array of LED pixels, arranged in a tiled pattern.The images displayed by each display unit 51 are combined in a tiled pattern to display a single image across the entire video wall 33.

[0044] The video wall controller 32 performs predetermined signal processing on the data consisting of the video signal of the video content supplied from the video server 31, distributes and supplies the data according to the arrangement of the display units 51-1 to 51-n, controls the individual displays of the display units 51-1 to 51-n, and controls the video wall 33 as a whole to display a single image.

[0045] The video wall controller 32 and the video wall 33 may be integrated into one unit, or may be integrated into one display device (information processing system).

[0046] <<3. Detailed Configuration of Video Wall Controller and Display Unit>> Next, with reference to FIG. 4, a detailed configuration example of the video wall controller 32 and the display unit 51 will be described.

[0047] The video wall controller 32 includes a LAN (Local Area Network) terminal 71, an HDMI (High Definition Multimedia Interface) (registered trademark) terminal 72, a DP (Display Port) terminal 73, a DVI (Digital Visual Interface) terminal 74, a network IF (Interface) 75, an MPU (Micro Processor Unit) 76, a signal input IF 77, a signal processing unit 78, a DRAM (Dynamic Random Access Memory) 79, a signal distribution unit 80, and output IFs 81-1 to 81-n.

[0048] The LAN (Local Area Network) terminal 71 is, for example, a connection terminal for a LAN cable or the like, and is operated by a user to realize communication via LAN with a personal computer (PC) 30, supplying control commands and the like according to the operation content to the video wall controller 32, and supplies the input control commands and the like to the MPU 76 via the network IF 75.

[0049] The LAN terminal 71 may be configured to be physically connected by a wired LAN cable, or may be configured to be connected by a so-called wireless LAN, which is realized by wireless communication.

[0050] The MPU 76 receives control commands from the PC 30 via the LAN terminal 71 and the network IF 75 , and supplies a control signal corresponding to the received control command to the signal processing unit 78 .

[0051] The HDMI terminal 72, DP terminal 73, and DVI terminal 74 are all input terminals for data consisting of video signals, and are connected to, for example, a server computer that functions as a video server 31, and supply data consisting of video signals to a signal processing unit 78 via a signal input IF 77.

[0052] In addition, in Figure 4, an example is shown in which the video server 31 is connected to the HDMI terminal 72, but the HDMI terminal 72, DP terminal 73, and DVI terminal 74 all have different standards and basically have the same functions, so any one of them can be selected and connected as needed.

[0053] Based on the control signal supplied from the MPU 76, the signal processing unit 78 adjusts the color temperature, contrast, brightness, etc. of the data consisting of the video signal supplied via the signal input IF 77, and supplies the adjusted data to the signal distribution unit 80. At this time, the signal processing unit 78 uses the connected DRAM 79 to expand the data consisting of the video signal, executes signal processing based on the control signal, and supplies the signal processing results to the signal distribution unit 80. The signal processing unit 78 also supplies various types of information relating to display, such as the frame rate, as control signals to the signal processing unit 112 of the display unit 51 to which the video signal is supplied.

[0054] The signal distribution unit 80 distributes the data consisting of the signal-processed video signal supplied from the signal processing unit 78, and distributes and transmits the data individually to the display units 51-1 to 51-n via the output IFs 81-1 to 81-n.

[0055] The display unit 51 includes a driver control unit 91 and LED array panels 92-1 to 92-N.

[0056] The driver control unit 91 supplies data consisting of video signals that control the light emission of the LEDs that make up the LED array panels 92-1 to 92-N.

[0057] More specifically, the driver control unit 91 includes a signal input IF 111, a signal processing unit 112, and output IFs 113-1 to 113-N.

[0058] The signal input IF 111 receives input of video signal data supplied from the video wall controller 32 and supplies it to the signal processing unit 112 .

[0059] The signal processing unit 112 corrects the color and brightness of each display unit 51 based on the video signal data supplied from the signal input IF 111, generates light emission control data for setting the light emission intensity of each LED 212 (FIG. 6) that constitutes the LED array panels 92-1 to 92-N, and distributes and supplies the data to the LED array panels 92-1 to 92-N via the output IFs 113-1 to 113-N.

[0060] The LED array panel 92 includes a plurality of LED pixel units 201-1 to 201-N (FIG. 5) arranged in an array.

[0061] The LED array panel 92 includes LEDs 212 (FIG. 6), and controls the light emission of the LEDs 212 using PWM (Pulse Width Modulation) based on data for setting the light emission intensity of the LEDs 212, which is made up of a video signal supplied from the driver control unit 91.

[0062] 5, a configuration example of the LED array panel 92 will be described. The LED array panel 92 is composed of a plurality of LED pixel units 201-1-1 to 201k-m arranged in an array, a column driver 202, a plurality of signal wirings 203, a plurality of power supply wirings 204, and a plurality of GND wirings 205.

[0063] The LED pixel units 201-1-1 to 201k-m are arranged in an array (arranged in k x m in the figure) and are daisy-chained, i.e., connected in a daisy-chain fashion, to multiple signal wirings 203 arranged in the column direction, starting from the column driver 202.

[0064] In addition, a plurality of power supply wirings 204 and a plurality of GND wirings 205 are arranged in parallel to the signal wirings 203, and each LED pixel unit 201 is also connected to the power supply wirings 204 and GND 205, and is driven by power supplied from the power supply wirings 204 and GND wirings 205.

[0065] Furthermore, the LED pixel unit 201 includes an LED 212 (FIG. 6), and controls the light emission of the LED 212, with each of the RGB LEDs 212r, 212g, and 212b constituting one pixel, based on light emission control data supplied from the column driver 202 via the signal wiring 203.

[0066] The column driver 202 is daisy-chained, i.e., connected in a daisy chain, to a plurality of LED pixel units 201 on each of a plurality of signal wirings 203 in the column direction, and sequentially supplies light emission control signals to the LED pixel units 201 via each of the signal wirings 203, starting from the LED pixel unit 201 closest to itself.

[0067] Therefore, when the LED pixel unit 201 acquires and stores the light emission control signal supplied to it, it outputs the light emission control signal for the LED pixel unit 201 connected later than itself from the column driver 202 to the LED pixel unit 201 in the subsequent stage in sequence.

[0068] With this configuration, the signal wiring 203, the power supply wiring 204, and the GND wiring 205 do not cross each other, so that the substrate can be made single-layered, and costs can be reduced.

[0069] When the LED pixel unit 201 makes the LED 212 emit light, it measures the operating voltage of the LED when it emits light, temporarily stores the data as LED status data, and then writes the data as an LED status pulse at a predetermined position in the light emission control signal supplied to other LED pixel units 201 via the signal wiring 203, and outputs the data to the subsequent LED pixel unit 201.

[0070] At this time, the LED pixel unit that receives the LED status data of the preceding LED pixel unit 201 performs an operation on its own LED status data and the LED status data of the preceding LED pixel unit 201, and outputs the data without changing the data length to the succeeding LED pixel unit 201. Note that the operation referred to here is an operation that performs a bit AND or NAND.

[0071] When the column driver 202 instructs the LED pixel unit 201 to read out an LED state pulse, the LED pixel unit 201 reads out the LED state data stored therein, generates an LED state pulse, and sends it back to the column driver 202 .

[0072] When a read command is issued, the LED pixel unit 201 performs a bitwise AND operation (AND) on the LED state data stored therein and the LED state data from the previous stage, generates the result as an LED state pulse, and sends it back to the column driver 202.

[0073] At this time, the LED pixel units 201 other than the LED pixel unit 201 instructed to be read are set in a state in which the LED state pulse of the LED pixel unit 201 read from the LED pixel unit 201 instructed to be read can be transmitted to the column driver 202.

[0074] <First Application Example of LED Array Panel> Furthermore, as shown in an LED array panel 92′ in FIG. 6 , a signal wiring 203′ may be provided as a return line from the last LED pixel unit 201-X-m (X=1 to k) in the daisy chain directly to the column driver 202, so that LED state data is transmitted directly from the last LED pixel unit 201-X-m to the column driver 202.

[0075] In this case, as the LED state data continues to be transmitted sequentially to the subsequent stage, the last LED pixel unit 201-X-m transmits the LED pixel data via the signal wiring 203', which serves as a return line, to the column driver 202, which is the subsequent stage from the LED pixel unit 201-X-m, as shown by the dotted arrow in Figure 6. As a result, a read instruction is no longer necessary, and each LED pixel unit 201 simply transmits the LED pixel data to the subsequent stage. In addition, in this case, by laying out the signal wiring 203', which serves as a return line, adjacent to the signal wiring 203, which serves as the outgoing path, there are no intersecting wirings, which enables the wiring layer to be made single-layered, thereby enabling cost reduction.

[0076] <Second Application Example of LED Array Panel> Furthermore, as shown in an LED array panel 92'' in Fig. 7, the signal wiring 203 may be connected so as to be zigzag in the column direction. That is, in the LED array panel 92'' in Fig. 7, the bottom LED pixel unit 201-1-m in the first column and the bottom LED pixel unit 201-2-m in the second column are connected by a signal wiring 203, and the LED pixel units 201 in the second column are connected in order from bottom to top in the figure. Furthermore, the top LED pixel unit 201-2-1 in the second column and the top LED pixel unit 201-3-1 in the third column are connected by the same signal wiring 203, and the LED pixel units 201 in the third column are connected in order from top to bottom in the figure. Furthermore, the LED pixel unit 201-3-m in the bottom row of the third column and the LED pixel unit 201-4-m in the bottom row of the fourth column are connected by the same signal wiring 203, and the LED pixel units 201 in the fourth column are connected in order from bottom to top in the figure. Then, the LED pixel unit 201-4-1 in the top row of the fourth column is connected to the column driver 202 via signal wiring 203'', which serves as a folded line.

[0077] Even in the configuration shown in the LED array panel 92'' in FIG. 7, the LED pixel units 201 connected by the same signal wiring 203 only need to sequentially transmit LED status data to the subsequent stages, as indicated by the dotted arrows. The last-stage LED pixel unit 201-4-1 only needs to transmit LED status data to the column driver 202 located downstream of itself. Furthermore, by positioning the last-stage LED pixel unit 201 closer to the column driver, as can be seen by comparing FIGS. 6 and 7, the signal wiring 203'' in FIG. 7, which is a folded line, can be shorter and shorter than the signal wiring 203' in FIG. 6, thereby reducing the cost of the device configuration. Furthermore, while FIG. 7 shows an example in which the signal wiring 203 makes two round trips in the column direction, it may make more round trips. Furthermore, by similarly laying out the power supply wiring 204 and the GND wiring 205, there is no crossing of the wiring, and the wiring layer can be made single-layered, thereby reducing costs.

[0078] The configuration of the LED pixel unit 201 in Figures 5 to 7 will be described in detail later with reference to Figure 8. In addition, the following description will be given on the assumption that the LED array panel 92 is the LED array panel 92 in Figure 5, but it may be either the LED array panel 92' in Figure 6 or the LED array panel 92'' in Figure 7.

[0079] <<5. Configuration Example of LED Pixel Unit>> Next, a configuration example of the LED pixel unit 201 will be described with reference to FIG.

[0080] The LED pixel unit 201 includes an IC 211 , an LED 212 , a main function input terminal 213 , a main function output terminal 214 , a power supply terminal 215 , and a GND terminal 216 .

[0081] The IC 211 is driven by power supplied from a power supply terminal 215 connected to the power supply wiring 204 and a GND terminal 216 connected to the GND wiring 205 .

[0082] The IC 211 acquires light emission control data supplied to it from the column driver 202 via the signal wiring 203 and the main function input terminal 213, and outputs light emission control data for the LED pixel unit 201 subsequent to itself to the subsequent LED pixel unit 201 from the main function output terminal 214.

[0083] The IC 211 controls the light emission of the LED 212 based on the light emission control data supplied from the acquired column driver 202 .

[0084] Based on the light emission control data, the IC 211 measures and stores the operating voltage and other data when the LED 212 is made to emit light, records this as LED status data in a predetermined position in the light emission control data of the subsequent LED pixel unit 201, and outputs it to the subsequent LED pixel unit 201.

[0085] When the IC 211 is instructed by the column driver 202 to read the recorded LED state data, it sends the data back to the column driver 202 via the main function input terminal 213 and the signal wiring 203 .

[0086] At this time, the ICs 211 of the LED pixel units 201 other than the LED pixel unit 201 instructed to be read pass through the LED state data sent from the LED pixel unit 201 instructed to be read via the signal wiring 203, the main function output terminal 214, the main function input terminal 213 and the signal wiring 203, and transmit the data to the column driver 202.

[0087] The IC 211 will be described in detail later with reference to FIG.

[0088] The LED 212 is made up of RGB LEDs 212 r, 212 g, and 212 b, each of which has its light emission controlled by an IC 211 and is driven by power supplied from the power supply wiring 204 via a power supply terminal 215 .

[0089] The main function input terminal 213 receives its own light emission control data supplied from the column driver 202 via a signal line, and light emission control data supplied to the LED pixel unit 201 at the subsequent stage.

[0090] At this time, the main function output terminal 214 outputs light emission control data for the LED pixel unit 201 in the subsequent stage, which is supplied from the column driver 202 via the signal wiring 203 , to the subsequent stage via the signal wiring 203 .

[0091] The main function output terminal 214 receives LED state data via the signal wiring 203 from the LED pixel unit 201 in the subsequent stage connected to the signal wiring 203 .

[0092] At this time, the main function input terminal 213 outputs LED state data from the LED pixel unit 201 connected in the subsequent stage to the previous stage via the signal wiring 203 toward the column driver 202 .

[0093] In this way, the main function input terminal 213 is an input terminal whose main function is to receive light emission control data supplied from the column driver 202, but it also functions as an output terminal that outputs LED state data to the column driver 202.

[0094] Similarly, the main function output terminal 214 is an output terminal whose main function is to output light emission control data for the subsequent LED pixel unit 201 supplied from the column driver 202 to the subsequent LED pixel unit 201, but it also functions as an input terminal that accepts LED status data supplied from the subsequent LED pixel unit 201 to the column driver 202.

[0095] <<6. Layout Example of LED Pixel Unit, Signal Wiring, Power Supply Wiring, and GND Wiring>> Next, with reference to FIG. 9, a layout example of the LED pixel unit 201, signal wiring 203, power supply wiring 204, and GND wiring 205 will be described.

[0096] 9, the LED pixel unit 201 is made up of a rectangular substrate, and on the rectangular substrate (toward the viewer in FIG. 9), a main function input terminal 213, a GND terminal 216, a main function output terminal 214, and a power supply terminal 215 are arranged clockwise from the top of the drawing at each corner of the rectangular substrate. An IC 211 is arranged near the center of the rectangular substrate that constitutes the LED pixel unit 201, and an LED 212 is arranged above it (toward the viewer in FIG. 9). In FIG. 9, the LEDs 212 are arranged in the order of LED 212r, 212g, and 212b from the left in the drawing.

[0097] In the rectangular substrate that constitutes the LED pixel unit 201, signal wiring 203 is arranged along the diagonal line in the vertical direction in the figure where the main function input terminals 213 and the main function output terminals 214 are arranged.

[0098] In addition, a power supply wiring 204 is disposed in parallel to the signal wiring 203 below a power supply terminal 215 disposed at the left corner in the figure of the square substrate that constitutes the LED pixel unit 201 .

[0099] Furthermore, a GND wiring 205 is disposed in parallel to the signal wiring 203 below a GND terminal 216 disposed at the right corner of the rectangular substrate that constitutes the LED pixel unit 201 in the drawing.

[0100] With this layout, the signal wiring 203, power supply wiring 204, and GND wiring 205 do not intersect at any points and can be arranged on the same wiring layer, making it possible to make the wiring layer on the substrate that makes up the LED pixel unit 201 a single layer.

[0101] As a result, the LED pixel unit 201 of the present disclosure can reduce manufacturing costs by using a single substrate layer.

[0102] <<7. Functions Realized by IC of LED Pixel Unit>> Next, functions realized by the IC 211 of the LED pixel unit 201 will be described with reference to the functional block diagram of FIG.

[0103] The IC 211 includes a switch 251, a signal detection unit 252, a signal reproduction unit 253, a serial-parallel data conversion unit 254, an IC control data register 255, a light emission control data register 256, a light emission control unit 257, an LED state determination recording unit 258, a bus data switching and timing control unit 259, a bus switching control unit 260, a header pulse generation unit 261, an LED state pulse generation unit 262, and a switch 263.

[0104] The switch 251 is composed of a switching unit 251a and terminals 251b and 251c. The switching unit 251a is controlled by the bus switching control unit 260 and is connected to either the terminal 251b or 251c.

[0105] More specifically, when the IC 211 of the LED pixel unit 201 at a later stage than itself, viewed from the daisy-chain-connected column driver 202, sends LED status data back to the column driver 202 (when reading out based on a read instruction flag), or when it sends LED status data back to the column driver 202 (when reading out based on a read instruction flag), the switching unit 251a is connected to the terminal 251c. This prevents the LED status data from looping inside the IC 211 when it is sent out.

[0106] Conversely, if the IC 211 of the LED pixel unit 201 itself or its downstream side does not send LED status data back to the column driver 202 (if there is no reading based on the read instruction flag), the switching unit 251a is connected to the terminal 251b.

[0107] The signal detection unit 252 detects three types of signals necessary for regenerating the light emission control signal from the clock signal on which the light emission control signal supplied from the column driver 202 is superimposed, and outputs the signals to the signal regeneration unit 253. Details of the signal detection unit 252 will be described later together with the explanation of the clock signal on which the light emission control signal supplied from the column driver 202 is superimposed.

[0108] Based on the three types of detection signals supplied from the signal detection unit 252, the signal reproduction unit 253 distinguishes between a header pulse indicating the start position of the light emission control signal and serial data consisting of 0s or 1s that constitute the light emission control signal, and supplies the header pulse to the bus data switching and timing control unit 259 and supplies the serial data to the serial-parallel data conversion unit 254.

[0109] The serial-to-parallel data conversion unit 254 is controlled by the bus data switching and timing control unit 259 at the timing when the header pulse is supplied, and converts the serial data related to the light emission control signal supplied from the signal reproduction unit 253 into parallel data, and supplies it to the IC control data register 255 and the light emission control data register 256.

[0110] The IC control data register 255 stores IC control data, which is data related to the control of the IC 211, from the parallel data of the light emission control signal supplied from the serial-parallel data conversion unit 254, and supplies it to the light emission control unit 257 and the bus data switching and timing control unit 259 as necessary.

[0111] The light emission control data register 256 stores light emission control data for controlling the light emission of the LED 212 out of the parallel data related to light emission control supplied from the serial-parallel data conversion unit 254, and supplies it to the light emission control unit 257 as necessary.

[0112] The light emission control unit 257 reads out the light emission control data stored in the light emission control data register 256 at the timing specified by the light emission timing instruction flag specified by the IC control data stored in the IC control data register 255, and causes the LED 212 to emit light by PWM (Pulse Width Modulation) control based on the light emission control data.

[0113] At this time, the light emission control unit 257 detects the operating state information such as the operating voltage when the LED 212 emits light, and supplies it to the LED state determination and recording unit 258 .

[0114] The LED state determination recording unit 258 holds the operation state information supplied from the light emission control unit 257 when the LED 212 emits light as LED state data, and supplies it to the LED state pulse generation unit 262 as necessary.

[0115] The bus data switching and timing control unit 259 controls the bus switching control unit 260 at a predetermined timing to switch the data bus connected by the switches 251 and 263, and also controls the operation timing of the serial-parallel data conversion unit 254, header pulse generation unit 261, and LED status pulse generation unit 262.

[0116] More specifically, when the bus data switching and timing control unit 259 detects a header pulse indicating the start of supply of its own light emission control signal among the light emission control signals supplied from the column driver 202 via the signal wiring 203 and the main function input terminal 213, it controls the serial-parallel data conversion unit 254 to start operation, using the detection timing of the header pulse as a trigger to import data related to light emission control based on the light emission control signal.

[0117] At this time, the bus data switching and timing control unit 259 controls the bus switching control unit 260 to connect the switching unit 251a of the switch 251 to the terminal 251b, and also controls the switching units 263a and 263e of the switch 263 to be turned off, so that data is not output to the LED pixel unit in the subsequent stage.

[0118] That is, since a plurality of LED pixel units 201 are connected in a daisy chain to one signal wiring 203, the light emission control signals for the plurality of LED pixel units 201 connected to one signal wiring 203 are supplied in order starting from the LED pixel unit 201 located closest to the column driver 202.

[0119] Therefore, while a light emission control signal is being supplied to itself, IC211 executes the process of capturing its own light emission control signal, and since its own light emission control signal is not required for the subsequent LED pixel unit 201, it does not output it to the subsequent LED pixel unit 201.

[0120] Then, when the process of taking in the light emission control signal into itself is completed and a dummy pulse indicating the start of supplying the light emission control signal to the subsequent LED pixel unit 201 is supplied, the bus data switching and timing control unit 259 controls the header pulse generation unit 261 to replace the dummy pulse set at the head position of the subsequent light emission control signal with a header pulse and output it.

[0121] At this time, the bus data switching and timing control unit 259 controls the bus switching control unit 260 to connect the switching unit 263a of the switch 263 to the terminal 263c, and output a header pulse to the subsequent LED pixel unit 201 instead of a dummy pulse.

[0122] Furthermore, when the output of the header pulse is completed, the bus data switching and timing control unit 259 controls the bus switching control unit 260 to connect the switching unit 263a of the switch 263 to the terminal 263b, and passes through (outputs as is) the light emission control signal supplied from the column driver 202 to the subsequent LED pixel unit 201 via the signal wiring 203 and the main function input terminal 213.

[0123] When transmitting LED status data to the downstream LED pixel unit 201, the bus data switching and timing control unit 259 controls the LED status pulse generation unit 262 to read out the LED status data recorded in the LED status determination recording unit 258 and generate a corresponding LED status pulse.

[0124] At this time, the bus data switching and timing control unit 259 controls the bus switching control unit 260 to connect the switching unit 263a of the switch 263 to the terminal 263d, and transmits an LED state pulse to a predetermined position in the data string of the light emission control signal to the downstream LED pixel unit 201.

[0125] If the IC control data stored in the IC control data register 255 includes a read instruction flag for sending the LED status data back to the column driver 202, the bus data switching and timing control unit 259 controls the LED status pulse generation unit 262 to read the LED status data recorded in the LED status determination recording unit 258 and generate an LED status pulse at the timing specified based on the read instruction flag.

[0126] At this time, the bus data switching and timing control unit 259 controls the bus switching control unit 260 to connect the switching unit 263a of the switch 263 to the terminal 263d and the switching unit 263e to the terminal 263f, thereby transmitting the LED state pulse to the column driver 202.

[0127] At the same time, in the IC 211 of the other LED pixel units 201 for which no read instruction has been issued by the read instruction flag, the switching unit 263a is set to OFF and the switching unit 263e is connected to the terminal 263f.

[0128] As a result, the LED state data transmitted from the LED pixel unit 201 that has been instructed to be read by the read instruction flag is passed through the LED pixel units 201 that have not been instructed to be read in sequence, and transferred to the column driver 202.

[0129] The switch 263 is composed of switching sections 263a and 263e, and terminals 263b to 263d and 263f.

[0130] One end of the switching unit 263 a is connected to the signal wiring 203 to the LED pixel unit 201 in the subsequent stage via the main function output terminal 214 .

[0131] The switching unit 263a is controlled by the bus switching control unit 260, and the other end is switched and connected to a terminal 263b connected to the main function input terminal 213, a terminal 263c connected to the header pulse generating unit 261, and a terminal 263d connected to the LED status pulse generating unit 262.

[0132] One end of the switching unit 263e is connected to the signal wiring 203 to the subsequent LED pixel unit 201 via the main function output terminal 214. The switching unit 263e outputs a signal supplied from the signal wiring 203 of the subsequent LED pixel unit 201 via the main function output terminal 214 to the main function input terminal 213 via the terminal 263f.

[0133] When a light emission control signal is supplied to the switching units 263a and 263e, both the switching units 263a and 263e are set to OFF.

[0134] When a header pulse is supplied to the LED pixel unit 201 in the subsequent stage, the switching unit 263a is connected to the terminal 263c and the switching unit 263e is set to OFF at the timing when the dummy pulse is transmitted.

[0135] When the LED state data is sent to the subsequent LED pixel unit 201, the switching unit 263a is connected to the terminal 263d, and the switching unit 263e is set to OFF.

[0136] When the LED state data is to be transmitted to the column driver 202 based on the read instruction flag, the switching unit 263a is connected to the terminal 263d, and the switching unit 263e is connected to the terminal 263f.

[0137] That is, in this case, the LED state pulse generated by the LED state pulse generating unit 262 is transmitted to the preceding LED pixel unit 201 via the terminal 263d, the switching unit 263a, the switching unit 263e, the terminal 263f, and the main function input terminal 213.

[0138] At this time, in the IC 211 of the other LED pixel unit 201 that has not received the read instruction flag, the switching unit 251a of the switch 251 is connected to the terminal 251c, the switching unit 263a is turned off, and the switching unit 263e is connected to the terminal 263f.

[0139] As a result, the LED state pulse from the LED pixel unit 201 that has received the read instruction flag is passed through by the LED pixel unit 201 provided in the preceding stage, and is then transmitted to the column driver 202 .

[0140] <<8. Communication Protocol of the Present Disclosure and Operations of the Signal Detection Unit and the Signal Regeneration Unit>> Next, with reference to FIG. 11 , the communication protocol of the present disclosure and operations of the signal detection unit 252 and the signal regeneration unit 253 will be described.

[0141] In the present disclosure, as described above, a plurality of LED pixel units 201 are connected in a daisy chain manner to a single signal wiring 203 connected to a column driver 202. For this reason, the light emission control signal needs to be superimposed on a clock signal for transmission.

[0142] Therefore, in the communication protocol of the present disclosure, for each of the signals whose data values ​​are Hi, Lo, and which indicate the header of the light emission control signal, the pulse width (time interval) of the Hi period within one cycle of the clock signal is fixed so that each can be distinguished by the pulse width, thereby superimposing the light emission control signal on the clock signal. Note that the fixed pulse width does not matter in polarity, so it may be the Low period rather than the Hi period.

[0143] FIG. 11 shows a comparison example between waveforms obtained by superimposing the data value Lo, header, and data value Hi as light emission control signals on a clock signal in accordance with the communication protocol of the present disclosure, and output waveforms obtained when the clock signals are simultaneously input to delay circuits 282-1 to 282-3 in signal detection unit 252.

[0144] More specifically, the upper part of Figure 11 shows the waveform of one cycle of the clock signal (CKin(Lo(0))) when an emission control signal corresponding to Lo(0) is superimposed, and the lower part shows an example waveform of the output signal (Delay1) when the clock signal is synchronized and input to delay circuit 282-1.

[0145] Also, the middle part of Figure 11 shows, at the top, an example waveform of one cycle of the clock signal (CKin (STR)) when an emission control signal corresponding to a header (STR) indicating the start of transmission of the emission control signal is superimposed, and, at the bottom, an example waveform of the output signal (Delay2) when the clock signal is synchronized and input to the delay circuit 282-2.

[0146] Furthermore, the lower part of Figure 11 shows, at the top, an example waveform of one cycle of the clock signal (CKin(Hi(1))) when an emission control signal corresponding to Hi(1) is superimposed, and at the bottom, an example waveform of the output signal (Delay3) when the clock signal is synchronized and input to the delay circuit 282-3.

[0147] In this example, the pulse width of one cycle of the clock signal when the light emission control signal corresponding to Lo(0) is superimposed is set to 10 nS.

[0148] Furthermore, the pulse width of one cycle of the clock signal when the light emission control signal corresponding to the header (STR) indicating the start of transmission of the light emission control signal is superimposed is set to 22.5 nS.

[0149] Furthermore, the pulse width of one cycle of the clock signal when a light emission control signal corresponding to Hi (1) is superimposed is set to 35 nS.

[0150] The clock (frequency) of the maximum transmission signal can be set arbitrarily, but FIG. 11 shows an example in which the clock signal is assumed to be 20 MHz (one period = 50 nS) and three values ​​are set: Lo (equivalent to 0), STR (start condition), and Hi (equivalent to 1).

[0151] In this example, the upper limit of the clock frequency is 20 MHz, but even if the clock frequency is lowered (slowed), the pulse width can be freely set relative to the clock frequency by setting a fixed value. Furthermore, since the three values ​​shown in FIG. 11 are distinguished by the pulse width at which the light emission control signal becomes high in the clock signal superimposed thereon, it can be said that the three values ​​are modulated using a PWM (Pulse Width Modulation) method. Therefore, by increasing the variation in the pulse width (time width) at which the light emission control signal becomes high within one cycle of the clock signal, it is possible to set more than three values. Furthermore, if modulation to multiple values, such as three values, is possible, it is not limited to the PWM method, which uses a fixed pulse width, but several patterns may be expressed using, for example, a PAM (Pulse Amplitude Modulation) method, which uses a fixed amplitude.

[0152] Here, the configuration and operation of the signal detection unit 252 will be described in association with the clock signal on which the light emission control signal in FIG. 11 is superimposed.

[0153] The signal detection unit 252 is made up of D latch circuits 281-1 to 281-3 and delay circuits 282-1 to 282-3.

[0154] The delay circuit 282-1 delays the clock signal on which the light emission control signal supplied via the switch 251 is superimposed by 10 nS, and outputs the delayed signal to the enable terminal CK of the D latch circuit 281-1 and to the delay circuit 282-2.

[0155] The D latch circuit 281-1 receives a clock signal on which a light emission control signal supplied via the switch 251 is superimposed at the data terminal D, and outputs the signal to the signal regeneration unit 253 at the timing when the signal input from the delay circuit 282-1, delayed by 10 nS, is input to the enable terminal CK.

[0156] The delay circuit 282-2 delays the clock signal superimposed with the light emission control signal supplied via the switch 251 by 10 nS, and then delays the signal by a further 12.5 nS, i.e., both the delay circuits 282-1 and 282-2 delay the signal by a total of 22.5 nS, and outputs the delayed signal to the enable terminal CK of the D latch circuit 281-2 and to the delay circuit 282-3.

[0157] The D latch circuit 281-2 receives a clock signal on data terminal D and superimposes an emission control signal supplied via switch 251, and outputs the signal to signal regeneration unit 253 at the timing when the signals input from delay circuits 282-1 and 282-2, delayed by a total of 22.5 nS, are input to enable terminal CK.

[0158] The delay circuit 282-3 delays the signal, which is a clock signal superimposed with the light emission control signal supplied via the switch 251 and delayed by 22.5 nS, by a further 12.5 nS, i.e., the delay circuits 282-1 to 282-3 delay the signal by a total of 35 nS, and outputs it to the enable terminal CK of the D latch circuit 281-3.

[0159] The D latch circuit 281-3 receives a clock signal on which a light emission control signal supplied via the switch 251 is superimposed at the data terminal D, and outputs the signal to the signal regeneration unit 253 at the timing when the signal received is delayed by a total of 35 nS by the delay circuits 282-1 to 282-3 and input to the enable terminal CK.

[0160] With this configuration, as shown in the top row of Figure 11, when a clock signal with a pulse width of 10 nS (+5 nS) is supplied on which an emission control signal corresponding to Lo (0) is superimposed, at the timing when an enable signal (Delay1) is supplied from the delay circuit 282-1 to the D latch circuit 281-1, a value of 1 is input to the data terminal D, and therefore a value of 1 is output from the output terminal Q of the D latch circuit 281-1.

[0161] However, when a clock signal with a pulse width of 10 nS (+5 nS) on which a light emission control signal corresponding to Lo (0) is superimposed is supplied, at the timing when enable signals (Delay2, 3) are supplied from the delay circuits 282-2, 282-3 to the D latch circuits 281-2, 281-3, respectively, 0 is input to the data terminal D, and therefore 0 is output from the output terminal Q of the D latch circuits 281-2, 281-3.

[0162] Furthermore, as shown in the middle of Figure 11, when a clock signal with a pulse width of 22.5 nS (+5 nS) is supplied on which an emission control signal corresponding to a header (STR) indicating the start of transmission of the emission control signal is superimposed, at the timing when enable signals (Delay1, 2) are supplied from the delay circuits 282-1, 282-2 to the D latch circuits 281-1, 281-2, respectively, a value of 1 is input to the data terminal D, and therefore a value of 1 is output from the output terminal Q of the D latch circuits 281-1, 281-2.

[0163] However, when a clock signal with a pulse width of 22.5 nS (+5 nS) is supplied on which an emission control signal corresponding to a header (STR) indicating the start of transmission of the emission control signal is superimposed, at the timing when an enable signal (Delay3) is supplied from the delay circuit 282-3 to the D latch circuit 281-3, 0 is input to the data terminal D, and therefore 0 is output from the output terminal Q of the D latch circuit 281-3.

[0164] Furthermore, as shown in the lower part of Figure 11, when a clock signal with a pulse width of 35 nS (+5 nS) on which a light emission control signal corresponding to Hi (1) is superimposed is supplied, at the timing when an enable signal (Delay1, 2, 3) is supplied from each of delay circuits 282-1 to 282-3 to D latch circuits 281-1 to 281-3, 1 is input to each data terminal D, and therefore 1 is output from each output terminal Q of D latch circuits 281-1 to 281-3.

[0165] On the other hand, the signal reproduction unit 253 has a built-in signal determination unit 271, which determines whether the type of the light emission control signal superimposed on the clock signal is Lo (0), Hi (1), or header (STR) based on the combination of output signals Lo, Mid, and Hi from the D latch circuits 281-1 to 281-3, and outputs serial data or a header pulse based on the determination result.

[0166] More specifically, the signal reproduction unit 253 has a built-in signal determination unit 271 that stores a table 271a shown in the center of Figure 10, and the signal determination unit 271 determines the type of light emission control signal superimposed on the clock signal based on the combination of output signals Lo, Mid, and Hi from the D latch circuits 281-1 to 281-3.

[0167] That is, in the table 271a, from the top, the output signals of the D latch circuits 281-1 to 281-3 are written as combinations of Lo, Mid, and Hi in order from the left for each of Lo (0), header (STR), and Hi (1).

[0168] That is, as described above, when the combination (Lo, Mid, Hi) of the output signals of the D latch circuits 281-1 to 281-3 is (1, 0, 0), the signal determination unit 271 determines that the light emission control signal is a signal corresponding to Lo (0).

[0169] Furthermore, when the combination (Lo, Mid, Hi) of the output signals of the D latch circuits 281-1 to 281-3 is (1, 1, 0), the signal determination unit 271 determines that the light emission control signal is a signal corresponding to the header (STR).

[0170] Furthermore, when the combination (Lo, Mid, Hi) of the output signals of the D latch circuits 281-1 to 281-3 is (1, 1, 1), the signal determination unit 271 determines that the light emission control signal is a signal corresponding to Hi (1).

[0171] As described above, the signal detection unit 252 determines a combination of three values ​​according to the pulse width of the Hi pulse, and the signal reproduction unit 253 reproduces the header pulse or serial data of the light emission control signal from the combination of three values.

[0172] <<9. Transmission Mode of Light-Emission Control Signals>> Next, the transmission mode of light-emission control signals according to the present disclosure will be described with reference to Fig. 12. In the upper part of Fig. 12, a configuration is shown in which ICs 212-1, 212-2, etc. of LED pixel units 201 are connected in a daisy chain from the column driver 202 to a single signal wiring 203 from the column driver 202, extending from left to right in the figure. In addition, the upper part of the lower part of Fig. 12 shows an example of a transmission mode of a light-emission control signal from the column driver 202 to IC 211-1 of the LED pixel unit 201 connected adjacently thereto, and the lower part of the lower part of Fig. 12 shows an example of a transmission mode of a light-emission control signal to IC 211-2 of the LED pixel unit 201 that is located downstream of IC 211-1 of the LED pixel unit 201.

[0173] The column driver 202 transmits the light emission control signal to IC211-1 of the nearest daisy-chained LED pixel unit 201, then transmits the light emission control signal to IC211-2 of the succeeding LED pixel unit 201, and thereafter transmits the light emission control signal to IC211 of the succeeding LED pixel unit 201 in succession.

[0174] The data length of the light emission control signal transmitted to each IC 211 is fixed as a constraint. The data length of the light emission control signal may be set to a fixed value during IC design, or may be variable by providing a setting terminal in the IC for changing the data length. Alternatively, the initial data length may be set to a fixed value, allowing the data length to be changed during initial setup. Note that FIG. 12 illustrates an example in which the data length for one transmission consists of a header of a predetermined data length and 64-bit payload data.

[0175] After transmitting the clock signal with the header (STR) having the pulse width of 27.5 nS superimposed thereon, the column driver 202 transmits 64 bits of serial data corresponding to the Hi (1) or Lo (0) as one frame of data for IC211-1.

[0176] Next, the column driver 202 inserts dummy data (Dummy) into the position corresponding to the header for the IC 211-2 of the LED pixel unit 201 in the next stage, and then transmits a 64-bit light emission control signal for one frame to the IC 211-2.

[0177] Thereafter, the column driver 202 sequentially inserts dummy data (Dummy) into the position corresponding to the header for the IC 211 of the LED pixel unit 201 in the next stage, and then repeats the process of transmitting a 64-bit light emission control signal for one frame until it has been transmitted to IC 211-n (assuming that n LED pixel units 201 are daisy-chained) of the LED pixel unit 201 connected at the end of the signal wiring 203.

[0178] On the other hand, when IC211-1 receives the clock signal that serves as the header, it recognizes that the subsequent signals are its own light emission control signals, sequentially acquires and stores the data string, and stops transmitting to subsequent stages. At this time, in the example of Figure 12, it acquires a 64-bit data string as one frame's worth of light emission control signal.

[0179] Then, IC211-1 acquires its own light emission control signal, and when it recognizes the dummy data (Dummy) of the light emission control signal for IC211-2 of the LED pixel unit 201 one stage later, it controls the header pulse generation unit 261 to replace it with a header (STR), and outputs the subsequent light emission control signals sequentially to IC211-2 of the LED pixel unit 201 one stage later.

[0180] Similarly to IC211-1, when IC211-2 and subsequent ICs recognize dummy data (Dummy), they control the header pulse generating unit 261 to replace it with a header (STR) and repeat the process of transmitting it to IC211 of the LED pixel unit 201 in the next stage.

[0181] <<10. Light Emission Timing Instruction Flag and Readout Instruction Flag>> Next, the light emission timing instruction flag and the readout instruction flag will be described with reference to FIG.

[0182] This section explains a case where the column driver 202 writes a light emission timing instruction flag EF and a read instruction flag RF into the light emission control signal sent to IC 211-n of the LED pixel unit 201 connected to the end of the daisy-chained signal wiring 203, as shown in FIG. 13, for example.

[0183] The light emission timing instruction flag EF and the read instruction flag RF are both information written to fixed flag bits, and are information that specifies the light emission timing and the read timing.

[0184] As described above, the light emission control signal to IC 211-n of the LED pixel unit 201 connected at the end of the daisy-chained signal wiring 203 passes through all of the ICs 211 in the previous stage before being transmitted to IC 211-n.

[0185] Therefore, when a light emission control signal to IC 211-n of the LED pixel unit 201 connected at the end passes through each IC, the ICs 211 acquire the light emission timing and readout timing as IC control data based on the information of the flag bits corresponding to the light emission timing instruction flag EF and readout instruction flag RF, and store this in the IC control data register 255. Note that each LED pixel unit 201 reads the light emission control signal with a header (STR (FIG. 13)) added to the start position by the immediately preceding LED pixel unit 201 as its own, but since the other light emission control signals have dummy data DM (FIG. 13) added to the start position, the light emission timing instruction flag EF and readout instruction flag RF are acquired from among these, from predetermined flag bits of the light emission control signal of the LED pixel unit 201 connected at the end.

[0186] As a result, the light emission control unit 257 in each IC 211 causes the LED 212 to emit light at synchronized timing based on the light emission timing instruction flag EF.

[0187] That is, this is turned into a timing chart as shown in Figure 14. In Figure 14, the vertical axis represents rows L1 to Lm in which LED pixel units 201 are arranged in order from the top of the figure to the row closest to the column driver 202 in each of the LED array panels 92-n and 92-(n+1), and the horizontal axis represents the time direction.

[0188] That is, from time t0 to t1, the IC 211 of the LED pixel unit 201 in row L1 closest to the column driver 202 writes light emission control data based on the first light emission control signal. Thereafter, the writing of light emission control data progresses for the IC 211 of the LED pixel unit 201 successively closer to the column driver 202. The thick line in Figure 14 is represented as a straight line sloping downward to the right, because over time, the LED pixel units 201 in rows that are progressively farther away from the column driver 202 write light emission control data. Then, at time t1, when writing in the IC 211 of the LED pixel unit 201 in the final row Lm is completed, the writing period Tw ends.

[0189] By this time, the light emission control signal for the final row Lm has passed through the ICs 211 of all of the LED pixel units 201 from rows L1 to Lm, and therefore the light emission timing instruction flag EF recorded in the flag bit at a predetermined position of the light emission control signal for the final row Lm is also recognized by the ICs 211 of all of the LED pixel units.

[0190] Therefore, when the light emission control signal for the last row Lm is written with light emission control data including the light emission timing instruction flag EF, all LED pixel units 201 synchronously cause the LEDs 212 to emit light for one frame during the period from time t1 to time t12.

[0191] Then, at time t11, which is a writing period Tw before time t12 when the light emission period for one frame ends, writing of the light emission control data for the next frame begins, and when the light emission period of the previous frame ends at time t12, the light emission period for the next frame begins, and the same operation is repeated thereafter.

[0192] The read instruction flag RF is set in the same manner as the light emission timing instruction flag EF. That is, for example, the read instruction flag RF is set for the IC 211 of the last LED pixel unit 201, as shown in the lower right of Figure 13, and a read instruction is issued in the subsequent period RT based on the read instruction flag RF.

[0193] In this case, as in the case of the light emission timing instruction flag EF, a light emission control signal including the read instruction flag RF is transmitted to the IC211 of the last LED pixel unit 201, but before the IC211 of the last LED pixel unit 201 acquires it, the IC211 of all of the LED pixel units 201 in the previous stages have grasped the flag bits of the read instruction flag RF.

[0194] Therefore, the bus data switching and timing control unit 259 in each IC 211 other than the last one controls the bus switching control unit 260 at synchronized timing during the last period PT corresponding to the period RT based on the read instruction flag RF to connect the switching unit 251 a of the switch 251 to the terminal 251 c, turn off the switching unit 263 a of the switch 263, and connect the switching unit 263 e to the terminal 263 f. This allows the read data from the IC 211 of the LED pixel unit 201 in the subsequent stage to be passed through to the column driver 202.

[0195] In addition, the bus data switching and timing control unit 259 in the last IC 211 controls the bus switching control unit 260 at synchronized timing during the period RT corresponding to the last period PT described above based on the read instruction flag RF, to connect the switching unit 251a of the switch 251 to the terminal 251c, connect the switching unit 263a of the switch 263 to the terminal 263d, and connect the switching unit 263e to the terminal 263f.

[0196] Then, the bus data switching and timing control unit 259 controls the LED status pulse generation unit 262 to generate an LED status pulse from the LED status data, and transmits it to the column driver 202 by passing it through the ICs 211 of all LED pixel units 201 in the preceding stages.

[0197] Here, the last IC 211 requires a clock signal even when performing read processing based on the read instruction flag, and therefore, as shown in Fig. 15, of the clock signals supplied from the column driver 202, only the portion of the clock signal drawn by the thin line after a predetermined period (after 5 ns in Fig. 15) from the rising edge of the clock signal is used as the clock signal to set the period indicated by the thick black line. In this readout, by setting the width of the thick black line in Fig. 15 to have variations, it is possible to set more than three values, not just the three values ​​shown in Fig. 15.

[0198] <<11. Display Processing>> Next, the display processing by the display system 21 in FIG. 4 will be described with reference to the flowchart in FIG.

[0199] In step S11, the signal processing unit 78 receives an input of a video signal consisting of content data or the like supplied from the video server 31 via one of the HDMI terminal 72, the DP terminal 73, and the DVI terminal 74 and the signal input IF 77.

[0200] In step S12, the signal processing unit 78 converts the video format of the received input video signal.

[0201] In step S13, the signal processing unit 78 receives the input of a control signal supplied from the MPU 76 in response to the operation of the PC 30, and executes signal processing such as color temperature, contrast, and brightness.

[0202] In step S14, the signal processing unit 78 allocates and distributes the processed video signals to the display units 51-1 to 51-n of the video wall 33.

[0203] In step S15, the signal processing unit 78 transmits and outputs the distributed video signals to the corresponding display units 51-1 to 51-n.

[0204] In step S16, when the distributed video signal is displayed on each of the corresponding display units 51-1 to 51-n, the signal processing unit 78 acquires LED status data indicating whether or not there is an abnormality in the light emission of the LED 212, and feeds this data back to the PC 30 and the video server 31.

[0205] Through the above series of processes, the video signal read from the video server 31 is subjected to signal processing and distributed to each of the display units 51-1 to 51-n that make up the video wall 33, and the signals are transmitted, causing the individual images to be displayed on the display units 51-1 to 51-n, thereby enabling the video content images to be displayed across the entire video wall 33. Furthermore, since any abnormalities in the operating voltage of the LEDs 212 when the video content images are displayed are fed back, it becomes possible to detect any abnormalities associated with the light emission of the LEDs 212 at an early stage.

[0206] <<12. Driver Control Processing by Display Unit>> Next, driver control processing by the display unit 51 will be described with reference to the flowchart of FIG.

[0207] In step S31, the signal processing unit 112 in the driver control unit 91 of the display unit 51 receives the input of the video signals distributed and supplied from the video wall controller 32 via the signal input IF 111 on a row-by-row basis.

[0208] In step S32, the signal processing unit 112 performs video signal processing on the row-by-row video signals distributed as the display units 51, such as applying color and brightness correction corresponding to each display unit 51.

[0209] In step S33, the signal processing unit 112 allocates the row-by-row video signals that have been subjected to the video signal processing to the LED array panels 92-1 to 92-N and transmits them via the corresponding output IFs 113-1 to 113-N.

[0210] In step S34, the daisy-chained LED pixel units 201-1 to 201-m in the LED array panel 92 each receive a video signal via the signal wiring 203, and perform LED drive control processing based on the received video signal, thereby displaying an image at an appropriate brightness by PWM control of each LED 212. The LED drive control processing will be described in detail later with reference to FIGS.

[0211] In step S35, the LED pixel units 201-1 to 201-m perform the LED drive control process, thereby feeding back LED state data, including the drive voltage of the LEDs 212 when the image of the immediately preceding frame was displayed, to the signal processing unit 112. The signal processing unit 112 feeds back the LED state data to the signal processing unit 78 of the wall controller 32.

[0212] Through the above processing, the brightness of each of the display units 51 that make up the video wall 33 is adjusted appropriately, and the images are output to the LED array panel 92, allowing the images to be displayed sequentially.

[0213] At this time, LED status data, such as the operating voltage of the LED 212, that can be used to check for operational abnormalities can be fed back to the wall controller 32, allowing for a rapid response to any abnormalities in the LED 212.

[0214] <<13. LED Drive Control Processing>> Next, the LED drive control processing in the LED array panel 92 will be described with reference to the flowcharts of FIGS.

[0215] In step S51 ( FIG. 18 ), the bus data switching and timing control unit 259 controls the bus switching control unit 260 to connect the switching unit 251 a of the switch 251 to the terminal 251 b and the switching unit 263 a of the switch 263 to the terminal 263 b. This enables the signal detection unit 252 to receive a clock signal on which a light emission control signal is superimposed, which is supplied from the column driver 202 via the signal wiring 203 and the main function input terminal 213, and to output the clock signal to the downstream LED pixel unit 201 via the main function output terminal 214 and the signal wiring 203.

[0216] In step S52, the signal detection unit 252 detects the presence or absence of detection signals of three types of pulse widths from the clock signal on which the light emission control signal is superimposed, to determine whether the light emission control signal corresponds to Lo (0), header (STR), or Hi (1), and outputs the result to the signal reproduction unit 253.

[0217] In step S53, the signal reproduction unit 253 controls the signal determination unit 271 to determine whether the light emission control signal corresponds to Lo (0), a header pulse (STR), or Hi (1) based on the patterns of the three types of signals supplied from the signal detection unit 252.

[0218] Then, based on the determination, the signal regeneration unit 253 outputs a light emission control signal corresponding to the header pulse (STR) to the bus data switching and timing control unit 259, and treats the light emission control signals corresponding to Lo (0) and Hi (1) as serial data and supplies them to the serial-parallel data conversion unit 254.

[0219] In the following description of the processing, the description of the processing by the signal detection unit 252 and the signal reproduction unit 253 in steps S52 and S53 will be omitted, and the description will proceed on the assumption that a header pulse and serial data are output sequentially from a clock signal onto which sequentially supplied light emission control signals are superimposed.

[0220] In step S54, the bus data switching and timing control section 259 determines whether or not a header pulse has been detected.

[0221] If it is determined in step S54 that the light emission control signal corresponds to the header pulse (STR), the process proceeds to step S55.

[0222] In step S55, the bus data switching and timing control unit 259 disconnects the terminal 263b of the switching unit 263a of the switch 263, turning it off, and prevents the clock signal on which the light emission control signal is superimposed from being output to the IC 211 of the downstream LED pixel unit 201.

[0223] In step S56, the bus data switching and timing control unit 259 operates the serial-to-parallel data conversion unit 254 to convert the serial data of a predetermined number of bits (64 bits in the above-described embodiment) supplied sequentially by the signal detection unit 252 and the signal reproduction unit 253 into parallel data, and stores the IC control data in the IC control data register 255 and the light emission control data in the light emission control data register 256.

[0224] In step S57, the bus data switching and timing control unit 259 determines whether or not a dummy pulse has been supplied to the IC control data register 255. If it is determined in step S57 that a dummy pulse has not been supplied, the process returns to step S56. That is, the process of step S56 is repeated until a dummy pulse is supplied.

[0225] If it is determined in step S57 that a dummy pulse has been supplied, the process proceeds to step S58.

[0226] In step S58, the bus data switching and timing control unit 259 controls the bus switching control unit 260 to connect the switching unit 263a of the switch 263 to the terminal 263b, and also controls the header pulse generating unit 261 to generate a header pulse, replace the dummy pulse with the header pulse, and output it.

[0227] In step S59, the bus data switching and timing control unit 259 connects to the terminal 263b of the switching unit 263a of the switch 263, and resumes outputting the clock signal on which the light emission control signal is superimposed to the IC 211 of the LED pixel unit 201 in the subsequent stage.

[0228] If it is determined in step S54 that the header pulse has not been supplied, the processes of steps S55 to S59 are skipped.

[0229] In step S60, the light emission control unit 257 accesses the IC control data register 255 and determines whether the flag bit of the light emission timing instruction flag is turned on.

[0230] If it is determined in step S60 that the flag bit of the light emission timing instruction flag is turned on, the process proceeds to step S61.

[0231] In step S61, the light emission control unit 257 stores in the IC control data register 255 that the light emission timing instruction flag is on, and recognizes the light emission timing.

[0232] If it is determined in step S60 that the flag bit of the light emission timing instruction flag is not on, the process of step S61 is skipped.

[0233] In step S62, the bus data switching and timing control unit 259 determines whether or not it has been notified by the IC control data register 255 that the flag bit of the read instruction flag is on.

[0234] If it is determined in step S62 that the flag bit of the read instruction flag is on, the process proceeds to step S63.

[0235] In step S63, the bus data switching and timing control unit 259 memorizes that the flag bit of the read instruction flag is on, and recognizes the timing of the read process. Note that the read instruction flag may indicate that the read process is to be performed by the bus data switching and timing control unit 259 itself, or that the read process is to be performed by the IC 211 of the LED pixel unit 201 at the subsequent stage, so the bus data switching and timing control unit 259 recognizes which of the two is the case.

[0236] If it is determined in step S62 that the flag bit of the read instruction flag is not on, the process of step S63 is skipped.

[0237] In step S64 (FIG. 19), the light emission control unit 257 determines, based on the light emission timing instruction flag stored in the IC control data register 255, whether or not the light emission timing has arrived.

[0238] If it is determined in step S64 that it is time to emit light, the process proceeds to step S65.

[0239] In step S 65 , the light emission control unit 257 causes the LED 212 to emit light based on the light emission control data stored in the light emission control data register 256 .

[0240] In step S66, the light emission control unit 257 reads out the operating voltage when the LED 212 emits light and the like as LED state information, and records it in the LED state determination recording unit 258. Note that if it is determined in step S64 that it is not time to emit light, the processes of steps S65 and S66 are skipped.

[0241] In step S67, the bus data switching and timing control unit 259 determines whether it is time to output an LED state pulse to the IC 211 of the LED pixel unit 201 at the subsequent stage.

[0242] If it is determined in step S67 that it is time to output the LED state pulse to the IC 211 of the LED pixel unit 201 at the subsequent stage, the process proceeds to step S68.

[0243] In step S68, the bus data switching and timing control unit 259 controls the bus switching control unit 260 to control the switching unit 263a of the switch 263 to connect to the terminal 263d. The bus data switching and timing control unit 259 also controls the LED status pulse generation unit 262 to generate an LED status pulse based on the LED status data recorded in the LED status determination recording unit 258, and outputs it to the IC 211 of the subsequent LED pixel unit 201 via the switch 263, the main function output terminal 214, and the signal wiring 203. Note that in step S67, if it is not the timing to output the LED status pulse to the IC 211 of the subsequent LED pixel unit 201, the processing of step S68 is skipped.

[0244] In step S69, the bus data switching and timing control unit 259 determines whether it is time to read out the IC 211 of the LED pixel unit 201 at the subsequent stage, based on the read instruction flag.

[0245] If it is determined in step S69 that it is time to read out the IC 211 of the LED pixel unit 201 at the subsequent stage, the process proceeds to step S70.

[0246] In step S70, the bus data switching and timing control unit 259 controls the bus switching control unit 260 to connect the switching unit 251a of the switch 251 to the terminal 251c, thereby stopping the inflow of signals to the signal detection unit 252.

[0247] In addition, the bus data switching and timing control unit 259 controls the switching unit 263a of the switch 263 to be turned off, and connects the switching unit 263e to the terminal 263f, so that the LED state pulse from the IC 211 of the downstream LED pixel unit 201 is passed through and transmitted to the column driver 202.

[0248] If it is determined in step S69 that it is not time to read out the IC 211 of the LED pixel unit 201 at the subsequent stage, the process of step S70 is skipped.

[0249] In step S71, the bus data switching and timing control unit 259 determines whether it is time for it to supply an LED state pulse to the column driver 202 based on the read instruction flag.

[0250] In step S71, if it is determined based on the read instruction flag that it is time for the pixel to supply its own LED state pulse to the column driver 202, the process proceeds to step S70.

[0251] In step S70, the bus data switching and timing control unit 259 controls the bus switching control unit 260 to connect the switching unit 251a of the switch 251 to the terminal 251c, thereby stopping the inflow of signals to the signal detection unit 252.

[0252] Furthermore, the bus data switching and timing control unit 259 connects the switching unit 263a of the switch 263 to the terminal 263d, and also connects the switching unit 263e to the terminal 263f.

[0253] Then, the bus data switching and timing control unit 259 controls the LED status pulse generation unit 262 to read its own LED status data recorded in the LED status determination recording unit 258, generate an LED status pulse, and transmit it to the column driver 202.

[0254] At this time, the ICs 211 of all LED pixel units 201 in the preceding stages are in read mode due to the operation of step 70 described above, so the LED state pulses of the ICs 211 of all LED pixel units 201 output by the ICs 211 are transferred to the column driver 202.

[0255] If it is determined in step S71 that it is not the timing to read out the LED state data and supply it to the column driver 202 as an LED state pulse, the process of step S72 is skipped.

[0256] In step S73, it is determined whether or not an instruction to end the process has been given. If an instruction to end the process has not been given, the process returns to step S51 (FIG. 16) and the subsequent steps are repeated.

[0257] Then, in step S73, if an instruction to end the process is given, the process ends.

[0258] By the above processing, even if multiple LED pixel units 201 are daisy-chained from the column driver 202 to the single signal wiring 203, it is possible to transfer a light emission control signal individually from the column driver 202 to each of the ICs 211 of the LED pixel units 201.

[0259] Furthermore, since it is possible to daisy-chain multiple LED pixel units 201 in units of columns, single-layer wiring can be realized, which makes it possible to reduce the cost of the display device. Furthermore, since the wiring length can be shortened, high-speed transfer can be achieved.

[0260] Furthermore, since the light emission control signal can be superimposed on the clock signal and transmitted, there is no need to provide separate terminals for the clock signal and the light emission control signal in IC 211 of LED pixel unit 201, which makes it possible to reduce the size and cost of the LED pixel unit.

[0261] In addition, not only does the column driver 202 unilaterally send a light emission control signal to the daisy-chained LED pixel units 201, but half-duplex communication is realized to feed back LED status information in the LED pixel units 201, making it possible to grasp the operating status of the LEDs 212.

[0262] In the above, an example has been described in which the ICs 211 of multiple LED pixel units 201 are daisy-chained together using a single signal wiring by superimposing the light emission control signal on the clock signal. However, the wiring for the light emission control signal and the wiring for the clock signal may be separate, and the ICs 211 of multiple LED pixel units 201 may be daisy-chained together using two wirings.

[0263] In this case, the number of wirings increases compared to when the light emission control signal is superimposed on the clock signal and the signal wiring is made one line, but the daisy chain connection allows the wiring layer to be a single layer, so the number of wiring layers can be reduced compared to when wiring is in a matrix, making it possible to reduce costs. Also, since there is no matrix wiring, only a column driver is required and no row driver is required, making it possible to reduce costs.

[0264] <<14. Modified Example of the Second Application Example of the LED Array Panel>> In the LED array panel 92″ in FIG. 7, the signal wiring 203 is connected so as to be folded back zigzag in the column direction. This causes the signal wiring 203″ in FIG. 7 to be folded back, thereby saving the length of the signal wiring and reducing the number of input / output wirings from the column driver 202, thereby making it possible to reduce the cost of the device configuration.

[0265] In such a case, for example, when comparing LED pixel units 201-1-2 and 201-2-2 within the dotted frame Zx in Figures 20 and 21, it can be seen that the arrangement of the IC 211, LED 212, main function input terminal 213, main function output terminal 214, power supply terminal 215, and GND terminal 216 of both units is reversed vertically and horizontally.

[0266] 20 is basically the same as the LED array panel 92'' in FIG. 7, but in order to compare the arrangements within horizontally adjacent LED pixel units 201, the diagram shows LED pixel units 201-1-2 and 201-2-2 within the dotted-line frame Zx as an example. Also, the LED array panel 92'' in FIG. 21 is a representation of the LED array panel 92'' in FIG. 20 using the layout example of the signal wiring 203, power supply wiring 204, and GND wiring 205 in FIG. 9, and in particular, only the left three columns of FIG. 20 are shown to enable comparison within the dotted-line frame Zx.

[0267] 20 and 21, the reference numerals of the IC 211 to the GND terminal 216 in the LED pixel unit 201 are omitted, but the layout of each generally corresponds to that in FIGS.

[0268] In other words, when the signal wiring 203 is connected so as to be folded zigzag in the column direction, the arrangement of the IC 211, LED 212, main function input terminal 213, main function output terminal 214, power supply terminal 215, and GND terminal 216 of each of the LED pixel units 201-1-2 and 201-2-2 within the dotted frame Zx is inverted vertically and horizontally.

[0269] Furthermore, within the LED array panel 92'', not only the LED pixel units 201-1-2 and 201-2-2, but all horizontally adjacent LED pixel units 201 are arranged such that the arrangements of the ICs 211, LEDs 212, main function input terminals 213, main function output terminals 214, power supply terminals 215, and GND terminals 216 of both of the units are alternately inverted vertically and horizontally.

[0270] In this way, when horizontally adjacent LED pixel units 201 are arranged with their orientations reversed vertically and horizontally, the LED alignment is disrupted, which may affect image quality. Note that LED alignment refers to the consistency of the spatial alignment of the R, G, and B LEDs 212r, 212g, and 212b that make up the LED 212 in Figures 8 and 9 when comparing two LED pixel units 201. Therefore, standardizing the LED alignment indicates that the spatial alignment of the R, G, and B LEDs 212r, 212g, and 212b that make up the LED 212 is also standardized. However, the unification of the spatial arrangement of each of the RGB LEDs 212r, 212g, and 212b that make up the LED 212 essentially means that the spatial arrangements of the IC 211, LED 212, main function input terminal 213, main function output terminal 214, power supply terminal 215, and GND terminal 216 that make up the LED pixel unit 201 are all unified, and the arrangement directions of each individual component are all unified and arranged.

[0271] Therefore, the LED alignment indicates the alignment of the spatial arrangement of the R, G, and B LEDs 212r, 212g, and 212b that constitute the LED 212. In other words, the LED alignment indicates the alignment of the spatial arrangement of the IC 211, LED 212, main function input terminal 213, main function output terminal 214, power supply terminal 215, and GND terminal 216 that constitute the LED pixel unit 201, and the alignment of the arrangement direction of each component.

[0272] One way to avoid this type of up / down / left / right reversal when aligning the LEDs is to use board wiring, for example. However, if the pixel spacing is narrow, the wiring itself may become difficult or a multi-layer board may be required, which may hinder simplification of the signal wiring 203.

[0273] As another example, by separately preparing an inverted LED pixel unit 201 in which the arrangement of the IC 211 is inverted vertically and horizontally, it is possible to use two types of LED pixel units 201, one with inversion and the other without, and arrange them alternately in each column.

[0274] In this case, although simplification of the signal wiring 203 is achieved, there is a possibility that manufacturing costs will increase due to the two types of LED pixel units 201. For example, if it is expected that approximately 2 million LED pixel units 201 will be used in Full-HD, 1 million of each of the two types of ICs 211 will be used, which means that the effort required for manufacturing the LED pixel units 201, mounting them on the board, and so on will all be doubled, which may result in an increase in manufacturing costs.

[0275] In the present disclosure, as an example, as shown in Figures 22 and 23, an LED array panel 92''' is configured to be composed of LED pixel units 201' in which the arrangements of the respective ICs 211, LEDs 212, main function input terminals 213, main function output terminals 214, power supply terminals 215, and GND terminals 216 are identical.

[0276] 22 and 23, it can be seen that the arrangements of the ICs 211, LEDs 212, main function input terminals 213, main function output terminals 214, power supply terminals 215, and GND terminals 216 of the LED pixel units 201 shown in Figures 8 and 9 are the same. Note that the LED array panel 92''' in Figure 23 is a representation of the LED array panel 92''' in Figure 22 using the layout example of the signal wiring 203, power supply wiring 204, and GND wiring 205 in Figure 9, and in particular, only the left two columns of Figure 22 are shown to enable comparison within the dotted line frame Zy.

[0277] However, although the layout of the IC 211, the main function input terminal 213, and the main function output terminal 214 remains unchanged, they are replaced with the IC 211' and the input / output terminals 213'-1 and 213'-2, as described below. Furthermore, the input / output terminals 213'-1 and 213'-2 are configured such that, through processing described below, the terminal that first receives a signal supplied from the LED pixel unit 201' in the preceding stage switches to function as an input terminal, and the terminal that does not receive a signal supplied from the LED pixel unit 201' in the preceding stage switches to function as an output terminal. Therefore, in each of the LED pixel units 201'-2-1, 201'-2-2, and 201'-2-m in the second column of FIG. 23 , the configuration corresponding to the main function output terminal 214 (the configuration labeled CK Out in the figure) is arranged at the bottom, and the configuration corresponding to the main function input terminal 213 (the configuration labeled CK In in the figure) is arranged at the top. However, the signal flow is in the order of LED pixel units 201'-2-m, 201'-2-2, and 201'-2-1, and essentially the configuration labeled CK Out in FIG. 23 functions as the main function input terminal 213, and the configuration labeled CK In in the figure functions as the main function output terminal 214.

[0278] This unifies the LED alignment, reducing the impact on image quality. Furthermore, since there is no need to manufacture LED units with two different configurations, increases in manufacturing costs can be suppressed. Furthermore, simply arranging and connecting the LED pixel units 201' in an array eliminates the need to configure the input / output terminals 213'-1 and 213'-2 to function as input and output terminals, thereby reducing labor and ultimately reducing costs. The configurations shown in Figures 20 and 21 may also be employed. For example, this configuration is employed when a configuration with limited power supply points is required or when a slight reduction in image quality and increased costs are acceptable.

[0279] <<15. Functions Realized by IC of LED Pixel Unit in Figures 22 and 23>> Next, with reference to the functional block diagram of Figure 24, functions realized by the IC 211' of the LED pixel unit 201' in Figures 22 and 23 will be described. Note that in the configuration that realizes the functions of the IC 211' in Figures 22 and 23, components that have the same functions as the configuration that realizes the functions of the IC 211 in Figure 10 are assigned the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0280] The IC211' in FIG. 24 differs from the IC211 in FIG. 10 in that the switch 251 is removed, the bus switching control unit 260 and the switch 263 are replaced with a pulse switching control unit 291 and a switch 263', and further, POR301 to WDT309 are newly provided.

[0281] In the IC 211', the switch 251 for switching buses is omitted because there is no need to return the LED state pulse from the subsequent IC 211' to the column driver 202. Similarly, in the switch 263, bus switching for returning the LED state pulse to the column driver 202 is not required, so the terminals 263b, 263f, and the switching unit 263e in Fig. 7 are not required, and therefore a switch 263' is provided that omits these. That is, the switch 263' is composed of the switching unit 263a, and terminals 263c, 263d.

[0282] Furthermore, since there is no need to switch buses, a pulse switching control unit 291 is provided instead of the bus switching control unit 260. That is, the pulse switching control unit 291 controls the switching unit 263a in the switch 263′ to connect to the terminal 263c when outputting a header pulse from the header pulse generating unit 261, and to connect to the terminal 263d when outputting an LED status pulse from the LED status pulse generating unit 262.

[0283] More specifically, in IC211′ of FIG. 24, a POR (Power On Reset) circuit 301, a one-shot circuit 302, DFF (Delay Flip Flop) circuits 303-1 and 303-2, AND circuits 304-1 and 304-2, an OR circuit 305, off switches 306-1 and 306-2, input ports (Port In) 307-1 and 307-2, output ports (Port Out) 308-1 and 308-2, and a WDT (Watch Dog Timer) 309 are newly provided.

[0284] A POR (Power On Reset) circuit 301 detects the potential of the power supply line to IC 211' and generates a predetermined potential as a reset pulse (Power On Reset pulse) determined within IC 211' for a fixed period of time immediately after power is applied, and supplies this to a one-shot circuit 302. In this example, the POR circuit 301 generates a low-potential signal as the reset pulse, and while the reset pulse is being generated, the logic circuit within IC 211' takes on an initial value, performing what is known as initialization processing. This initialization processing sets input / output terminals 213'-1 and 213'-2 of IC 211' to an input mode in which they both function as input terminals.

[0285] When a reset pulse is supplied from the POR circuit 301, the one-shot circuit 302 supplies a clear signal consisting of a Hi signal to the clear terminals clr of the DFF circuits 303-1 and 303-2, thereby initializing the DFF circuits 303-1 and 303-2. Also, when a reset pulse is supplied from the WDT 309, the one-shot circuit 302 supplies a clear signal consisting of a Hi signal to the clear terminals clr of the DFF circuits 303-1 and 303-2, similar to when a reset pulse is supplied from the POR 301, thereby initializing the DFF circuits 303-1 and 303-2.

[0286] When the DFF circuits 303-1 and 303-2 receive the rising edge of the clock pulse from the AND circuits 304-1 and 304-2 at their clock terminals ck, they hold the state of the D terminal supplied from the power supply VDD at that time, and output the inverted value of the held signal from the output terminal Q_ to the off switches 306-1 and 306-2.

[0287] The bottom left of FIG. 24 shows a truth table for the DFF circuits 303-1 and 303-2.

[0288] The AND circuit 304 - 1 performs an AND operation on the input signal from the input port 307 - 1 and the signal from the output terminal Q of the DFF circuit 303 - 2 , and outputs the result to the input terminal of the OR circuit 305 .

[0289] Furthermore, the AND circuit 304 - 2 performs an AND operation on the input signal from the input port 307 - 2 and the signal from the output terminal Q of the DFF circuit 303 - 1 , and outputs the result to the input terminal of the OR circuit 305 .

[0290] The OR circuit 305 takes the NOR of the AND circuits 304 - 1 and 304 - 2 and outputs the result to the signal detection unit 252 and the WDT 309 .

[0291] By default (immediately after power-on), the off switches 306-1 and 306-2 are turned on by receiving a Hi signal from the DFFs 303-1 and 303-2, respectively. This means that the off switches are turned on, and the circuits function in an off state (non-conducting state). This stops the function of the output ports 308-1 and 308-2. Furthermore, by default (immediately after power-on), the AND circuits 304-1 and 304-2 are supplied with a Hi signal from the output terminals Q of the DFFs 303-1 and 303-2, respectively. This allows them to accept input signals from the input / output terminals 213'-1 and 213'-2, and the input / output terminals 213'-1 and 213'-2 function as input terminals.

[0292] Furthermore, when a Low signal is supplied from the output terminal Q of the DFF circuits 303-2 and 303-1, the off switches 306-1 and 306-2 are turned off, i.e., function as circuits in an on state (conductive state), causing the output ports 308-1 and 308-2 to function, thereby causing the input / output terminals 213'-1 and 213'-2 to function as output terminals. At this time, a Low signal is supplied from the DFFs 303-1 and 303-2 to the AND circuits 304-1 and 304-2, so that the input signals from the input / output terminals 213'-1 and 213'-2 cannot be accepted, and the function as input terminals is stopped.

[0293] 24, the WDT (Watch Dog Timer) 309 is a ring oscillator timer using an inverter, which repeatedly resets the positive feedback loop of the ring oscillator with a signal from the OR circuit 305. Therefore, if the signal from the OR circuit 305 is interrupted for some reason, the WDT 309 is not reset, and if this state continues for a predetermined time or longer, the WDT 309 supplies a reset pulse to the one-shot circuit 302. This causes the one-shot circuit 302 to generate a clear signal similar to the state when the power is turned on, and supplies this signal to the DFF circuits 303-1 and 303-2.

[0294] That is, when each of the input / output terminals 213'-1, 213'-2 is functioning normally as either an input terminal or an output terminal, an input signal is supplied from either of the input ports 307-1, 307-2 at predetermined time intervals, and the input signal is supplied to the OR circuit 305 via the AND circuits 304-1, 304-2. Therefore, when each of the input / output terminals 213'-1, 213'-2 is functioning normally as an input terminal or an output terminal, the OR circuit 305 continues to output a signal to the WDT 309 within a predetermined time.

[0295] However, if some kind of failure causes both the input / output terminals 213' between the IC 211' in the previous or next stage in the daisy chain to function as input or output terminals, a conflict occurs, and signals cannot be sent or received from the previous or next IC 211', resulting in a so-called deadlock state. When a deadlock state occurs, no input signal is supplied to the OR circuit 305 even after a predetermined time has passed. When no signal is supplied from the OR circuit 305 for a predetermined time or longer, the WDT 309 detects the deadlock state and supplies a reset pulse to the one-shot circuit 302, thereby simulating a power-on state and recovering from the deadlock state.

[0296] There are many methods that can be used for the WDT 309, and the configuration is not limited to that shown in FIG. 24. As an example, the predetermined time Tth of the WDT 309 is ensured to be less than 1 MHz using an oscillator. That is, when there is a signal from the OR circuit 305, the WDT 309 resets the timer, and when there is no signal from the OR circuit 305 for 1 μs or more, it supplies a reset pulse to the one-shot circuit 302. Here, the signal from the OR circuit 305 must have a frequency higher than 2 MHz, but this is not a limitation.

[0297] <<16. Setting Operation of Input / Output Terminals>> Next, the setting operation of the input / output terminals 213'-1 and 213'-2 will be described with reference to the timing chart of FIG.

[0298] In FIG. 25, the top row is the waveform of the power supply voltage (VDD Power), and the second row is the waveform of a reset pulse (internal reset) output from a POR (Power On Reset) circuit 301 in the IC 211′.

[0299] Furthermore, the third to fifth rows show the input / output signal waveforms of the input / output terminals 213'-1 and 213'-2 when the input / output terminal 213'-1 functions as an input terminal and the input / output terminal 213'-2 functions as an output terminal, as well as the signal waveform input to the input / output terminal 213'-1 from the previous IC 211'.

[0300] Furthermore, the sixth to eighth rows show the input / output signal waveforms of the input / output terminals 213'-1 and 213'-2 when the input / output terminal 213'-2 functions as an input terminal and the input / output terminal 213'-1 functions as an output terminal, as well as the signal waveform input to the input / output terminal 213'-2 from the previous IC 211'.

[0301] That is, at time t100, as shown in the top row, when the power is turned on, the voltage rises and, in response, as shown in the second row, the POR circuit 301 outputs a low signal as a reset pulse for a predetermined period of time from t100 to t101.

[0302] Then, in response to the reset pulse, the one-shot circuit 302 supplies a clear signal (Hi signal) to the clear terminals clr of the DFFs 303-1 and 303-2, thereby initializing the DFFs 303-1 and 303-2.

[0303] Between times t101 and t102, as shown in the third and fourth rows, in response to the clear signal, DFFs 303-1 and 303-2 supply Hi signals to the off switches 306-1 and 306-2 and the AND circuits 304-1 and 304-2 via their output terminals Q, respectively, thereby fixing the states of the input / output terminals 213-1 and 213-2.

[0304] As a result, the off switches 306-1 and 306-2 are fixed to the on state, so that the output ports 308-1 and 308-2 are stopped from functioning and both the input ports 307-1 and 307-2 are functional. At this time, the input / output terminals 213-1 and 213-2 are fixed to the Lo state (Weak Pull Down) due to a weak current.

[0305] As a result, both the input / output terminals 213'-1 and 213'-2 are in a state where they function substantially as input terminals, that is, in the input mode.

[0306] Next, at time t102 to t103, as shown in the fifth row, when a Hi signal (STR), which is a header pulse indicating the start of supply of a light emission control signal, is supplied to input / output terminal 213'-1 from the previous column driver 202 or IC 211', a Hi signal as a clock pulse is supplied to the clock terminal ck of DFF303-1 via input / output terminal 213'-1 and AND circuit 304-1.

[0307] Accordingly, the ck terminal of the DFF circuit 303-1 detects a rising edge at time t102, and by accepting the input of a Hi signal supplied from the power supply VDD, the state of the Hi signal is maintained, and a Low signal, which is the inverted value of the maintained Hi signal, is supplied from the output terminal Q to the AND circuit 304-2 and the off switch 306-2.

[0308] Accordingly, the off switch 306-2 is turned off, the output port 308-2 is activated, and the input / output terminal 213'-2 is placed in an output mode (functioning as an output terminal). At the same time, a low signal is supplied to the AND circuit 304-2, which stops the function of the input port 307-2.

[0309] As a result, from time t103 onwards, the input / output terminal 213'-1 functions as an input terminal, and the input / output terminal 213'-2 functions as an output terminal.

[0310] As a result, as shown in the third row of Figure 25, after time t104 when a predetermined time ΔT has elapsed, input / output terminal 213'-1 functions as an input terminal, and data input is accepted sequentially at intervals of the predetermined time ΔT.

[0311] On the other hand, as shown in the fourth row of FIG. 25, the input / output terminal 213'-2 functions as an output terminal, and therefore, while receiving the light emission control signal, the signal output to the subsequent stage is stopped.

[0312] On the other hand, from time t102 to t103, as shown in the eighth row of Figure 25, when a Hi signal (STR), which is a header pulse indicating the start of supply of a light emission control signal, is supplied to the input / output terminal 213'-2 from the previous column driver 202 or IC 211', a Hi signal, which is a clock pulse, is supplied to the clock terminal sk of DFF303-2 via the input / output terminal 213'-2 and the AND circuit 304-2.

[0313] Accordingly, the D terminal of the DFF circuit 303-2 detects the rising edge at time t102, and by accepting the input of a Hi signal supplied from the power supply VDD, the state of the Hi signal is maintained, and a Low signal, which is the inverted value of the maintained Hi signal, is supplied from the output terminal Q to the AND circuit 304-1 and the off switch 306-1.

[0314] Accordingly, the off switch 306-1 is turned off, the output port 308-1 is activated, and the input / output terminal 213'-1 is placed in an output mode (functioning as an output terminal). At the same time, a low signal is supplied to the AND circuit 304-1, causing the input port 307-1 to stop functioning.

[0315] As a result, from time t103 onwards, the input / output terminal 213'-2 functions as an input terminal, and the input / output terminal 213'-1 functions as an output terminal.

[0316] As a result, as shown in the seventh row of Figure 25, from time t104 onwards when a predetermined time ΔT has elapsed, the input / output terminal 213'-2 functions as an input terminal, and data input is sequentially accepted at intervals of the predetermined time ΔT.

[0317] On the other hand, as shown in the sixth row of FIG. 25, the output terminal 213'-1 functions as an output terminal, and therefore, while receiving the light emission control signal, the output of the signal to the subsequent stage is stopped.

[0318] <<17. Deadlock and Reset>> Next, reset by the WDT 309 when a deadlock state occurs will be described with reference to FIGS.

[0319] Consider the case where the LED pixel units 201'-1-101 to 201'-104 are connected in a zigzag pattern as shown in an LED array panel 92''' in FIG. 26, for example, through the above series of processes.

[0320] In the case of FIG. 26, when a light emission control signal is supplied from the column driver 202 to the LED pixel units 201′-1-101 to 201′-104 in that order, the input / output terminal 213′-1-101 of the LED pixel unit 201′-1-101 functions as an input terminal, and the input / output terminal 213′-2-101 functions as an output terminal.

[0321] Furthermore, the input / output terminal 213'-1-102 of the LED pixel unit 201'-1-102 functions as an input terminal, and the input / output terminal 213'-2-102 functions as an output terminal.

[0322] Furthermore, the input / output terminal 213'-2-103 of the LED pixel unit 201'-1-103 functions as an input terminal, and the input / output terminal 213'-1-103 functions as an output terminal.

[0323] Furthermore, the input / output terminal 213'-2-104 of the LED pixel unit 201'-1-104 functions as an input terminal, and the input / output terminal 213'-1-104 functions as an output terminal.

[0324] However, as described above, the DFF circuits 303-1 and 303-2 output the inverted value of the held signal from the output terminal Q to the off switches 306-1 and 306-2 at the timing when they receive the rising edge of the clock signal, whichever is earlier, when a clock pulse is supplied to the clock terminal ck from the input / output terminal 213'-1 and the AND circuit 304-1 or from the input / output terminal 213'-2 and the AND circuit 304-2. Accordingly, one of the output ports 308-1 and 308-2 is enabled, so that one of the input / output terminals 213'-1 and 213'-2 functions as an output terminal, and the other functions as an input terminal.

[0325] Therefore, if noise generated for some reason, such as ESD (Electric Static Discharge) or an erroneous signal at startup, is input to the clock terminals ck of the DFF circuits 303-1 and 303-2 as noise similar to a clock pulse, there is a risk that the input / output terminals 213'-1 and 213'-2 will be set as either an input terminal or an output terminal based on the noise.

[0326] For example, consider a situation in which, as shown in the LED array panel 92'' in Figure 26, the input / output terminals 213'-1 and 213'-2 of the LED pixel units 201'-1-101 to 201'-1-104 should be set as input and output terminals, but for some reason, noise is generated from the column driver 202 toward the LED pixel unit 201'-104.

[0327] In this case, as shown in the LED array panel 92''' in Figure 27, the input / output terminal 213'-2-104 should function as an input terminal and the input / output terminal 213'-1-104 should function as an output terminal, but the input / output terminal 213'-1-104 is set to function as an input terminal and the input / output terminal 213'-2-104 to function as an output terminal.

[0328] As a result, both the input / output terminal 213'-1-103 of the LED pixel unit 201'-1-103 and the input / output terminal 213'-2-104 of the LED pixel unit 201'-1-104 are set to function as output terminals, resulting in a so-called conflict.

[0329] As a result, even if a light emission control signal is supplied via the LED pixel units 201'-1-101 to 201'-1-103, it will not be transmitted to the LED pixel unit 201'-1-104.

[0330] Furthermore, during normal operation, input / output terminals 213'-1 and 213'-2 are set to either input or output terminals only when the power is on. Therefore, in the case of Figure 27, no light emission control signal is supplied to LED pixel unit 201'-1-104 from either input / output terminal 213'-1-104 or 213'-2-104, and therefore LED 212 in LED pixel unit 201'-1-104 will remain unable to emit light unless it is restarted by turning the power off and on.

[0331] This state in which the LED pixel unit 201' does not function unless the power is turned on again and restarted is what is called a deadlock state.

[0332] In the present disclosure, the WDT 309 is provided to recover from such a deadlock state.

[0333] That is, for example, as shown in the timing chart of FIG. 28, at time t120, the power supply is turned on, and from time t120 to t121, an initial pulse consisting of a Low signal is generated from the POR circuit, and then from time t121 to t122, both input / output terminals 213'-1 and 213'-2 are set to an input mode in which they are set to function as input terminals.

[0334] In FIG. 28, the first five rows show waveforms similar to those in FIG. 25, but the sixth row shows the waveform of the timer addition value of the WDT 309.

[0335] Then, from time t122 ​​to time t123, a header pulse is supplied from the preceding IC 211' to the input / output terminal 213'-1, so that the input / output terminal 213'-1 is set as an input terminal and the input / output terminal 213'-2 is set as an output terminal.

[0336] At this time, a header pulse is supplied to the WDT 309 from the input / output terminal 213'-1 via the input port 307-1, the AND circuit 304-1, and the OR circuit 305. As a result, the WDT 309 is reset between times t122 ​​and t123.

[0337] Here, for example, in the LED pixel unit 201'-1-104 of Figure 27, no light emission control data will be supplied from either the input / output terminals 213'-1-104 or 213'-2-104 from then on, so the Low signal state continues as shown at times t123 to t124 in the third and fourth rows of Figure 28.

[0338] When receiving data input at intervals of a predetermined time ΔT, the WDT 309 determines whether the period during which there is no signal from the OR circuit 305 is longer than the threshold time Tth (>predetermined time ΔT), i.e., whether the state in which no light emission control data is supplied from either the input / output terminal 213'-1-104 or 213'-2-104 is longer than the threshold time Tth (>predetermined time ΔT). In other words, the WDT 309 determines whether a deadlock state exists based on whether the state in which no light emission control data is supplied from either the input / output terminal 213'-1-104 or 213'-2-104 is longer than the threshold time Tth (>predetermined time ΔT).

[0339] Then, as shown from time t123 to t124 in Figure 28, when the period is longer than the threshold time Tth (>predetermined time ΔT), at time t124, the WDT 309 supplies a reset pulse to the one-shot circuit 302, generates a clear signal, and also resets itself.

[0340] As a result, LED pixel unit 201'-1-104 is initialized, so even if it falls into a deadlock state, it will be in the same state as immediately after power-on at times t121 to t122 ​​in Figure 28, and if the interrupted light emission control data is received from the appropriate one of input / output terminals 213'-1-104, 213'-2-104, the functions as an input terminal and output terminal will be set appropriately, making it possible to obtain light emission control data thereafter.

[0341] Furthermore, even if a similar deadlock state occurs thereafter, it is possible to recover from the deadlock state by performing the same processing.

[0342] <<18. Input / Output Terminal Setting Process>> Next, the input / output terminal setting process by the LED pixel unit 201′ will be described with reference to the flowchart of FIG.

[0343] In step S101, the POR circuit 301 determines whether the power supply is turned on, and repeats the same process until the power supply is turned on.

[0344] If it is determined in step S101 that the power has been turned on, the process proceeds to step S102.

[0345] In step S102, the POR circuit 301 outputs a Low signal as a reset pulse to the one-shot circuit 302.

[0346] In step S103, the one-shot circuit 302 generates a clear signal based on the reset pulse and supplies it to the clear terminals clr of the DFF circuits 303-1 and 303-2.

[0347] In response to this, the DFF circuits 303-1 and 303-2 are initialized and supply a Hi signal from the output terminal Q_ to the AND circuits 304-1 and 304-2 and the off switches 306-2 and 306-1, respectively.

[0348] As a result, both of the off switches 306-1 and 306-2 are turned on, and the functions of the output ports 308-1 and 308-2 are stopped.

[0349] As a result, the input / output terminals 213'-1 and 213'-2 are both in a state where the input ports 307-1 and 307-2 function, and both are in a state where they function as input terminals (input mode).

[0350] In step S104, it is determined whether a rising transition has occurred in either the input / output terminal 213'-1 or 213'-2, and the same process is repeated until a rising transition occurs.

[0351] That is, when a header pulse or a pulse of light emission control data is input via input / output terminals 213'-1, 213'-2, input ports 307-1, 307-2, and AND circuits 304-1, 304-2, respectively, DFF circuits 303-1, 303-2 supply a clock pulse to clock terminal ck, and determine whether a rising transition has occurred.

[0352] If it is determined in step S104 that a rising transition has occurred in either the input / output terminal 213'-1 or 213'-2, the process proceeds to step S105.

[0353] In step S105, the DFF circuit 303 (either of the DFF circuits 303-1 or 303-2) connected to the input / output terminal 213′ (either of the input / output terminals 213′-1 or 213′-2) where the rising transition occurred latches Hi, which is the potential of the power supply VDD, and transitions the signal from the output terminal Q_ from Hi to Low, outputting it to the AND circuit 304 (either of the AND circuits 304-2 or 304-1) and the off switch 306 (either of the off switches 306-2 or 306-1).

[0354] In step S106, the AND circuit 304 (either of AND circuits 304-2 and 304-1) connected to the input / output terminal 213' (either of 213'-1 and 213'-2) that did not transition the signal from the output terminal Q_ from a Hi signal to a Low signal has its output controlled to be off, and the off switch 306 (either of off switches 306-2 and 306-1) is turned off, thereby turning it on.

[0355] As a result, the function of the input port 307 of the input / output terminal 213' where a rising transition has occurred is maintained, and the function of the input port 307 of the input / output terminal 213' where a rising transition has not occurred is stopped. Furthermore, the stopped state of the function of the output port 308 of the input / output terminal 213' where a rising transition has occurred is maintained, and the output port 308 of the input / output terminal 213' where a rising transition has not occurred is set to function.

[0356] As a result, the input / output terminal 213' where a rising transition has occurred is set to input mode and functions as an input terminal, while the input / output terminal 213' where no rising transition has occurred is set to output mode and functions as an output terminal.

[0357] In step S107, the WDT 309 resets the timer. That is, when the input / output terminals 213'-1 and 213'-2 are set as either input terminals or output terminals, respectively, and a header pulse or light emission control data is supplied, an input signal from one of the terminals is supplied to the OR circuit 305 via the input ports 307-1 and 307-2 and the AND circuits 304-1 and 304-2, and the output from the OR circuit 305 is supplied to the signal detection unit 252 and the WDT 309. This causes the WDT 309 to reset the timer.

[0358] In step S308, the WDT 309 determines whether or not there is input data consisting of a header pulse and light emission control data at the input / output terminals 213'-1 and 213'-2 based on the presence or absence of an output from the OR circuit 305.

[0359] If it is determined in step S308 that input data exists, the process proceeds to step S109.

[0360] In step S109, it is determined whether or not an instruction to end has been given. If an instruction to end has not been given, the process returns to step S107, and the subsequent steps are repeated.

[0361] If it is determined in step S108 that there is no input data, the process proceeds to step S110.

[0362] In step S110, the WDT 309 determines whether the time during which no input data is being input has elapsed beyond a predetermined threshold time Tth.

[0363] If it is determined in step S110 that the time during which no input data has been input has not exceeded the predetermined time (threshold time Tth), the process returns to step S108.

[0364] That is, even if no input data is being input, if the time during which no input data is being input is shorter than a predetermined time (threshold time Tth), the processes of steps S108 and S110 are repeated.

[0365] If it is determined in step S110 that the time during which no input data is being input has elapsed for a predetermined time (threshold time Tth), the process returns to step S102, and the WDT 309 outputs a reset pulse to the one-shot circuit 302. At startup, the reset pulse supplied to the one-shot circuit 302 is generated by the POR circuit 301 when the power is turned on, but thereafter, the WDT 309 generates the reset pulse.

[0366] That is, by the processing of steps S101 to S106, of the input / output terminals 213'-1, 213'-2, the one to which the header pulse or light emission control data is input first is set to input mode and functions as an input terminal, and the other input / output terminal 213' is set to output mode and functions as an output terminal.

[0367] Then, the input / output terminals 213'-1 and 213'-2 are set to function as either input terminals or output terminals, and in step S107, the WDT 309 resets the timer. Then, in step S108, it determines whether there is no input data, and repeats the process of resetting the timer as long as it is determined that there is input data.

[0368] At this time, it is determined in step S108 that there is no input data, and further in step S110 it is determined whether the state without input data has lasted longer than a predetermined time (threshold time Tth), thereby determining whether a deadlock state has occurred. If it is determined in step S110 that the state without input data has lasted longer than the predetermined time (threshold time Tth), the process returns to step S102, and the same process as that at the time of startup is carried out.

[0369] This allows the IC 211', LED 212, input / output terminals 213'-1 and 213'-2, power supply terminal 215, and GND terminal 216 in the LED pixel unit 201' to be daisy-chained and used with their arrangements aligned.

[0370] Furthermore, even if the IC 211' to the GND terminal 216 in the LED pixel unit 201' are arranged in the same direction and connected in a daisy chain, it is possible to automatically set whether each of the input / output terminals 213'-1, 213'-2 will function as an input terminal or an output terminal simply by turning on the power while connected.

[0371] Furthermore, even if a deadlock state occurs due to the influence of some kind of disturbance or noise, if the state in which there is no input data continues for a period longer than a predetermined time (threshold time Tth), it is possible to reconfigure the input / output terminals 213'-1 and 213'-2 to function as either input terminals or output terminals, just as when the power is turned on.

[0372] As a result, the signal wiring 203 is connected so as to be folded zigzag in the column direction, and by folding back the signal wiring 203'' in Figure 7, it is possible to save length and suppress degradation of image quality without disrupting the alignment of the LEDs even while reducing the cost of the device configuration.

[0373] In this specification, a system refers to a collection of multiple components (devices, modules (components), etc.), regardless of whether all of the components are housed in the same housing. Therefore, multiple devices housed in separate housings and connected via a network, and a single device housed in a single housing with multiple modules, are both systems.

[0374] The embodiments of the present disclosure are not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the present disclosure.

[0375] For example, the present disclosure can be configured as a cloud computing system in which a single function is shared and processed collaboratively by multiple devices via a network.

[0376] Furthermore, each step described in the above flowchart can be executed by one device, or can be shared and executed by a plurality of devices.

[0377] Furthermore, when one step includes multiple processes, the multiple processes included in that one step can be executed by one device or can be shared and executed by multiple devices.

[0378] The present disclosure may also be configured as follows. <1> A drive control device comprising: a plurality of LED pixel units, each of which includes an LED (Light Emitting Diode) and an emission control unit that controls emission of the LED based on an emission control signal; and a driver that generates the emission control signal and supplies it to the plurality of LED pixel units, the plurality of LED pixel units being electrically connected in series to the driver. <2> The drive control device according to <1>, in which the plurality of LED pixel units are daisy-chained from the driver. <3> The drive control device according to <1>, in which the plurality of LED pixel units are connected from the driver by a single signal wiring. <4> The drive control device according to <3>, in which the driver superimposes the emission control signal on a clock signal and supplies the light-emission control signal to the plurality of LED pixel units via the single signal wiring. <5> The drive control device according to <4>, in which the driver superimposes the light-emission control signal on the clock signal and supplies the light-emission control signal to the plurality of LED pixel units via the single signal wiring using a PWM (Pulse Width Modulation) method that switches between signals with different fixed pulse widths for a predetermined polarity within one cycle of the clock signal. <6> The drive control device according to <4>, wherein the driver superimposes the light-emission control signal on the clock signal using a PAM (Pulse Amplitude Modulation) method that switches between pulse signals of different fixed amplitudes for a predetermined polarity within one cycle of the clock signal, and supplies the superimposed light-emission control signal to the plurality of LED pixel units via the single signal wiring. <7> The drive control device according to <4>, wherein the driver superimposes the light-emission control signal on the clock signal by switching between signals that distinguish between 1, 0, and a header pulse in the light-emission control signal for each cycle of the clock signal, and supplies the superimposed light-emission control signal to the plurality of LED pixel units via the single signal wiring.<8> The drive control device according to <7>, wherein the driver continuously supplies the light emission control signals for the plurality of LED pixel units to the LED pixel units in order of proximity to the driver via the LED pixel unit closest to the driver among the plurality of LED pixel units connected by the single signal wiring. <9> The LED pixel unit closest to the driver, when it acquires its own light emission control signal from the light emission control signals for the plurality of LED pixel units supplied from the driver, supplies the subsequent light emission control signals to the nearest LED pixel unit in a subsequent stage connected by the single signal wiring, and similarly repeats thereafter. <10> The drive control device according to <7>, wherein the driver inserts the header pulse at the beginning of the light emission control signal for the LED pixel unit closest to the driver and supplies the subsequent light emission control signals with a dummy pulse inserted at the beginning for each LED pixel unit. <11> The drive control device according to <10>, wherein the LED pixel unit closest to the driver acquires the light-emission control signal for a predetermined length from the timing at which the header pulse is detected as its own light-emission control signal, replaces the dummy pulse of the light-emission control signal in a subsequent stage with the header pulse, and supplies this to the LED pixel unit closest to the subsequent stage, and similarly repeats thereafter. <12> The drive control device according to <7>, wherein the driver inserts information indicating light-emission timing into a predetermined position in one of the light-emission control signals and supplies it via the LED pixel unit closest to the driver, and the LED pixel units each acquire light-emission timing information for the predetermined position in the light-emission control signal of the other LED pixel units, and causes the LED to emit light at the acquired light-emission timing. <13> The drive control device according to <12>, wherein the LED pixel unit detects the operating state of the LED when causing the LED to emit light, and stores the detected information as LED state data.<14> The drive control device according to <13>, wherein the driver inserts information specifying a target LED pixel unit and information indicating the read timing of the LED state data into a predetermined position in one of the light emission control signals and supplies the light emission control signal via the LED pixel unit closest to the driver, the LED pixel units each acquire information specifying a target LED pixel unit from the predetermined position in the light emission control signal of the other LED pixel units and information indicating the read timing of the LED state data, the target LED pixel unit reads the LED state data and sends it to the driver at the acquired read timing, and the non-target LED pixel units pass through the LED state data sent by the target LED pixel unit to the driver at the acquired read timing so that it reaches the driver. <15> The drive control device according to <13>, wherein the LED pixel unit transmits the LED state data to the LED pixel unit in a subsequent stage. <16> The drive control device according to <15>, wherein, of the plurality of LED pixel units connected to the single signal wiring, the LED pixel unit connected at the end of the single signal wiring as viewed from the driver is further connected to the driver via a signal wiring that returns from the signal wiring, and the LED pixel unit connected at the end transmits the LED state data transmitted from the LED pixel unit in the previous stage to the driver that is configured in the subsequent stage as viewed from the driver via the signal wiring that returns. <17> The drive control device according to <1>, wherein the plurality of LED pixel units are connected by two signal wirings from the driver. <18> The drive control device according to <17>, wherein one of the two signal wirings is used to supply the light emission control signal and the other is used to supply a clock signal. <19> The drive control device according to <1>, wherein the plurality of LED pixel units are arranged with RGB LED alignment matched and are connected by a single signal wiring from the driver.<20> The drive control device according to <19>, wherein each of the plurality of LED pixel units further includes two input / output terminals, and one of the two input / output terminals is set as an input terminal that accepts an input of a signal supplied via the signal wiring of the driver, and the other input / output terminal is set as an output terminal that outputs the signal to a subsequent stage via the signal wiring. <21> The drive control device according to <20>, wherein of the two input / output terminals, the one input / output terminal to which a signal from the driver is first input is set as the input terminal, and the other input / output terminal that is not set as the input terminal is set as the output terminal. <22> The drive control device according to <21>, wherein the signal from the driver that is first input to one of the two input / output terminals is a header pulse provided at the beginning of the light-emission control signal, or the light-emission control signal. <23> The drive control device according to <21>, wherein a reset pulse generated when power is turned on sets both of the two input / output terminals as the input terminals, and then the input / output terminal to which a signal from the driver is first input is maintained in a state where it is set as the input terminal, and the input / output terminal that is not maintained in a state where it is set as the input terminal is set as the output terminal. <24> The drive control device according to <23>, further comprising a timer that measures a time during which a state in which no signal is supplied to the input terminal continues after one of the input / output terminals is set as the input terminal and the other input / output terminal is set as the output terminal, and when the time during which the state in which the signal is not supplied to the input terminal continues is longer than a predetermined time, the timer outputs the reset pulse, and after both of the two input / output terminals are set again as the input terminals, the input / output terminal to which a signal from the driver is first input is maintained in a state where it is set as the input terminal, and the input / output terminal that is not maintained in a state where it is set as the input terminal is set as the output terminal.<25> A drive control device comprising: a plurality of LED pixel units each consisting of an LED (Light Emitting Diode) and a light emission control unit that controls light emission of the LED based on a light emission control signal; and a driver that generates the light emission control signal and supplies it to the plurality of LED pixel units. The plurality of LED pixel units are electrically connected in series to the driver.

[0379] 11 Display system, 30 PC, 31 Video server, 32 Video wall controller, 33 Video wall, 51, 51-1 to 51-n Display unit, 78 Signal processing unit, 91 Driver control unit, 92, 92-1 to 92-N LED array panel, 201, 201-1-1 to 201-k-m, 201', 201'-1-1 to 201'-k-m LED pixel unit, 202 Column driver, 203 Signal wiring, 204 Power supply wiring, 205 GND wiring, 211 IC, 212, 212r, 212g, 212b LED, 213 Clock input / output terminal, 213', 213'-1, 213'-2 Input / output terminal, 214 Clock input / output terminal, 215 Power supply terminal, 216 GND terminal, 251 Switch, 251a switching unit, 251b, 251c terminal, 252 signal detection unit, 253 signal reproduction unit, 254 serial-parallel conversion unit, 255 IC control data register, 256 light emission control data register, 257 light emission control unit, 258 LED state determination recording unit, 259 bus data switching and timing control unit, 260 bus switching control unit, 261 header pulse generation unit, 262 LED state pulse generation unit, 263, 263' switch, 263a switching unit, 263b to 263d terminal, 263e switching unit, 263f terminal, 271 signal determination unit, 281-1 to 281-3 D latch circuits, 282-1 to 281-3 delay circuits, 291 pulse switching control unit, 301 POR circuit, 302 One-shot circuit, 303, 303-1, 303-2 DFF circuit, 304, 304-1, 304-2 AND circuit, 305 OR circuit, 306, 306-1, 306-2 Off switch, 307, 307-1, 307-2 Input port, 308, 308-1, 308-2 Output port, 309 WDT

Claims

1. A drive control device comprising: a plurality of LED pixel units each consisting of an LED (Light Emitting Diode) and an emission control unit that controls the emission of the LED based on an emission control signal; and a driver that generates the emission control signal and supplies it to the plurality of LED pixel units, the plurality of LED pixel units being electrically connected in series to the driver.

2. The drive control device according to claim 1, wherein the plurality of LED pixel units are daisy-chained from the driver.

3. The drive control device according to claim 1, wherein the plurality of LED pixel units are connected to the driver by a single signal wiring.

4. The drive control device according to claim 3, wherein the driver superimposes the light emission control signal on a clock signal and supplies the signal to the plurality of LED pixel units through the single signal wiring.

5. The drive control device according to claim 4, wherein the driver superimposes the light emission control signal on the clock signal using a PWM (Pulse Width Modulation) method that switches between signals of different fixed pulse widths for a predetermined polarity within one cycle of the clock signal, and supplies the superimposed light emission control signal to the plurality of LED pixel units via the single signal wiring.

6. The drive control device according to claim 4, wherein the driver superimposes the light emission control signal on the clock signal using a PAM (Pulse Amplitude Modulation) method that switches between pulse signals of different fixed amplitudes for a predetermined polarity within one cycle of the clock signal, and supplies the light emission control signal to the plurality of LED pixel units via the single signal wiring.

7. The drive control device according to claim 4, wherein the driver superimposes the light emission control signal on the clock signal by switching between signals that distinguish between 1, 0, and a header pulse in the light emission control signal every cycle of the clock signal, and supplies the light emission control signal to the plurality of LED pixel units via the single signal wiring.

8. The drive control device according to claim 7, wherein the driver continuously supplies the light emission control signal to each of the LED pixel units in order of distance from the driver via the LED pixel unit that is closest to the driver among the LED pixel units connected by the single signal wiring.

9. The drive control device according to claim 8, wherein when the LED pixel unit closest to the driver acquires its own light emission control signal from the light emission control signals of the plurality of LED pixel units supplied from the driver, it supplies subsequent light emission control signals to the LED pixel unit in a subsequent stage connected to the single signal wiring, and similarly repeats thereafter.

10. The drive control device according to claim 7, wherein the driver supplies the light emission control signal for the LED pixel unit closest to the driver with the header pulse inserted at the beginning thereof, and supplies the subsequent light emission control signals with a dummy pulse inserted at the beginning thereof for each of the LED pixel units.

11. The drive control device according to claim 10, wherein the LED pixel unit closest to the driver acquires a predetermined length of the light emission control signal from the timing when the header pulse is detected as its own light emission control signal, replaces the dummy pulse of the subsequent light emission control signal with the header pulse, and supplies it to the LED pixel unit closest to the subsequent stage, and similarly repeats thereafter.

12. The drive control device according to claim 7, wherein the driver inserts information indicating a light emission timing into a predetermined position in any one of the light emission control signals and supplies the information via the LED pixel unit closest to the driver, and the LED pixel units each obtain information on the light emission timing of the predetermined position in the light emission control signal of the other LED pixel units and cause the LED to emit light at the obtained light emission timing.

13. The drive control device according to claim 12, wherein the LED pixel unit detects an operating state of the LED when the LED is caused to emit light, and stores the detected operating state as LED state data.

14. The drive control device according to claim 13, wherein the driver inserts information identifying a target LED pixel unit and information indicating a read timing of the LED status data into a predetermined position in any of the light emission control signals and supplies the signal via the LED pixel unit closest to the driver, and the LED pixel units each acquire information identifying a target LED pixel unit from the predetermined position in the light emission control signal of the other LED pixel units and information indicating a read timing of the LED status data, the target LED pixel unit reads out the LED status data at the acquired read timing and transmits it to the driver, and the non-target LED pixel units pass through the LED status data transmitted by the target LED pixel unit to the driver at the acquired read timing so that the data reaches the driver.

15. The drive control device according to claim 13, wherein the LED pixel unit transmits the LED status data to the LED pixel unit in a subsequent stage.

16. The drive control device according to claim 15, wherein, of the plurality of LED pixel units connected to the single signal wiring, the LED pixel unit connected to the end of the single signal wiring as viewed from the driver is further connected to the driver via a return signal wiring of the signal wiring, and the LED pixel unit connected to the end transmits the LED state data transmitted from the LED pixel unit in the previous stage to the driver which is configured in the subsequent stage as viewed from the driver itself, via the return signal wiring.

17. The drive control device according to claim 1, wherein the plurality of LED pixel units are connected to the driver by two signal wirings.

18. The drive control device according to claim 17, wherein one of the two signal wirings is used to supply the light emission control signal and the other is used to supply a clock signal.

19. The drive control device according to claim 1, wherein the plurality of LED pixel units are arranged with the RGB LED arrangement matching consistent, and are connected to the driver by a single signal wiring.

20. A drive control device as described in claim 19, wherein each of the plurality of LED pixel units further comprises two input / output terminals, one of the two input / output terminals being set as an input terminal that receives an input of a signal supplied via the signal wiring of the driver, and the other input / output terminal being set as an output terminal that outputs the signal to a subsequent stage via the signal wiring.

21. A drive control device as described in claim 20, wherein of the two input / output terminals, the one to which a signal from the driver is input first is set as the input terminal, and the other input / output terminal that is not set as the input terminal is set as the output terminal.

22. The drive control device according to claim 21, wherein the signal from the driver that is input to either of the two input / output terminals first is a header pulse provided at the beginning of the light emission control signal, or the light emission control signal.

23. A drive control device as described in claim 21, wherein a reset pulse generated when power is turned on sets both of the two input / output terminals as the input terminals, and then the input / output terminal to which a signal from the driver is first input remains set as the input terminal, and the input / output terminal that does not remain set as the input terminal is set as the output terminal.

24. A drive control device as described in claim 23, further comprising a timer that measures the time during which a state in which the signal is not supplied to the input terminal continues after one of the input / output terminals is set as the input terminal and the other of the input / output terminals is set as the output terminal, and when the time during which the state in which the signal is not supplied to the input terminal continues is longer than a predetermined time, the timer outputs the reset pulse and re-configures both of the two input / output terminals as the input terminals, after which the input / output terminal to which the signal from the driver was first input remains set as the input terminal, and the input / output terminal that does not remain set as the input terminal is set as the output terminal.

25. A display device comprising: a plurality of LED pixel units each consisting of an LED (Light Emitting Diode) and an emission control unit that controls the emission of the LED based on an emission control signal; and a drive control device that includes a driver that generates the emission control signal and supplies it to the plurality of LED pixel units, wherein the plurality of LED pixel units are electrically connected in series to the driver.

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