Light detection device and electronic apparatus

Abstract

[Problem] To make it possible to detect an event quickly and with high accuracy even in an imaging scene with low illuminance. [Solution] A light detection device for detecting an event based on the amount of change in the light amount of incident light comprises: a photoelectric conversion element that generates an electric charge corresponding to the light amount of the incident light; an electric charge multiplication part that multiplies the electric charge; a current-to-voltage conversion circuit that converts a current corresponding to the multiplied electric charge into a voltage; and an event detection circuit that detects the event on the basis of the voltage obtained by the conversion.

Description

Photodetector and electronic equipment

[0001] The present disclosure relates to photodetection devices and electronic devices.

[0002] An event-based vision sensor (EVS) has been proposed that rapidly acquires event information from a photoelectric conversion element when some event, such as a change in illuminance, occurs in a captured scene. An EVS has the ability to rapidly capture changes in the state of a subject. Applying this ability, a method has been proposed for acquiring information from an artificial light source by analyzing the frequency pattern of the artificial light source (see Patent Document 1).

[0003] Special Publication No. 2021-513235

[0004] However, in low-illuminance imaging scenes, EVS generates a small amount of photocurrent depending on the amount of incident light, which makes it difficult to quickly detect changes in illuminance, resulting in a slow operating speed. Furthermore, when the photocurrent is small, the sensor is more susceptible to the effects of dark current, which deteriorates the S / N ratio.

[0005] Therefore, the present disclosure provides a light detection device and electronic equipment that can detect events quickly and accurately even in low-illumination imaging scenes.

[0006] In order to solve the above problems, the present disclosure provides a photodetection device that detects an event based on a change in the amount of incident light, the photodetection device comprising: a photoelectric conversion element that generates an electric charge according to the amount of incident light; a charge multiplier that multiplies the electric charge; a current-voltage conversion circuit that converts a current according to the multiplied electric charge into a voltage; and an event detection circuit that detects the event based on the converted voltage.

[0007] The photoelectric conversion element and the charge multiplication section may each include a phototransistor.

[0008] The photoelectric conversion element and the charge multiplication section may each include an avalanche photodiode.

[0009] The photoelectric conversion element may include a photodiode that transfers the charge to a substrate, and the charge multiplier section may include a first transistor whose threshold is modulated in accordance with the charge transferred to the substrate.

[0010] The phototransistor may be a bipolar transistor or a MOS (Metal Oxide Semiconductor) transistor.

[0011] The phototransistor may have: a first diffusion region located on the side opposite to the light incident surface of the substrate and generating charges based on incident light; a second diffusion region located on at least a portion of the surface of the first diffusion region and connected to an emitter electrode; and a third diffusion region located on a portion of the substrate surrounding the first diffusion region and connected to a collector electrode.

[0012] The photoelectric conversion element may include a first wiring connected to an output portion of the photoelectric conversion element, a second wiring connected to an output portion of the current-voltage conversion circuit, and a parasitic capacitance disposed between the first wiring and the second wiring, and the first diffusion region may have a capacitance smaller than the parasitic capacitance.

[0013] An end face of the third diffusion region opposite to the substrate may be located closer to the substrate than an end face of the second diffusion region opposite to the substrate.

[0014] A height of a sidewall of the third diffusion region facing the second diffusion region may be lower than a height of a sidewall of the second diffusion region facing the third diffusion region.

[0015] An area of ​​a sidewall of the first diffusion region facing the second diffusion region may be smaller than an area of ​​a sidewall of the second diffusion region facing the first diffusion region.

[0016] An insulating region may be disposed between the second diffusion region and the third diffusion region.

[0017] The insulating region may be disposed to surround the first diffusion region.

[0018] The insulating region may be disposed from the surface of the second diffusion region to the bottom surface of the first diffusion region or to a position deeper than the bottom surface.

[0019] The insulating region may include a low-k material.

[0020] The collector electrode may extend from the substrate toward the light incident surface.

[0021] The semiconductor device may further include a single collector electrode extending from the third diffusion region in a direction opposite to the substrate.

[0022] The first transistor has: a fourth diffusion region arranged on the side opposite the light incident surface of the substrate; a gate electrode arranged facing an end face of the fourth diffusion region opposite the substrate; a fifth diffusion region arranged in part of the fourth diffusion region and connected to a drain electrode; and a sixth diffusion region arranged in part of the fourth diffusion region and connected to a source electrode, and the end face opposite the light incident surface of the substrate arranged to face the fourth diffusion region may be arranged closer to the light incident surface of the substrate than the end face of the fourth diffusion region on the gate electrode side.

[0023] The end face of the substrate opposite the light incident surface, which is arranged opposite the fourth diffusion region, may be at the same height as the end face of the fourth diffusion region on the light incident surface side of the substrate, or may be arranged on the light incident surface side of the substrate.

[0024] The image sensor may include a plurality of first pixels that each detect the event based on a change in the amount of incident light, and a plurality of second pixels that each output a pixel signal including gradation information based on an electric charge corresponding to the amount of incident light, wherein each of the plurality of first pixels may have the photoelectric conversion element, the electric charge multiplication unit, the current-voltage conversion circuit, and the event detection circuit.

[0025] The pixel circuit may include a charge accumulation section disposed at a position deeper than a channel region of the first transistor in the substrate, and accumulating charges generated by photoelectric conversion of the photoelectric conversion element; and a pixel circuit outputting a pixel signal including gradation information based on the charges accumulated in the charge accumulation section, wherein the threshold of the first transistor may be modulated in accordance with the charges accumulated in the charge accumulation section.

[0026] The semiconductor device may further comprise a floating diffusion region that holds the charge accumulated in the charge accumulation portion, and a second transistor that switches between transferring and not transferring the charge accumulated in the charge accumulation portion to the floating diffusion region.

[0027] The first transistor may switch between modulating the threshold value and transferring the charge stored in the charge storage portion to the pixel circuit, depending on a gate voltage.

[0028] The semiconductor device may include: a pixel isolation region arranged around the photoelectric conversion element; a seventh diffusion region that serves as at least a part of the source region or drain region of the first transistor and also serves as at least a part of the pixel isolation region; and a contact that is connected to the seventh diffusion region and set to a predetermined potential.

[0029] The semiconductor device may include: a pixel isolation region arranged around the photoelectric conversion element; a seventh diffusion region that also serves as at least a part of the source region or drain region of the first transistor; an eighth diffusion region that is provided separately from the seventh diffusion region and also serves as at least a part of the pixel isolation region; and contacts that are connected to the seventh diffusion region and the eighth diffusion region and are set to a predetermined potential.

[0030] The pixel may include a pixel having the photoelectric conversion element; an element isolation region arranged to surround the pixel; and an electrode arranged inside the element isolation region.

[0031] The first transistor may include: a ninth diffusion region that also serves as at least a part of a source region or a drain region of the first transistor; and a ring-shaped gate electrode that is disposed so as to surround the ninth diffusion region.

[0032] The pixel may include a plurality of pixels each having the photoelectric conversion element, and the first transistor may have a tenth diffusion region that is shared among the plurality of pixels and also serves as at least a part of a source region or a drain region of the first transistor.

[0033] Furthermore, according to the present disclosure, there is provided an electronic device comprising: a photodetector that detects an event based on a change in the amount of incident light; and an image processing unit that processes image data output from the photodetector, wherein the photodetector comprises: a photoelectric conversion element that generates an electric charge according to the amount of incident light; a charge multiplier that multiplies the electric charge; a current-voltage conversion circuit that converts a current according to the multiplied electric charge into a voltage; and an event detection circuit that detects the event based on the converted voltage.

[0034] 1 is a block diagram of an electronic device according to a first embodiment of the present disclosure. FIG. 2 is a block diagram of a photodetector according to a first embodiment of the present disclosure. FIG. 3 is a diagram showing a stacked structure of a detection device. FIG. 4 is a circuit diagram showing a first configuration example of an EVS pixel according to a first embodiment of the present disclosure. FIG. 5 is a diagram showing an equivalent circuit of a phototransistor. FIG. 6 is a block diagram showing a configuration of an EVS pixel and an event detection circuit according to a first embodiment of the present disclosure. FIG. 7 is a circuit diagram showing a second configuration example of an EVS pixel according to a first embodiment of the present disclosure. FIG. 8 is a circuit diagram showing a fourth configuration example of an EVS pixel according to a first embodiment of the present disclosure. FIG. 9 is a cross-sectional view showing a first configuration example of a phototransistor according to a first embodiment of the present disclosure. FIG. 10 is a cross-sectional view showing a second configuration example of a phototransistor according to a first embodiment of the present disclosure. FIG. 11 is a circuit diagram showing the parasitic capacitance of an EVS pixel. FIG. 12 is a circuit diagram showing the configuration of a gradation pixel and a pixel circuit according to a first embodiment of the present disclosure. FIG. 13 is a cross-sectional view showing an EVS pixel and a gradation pixel according to a first embodiment of the present disclosure. FIG. 14 is a plan view showing a second configuration example of a pixel array. 1 is a plan view showing a third configuration example of a pixel array; 2 is a plan view showing a fourth configuration example of a pixel array; 3 is a circuit diagram showing the configuration of an EVS pixel according to a comparative example; 4 is a diagram showing punch-through that occurs in a phototransistor; 5 is a plan view showing an EVS pixel according to a second embodiment of the present disclosure; 6 is a cross-sectional view showing a phototransistor according to a second embodiment of the present disclosure; 7 is a diagram showing each component of base capacitance in a phototransistor; 8 is a cross-sectional view showing a first configuration example of a phototransistor according to a third embodiment of the present disclosure; 9 is a diagram showing a process of forming an insulating region of a phototransistor according to a third embodiment of the present disclosure; 10 is a diagram showing a process of forming a base of a phototransistor according to a third embodiment of the present disclosure; 11 is a diagram showing an etch-back process of a phototransistor according to a third embodiment of the present disclosure; 12 is a diagram showing a process of forming an emitter and a collector of a phototransistor according to a third embodiment of the present disclosure; 13 is a cross-sectional view showing a second configuration example of a phototransistor according to a third embodiment of the present disclosure; 14 is a cross-sectional view showing a third configuration example of a phototransistor according to a third embodiment of the present disclosure; 15 is a cross-sectional view showing a fourth configuration example of a phototransistor according to a third embodiment of the present disclosure; 16 is a cross-sectional view showing a fifth configuration example of a phototransistor according to a third embodiment of the present disclosure; 17 is a cross-sectional view showing a phototransistor according to a fourth embodiment of the present disclosure.10 is a circuit diagram showing a first configuration example of an EVS pixel according to a fifth embodiment of the present disclosure. 11 is a circuit diagram showing a second configuration example of an EVS pixel according to a fifth embodiment of the present disclosure. 12 is a circuit diagram showing a third configuration example of an EVS pixel according to a fifth embodiment of the present disclosure. 13 is a circuit diagram showing a fourth configuration example of an EVS pixel according to a fifth embodiment of the present disclosure. 14 is a plan view showing an EVS pixel according to a fifth embodiment of the present disclosure. 15 is a cross-sectional view showing a threshold modulation transistor according to a fifth embodiment of the present disclosure. 16 is a plan view showing a modified example of an EVS pixel according to a fifth embodiment of the present disclosure. 17 is a cross-sectional view showing a modified example of a threshold modulation transistor according to a sixth embodiment of the present disclosure. 18 is a circuit diagram showing a first configuration example of an EVS pixel according to a seventh embodiment of the present disclosure. 19 is a circuit diagram showing a second configuration example of an EVS pixel according to a seventh embodiment of the present disclosure. 20 is a circuit diagram showing a third configuration example of an EVS pixel according to a seventh embodiment of the present disclosure. 21 is a circuit diagram showing a fourth configuration example of an EVS pixel according to a seventh embodiment of the present disclosure. 22 is a plan view showing an EVS pixel according to a seventh embodiment of the present disclosure. 23 is a cross-sectional view showing an EVS pixel according to a seventh embodiment of the present disclosure. 38A and 38B . 38B is a waveform diagram showing a potential gradient in the depth direction of the EVS pixel of FIG. 32 . 38C is a waveform diagram showing a potential gradient after charge is accumulated in an electron pocket. 38D is a plan view showing a first modified example of an EVS pixel according to a seventh embodiment of the present disclosure. 38D is a plan view showing a second modified example of an EVS pixel according to the seventh embodiment of the present disclosure. 38E is a cross-sectional view showing an EVS pixel according to an eighth embodiment of the present disclosure. 38F is a plan view showing a first configuration example of an EVS pixel according to a ninth embodiment of the present disclosure. 38G is a plan view showing a second configuration example of an EVS pixel according to the ninth embodiment of the present disclosure. 38H is a cross-sectional view showing an EVS pixel according to the ninth embodiment of the present disclosure. 38H is a plan view showing a first configuration example of an EVS pixel according to a tenth embodiment of the present disclosure. 38I is a waveform diagram showing a time change of a bias voltage applied to the gate electrode of FIGS. 38A and 38B . 38I is a plan view showing an EVS pixel according to an eleventh embodiment of the present disclosure. 38I is a first cross-sectional view showing an EVS pixel according to an eleventh embodiment of the present disclosure. 38I is a second cross-sectional view showing an EVS pixel according to the eleventh embodiment of the present disclosure. 12. A plan view showing a first configuration example of an EVS pixel according to a twelfth embodiment of the present disclosure. A plan view showing a second configuration example of an EVS pixel according to a twelfth embodiment of the present disclosure. A cross-sectional view showing an EVS pixel according to a twelfth embodiment of the present disclosure.13A and 13B are plan views showing a modified example of an EVS pixel according to a twelfth embodiment of the present disclosure; a cross-sectional view showing a modified example of an EVS pixel according to the twelfth embodiment of the present disclosure; a plan view showing an EVS pixel according to a thirteenth embodiment of the present disclosure; a cross-sectional view showing an EVS pixel according to a thirteenth embodiment of the present disclosure; a plan view showing a modified example of an EVS pixel according to the thirteenth embodiment of the present disclosure; a cross-sectional view showing a modified example of an EVS pixel according to the thirteenth embodiment of the present disclosure; a circuit diagram showing a first configuration example of an EVS pixel according to a fourteenth embodiment of the present disclosure; a circuit diagram showing a second configuration example of an EVS pixel according to a fourteenth embodiment of the present disclosure; a circuit diagram showing a third configuration example of an EVS pixel according to a fourteenth embodiment of the present disclosure; a cross-sectional view showing an avalanche photodiode according to a fourteenth embodiment of the present disclosure; a block diagram showing an example of a schematic configuration of a vehicle control system; an explanatory diagram showing an example of installation positions of an outside vehicle information detection unit and an imaging unit;

[0035] Hereinafter, embodiments of a light detection device and electronic equipment will be described with reference to the drawings. The following description will focus on the main components of the light detection device and electronic equipment, but the light detection device and electronic equipment may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0036] 1 is a block diagram of an electronic device 1 according to a first embodiment of the present disclosure. The electronic device 1 captures image data and includes a photodetector 10, an image processing unit 2, a recording unit 3, and a control unit 4. The electronic device 1 can be applied to, for example, an in-vehicle camera, a smartphone, or a camera mounted on an industrial robot, but the specific use and configuration of the electronic device 1 are arbitrary.

[0037] The photodetector 10 is, for example, an EVS, and performs photoelectric conversion on incident light to capture image data. The image data output from the photodetector 10 is input to the image processing unit 2 and the recording unit 3 via a transmission line L1. The electronic device 1 also has an imaging lens 5 that focuses the incident light and guides it to the photodetector 10.

[0038] The image processing unit 2 performs predetermined image processing such as image recognition, tracking, analysis, etc. on the image data. The image data that has been subjected to image processing by the image processing unit 2 is output to the recording unit 3, for example.

[0039] The recording unit 3 records the image data output from the light detection device 10 or the image processing unit 2. The recording unit 3 may be disposed in a server connected via a network. In the electronic device 1 according to this embodiment, at least one of the image processing unit 2 and the recording unit 3 in FIG. 1 may be omitted.

[0040] The control unit 4 instructs the photodetector 10 to generate image data via a control line L2.

[0041] 2 is a block diagram of a photodetector 10 according to a first embodiment of the present disclosure. The photodetector 10 includes a plurality of pixels having different configurations. The photodetector 10 includes a pixel array unit 11, a vertical drive circuit 12, an event readout circuit 13, and a grayscale signal readout circuit 14.

[0042] The pixel array unit 11 includes a plurality of EVS pixels (first pixels) 20 and a plurality of gradation pixels (second pixels) 30 arranged in a first direction X and a second direction Y. The EVS pixels 20 and the gradation pixels 30 each include a photoelectric conversion element that generates an electric charge according to the amount of incident light. Each of the plurality of EVS pixels 20 is connected to an event detection circuit that detects an event indicating a change in the amount of incident light. Each of the plurality of gradation pixels 30 is connected to a pixel circuit that outputs a pixel signal including gradation information according to the amount of incident light. Note that the event detection circuit and pixel circuit are not shown in FIG. 2 .

[0043] In this specification, the left-right (horizontal) direction in Fig. 2 is referred to as the first direction X, and the up-down (vertical) direction in Fig. 2 is referred to as the second direction Y. Also, in this specification, a row of EVS pixels 20 and gradation pixels 30 arranged in the first direction X is referred to as a pixel row. A column of EVS pixels 20 and gradation pixels 30 arranged in the second direction Y is referred to as a pixel column.

[0044] The vertical drive circuit 12 selects pixel rows in order and drives the gradation pixels 30 for each pixel row. A selection control line HCL is connected to the vertical drive circuit 12 for each pixel row. Each selection control line HCL is connected to all the gradation pixels 30 in the corresponding pixel row. If the EVS pixel 20 is an asynchronous type, it outputs an event signal via an event detection circuit when it detects an event, and if it is a synchronous type, it outputs the event signal via the event detection circuit at a timing instructed by the vertical drive circuit 12. In this specification, an example in which the EVS pixel 20 is an asynchronous type will be described.

[0045] The event readout circuit 13 reads out event signals from the EVS pixels 20 and the event detection circuits, and outputs them to a signal processing unit (not shown), etc. An event signal line ESL is connected to the event readout circuit 13 for each pixel column. Each event signal line ESL transmits event signals output from all the EVS pixels 20 and event detection circuits in the corresponding pixel column.

[0046] The gradation signal readout circuit 14 reads out pixel signals from the gradation pixels 30 and pixel circuits, and outputs the pixel signals to a downstream signal processing unit, etc. A vertical signal line VSL is connected to the gradation signal readout circuit 14 for each pixel column. Each vertical signal line VSL transmits pixel signals output from all the gradation pixels 30 and pixel circuits of the corresponding pixel column.

[0047] 2 shows an example of a hybrid pixel configuration in which gradation pixels 30 and EVS pixels 20 are mixed, but the photodetector 10 may not have gradation pixels 30 and all pixels may be configured with EVS pixels 20. In this case, the gradation signal readout circuit 14 can be omitted from the photodetector 10.

[0048] The photodetector 10 can be configured, for example, as a stacked chip in which multiple chips are stacked. FIG. 3 is a diagram showing the stacked structure of the photodetector 10. The photodetector 10 has a three-layer structure in which a first pixel chip b1, a second pixel chip b2, and a logic chip b3 are bonded together in this order. These chips are bonded together by vias or the like. Note that these chips may also be bonded together by Cu-Cu bonding or bumps, in addition to vias.

[0049] The first pixel chip b1 has, for example, a plurality of EVS pixels 20 in the pixel array unit 11 and gradation pixels 30 arranged therein. The second pixel chip b2 has, for example, an event detection circuit and a pixel circuit arranged therein. The logic chip b3 has, for example, a vertical drive circuit 12, an event readout circuit 13, and a gradation signal readout circuit 14 arranged therein.

[0050] The circuits arranged on each chip are not limited to the circuits described above. For example, some or all of the event detection circuit or pixel circuit may be arranged on the first pixel chip b1, and some or all of the EVS pixels 20 or gradation pixels 30 may be arranged on the second pixel chip b2. Furthermore, the photodetector 10 may be configured with stacked chips of two or less layers, or four or more layers, or may be configured with a single flat chip.

[0051] By arranging the event detection circuit and the like connected to the EVS pixel 20 on the second pixel chip b2, the photodetector device 10 can increase the proportion of the area of ​​the photoelectric conversion element in the chip area, thereby improving sensitivity and enabling the chip to be miniaturized.

[0052] 4 is a circuit diagram showing a first configuration example of the EVS pixel 20 according to the first embodiment of the present disclosure. The EVS pixel 20 has a phototransistor 21 and a current-voltage conversion circuit 22. The current-voltage conversion circuit 22 has a current source 23 and transistors Tr1, Tr2, Tr3, and Tr4. The current source 23 has a transistor Tr5. FIG. 5 is a diagram showing an equivalent circuit of the phototransistor 21. The phototransistor 21 has a photoelectric conversion element 24 and a charge multiplication unit 25. The charge multiplication unit 25 has a transistor Tr11.

[0053] The photoelectric conversion element 24 is, for example, a photodiode, and generates an electric charge based on incident light that is incident on the EVS pixel 20. Either the anode or the cathode of the photoelectric conversion element 24 (the cathode in the example of FIG. 5) is connected to the base of the transistor Tr11, and the other (the anode in the example of FIG. 5) is connected to a predetermined reference voltage node such as a ground voltage.

[0054] The transistor Tr11 is formed of, for example, a PNP bipolar transistor. The emitter of the transistor Tr11 is connected to the output node n1, and the collector of the transistor Tr11 is connected to a predetermined reference voltage node such as a ground voltage. The charge multiplier 25 multiplies the charge generated by the photoelectric conversion element 24. Specifically, the base of the transistor Tr11 is supplied with the charge generated by photoelectric conversion in the photoelectric conversion element 24, and the emitter outputs the multiplied charge from the photoelectric conversion element 24.

[0055] The EVS pixel 20 in FIG. 4 is also referred to as a pixel with a 4Tr configuration because it is composed of four transistors Tr1 to Tr4, excluding transistor Tr11 that constitutes the phototransistor 21 and transistor Tr5 that constitutes the current source 23. In the example of FIG. 4, transistors Tr1 to Tr4 are composed of, for example, NMOS (N-channel Metal-Oxide-Semiconductor) transistors. However, the conductivity types of transistors Tr1 to Tr4 are arbitrary. Any or all of the four transistors may be composed of, for example, PMOS (P-channel Metal-Oxide-Semiconductor) transistors. Transistor Tr5 is composed of, for example, a PMOS transistor.

[0056] The source of transistor Tr1 is connected to the output node n1 of the phototransistor 21 and the gate of transistor Tr2. The gate of transistor Tr1 is connected to the drain of transistor Tr2 and the source of transistor Tr4. The drain of transistor Tr1 is connected to the source of transistor Tr3 and the gate of transistor Tr4. The source of transistor Tr2 is connected to a predetermined reference voltage node such as ground voltage. The gate of transistor Tr3 is connected to the drain of transistor Tr4 and the drain of transistor Tr5 via the output node n2 of the current-voltage conversion circuit 22. The drain of transistor Tr3 is connected to a predetermined high-voltage power supply voltage node. Transistors Tr1 and Tr3 are also called log transistors because they generate a voltage that is a logarithmic conversion of the current supplied to their sources. Transistors Tr2 and Tr4 are also called transimpedance amplifiers because they amplify the current input to their gates and convert it into a voltage.

[0057] The transistor Tr5 has a source connected to a predetermined high-voltage power supply voltage node, and a gate to which a predetermined bias voltage is applied to supply a constant current to the output node n2 of the current-voltage conversion circuit 22.

[0058] The current-voltage conversion circuit 22 converts a current corresponding to the charge multiplied by the phototransistor 21 into a voltage. Specifically, a current signal corresponding to the charge multiplied by the phototransistor 21 is output from the output node n2 as a signal Vlog to an event detection circuit downstream of the EVS pixel 20. The current-voltage conversion circuit 22 in FIG. 4 is also called a logarithmic response unit because it generates a signal Vlog that logarithmically increases the current generated by the phototransistor 21. The current-voltage conversion circuit 22 can widen the dynamic range of the EVS pixel 20 that acquires illuminance information.

[0059] 6 is a block diagram showing the configurations of the EVS pixel 20 and the event detection circuit 40 according to the first embodiment of the present disclosure. The event detection circuit 40 includes a differentiation circuit 41 and a comparator 42. Note that a buffer circuit may be disposed between the current-voltage conversion circuit 22 and the differentiation circuit 41, and an output circuit may be disposed downstream of the comparator 42, but these are omitted from FIG.

[0060] The event detection circuit 40 detects an event based on the voltage converted by the current-voltage conversion circuit 22. Specifically, the differentiation circuit 41 extracts the amount of change in signal level from the signal Vlog output from the current-voltage conversion circuit 22 and outputs a differentiation signal Vdiff. The signal level of the differentiation signal Vdiff indicates the amount of change in the amount of light incident on the EVS pixel 20. The differentiation circuit 41 includes, for example, a capacitor that accumulates charge based on the signal Vlog and a reset circuit that resets the charge in the capacitor when the event detection circuit 40 detects an event. The comparator 42 compares the differentiation signal Vdiff with a predetermined threshold and outputs a signal COMP. In this specification, it is assumed that when an event is detected, the comparator 42 outputs a high-level (or low-level) signal COMP. Note that the event detection circuit 40 may detect multiple types of events, such as two types of events with different polarities or an on-event and an off-event.

[0061] As shown in FIG. 6 , the event detection circuit 40 compares the differential signal Vdiff with a predetermined threshold to determine whether there is a change in the amount of incident light. However, when the signal level of the signal Vlog output from the EVS pixel 20 is low, the signal level of the differential signal Vdiff decreases, and changes in the amount of incident light may not be detected sufficiently. In this case, it becomes difficult to detect events, and it takes time from the detection of one event to the detection of the next event. This reduces the operating speed of the photodetector 10. Furthermore, when the signal level of the differential signal Vdiff decreases, it becomes more susceptible to the influence of dark current, deteriorating the S / N ratio.

[0062] Therefore, in the first embodiment of the present disclosure, a phototransistor 21 is used in the EVS pixel 20. The charge multiplier 25 of the phototransistor 21 multiplies the charge of the photoelectric conversion element 24 and increases the signal level of the signal Vlog based on the charge generated by the photoelectric conversion element 24. This increases the signal level of the differential signal Vdiff, making it easier to detect changes in the amount of incident light and improving the operating speed of the photodetector 10. The multiplication of charge by the charge multiplier 25 is particularly effective when the amount of light incident on the EVS pixel 20 is small and the charge generated by the photoelectric conversion element 24 is small.

[0063] 7A is a circuit diagram showing a second configuration example of the EVS pixel 20 according to the first embodiment of the present disclosure. The EVS pixel 20a shown in FIG. 7A differs from the EVS pixel 20 of FIG. 4 in that it does not include transistors Tr3 and Tr4. The output node n2 is connected to the gate of transistor Tr1 and the drain of transistor Tr2. Because the EVS pixel 20a is configured with two transistors Tr1 and Tr2, it is also referred to as a pixel with a 2Tr configuration.

[0064] 7B is a circuit diagram showing a third configuration example of the EVS pixel 20 according to the first embodiment of the present disclosure. The EVS pixel 20b shown in FIG. 7B has a transistor Tr21 instead of the transistor Tr1. The transistor Tr21 is configured, for example, as a PMOS transistor, and has a drain connected to the output node n1 of the phototransistor 21 and a source connected to the output node n2 of the current-voltage conversion circuit 22. A predetermined bias signal is applied to the gate of the transistor Tr21. The charge generated by the phototransistor 21 is output to the output node n2 via the transistor Tr21. In addition, a ground-level voltage, for example, is applied to the gate of the transistor Tr21. The EVS pixel 20b is also called a gate-grounded pixel.

[0065] 7C is a circuit diagram showing a fourth configuration example of the EVS pixel 20 according to the first embodiment of the present disclosure. The EVS pixel 20c shown in FIG. 7B includes a phototransistor 21 and a transistor Tr22. The transistor Tr22 is, for example, an NMOS transistor, and its gate and drain are connected to a predetermined high-voltage power supply voltage node. The source of the transistor Tr22 is connected to an output node n1 of the phototransistor 21. The signal Vlog is output from the output node n1 of the phototransistor 21. The EVS pixel 20c is also called a diode-type pixel because charge is output directly from the phototransistor 21 to the event detection circuit 40 in the downstream stage.

[0066] FIG. 8 is a plan view of an EVS pixel 20 according to the first embodiment of the present disclosure. The plan view of FIG. 8 corresponds to the circuit configuration of the EVS pixel 20 in FIG. 4 . The phototransistor 21 has a base diffusion region (first diffusion region) 51, an emitter diffusion region (second diffusion region) 52, and a collector diffusion region (third diffusion region) 53. Transistors Tr1 and Tr3 are arranged on the left side of FIG. 8 . Transistors Tr2 and Tr4 are arranged on the right side of FIG. 8 . An emitter diffusion region 52 is arranged in the center of the EVS pixel 20, and a base diffusion region 51 is arranged directly below the emitter diffusion region 52, i.e., closer to the light incident surface than the emitter diffusion region 52. A collector diffusion region 54 is arranged to surround the base diffusion region 51. A high-concentration collector diffusion region 53 for connecting a collector electrode is arranged in a portion of the end face of the collector diffusion region 54 opposite the light incident surface.

[0067] 9A is a cross-sectional view showing a first configuration example of the phototransistor 21 according to the first embodiment of the present disclosure. FIG. 9A illustrates a cross-sectional structure taken along line A-A in FIG. 8 . Incident light LGT is incident on the phototransistor 21 from the lower side of FIG. 9A . The base diffusion region 51 is disposed on the side opposite the light incident surface of the substrate 50 and generates charge based on the incident light LGT. The emitter diffusion region 52 is disposed on at least a portion of the surface of the base diffusion region 51 and is connected to an emitter electrode 55. The collector diffusion regions 53 and 54 are disposed in a portion of the substrate 50 so as to surround the base diffusion region 51. The collector diffusion region 53 is connected to a collector electrode 56. An insulating region (STI: Shallow Trench Isolation) 57 is disposed between the emitter diffusion region 52 and the collector diffusion region 53.

[0068] 9A is, for example, a p-type silicon substrate (P-SUB; p-substrate) containing p-type impurity ions. Base diffusion region 51 is a diffusion region containing n-type impurities. Diffusion regions 52, 53, and 54 are diffusion regions containing p-type impurity ions. Diffusion regions 52 and 53 are diffusion regions with higher impurity concentrations than collector diffusion region 54. Diffusion regions 51 to 54 are formed, for example, by implanting impurities into an underlying substrate 58.

[0069] 9A are used to form the transistor Tr11 of the charge multiplication section 25. The base diffusion region 51 is used to form the photoelectric conversion element 24. As shown in FIG. 9A , the photoelectric conversion element 24 and the charge multiplication section 25 according to the first embodiment of the present disclosure constitute a phototransistor 21.

[0070] The charge / discharge speed of the phototransistor 21 is determined by the base capacitance (more specifically, the capacitance of the base diffusion region 51). The smaller the capacitance of the base diffusion region 51, the faster the operating speed of the phototransistor 21. Therefore, in order to improve the operating speed of the phototransistor 21 and ultimately the photodetector device 10, it is desirable to reduce the capacitance of the base diffusion region 51. For example, the capacitance of the base diffusion region 51 can be reduced by reducing the size of the base diffusion region 51.

[0071] The base capacitance of the phototransistor 21 is desirably smaller than the parasitic capacitance Cpr between the phototransistor 21 and the output section of the EVS pixel 20. Fig. 10 is a circuit diagram showing the parasitic capacitance Cpr. As shown in Fig. 10, the parasitic capacitance Cpr is, for example, the capacitance between the output node n1 of the phototransistor 21 and the output node n2 of the EVS pixel 20 (i.e., the output node of the current-voltage conversion circuit 22). In this specification, of the two wirings that generate the parasitic capacitance Cpr, the wiring connected to the output node (collector) n1 of the phototransistor 21 is referred to as the first wiring Ln1, and the wiring connected to the output node n2 of the EVS pixel 20 is referred to as the second wiring Ln2.

[0072] The relationship between the base capacitance of the phototransistor 21 and the parasitic capacitance Cpr will be explained in detail below. The charging time required for the base capacitance of the phototransistor 21 to be charged by the photocurrent is expressed as base capacitance / photocurrent. Meanwhile, the current amplified by the phototransistor 21 charges the parasitic capacitance Cpr in the EVS pixel 20, thereby driving the current-voltage conversion circuit 22 of the EVS pixel 20. The charging time required for the parasitic capacitance Cpr to be charged is expressed as Cpr / (photocurrent×amplification factor).

[0073] If the base capacitance is made sufficiently smaller than the parasitic capacitance Cpr, the charging time of the base capacitance can be made shorter than the charging time of the parasitic capacitance Cpr. This allows the phototransistor 21 to operate more quickly, which can speed up the drive timing of the current-voltage conversion circuit 22 and increase the speed of the EVS pixel 20. If the charging time of the base capacitance is longer than the charging time of the parasitic capacitance Cpr, the operating speed of the phototransistor 21 will be slowed and the drive timing of the current-voltage conversion circuit 22 will also be delayed, which will defeat the purpose of amplifying the current with the phototransistor 21 and increasing the speed of the EVS pixel 20. Therefore, it is desirable that the base capacitance be smaller than the parasitic capacitance Cpr.

[0074] 9B is a cross-sectional view showing a second configuration example of the phototransistor 21 according to the first embodiment of the present disclosure. The phototransistor 21a shown in Fig. 9B differs from the phototransistor 21 of Fig. 9A in that it does not have an insulating region 57. In Fig. 9B, a base diffusion region 51a is disposed between the emitter diffusion region 52 and the collector diffusion regions 53 and 54.

[0075] 9B is also called a flat-type phototransistor (photodiode) because a flat base diffusion region 51 is disposed on the surface opposite to the light incident surface of the substrate 50. The phototransistor 21a in FIG. 9B does not require the step of forming the insulating region 57, which simplifies the process of forming the phototransistor 21a.

[0076] The phototransistor 21 shown in Figure 9A is also called an STI-isolated phototransistor (photodiode) because the emitter diffusion region 52 and the collector diffusion region 53 are separated by an insulating region 57 on the surface of the substrate 50 opposite the light incident surface. The size of the base diffusion region 51 in Figure 9A is smaller than the base diffusion region 51a in Figure 9B by the size of the insulating region 57. By providing an STI between the collector and emitter, the capacitance of the base diffusion region 51 can be reduced.

[0077] 9A can have a smaller capacitance of the base diffusion region 51 than the phototransistor 21a of FIG. 9B, and therefore can operate at a higher speed. In the following, an example using the STI isolated phototransistor 21 shown in FIG.

[0078] 11 is a circuit diagram showing the configuration of a gradation pixel 30 and a pixel circuit 31 according to the first embodiment of the present disclosure. The gradation pixel 30 has a photoelectric conversion element 32. The pixel circuit 31 has a transfer transistor Tr31, a reset transistor Tr32, an amplification transistor Tr33, and a selection transistor Tr34. The transistors Tr31 to Tr34 are, for example, NMOS transistors. Some or all of the transistors Tr31 to Tr34 in the pixel circuit 31 may be included in the gradation pixel 30.

[0079] The source of the transfer transistor Tr31 is connected to either the anode or cathode (the cathode in the example of FIG. 11) of the photoelectric conversion element 32, and the drain is connected to a floating diffusion (floating diffusion region) FD. The transfer transistor Tr31 transfers the charge of the photoelectric conversion element 32 to the floating diffusion FD when a transfer signal TRG is input to the gate.

[0080] The reset transistor Tr32 has a source connected to the floating diffusion FD and a drain connected to a predetermined high-voltage power supply voltage node, and resets the charge of the floating diffusion FD when a reset signal RST is input to its gate.

[0081] The source of the amplifier transistor Tr33 is connected to the drain of the selection transistor Tr34, the source is connected to a predetermined high-voltage side power supply voltage node, and the gate is connected to the floating diffusion FD. The amplifier transistor Tr33 generates a current by amplifying the charge of the floating diffusion FD.

[0082] The source of the selection transistor Tr34 is connected to the vertical signal line VSL. A selection signal SEL indicating that the gradation pixel 30 has been selected is input to the gate of the selection transistor Tr34 from, for example, the vertical drive circuit 12. This causes the selection transistor Tr34 to output a pixel signal Vimg based on the amount of light incident on the gradation pixel 30 to the vertical signal line VSL.

[0083] FIG. 12 is a plan view showing a first configuration example of a pixel array. FIG. 12 shows a pixel block G consisting of 4×4 pixels, with four pixel rows arranged in the first direction X and four pixel columns arranged in the second direction Y. A pixel block G is a unit of pixel repetition within the pixel array unit 11. The pixel block G in FIG. 12 includes four small pixel blocks, two arranged in the first direction X and two arranged in the second direction Y. Each small pixel block includes 2×2 pixels. Of the four small pixel blocks, two small pixel blocks arranged diagonally include only a green gradation pixel 30a. Of the remaining two small pixel blocks, one includes two red gradation pixels 30b and two EVS pixels 20, and the remaining small pixel block includes two blue gradation pixels 30c and two EVS pixels 20. Color filters are arranged on the incident surface side of each of the red, green, and blue gradation pixels. The color filters transmit only specific wavelength components of incident light. For example, a color filter that transmits green wavelength light is arranged on the light incident surface side of gradation pixel 30a, a color filter that transmits red wavelength light is arranged on the light incident surface side of gradation pixel 30b, and a color filter that transmits blue wavelength light is arranged on the light incident surface side of gradation pixel 30c. In this way, the pixel block G in Figure 12 includes 12 gradation pixels 30 and four EVS pixels 20.

[0084] FIG. 13 is a cross-sectional view showing an EVS pixel 20 and a gradation pixel 30 according to the first embodiment of the present disclosure. FIG. 13 shows a cross-sectional structure taken along line B-B in FIG. 12. The gradation pixel 30 in FIG. 13 has one or more pixel transistors Trn connected to a photoelectric conversion element 32. The pixel transistor Trn is, for example, a transfer transistor Tr31. The EVS pixel 20 and the gradation pixel 30 each have an on-chip lens LNS that collects incident light. A pixel isolation region is disposed along the boundary between the EVS pixel 20 and the gradation pixel 30. The gradation pixel 30 has a color filter CF that transmits specific wavelength components of the incident light.

[0085] The EVS pixel 20 in Fig. 13 is an STI isolated pixel in which an insulating region 57 is arranged on the surface of the substrate 50. On the other hand, the gradation pixel 30 is a FAT pixel in which no insulating region is arranged on the surface of the substrate 50 and a flat diffusion region PWL is arranged. In the configuration of Fig. 13, the gradation pixel 30 can be easily formed as a FAT type, and the EVS pixel 20 is an STI isolated type, which allows the base diffusion region 51 to be reduced.

[0086] The EVS pixel 20 may be configured as a flat type, and the gradation pixel 30 may be configured as an STI-isolated type. Both the EVS pixel 20 and the gradation pixel 30 may be configured as a flat type (or an STI-isolated type). Some of the multiple EVS pixels 20 (or gradation pixels 30) may be configured as a flat type, and the rest may be configured as an STI-isolated type.

[0087] Fig. 14A is a diagram showing a second configuration example of a pixel array. Compared to pixel block G of Fig. 12, pixel block Ga of Fig. 14A has a pixel configuration different from that of pixel block G of Fig. 12, in that it has a small pixel block including a red gradation pixel 30b and a small pixel block including a blue gradation pixel 30c. Pixel block Ga of Fig. 14A has a small pixel block including three red gradation pixels 30b and one EVS pixel 20, and a small pixel block including four blue gradation pixels 30c. Thus, pixel block Ga of Fig. 14A differs from pixel block G of Fig. 12 in that it has only one EVS pixel 20.

[0088] Fig. 14B is a diagram showing a third configuration example of a pixel array. The pixel block Ga in Fig. 14B is different from the pixel block G in Fig. 12 in the pixel configuration of the small pixel blocks including the blue gradation pixels 30c. The pixel block Ga in Fig. 14B has small pixel blocks including four blue gradation pixels 30c. Thus, the pixel block Gb in Fig. 14B differs from the pixel block G in Fig. 12 in that it has two EVS pixels 20.

[0089] 14C is a diagram showing a fourth configuration example of a pixel array. Of the four small pixel blocks constituting the pixel block Gc in FIG. 14C, two small pixel blocks arranged diagonally include three green gradation pixels 30a and one EVS pixel 20. Of the remaining two small pixel blocks, one includes three red gradation pixels 30b and one EVS pixel 20, and the remaining one includes three blue gradation pixels 30c and one EVS pixel 20. Thus, the pixel block Gc in FIG. 14C differs from the pixel block G in FIG. 12 in that the four EVS pixels 20 are arranged adjacent to each other in the center.

[0090] The pixel array unit 11 may have any arrangement and configuration, without being limited to the examples shown in Figures 14A to 14C. For example, all pixels in the pixel array unit 11 may be configured as EVS pixels 20. Alternatively, the pixel array unit 11 may include gradation pixels 30 that detect colors (e.g., white, cyan, magenta, yellow, etc.) different from the gradation pixels 30a, 30b, and 30c. Furthermore, the pixel array unit 11 may be configured such that each pixel in the pixel array unit 11 can be dynamically switched between operating as an EVS pixel 20 or as a gradation pixel 30 using a switching element or the like.

[0091] Fig. 15 is a circuit diagram showing the configuration of an EVS pixel 100 according to a comparative example. The EVS pixel 100 in Fig. 15 differs from the EVS pixel 20 in Fig. 4 in that it has a photoelectric conversion element 24 instead of the phototransistor 21. In other words, the EVS pixel 100 does not have the charge multiplication unit 25 in Fig. 5.

[0092] In the EVS pixel 100, the charge generated in the photoelectric conversion element 24 is not multiplied. As a result, in the case of low illuminance, the signal level of the signal Vlog based on the charge generated in the photoelectric conversion element 24 decreases, making it difficult for the event detection circuit 40 to detect an event and reducing the operating speed of the photodetector. Furthermore, in the case of low illuminance, the EVS pixel 100 is susceptible to the influence of dark current, deteriorating the S / N ratio.

[0093] The EVS pixel 20 according to the first embodiment of the present disclosure multiplies the charge of the photoelectric conversion element 24 by a charge multiplier 25 in the phototransistor 21. This increases the signal level of the signal Vlog even under low illuminance conditions, making it easier to detect events and improving the operating speed. Furthermore, the photodetector 10 according to the first embodiment of the present disclosure can suppress the effects of dark current and prevent a deterioration in the S / N ratio.

[0094] When the phototransistor 21 multiplies the charge of the photoelectric conversion element 24, noise may be generated. Therefore, when a phototransistor is used in a gradation pixel 30 that outputs gradation information according to illuminance, accurate gradation information may not be obtained due to noise. On the other hand, the EVS pixel 20 detects whether there is a change in illuminance equal to or greater than a certain threshold, and is therefore less affected by noise due to charge multiplication. Therefore, the phototransistor 21 is particularly suitable for the EVS pixel 20.

[0095] Second Embodiment As described above, the phototransistor 21 can not only multiply the charge generated by photoelectric conversion, but also increase the operation speed by reducing the capacitance of the base diffusion region 51 (hereinafter referred to as base capacitance). However, reducing the base capacitance may cause punch-through in the phototransistor 21. FIG. 16 is a diagram showing punch-through that occurs in the phototransistor 21. As shown in FIG. 16, in the phototransistor 21, a depletion layer EL1 is generated between the base diffusion region 51 and the emitter diffusion region 52. Furthermore, a depletion layer EL2 is generated between the base diffusion region 51 and the collector diffusion region 54 and between the base diffusion region 51 and the P-SUB region in the substrate 50. The depletion layer EL1 extends to the surface of the base diffusion region 51. The depletion layer EL2 extends from the bottom surface of the base diffusion region 51 to the surface of the base diffusion region 51.

[0096] When the base capacitance decreases, the depletion layer EL1 and the depletion layer EL2 come into contact with each other on the surface of the base diffusion region 51, causing conduction between the emitter and the collector of the phototransistor 21 (i.e., between the emitter diffusion region 52 and the collector diffusion region 53), resulting in punch-through. Therefore, the second embodiment of the present disclosure is characterized by being able to eliminate this punch-through.

[0097] 17 is a plan view showing an EVS pixel 20d according to a second embodiment of the present disclosure. The EVS pixel 20d differs from the EVS pixel 20 of FIG. 8 in that it includes an insulating region 57a ​​that surrounds the diffusion regions 51 and 52. The insulating region 57a ​​is also called a deep STI because it is embedded deeper than the base diffusion region 51. FIG. 17 also shows a phototransistor 21b that includes the insulating region 57a.

[0098] Fig. 18 is a cross-sectional view showing a phototransistor 21b according to a second embodiment of the present disclosure. Fig. 18 illustrates a cross section taken along line A-A in Fig. 17. As shown in Fig. 18, the insulating region 57a ​​is disposed from the surface of the emitter diffusion region 52 (i.e., the surface opposite the light incident surface of the substrate 50) to the bottom surface of the base diffusion region 51 or to a position deeper than the bottom surface. As shown in Fig. 18, the base diffusion region 51 and the collector diffusion region 54 are separated by the insulating region 57a.

[0099] 16, in the phototransistor 21b, a depletion layer EL1a is generated on the surface side of the base diffusion region 51, and a depletion layer EL2a is generated on the bottom side of the base diffusion region 51. The insulating region 57a ​​is arranged to prevent the expansion of the depletion layers EL1a and EL2a. Furthermore, by providing the insulating region 57a, the depletion layers EL1a and EL1b can be separated from each other, thereby preventing punch-through. This eliminates the risk of the emitter and collector of the phototransistor 21b being covered with the depletion layer, and punch-through can be prevented even if the base capacitance is reduced.

[0100] Third Embodiment A third embodiment is characterized in that the base capacitance is reduced by a method other than reducing the size of the base diffusion region 51. FIG. 19 is a diagram showing each component of the base capacitance in a phototransistor 21b. As shown in FIG. 19, the base capacitance of the phototransistor 21b includes an emitter-base area component capacitance Ceb_area, a base-collector area component capacitance Cbc_area, and a base-collector perimeter component capacitance Cbc_peri. Of these, the base-collector perimeter component capacitance Cbc_peri is determined by the base depth Dbase, the width Wsti of the insulating region 57a, the perimeter Lperi of the insulating region 57a, and the thickness of a silicon oxide film (SiO ２ ) the material coefficient E of the insulating region 57a SiO2 and is expressed by the following formula.

[0101] 20 is a cross-sectional view showing a first configuration example of a phototransistor 21 according to a third embodiment of the present disclosure. The phototransistor 21c shown in FIG. 20 differs from the phototransistor 21b shown in FIG. 19 in that the collector diffusion region 53 is positioned deeper than the emitter diffusion region 52. That is, the end face of the collector diffusion region 53 opposite the substrate 50 is positioned closer to the substrate 50 than the end face of the emitter diffusion region 52 opposite the substrate 50. In addition, the height of the sidewall of the collector diffusion region 53 facing the emitter diffusion region 52 is lower than the height of the sidewall of the emitter diffusion region 52 facing the collector diffusion region 53. Note that the emitter electrode 55, the collector electrode 56, and the like are not shown in FIG. 20.

[0102] The phototransistor 21c is formed, for example, by etching back the collector portion of the substrate 50. The detailed process of forming the phototransistor 21c will be described later.

[0103] The base capacitance of the phototransistor 21c has an emitter-base area component capacitance Ceb_area, a base-collector area component capacitance Cbc_area, and a base-collector perimeter component capacitance Cbc_peri_a. In the phototransistor 21c, a portion of the diffusion region PWL facing the base diffusion region 51 across the insulating region 57a ​​is removed. That is, the area of ​​the sidewall of the collector diffusion region 54 facing the base diffusion region 51 is smaller than the area of ​​the sidewall of the base diffusion region 51 facing the collector diffusion region 54.

[0104] By removing a part of the diffusion region PWL, the base-collector perimeter length component capacitance Cbc_peri_a is reduced in capacitance compared to the base-collector perimeter length component capacitance Cbc_peri in Fig. 19. In other words, the base capacitance of the phototransistor 21c can be reduced.

[0105] 21A to 21D are cross-sectional views showing the manufacturing process of the phototransistor 21c. First, as shown in FIG. 21A, a process for forming an insulating region 57a ​​is performed. FIG. 21A shows an example in which a silicon substrate 50 into which a trace amount of p-type impurity (e.g., boron) is implanted is used. The insulating region 57a ​​is formed by filling a trench formed by removing a portion of the substrate 50 by etching or the like with, for example, a silicon oxide film. As described above, it is desirable that the insulating region 57a ​​be embedded to a position deeper than the base diffusion region 51, which will be formed in a subsequent process.

[0106] 21B, a base formation step is performed. The base diffusion region 51 is formed by implanting n-type impurities (for example, boron) into a region of the substrate 50 surrounded by the insulating region 57a.

[0107] Next, as shown in Fig. 21C, an etch-back process for the phototransistor 21c is performed. In this process, a portion of the substrate 50 is removed by wet etching, as shown in Fig. 21C. The portion that is removed is the region surrounding the insulating region 57a.

[0108] Next, as shown in FIG. 21D , the emitter and collector of the phototransistor 21c are formed. In this process, high-concentration p-type impurity (e.g., arsenic) ions are implanted and diffused into the etched-back portions of the substrate 50 to form collector diffusion regions 53 and 54. The collector diffusion region 53 is located closer to the light incident surface (lower side in FIG. 21D ) than the collector diffusion region 54, and the collector diffusion region 54 has a higher p-type impurity concentration than the collector diffusion region 53. High-concentration p-type impurity (e.g., arsenic) ions are also implanted and diffused into the surface of the base diffusion region 51 to form an emitter diffusion region 52. Furthermore, a contact electrode CS (emitter electrode) 55 and a contact electrode (collector electrode) 56 are formed in the emitter diffusion region 52 and the collector diffusion region 53, respectively, extending upward. This completes the phototransistor 21c.

[0109] 22A is a cross-sectional view showing a second configuration example of the phototransistor 21 according to the third embodiment of the present disclosure. The phototransistor 21d shown in FIG. 22A differs from the phototransistor 21c shown in FIG. 20 in that the collector diffusion regions 53 and 54 are disposed at a position deeper than the bottom surface of the base diffusion region 51. That is, in the phototransistor 21d shown in FIG. 22A, the collector diffusion region 53 is disposed closer to the light incident surface than the end face of the base diffusion region 51 on the light incident surface side. As a result, the collector diffusion regions 53 and 54 are no longer disposed opposite the base diffusion region 51, thereby minimizing the reduction in the base-collector perimeter-length component capacitance Cbc_peri.

[0110] FIG. 22B is a cross-sectional view showing a third configuration example of the phototransistor 21 according to the third embodiment of the present disclosure. In the phototransistor 21e shown in FIG. 22B, the end face of the collector diffusion region 53 opposite the light incident surface is positioned lower than the end face of the emitter diffusion region 52 opposite the light incident surface, and an insulating region 57b made of a low-k material is disposed on the end face of the collector diffusion region 53 opposite the light incident surface. The end face of the insulating region 57b opposite the light incident surface is flush with, for example, the end face of the emitter diffusion region 52 opposite the light incident surface. The low-k material of the insulating region 57b is, for example, black diamond or porous silica. Because the dielectric constant of the insulating region 57b is smaller than that of silicon, the base-collector perimeter capacitance Cbc_peri can be reduced, thereby reducing the base capacitance of the phototransistor 21. The third configuration example of the phototransistor 21 shown in FIG. 22B can be applied to both the first and second configuration examples of the phototransistor 21.

[0111] 22C is a cross-sectional view showing a fourth configuration example of the phototransistor 21 according to the third embodiment of the present disclosure. The phototransistor 21f shown in FIG. 22C includes collector diffusion regions 53 and 54 disposed on the light incident surface side of the substrate 50, and a collector electrode 56 extending from the substrate 50 toward the light incident surface side. This prevents the base diffusion region 51 and the collector diffusion regions 53 and 54 from being disposed opposite each other, thereby minimizing the base-collector perimeter component capacitance Cbc_peri of the collector electrode 56 extending from the substrate 50 toward the light incident surface side. The fourth configuration example of the phototransistor 21 shown in FIG. 22C can be applied to any of the first to third configuration examples of the phototransistor 21.

[0112] FIG. 22D is a cross-sectional view showing a fifth configuration example of the phototransistor 21 according to the third embodiment of the present disclosure. The phototransistor 21g shown in FIG. 22D has a cross-sectional structure in which the insulating region 57a ​​is omitted from the cross-sectional structure of FIG. 20 . In the phototransistor 21g shown in FIG. 22D , the emitter diffusion region 52 and the collector diffusion regions 53 and 54 are not at the same height. This eliminates the risk of the emitter and collector of the phototransistor 21g being covered by a depletion layer, thereby suppressing punch-through. Furthermore, the process of forming an insulating region between the base diffusion region 51 and the collector diffusion regions 53 and 54 is unnecessary, thereby simplifying the manufacturing process of the phototransistor 21g. The fifth configuration example of the phototransistor 21 shown in FIG. 22D can be applied to any of the first to fourth configuration examples of the phototransistor 21.

[0113] In this way, the phototransistors 21c to 21g according to the third embodiment of the present disclosure can reduce the base capacitance by reducing the opposing area between the collector and the base by etching back the substrate 50. As a result, the phototransistors 21c to 21g can increase the speed of operation of the photodetector 10 compared to the phototransistor 21 according to the first and second embodiments of the present disclosure.

[0114] Fourth Embodiment Various methods can be considered for reducing the base capacitance of the phototransistor 21. For example, the base capacitance includes the base-collector CS capacitance Cbc_cs. FIG. 23 is a cross-sectional view showing a phototransistor 21h according to a fourth embodiment of the present disclosure. The base-collector CS capacitance Cbc_cs is a capacitance generated between the base diffusion region 51 and the collector electrode 56, and increases as the number of collector electrodes 56 increases. Therefore, the fourth embodiment is characterized in that the base-collector CS capacitance Cbc_cs is reduced by reducing the number of collector electrodes 56.

[0115] The phototransistor 21h can minimize the base-collector capacitance Cbc_cs by, for example, providing only one collector electrode 56. That is, the phototransistor 21h has a single collector electrode 56 extending from the collector diffusion region 53 in the direction opposite to the substrate 50. This can further reduce the base capacitance of the phototransistor 21h, thereby increasing the operation speed of the photodetector 10. The fourth embodiment of the present disclosure can be applied to any of the first to third embodiments.

[0116] Fifth Embodiment Various modifications are possible for the configurations of the photoelectric conversion element 24 and the charge multiplication unit 25. Fig. 24A is a circuit diagram showing a first configuration example of an EVS pixel 70 according to a fifth embodiment of the present disclosure. The EVS pixel 70 in Fig. 24A differs from the EVS pixel 20 in Fig. 4 in that it includes a threshold modulation transistor (first transistor) Tr51. The threshold modulation transistor Tr51 constitutes a charge multiplication unit 25b.

[0117] The threshold modulation transistor Tr51 is configured, for example, by a PMOS transistor. The drain of the threshold modulation transistor Tr51 is connected to a predetermined reference voltage node such as a ground voltage, and the source is connected to an output node n1. A predetermined bias voltage Vg is applied to the gate of the threshold modulation transistor Tr51, and charge is transferred to the back gate of the threshold modulation transistor Tr51 from either the anode or cathode of the photoelectric conversion element 24a (the anode in the example of FIG. 24A). The other of the anode or cathode of the photoelectric conversion element 24a (the cathode in the example of FIG. 24A) is connected to a predetermined high-voltage power supply voltage node.

[0118] The threshold modulation transistor Tr51 is a transistor whose threshold is modulated in accordance with the charge transferred from the photoelectric conversion element 24a to the substrate 50. The EVS pixel 70 including the threshold modulation transistor Tr51 is called a VMIS (Threshold Voltage Modulation Image Sensor) or a CMD (Charge Modulation Device).

[0119] 24B is a circuit diagram showing a second configuration example of an EVS pixel 70 according to a fifth embodiment of the present disclosure. The EVS pixel 70a shown in FIG. 24B is a pixel with a 2Tr configuration similar to that shown in FIG. 7A. FIG. 24C is a circuit diagram showing a third configuration example of an EVS pixel 70 according to a fifth embodiment of the present disclosure. The EVS pixel 70b shown in FIG. 24C has a gate-grounded configuration similar to that shown in FIG. 7B. FIG. 24D is a circuit diagram showing a fourth configuration example of an EVS pixel 70 according to a fifth embodiment of the present disclosure. The EVS pixel 70c shown in FIG. 24D has a diode configuration similar to that shown in FIG. 7C.

[0120] 25 is a plan view of an EVS pixel 70 according to a fifth embodiment of the present disclosure. The EVS pixel 70 of FIG. 25 has a threshold modulation transistor Tr51 in its central portion. The threshold modulation transistor Tr51 has a gate electrode 71, a diffusion region (fourth diffusion region) 72 arranged opposite the gate electrode 71, a drain diffusion region (fifth diffusion region) 73, and a source diffusion region (sixth diffusion region) 74. The diffusion region 72 performs photoelectric conversion, and is therefore hereinafter referred to as a photoelectric conversion region 72. As shown in FIG. 25, transistors Tr1 and Tr3 and transistors Tr2 and Tr4 are arranged around the threshold modulation transistor Tr51.

[0121] FIG. 26 is a cross-sectional view showing a threshold modulation transistor Tr51 according to a fifth embodiment of the present disclosure. FIG. 26 shows a cross-sectional structure taken along line CC in FIG. 25 , illustrating the threshold modulation transistor Tr51 and the transistor Tr1. As shown in FIG. 26 , a drain diffusion region 73 and a source diffusion region 74 are disposed in a portion of a photoelectric conversion region 72. The photoelectric conversion region 72 is disposed on the opposite side of the substrate 50 from the light incident surface, and charges are transferred from a photoelectric conversion element 24a (not shown in FIG. 26 ). The threshold modulation transistor Tr51 has a threshold modulated by charges accumulated in the photoelectric conversion region 72. More specifically, the transfer of holes h from the photoelectric conversion element 24a lowers the threshold of the threshold modulation transistor Tr51, and a current based on the charges transferred from the photoelectric conversion element 24a flows between the drain and source. In other words, the threshold modulation transistor Tr51 can multiply the charges generated by the photoelectric conversion element 24a. The gain of the threshold modulation transistor Tr51 changes logarithmically depending on the bias voltage Vg applied to the gate thereof. That is, the threshold modulation transistor Tr51 can adjust the multiplication factor of the charge photoelectrically converted by the photoelectric conversion element 24a by adjusting the bias voltage Vg.

[0122] The threshold modulation transistor Tr51 has an insulating region 75 arranged to surround the photoelectric conversion region 72. The insulating region 75 may be buried at a position deeper than the photoelectric conversion region 72 in order to prevent charges from leaking out of the photoelectric conversion region 72 due to a depletion layer generated near the photoelectric conversion region 72.

[0123] 27 is a plan view showing a modified example of the EVS pixel 70 according to the fifth embodiment of the present disclosure. The EVS pixel 70d shown in FIG. 27 differs from the EVS pixel 70 shown in FIG. 25 in that it has a threshold modulation transistor Tr51a with a ring-shaped structure. The threshold modulation transistor Tr51a has a source diffusion region 74 in the center. The gate electrode 71 is arranged in a ring shape to surround the source diffusion region 74. The drain diffusion region 73 is arranged in a ring shape to surround the source diffusion region 74 and the gate electrode 71. In addition, a ring-shaped insulating region 75 is arranged to surround the diffusion regions 73, 74 and the gate electrode 71. Transistors Tr1 and Tr3 and transistors Tr2 and Tr4 are arranged around the threshold modulation transistor Tr51a.

[0124] 28 is a cross-sectional view showing a modified example of the threshold modulation transistor Tr51 according to the fifth embodiment of the present disclosure. Fig. 28 shows the cross-sectional structure taken along line DD in Fig. 27 , and also shows the threshold modulation transistor Tr51a and the transistor Tr1. As shown in Fig. 28 , the source diffusion region 74 is disposed in the center of the photoelectric conversion region 72, and the drain diffusion region 73 is disposed so as to surround the source diffusion region 74.

[0125] In this way, the EVS pixel 70 according to the fifth embodiment of the present disclosure can multiply the charge of the photoelectric conversion element 24 a by the threshold modulation transistor Tr51. Furthermore, the charge multiplication factor can be adjusted by the bias voltage Vg applied to the gate of the threshold modulation transistor Tr51.

[0126] Sixth Embodiment A threshold modulation transistor according to a sixth embodiment of the present disclosure has a lower substrate height around the threshold modulation transistor according to the fifth embodiment and a smaller capacitance of the photoelectric conversion region. Figure 29 is a cross-sectional view showing a threshold modulation transistor Tr41 according to the sixth embodiment of the present disclosure. The threshold modulation transistor Tr41 of Figure 29 differs from the threshold modulation transistor Tr51 of Figure 26 etc. in that it has an insulating region 57a ​​buried to a position deeper than the gate diffusion region and in that the height of the substrate 50 outside the insulating region 57a ​​is lower than the upper surfaces of the source diffusion region 67 and the drain diffusion region 65.

[0127] The threshold modulation transistor Tr41 has a diffusion region (fourth diffusion region) 62 located on the side opposite the light incident surface of the substrate 50, a gate electrode 63 located opposite the end face of the diffusion region 62 facing the substrate 50, a drain diffusion region (fifth diffusion region) 65 located in part of the diffusion region 62 and connected to a drain electrode 64, and a source diffusion region (sixth diffusion region) 67 located in part of the diffusion region 62 and connected to a source electrode 66. The diffusion region 62 functions as the photoelectric conversion element 24, and therefore will be referred to as the photoelectric conversion region 62 hereinafter. The threshold modulation transistor Tr41 also constitutes a charge multiplication section 25a. The lower surface of the substrate 50 in FIG. 29 is the light incident surface for incident light LGT. The threshold modulation transistor Tr41 and the photoelectric conversion element 24 can also be referred to as a phototransistor 61 composed of a MOS transistor.

[0128] The charge / discharge speed of the threshold modulation transistor Tr41 is determined by the capacitance of the photoelectric conversion region 62. Therefore, it is desirable to make the capacitance of the photoelectric conversion region 62 as small as possible. An insulating region 57a ​​is arranged around the photoelectric conversion region 62, which makes it possible to reduce the capacitance of the photoelectric conversion region 62, similar to the phototransistor 21b in FIG. 18. The expansion of a depletion layer generated near the photoelectric conversion region 62 is suppressed by the insulating region 57a, thereby preventing charge from leaking from the threshold modulation transistor Tr41.

[0129] 29 shows an example in which a portion of the upper surface of the substrate 50 facing the photoelectric conversion region 62 across the insulating region 57a ​​is removed in order to reduce the capacitance of the photoelectric conversion region 62. That is, the end face of the substrate 50 opposite the light incident surface, which is disposed opposite the photoelectric conversion region 62, is positioned closer to the light incident surface of the substrate 50 than the end face of the photoelectric conversion region 62 facing the gate electrode 63. Furthermore, the end face of the substrate 50 opposite the light incident surface is positioned at the same height as the end face of the photoelectric conversion region 62 facing the light incident surface, or is positioned closer to the light incident surface than the end face of the photoelectric conversion region 62 facing the light incident surface. This allows the capacitance between the substrate 50 and the photoelectric conversion region 62 to be reduced.

[0130] In this way, the threshold modulation transistor Tr41 according to the sixth embodiment of the present disclosure can prevent punch-through by virtue of the insulating region 57a ​​buried to a position deeper than the photoelectric conversion region 62, and can also reduce the capacitance of the photoelectric conversion region 62, thereby improving the charge / discharge speed of the threshold modulation transistor Tr41. The threshold modulation transistor Tr41 may also be applied to the first to fourth embodiments of the present disclosure.

[0131] Seventh Embodiment The EVS pixel of the present disclosure may have a configuration having the function of a gradation pixel. Fig. 30A is a circuit diagram showing a first configuration example of a pixel 80 according to a seventh embodiment of the present disclosure. The pixel 80 of Fig. 30A includes a photoelectric conversion element 24a, a threshold modulation transistor Tr51, and a current-voltage conversion circuit 22, similar to the EVS pixel 70 of Fig. 24A. The pixel 80 also differs from the EVS pixel 70 of Fig. 24A in that it includes a gradation pixel circuit 81.

[0132] The gradation pixel circuit 81 has a transfer transistor (second transistor) Tr31a, a reset transistor Tr32, an amplification transistor Tr33, and a selection transistor Tr34, similar to the gradation pixel 30 of FIG.

[0133] The transfer transistor Tr31a is configured, for example, by an NMOS transistor. The transfer transistor Tr31a may have any conductivity type. The source of the transfer transistor Tr31a is connected to either the anode or cathode of the photoelectric conversion element 24a (the cathode in the example of FIG. 30A). The drain of the transfer transistor Tr31a is connected to the floating diffusion FD. The transfer transistor Tr31a transfers the charge of the photoelectric conversion element 24a to the floating diffusion FD when a transfer signal TRG is input to its gate.

[0134] The connection relationship between the reset transistor Tr32, the amplification transistor Tr33, and the selection transistor Tr34 is the same as that in FIG.

[0135] The threshold modulation transistor Tr51 is configured, for example, by a PMOS transistor. Charge is transferred to the back gate of the threshold modulation transistor Tr51 in Fig. 30A from either the anode or cathode of the photoelectric conversion element 24a (the cathode in the example of Fig. 30A). The connection relationship between the source, drain, and gate of the threshold modulation transistor Tr51 is the same as in Fig. 24A. The other of the anode or cathode of the photoelectric conversion element 24a (the anode in the example of Fig. 30A) is connected to the drain of the threshold modulation transistor Tr51 and a predetermined reference voltage node such as ground voltage.

[0136] Fig. 30B is a circuit diagram showing a second configuration example of a pixel 80 according to the seventh embodiment of the present disclosure. A pixel 80a shown in Fig. 30B has a 2Tr configuration similar to that shown in Fig. 7A. Fig. 30C is a circuit diagram showing a third configuration example of a pixel 80 according to the seventh embodiment of the present disclosure. A pixel 80b shown in Fig. 30C has a gate-grounded configuration similar to that shown in Fig. 7B. Fig. 30D is a circuit diagram showing a fourth configuration example of a pixel 80 according to the seventh embodiment of the present disclosure. A pixel 80c shown in Fig. 30D has a diode configuration similar to that shown in Fig. 7C.

[0137] Fig. 31 is a plan view showing a pixel 80 according to a seventh embodiment of the present disclosure. Fig. 31 illustrates four pixels 80 sharing one floating diffusion FD. That is, the four pixels 80 can share one gradation pixel circuit 81 (not shown in Fig. 31). Note that each of the multiple pixels 80 may have one floating diffusion FD.

[0138] Each of the pixels 80 includes a threshold modulation transistor Tr51, a transfer transistor Tr31a, a photoelectric conversion region 72, and a pixel isolation region 72a. The threshold modulation transistor Tr51 includes a gate electrode 71, a drain diffusion region 73, and a source diffusion region 74.

[0139] 31 has an electron pocket (charge accumulation portion) 82. The electron pocket 82 is a region with a deeper potential than other regions of the photoelectric conversion region 72.

[0140] The gate electrode 71 in FIG. 31 is disposed so as to overlap the electron pocket 82 in plan view.

[0141] 31 is disposed between the electron pocket 82 and the floating diffusion FD. The transfer transistor Tr31a has a contact Ct that extends toward the light incident surface (i.e., approximately perpendicular to the plane of FIG. 31).

[0142] The pixel isolation region 72a is disposed, for example, so as to surround the photoelectric conversion region 72. The drain diffusion region 73 is disposed so as to at least partially overlap with the pixel isolation region 72a in a plan view. The pixel isolation region 72a suppresses dark current in the pixel 80.

[0143] A boundary region 75a is disposed between two adjacent pixels 80. The boundary region 75a prevents color mixing between the pixels 80. The boundary region 75a includes, for example, an insulating film.

[0144] FIG. 32 is a cross-sectional view showing a pixel 80 according to a seventh embodiment of the present disclosure. FIG. 32 shows a cross-sectional structure taken along line E-E in FIG. 31. FIG. 32 also illustrates a pinning film 83 disposed on the cathode side of the photoelectric conversion element 24a and an inversion layer (channel region) 84 formed by the threshold modulation transistor Tr51. Note that, instead of the pinning film 83, an ITO (indium tin oxide) electrode, for example, may be disposed. The pinning film 83 or the ITO electrode is set to a predetermined potential (for example, GND potential).

[0145] A predetermined bias voltage Vg is applied to the gate electrode 71 of the threshold modulation transistor Tr51, which forms an inversion layer 84 between the drain diffusion region 73 and the source diffusion region 74, causing a current to flow between the drain diffusion region 73 and the source diffusion region 74.

[0146] The source diffusion region 74 is connected to the current-voltage conversion circuit 22. The drain diffusion region 73 is connected to a contact (not shown in FIG. 32) that is set to a predetermined potential Vd (e.g., ground level). This allows the potential Vs of the source diffusion region 74 to be changed by threshold modulation of the threshold modulation transistor Tr51. A predetermined constant current may be supplied to the drain diffusion region 73.

[0147] As described above, the drain diffusion region (seventh diffusion region) 73 adjusts the potential on the drain side of the threshold modulation transistor Tr51. Furthermore, the drain diffusion region 73 in Fig. 32 also serves as part of the pixel isolation region 72a. This allows the potential of the pixel isolation region 72a to be stabilized by the contact.

[0148] The drain diffusion region 73 and the source diffusion region 74 contain, for example, a high concentration of p-type impurities. The floating diffusion FD contains, for example, a high concentration of n-type impurities. The photoelectric conversion region 72 contains, for example, n-type impurities. The pixel isolation region 72a contains, for example, p-type impurities.

[0149] 32 has an insulating region (STI) 75b that separates the source diffusion region 74 and the floating diffusion FD. That is, the pixel 80 in FIG. 32 is an STI isolated pixel.

[0150] The electron pocket 82 is disposed inside the substrate 50 so as to face the gate electrode 71 of the threshold modulation transistor Tr51. More specifically, the electron pocket 82 is disposed on the shallower side of the photoelectric conversion region 72 (i.e., the upper side in FIG. 32 ) and at a position deeper than the position where the inversion layer 84 is formed.

[0151] 32 is a region into which impurities of the same conductivity type (e.g., n-type) as the photoelectric conversion region 72 are implanted. The electron pocket 82 has a higher impurity concentration than other regions of the photoelectric conversion region 72 and a lower impurity concentration than the drain diffusion region 73 and the source diffusion region 74, for example.

[0152] Fig. 33A is a waveform diagram showing the potential gradient in the depth direction of the pixel 80 in Fig. 32. Specifically, Fig. 33A illustrates the potential gradient in the range from one main surface on which the gate electrode 71 is disposed to the pinning film 83 (hereinafter also referred to as the range depth).

[0153] 32 illustrates the range Depth. The range Depth includes the photoelectric conversion region 72, the pixel isolation region 72a, the electron pocket 82, and the back gate region Tr_bk of the threshold modulation transistor Tr51. The back gate region Tr_bk includes a part of the photoelectric conversion region 72.

[0154] The horizontal axis of Fig. 33A indicates the depth of the pixel 80, and the vertical axis indicates the potential (V). Note that the upper side of Fig. 33A indicates a low potential, and the lower side indicates a high potential.

[0155] During the exposure period of the pixel 80, charges are generated by photoelectric conversion in the photoelectric conversion region 72. As shown in FIG. 33A , the electron pocket 82 has a deeper potential than the photoelectric conversion region 72 and the back gate region Tr_bk, so the charges (specifically, electrons e) generated in the photoelectric conversion region 72 are transferred to the electron pocket 82 and accumulated in the electron pocket 82.

[0156] 33B is a waveform diagram showing the potential gradient after charges are accumulated in the electron pocket 82. As shown in Fig. 33B, when electrons e are accumulated in the electron pocket 82, the potential of the back gate region Tr_bk decreases due to the substrate bias effect.

[0157] This causes the inversion layer 84 to expand, changing the voltage between the drain diffusion region 73 and the source diffusion region 74 or the amount of current flowing through the source diffusion region 74. The event detection circuit 40 connected to the pixel 80 can detect an event based on the change in voltage or the change in the amount of current.

[0158] That is, the photodetector 10 according to the seventh embodiment of the present disclosure can sequentially detect events during the exposure period based on the charges accumulated in the electron pocket 82 .

[0159] The transfer transistor Tr31a controls switching to determine whether or not to transfer the charge stored in the electron pocket 82 to the floating diffusion FD.

[0160] A transfer signal TRG is input to the transfer transistor Tr31a, for example, at the end of the exposure period. This turns on the transfer transistor Tr31a, allowing the charge stored in the electron pocket 82 to be transferred to the floating diffusion FD. The gradation pixel circuit 81 can output a pixel signal Vimg based on the charge transferred to the floating diffusion FD.

[0161] 32 shows an example of a pixel 80 in which an electron pocket 82 that accumulates electrons is arranged in the photoelectric conversion region 72. Note that a region that accumulates holes may be arranged instead of the electron pocket 82. That is, the threshold modulation transistor Tr51 may modulate the threshold value by holes transferred to the back gate, and the transfer transistor Tr31a may transfer holes to the floating diffusion FD.

[0162] The planar layout configuration of the pixel 80 can be changed as desired. FIG. 34A is a plan view showing a first modified example of the pixel 80 according to the seventh embodiment of the present disclosure. The pixel 80d in FIG. 34A has a rectangular shape. The threshold modulation transistor Tr51 in FIG. 34A is arranged along one side of the pixel 80d. More specifically, the threshold modulation transistor Tr51 is arranged such that the drain diffusion region 73 and the source diffusion region 74 are spaced apart in the vertical direction of FIG. 34A (hereinafter also referred to as vertical arrangement). The threshold modulation transistor Tr51 may also be arranged such that the drain diffusion region 73 and the source diffusion region 74 are spaced apart in the horizontal direction of FIG. 34A (hereinafter also referred to as horizontal arrangement).

[0163] 34B is a plan view showing a second modified example of a pixel 80 according to the seventh embodiment of the present disclosure. In a pixel 80e in FIG. 34A, the threshold modulation transistor Tr51 is arranged such that the drain diffusion region 73 and the source diffusion region 74 are spaced apart in a diagonal direction of the pixel 80e (hereinafter also referred to as a diagonal arrangement). More specifically, the drain diffusion region 73 and the source diffusion region 74 are arranged so as to be spaced apart in a diagonal direction different from the diagonal direction in which the transfer transistor Tr31a is arranged.

[0164] 34A and 34B respectively show distances d1 and d2 from the transfer transistor Tr31a to the diffusion layer of the threshold modulation transistor Tr51. More specifically, the distances d1 and d2 are the distances from the transfer transistor Tr31a to either the drain diffusion region 73 or the source diffusion region 74, whichever is closer to the transfer transistor Tr31a.

[0165] Increasing the distance from the transfer transistor Tr31a to the diffusion layer of the threshold modulation transistor Tr51 can improve the electric field characteristics of the pixel 80. Furthermore, the distance d2 in Fig. 34B is greater than the distance d1 in Fig. 34A. In other words, by arranging the threshold modulation transistor Tr51 diagonally, the electric field characteristics of the pixel 80 can be improved more than by arranging it vertically or horizontally.

[0166] Thus, the pixel 80 according to the seventh embodiment of the present disclosure has an electron pocket 82 that accumulates charge based on incident light, a threshold modulation transistor Tr51 whose threshold is modulated by the electron pocket 82, and a transfer transistor Tr31a that reads out the charge in the electron pocket 82.

[0167] During the exposure period, the pixel 80 and the event detection circuit 40 can detect an event based on the output voltage or output current of the threshold modulation transistor Tr51. Furthermore, the pixel 80 and the gradation pixel circuit 81 can output a pixel signal Vimg based on the charge accumulated in the electron pocket 82 at the end of the exposure period.

[0168] That is, the pixel 80 according to the seventh embodiment of the present disclosure can be used for both detecting an event and outputting the pixel signal Vimg.

[0169] The photodetector 10 according to the seventh embodiment of the present disclosure does not need to replace some of the pixels 80 with gradation pixels in order to output gradation information. Therefore, there is no risk of pixel defects occurring in the pixel array unit 11, and the image quality of the image data of the photodetector 10 can be improved.

[0170] Furthermore, as shown in FIG. 34B, the drain diffusion region 73 and the source diffusion region 74 in the threshold modulation transistor Tr51 are arranged farther away from the transfer transistor Tr31a, thereby improving the electric field characteristics of the pixel 80.

[0171] 30A and other related art, the threshold modulation transistor Tr51 has a different conductivity type from the transfer transistor Tr31a. The threshold modulation transistor Tr51 may have the same conductivity type as the transfer transistor Tr31a. For example, both the threshold modulation transistor Tr51 and the transfer transistor Tr31a may be configured as NMOS transistors.

[0172] Figure 35 is a cross-sectional view showing a pixel 80f according to an eighth embodiment of the present disclosure. The pixel 80f in Figure 35 includes a threshold modulation transistor Tr51b, which is an NMOS transistor. The threshold modulation transistor Tr51b includes a drain diffusion region 73a containing a high concentration of n-type impurities and a source diffusion region 74a containing a high concentration of n-type impurities. Furthermore, the back gate region Tr_bka of the threshold modulation transistor Tr51b includes a diffusion region containing p-type impurities (e.g., a part of the pixel isolation region 72a).

[0173] In the pixel 80f of FIG. 35, the pixel isolation region 72a is exposed on one main surface on which the gate electrode 71 is disposed, thereby making it possible to suppress the generation of dark current.

[0174] 35, the source diffusion region 74a and the floating diffusion FD contain impurities of the same conductivity type, and therefore the pixel 80f can be configured as a flat-type pixel that omits an insulating region separating the source diffusion region 74a and the floating diffusion FD (i.e., the insulating region 75b in FIG. 32).

[0175] Since the formation of the insulating region 75b can be omitted for the pixel 80f, the formation process can be simplified compared to the pixel 80 of FIG.

[0176] 32 adjusts the potential on the drain side of the threshold modulation transistor Tr51 and stabilizes the potential of the pixel isolation region 72 a. The potential of the pixel isolation region 72 a may be stabilized by a contact region different from the drain diffusion region 73.

[0177] Fig. 36A is a plan view showing a first configuration example of a pixel 80g according to a ninth embodiment of the present disclosure, Fig. 36B is a plan view showing a second configuration example of a pixel 80g according to the ninth embodiment of the present disclosure, and Fig. 37 is a cross-sectional view showing a pixel 80g according to the ninth embodiment of the present disclosure.

[0178] FIG. 36A shows an example in which the threshold modulation transistor Tr51 is arranged vertically, and FIG. 36B shows an example in which the threshold modulation transistor Tr51 is arranged diagonally.

[0179] 36A and 36B includes a contact region (eighth diffusion region) 73b. The contact region 73b is connected to the pixel isolation region 72a and stabilizes the potential of the pixel isolation region 72a. In this specification, the contact region 73b is also referred to as a well contact.

[0180] The contact region 73b is shared among multiple pixels 80g. Note that each of the multiple pixels 80g may have the contact region 73b. The position of the contact region 73b is not limited to the examples in Figures 36A and 36B and may be arbitrary.

[0181] The threshold modulation transistor Tr51 has a drain diffusion region (seventh diffusion region) 73c that adjusts the potential on the drain side. The drain diffusion region 73c in Figures 36A and 36B is arranged so as not to overlap the pixel isolation region 72a in plan view.

[0182] 37, the drain diffusion region 73c and the contact region 73b contain, for example, a high concentration of p-type impurities and are connected to a contact (not shown in FIG. 37) set to a predetermined potential Vd by, for example, a wiring layer or the like.

[0183] 37, the drain diffusion region 73 in FIG. 32 is divided into a drain diffusion region 73c that adjusts the potential on the drain side of the threshold modulation transistor Tr51, and a contact region 73b that stabilizes the potential of the pixel isolation region 72a. This allows the potential design of the contact region 73b and the drain diffusion region 73c to be performed independently.

[0184] Tenth Embodiment The threshold modulation transistor Tr51 may have the function of the transfer transistor Tr31. Fig. 38A is a plan view showing a first configuration example of a pixel 80h according to a tenth embodiment of the present disclosure. The threshold modulation transistor Tr51c in Fig. 38A has a gate electrode 71a, a drain diffusion region 73, and a source diffusion region 74.

[0185] The gate electrode 71a is arranged so that at least a portion thereof overlaps with the electron pocket 82 in a plan view. The gate electrode 71a is also arranged between the electron pocket 82 and the floating diffusion FD. The gate electrode 71a functions as a transfer transistor Tr31a, as will be described later.

[0186] The drain diffusion region 73 and the source diffusion region 74 in FIG. 38A are arranged to be spaced apart in the vertical direction of the pixel 80h (i.e., arranged vertically).

[0187] 38B is a plan view showing a second configuration example of a pixel 80 h according to the tenth embodiment of the present disclosure. The drain diffusion region 73 and the source diffusion region 74 in Fig. 38B are arranged so as to be spaced apart in the diagonal direction of the pixel 80 h (i.e., arranged diagonally).

[0188] The threshold modulation transistor Tr51c in Figures 38A and 38B is configured, for example, by a PMOS transistor. The transfer transistor Tr31a in Figures 38A and 38B is configured, for example, by an NMOS transistor. As described above, by making the conductivity type of the threshold modulation transistor Tr51c different from that of the transfer transistor Tr31a, it is possible to simultaneously perform the operation of transferring charge between the drain diffusion region 73 and the source diffusion region 74 and the operation of preventing charge transfer between the electron pocket 82 and the floating diffusion FD. Note that the threshold modulation transistor Tr51c and the transfer transistor Tr31a may be configured, for example, by an NMOS transistor and a PMOS transistor, respectively.

[0189] 39 is a waveform diagram showing the change over time in the bias voltage Vg applied to the gate electrode 71a in FIGS. 38A and 38B. During the exposure period T1, a voltage (first voltage) V1 is applied to the gate electrode 71a. At voltage V1, a current flows between the drain diffusion region 73 and the source diffusion region 74. In addition, the threshold of the threshold modulation transistor Tr51 is modulated by the charge accumulated in the electron pocket 82.

[0190] At the voltage V1, no charge is transferred from the electron pocket 82 to the floating diffusion FD. That is, the voltage V1 corresponds to the off level of the transfer transistor Tr31a.

[0191] During a readout period T2 after the exposure period ends, a voltage (second voltage) V2 is applied to the gate electrode 71a, causing the gate electrode 71a (transfer transistor Tr31a) to transfer charges from the electron pocket 82 to the floating diffusion FD. In other words, the voltage V2 corresponds to the on level of the transfer transistor Tr31a.

[0192] As described above, the gate electrode 71a according to the tenth embodiment of the present disclosure functions as a transfer transistor Tr31a. In the pixel 80h according to the tenth embodiment of the present disclosure, the bias voltage Vpg applied to the gate electrode 71a is switched between the exposure period and the readout period. This allows the gate electrode 71a to change the voltage (or the amount of current) between the drain diffusion region 73 and the source diffusion region 74 according to the charge accumulated in the electron pocket 82 during the exposure period, and to transfer the charge in the electron pocket 82 to the floating diffusion FD during the readout period.

[0193] As shown in FIGS. 38A and 38B, by integrating the transfer transistor Tr31a with the threshold modulation transistor Tr51c, the pixel size of the pixel 80h can be reduced.

[0194] 40 is a plan view showing a pixel 80i according to an eleventh embodiment of the present disclosure. The pixel 80i in Fig. 40 has a threshold modulation transistor Tr51c integrated with a transfer transistor Tr31a, similar to the pixel 80h in Fig. 38A and Fig. 38B .

[0195] The pixel 80i in Fig. 40 has an electrode 85. A portion of the electrode 85 (hereinafter also referred to as electrode 85a) is embedded in a boundary region (element isolation region) 75a. The boundary region 75a in Fig. 40 is, for example, a full trench isolation (FFTI). In this specification, the electrode 85a embedded in the boundary region 75a is also referred to as a capacitive deep trench isolation (CDTI).

[0196] Fig. 41A is a first cross-sectional view showing a pixel 80i according to an eleventh embodiment of the present disclosure. Fig. 41A illustrates a cross section taken along line F-F in Fig. 40. Fig. 41A illustrates cross sections of the gate electrode 71a, drain diffusion region 73, source diffusion region 74, boundary region 75a, and electrode 85a in Fig. 40. Fig. 41A also illustrates the photoelectric conversion region 72 and pinning film 83.

[0197] Fig. 41B is a second cross-sectional view showing a pixel 80i according to an eleventh embodiment of the present disclosure. Fig. 41B illustrates a cross section taken along line G-G in Fig. 40. Fig. 41B illustrates cross sections of the floating diffusion FD, gate electrode 71a, photoelectric conversion region 72, and electrode 85 in Fig. 40. Fig. 41B also illustrates a boundary region 75a, an electrode 85a, and a pinning film 83.

[0198] 41A and 41B, the electronic pocket 82 is omitted from the illustration.

[0199] 41A and 41B , when a predetermined voltage Vc is applied to the electrode 85, a pinning region 84a is formed in the sidewall portion that contacts the boundary region 75a of the photoelectric conversion region 72. The pinning region 84a is, for example, a region containing p-type impurities.

[0200] The electrodes 85 and 85a stabilize the potential of the pinning region 84a. In the pixel 80i, the electrodes 85, 85a and the pinning region 84a can suppress dark current. Therefore, the pixel 80i does not require the pixel isolation region 72a.

[0201] Furthermore, the pinning film 83 forms an inversion layer 84b in the bottom portion of the photoelectric conversion region 72. The pinning region 84a and the inversion layer 84b can be used as a channel that electrically connects the source diffusion region 74 and the drain diffusion region 73. Therefore, the electrodes 85 and 85a function as the gate electrode of the threshold modulation transistor Tr51c.

[0202] Furthermore, by using the pinning region 84a and the inversion layer 84b as a channel, the sensitivity of threshold modulation of the threshold modulation transistor Tr51c can be improved. Furthermore, by using the electrodes 85 and 85a as gate electrodes, the source diffusion region 74 and the drain diffusion region 73 can be separated. Therefore, the pixel 80i can be configured as a flat-type pixel.

[0203] 42A is a plan view showing a first configuration example of a pixel 80j according to a twelfth embodiment of the present disclosure. The pixel 80j shown in FIG. 42A differs from the pixel 80 of FIG. 31 in that it has a threshold modulation transistor Tr51d with a ring-shaped structure. The threshold modulation transistor Tr51d has a source diffusion region (ninth diffusion region) 74 in the center. The gate electrode 71 is arranged in a ring shape to surround the source diffusion region 74. The drain diffusion region 73 is arranged in a ring shape to surround the source diffusion region 74 and the gate electrode 71.

[0204] Fig. 42B is a plan view showing a second configuration example of a pixel 80j according to the twelfth embodiment of the present disclosure. The drain diffusion region 73 shown in Fig. 42B has a region near the transfer transistor Tr31a removed, compared to the drain diffusion region 73 in Fig. 42A. This increases the distance from the transfer transistor Tr31a to the drain diffusion region 73, allowing the pixel 80j in Fig. 42B to have improved electric field characteristics compared to the pixel 80j in Fig. 42A.

[0205] 43 is a cross-sectional view showing a pixel 80j according to a twelfth embodiment of the present disclosure. In the pixel 80j in FIG. 43, the drain diffusion region 73 and the source diffusion region 74 can be separated by arranging the gate electrode 71 so as to surround the source diffusion region 74. Therefore, the pixel 80j can be configured as a flat type pixel.

[0206] Figure 44 is a plan view showing a modified example of a pixel 80j according to the twelfth embodiment of the present disclosure. Figure 45 is a cross-sectional view showing a modified example of a pixel 80j according to the twelfth embodiment of the present disclosure. The pixel 80j in Figures 44 and 45 differs from the pixel 80j in Figure 43 in that it has a threshold modulation transistor Tr51e integrated with the transfer transistor Tr31a, similar to the threshold modulation transistor Tr51c in Figures 38A and 38B. This allows the pixel size of the pixel 80j to be reduced.

[0207] 46 is a plan view showing a pixel 80k according to a thirteenth embodiment of the present disclosure. FIG. 47 is a cross-sectional view showing a pixel 80k according to the thirteenth embodiment of the present disclosure. In the pixel 80k of FIGS. 46 and 47, the drain diffusion region (tenth diffusion region) 73 can be shared with another adjacent pixel 80k. This allows the pixel size of the pixel 80k to be reduced.

[0208] 46 and 47 has a gate electrode 71 arranged in a ring shape so as to surround a source diffusion region 74. Without being limited to this, the gate electrode 71 may be arranged so as to contact a part of the source diffusion region 74, as shown in FIG.

[0209] Figure 48 is a plan view showing a modified example of a pixel 80k according to the thirteenth embodiment of the present disclosure. Figure 49 is a cross-sectional view showing a modified example of a pixel 80k according to the thirteenth embodiment of the present disclosure. The pixel 80k in Figures 48 and 49 has a threshold modulation transistor Tr51e integrated with the transfer transistor Tr31a, similar to the threshold modulation transistor Tr51c in Figures 38A and 38B. This allows the pixel size of the pixel 80j to be further reduced.

[0210] 50A is a circuit diagram showing the configuration of an EVS pixel 90 according to a fourteenth embodiment of the present disclosure. The EVS pixel 90 of FIG. 50A differs from the EVS pixel 20 of FIG. 4 in that an avalanche photodiode is used as the photoelectric conversion element 24b (and the charge multiplication section 25c). Either the anode or the cathode of the photoelectric conversion element 24b (the cathode in the example of FIG. 50A) is connected to the output node n1. The other of the anode or the cathode of the photoelectric conversion element 24b (the anode in the example of FIG. 50A) is connected to a predetermined reference voltage node such as a ground voltage.

[0211] Fig. 50B is a circuit diagram showing a second configuration example of the EVS pixel 90 according to the fourteenth embodiment of the present disclosure. The EVS pixel 90a shown in Fig. 50B is a pixel with a 2Tr configuration similar to that shown in Fig. 7A. Fig. 50C is a circuit diagram showing a third configuration example of the EVS pixel 90 according to the fourteenth embodiment of the present disclosure. The EVS pixel 90b shown in Fig. 50C has a gate-grounded configuration similar to that shown in Fig. 7B. Fig. 50D is a circuit diagram showing a fourth configuration example of the EVS pixel 90 according to the fourteenth embodiment of the present disclosure. The EVS pixel 90c shown in Fig. 50D has a diode configuration similar to that shown in Fig. 7C.

[0212] 51 is a cross-sectional view showing the configuration of an avalanche photodiode APD according to the fourteenth embodiment of the present disclosure. The avalanche photodiode APD has an absorption region 91, an amplification region 92, diffusion regions 93 and 94, and an isolation region 95. The absorption region 91 has, for example, a wide n-type diffusion region (NWL; n-well).

[0213] The absorption region 91 absorbs incident light LGT and generates charges (e.g., electrons e). The amplification region 92 has a diffusion region NWL. In the amplification region 92, the electrons e generated by the absorption region 91 are accelerated and collide with semiconductor atoms, generating new electrons e. In the amplification region 92, the generated electrons e further collide with other semiconductor atoms, generating new electrons e one after another, a phenomenon known as an electron avalanche. This allows the amplification region 92 to multiply the charges generated by the absorption region 91. The absorption region 91 constitutes the photoelectric conversion element 24b. The amplification region 92 constitutes the charge multiplication section 25c.

[0214] The diffusion region 93 corresponds to the cathode of the avalanche photodiode APD and outputs the charge multiplied in the amplification region 92. The diffusion region 93 is disposed opposite the amplification region 92 on the surface of the substrate 50 opposite the light incident surface. The diffusion region 94 corresponds to the anode of the avalanche photodiode APD and is disposed on the surface of the substrate 50 opposite the light incident surface. The diffusion region 94 is separated from the absorption region 91 and the amplification region 92 by an isolation region 95 having a diffusion region PWL. The diffusion regions 93 and 94 are p-type impurity diffusion regions and have a higher impurity concentration than the isolation region 95.

[0215] As described above, the EVS pixel 90 according to the fourteenth embodiment of the present disclosure uses an avalanche photodiode as a photoelectric conversion element, thereby generating a large current even from weak light. As a result, similar to the first embodiment, the operation speed of the photodetector 10 can be increased even under low illumination, and the S / N ratio can be improved because the device is less susceptible to the influence of dark current even under low illumination. The avalanche photodiode according to the fourteenth embodiment of the present disclosure may be applied to the phototransistors according to the first to fourth embodiments or the VMISs according to the fifth to thirteenth embodiments.

[0216] (Application Examples) The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, a robot, construction machinery, or agricultural machinery (tractor).

[0217] 52 is a block diagram showing a schematic configuration example of a vehicle control system 7000, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied. The vehicle control system 7000 includes a plurality of electronic control units connected via a communication network 7010. In the example shown in FIG. 52, the vehicle control system 7000 includes a drive system control unit 7100, a body system control unit 7200, a battery control unit 7300, an outside-vehicle information detection unit 7400, an inside-vehicle information detection unit 7500, and an integrated control unit 7600. The communication network 7010 connecting these multiple control units may be an in-vehicle communication network conforming to any standard, such as a Controller Area Network (CAN), a Local Interconnect Network (LIN), a Local Area Network (LAN), or FlexRay (registered trademark).

[0218] Each control unit includes a microcomputer that performs arithmetic processing according to various programs, a memory unit that stores the programs executed by the microcomputer or parameters used in various calculations, and a drive circuit that drives various controlled devices. Each control unit includes a network I / F for communicating with other control units via a communication network 7010, and a communication I / F for communicating with devices or sensors inside and outside the vehicle via wired or wireless communication. Figure 52 illustrates the functional configuration of the integrated control unit 7600, including a microcomputer 7610, a general-purpose communication I / F 7620, a dedicated communication I / F 7630, a positioning unit 7640, a beacon receiving unit 7650, an in-vehicle device I / F 7660, an audio / video output unit 7670, an in-vehicle network I / F 7680, and a memory unit 7690. Other control units also include a microcomputer, a communication I / F, a memory unit, and the like.

[0219] The drivetrain control unit 7100 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 7100 functions as a control device for a drive force generating device for generating drive force for the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating braking force for the vehicle. The drivetrain control unit 7100 may also function as a control device for an ABS (Antilock Brake System) or an ESC (Electronic Stability Control), etc.

[0220] A vehicle state detection unit 7110 is connected to the drivetrain control unit 7100. The vehicle state detection unit 7110 includes at least one of a gyro sensor that detects the angular velocity of the axial rotational motion of the vehicle body, an acceleration sensor that detects the acceleration of the vehicle, or a sensor that detects the amount of operation of the accelerator pedal, the amount of operation of the brake pedal, the steering angle of the steering wheel, the engine rotation speed, the rotation speed of the wheels, etc. The drivetrain control unit 7100 performs arithmetic processing using signals input from the vehicle state detection unit 7110, and controls the internal combustion engine, the drive motor, the electric power steering device, the brake device, etc.

[0221] The body system control unit 7200 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 7200 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 7200. The body system control unit 7200 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0222] The battery control unit 7300 controls the secondary battery 7310, which is the power supply source for the drive motor, in accordance with various programs. For example, information such as battery temperature, battery output voltage, or remaining battery capacity is input to the battery control unit 7300 from a battery device equipped with the secondary battery 7310. The battery control unit 7300 performs arithmetic processing using these signals, and controls the temperature regulation of the secondary battery 7310 or a cooling device or the like equipped in the battery device.

[0223] The outside vehicle information detection unit 7400 detects information outside the vehicle equipped with the vehicle control system 7000. For example, at least one of an imaging unit 7410 and an outside vehicle information detection unit 7420 is connected to the outside vehicle information detection unit 7400. The imaging unit 7410 includes at least one of a time-of-flight (ToF) camera, a stereo camera, a monocular camera, an infrared camera, and other cameras. The outside vehicle information detection unit 7420 includes at least one of an environmental sensor for detecting the current weather or climate, or a surrounding information detection sensor for detecting other vehicles, obstacles, pedestrians, etc. around the vehicle equipped with the vehicle control system 7000.

[0224] The environmental sensor may be, for example, at least one of a raindrop sensor that detects rain, a fog sensor that detects fog, a sunshine sensor that detects the degree of sunshine, and a snow sensor that detects snowfall. The surrounding information detection sensor may be at least one of an ultrasonic sensor, a radar device, and a LIDAR (Light Detection and Ranging, Laser Imaging Detection and Ranging) device. The imaging unit 7410 and the outside vehicle information detection unit 7420 may each be provided as an independent sensor or device, or may be provided as a device in which multiple sensors or devices are integrated.

[0225] Here, Figure 53 shows an example of the installation positions of the imaging unit 7410 and the vehicle exterior information detection unit 7420. The imaging units 7910, 7912, 7914, 7916, and 7918 are provided, for example, at least one of the front nose, side mirrors, rear bumper, back door, and upper part of the windshield inside the vehicle cabin of the vehicle 7900. The imaging unit 7910 provided on the front nose and the imaging unit 7918 provided on the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 7900. The imaging units 7912 and 7914 provided on the side mirrors mainly acquire images of the sides of the vehicle 7900. The imaging unit 7916 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 7900. The imaging unit 7918 provided on the upper part of the windshield inside the vehicle cabin is mainly used to detect leading vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0226] 53 shows an example of the imaging ranges of the imaging units 7910, 7912, 7914, and 7916. Imaging range a indicates the imaging range of the imaging unit 7910 provided on the front nose, imaging ranges b and c indicate the imaging ranges of the imaging units 7912 and 7914 provided on the side mirrors, respectively, and imaging range d indicates the imaging range of the imaging unit 7916 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 7910, 7912, 7914, and 7916, a bird's-eye view image of the vehicle 7900 viewed from above can be obtained.

[0227] The outside vehicle information detection units 7920, 7922, 7924, 7926, 7928, and 7930 provided on the front, rear, sides, corners, and above the windshield inside the vehicle cabin of the vehicle 7900 may be, for example, ultrasonic sensors or radar devices. The outside vehicle information detection units 7920, 7926, and 7930 provided on the front nose, rear bumper, back door, and above the windshield inside the vehicle cabin of the vehicle 7900 may be, for example, LIDAR devices. These outside vehicle information detection units 7920 to 7930 are mainly used to detect preceding vehicles, pedestrians, obstacles, etc.

[0228] Returning to FIG. 52 , the explanation continues. The outside-vehicle information detection unit 7400 causes the imaging unit 7410 to capture an image outside the vehicle and receives the captured image data. The outside-vehicle information detection unit 7400 also receives detection information from the connected outside-vehicle information detection unit 7420. If the outside-vehicle information detection unit 7420 is an ultrasonic sensor, a radar device, or a LIDAR device, the outside-vehicle information detection unit 7400 emits ultrasonic waves or electromagnetic waves and receives information on the received reflected waves. Based on the received information, the outside-vehicle information detection unit 7400 may perform object detection processing or distance detection processing for people, vehicles, obstacles, signs, or text on the road surface. Based on the received information, the outside-vehicle information detection unit 7400 may also perform environmental recognition processing for recognizing rainfall, fog, road conditions, etc. Based on the received information, the outside-vehicle information detection unit 7400 may also calculate the distance to an object outside the vehicle.

[0229] The outside vehicle information detection unit 7400 may also perform image recognition processing or distance detection processing to recognize people, vehicles, obstacles, signs, or characters on the road surface based on the received image data. The outside vehicle information detection unit 7400 may perform processing such as distortion correction or alignment on the received image data, and may also generate an overhead image or a panoramic image by combining image data captured by different image capturing units 7410. The outside vehicle information detection unit 7400 may also perform viewpoint conversion processing using image data captured by different image capturing units 7410.

[0230] The interior information detection unit 7500 detects information inside the vehicle. A driver state detection unit 7510 that detects the driver's state is connected to the interior information detection unit 7500, for example. The driver state detection unit 7510 may include a camera that captures an image of the driver, a biosensor that detects the driver's biometric information, or a microphone that collects sound from within the vehicle cabin. The biosensor is provided, for example, on the seat or steering wheel, and detects the biometric information of a passenger sitting in the seat or the driver gripping the steering wheel. The interior information detection unit 7500 may calculate the driver's level of fatigue or concentration based on the detection information input from the driver state detection unit 7510, or may determine whether the driver is dozing off. The interior information detection unit 7500 may perform processing such as noise canceling on the collected audio signal.

[0231] The integrated control unit 7600 controls the overall operation of the vehicle control system 7000 according to various programs. An input unit 7800 is connected to the integrated control unit 7600. The input unit 7800 may be implemented by a device that can be operated by a passenger, such as a touch panel, a button, a microphone, a switch, or a lever. Data obtained by voice recognition of a voice input through a microphone may be input to the integrated control unit 7600. The input unit 7800 may be, for example, a remote control device using infrared or other radio waves, or an externally connected device such as a mobile phone or a personal digital assistant (PDA) that can operate the vehicle control system 7000. The input unit 7800 may be, for example, a camera, in which case the passenger can input information using gestures. Alternatively, data obtained by detecting the movement of a wearable device worn by the passenger may be input. Furthermore, the input unit 7800 may include, for example, an input control circuit that generates an input signal based on information input by the passenger using the input unit 7800 and outputs the input signal to the integrated control unit 7600. Passengers and the like operate this input unit 7800 to input various data to the vehicle control system 7000 and to instruct processing operations.

[0232] The storage unit 7690 may include a ROM (Read Only Memory) that stores various programs executed by the microcomputer, and a RAM (Random Access Memory) that stores various parameters, calculation results, sensor values, etc. The storage unit 7690 may also be realized by a magnetic storage device such as an HDD (Hard Disc Drive), a semiconductor storage device, an optical storage device, a magneto-optical storage device, or the like.

[0233] The general-purpose communication I / F 7620 is a general-purpose communication I / F that mediates communication with various devices present in the external environment 7750. The general-purpose communication I / F 7620 may implement a cellular communication protocol such as GSM (Global System of Mobile communications), WiMAX (registered trademark), LTE (Long Term Evolution), or LTE-Advanced (LTE-A), or other wireless communication protocols such as a wireless LAN (also referred to as Wi-Fi (registered trademark)) or Bluetooth (registered trademark). The general-purpose communication I / F 7620 may connect to a device (e.g., an application server or a control server) present on an external network (e.g., the Internet, a cloud network, or an operator-specific network) via, for example, a base station or an access point. In addition, the general-purpose communication I / F 7620 may connect to a terminal located near the vehicle (e.g., a terminal of a driver, pedestrian, or store, or an MTC (Machine Type Communication) terminal) using, for example, P2P (Peer To Peer) technology.

[0234] The dedicated communication I / F 7630 is a communication I / F that supports a communication protocol designed for use in vehicles. The dedicated communication I / F 7630 may implement a standard protocol such as WAVE (Wireless Access in Vehicle Environment), which is a combination of a lower layer IEEE 802.11p and an upper layer IEEE 1609, DSRC (Dedicated Short Range Communications), or a cellular communication protocol. The dedicated communication I / F 7630 typically performs V2X communication, which is a concept including one or more of vehicle-to-vehicle communication, vehicle-to-infrastructure communication, vehicle-to-home communication, and vehicle-to-pedestrian communication.

[0235] The positioning unit 7640 performs positioning by receiving, for example, GNSS signals from GNSS (Global Navigation Satellite System) satellites (for example, GPS signals from GPS (Global Positioning System) satellites), and generates position information including the latitude, longitude, and altitude of the vehicle. Note that the positioning unit 7640 may identify the current position by exchanging signals with a wireless access point, or may obtain position information from a terminal such as a mobile phone, PHS, or smartphone that has a positioning function.

[0236] The beacon receiving unit 7650 receives, for example, radio waves or electromagnetic waves transmitted from radio stations or the like installed on the road, and acquires information such as the current location, congestion, road closures, required travel time, etc. The function of the beacon receiving unit 7650 may be included in the dedicated communication I / F 7630 described above.

[0237] The in-vehicle device I / F 7660 is a communication interface that mediates connections between the microcomputer 7610 and various in-vehicle devices 7760 present in the vehicle. The in-vehicle device I / F 7660 may establish wireless connections using wireless communication protocols such as wireless LAN, Bluetooth (registered trademark), NFC (Near Field Communication), or WUSB (Wireless USB). Furthermore, the in-vehicle device I / F 7660 may establish a wired connection such as USB (Universal Serial Bus), HDMI (High-Definition Multimedia Interface), or MHL (Mobile High-Definition Link) via a connection terminal (and a cable, if necessary) not shown. The in-vehicle device 7760 may include, for example, at least one of a mobile device or a wearable device owned by a passenger, or an information device carried into or attached to the vehicle. The in-vehicle device 7760 may also include a navigation device that searches for a route to an arbitrary destination. The in-vehicle device I / F 7660 exchanges control signals or data signals with these in-vehicle devices 7760.

[0238] The in-vehicle network I / F 7680 is an interface that mediates communication between the microcomputer 7610 and the communication network 7010. The in-vehicle network I / F 7680 transmits and receives signals in accordance with a predetermined protocol supported by the communication network 7010.

[0239] The microcomputer 7610 of the integrated control unit 7600 controls the vehicle control system 7000 in accordance with various programs based on information acquired via at least one of the general-purpose communication I / F 7620, the dedicated communication I / F 7630, the positioning unit 7640, the beacon receiving unit 7650, the in-vehicle device I / F 7660, and the in-vehicle network I / F 7680. For example, the microcomputer 7610 may calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the acquired information inside and outside the vehicle, and output control commands to the drivetrain control unit 7100. For example, the microcomputer 7610 may perform cooperative control aimed at realizing functions of an Advanced Driver Assistance System (ADAS), including vehicle collision avoidance or impact mitigation, following driving based on the following distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc. In addition, the microcomputer 7610 may perform cooperative control for the purpose of autonomous driving, in which the vehicle travels autonomously without relying on driver operation, by controlling a driving force generating device, a steering mechanism, a braking device, etc. based on information acquired about the vehicle's surroundings.

[0240] The microcomputer 7610 may generate three-dimensional distance information between the vehicle and objects such as surrounding structures and people, and create local map information including information about the vicinity of the vehicle's current location, based on information acquired via at least one of the general-purpose communication I / F 7620, the dedicated communication I / F 7630, the positioning unit 7640, the beacon receiving unit 7650, the in-vehicle device I / F 7660, and the in-vehicle network I / F 7680. Furthermore, the microcomputer 7610 may predict dangers, such as a vehicle collision, the approach of a pedestrian, or entry into a closed road, based on the acquired information, and generate a warning signal. The warning signal may be, for example, a signal for generating a warning sound or turning on a warning lamp.

[0241] The audio / image output unit 7670 transmits at least one audio and / or image output signal to an output device capable of visually or audibly notifying vehicle occupants or the outside of the vehicle of information. In the example of FIG. 52 , an audio speaker 7710, a display unit 7720, and an instrument panel 7730 are illustrated as output devices. The display unit 7720 may include, for example, at least one of an on-board display and a head-up display. The display unit 7720 may have an AR (Augmented Reality) display function. The output device may also be other devices, such as headphones, a wearable device such as an eyeglass-type display worn by the occupant, a projector, or a lamp. When the output device is a display device, the display device visually displays results obtained by various processes performed by the microcomputer 7610 or information received from other control units in various formats, such as text, images, tables, and graphs. When the output device is an audio output device, the audio output device converts audio signals, such as reproduced audio data or acoustic data, into analog signals and audibly outputs the analog signals.

[0242] In the example shown in FIG. 52 , at least two control units connected via the communication network 7010 may be integrated into a single control unit. Alternatively, each control unit may be composed of multiple control units. Furthermore, the vehicle control system 7000 may include another control unit not shown. In the above description, some or all of the functions performed by one of the control units may be performed by another control unit. In other words, as long as information is transmitted and received via the communication network 7010, predetermined arithmetic processing may be performed by one of the control units. Similarly, a sensor or device connected to one of the control units may be connected to another control unit, and multiple control units may transmit and receive detection information to and from each other via the communication network 7010.

[0243] In the vehicle control system 7000 described above, the photodetector 10 according to the present embodiment described with reference to Fig. 2 can be applied to the image capturing unit 7410 of the application example shown in Fig. 52. This allows the image capturing unit 7410 to output images at a higher speed.

[0244] The present technology may have the following configurations: (1) A photodetector that detects an event based on a change in the amount of incident light, the photodetector comprising: a photoelectric conversion element that generates a charge according to the amount of incident light; a charge multiplier that multiplies the charge; a current-voltage conversion circuit that converts a current according to the multiplied charge into a voltage; and an event detection circuit that detects the event based on the converted voltage. (2) The photodetector according to (1), in which the photoelectric conversion element and the charge multiplier have a phototransistor. (3) The photodetector according to (1), in which the photoelectric conversion element and the charge multiplier have an avalanche photodiode. (4) The photodetector according to (1), in which the photoelectric conversion element has a photodiode that transfers the charge to a substrate, and the charge multiplier has a first transistor whose threshold is modulated according to the charge transferred to the substrate. (5) The photodetector according to (2), in which the phototransistor is a bipolar transistor or a MOS (Metal Oxide Semiconductor) transistor. (6) The photodetector according to (2) or (5), wherein the phototransistor has: a first diffusion region disposed on the side opposite to the light incident surface of the substrate and generating a charge based on incident light; a second diffusion region disposed on at least a portion of the surface of the first diffusion region and connected to an emitter electrode; and a third diffusion region disposed on a portion of the substrate so as to surround the first diffusion region and connected to a collector electrode. (7) The photodetector according to (6), comprising: a first wiring connected to an output portion of the photoelectric conversion element; a second wiring connected to an output portion of the current-voltage conversion circuit; and a parasitic capacitance disposed between the first wiring and the second wiring, wherein the first diffusion region has a capacitance smaller than the parasitic capacitance. (8) The photodetector according to (6) or (7), wherein an end face of the third diffusion region opposite to the substrate is disposed closer to the substrate than an end face of the second diffusion region opposite to the substrate. (9) The photodetector device according to any one of (6) to (8), wherein a height of a sidewall of the third diffusion region facing the second diffusion region is lower than a height of a sidewall of the second diffusion region facing the third diffusion region.(10) The photodetector according to any one of (6) to (9), wherein an area of ​​a sidewall of the first diffusion region facing the second diffusion region is smaller than an area of ​​a sidewall of the second diffusion region facing the first diffusion region. (11) The photodetector according to (10), comprising an insulating region disposed between the second diffusion region and the third diffusion region. (12) The photodetector according to (11), wherein the insulating region is disposed so as to surround the first diffusion region. (13) The photodetector according to (11) or (12), wherein the insulating region is disposed from a surface of the second diffusion region to a bottom surface of the first diffusion region or to a position deeper than the bottom surface. (14) The photodetector according to any one of (11) to (13), wherein the insulating region includes a low-k material. (15) The photodetector according to any one of (6) to (14), comprising the collector electrode extending from the substrate toward the light incident surface. (16) The photodetector according to any one of (6) to (15), further comprising a single collector electrode extending from the third diffusion region in a direction away from the substrate. (17) The photodetector according to (4), wherein the first transistor has: a fourth diffusion region disposed on the side opposite to the light incident surface of the substrate; a gate electrode disposed facing an end face of the fourth diffusion region opposite to the substrate; a fifth diffusion region disposed in part of the fourth diffusion region and connected to a drain electrode; and a sixth diffusion region disposed in part of the fourth diffusion region and connected to a source electrode, wherein the end face of the substrate opposite to the light incident surface disposed facing the fourth diffusion region is disposed closer to the light incident surface of the substrate than the end face of the fourth diffusion region facing the gate electrode. (18) The photodetector according to (17), wherein the end face of the substrate opposite to the light incident surface disposed facing the fourth diffusion region is disposed at the same height as the end face of the fourth diffusion region on the light incident surface side of the substrate, or is disposed on the light incident surface side of the substrate.(19) The photodetector according to any one of (1) to (18), comprising: a plurality of first pixels each detecting the event based on a change in the amount of incident light; and a plurality of second pixels each outputting a pixel signal including gradation information based on a charge corresponding to the amount of incident light, wherein each of the plurality of first pixels has the photoelectric conversion element, the charge multiplier, the current-voltage conversion circuit, and the event detection circuit. (20) The photodetector according to (4), (17), or (18), comprising: a charge accumulation unit disposed in the substrate deeper than a channel region of the first transistor, the charge accumulation unit accumulating charge generated by photoelectric conversion of the photoelectric conversion element; and a pixel circuit outputting a pixel signal including gradation information based on the charge accumulated in the charge accumulation unit, wherein the threshold of the first transistor is modulated in accordance with the charge accumulated in the charge accumulation unit. (21) The photodetector according to (20), comprising: a floating diffusion region that holds charge accumulated in the charge accumulation portion; and a second transistor that switches whether to transfer the charge accumulated in the charge accumulation portion to the floating diffusion region. (22) The photodetector according to (20), wherein the first transistor switches whether to modulate the threshold value or to transfer the charge accumulated in the charge accumulation portion to the pixel circuit, using a gate voltage. (23) The photodetector according to any one of (20) to (22), comprising: a pixel isolation region disposed around the photoelectric conversion element; a seventh diffusion region that serves as at least a part of the source region or drain region of the first transistor and also serves as at least a part of the pixel isolation region; and a contact connected to the seventh diffusion region and set to a predetermined potential. (24) A photodetection device according to any one of (20) to (22), comprising: a pixel isolation region arranged around the photoelectric conversion element; a seventh diffusion region that also serves as at least a portion of the source region or drain region of the first transistor; an eighth diffusion region that is provided separately from the seventh diffusion region and also serves as at least a portion of the pixel isolation region; and a contact that is connected to the seventh diffusion region and the eighth diffusion region and is set to a predetermined potential.(25) The photodetector according to any one of (20) to (22), comprising: a pixel having the photoelectric conversion element; an element isolation region arranged to surround the pixel; and an electrode arranged inside the element isolation region. (26) The photodetector according to any one of (20) to (25), wherein the first transistor comprises: a ninth diffusion region serving as at least a part of a source region or a drain region of the first transistor; and an annular gate electrode arranged to surround the ninth diffusion region. (27) The photodetector according to any one of (20) to (26), comprising: a plurality of pixels each having the photoelectric conversion element, wherein the first transistor has a tenth diffusion region shared among the plurality of pixels and serving as at least a part of a source region or a drain region of the first transistor. (28) An electronic device comprising: a photodetector that detects an event based on a change in the amount of incident light; and an image processing unit that processes image data output from the photodetector, wherein the photodetector comprises: a photoelectric conversion element that generates an electric charge according to the amount of incident light; a charge multiplier that multiplies the electric charge; a current-voltage conversion circuit that converts a current according to the multiplied electric charge into a voltage; and an event detection circuit that detects the event based on the converted voltage.

[0245] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents.

[0246] 1 Electronic device, 2 Image processing unit, 3 Recording unit, 4 Control unit, 5 Imaging lens, 10 Photodetector, 11 Pixel array unit, 12 Vertical drive circuit, 13 Event readout circuit, 14 Gradation signal readout circuit, 20, 20a, 20b, 20c, 20d, 70, 70a, 70b, 70c, 70d, 90, 90a, 90b, 90c, 100 EVS pixel, 21, 21a, 21b, 21c, 21d, 21e, 21f, 21g, 21h, 61 Phototransistor, 22 Current-voltage conversion circuit, 23 Current source, 24, 24a, 24b, 32 Photoelectric conversion element, 25, 25a, 25b, 25c Charge multiplication unit, 30, 30a, 30b, 30c Gradation pixel, 31 Pixel circuit, 40 Event detection circuit, 41 Differentiation circuit, 42 Comparator, 50 Substrate, 51, 51a Base diffusion region, 52 Emitter diffusion region, 53, 54 Collector diffusion region, 55 Emitter electrode, 56 Collector electrode, 57, 57a, 57b, 75, 75b Insulating region, 58 Underlying substrate, 62, 72 Photoelectric conversion region, 65, 73, 73a, 73c Drain diffusion region, 67, 74, 74a Source diffusion region, 63, 71, 71a Gate electrode, 64 Drain electrode, 66 Source electrode, 72a Pixel isolation region, 73b Contact region, 75a Boundary region, 80, 80a, 80b, 80c, 80d, 80e, 80f, 80g, 80h, 80i, 80j, 80k Pixel, 81 Gradation pixel circuit, 82 Electron pocket, 83 Pinning film, 84, 84b inversion layer, 84a pinning region, 85, 85a electrodes, 91 absorption region, 92 amplification region, 93, 94 diffusion region, 95 separation region

Claims

1. A photodetection device that detects an event based on a change in the amount of incident light, comprising: a photoelectric conversion element that generates an electric charge according to the amount of incident light; a charge multiplier that multiplies the electric charge; a current-voltage conversion circuit that converts a current according to the multiplied charge into a voltage; and an event detection circuit that detects the event based on the converted voltage.

2. The light detection device according to claim 1, wherein the photoelectric conversion element and the charge multiplication section each include a phototransistor.

3. The photodetector according to claim 1, wherein the photoelectric conversion element and the charge multiplier section each include an avalanche photodiode.

4. The photodetector according to claim 1, wherein the photoelectric conversion element has a photodiode that transfers the charge to a substrate, and the charge multiplication section has a first transistor whose threshold is modulated in accordance with the charge transferred to the substrate.

5. The photodetection device according to claim 2, wherein the phototransistor is a bipolar transistor or a MOS (Metal Oxide Semiconductor) transistor.

6. The photodetection device according to claim 2, wherein the phototransistor comprises: a first diffusion region that is disposed on the side opposite to the light incident surface of the substrate and generates an electric charge based on incident light; a second diffusion region that is disposed on at least a portion of the surface of the first diffusion region and connected to an emitter electrode; and a third diffusion region that is disposed on a portion of the substrate surrounding the first diffusion region and connected to a collector electrode.

7. The photodetection device according to claim 6, comprising: a first wiring connected to an output portion of the photoelectric conversion element; a second wiring connected to an output portion of the current-voltage conversion circuit; and a parasitic capacitance disposed between the first wiring and the second wiring, wherein the first diffusion region has a capacitance smaller than the parasitic capacitance.

8. The photodetector according to claim 6, wherein an end face of the third diffusion region opposite to the substrate is located closer to the substrate than an end face of the second diffusion region opposite to the substrate.

9. The photodetection device according to claim 6, wherein a height of a sidewall of said third diffusion region facing said second diffusion region is lower than a height of a sidewall of said second diffusion region facing said third diffusion region.

10. The photodetection device according to claim 6, wherein an area of ​​a sidewall of said first diffusion region facing said second diffusion region is smaller than an area of ​​a sidewall of said second diffusion region facing said first diffusion region.

11. The photodetection device of claim 10, further comprising an insulating region disposed between said second diffusion region and said third diffusion region.

12. The photodetection device according to claim 11, wherein the insulating region is disposed to surround the first diffusion region.

13. The photodetection device according to claim 11, wherein the insulating region is disposed from a surface of the second diffusion region to a bottom surface of the first diffusion region or to a position deeper than the bottom surface.

14. The photodetection device of claim 11, wherein the insulating region comprises a low-k material.

15. The photodetector according to claim 6, further comprising the collector electrode extending from the substrate toward the light incident surface side.

16. The photodetector device of claim 6, further comprising a single collector electrode extending from said third diffusion region in a direction away from said substrate.

17. The photodetector of claim 4, wherein the first transistor has: a fourth diffusion region arranged on the side opposite the light incident surface of the substrate; a gate electrode arranged facing an end face of the fourth diffusion region opposite the substrate; a fifth diffusion region arranged in part of the fourth diffusion region and connected to a drain electrode; and a sixth diffusion region arranged in part of the fourth diffusion region and connected to a source electrode, and wherein the end face opposite the light incident surface of the substrate arranged to face the fourth diffusion region is arranged closer to the light incident surface of the substrate than the end face of the fourth diffusion region on the gate electrode side.

18. The optical detection device described in claim 17, wherein an end face of the substrate opposite the light incident surface and arranged to face the fourth diffusion region is at the same height as the end face of the fourth diffusion region on the light incident surface side of the substrate, or is arranged on the light incident surface side of the substrate.

19. The photodetection device according to claim 1, comprising: a plurality of first pixels each detecting an event based on a change in the amount of incident light; and a plurality of second pixels each outputting a pixel signal including gradation information based on an electric charge corresponding to the amount of incident light, wherein each of the plurality of first pixels has the photoelectric conversion element, the electric charge multiplication section, the current-voltage conversion circuit, and the event detection circuit.

20. The photodetection device according to claim 4, comprising: a charge accumulation section disposed in the substrate at a position deeper than the channel region of the first transistor, which accumulates charge generated by photoelectric conversion of the photoelectric conversion element; and a pixel circuit which outputs a pixel signal including gradation information based on the charge accumulated in the charge accumulation section, wherein the threshold of the first transistor is modulated in accordance with the charge accumulated in the charge accumulation section.

21. The photodetector according to claim 20, further comprising: a floating diffusion region that holds the charge accumulated in the charge accumulation section; and a second transistor that switches between transferring the charge accumulated in the charge accumulation section to the floating diffusion region.

22. The photodetection device according to claim 20, wherein the first transistor switches between modulating the threshold value and transferring the charge accumulated in the charge accumulation portion to the pixel circuit, depending on a gate voltage.

23. The photodetection device according to claim 20, comprising: a pixel isolation region arranged around the photoelectric conversion element; a seventh diffusion region that also serves as at least a part of the source region or drain region of the first transistor and also serves as at least a part of the pixel isolation region; and a contact connected to the seventh diffusion region and set to a predetermined potential.

24. The photodetection device of claim 20, comprising: a pixel isolation region arranged around the photoelectric conversion element; a seventh diffusion region that also serves as at least a part of the source region or drain region of the first transistor; an eighth diffusion region provided separately from the seventh diffusion region and that also serves as at least a part of the pixel isolation region; and a contact connected to the seventh diffusion region and the eighth diffusion region and set to a predetermined potential.

25. The photodetection device according to claim 20, comprising: a pixel having the photoelectric conversion element; an element isolation region arranged to surround the pixel; and an electrode arranged inside the element isolation region.

26. The photodetection device according to claim 20, wherein the first transistor comprises: a ninth diffusion region that also serves as at least a part of a source region or a drain region of the first transistor; and a ring-shaped gate electrode arranged to surround the ninth diffusion region.

27. The photodetection device according to claim 20, comprising a plurality of pixels each having the photoelectric conversion element, and the first transistor having a tenth diffusion region shared among the plurality of pixels and serving as at least a portion of a source region or a drain region of the first transistor.

28. An electronic device comprising: a photodetection device that detects an event based on a change in the amount of incident light; and an image processing unit that processes image data output from the photodetection device, wherein the photodetection device comprises: a photoelectric conversion element that generates an electric charge according to the amount of incident light; a charge multiplier that multiplies the electric charge; a current-voltage conversion circuit that converts a current according to the multiplied charge into a voltage; and an event detection circuit that detects the event based on the converted voltage.

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